; --------------------------------------------------------------------------------
; @Title: Agilex5 On-Chip Peripherals
; @Props: Released
; @Author: KRZ
; @Changelog: 2025-02-04 KRZ
; @Manufacturer: INTEL - Intel Corporation
; @Doc: Generated (TRACE32, build: 176489.), based on: soc_hps.svd (Ver. 1.0)
; @Core: Cortex-A76, Cortex-A55
; @Chip: AGILEX5
; @Copyright: (C) 1989-2025 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: peragilex5.per 19100 2025-02-24 14:34:34Z kwisniewski $

AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
sif (CORENAME()=="CORTEXA55")
tree "Core Registers (Cortex-A76/A55)"
AUTOINDENT.PUSH
AUTOINDENT.ON center tree
tree.open "AArch64"
tree "ID Registers"
rgroup.quad spr:0x30000++0x00
line.quad 0x00 "MIDR_EL1,Main ID Register"
hexmask.quad.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.quad 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "ARCH,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme"
newline
hexmask.quad.word 0x00 4.--15. 1. "PART,Primary Part Number"
bitfld.quad 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,Processor Feature Register 0"
bitfld.quad 0x00 60.--63. "CSV3,Data loaded under speculation can be used to form an address/generate condition codes" "Reserved,Disclosed/No,?..."
bitfld.quad 0x00 56.--59. "CSV2,Branch targets trained in one context can affect speculative execution" "Reserved,Disclosed/No,?..."
newline
bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Not present,Version 1,?..."
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
newline
bitfld.quad 0x00 20.--23. "ASIMD,Advanced SIMD" "Reserved,Implemented,?..."
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 12.--15. "EL3_ELH,EL3 exception level handling" "Reserved,AArch64,?..."
bitfld.quad 0x00 8.--11. "EL2_ELH,EL2 exception level handling" "Reserved,AArch64,?..."
newline
bitfld.quad 0x00 4.--7. "EL1_ELH,EL1 exception level handling" "Reserved,AArch64,?..."
bitfld.quad 0x00 0.--3. "EL0_ELH,EL0 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30040++0x00
line.quad 0x00 "ID_AA64PFR0_EL1,Processor Feature Register 0"
bitfld.quad 0x00 60.--63. "CSV3,Data loaded under speculation can be used to form an address/generate condition codes" "Disclosed/No,?..."
bitfld.quad 0x00 56.--59. "CSV2,Branch targets trained in one context can affect speculative execution" "Disclosed/No,?..."
newline
bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..."
bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..."
newline
bitfld.quad 0x00 20.--23. "ASIMD,Advanced SIMD" "Reserved,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
bitfld.quad 0x00 16.--19. "FP,Floating-point" "Reserved,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.quad 0x00 12.--15. "EL3_ELH,EL3 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 8.--11. "EL2_ELH,EL2 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
newline
bitfld.quad 0x00 4.--7. "EL1_ELH,EL1 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
bitfld.quad 0x00 0.--3. "EL0_ELH,EL0 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..."
endif
rgroup.quad spr:0x30050++0x00
line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register"
bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware" "Reserved,2,?..."
bitfld.quad 0x00 20.--23. "WRPS,Number of watchpoints" "Reserved,Reserved,Reserved,4,?..."
bitfld.quad 0x00 12.--15. "BRPS,Number of breakpoints" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.quad 0x00 8.--11. "PMEV,Performance monitor extension version" "Reserved,Reserved,Reserved,Reserved,Version 3/16 bit evtCount,?..."
bitfld.quad 0x00 4.--7. "TEV,Trace extension version" "Not implemented,?..."
bitfld.quad 0x00 0.--3. "DAV,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,v8-A,?..."
rgroup.quad spr:0x30060++0x00
line.quad 0x00 "ID_AA64ISAR0_EL1,Instruction Set Attribute Register 0"
bitfld.quad 0x00 44.--47. "DP,Implemented UDOT and SDOT instructions" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 28.--31. "RDM,Rounding Double Multiply Add/Subtract instructions Support" "Reserved,Implemented,?..."
bitfld.quad 0x00 20.--23. "ATOMIC,Atomic instructions in AArch64" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 16.--19. "CRC32,Indicates whether CRC32 instructions are implemented" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions in AArch64" "Not implemented,Implemented,?..."
bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions in AArch64" "Not implemented,Implemented,?..."
bitfld.quad 0x00 4.--7. "AES,AES instruction in AArch64" "Not implemented,Reserved,AESE/AESD/AESMC/AESIMC/PMULL/PMULL2,?..."
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "TGRAN4,4KB granule supported" "Supported,?..."
bitfld.quad 0x00 24.--27. "TGRAN64,64KB granule supported" "Supported,?..."
bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "BIGENDEL0,Mixed-endian support at EL0" "Not supported,?..."
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30070++0x00
line.quad 0x00 "ID_AA64MMFR0_EL1,Memory Model Feature Register 0"
bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Reserved,Supported,?..."
bitfld.quad 0x00 16.--19. "BIGENDEL0,Mixed-endian support at EL0" "Not supported,?..."
bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..."
bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..."
endif
rgroup.quad spr:0x30041++0x00
line.quad 0x00 "ID_AA64PFR1_EL1,Processor Feature Register 1"
bitfld.quad 0x00 4.--7. "SSBS,Speculative store bypassing safe" "Reserved,Implemented without MSR/MRS,?..."
rgroup.quad spr:0x30051++0x00
line.quad 0x00 "ID_AA64DFR1_EL1,Debug Feature Register 1"
rgroup.quad spr:0x30061++0x00
line.quad 0x00 "ID_AA64ISAR1_EL1,Instruction Set Attribute Register 1"
bitfld.quad 0x00 20.--23. "LRCPC,Indicates whether load-acquire (LDA) instructions are implemented for an Release Consistent processor consistent RCPC model" "Reserved,Implemented,?..."
bitfld.quad 0x00 0.--3. "DPB,DC CVAP support in AArch64" "Reserved,Implemented,?..."
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x30071++0x00
line.quad 0x00 "ID_AA64MMFR1_EL1,Memory Model Feature Register 1"
bitfld.quad 0x00 28.--31. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "SPECSEI,Describes whether the PE can generate SError interrupt exceptions" "Not occurred,?..."
newline
bitfld.quad 0x00 20.--23. "PAN,Privileged access never support" "Reserved,Reserved,Extended,?..."
bitfld.quad 0x00 16.--19. "LO,Limited order regions support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "HD,Hierarchical permission disabled support" "Reserved,Reserved,Extended,?..."
newline
bitfld.quad 0x00 8.--11. "VH,Virtualization host extensions support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "VMID,Number of VMID bits" "Reserved,Reserved,16 bits,?..."
bitfld.quad 0x00 0.--3. "HAFDBS,Hardware updates of the access and dirty" "Reserved,Reserved,Access/Dirty supported,?..."
rgroup.quad spr:0x30072++0x00
line.quad 0x00 "ID_AA64MMFR2_EL1,Memory Model Feature Register 2"
bitfld.quad 0x00 16.--19. "VARANGE,Larger virtual address support" "Supported,?..."
newline
bitfld.quad 0x00 12.--15. "IESB,Indicates whether an implicit Error Synchronization Barrier has been inserted" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "LSM,Indicates whether LDM and STM are supported" "Not supported,?..."
bitfld.quad 0x00 4.--7. "UAO,User Access Override support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "CNP,Common not Private support" "Reserved,Supported,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30071++0x00
line.quad 0x00 "ID_AA64MMFR1_EL1,Memory Model Feature Register 1"
bitfld.quad 0x00 28.--31. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 20.--23. "PAN,Privileged access never support" "Reserved,Reserved,Extended,?..."
bitfld.quad 0x00 16.--19. "LO,Limited order regions support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "HD,Hierarchical permission disabled support" "Reserved,Reserved,Extended,?..."
newline
bitfld.quad 0x00 8.--11. "VH,Virtualization host extensions support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "VMID,Number of VMID bits" "Reserved,Reserved,16 bits,?..."
bitfld.quad 0x00 0.--3. "HAFDBS,Hardware updates of the access and dirty" "Reserved,Reserved,Access/Dirty supported,?..."
rgroup.quad spr:0x30072++0x00
line.quad 0x00 "ID_AA64MMFR2_EL1,Memory Model Feature Register 2"
bitfld.quad 0x00 12.--15. "IESB,Indicates whether an implicit Error Synchronization Barrier has been inserted" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "LSM,Indicates whether LDM and STM are supported" "Not supported,?..."
bitfld.quad 0x00 4.--7. "UAO,User Access Override support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "CNP,Common not Private support" "Reserved,Supported,?..."
endif
rgroup.quad spr:0x30054++0x00
line.quad 0x00 "ID_AA64AFR0_EL1,Auxiliary Feature Register 0"
rgroup.quad spr:0x30055++0x00
line.quad 0x00 "ID_AA64AFR1_EL1,Auxiliary Feature Register 1"
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x30010++0x00
line.quad 0x00 "ID_PFR0_EL1,AArch32 Processor Feature Register 0"
bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..."
bitfld.quad 0x00 16.--19. "CSV2,Branch targets trained in one context can affect speculative execution" "Not disclosed,Disclosed/No,?..."
newline
bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Trivial,?..."
bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,After Thumb-2,?..."
newline
bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30010++0x00
line.quad 0x00 "ID_PFR0_EL1,AArch32 Processor Feature Register 0"
bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..."
bitfld.quad 0x00 16.--19. "CSV2,Branch targets trained in one context cannot affect speculative execution" "Not disclosed,?..."
newline
bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Trivial,?..."
bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,After Thumb-2,?..."
newline
bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
endif
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x30011++0x00
line.quad 0x00 "ID_PFR1_EL1,AArch32 Processor Feature Register 1"
bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
bitfld.quad 0x00 24.--27. "VF,Virtualization fractional Support - Supported features from the ARMv7 Virtualization Extensions" "Not supported,?..."
bitfld.quad 0x00 20.--23. "SF,Security fractional Support - Supported features from the ARMv7 Security Extensions" "Not supported,?..."
newline
bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "VE,Virtualization Extensions Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Not supported,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30011++0x00
line.quad 0x00 "ID_PFR1_EL1,AArch32 Processor Feature Register 1"
bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
newline
bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
endif
rgroup.quad spr:0x30034++0x00
line.quad 0x00 "ID_PFR2_EL1,AArch32 Processor Feature Register 2"
bitfld.quad 0x00 4.--7. "SSBS,Speculative store bypassing safe mechanism supported" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "CSV3,Data loaded under speculation can be used to form an address/generate condition codes" "Reserved,Disclosed/No,?..."
rgroup.quad spr:0x30013++0x00
line.quad 0x00 "ID_AFR0_EL1,AArch32 Auxiliary Feature Register 0"
rgroup.quad spr:0x30014++0x00
line.quad 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0"
bitfld.quad 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,HW coherency,?..."
bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,Control/Fault Status,?..."
newline
bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.quad 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.quad 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,HW coherency,?..."
newline
bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7/PXN/L-DESC,?..."
rgroup.quad spr:0x30015++0x00
line.quad 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1"
bitfld.quad 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..."
bitfld.quad 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.quad spr:0x30016++0x00
line.quad 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2"
bitfld.quad 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,DSB/ISB/DMB,?..."
newline
bitfld.quad 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,S2 operations,?..."
bitfld.quad 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.quad 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.quad spr:0x30017++0x00
line.quad 0x00 "ID_MMFR3_EL1,AArch32 Memory Model Feature Register 3"
bitfld.quad 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte or more,?..."
bitfld.quad 0x00 20.--23. "CW,Indicates whether translation table updates require a clean to the point of unification" "Reserved,Not required,?..."
newline
bitfld.quad 0x00 16.--19. "PAN,Privileged Access Never Support" "Reserved,Reserved,Extended,?..."
bitfld.quad 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Shareability/Defined behavior,?..."
bitfld.quad 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Invalidate All/MVA,?..."
newline
bitfld.quad 0x00 4.--7. "CMSW,Cache maintenance by set/way" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "CMMVA,Cache maintenance by MVA" "Reserved,Supported,?..."
rgroup.quad spr:0x30026++0x00
line.quad 0x00 "ID_MMFR4_EL1,AArch32 Memory Model Feature Register 4"
bitfld.quad 0x00 20.--23. "LSM,LSMAOE and NTLSMD bits support" "Not supported,?..."
bitfld.quad 0x00 16.--19. "HD,Hierarchical Permission Disabled Support" "Reserved,Reserved,Extended,?..."
bitfld.quad 0x00 12.--15. "CNP,Common not Private support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 8.--11. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "AC2,Indicates the extension of the HACTLR Register using HACTLR2" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "SPECSEI,Describes whether the PE can generate SError interrupt exceptions" "Not possible,?..."
rgroup.quad SPR:0x30020++0x00
line.quad 0x00 "ID_ISAR0_EL1,Instruction Set Attribute Register 0"
bitfld.quad 0x00 24.--27. "DIVI,Divide instructions support" "Reserved,Reserved,T32/A32,?..."
bitfld.quad 0x00 20.--23. "DEBI,Debug instructions support (BKPT)" "Reserved,Supported,?..."
bitfld.quad 0x00 16.--19. "COPROC,Coprocessor instructions support" "Not supported,?..."
newline
bitfld.quad 0x00 12.--15. "CBI,Combined compare and branch instructions support (CBNZ/CBZ)" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "BI,Bitfield instructions support (BFC,BFI,SBFX and UBFX)" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "BCI,Bit counting instructions support (CLZ)" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 0.--3. "SI,Swap instructions support" "Not supported,?..."
rgroup.quad SPR:0x30021++0x00
line.quad 0x00 "ID_ISAR1_EL1,Instruction Set Attribute Register 1"
bitfld.quad 0x00 28.--31. "JI,Jazelle instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 24.--27. "INTI,Interworking instructions support" "Reserved,Reserved,Reserved,A32-BX like,?..."
bitfld.quad 0x00 20.--23. "IMMI,Immediate instructions support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "ITEI,If then instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "EXTI,Extend instructions support" "Reserved,Reserved,Full supported,?..."
bitfld.quad 0x00 8.--11. "EARI,Exception A instructions support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 4.--7. "EXIN,Exception in A32 instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "ENDI,Endian instructions implemented" "Reserved,Implemented,?..."
rgroup.quad SPR:0x30022++0x00
line.quad 0x00 "ID_ISAR2_EL1,Instruction Set Attribute Register 2"
bitfld.quad 0x00 28.--31. "RI,Reversal instructions support" "Reserved,Reserved,REV/REV16/REVSH/RBIT,?..."
bitfld.quad 0x00 24.--27. "PSRI,A and R profile instructions" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "UMI,Advanced unsigned multiply instructions support" "Reserved,Reserved,UMULL/UMLAL/UMAAL,?..."
newline
bitfld.quad 0x00 16.--19. "SMI,Advanced signed multiply instructions support" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "MI,Multiply instructions support" "Reserved,Reserved,MUL/MLA/MLS,?..."
bitfld.quad 0x00 8.--11. "II,Multi-access interruptible instructions support" "Not supported,?..."
newline
bitfld.quad 0x00 4.--7. "MHI,Memory hint instructions support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLDW,?..."
newline
bitfld.quad 0x00 0.--3. "LSI,Load and store instructions support" "Reserved,Reserved,Supported,?..."
rgroup.quad SPR:0x30023++0x00
line.quad 0x00 "ID_ISAR3_EL1,Instruction Set Attribute Register 3"
bitfld.quad 0x00 28.--31. "TEEEI,Thumb-EE extensions support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "NOPI,True NOP instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 20.--23. "T32C,T32 non flag-setting MOV instructions support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 16.--19. "TBI,Table branch instructions support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "SPI,Synchronization primitive instructions support" "Reserved,Reserved,Supported,?..."
newline
bitfld.quad 0x00 8.--11. "SVCI,SVC instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 4.--7. "SIMDI,Single instruction multiple data (SIMD) instructions support" "Reserved,Reserved,Reserved,Full support,?..."
bitfld.quad 0x00 0.--3. "SI,Saturate instructions support" "Reserved,Supported,?..."
if (CORENAME()=="CORTEXA76")
rgroup.quad SPR:0x30024++0x00
line.quad 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4"
bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory system locking support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "PSR_M_I,M profile instructions to modify the PSRs" "Not supported,?..."
bitfld.quad 0x00 20.--23. "SPRI,Synchronization primitive instructions" "LDREX/STREX/CLREX,?..."
newline
bitfld.quad 0x00 16.--19. "BI,Barrier instructions in A32/T32 support" "Reserved,DMB/DSB/ISB,?..."
bitfld.quad 0x00 12.--15. "SMCI,SMC instructions support" "Not supported,?..."
bitfld.quad 0x00 8.--11. "WBI,Write-back instructions support" "Reserved,Full supported,?..."
newline
bitfld.quad 0x00 4.--7. "WSI,With-shift instructions support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "UI,Unprivileged instructions support" "Reserved,Reserved,Supported,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad SPR:0x30024++0x00
line.quad 0x00 "ID_ISAR4_EL1,Instruction Set Attribute Register 4"
bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory system locking support" "Not supported,?..."
bitfld.quad 0x00 24.--27. "PSR_M_I,M profile instructions to modify the PSRs" "Not supported,?..."
bitfld.quad 0x00 20.--23. "SPRI,Synchronization primitive instructions" "LDREX/STREX/CLREX,?..."
newline
bitfld.quad 0x00 16.--19. "BI,Barrier instructions in A32/T32 support" "Reserved,DMB/DSB/ISB,?..."
bitfld.quad 0x00 12.--15. "SMCI,SMC instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 8.--11. "WBI,Write-back instructions support" "Reserved,Full supported,?..."
newline
bitfld.quad 0x00 4.--7. "WSI,With-shift instructions support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.quad 0x00 0.--3. "UI,Unprivileged instructions support" "Reserved,Reserved,Supported,?..."
endif
rgroup.quad SPR:0x30025++0x00
line.quad 0x00 "ID_ISAR5_EL1,Instruction Set Attribute Register 5"
bitfld.quad 0x00 24.--27. "RDM,VQRDMLAH and VQRDMLSH instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 16.--19. "CRC32,CRC32 instructions support" "Reserved,Supported,?..."
bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions support" "Not supported,Supported,?..."
newline
bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions support" "Not supported,Supported,?..."
bitfld.quad 0x00 4.--7. "AES,AES instructions support" "Not supported,Reserved,Full support,?..."
bitfld.quad 0x00 0.--3. "SEVL,SEVL instructions support" "Reserved,Supported,?..."
rgroup.quad spr:0x30027++0x00
line.quad 0x00 "ID_ISAR6_EL1,ID_ISAR6_EL1"
bitfld.quad 0x00 4.--7. "DP,UDOT and SDOT support" "Reserved,Supported,?..."
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x33001++0x00
line.quad 0x00 "CTR_EL0,Cache Type Register"
bitfld.quad 0x00 28. "IDC,Data cache clean requirements for instruction to data coherence" "Required,Not required"
newline
bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x00 14.--15. "L1IP,Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
newline
bitfld.quad 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x33001++0x00
line.quad 0x00 "CTR_EL0,Cache Type Register"
bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x00 14.--15. "L1IP,Instruction cache policy" "Reserved,Reserved,VIPT,?..."
newline
bitfld.quad 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
rgroup.quad spr:0x30005++0x00
line.quad 0x00 "MPIDR_EL1,Multiprocessor Affinity Register"
hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Affinity level 3. Highest level affinity field"
bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level affinity using a multi-threading" "Reserved,Very interdependent"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
bitfld.quad 0x00 8.--10. "AFF1,Third highest level affinity field/Identification number for each CPU in cluster" "CPUID0,CPUID1,CPUID2,CPUID3,CPUID4,CPUID5,CPUID6,CPUID7"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. The level identifies individual threads within a multi-threaded core"
rgroup.quad spr:0x30006++0x00
line.quad 0x00 "REVIDR_EL1,Revision ID Register"
rgroup.quad spr:0x33007++0x00
line.quad 0x00 "DCZID_EL0,DCZID_EL0"
bitfld.quad 0x00 4. "DZP,Data Zero prohibited" "Permitted,Prohibited"
bitfld.quad 0x00 0.--3. "BLOCK,Log2 of the block size in words" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
rgroup.quad spr:0x31007++0x00
line.quad 0x00 "AIDR_EL1,Auxiliary ID Register EL1"
group.quad spr:0x34000++0x00
line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID Register"
hexmask.quad.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.quad 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 16.--19. "ARCH,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme"
newline
hexmask.quad.word 0x00 4.--15. 1. "PART,Primary Part Number"
bitfld.quad 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (CORENAME()=="CORTEXA76")
group.quad spr:0x34005++0x00
line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID Register"
hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Affinity level 3. highest level affinity field"
bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,Uniprocessor"
bitfld.quad 0x00 24. "MT,Lowest level affinity using a multi-threading" "Largely independent,Very interdependent"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
hexmask.quad.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Third highest level affinity field"
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Lowest level affinity field"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x34005++0x00
line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID Registers"
hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Affinity level 3. Highest level affinity field"
bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,?..."
bitfld.quad 0x00 24. "MT,Lowest level affinity using a multi-threading" "Reserved,Very interdependent"
newline
hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field"
bitfld.quad 0x00 8.--11. "AFF1,Third highest level affinity field/Identification number for each CPU in cluster" "CPUID0,CPUID1,CPUID2,CPUID3,CPUID4,CPUID5,CPUID6,CPUID7,?..."
hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. The level identifies individual threads within a multi-threaded core"
endif
tree.end
tree "System Control and Configuration"
group.quad spr:0x36111++0x00
line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register"
bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled"
if (CORENAME()=="CORTEXA76")
group.quad SPR:0x30100++0x00
line.quad 0x00 "SCTLR_EL1,System Control Register"
bitfld.quad 0x00 44. "DSSBS,Default PSTATE.SSBS value on Exception Entry" "0,1"
bitfld.quad 0x00 26. "UCI,Traps EL0 execution of cache maintenance instructions" "Trapped,Not trapped"
newline
bitfld.quad 0x00 25. "EE,Endianness of data accesses at EL1 and stage 1 translation table walks in the EL1&0 translation regime" "Little,Big"
bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big"
newline
bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Set,Unchanged"
bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization event enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Disabled,Enabled"
bitfld.quad 0x00 18. "NTWE,Traps EL0 execution of WFE instructions" "Trapped,Not trapped"
newline
bitfld.quad 0x00 16. "NTWI,Traps EL0 execution of WFI instructions" "Trapped,Not trapped"
bitfld.quad 0x00 15. "UCT,Traps EL0 accesses to the CTR_EL0 register" "Trapped,Not trapped"
newline
bitfld.quad 0x00 14. "DZE,Traps EL0 execution of DC ZVA instructions" "Trapped,Not trapped"
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 9. "UMA,User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D, A, I, F} masks" "Trapped,Not trapped"
bitfld.quad 0x00 8. "SED,SETEND instruction availability" "No,Yes"
newline
bitfld.quad 0x00 7. "ITD,IT Disable" "No,Yes"
bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier operation enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "SA0,SP Alignment check enable for EL0" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP Alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU enable for EL1&0 stage 1 address translation" "Disabled,Enabled"
group.quad SPR:0x35100++0x00
line.quad 0x00 "SCTLR_EL12,System Control Register"
bitfld.quad 0x00 44. "DSSBS,Default PSTATE.SSBS value on Exception Entry" "0,1"
bitfld.quad 0x00 26. "UCI,Traps EL0 execution of cache maintenance instructions" "Trapped,Not trapped"
newline
bitfld.quad 0x00 25. "EE,Endianness of data accesses at EL1 and stage 1 translation table walks in the EL1&0 translation regime" "Little,Big"
bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big"
newline
bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Set,Unchanged"
bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization event enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Disabled,Enabled"
bitfld.quad 0x00 18. "NTWE,Traps EL0 execution of WFE instructions" "Trapped,Not trapped"
newline
bitfld.quad 0x00 16. "NTWI,Traps EL0 execution of WFI instructions" "Trapped,Not trapped"
bitfld.quad 0x00 15. "UCT,Traps EL0 accesses to the CTR_EL0 register" "Trapped,Not trapped"
newline
bitfld.quad 0x00 14. "DZE,Traps EL0 execution of DC ZVA instructions" "Trapped,Not trapped"
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 9. "UMA,User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D, A, I, F} masks" "Trapped,Not trapped"
bitfld.quad 0x00 8. "SED,SETEND instruction availability" "No,Yes"
newline
bitfld.quad 0x00 7. "ITD,IT Disable" "No,Yes"
bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier operation enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "SA0,SP Alignment check enable for EL0" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP Alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU enable for EL1&0 stage 1 address translation" "Disabled,Enabled"
elif (CORENAME()=="CORTEXA55")
group.quad SPR:0x30100++0x00
line.quad 0x00 "SCTLR_EL1,System Control Register"
bitfld.quad 0x00 26. "UCI,EL0 access in AArch64 for DC CVAU/ DC CIVAC/ DC CVAC and IC IVAU instructions enable" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big"
bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Set,Unchanged"
newline
bitfld.quad 0x00 19. "WXN,Write permission implies XN (execute never)" "Not forced,Forced"
bitfld.quad 0x00 18. "NTWE,WFE instruction executed at EL0" "Executed,Not executed"
newline
bitfld.quad 0x00 16. "NTWI,WFI instruction executed at EL0" "Executed,Not executed"
bitfld.quad 0x00 15. "UCT,EL0 access in AArch64 to the CTR_EL0 enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 14. "DZE,Access to DC ZVA instruction at EL0" "Prohibited,Allowed"
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 9. "UMA,User mask access controls access to interrupt masks from EL0 when EL0 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 8. "SED,SETEND instruction availability" "No,Yes"
newline
bitfld.quad 0x00 5. "CP15BEN,CP15 barrier operation enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,Stack alignment check enable for EL0" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Alignment check" "Low,High"
bitfld.quad 0x00 0. "M,MMU enable" "Disabled,Enabled"
group.quad SPR:0x35100++0x00
line.quad 0x00 "SCTLR_EL12,System Control Register"
bitfld.quad 0x00 26. "UCI,EL0 access in AArch64 for DC CVAU/ DC CIVAC/ DC CVAC and IC IVAU instructions enable" "Disabled,Enabled"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big"
bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Set,Unchanged"
newline
bitfld.quad 0x00 19. "WXN,Write permission implies XN (execute never)" "Not forced,Forced"
bitfld.quad 0x00 18. "NTWE,WFE instruction executed at EL0" "Executed,Not executed"
newline
bitfld.quad 0x00 16. "NTWI,WFI instruction executed at EL0" "Executed,Not executed"
bitfld.quad 0x00 15. "UCT,EL0 access in AArch64 to the CTR_EL0 enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 14. "DZE,Access to DC ZVA instruction at EL0" "Prohibited,Allowed"
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 9. "UMA,User mask access controls access to interrupt masks from EL0 when EL0 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 8. "SED,SETEND instruction availability" "No,Yes"
newline
bitfld.quad 0x00 5. "CP15BEN,CP15 barrier operation enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,Stack alignment check enable for EL0" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Alignment check" "Low,High"
bitfld.quad 0x00 0. "M,MMU enable" "Disabled,Enabled"
endif
if (CORENAME()=="CORTEXA76")
if (((per.q(spr:0x34110))&0x408000000)==0x408000000)
group.quad spr:0x34100++0x00
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 44. "DSSBS,Default PSTATE.SSBS value on Exception Entry" "0,1"
bitfld.quad 0x00 26. "UCI,Traps EL0 execution of cache maintenance instructions" "Trapped,Not trapped"
newline
bitfld.quad 0x00 25. "EE,Endianness of data accesses at EL2 and stage 1 translation table walks in the EL2&0 translation regime" "Little,Big"
bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big"
newline
bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL2 exception level" "Set,Unchanged"
bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization event enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Disabled,Enabled"
bitfld.quad 0x00 18. "NTWE,Traps EL0 execution of WFE instructions" "Trapped,Not trapped"
newline
bitfld.quad 0x00 16. "NTWI,Traps EL0 execution of WFI instructions" "Trapped,Not trapped"
bitfld.quad 0x00 15. "UCT,Traps EL0 accesses to the CTR_EL0 register" "Trapped,Not trapped"
newline
bitfld.quad 0x00 14. "DZE,Traps EL0 execution of DC ZVA instructions" "Trapped,Not trapped"
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 8. "SED,SETEND instruction availability" "No,Yes"
bitfld.quad 0x00 7. "ITD,IT Disable" "No,Yes"
newline
bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier operation enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "SA0,SP Alignment check enable for EL0" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,SP Alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Alignment check enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "M,MMU enable for EL2&0 stage 1 address translation" "Disabled,Enabled"
else
group.quad spr:0x34100++0x00
line.quad 0x00 "SCTLR_EL2,System Control Register (EL2)"
bitfld.quad 0x00 44. "DSSBS,Default PSTATE.SSBS value on Exception Entry" "0,1"
bitfld.quad 0x00 25. "EE,Endianness of data accesses at EL2 and stage 1 translation table walks in the EL2&0 translation regime" "Little,Big"
newline
bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization event enable" "Disabled,Enabled"
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,SP Alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Data/Unified cache enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU enable for EL2&0 stage 1 address translation" "Disabled,Enabled"
endif
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x34100++0x00
line.quad 0x00 "SCTLR_EL2,System Control Register EL2"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced"
newline
bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Alignment Check" "Low,High"
newline
bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled"
endif
if (CORENAME()=="CORTEXA76")
group.quad spr:0x36100++0x00
line.quad 0x00 "SCTLR_EL3,System Control Register (EL3)"
bitfld.quad 0x00 44. "DSSBS,Default PSTATE.SSBS value on Exception Entry" "0,1"
bitfld.quad 0x00 25. "EE,Endianness of data accesses at EL3 and stage 1 translation table walks in the EL3&0 translation regime" "Little,Big"
newline
bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization event enable" "Disabled,Enabled"
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "I,Instruction cache enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "A,Alignment check enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "M,MMU enable for EL3&0 stage 1 address translation" "Disabled,Enabled"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x36100++0x00
line.quad 0x00 "SCTLR_EL3,System Control Register EL3"
bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big"
bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization Barrier enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced"
bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "A,Alignment Check" "Low,High"
bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled"
endif
group.quad spr:0x30F70++0x00
line.quad 0x00 "ATCR_EL1,CPU Auxiliary Control Register"
bitfld.quad 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1"
bitfld.quad 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1"
newline
bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.quad 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
bitfld.quad 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
if (((per.q(spr:0x34110))&0x400000000)==0x400000000)
group.quad spr:0x35F70++0x00
line.quad 0x00 "ATCR_EL12,CPU Auxiliary Control Register"
bitfld.quad 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1"
bitfld.quad 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1"
newline
bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.quad 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
bitfld.quad 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
else
group.quad spr:0x35F70++0x00
line.quad 0x00 "ATCR_EL12,CPU Auxiliary Control Register"
endif
group.quad spr:0x34F70++0x00
line.quad 0x00 "ATCR_EL2,CPU Auxiliary Control Register"
bitfld.quad 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1"
bitfld.quad 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1"
newline
bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.quad 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
bitfld.quad 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
group.quad spr:0x36F70++0x00
line.quad 0x00 "ATCR_EL3,CPU Auxiliary Control Register"
bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
group.quad spr:0x34F71++0x00
line.quad 0x00 "AVTCR_EL2,CPU Auxiliary Control Register"
bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
group.quad spr:0x30F10++0x00
line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register"
if (CORENAME()=="CORTEXA76")
group.quad spr:0x30F11++0x00
line.quad 0x00 "CPUACTLR2_EL1,CPU Auxiliary Control Register 2"
group.quad spr:0x30F12++0x00
line.quad 0x00 "CPUACTLR3_EL1,CPU Auxiliary Control Register 3"
group.quad spr:0x30F14++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 61. "MXP_EN,Max-power throttle enable" "Disabled,Enabled"
bitfld.quad 0x00 57.--58. "MXP_TP,Percentage of throttling in the load-store and vector execute units" "60%,50%,40%,30%"
newline
bitfld.quad 0x00 55.--56. "MXP_ATHR,Peak activity threshold at which max-power throttling is triggered" "70%,60%,50%,40%"
bitfld.quad 0x00 54. "MM_VMID_THR,VMID filter threshold" "16,32"
newline
bitfld.quad 0x00 53. "MM_ASP_EN,Allocation of splintered pages in L2 TLB disable" "No,Yes"
bitfld.quad 0x00 52. "MM_CH_DIS,Contiguous hint disables" "No,Yes"
newline
bitfld.quad 0x00 51. "MM_TLBPF_DIS,L2 TLB prefetcher disable" "No,Yes"
bitfld.quad 0x00 49.--50. "HPA_MODE,Hardware page aggregation mode" "Moderately conservative,Aggressive,Moderately aggressive,Conservative"
newline
bitfld.quad 0x00 48. "HPA_CAP,Limited or full hardware page aggregation selection" "Limited,Full"
bitfld.quad 0x00 47. "HPA_L1_DIS,HPA in L1 TLBs disable" "No,Yes"
newline
bitfld.quad 0x00 46. "HPA_DIS,Hardware page aggregation disable" "No,Yes"
bitfld.quad 0x00 43. "L2_FLUSH,Allocation behavior of copybacks caused by L2 cache hardware flush" "Not allocated,Allocated"
newline
bitfld.quad 0x00 40.--41. "PFT_MM,DRAM prefetch using PrefetchTgt transactions for table walk requests" "Disabled,Conservatively,Aggressively,Always"
bitfld.quad 0x00 38.--39. "PFT_LS,DRAM prefetch using PrefetchTgt transactions for load and store requests" "Disabled,Conservatively,Aggressively,Always"
newline
bitfld.quad 0x00 36.--37. "PFT_IF,DRAM prefetch using PrefetchTgt transactions for instruction fetch requests" "Disabled,Conservatively,Aggressively,Always"
bitfld.quad 0x00 35. "CA_UCLEAN_EVICT_EN,Enable sending WriteEvict transactions on the CPU CHI interface" "Disabled,Enabled"
newline
bitfld.quad 0x00 34. "CA_EVICT_DIS,Disable sending of Evict transactions on the CPU CHI interface" "No,Yes"
bitfld.quad 0x00 32. "ATOMIC_ACQ_NEAR,An atomic instruction to WB memory with acquire semantics" "Exclusive,Make up to 1"
newline
bitfld.quad 0x00 31. "ATOMIC_ST_NEAR,A store atomic instruction to WB memory that does not hit in the cache in Exclusive state" "Exclusive,Make up to 1"
bitfld.quad 0x00 30. "ATOMIC_REL_NEAR,An atomic instruction to WB memory with release semantics that does not hit in the cache in Exclusive state" "Exclusive,Make up to 1"
newline
bitfld.quad 0x00 29. "ATOMIC_LD_NEAR,A load atomic (including SWP & CAS) instruction to WB memory that does not hit in the cache in Exclusive state" "Exclusive,Make up to 1"
bitfld.quad 0x00 28. "TLD_PRED_DIS,Transient load prediction disabled" "No,Yes"
newline
bitfld.quad 0x00 26. "DTLB_CABT_EN,TLB conflict data abort exception enable" "Disabled,Enabled"
bitfld.quad 0x00 24.--25. "WS_THR_L2,Threshold for direct stream to L2 cache on store" "256B,4KB,8KB,Disabled"
newline
bitfld.quad 0x00 22.--23. "WS_THR_L3,Threshold for direct stream to L3 cache on store" "768B,16KB,32KB,Disabled"
bitfld.quad 0x00 20.--21. "WS_THR_L4,Threshold for direct stream to L4 cache on store" "16KB,64KB,128KB,Disabled"
newline
bitfld.quad 0x00 18.--19. "WS_THR_DRAM,Threshold for direct stream to DRAM on store" "64KB,1MB designated as outer-allocate,1MB irrespective of outer-allocate,Disabled"
bitfld.quad 0x00 17. "WS_THR_DCZVA,Have DCZVA use a lower WS_THR_L2 configuration" "Normal store,One lower stream"
newline
bitfld.quad 0x00 15. "PF_DIS,Data-side hardware prefetching disable" "No,Yes"
bitfld.quad 0x00 12.--13. "PF_SS_L2_DIST,Single cache line stride prefetching L2 distance" "22,28,34,40"
newline
bitfld.quad 0x00 8. "PF_STI_DIS,Store prefetches at issue (not overriden by CPUECTLR_EL1[15]) disable" "No,Yes"
bitfld.quad 0x00 7. "PF_STS_DIS,Store-stride prefetches disable" "No,Yes"
newline
bitfld.quad 0x00 5. "RPF_DIS,Region prefetcher disable" "No,Yes"
bitfld.quad 0x00 4. "RPF_LO_CONF,Region prefetcher training behavior" "Limited,Always"
newline
bitfld.quad 0x00 3. "RPF_PHIT_EN,Region prefetcher propagation on hit enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "EXTLLC,Internal or external Last-level cache in the system" "Internal,External"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x30F14++0x00
line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register"
bitfld.quad 0x00 38.--39. "ATOM,Force most cacheable atomic instructions to be executed far in the L3 cache or beyond and near in the L1 cache" "Near - hit/unique | Far - miss/shared,Near,Far,Near - load | Far - store"
bitfld.quad 0x00 37. "L2FLUSH,L2 cache flush" "Enabled,Disabled"
newline
bitfld.quad 0x00 29.--30. "L3WSCTL,Write streaming no-L3-allocate threshold" "128th line,1024th line,4096th line,Disabled"
bitfld.quad 0x00 27.--28. "L2WSCTL,Write streaming no-L2-allocate threshold" "16th line,128th line,512th line,Disabled"
newline
bitfld.quad 0x00 25.--26. "L1WSCTL,Write streaming no-L1-allocate threshold" "4th line,64th line,128th line,Disabled"
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control. Maximum number of outstanding data prefetches allowed in the L1 memory system" "Disabled,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--12. "L3PCTL,L3 Data prefetch control. Maximum number of outstanding data prefetches allowed that can be sent to the L3 memory system" "16 lines,32 lines,Reserved,Reserved,Prefetch disabled,2 lines,4 lines,8 lines"
bitfld.quad 0x00 0. "EXTLLC,Type of last-level cache that is present in the system" "Internal,External"
endif
group.quad spr:0x36F81++0x00
line.quad 0x00 "CPUPCR_EL3,CPU Private Control Register"
group.quad spr:0x36F83++0x00
line.quad 0x00 "CPUPMR_EL3,CPU Private Mask Register"
group.quad spr:0x36F82++0x00
line.quad 0x00 "CPUPOR_EL3,CPU Private Operation Register"
group.quad spr:0x36F80++0x00
line.quad 0x00 "CPUPSELR_EL3,CPU Private Selection Register"
group.quad spr:0x30101++0x00
line.quad 0x00 "ACTLR_EL1,Auxiliary Control Register 1"
if (CORENAME()=="CORTEXA76")
group.quad spr:0x34101++0x00
line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register 2"
bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 4. "AMEN,Activity Monitor enable" "Trapped,Not trapped"
bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible"
group.quad spr:0x36101++0x00
line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register 3"
bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible"
bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 4. "AMEN,Activity Monitor enable" "Trapped,Not trapped"
newline
bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible"
group.quad spr:0x30102++0x00
line.quad 0x00 "CPACR_EL1,Coprocessor Access Control Register 1"
bitfld.quad 0x00 28. "TTA,Traps EL0 and EL1 System Register accesses to all implemented trace Registers to EL1" "No trap,?..."
bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap"
group.quad spr:0x35102++0x00
line.quad 0x00 "CPACR_EL12,Coprocessor Access Control Register 1"
bitfld.quad 0x00 28. "TTA,Traps EL0 and EL1 System Register accesses to all implemented trace Registers to EL1" "No trap,?..."
bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x34101++0x00
line.quad 0x00 "ACTLR_EL2,Auxiliary Control Register 2"
bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible"
bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible"
group.quad spr:0x36101++0x00
line.quad 0x00 "ACTLR_EL3,Auxiliary Control Register 3"
bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible"
bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible"
bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible"
if (((per.q(spr:0x30040))&0xF00000)==0x100000)
group.quad spr:0x30102++0x00
line.quad 0x00 "CPACR_EL1,Coprocessor Access Control Register 1"
bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap"
else
rgroup.quad spr:0x30102++0x00
line.quad 0x00 "CPACR_EL1,Coprocessor Access Control Register 1"
endif
group.quad spr:0x35102++0x00
line.quad 0x00 "CPACR_EL12,Coprocessor Access Control Register 1"
bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap"
endif
group.quad spr:0x34112++0x00
line.quad 0x00 "CPTR_EL2,Coprocessor Access Control Register 2"
bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "No trap,Trap"
bitfld.quad 0x00 10. "TFP,Trap Floating Point and Advanced SIMD execution" "No trap,Trap"
group.quad spr:0x36112++0x00
line.quad 0x00 "CPTR_EL3,Coprocessor Access Control Register 3"
bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "No trap,Trap"
bitfld.quad 0x00 10. "TFP,Trap Floating Point and Advanced SIMD execution" "No trap,Trap"
group.quad spr:0x36110++0x00
line.quad 0x00 "SCR_EL3,Secure Configuration Register"
bitfld.quad 0x00 15. "TERR,Trap Error record accesses" "No Trap,Trap"
bitfld.quad 0x00 14. "TLOR,Trap access to the LOR Registers from Non-secure EL1 and EL2 to EL3" "No trap,Trap"
newline
bitfld.quad 0x00 13. "TWE,Trap WFE" "No trap,Trap"
bitfld.quad 0x00 12. "TWI,Trap WFI" "No trap,Trap"
newline
bitfld.quad 0x00 11. "ST,Enables Secure EL1 access to the CNTPS_TVAL_EL1 CNTPS_CTL_EL1 CNTPS_CVAL_EL1[63:0] Registers" "Disabled,Enabled"
bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64"
newline
bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.quad 0x00 8. "HCE,Hyp Call enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable at EL1, EL2, or EL3" "No,Yes"
bitfld.quad 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
newline
bitfld.quad 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
bitfld.quad 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
newline
bitfld.quad 0x00 0. "NS,Secure mode" "Secure,Non-secure"
if (CORENAME()=="CORTEXA76")
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hyp Configuration Register"
bitfld.quad 0x00 38. "MIOCNCE,Mismatched inner/outer cacheable non-coherency enable" "Not lost,Lost"
bitfld.quad 0x00 37. "TEA,Route synchronous external aborts to EL2" "Not routed,Routed"
newline
bitfld.quad 0x00 36. "TERR,Trap error record accesses" "No trap,Trap"
bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 34. "E2H,EL2 host" "Disabled,Enabled"
bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes"
newline
bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes"
bitfld.quad 0x00 30. "TRVM,Trap read of virtual memory controls" "Disabled,Enabled"
newline
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
bitfld.quad 0x00 27. "TGE,Trap general exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
newline
bitfld.quad 0x00 26. "TVM,Trap virtual memory controls to EL2" "Disabled,Enabled"
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 24. "TPU,Trap cache maintenance instructions to point of unification to EL2" "Disabled,Enabled"
bitfld.quad 0x00 23. "TPC,Trap data/Unified cache maintenance instructions to point of coherency to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 22. "TSW,Trap data/Unified cache maintenance instructions by set/Way to EL2" "Disabled,Enabled"
bitfld.quad 0x00 21. "TACR,Trap auxiliary control Register" "Disabled,Enabled"
newline
bitfld.quad 0x00 20. "TIDCP,Trap implementation dependent functionality" "Disabled,Enabled"
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
newline
bitfld.quad 0x00 18. "TID3,Trap ID group 3" "Disabled,Enabled"
bitfld.quad 0x00 17. "TID2,Trap ID group 2" "Disabled,Enabled"
newline
bitfld.quad 0x00 16. "TID1,Trap ID group 1" "Disabled,Enabled"
bitfld.quad 0x00 15. "TID0,Trap ID group 0" "Disabled,Enabled"
newline
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
newline
bitfld.quad 0x00 12. "DC,Default cacheable" "Disabled,Enabled"
bitfld.quad 0x00 10.--11. "BSU,Barrier shareability upgrade - determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
newline
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
bitfld.quad 0x00 8. "VSE,Virtual system error/Asynchronous abort" "No pending,Pending"
newline
bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "Not pending,Pending"
bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled"
bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled"
bitfld.quad 0x00 2. "PTW,Protected table walk" "Disabled,Enabled"
newline
bitfld.quad 0x00 0. "VM,Second stage of translation enable" "Disabled,Enabled"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x34110++0x00
line.quad 0x00 "HCR_EL2,Hyp Configuration Register"
bitfld.quad 0x00 38. "MIOCNCE,Mismatched inner/outer cacheable non-coherency enable" "Not lost,Lost"
bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 34. "E2H,EL2 host" "Disabled,Enabled"
bitfld.quad 0x00 33. "ID,Stage 2 instruction cache disable" "No,Yes"
newline
bitfld.quad 0x00 32. "CD,Stage 2 data cache disable" "No,Yes"
bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit"
newline
bitfld.quad 0x00 30. "TRVM,Trap read of virtual memory controls" "Disabled,Enabled"
bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "TGE,Trap general exceptions has an enhanced role when EL2 is using AArch64" "Disabled,Enabled"
bitfld.quad 0x00 26. "TVM,Trap virtual memory controls to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "Disabled,Enabled"
bitfld.quad 0x00 24. "TPU,Trap cache maintenance instructions to point of unification to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 23. "TPC,Trap data/Unified cache maintenance instructions to point of coherency to EL2" "Disabled,Enabled"
bitfld.quad 0x00 22. "TSW,Trap data/Unified cache maintenance instructions by set/Way to EL2" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "TACR,Trap auxiliary control Register" "Disabled,Enabled"
bitfld.quad 0x00 20. "TIDCP,Trap implementation dependent functionality" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "TSC,Trap SMC" "Disabled,Enabled"
bitfld.quad 0x00 18. "TID3,Trap ID group 3" "Disabled,Enabled"
newline
bitfld.quad 0x00 17. "TID2,Trap ID group 2" "Disabled,Enabled"
bitfld.quad 0x00 16. "TID1,Trap ID group 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 15. "TID0,Trap ID group 0" "Disabled,Enabled"
bitfld.quad 0x00 14. "TWE,Trap WFE" "Disabled,Enabled"
newline
bitfld.quad 0x00 13. "TWI,Trap WFI" "Disabled,Enabled"
bitfld.quad 0x00 12. "DC,Default cacheable" "Disabled,Enabled"
newline
bitfld.quad 0x00 10.--11. "BSU,Barrier shareability upgrade - determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System"
bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced"
newline
bitfld.quad 0x00 8. "VSE,Virtual system error/Asynchronous abort" "No pending,Pending"
bitfld.quad 0x00 7. "VI,Virtual IRQ interrupt" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "VF,Virtual FIQ interrupt" "Not pending,Pending"
bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 4. "IMO,Physical IRQ routing" "Disabled,Enabled"
bitfld.quad 0x00 3. "FMO,Physical FIQ routing" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "PTW,Protected table walk" "Disabled,Enabled"
bitfld.quad 0x00 0. "VM,Second stage of translation enable" "Disabled,Enabled"
endif
group.quad spr:0x30510++0x00
line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Registers"
group.quad spr:0x35510++0x00
line.quad 0x00 "AFSR0_EL12,Auxiliary Fault Status Registers"
group.quad spr:0x30511++0x00
line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Registers"
group.quad spr:0x35511++0x00
line.quad 0x00 "AFSR1_EL12,Auxiliary Fault Status Registers"
group.quad spr:0x34510++0x00
line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Registers"
group.quad spr:0x34511++0x00
line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Registers"
group.quad spr:0x36510++0x00
line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Registers"
group.quad spr:0x36511++0x00
line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Registers"
tree.open "Exception Syndrome Registers"
if (((per.q(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x30520))&0xFC000000)==0x04000000)
if (((per.q(spr:0x30520))&0x01000000)==0x01000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.q(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000))
if (((per.q(spr:0x30520))&0x01000000)==0x01000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.q(spr:0x30520))&0x01000000)==0x01000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x30520))&0xFC000000)==0x18000000)
if (((per.q(spr:0x30520))&0x01000000)==0x01000000)
if (((per.q(spr:0x30520))&0x08)==0x00)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
else
if (((per.q(spr:0x30520))&0x08)==0x00)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
endif
elif (((per.q(spr:0x30520))&0xFC000000)==0x1C000000)
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.q(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x30520))&0xFC000000)==0x60000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS"
elif (((per.q(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.q(spr:0x30520))&0x3F)==0x10)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,UEO/CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
endif
elif (((per.q(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.q(spr:0x30520))&0x3F)==0x10)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the Register accessed by the instruction is sixty-four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,UEO/CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous Tag Check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the Register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous Tag Check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
endif
elif (((per.q(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.q(spr:0x30520))&0x3F)==0x10)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO/CE"
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous Tag Check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous Tag Check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
endif
elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x30520))&0xFD000000)==0xBD000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Additional information about the SError interrupt"
elif (((per.q(spr:0x30520))&0xFD000000)==0xBC000000)
if (((per.q(spr:0x30520))&0x3F)==0x11)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit error synchronization event" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous error type" "UC,UEU,?..."
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.q(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000))
if (((per.q(spr:0x30520))&0x1000000)==0x1000000)
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "Not stepped,Stepped"
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
elif (((per.q(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x30520++0x00
line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
endif
if (((per.q(spr:0x35520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x35520))&0xFC000000)==0x04000000)
if (((per.q(spr:0x35520))&0x01000000)==0x01000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.q(spr:0x35520))&0xFC000000)==(0x0C000000||0x14000000))
if (((per.q(spr:0x35520))&0x01000000)==0x01000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x35520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.q(spr:0x35520))&0x01000000)==0x01000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x35520))&0xFC000000)==0x18000000)
if (((per.q(spr:0x35520))&0x01000000)==0x01000000)
if (((per.q(spr:0x35520))&0x08)==0x00)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
else
if (((per.q(spr:0x35520))&0x08)==0x00)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
endif
elif (((per.q(spr:0x35520))&0xFC000000)==0x1C000000)
if (((per.q(spr:0x35520))&0x1000000)==0x1000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.q(spr:0x35520))&0xFC000000)==(0x44000000||0x54000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x35520))&0xFC000000)==0x60000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS"
elif (((per.q(spr:0x35520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.q(spr:0x35520))&0x3F)==0x10)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO/CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
endif
elif (((per.q(spr:0x35520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.q(spr:0x35520))&0x3F)==0x10)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the Register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,UEO/CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous Tag Check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the Register accessed by the instruction is sixty-four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous Tag Check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
endif
elif (((per.q(spr:0x35520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.q(spr:0x35520))&0x3F)==0x10)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO/CE"
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous Tag Check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous Tag Check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
endif
elif (((per.q(spr:0x35520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x35520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x35520))&0xFD000000)==0xBD000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Additional information about the SError interrupt"
elif (((per.q(spr:0x35520))&0xFD000000)==0xBC000000)
if (((per.q(spr:0x35520))&0x3F)==0x11)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit error synchronization event" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous error type" "UC,UEU,?..."
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.q(spr:0x35520))&0xFC000000)==(0xC0000000||0xC4000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x35520))&0xFC000000)==(0xC8000000||0xCC000000))
if (((per.q(spr:0x35520))&0x1000000)==0x1000000)
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "Not stepped,Stepped"
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
elif (((per.q(spr:0x35520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x35520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x35520++0x00
line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL12)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,?..."
endif
if (((per.q(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x34520))&0xFC000000)==0x04000000)
if (((per.q(spr:0x34520))&0x01000000)==0x01000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000))
if (((per.q(spr:0x34520))&0x01000000)==0x01000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.q(spr:0x34520))&0x01000000)==0x01000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==0x18000000)
if (((per.q(spr:0x34520))&0x01000000)==0x01000000)
if (((per.q(spr:0x34520))&0x08)==0x00)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
else
if (((per.q(spr:0x34520))&0x08)==0x00)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
endif
elif (((per.q(spr:0x34520))&0xFC000000)==0x1C000000)
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000||0x5C000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x34520))&0xFC000000)==0x4C000000)
if (((per.q(spr:0x34520))&0x01080000)==0x01080000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
elif (((per.q(spr:0x34520))&0x01080000)==0x00080000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==0x60000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,The Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,The Op2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,The Op1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIR,Indicates the direction of the trapped instruction" "Write/MSR,Read/MRS"
elif (((per.q(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.q(spr:0x34520))&0x3F)==0x10)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,UEO/CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
endif
elif (((per.q(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.q(spr:0x34520))&0x3F)==0x10)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the Register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,UEO/CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the Register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
endif
elif (((per.q(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.q(spr:0x34520))&0x3F)==0x10)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO/CE"
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
endif
elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x34520))&0xFD000000)==0xBD000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Additional information about the SError interrupt"
elif (((per.q(spr:0x34520))&0xFD000000)==0xBC000000)
if (((per.q(spr:0x34520))&0x3F)==0x11)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit error synchronization event" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous error type" "UC,UEU,?..."
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.q(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000))
if (((per.q(spr:0x34520))&0x1000000)==0x1000000)
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
bitfld.quad 0x00 6. "EX,Exclusive operation" "Not stepped,Stepped"
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid"
newline
newline
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
elif (((per.q(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000))
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x34520++0x00
line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,?..."
endif
if (((per.q(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
elif (((per.q(spr:0x36520))&0xFC000000)==0x04000000)
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000))
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000))
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==0x18000000)
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
if (((per.q(spr:0x36520))&0x08)==0x00)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
else
if (((per.q(spr:0x36520))&0x08)==0x00)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,?..."
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
endif
endif
elif (((per.q(spr:0x36520))&0xFC000000)==0x1C000000)
if (((per.q(spr:0x36520))&0x1000000)==0x1000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==0x4C000000)
if (((per.q(spr:0x36520))&0x01080000)==0x01080000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
elif (((per.q(spr:0x36520))&0x01080000)==0x00080000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid"
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional"
endif
elif (((per.q(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000||0x5C000000))
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.q(spr:0x36520))&0xFC000000)==0x60000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3"
bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read"
elif (((per.q(spr:0x36520))&0xFC000000)==0x7C000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.long 0x00 0.--24. 1. "IMPL_DEF,Implementation defined"
elif (((per.q(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000))
if (((per.q(spr:0x36520))&0x3F)==0x10)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,UEO/CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
newline
bitfld.quad 0x00 9. "EA,External abort type" "Not external,External"
newline
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
bitfld.quad 0x00 0.--5. "IFSC,Instruction fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Unsupported atomic hardware,?..."
endif
elif (((per.q(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000))
if (((per.q(spr:0x36520))&0x3F)==0x10)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the Register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous error type" "UER,Reserved,UC,UEO/CE"
newline
bitfld.quad 0x00 10. "FNV,FAR not valid" "No,Yes"
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
bitfld.quad 0x00 22.--23. "SAS,Syndrome access size" "Byte,Halfword,Word,Doubleword"
newline
bitfld.quad 0x00 21. "SSE,Syndrome sign extend" "Not required,Required"
bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.quad 0x00 15. "SF,Width of the Register accessed by the instruction is Sixty-Four" "32-bit,64-bit"
bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes"
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a cache maintenance instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
endif
elif (((per.q(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000))
if (((per.q(spr:0x36520))&0x3F)==0x10)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,Reserved,UC,UEO/CE"
bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes"
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid"
newline
newline
newline
newline
newline
bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes"
bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2"
newline
bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write"
bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Synchronous tag check fail,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Atomic/AArch64,Reserved,Reserved,Lockdown,Unsupported Exclusive access,?..."
endif
elif (((per.q(spr:0x36520))&0xFC800000)==0xB0800000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred"
newline
bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred"
bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred"
elif (((per.q(spr:0x36520))&0xFC800000)==0xB0000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid"
bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7"
elif (((per.q(spr:0x36520))&0xFD000000)==0xBD000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Instruction syndrome valid" "Not valid,Valid"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Additional information about the SError interrupt"
elif (((per.q(spr:0x36520))&0xFD000000)==0xBC000000)
if (((per.q(spr:0x36520))&0x3F)==0x11)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
bitfld.quad 0x00 13. "IESB,Implicit error synchronization event" "Not synchronized,Synchronized"
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous error type" "UC,UEU,?..."
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold"
newline
newline
bitfld.quad 0x00 0.--5. "DFSC,Data fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..."
endif
elif (((per.q(spr:0x36520))&0xFC000000)==0xF0000000)
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit"
newline
hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value"
else
group.quad spr:0x36520++0x00
line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)"
bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point Register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/AArch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Breakpoint/AArch64,?..."
endif
tree.end
newline
if (CORENAME()=="CORTEXA76")
group.quad spr:0x30C11++0x00
line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register"
bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,?..."
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC/Uncontainable,UEU/Unrecoverable,?..."
bitfld.quad 0x00 0.--5. "DFSC,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..."
elif (CORENAME()=="CORTEXA55")
if (((per.q(spr:0x30C11))&0x1000000)==0x00)&&(((per.q(spr:0x30C11))&0x3F)==0x11)
group.quad spr:0x30C11++0x00
line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register"
bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,?..."
newline
bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
bitfld.quad 0x00 0.--5. "DFSC,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt/EAE=0,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt/EAE=1,?..."
else
group.quad spr:0x30C11++0x00
line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register"
bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,?..."
newline
bitfld.quad 0x00 0.--5. "DFSC,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt/EAE=0,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt/EAE=1,?..."
endif
endif
if (CORENAME()=="CORTEXA76")
group.quad spr:0x34523++0x00
line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch32"
bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
bitfld.quad 0x00 12. "EXT,External Abort Type" "0,1"
group.quad spr:0x34523++0x00
line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch64"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x34523++0x00
line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch32"
bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
group.quad spr:0x34523++0x00
line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch64"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined"
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information"
if (((per.q(spr:0x34C11))&0x200)==0x00)
group.quad spr:0x34C11++0x00
line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch32 Short-descriptor"
bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred"
bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
newline
bitfld.quad 0x00 9. "LPAE,Translation table format" "Short,Long"
bitfld.quad 0x00 0.--3. 10. "FS,Fault status code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous SError interrupt,?..."
else
group.quad spr:0x34C11++0x00
line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch32 Long-descriptor"
bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred"
bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..."
newline
bitfld.quad 0x00 9. "LPAE,Translation table format" "Short,Long"
bitfld.quad 0x00 0.--5. "STATUS,Fault status code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous SError interrupt,?..."
endif
endif
group.quad spr:0x34C11++0x00
line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch64"
bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred"
bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined"
newline
hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information"
if (CORENAME()=="CORTEXA76")
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.quad 0x00 12. "EXT,External abort type" "0,1"
newline
bitfld.quad 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault status bits" "Address size fault/TTBR0/TTBR1,Address size fault/L1,Address size fault/L2,Address size fault/L3,Reserved,Translation fault/L1,Translation fault/L2,Translation fault/L3,Reserved,Access flag fault/L1,Access flag fault/L2,Access flag fault/L3,Reserved,Permission fault/L1,Permission fault/L2,Permission fault/L3,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/L1,Synchronous external abort on translation table walk/L2,Synchronous external abort on translation table walk/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug exception,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
elif (CORENAME()=="CORTEXA55")
if (((per.q(c15:0x0202))&0x80000000)==0x00000000)
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
rbitfld.quad 0x00 12. "EXT,External abort type" "0,?..."
newline
bitfld.quad 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
newline
bitfld.quad 0x00 0.--3. 10. "FS,Fault status. Type of exception generated" "Reserved,Alignment,Debug,Access/L1,Reserved,Translation/L1,Access/L2,Translation/L2,External,Domain/L1,Reserved,Domain/L2,External/L1,Permission/L1,External/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,?..."
else
group.quad spr:0x34501++0x00
line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register"
bitfld.quad 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
rbitfld.quad 0x00 12. "EXT,External abort type" "0,?..."
newline
bitfld.quad 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
newline
bitfld.quad 0x00 0.--5. "STATUS,Fault status bits" "Address size fault/TTBR0/TTBR1,Address size fault/L1,Address size fault/L2,Address size fault/L3,Reserved,Translation fault/L1,Translation fault/L2,Translation fault/L3,Reserved,Access flag fault/L1,Access flag fault/L2,Access flag fault/L3,Reserved,Permission fault/L1,Permission fault/L2,Permission fault/L3,Synchronous external abort,Reserved,Reserved,Reserved,Reserved,Synchronous external abort on translation table walk/L1,Synchronous external abort on translation table walk/L2,Synchronous external abort on translation table walk/L3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug exception,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
endif
endif
group.quad spr:0x30600++0x00
line.quad 0x00 "FAR_EL1,Fault Address Register"
group.quad spr:0x35600++0x00
line.quad 0x00 "FAR_EL12,Fault Address Register"
group.quad spr:0x34600++0x00
line.quad 0x00 "FAR_EL2,Fault Address Register"
group.quad spr:0x36600++0x00
line.quad 0x00 "FAR_EL3,Fault Address Register"
group.quad spr:0x34604++0x00
line.quad 0x00 "HPFAR_EL2,Hyp IPA Fault Address Register"
hexmask.quad 0x00 4.--39. 0x10 "FIPA[47:12],Bits [47:12] of the faulting intermediate physical address"
group.quad spr:0x30C00++0x00
line.quad 0x00 "VBAR_EL1,Vector Base Address Register (EL1)"
hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector Base Address"
group.quad spr:0x35C00++0x00
line.quad 0x00 "VBAR_EL12,Vector Base Address Register (EL12)"
hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector Base Address"
group.quad spr:0x34C00++0x00
line.quad 0x00 "VBAR_EL2,Vector Base Address Register (EL2)"
hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector Base Address"
group.quad spr:0x36C00++0x00
line.quad 0x00 "VBAR_EL3,Vector Base Address Register (EL3)"
hexmask.quad 0x00 11.--63. 0x08 "VBA,Vector Base Address"
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
group.quad spr:0x36C02++0x00
line.quad 0x00 "RMR_EL3,Reset Management Register"
bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested"
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x36C01++0x00
line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register"
hexmask.quad 0x00 0.--39. 0x01 "RVBA,Reset Vector Base Address"
group.quad spr:0x36C02++0x00
line.quad 0x00 "RMR_EL3,Reset Management Register"
bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
endif
rgroup.quad spr:0x30C10++0x00
line.quad 0x00 "ISR_EL1,Interrupt Status Register"
bitfld.quad 0x00 8. "A,SError interrupt pending bit" "Not pending,Pending"
bitfld.quad 0x00 7. "I,IRQ pending bit" "Not pending,Pending"
newline
bitfld.quad 0x00 6. "F,FIQ pending bit" "Not pending,Pending"
group.quad spr:0x30D01++0x00
line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register"
group.quad spr:0x35D01++0x00
line.quad 0x00 "CONTEXTIDR_EL12,Context ID Register"
group.quad spr:0x34D01++0x00
line.quad 0x00 "CONTEXTIDR_EL2,Context ID Register"
group.quad spr:0x33D02++0x00
line.quad 0x00 "TPIDR_EL0,Software Thread ID Register"
group.quad spr:0x33D03++0x00
line.quad 0x00 "TPIDRRO_EL0,Software Thread ID Register"
group.quad spr:0x30D04++0x00
line.quad 0x00 "TPIDR_EL1,Software Thread ID Register"
group.quad spr:0x34D02++0x00
line.quad 0x00 "TPIDR_EL2,Software Thread ID Register"
group.quad spr:0x36D02++0x00
line.quad 0x00 "TPIDR_EL3,Software Thread ID Register"
tree "System Instructions"
wgroup.quad spr:0x10710++0x00
line.quad 0x00 "IC_IALLUIS,IC_IALLUIS"
wgroup.quad spr:0x10750++0x00
line.quad 0x00 "IC_IALLU,IC_IALLU"
wgroup.quad spr:0x13751++0x00
line.quad 0x00 "IC_IVAU,IC_IVAU"
wgroup.quad spr:0x13741++0x00
line.quad 0x00 "DC_ZVA,DC_ZVA"
wgroup.quad spr:0x10761++0x00
line.quad 0x00 "DC_IVAC,DC_IVAC"
wgroup.quad spr:0x10762++0x00
line.quad 0x00 "DC_ISW,DC_ISW"
wgroup.quad spr:0x137A1++0x00
line.quad 0x00 "DC_CVAC,DC_CVAC"
wgroup.quad spr:0x137C1++0x00
line.quad 0x00 "DC_CVAP,DC CVAP"
wgroup.quad spr:0x107A2++0x00
line.quad 0x00 "DC_CSW,DC_CSW"
wgroup.quad spr:0x137B1++0x00
line.quad 0x00 "DC_CVAU,DC_CVAU"
wgroup.quad spr:0x137E1++0x00
line.quad 0x00 "DC_CIVAC,DC_CIVAC"
wgroup.quad spr:0x107E2++0x00
line.quad 0x00 "DC_CISW,DC_CISW"
wgroup.quad spr:0x10780++0x00
line.quad 0x00 "AT_S1E1R,AT_S1E1R"
wgroup.quad spr:0x10781++0x00
line.quad 0x00 "AT_S1E1W,AT_S1E1W"
wgroup.quad spr:0x10782++0x00
line.quad 0x00 "AT_S1E0R,AT_S1E0R"
wgroup.quad spr:0x10790++0x00
line.quad 0x00 "AT_S1E1RP,AT_S1E1RP"
wgroup.quad spr:0x10791++0x00
line.quad 0x00 "AT_S1E1WP,AT_S1E1WP"
wgroup.quad spr:0x10783++0x00
line.quad 0x00 "AT_S1E0W,AT_S1E0W"
wgroup.quad spr:0x14784++0x00
line.quad 0x00 "AT_S12E1R,AT_S12E1R"
wgroup.quad spr:0x14785++0x00
line.quad 0x00 "AT_S12E1W,AT_S12E1W"
wgroup.quad spr:0x14786++0x00
line.quad 0x00 "AT_S12E0R,AT_S12E0R"
wgroup.quad spr:0x14787++0x00
line.quad 0x00 "AT_S12E0W,AT_S12E0W"
wgroup.quad spr:0x14780++0x00
line.quad 0x00 "AT_S1E2R,AT_S1E2R"
wgroup.quad spr:0x14781++0x00
line.quad 0x00 "AT_S1E2W,AT_S1E2W"
wgroup.quad spr:0x16780++0x00
line.quad 0x00 "AT_S1E3R,AT_S1E3R"
wgroup.quad spr:0x16781++0x00
line.quad 0x00 "AT_S1E3W,AT_S1E3W"
wgroup.quad spr:0x10870++0x00
line.quad 0x00 "TLBI_VMALLE1,TLBI_VMALLE1"
wgroup.quad spr:0x10871++0x00
line.quad 0x00 "TLBI_VAE1,TLBI_VAE1"
wgroup.quad spr:0x10872++0x00
line.quad 0x00 "TLBI_ASIDE1,TLBI_ASIDE1"
wgroup.quad spr:0x10873++0x00
line.quad 0x00 "TLBI_VAAE1,TLBI_VAAE1"
wgroup.quad spr:0x10875++0x00
line.quad 0x00 "TLBI_VALE1,TLBI_VALE1"
wgroup.quad spr:0x10877++0x00
line.quad 0x00 "TLBI_VAALE1,TLBI_VAALE1"
wgroup.quad spr:0x10830++0x00
line.quad 0x00 "TLBI_VMALLE1IS,TLBI_VMALLE1IS"
wgroup.quad spr:0x10831++0x00
line.quad 0x00 "TLBI_VAE1IS,TLBI_VAE1IS"
wgroup.quad spr:0x10832++0x00
line.quad 0x00 "TLBI_ASIDE1IS,TLBI_ASIDE1IS"
wgroup.quad spr:0x10833++0x00
line.quad 0x00 "TLBI_VAAE1IS,TLBI_VAAE1IS"
wgroup.quad spr:0x10835++0x00
line.quad 0x00 "TLBI_VALE1IS,TLBI_VALE1IS"
wgroup.quad spr:0x10837++0x00
line.quad 0x00 "TLBI_VAALE1IS,TLBI_VAALE1IS"
wgroup.quad spr:0x14801++0x00
line.quad 0x00 "TLBI_IPAS2E1IS,TLBI_IPAS2E1IS"
wgroup.quad spr:0x14805++0x00
line.quad 0x00 "TLBI_IPAS2LE1IS,TLBI_IPAS2LE1IS"
wgroup.quad spr:0x14841++0x00
line.quad 0x00 "TLBI_IPAS2E1,TLBI_IPAS2E1"
wgroup.quad spr:0x14845++0x00
line.quad 0x00 "TLBI_IPAS2LE1,TLBI_IPAS2LE1"
wgroup.quad spr:0x14871++0x00
line.quad 0x00 "TLBI_VAE2,TLBI_VAE2"
wgroup.quad spr:0x14875++0x00
line.quad 0x00 "TLBI_VALE2,TLBI_VALE2"
wgroup.quad spr:0x14876++0x00
line.quad 0x00 "TLBI_VMALLS12E1,TLBI_VMALLS12E1"
wgroup.quad spr:0x14831++0x00
line.quad 0x00 "TLBI_VAE2IS,TLBI_VAE2IS"
wgroup.quad spr:0x14835++0x00
line.quad 0x00 "TLBI_VALE2IS,TLBI_VALE2IS"
wgroup.quad spr:0x14836++0x00
line.quad 0x00 "TLBI_VMALLS12E1IS,TLBI_VMALLS12E1IS"
wgroup.quad spr:0x16871++0x00
line.quad 0x00 "TLBI_VAE3,TLBI_VAE3"
wgroup.quad spr:0x16875++0x00
line.quad 0x00 "TLBI_VALE3,TLBI_VALE3"
wgroup.quad spr:0x16831++0x00
line.quad 0x00 "TLBI_VAE3IS,TLBI_VAE3IS"
wgroup.quad spr:0x16835++0x00
line.quad 0x00 "TLBI_VALE3IS,TLBI_VALE3IS"
wgroup.quad spr:0x14870++0x00
line.quad 0x00 "TLBI_ALLE2,TLBI_ALLE2"
wgroup.quad spr:0x14830++0x00
line.quad 0x00 "TLBI_ALLE2IS,TLBI_ALLE2IS"
wgroup.quad spr:0x14874++0x00
line.quad 0x00 "TLBI_ALLE1,TLBI_ALLE1"
wgroup.quad spr:0x14834++0x00
line.quad 0x00 "TLBI_ALLE1IS,TLBI_ALLE1IS"
wgroup.quad spr:0x16870++0x00
line.quad 0x00 "TLBI_ALLE3,TLBI_ALLE3"
wgroup.quad spr:0x16830++0x00
line.quad 0x00 "TLBI_ALLE3IS,TLBI_ALLE3IS"
tree.end
tree.end
tree "Memory Management Unit"
group.quad spr:0x34113++0x00
line.quad 0x00 "HSTR_EL2,Hyp System Trap Register"
bitfld.quad 0x00 15. "T15,Trap to Hyp mode Non-secure priv 15" "No trap,Trap"
bitfld.quad 0x00 13. "T13,Trap to Hyp mode Non-secure priv 13" "No trap,Trap"
newline
bitfld.quad 0x00 12. "T12,Trap to Hyp mode Non-secure priv 12" "No trap,Trap"
bitfld.quad 0x00 11. "T11,Trap to Hyp mode Non-secure priv 11" "No trap,Trap"
newline
bitfld.quad 0x00 10. "T10,Trap to Hyp mode Non-secure priv 10" "No trap,Trap"
bitfld.quad 0x00 9. "T9,Trap to Hyp mode Non-secure priv 9" "No trap,Trap"
newline
bitfld.quad 0x00 8. "T8,Trap to Hyp mode Non-secure priv 8" "No trap,Trap"
bitfld.quad 0x00 7. "T7,Trap to Hyp mode Non-secure priv 7" "No trap,Trap"
newline
bitfld.quad 0x00 6. "T6,Trap to Hyp mode Non-secure priv 6" "No trap,Trap"
bitfld.quad 0x00 5. "T5,Trap to Hyp mode Non-secure priv 5" "No trap,Trap"
newline
bitfld.quad 0x00 3. "T3,Trap to Hyp mode Non-secure priv 3" "No trap,Trap"
bitfld.quad 0x00 2. "T2,Trap to Hyp mode Non-secure priv 2" "No trap,Trap"
newline
bitfld.quad 0x00 1. "T1,Trap to Hyp mode Non-secure priv 1" "No trap,Trap"
bitfld.quad 0x00 0. "T0,Trap to Hyp mode Non-secure priv 0" "No trap,Trap"
group.quad spr:0x34117++0x00
line.quad 0x00 "HACR_EL2,Hyp Auxiliary Configuration Register"
if (CORENAME()=="CORTEXA76")
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x35200++0x00
line.quad 0x00 "TTBR0_EL12,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x35201++0x00
line.quad 0x00 "TTBR1_EL12,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Registers"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[47:2],Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34201++0x00
line.quad 0x00 "TTBR1_EL2,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[47:1],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Registers"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[47:1],Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.word 0x00 48.--63. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 4.--47. 0x10 "BADDR[47:4],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x30200++0x00
line.quad 0x00 "TTBR0_EL1,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x30201++0x00
line.quad 0x00 "TTBR1_EL1,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x35200++0x00
line.quad 0x00 "TTBR0_EL12,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x35201++0x00
line.quad 0x00 "TTBR1_EL12,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34200++0x00
line.quad 0x00 "TTBR0_EL2,Translation Table Base Registers"
hexmask.quad 0x00 1.--47. 0x02 "BADDR[47:2],Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34201++0x00
line.quad 0x00 "TTBR1_EL2,Translation Table Base Registers"
hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x36200++0x00
line.quad 0x00 "TTBR0_EL3,Translation Table Base Registers"
hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad spr:0x34210++0x00
line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register"
hexmask.quad.word 0x00 48.--63. 1. "VMID,The VMID for the translation table"
hexmask.quad 0x00 2.--47. 0x04 "BADDR[47:2],Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
endif
group.quad spr:0x30202++0x00
line.quad 0x00 "TCR_EL1,Translation Control Registers"
bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 42. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes"
bitfld.quad 0x00 41. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes"
newline
bitfld.quad 0x00 40. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 39. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 38. "TBI1,Top Byte ignored" "Used,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID Size" "8 bit,16 bit"
bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 Granule size" "Reserved,16KByte,4KByte,64KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer Cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner Cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes"
bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 7. "EPD0,Translation Table walk disable for TTBR0 as described in LPAE" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.quad spr:0x35202++0x00
line.quad 0x00 "TCR_EL12,Translation Control Registers"
bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 42. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes"
bitfld.quad 0x00 41. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes"
newline
bitfld.quad 0x00 40. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 39. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 38. "TBI1,Top Byte ignored" "Used,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID Size" "8 bit,16 bit"
bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 Granule size" "Reserved,16KByte,4KByte,64KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer Cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner Cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes"
bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 7. "EPD0,Translation Table walk disable for TTBR0 as described in LPAE" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
if (((per.q(spr:0x34110))&0x400000000)==0x000000000)
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Registers"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 24. "HPD,Hierarchical Permission Disable" "No,Yes"
bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 20. "TBI,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,?..."
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR_ELx as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR_ELx as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR_ELx as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for TTBR_ELx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad spr:0x34202++0x00
line.quad 0x00 "TCR_EL2,Translation Control Registers"
bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible"
newline
bitfld.quad 0x00 42. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes"
bitfld.quad 0x00 41. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes"
newline
bitfld.quad 0x00 40. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 39. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 38. "TBI1,Top Byte ignored" "Used,Ignored"
bitfld.quad 0x00 37. "TBI0,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 36. "AS,ASID Size" "8 bit,16 bit"
bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,?..."
newline
bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 Granule size" "Reserved,16KByte,4KByte,64KByte"
bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 26.--27. "ORGN1,Outer Cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 24.--25. "IRGN1,Inner Cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes"
bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1"
newline
bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 7. "EPD0,Translation Table walk disable for TTBR0 as described in LPAE" "No,Yes"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
group.quad spr:0x36202++0x00
line.quad 0x00 "TCR_EL3,Translation Control Registers"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 24. "HPD,Hierarchical Permission Disable" "No,Yes"
bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled"
newline
bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled"
bitfld.quad 0x00 20. "TBI,Top Byte ignored" "Used,Ignored"
newline
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,?..."
bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..."
newline
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR_ELx as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR_ELx as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
newline
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR_ELx as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for TTBR_ELx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
if (((per.q(spr:0x34212))&0xC000)==0x00)
group.quad spr:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 2" "Disabled,Enabled"
bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 2" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "VS,VMID Size" "8-bit,16-bit"
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,VTTBR0_EL2 Granule size" "4KByte,64KByte,16KByte,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 6.--7. "SL0,Starting level of the VTCR_EL2 addressed region" "Level 2,Level 1,Level 0,?..."
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for VTTBR_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
elif (((per.q(spr:0x34212))&0xC000)==0xC000)
group.quad spr:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 2" "Disabled,Enabled"
bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 2" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "VS,VMID Size" "8-bit,16-bit"
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,VTTBR0_EL2 Granule size" "4KByte,64KByte,16KByte,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for VTTBR_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
group.quad spr:0x34212++0x00
line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register"
bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage 2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 2" "Disabled,Enabled"
bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 2" "Disabled,Enabled"
newline
bitfld.quad 0x00 19. "VS,VMID Size" "8-bit,16-bit"
bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,?..."
newline
bitfld.quad 0x00 14.--15. "TG0,VTTBR0_EL2 Granule size" "4KByte,64KByte,16KByte,?..."
bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable"
newline
bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable"
bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable"
newline
bitfld.quad 0x00 6.--7. "SL0,Starting level of the VTCR_EL2 addressed region" "Level 3,Level 2,Level 1,?..."
bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for VTTBR_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE,Reserved,Reserved,Reserved,Device-nGnRE,Reserved,Reserved,Reserved,Device-nGRE,Reserved,Reserved,Reserved,Device-GRE,?..."
newline
hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif (((per.q(spr:0x30740))&0x01)==0x00)
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Reserved,Normal Memory/Inner Write-through transient/W allocate,Normal Memory/Inner Write-through transient/R allocate,Normal Memory/Inner Write-through transient/RW allocate,Normal Memory/Inner Non-Cacheable,Normal Memory/Inner Write-back transient/W allocate,Normal Memory/Inner Write-back transient/R allocate,Normal Memory/Inner Write-back transient/RW allocate,Normal Memory/Inner Write-through non-transient,Normal Memory/Inner Write-through non-transient/W allocate,Normal Memory/Inner Write-through non-transient/R allocate,Normal Memory/Inner Write-through non-transient/RW allocate,Normal Memory/Inner Write-back non-transient,Normal Memory/Inner Write-back non-transient/W allocate,Normal Memory/Inner Write-back non-transient/R allocate,Normal Memory/Inner Write-back non-transient/RW allocate"
newline
hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address"
bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad spr:0x30740++0x00
line.quad 0x00 "PAR_EL1,Physical Address Register"
newline
newline
bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size/TTBR,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC/on TTW/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
tree.open "Memory Attribute Indirection Registers"
group.quad spr:0x30A20++0x00
line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.quad spr:0x35A20++0x00
line.quad 0x00 "MAIR_EL12,Memory Attribute Indirection Register"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.quad spr:0x34A20++0x00
line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.quad spr:0x36A20++0x00
line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register"
bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.quad spr:0x30A30++0x00
line.quad 0x00 "AMAIR_EL1,Auxiliary Memory Attribute Indirection Register"
group.quad spr:0x35A30++0x00
line.quad 0x00 "AMAIR_EL12,Auxiliary Memory Attribute Indirection Register"
group.quad spr:0x34A30++0x00
line.quad 0x00 "AMAIR_EL2,Auxiliary Memory Attribute Indirection Register"
group.quad spr:0x36A30++0x00
line.quad 0x00 "AMAIR_EL3,Auxiliary Memory Attribute Indirection Register"
tree.end
newline
group.quad spr:0x34300++0x00
line.quad 0x00 "DACR32_EL2,Domain Access Control Register"
bitfld.quad 0x00 30.--31. "D15,Domain 15 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 28.--29. "D14,Domain 14 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 26.--27. "D13,Domain 13 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 24.--25. "D12,Domain 12 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 22.--23. "D11,Domain 11 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 20.--21. "D10,Domain 10 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 18.--19. "D9,Domain 9 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 16.--17. "D8,Domain 8 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 14.--15. "D7,Domain 7 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 12.--13. "D6,Domain 6 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 10.--11. "D5,Domain 5 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 8.--9. "D4,Domain 4 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 6.--7. "D3,Domain 3 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 4.--5. "D2,Domain 2 access permission" "No access,Client,Reserved,Manager"
newline
bitfld.quad 0x00 2.--3. "D1,Domain 1 access permission" "No access,Client,Reserved,Manager"
bitfld.quad 0x00 0.--1. "D0,Domain 0 access permission" "No access,Client,Reserved,Manager"
tree.end
tree "Virtualization Extensions"
group.quad spr:0x34111++0x00
line.quad 0x00 "MDCR_EL2,Monitor Debug Configuration Register"
bitfld.quad 0x00 17. "HPMD,Hyp performance monitors disable" "No,Yes"
newline
bitfld.quad 0x00 11. "TDRA,Trap valid EL1 and EL0 access to debug ROM address Registers to EL2" "No trap,Trap"
bitfld.quad 0x00 10. "TDOSA,Trap valid accesses to OS-related debug Registers to EL2" "No trap,Trap"
bitfld.quad 0x00 9. "TDA,Trap valid Non-secure accesses to Debug Registers to EL2" "No trap,Trap"
newline
bitfld.quad 0x00 8. "TDE,Route debug exceptions from Non-secure EL1 and EL0 to EL2" "Disabled,Enabled"
bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "TPM,Trap Non-secure EL0 and EL1 accesses to Performance Monitors Registers that are not UNALLOCATED to EL2" "No trap,Trap"
newline
bitfld.quad 0x00 5. "TPMCR,Trap Non-secure EL0 and EL1 accesses to PMCR_EL0 to EL2" "No trap,Trap"
bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters accessible from non-secure EL0/EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (CORENAME()=="CORTEXA76")
group.quad spr:0x36131++0x00
line.quad 0x00 "MDCR_EL3,Monitor Debug Configuration Register"
bitfld.quad 0x00 21. "EPMAD,External debugger to Performance Monitor Registers access disable" "No,Yes"
bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint Registers disabled" "No,Yes"
bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 16. "SDD,Secure self-hosted invasive debug disable" "No,Yes"
bitfld.quad 0x00 10. "TDOSA,Trap valid accesses to OS-related debug Registers to EL3" "No trap,Trap"
bitfld.quad 0x00 9. "TDA,Trap valid Non-secure accesses to Debug Registers to EL3" "No trap,Trap"
newline
bitfld.quad 0x00 6. "TPM,Trap performance monitors accesses" "No trap,Trap"
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x36131++0x00
line.quad 0x00 "MDCR_EL3,Monitor Debug Configuration Register"
bitfld.quad 0x00 21. "EPMAD,External debugger to Performance Monitor Registers access disable" "No,Yes"
bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint Registers disabled" "No,Yes"
bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 16. "SDD,Secure self-hosted invasive debug disable" "No,Yes"
newline
bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy mode,Reserved,Disabled,Enabled"
bitfld.quad 0x00 10. "TDOSA,Trap valid accesses to OS-related debug Registers to EL3" "No trap,Trap"
bitfld.quad 0x00 9. "TDA,Trap valid Non-secure accesses to Debug Registers to EL3" "No trap,Trap"
newline
bitfld.quad 0x00 6. "TPM,Trap performance monitors accesses" "No trap,Trap"
endif
rgroup.quad spr:0x30012++0x00
line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register"
bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Reserved,Supported/16-bit evtCount,?..."
bitfld.quad 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.quad 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.quad 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.quad 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..."
bitfld.quad 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..."
tree.end
tree "Cache Control and Configuration"
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x30F00++0x00
line.quad 0x00 "CPUCFR_EL1,CPU Configuration Register (EL1)"
bitfld.quad 0x00 0.--1. "ECC,Indicates whether ECC is present or not" "Not present,Present,?..."
group.quad spr:0x30F27++0x00
line.quad 0x00 "CPUPWRCTLR_EL1,Power Control Register (EL1)"
bitfld.quad 0x00 7.--9. "WFE_RET_CTRL,CPU WFE retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
newline
bitfld.quad 0x00 4.--6. "WFI_RET_CTRL,CPU WFI retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.quad 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFI state" "Not requested,Requested"
rgroup.quad spr:0x33001++0x00
line.quad 0x00 "CTR_EL0,Cache Type Register"
bitfld.quad 0x00 28. "IDC,Data cache clean requirements for instruction to data coherence" "Required,Not required"
newline
bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 14.--15. "L1IP,Instruction cache policy" "Reserved,Reserved,Reserved,PIPT"
bitfld.quad 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30F00++0x00
line.quad 0x00 "CPUCFR_EL1,CPU Configuration Register (EL1)"
bitfld.quad 0x00 2. "SCU,Indicates whether the SCU is present or not" "Present,?..."
bitfld.quad 0x00 0.--1. "ECC,Indicates whether ECC is present or not" "Not present,Present,?..."
group.quad spr:0x30F27++0x00
line.quad 0x00 "CPUPWRCTLR_EL1,Power Control Register (EL1)"
bitfld.quad 0x00 10.--12. "SIMD_RET_CTRL,Advanced SIMD and floating-point retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.quad 0x00 7.--9. "WFE_RET_CTRL,CPU WFE retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
newline
bitfld.quad 0x00 4.--6. "WFI_RET_CTRL,CPU WFI retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.quad 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFI state" "Not requested,Requested"
rgroup.quad spr:0x33001++0x00
line.quad 0x00 "CTR_EL0,Cache Type Register"
bitfld.quad 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.quad 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.quad 0x00 14.--15. "L1IP,Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.quad 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
endif
if (((per.q(spr:0x32000))&0x0F)>=0x04)
group.quad spr:0x32000++0x00
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
elif (((per.q(spr:0x32000))&0xE)==0x02)
group.quad spr:0x32000++0x00
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,?..."
elif (((per.q(spr:0x32000))&0x01)==0x01)
group.quad spr:0x32000++0x00
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Reserved,Level 3,?..."
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
else
group.quad spr:0x32000++0x00
line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register"
bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
endif
rgroup.quad spr:0x31000++0x00
line.quad 0x00 "CCSIDR_EL1,Cache size and ID Register"
bitfld.quad 0x00 31. "WT,Write-Through" "Not Supported,?..."
bitfld.quad 0x00 30. "WB,Write-Back" "Not Supported,Supported"
newline
bitfld.quad 0x00 29. "RA,Read-Allocate" "Not Supported,Supported"
bitfld.quad 0x00 28. "WA,Write-Allocate" "Not Supported,Supported"
newline
hexmask.quad.word 0x00 13.--27. 1. 1. "SETS,Number of Sets"
hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOC,Associativity"
newline
bitfld.quad 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..."
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x31001++0x00
line.quad 0x00 "CLIDR_EL1,Cache Level ID Register"
bitfld.quad 0x00 30.--32. "ICB,Inner cache boundary" "Reserved,Reserved,L2 highest,L3 highest,?..."
newline
bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Not required,?..."
bitfld.quad 0x00 24.--26. "LOC,Level 3 of coherency" "Reserved,Reserved,Not implemented,Implemented,?..."
newline
bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "No cache,?..."
newline
newline
bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3 (per-core L2/cluster L3)" "All other,Reserved,Reserved,Reserved,Both present,?..."
newline
bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2 (per-core L2/cluster L2)" "All other,Reserved,Reserved,Reserved,Either present,?..."
bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate instruction/data,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x31001++0x00
line.quad 0x00 "CLIDR_EL1,Cache Level ID Register"
bitfld.quad 0x00 30.--32. "ICB,Inner cache boundary" "Reserved,L1 highest,L2 highest,L3 highest,?..."
newline
bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Not required,?..."
bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,No cache,L2 or L3 cache,L2 and L3 cache,?..."
newline
bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "No cache,?..."
newline
newline
bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3 (L2/L3 cache)" "Either not implemented,Reserved,Reserved,Reserved,Both implemented,?..."
newline
bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2 (L2/L3 cache)" "Both not implemented,Reserved,Reserved,Reserved,Either implemented,?..."
bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate instruction/data,?..."
endif
tree "Level 1 memory system"
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x36F00++0x00
line.quad 0x00 "IDATA0_EL3,Instruction Register 0"
rgroup.quad spr:0x36F01++0x00
line.quad 0x00 "IDATA1_EL3,Instruction Register 1"
rgroup.quad spr:0x36F02++0x00
line.quad 0x00 "IDATA2_EL3,Instruction Register 2"
rgroup.quad spr:0x36F10++0x00
line.quad 0x00 "DDATA0_EL3,Data Register 0"
rgroup.quad spr:0x36F11++0x00
line.quad 0x00 "DDATA1_EL3,Data Register 1"
rgroup.quad spr:0x36F12++0x00
line.quad 0x00 "DDATA2_EL3,Data Register 2"
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x36F00++0x00
line.quad 0x00 "CDBGDR0_EL3,Data Register 0"
rgroup.quad spr:0x36F01++0x00
line.quad 0x00 "CDBGDR1_EL3,Data Register 1"
rgroup.quad spr:0x36F02++0x00
line.quad 0x00 "CDBGDR2_EL3,Data Register 2"
wgroup.quad spr:0x16F20++0x00
line.quad 0x00 "CDBGDCT_EL3,Data Cache Tag Read Operation Register"
bitfld.quad 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.quad.byte 0x00 6.--13. 1. "SETIND,Set index"
wgroup.quad spr:0x16F21++0x00
line.quad 0x00 "CDBGICT_EL3,Instruction Cache Tag Read Operation Register"
bitfld.quad 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.quad.byte 0x00 6.--13. 1. "SETIND,Set index"
wgroup.quad spr:0x16F22++0x00
line.quad 0x00 "CDBGTT_EL3,TLB Tag Read Operation Register"
bitfld.quad 0x00 30.--31. "TLBW,TLB way" "0,1,2,3"
hexmask.quad.word 0x00 0.--8. 1. "TLBINDEX,TLB index"
wgroup.quad spr:0x16F40++0x00
line.quad 0x00 "CDBGDCD_EL3,Data Cache Data Read Operation Register"
bitfld.quad 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.quad.byte 0x00 6.--13. 1. "SETIND,Set index"
bitfld.quad 0x00 3.--5. "CDDO,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
wgroup.quad spr:0x16F41++0x00
line.quad 0x00 "CDBGICD_EL3,Instruction Cache Data Read Operation Register"
bitfld.quad 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.quad.byte 0x00 6.--13. 1. "SETIND,Set index"
bitfld.quad 0x00 2.--5. "CDDO,Cache doubleword data offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.quad spr:0x16F42++0x00
line.quad 0x00 "CDBGTD_EL3,TLB Data Read Operation Register"
bitfld.quad 0x00 30.--31. "TLBW,TLB way" "0,1,2,3"
hexmask.quad.word 0x00 0.--8. 1. "TLBINDEX,TLB index"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.quad spr:0x339C0++0x00
line.quad 0x00 "PMCR_EL0,Performance Monitors Control Register"
hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.quad 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
bitfld.quad 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "DP,Disable CCNT when event counting prohibited" "No,Yes"
bitfld.quad 0x00 4. "X,Export of events Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.quad spr:0x339C1++0x00
line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set Register"
bitfld.quad 0x00 31. "C,Enables the cycle counter Register" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "P5,Event counter PMN 5 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 4. "P4,Event counter PMN 4 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled"
group.quad spr:0x339C2++0x00
line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear Register"
bitfld.quad 0x00 31. "C,Disables the cycle counter Register" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
bitfld.quad 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
bitfld.quad 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
newline
bitfld.quad 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
bitfld.quad 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
bitfld.quad 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
group.quad spr:0x339C3++0x00
line.quad 0x00 "PMOVSCLR_EL0,Overflow Status Flags Clear Register"
eventfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
newline
eventfld.quad 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
eventfld.quad 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
eventfld.quad 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
newline
eventfld.quad 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
eventfld.quad 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
eventfld.quad 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
wgroup.quad spr:0x339C4++0x00
line.quad 0x00 "PMSWINC_EL0,Software Increment Register"
bitfld.quad 0x00 5. "P5,PMN5 software increment" "Disabled,Enabled"
bitfld.quad 0x00 4. "P4,PMN4 software increment" "Disabled,Enabled"
bitfld.quad 0x00 3. "P3,PMN3 software increment" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "P2,PMN2 software increment" "Disabled,Enabled"
bitfld.quad 0x00 1. "P1,PMN1 software increment" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,PMN0 software increment" "Disabled,Enabled"
group.quad spr:0x339C5++0x00
line.quad 0x00 "PMSELR_EL0,Event Counter Selection Register"
bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.open "Common Event Identification Registers"
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x339C6++0x00
line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register"
bitfld.quad 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,?..."
bitfld.quad 0x00 30. "CHAIN,Chain" "Reserved,Implemented"
bitfld.quad 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented"
newline
bitfld.quad 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Reserved,Implemented"
bitfld.quad 0x00 27. "INST_SPEC,Instruction speculatively executed" "Reserved,Implemented"
bitfld.quad 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented"
newline
bitfld.quad 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented"
bitfld.quad 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Reserved,Implemented"
bitfld.quad 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 22. "L2D_CACHE,Level 2 data cache access" "Reserved,Implemented"
bitfld.quad 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Reserved,Implemented"
bitfld.quad 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Reserved,Implemented"
newline
bitfld.quad 0x00 19. "MEM_ACCESS,Data memory access" "Reserved,Implemented"
bitfld.quad 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Reserved,Implemented"
bitfld.quad 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented"
newline
bitfld.quad 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented"
bitfld.quad 0x00 15. "UNALIGNED_LDST_RETIRED,UNALIGNED_LDST_RETIRED" "Not implemented,?..."
bitfld.quad 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,?..."
newline
bitfld.quad 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,?..."
bitfld.quad 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,?..."
bitfld.quad 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented"
newline
bitfld.quad 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented"
bitfld.quad 0x00 9. "EXC_TAKEN,Exception taken" "Reserved,Implemented"
bitfld.quad 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Reserved,Implemented"
newline
bitfld.quad 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,?..."
bitfld.quad 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,?..."
bitfld.quad 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 4. "L1D_CACHE,Level 1 data cache access" "Reserved,Implemented"
bitfld.quad 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Reserved,Implemented"
bitfld.quad 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Reserved,Implemented"
bitfld.quad 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented"
rgroup.quad spr:0x339C7++0x00
line.quad 0x00 "PMCEID1_EL0,Common Event Identification Register"
bitfld.quad 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Reserved,Implemented"
bitfld.quad 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Reserved,Implemented"
bitfld.quad 0x00 21. "ITLB_WALK,Access to instruction TLB with at least one translation table walk" "Reserved,Implemented"
newline
bitfld.quad 0x00 20. "DTLB_WALK,Attributable data or unified TLB access with at least one translation table walk" "Reserved,Implemented"
bitfld.quad 0x00 17. "REMOTE_ACCESS,Attributable access to another socket in a multi-socket system" "Reserved,Implemented"
bitfld.quad 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Reserved,Implemented"
newline
bitfld.quad 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Reserved,Implemented"
bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data cache access" "Reserved,Implemented"
bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data cache refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented"
bitfld.quad 0x00 6. "L1I_TLB,Attributable Level 1 data instruction TLB access" "Reserved,Implemented"
bitfld.quad 0x00 5. "L1D_TLB,Attributable Level 1 data or unified TLB access" "Reserved,Implemented"
newline
bitfld.quad 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Reserved,Implemented"
bitfld.quad 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Reserved,Implemented"
bitfld.quad 0x00 2. "BR_MIS_PRED_RETIRED,Mispredicted branch" "Reserved,Implemented"
newline
bitfld.quad 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Reserved,Implemented"
bitfld.quad 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Reserved,Implemented"
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x339C6++0x00
line.quad 0x00 "PMCEID0_EL0,Common Event Identification Register"
bitfld.quad 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,?..."
bitfld.quad 0x00 30. "CHAIN,Chain" "Reserved,Implemented"
bitfld.quad 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented"
newline
bitfld.quad 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Reserved,Implemented"
bitfld.quad 0x00 27. "INST_SPEC,Instruction speculatively executed" "Reserved,Implemented"
bitfld.quad 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented"
newline
bitfld.quad 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented"
bitfld.quad 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.quad 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 22. "L2D_CACHE,Level 2 data cache access" "Not implemented,Implemented"
bitfld.quad 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Reserved,Implemented"
bitfld.quad 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Reserved,Implemented"
newline
bitfld.quad 0x00 19. "MEM_ACCESS,Data memory access" "Reserved,Implemented"
bitfld.quad 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Reserved,Implemented"
bitfld.quad 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented"
newline
bitfld.quad 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented"
bitfld.quad 0x00 15. "UNALIGNED_LDST_RETIRED,UNALIGNED_LDST_RETIRED" "Reserved,Implemented"
bitfld.quad 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Reserved,Implemented"
newline
bitfld.quad 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Reserved,Implemented"
bitfld.quad 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Reserved,Implemented"
bitfld.quad 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented"
newline
bitfld.quad 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented"
bitfld.quad 0x00 9. "EXC_TAKEN,Exception taken" "Reserved,Implemented"
bitfld.quad 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Reserved,Implemented"
newline
bitfld.quad 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Reserved,Implemented"
bitfld.quad 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Reserved,Implemented"
bitfld.quad 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 4. "L1D_CACHE,Level 1 data cache access" "Reserved,Implemented"
bitfld.quad 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Reserved,Implemented"
bitfld.quad 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Reserved,Implemented"
bitfld.quad 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented"
rgroup.quad spr:0x339C7++0x00
line.quad 0x00 "PMCEID1_EL0,Common Event Identification Register"
bitfld.quad 0x00 24. "REMOTE_ACCESS_RD,Access to another socket in a multi-socket system" "Reserved,Implemented"
bitfld.quad 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Reserved,Implemented"
bitfld.quad 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Reserved,Implemented"
newline
bitfld.quad 0x00 21. "ITLB_WALK,Access to instruction TLB with at least one translation table walk" "Reserved,Implemented"
bitfld.quad 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Reserved,Implemented"
bitfld.quad 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,?..."
newline
bitfld.quad 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Reserved,Implemented"
bitfld.quad 0x00 14. "L2I_TLB_REFILL,Attributable Level 2 instruction TLB refill" "Not implemented,?..."
bitfld.quad 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Not implemented,?..."
bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented"
bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented"
newline
bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented"
bitfld.quad 0x00 8. "L2I_CACHE_REFILL,Attributable Level 2 instruction cache refill" "Not implemented,?..."
bitfld.quad 0x00 7. "L2I_CACHE,Attributable Level 2 instruction cache access" "Not implemented,?..."
newline
bitfld.quad 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Reserved,Implemented"
bitfld.quad 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Reserved,Implemented"
bitfld.quad 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Reserved,Implemented"
newline
bitfld.quad 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Reserved,Implemented"
bitfld.quad 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Reserved,Implemented"
bitfld.quad 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Reserved,Implemented"
newline
bitfld.quad 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Reserved,Implemented"
endif
tree.end
newline
group.quad spr:0x339D0++0x00
line.quad 0x00 "PMCCNTR_EL0,Performance Monitors Cycle Counter"
if (((per.q(spr:0x339C5))&0x1F)==0x1F)
group.quad spr:0x339D1++0x00
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
elif (((per.q(spr:0x339C5))&0x1F)<=0x05)
group.quad spr:0x339D1++0x00
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
bitfld.quad 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event to count"
else
rgroup.quad spr:0x339D1++0x00
line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitor Event Type Register"
endif
group.quad spr:0x339D2++0x00
line.quad 0x00 "PMXEVCNTR_EL0,Selected Event Counter Register"
group.quad spr:0x339E0++0x00
line.quad 0x00 "PMUSERENR_EL0,User Enable Register"
bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.quad 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "EN,EL0 access enable bit" "Disabled,Enabled"
group.quad spr:0x309E1++0x00
line.quad 0x00 "PMINTENSET_EL1,Interrupt Enable Set Register"
bitfld.quad 0x00 31. "C,CCNT Overflow Interrupt Request Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.quad spr:0x309E2++0x00
line.quad 0x00 "PMINTENCLR_EL1,Interrupt Enable Clear Register"
eventfld.quad 0x00 31. "C,CCNT Overflow Interrupt Request Enable" "Disabled,Enabled"
newline
eventfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
eventfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
eventfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
newline
eventfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
eventfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
eventfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.quad spr:0x339E3++0x00
line.quad 0x00 "PMOVSSET_EL0,Overflow Status Flags Set Register"
bitfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
newline
bitfld.quad 0x00 5. "P5,PMN5 Overflow" "No overflow,Overflow"
bitfld.quad 0x00 4. "P4,PMN4 Overflow" "No overflow,Overflow"
bitfld.quad 0x00 3. "P3,PMN3 Overflow" "No overflow,Overflow"
newline
bitfld.quad 0x00 2. "P2,PMN2 Overflow" "No overflow,Overflow"
bitfld.quad 0x00 1. "P1,PMN1 Overflow" "No overflow,Overflow"
bitfld.quad 0x00 0. "P0,PMN0 Overflow" "No overflow,Overflow"
group.quad spr:(0x33E80+0x0)++0x00
line.quad 0x00 "PMEVCNTR0_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x1)++0x00
line.quad 0x00 "PMEVCNTR1_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x2)++0x00
line.quad 0x00 "PMEVCNTR2_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x3)++0x00
line.quad 0x00 "PMEVCNTR3_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x4)++0x00
line.quad 0x00 "PMEVCNTR4_EL0,Event Counter Register"
group.quad spr:(0x33E80+0x5)++0x00
line.quad 0x00 "PMEVCNTR5_EL0,Event Counter Register"
group.quad spr:(0x33EC0+0x0)++0x00
line.quad 0x00 "PMEVTYPER0_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x1)++0x00
line.quad 0x00 "PMEVTYPER1_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x2)++0x00
line.quad 0x00 "PMEVTYPER2_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x3)++0x00
line.quad 0x00 "PMEVTYPER3_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x4)++0x00
line.quad 0x00 "PMEVTYPER4_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:(0x33EC0+0x5)++0x00
line.quad 0x00 "PMEVTYPER5_EL0,Event Counter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.quad spr:0x33EF7++0x00
line.quad 0x00 "PMCCFILTR_EL0,Event Type and Cycle Counter Filter Register"
bitfld.quad 0x00 31. "P,Count events in EL1" "No,Yes"
bitfld.quad 0x00 30. "U,Count events in EL0" "No,Yes"
bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.quad spr:0x33E00++0x00
line.quad 0x00 "CNTFRQ_EL0,Counter-timer Frequency Register"
rgroup.quad spr:0x33E01++0x00
line.quad 0x00 "CNTPCT_EL0,Counter-timer Physical Count Register"
rgroup.quad spr:0x33E02++0x00
line.quad 0x00 "CNTVCT_EL0,Counter-timer Virtual Count Register"
group.quad spr:0x34E03++0x00
line.quad 0x00 "CNTVOFF_EL2,Counter-timer Virtual Offset Register"
group.quad spr:0x30E10++0x00
line.quad 0x00 "CNTKCTL_EL1,Counter-timer Kernel Control Register"
bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer Registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer Registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
newline
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency Register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency Register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
group.quad spr:0x35E10++0x00
line.quad 0x00 "CNTKCTL_EL12,Counter-timer Kernel Control Register"
bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer Registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer Registers are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
newline
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency Register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency Register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled"
if (((per.q(spr:0x34110))&0x400000000)==0x000000000)
group.quad spr:0x34E10++0x00
line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control Register"
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL1PCEN,Controls whether the physical timer Registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
else
group.quad spr:0x34E10++0x00
line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control Register"
bitfld.quad 0x00 11. "EL1PTEN,Physical timer Register accessing instructions are accessible from Non-secure EL1 and EL0" "Not accessible,Accessible"
bitfld.quad 0x00 10. "EL1PCTEN,Physical counter is accessible from Non-secure EL1 and EL0" "Not accessible,Accessible"
bitfld.quad 0x00 9. "EL0PTEN,Physical timer Register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible"
bitfld.quad 0x00 8. "EL0VTEN,Virtual timer Register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible"
newline
bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0"
bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
bitfld.quad 0x00 1. "EL0VCTEN,Virtual counter Register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible"
newline
bitfld.quad 0x00 0. "EL0PCTEN,Physical counter is accessible from Non-secure EL0 modes" "Not accessible,Accessible"
endif
group.quad spr:0x33E20++0x00
line.quad 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue Register"
group.quad spr:0x35E20++0x00
line.quad 0x00 "CNTP_TVAL_EL02,Counter-timer Physical Timer TimerValue Register"
if (((per.q(spr:0x33E21))&0x01)==0x01)
group.quad spr:0x33E21++0x00
line.quad 0x00 "CNTP_CTL_EL0,Counter-timer Physical Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x33E21++0x00
line.quad 0x00 "CNTP_CTL_EL0,Counter-timer Physical Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
if (((per.q(spr:0x35E21))&0x01)==0x01)
group.quad spr:0x35E21++0x00
line.quad 0x00 "CNTP_CTL_EL02,Counter-timer Physical Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x35E21++0x00
line.quad 0x00 "CNTP_CTL_EL02,Counter-timer Physical Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad spr:0x33E22++0x00
line.quad 0x00 "CNTP_CVAL_EL0,Counter-timer Physical Timer CompareValue Register"
group.quad spr:0x35E22++0x00
line.quad 0x00 "CNTP_CVAL_EL02,Counter-timer Physical Timer CompareValue Register"
group.quad spr:0x33E30++0x00
line.quad 0x00 "CNTV_TVAL_EL0,Counter-timer Virtual Timer TimerValue Register"
group.quad spr:0x35E30++0x00
line.quad 0x00 "CNTV_TVAL_EL02,Counter-timer Virtual Timer TimerValue Register"
if (((per.q(spr:0x33E31))&0x01)==0x01)
group.quad spr:0x33E31++0x00
line.quad 0x00 "CNTV_CTL_EL0,Counter-timer Virtual Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x33E31++0x00
line.quad 0x00 "CNTV_CTL_EL0,Counter-timer Virtual Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
if (((per.q(spr:0x35E31))&0x01)==0x01)
group.quad spr:0x35E31++0x00
line.quad 0x00 "CNTV_CTL_EL02,Counter-timer Virtual Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x35E31++0x00
line.quad 0x00 "CNTV_CTL_EL02,Counter-timer Virtual Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad spr:0x33E32++0x00
line.quad 0x00 "CNTV_CVAL_EL0,Counter-timer Virtual Timer CompareValue Register"
group.quad spr:0x35E32++0x00
line.quad 0x00 "CNTV_CVAL_EL02,Counter-timer Virtual Timer CompareValue Register"
group.quad spr:0x34E20++0x00
line.quad 0x00 "CNTHP_TVAL_EL2,Counter-timer Hypervisor Physical Timer TimerValue Register"
if (((per.q(spr:0x34E21))&0x01)==0x01)
group.quad spr:0x34E21++0x00
line.quad 0x00 "CNTHP_CTL_EL2,Counter-timer Hypervisor Physical Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x34E21++0x00
line.quad 0x00 "CNTHP_CTL_EL2,Counter-timer Hypervisor Physical Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad spr:0x34E22++0x00
line.quad 0x00 "CNTHP_CVAL_EL2,Counter-timer Hypervisor Physical Timer CompareValue Register"
group.quad spr:0x34E30++0x00
line.quad 0x00 "CNTHV_TVAL_EL2,Counter-timer Hypervisor Virtual Timer Value Register"
if (((per.q(spr:0x34E31))&0x01)==0x01)
group.quad spr:0x34E31++0x00
line.quad 0x00 "CNTHV_CTL_EL2,Counter-timer Hypervisor Virtual Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x34E31++0x00
line.quad 0x00 "CNTHV_CTL_EL2,Counter-timer Hypervisor Virtual Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad spr:0x34E32++0x00
line.quad 0x00 "CNTHV_CVAL_EL2,Counter-timer Hypervisor Virtual Timer CompareValue Register"
group.quad spr:0x37E20++0x00
line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical Secure Timer TimerValue Register"
if (((per.q(spr:0x37E21))&0x01)==0x01)
group.quad spr:0x37E21++0x00
line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control Register"
rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.quad spr:0x37E21++0x00
line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control Register"
newline
bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad spr:0x37E22++0x00
line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue Register"
tree.end
tree "Generic Interrupt Controller System Registers"
tree "AArch64 GIC Physical CPU Interface System Registers"
tree.open "Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICC_AP0R0_EL1,Active Priorities 0 Register 0"
bitfld.quad 0x00 31. "P31,Priority 31" "0,1"
bitfld.quad 0x00 30. "P30,Priority 30" "0,1"
bitfld.quad 0x00 29. "P29,Priority 29" "0,1"
bitfld.quad 0x00 28. "P28,Priority 28" "0,1"
newline
bitfld.quad 0x00 27. "P27,Priority 27" "0,1"
bitfld.quad 0x00 26. "P26,Priority 26" "0,1"
bitfld.quad 0x00 25. "P25,Priority 25" "0,1"
bitfld.quad 0x00 24. "P24,Priority 24" "0,1"
newline
bitfld.quad 0x00 23. "P23,Priority 23" "0,1"
bitfld.quad 0x00 22. "P22,Priority 22" "0,1"
bitfld.quad 0x00 21. "P21,Priority 21" "0,1"
bitfld.quad 0x00 20. "P20,Priority 20" "0,1"
newline
bitfld.quad 0x00 19. "P19,Priority 19" "0,1"
bitfld.quad 0x00 18. "P18,Priority 18" "0,1"
bitfld.quad 0x00 17. "P17,Priority 17" "0,1"
bitfld.quad 0x00 16. "P16,Priority 16" "0,1"
newline
bitfld.quad 0x00 15. "P15,Priority 15" "0,1"
bitfld.quad 0x00 14. "P14,Priority 14" "0,1"
bitfld.quad 0x00 13. "P13,Priority 13" "0,1"
bitfld.quad 0x00 12. "P12,Priority 12" "0,1"
newline
bitfld.quad 0x00 11. "P11,Priority 11" "0,1"
bitfld.quad 0x00 10. "P10,Priority 10" "0,1"
bitfld.quad 0x00 9. "P9,Priority 9" "0,1"
bitfld.quad 0x00 8. "P8,Priority 8" "0,1"
newline
bitfld.quad 0x00 7. "P7,Priority 7" "0,1"
bitfld.quad 0x00 6. "P6,Priority 6" "0,1"
bitfld.quad 0x00 5. "P5,Priority 5" "0,1"
bitfld.quad 0x00 4. "P4,Priority 4" "0,1"
newline
bitfld.quad 0x00 3. "P3,Priority 3" "0,1"
bitfld.quad 0x00 2. "P2,Priority 2" "0,1"
bitfld.quad 0x00 1. "P1,Priority 1" "0,1"
bitfld.quad 0x00 0. "P0,Priority 0" "0,1"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICC_AP1R0_EL1,Active Priorities 1 Register 0"
bitfld.quad 0x00 31. "P31,Priority 31" "0,1"
bitfld.quad 0x00 30. "P30,Priority 30" "0,1"
bitfld.quad 0x00 29. "P29,Priority 29" "0,1"
bitfld.quad 0x00 28. "P28,Priority 28" "0,1"
newline
bitfld.quad 0x00 27. "P27,Priority 27" "0,1"
bitfld.quad 0x00 26. "P26,Priority 26" "0,1"
bitfld.quad 0x00 25. "P25,Priority 25" "0,1"
bitfld.quad 0x00 24. "P24,Priority 24" "0,1"
newline
bitfld.quad 0x00 23. "P23,Priority 23" "0,1"
bitfld.quad 0x00 22. "P22,Priority 22" "0,1"
bitfld.quad 0x00 21. "P21,Priority 21" "0,1"
bitfld.quad 0x00 20. "P20,Priority 20" "0,1"
newline
bitfld.quad 0x00 19. "P19,Priority 19" "0,1"
bitfld.quad 0x00 18. "P18,Priority 18" "0,1"
bitfld.quad 0x00 17. "P17,Priority 17" "0,1"
bitfld.quad 0x00 16. "P16,Priority 16" "0,1"
newline
bitfld.quad 0x00 15. "P15,Priority 15" "0,1"
bitfld.quad 0x00 14. "P14,Priority 14" "0,1"
bitfld.quad 0x00 13. "P13,Priority 13" "0,1"
bitfld.quad 0x00 12. "P12,Priority 12" "0,1"
newline
bitfld.quad 0x00 11. "P11,Priority 11" "0,1"
bitfld.quad 0x00 10. "P10,Priority 10" "0,1"
bitfld.quad 0x00 9. "P9,Priority 9" "0,1"
bitfld.quad 0x00 8. "P8,Priority 8" "0,1"
newline
bitfld.quad 0x00 7. "P7,Priority 7" "0,1"
bitfld.quad 0x00 6. "P6,Priority 6" "0,1"
bitfld.quad 0x00 5. "P5,Priority 5" "0,1"
bitfld.quad 0x00 4. "P4,Priority 4" "0,1"
newline
bitfld.quad 0x00 3. "P3,Priority 3" "0,1"
bitfld.quad 0x00 2. "P2,Priority 2" "0,1"
bitfld.quad 0x00 1. "P1,Priority 1" "0,1"
bitfld.quad 0x00 0. "P0,Priority 0" "0,1"
tree.end
newline
if (((per.q(spr:0x30CB6))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Alternate SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff(3:1),All PEs/not self"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
newline
else
wgroup.quad spr:0x30CB6++0x00
line.quad 0x00 "ICC_ASGI1R_EL1,Alternate SGI Generation Register 1"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff(3:1),All PEs/not self"
newline
bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
endif
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICC_BPR0_EL1,Binary Point Register 0"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICC_BPR1_EL1,Binary Point Register 1"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control (Non-secure/Secure)" "Reserved,Reserved,---/[7:3]-[2:0],[7:3]-[2:0]/[7:4]-[3:0],[7:4]-[3:0]/[7:5]-[4:0],[7:5]-[4:0]/[7:6]-[5:0],[7:6]-[5:0]/[7]-[6:0],[7]-[6:0]/No preemption-[7:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICC_CTLR_EL1,Interrupt Control Registers for EL1"
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Valid"
rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,?..."
rbitfld.quad 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..."
rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
newline
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "EOIMODE,Indicates whether ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality" "Both,Priority drop"
bitfld.quad 0x00 0. "CBPR,Common Binary Point Register" "Separate,Common"
group.quad spr:0x36CC4++0x00
line.quad 0x00 "ICC_CTLR_EL3,Interrupt Control Registers for EL3"
rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Reserved,Not supported"
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Valid"
rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,?..."
rbitfld.quad 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
rbitfld.quad 0x00 5. "RM,Routing Modifier" "Normal,?..."
newline
bitfld.quad 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop"
newline
bitfld.quad 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Priority drop/Deactivation,Priority drop"
newline
bitfld.quad 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Priority drop/Deactivation,Priority drop"
newline
bitfld.quad 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate Registers,Same Register"
newline
bitfld.quad 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate Registers,Same Register"
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICC_DIR_EL1,Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICC_EOIR0_EL1,End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0_EL1 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICC_EOIR1_EL1,End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1_EL1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICC_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICC_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
newline
hgroup.quad spr:0x30C80++0x00
hide.quad 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0"
in
hgroup.quad spr:0x30CC0++0x00
hide.quad 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1"
in
newline
group.quad spr:0x30CC6++0x00
line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Group 0 Enable Register (EL1)"
bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad spr:0x30CC7++0x00
line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Group 1 Enable Register (EL1)"
bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled"
group.quad spr:0x36CC7++0x00
line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)"
bitfld.quad 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.quad 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.quad spr:0x30460++0x00
line.quad 0x00 "ICC_PMR_EL1,Priority Mask Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad spr:0x30CB3++0x00
line.quad 0x00 "ICC_RPR_EL1,Running Priority Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
if (((per.q(spr:0x30CB7))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff(3:1),All PEs/not self"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
else
wgroup.quad spr:0x30CB7++0x00
line.quad 0x00 "ICC_SGI0R_EL1,SGI Generation Register 0"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff3/2/1,All PEs/not self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
if (((per.q(spr:0x30CB5))&0x10000000000)==0x00)
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff(3:1),All PEs/not self"
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
newline
bitfld.quad 0x00 24.--27. "INTID,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
else
wgroup.quad spr:0x30CB5++0x00
line.quad 0x00 "ICC_SGI1R_EL1,SGI Generation Register 1"
newline
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Target list/Aff3/2/1,All PEs/not self"
newline
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.quad spr:0x30CC5++0x00
line.quad 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
rbitfld.quad 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
group.quad spr:0x34C95++0x00
line.quad 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2"
rbitfld.quad 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Reserved,Enabled"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
rbitfld.quad 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
group.quad spr:0x36CC5++0x00
line.quad 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3"
rbitfld.quad 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Reserved,Enabled"
bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
rbitfld.quad 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
tree.end
tree "AArch64 GIC Virtual CPU Interface System Registers"
tree.open "Active Priorities Registers"
group.quad spr:0x30C84++0x00
line.quad 0x00 "ICV_AP0R0_EL1,Active Priorities Group 0 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Priority 31" "0,1"
bitfld.quad 0x00 30. "P30,Priority 30" "0,1"
bitfld.quad 0x00 29. "P29,Priority 29" "0,1"
bitfld.quad 0x00 28. "P28,Priority 28" "0,1"
newline
bitfld.quad 0x00 27. "P27,Priority 27" "0,1"
bitfld.quad 0x00 26. "P26,Priority 26" "0,1"
bitfld.quad 0x00 25. "P25,Priority 25" "0,1"
bitfld.quad 0x00 24. "P24,Priority 24" "0,1"
newline
bitfld.quad 0x00 23. "P23,Priority 23" "0,1"
bitfld.quad 0x00 22. "P22,Priority 22" "0,1"
bitfld.quad 0x00 21. "P21,Priority 21" "0,1"
bitfld.quad 0x00 20. "P20,Priority 20" "0,1"
newline
bitfld.quad 0x00 19. "P19,Priority 19" "0,1"
bitfld.quad 0x00 18. "P18,Priority 18" "0,1"
bitfld.quad 0x00 17. "P17,Priority 17" "0,1"
bitfld.quad 0x00 16. "P16,Priority 16" "0,1"
newline
bitfld.quad 0x00 15. "P15,Priority 15" "0,1"
bitfld.quad 0x00 14. "P14,Priority 14" "0,1"
bitfld.quad 0x00 13. "P13,Priority 13" "0,1"
bitfld.quad 0x00 12. "P12,Priority 12" "0,1"
newline
bitfld.quad 0x00 11. "P11,Priority 11" "0,1"
bitfld.quad 0x00 10. "P10,Priority 10" "0,1"
bitfld.quad 0x00 9. "P9,Priority 9" "0,1"
bitfld.quad 0x00 8. "P8,Priority 8" "0,1"
newline
bitfld.quad 0x00 7. "P7,Priority 7" "0,1"
bitfld.quad 0x00 6. "P6,Priority 6" "0,1"
bitfld.quad 0x00 5. "P5,Priority 5" "0,1"
bitfld.quad 0x00 4. "P4,Priority 4" "0,1"
newline
bitfld.quad 0x00 3. "P3,Priority 3" "0,1"
bitfld.quad 0x00 2. "P2,Priority 2" "0,1"
bitfld.quad 0x00 1. "P1,Priority 1" "0,1"
bitfld.quad 0x00 0. "P0,Priority 0" "0,1"
group.quad spr:0x30C90++0x00
line.quad 0x00 "ICV_AP1R0_EL1,Active Priorities Group 1 Register 0 (EL1)"
bitfld.quad 0x00 31. "P31,Priority 31" "0,1"
bitfld.quad 0x00 30. "P30,Priority 30" "0,1"
bitfld.quad 0x00 29. "P29,Priority 29" "0,1"
bitfld.quad 0x00 28. "P28,Priority 28" "0,1"
newline
bitfld.quad 0x00 27. "P27,Priority 27" "0,1"
bitfld.quad 0x00 26. "P26,Priority 26" "0,1"
bitfld.quad 0x00 25. "P25,Priority 25" "0,1"
bitfld.quad 0x00 24. "P24,Priority 24" "0,1"
newline
bitfld.quad 0x00 23. "P23,Priority 23" "0,1"
bitfld.quad 0x00 22. "P22,Priority 22" "0,1"
bitfld.quad 0x00 21. "P21,Priority 21" "0,1"
bitfld.quad 0x00 20. "P20,Priority 20" "0,1"
newline
bitfld.quad 0x00 19. "P19,Priority 19" "0,1"
bitfld.quad 0x00 18. "P18,Priority 18" "0,1"
bitfld.quad 0x00 17. "P17,Priority 17" "0,1"
bitfld.quad 0x00 16. "P16,Priority 16" "0,1"
newline
bitfld.quad 0x00 15. "P15,Priority 15" "0,1"
bitfld.quad 0x00 14. "P14,Priority 14" "0,1"
bitfld.quad 0x00 13. "P13,Priority 13" "0,1"
bitfld.quad 0x00 12. "P12,Priority 12" "0,1"
newline
bitfld.quad 0x00 11. "P11,Priority 11" "0,1"
bitfld.quad 0x00 10. "P10,Priority 10" "0,1"
bitfld.quad 0x00 9. "P9,Priority 9" "0,1"
bitfld.quad 0x00 8. "P8,Priority 8" "0,1"
newline
bitfld.quad 0x00 7. "P7,Priority 7" "0,1"
bitfld.quad 0x00 6. "P6,Priority 6" "0,1"
bitfld.quad 0x00 5. "P5,Priority 5" "0,1"
bitfld.quad 0x00 4. "P4,Priority 4" "0,1"
newline
bitfld.quad 0x00 3. "P3,Priority 3" "0,1"
bitfld.quad 0x00 2. "P2,Priority 2" "0,1"
bitfld.quad 0x00 1. "P1,Priority 1" "0,1"
bitfld.quad 0x00 0. "P0,Priority 0" "0,1"
tree.end
newline
group.quad spr:0x30C83++0x00
line.quad 0x00 "ICV_BPR0_EL1,Binary Point Register 0 (EL1)"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.quad spr:0x30CC3++0x00
line.quad 0x00 "ICV_BPR1_EL1,Binary Point Register 1 (EL1)"
bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control (Non-secure/Secure)" "Reserved,Reserved,---/[7:3]-[2:0],[7:3]-[2:0]/[7:4]-[3:0],[7:4]-[3:0]/[7:5]-[4:0],[7:5]-[4:0]/[7:6]-[5:0],[7:6]-[5:0]/[7]-[6:0],[7]-[6:0]/No preemption-[7:0]"
group.quad spr:0x30CC4++0x00
line.quad 0x00 "ICV_CTLR_EL1,Control Register (EL1)"
rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Valid"
rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported,?..."
rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
newline
rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 1. "VEOIMODE,Indicates whether ICV_EOIR0 and ICV_EOIR1 provide both priority drop and interrupt deactivation functionality" "Both,Priority drop"
bitfld.quad 0x00 0. "VCBPR,Common Binary Point Register" "Separate,Common"
wgroup.quad spr:0x30CB1++0x00
line.quad 0x00 "ICV_DIR_EL1,Deactivate Interrupt Register"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the virtual interrupt to be deactivated"
wgroup.quad spr:0x30C81++0x00
line.quad 0x00 "ICV_EOIR0_EL1,End Of Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICV_IAR0_EL1 access"
wgroup.quad spr:0x30CC1++0x00
line.quad 0x00 "ICV_EOIR1_EL1,End Of Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICV_IAR1_EL1 access"
rgroup.quad spr:0x30C82++0x00
line.quad 0x00 "ICV_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.quad spr:0x30CC2++0x00
line.quad 0x00 "ICV_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.quad SPR:0x30C80++0x00
line.quad 0x00 "ICV_IAR0_EL1,Interrupt Controller Interrupt Acknowledge Register 0"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt, if that interrupt is observable at the currentSecurity state and Exception level"
rgroup.quad SPR:0x30CC0++0x00
line.quad 0x00 "ICV_IAR1_EL1,Interrupt Controller Interrupt Acknowledge Register 1"
hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt, if that interrupt is observable at the currentSecurity state and Exception level"
group.quad spr:0x30CC6++0x00
line.quad 0x00 "ICV_IGRPEN0_EL1,Interrupt Group 0 Enable Register"
bitfld.quad 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.quad spr:0x30CC7++0x00
line.quad 0x00 "ICV_IGRPEN1_EL1,Interrupt Group 1 Enable Register"
bitfld.quad 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled"
group.quad spr:0x30460++0x00
line.quad 0x00 "ICV_PMR_EL1,Priority Mask Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.quad spr:0x30CB3++0x00
line.quad 0x00 "ICV_RPR_EL1,Running Priority Register"
hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
tree.end
tree "AArch64 Virtual Interface Control System Register Summary"
tree.open "Hyp Active Priorities Registers"
group.quad spr:0x34C80++0x00
line.quad 0x00 "ICH_AP0R0_EL2,Hyp Active Priorities Group 0 Register 0"
bitfld.quad 0x00 31. "P31,Active Priority 31" "0,1"
bitfld.quad 0x00 30. "P30,Active Priority 30" "0,1"
bitfld.quad 0x00 29. "P29,Active Priority 29" "0,1"
bitfld.quad 0x00 28. "P28,Active Priority 28" "0,1"
newline
bitfld.quad 0x00 27. "P27,Active Priority 27" "0,1"
bitfld.quad 0x00 26. "P26,Active Priority 26" "0,1"
bitfld.quad 0x00 25. "P25,Active Priority 25" "0,1"
bitfld.quad 0x00 24. "P24,Active Priority 24" "0,1"
newline
bitfld.quad 0x00 23. "P23,Active Priority 23" "0,1"
bitfld.quad 0x00 22. "P22,Active Priority 22" "0,1"
bitfld.quad 0x00 21. "P21,Active Priority 21" "0,1"
bitfld.quad 0x00 20. "P20,Active Priority 20" "0,1"
newline
bitfld.quad 0x00 19. "P19,Active Priority 19" "0,1"
bitfld.quad 0x00 18. "P18,Active Priority 18" "0,1"
bitfld.quad 0x00 17. "P17,Active Priority 17" "0,1"
bitfld.quad 0x00 16. "P16,Active Priority 16" "0,1"
newline
bitfld.quad 0x00 15. "P15,Active Priority 15" "0,1"
bitfld.quad 0x00 14. "P14,Active Priority 14" "0,1"
bitfld.quad 0x00 13. "P13,Active Priority 13" "0,1"
bitfld.quad 0x00 12. "P12,Active Priority 12" "0,1"
newline
bitfld.quad 0x00 11. "P11,Active Priority 11" "0,1"
bitfld.quad 0x00 10. "P10,Active Priority 10" "0,1"
bitfld.quad 0x00 9. "P9,Active Priority 9" "0,1"
bitfld.quad 0x00 8. "P8,Active Priority 8" "0,1"
newline
bitfld.quad 0x00 7. "P7,Active Priority 7" "0,1"
bitfld.quad 0x00 6. "P6,Active Priority 6" "0,1"
bitfld.quad 0x00 5. "P5,Active Priority 5" "0,1"
bitfld.quad 0x00 4. "P4,Active Priority 4" "0,1"
newline
bitfld.quad 0x00 3. "P3,Active Priority 3" "0,1"
bitfld.quad 0x00 2. "P2,Active Priority 2" "0,1"
bitfld.quad 0x00 1. "P1,Active Priority 1" "0,1"
bitfld.quad 0x00 0. "P0,Active Priority 0" "0,1"
group.quad spr:0x34C90++0x00
line.quad 0x00 "ICH_AP1R0_EL2,Hyp Active Priorities Group 1 Register 0"
bitfld.quad 0x00 31. "P31,Active Priority 31" "0,1"
bitfld.quad 0x00 30. "P30,Active Priority 30" "0,1"
bitfld.quad 0x00 29. "P29,Active Priority 29" "0,1"
bitfld.quad 0x00 28. "P28,Active Priority 28" "0,1"
newline
bitfld.quad 0x00 27. "P27,Active Priority 27" "0,1"
bitfld.quad 0x00 26. "P26,Active Priority 26" "0,1"
bitfld.quad 0x00 25. "P25,Active Priority 25" "0,1"
bitfld.quad 0x00 24. "P24,Active Priority 24" "0,1"
newline
bitfld.quad 0x00 23. "P23,Active Priority 23" "0,1"
bitfld.quad 0x00 22. "P22,Active Priority 22" "0,1"
bitfld.quad 0x00 21. "P21,Active Priority 21" "0,1"
bitfld.quad 0x00 20. "P20,Active Priority 20" "0,1"
newline
bitfld.quad 0x00 19. "P19,Active Priority 19" "0,1"
bitfld.quad 0x00 18. "P18,Active Priority 18" "0,1"
bitfld.quad 0x00 17. "P17,Active Priority 17" "0,1"
bitfld.quad 0x00 16. "P16,Active Priority 16" "0,1"
newline
bitfld.quad 0x00 15. "P15,Active Priority 15" "0,1"
bitfld.quad 0x00 14. "P14,Active Priority 14" "0,1"
bitfld.quad 0x00 13. "P13,Active Priority 13" "0,1"
bitfld.quad 0x00 12. "P12,Active Priority 12" "0,1"
newline
bitfld.quad 0x00 11. "P11,Active Priority 11" "0,1"
bitfld.quad 0x00 10. "P10,Active Priority 10" "0,1"
bitfld.quad 0x00 9. "P9,Active Priority 9" "0,1"
bitfld.quad 0x00 8. "P8,Active Priority 8" "0,1"
newline
bitfld.quad 0x00 7. "P7,Active Priority 7" "0,1"
bitfld.quad 0x00 6. "P6,Active Priority 6" "0,1"
bitfld.quad 0x00 5. "P5,Active Priority 5" "0,1"
bitfld.quad 0x00 4. "P4,Active Priority 4" "0,1"
newline
bitfld.quad 0x00 3. "P3,Active Priority 3" "0,1"
bitfld.quad 0x00 2. "P2,Active Priority 2" "0,1"
bitfld.quad 0x00 1. "P1,Active Priority 1" "0,1"
bitfld.quad 0x00 0. "P0,Active Priority 0" "0,1"
tree.end
newline
rgroup.quad spr:0x34CB3++0x00
line.quad 0x00 "ICH_EISR_EL2,End of Interrupt Status Register"
bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List Register ICH_LR3_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List Register ICH_LR2_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List Register ICH_LR1_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List Register ICH_LR0_EL2" "No interrupt,Interrupt"
rgroup.quad spr:0x34CB5++0x00
line.quad 0x00 "ICH_ELRSR_EL2,Empty List Register Status Register"
bitfld.quad 0x00 3. "STATUS3,Status bit for List Register ICH_LR3_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "STATUS2,Status bit for List Register ICH_LR2_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 1. "STATUS1,Status bit for List Register ICH_LR1_EL2" "No interrupt,Interrupt"
bitfld.quad 0x00 0. "STATUS0,Status bit for List Register ICH_LR0_EL2" "No interrupt,Interrupt"
group.quad spr:0x34CB0++0x00
line.quad 0x00 "ICH_HCR_EL2,Hyp Control Register"
bitfld.quad 0x00 27.--31. "EOICOUNT,Incremented whenever a successful write to a virtual EOIR or DIR Register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR_EL1 and ICV_DIR" "No trap,Trap"
bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "No trap,?..."
newline
bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* and ICV* System Registers for Group 1 interrupts to EL2" "No trap,Trap"
bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* and ICV* System Registers for Group 0 interrupts to EL2" "No trap,Trap"
bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System Registers that are common to Group 0 and Group 1 to EL2" "No trap,Trap"
newline
bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
if (((per.q(spr:0x34CC0))&0x2000000000000000)==0x00)
group.quad spr:0x34CC0++0x00
line.quad 0x00 "ICH_LR0_EL2,List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC0++0x00
line.quad 0x00 "ICH_LR0_EL2,List Register 0"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:0x34CC1))&0x2000000000000000)==0x00)
group.quad spr:0x34CC1++0x00
line.quad 0x00 "ICH_LR1_EL2,List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC1++0x00
line.quad 0x00 "ICH_LR1_EL2,List Register 1"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:0x34CC2))&0x2000000000000000)==0x00)
group.quad spr:0x34CC2++0x00
line.quad 0x00 "ICH_LR2_EL2,List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC2++0x00
line.quad 0x00 "ICH_LR2_EL2,List Register 2"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
if (((per.q(spr:0x34CC3))&0x2000000000000000)==0x00)
group.quad spr:0x34CC3++0x00
line.quad 0x00 "ICH_LR3_EL2,List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
else
group.quad spr:0x34CC3++0x00
line.quad 0x00 "ICH_LR3_EL2,List Register 3"
bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active"
bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware"
bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt"
newline
hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts"
hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt"
endif
rgroup.quad spr:0x34CB2++0x00
line.quad 0x00 "ICH_MISR_EL2,Maintenance Interrupt State Register"
bitfld.quad 0x00 7. "VGRP1D,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 6. "VGRP1E,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 5. "VGRP0D,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 4. "VGRP0E,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
newline
bitfld.quad 0x00 3. "NP,No Pending maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 1. "U,Underflow maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.quad 0x00 0. "EOI,End of Interrupt maintenance interrupt assertion" "Not asserted,Asserted"
group.quad spr:0x34CB7++0x00
line.quad 0x00 "ICH_VMCR_EL2,Virtual Machine Control Register"
hexmask.quad.byte 0x00 24.--31. 1. "VPMR,Virtual Priority Mask"
bitfld.quad 0x00 21.--23. "VBPR0,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.quad 0x00 18.--20. "VBPR1,Interrupt Priority Field Control And Interrupt Preemption Control (Non-secure/Secure)" "Reserved,Reserved,---/[7:3]-[2:0],[7:3]-[2:0]/[7:4]-[3:0],[7:4]-[3:0]/[7:5]-[4:0],[7:5]-[4:0]/[7:6]-[5:0],[7:6]-[5:0]/[7]-[6:0],[7]-[6:0]/No preemption-[7:0]"
newline
bitfld.quad 0x00 9. "VEOIM,Virtual EOI mode. Controls whether a write to an End of Interrupt Register also deactivates the virtual interrupt" "Both,Priority drop"
newline
bitfld.quad 0x00 4. "VCBPR,Decides whether both interrupt groups are controlled by ICV_BPR0_EL1" "Separate,Both"
bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Reserved,Enabled"
bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
rgroup.quad spr:0x34CB1++0x00
line.quad 0x00 "ICH_VTR_EL2,VGIC Type Register"
bitfld.quad 0x00 29.--31. "PRIBITS,The number of virtual priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.quad 0x00 23.--25. "IDBITS,The number of virtual interrupt identifier bits supported" "16 bits,?..."
bitfld.quad 0x00 22. "SEIS,SEI Support" "Not supported,?..."
newline
bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Reserved,Valid"
bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,?..."
bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Reserved,Supported"
bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List Registers" "Reserved,Reserved,Reserved,4,?..."
tree.end
tree.end
tree "Debug Registers"
rgroup.quad spr:0x23010++0x00
line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register"
bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
group.quad spr:0x20020++0x00
line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable Register"
bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
group.quad spr:0x23040++0x00
line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register"
hexmask.quad.long 0x00 32.--63. 1. "HIGHWORD,HighWord - write/read DTRRX/DTRTX value without changing RXfull/TXfull"
newline
hexmask.quad.long 0x00 0.--31. 1. "LOWWORD,LowWord - write/read DTRTX/DTRRX value without changing TXfull/RXfull"
rgroup.quad spr:0x23050++0x00
line.quad 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register"
wgroup.quad spr:0x23050++0x00
line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register"
if (CORENAME()=="CORTEXA55")
group.quad spr:0x24070++0x00
line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register"
bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Disabled,Enabled"
newline
bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Disabled,Enabled"
bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Disabled,Enabled"
newline
bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Disabled,Enabled"
bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Disabled,Enabled"
endif
group.quad spr:0x20002++0x00
line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register"
if (((per.q(spr:0x20114)&0x02)==0x00))
group.quad spr:0x20022++0x00
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
rbitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full"
rbitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full"
newline
rbitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High"
rbitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High"
newline
rbitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTDIS" "0,1,2,3"
rbitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High"
newline
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
rbitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High"
newline
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC Registers to EL1" "No trap,Trap"
newline
rbitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High"
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
else
group.quad spr:0x20022++0x00
line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register"
bitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full"
bitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full"
newline
bitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High"
bitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High"
newline
bitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTDIS" "0,1,2,3"
bitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High"
newline
bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled"
bitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High"
newline
bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled"
bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC Registers to EL1" "No trap,Trap"
newline
bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High"
bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled"
endif
group.quad spr:0x20032++0x00
line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register"
if (((per.q(spr:0x20114)&0x02)==0x02))
group.quad spr:0x20062++0x00
line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
bitfld.quad 0x00 7. 15. "NS[3],Coarse-grained Non-secure exception catch/return bit NSE[3] and NSR[3]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 6. 14. "NS[2],Coarse-grained Non-secure exception catch/return bit NSE[2] and NSR[2]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 5. 13. "NS[1],Coarse-grained Non-secure exception catch/return bit NSE[1] and NSR[1]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
newline
bitfld.quad 0x00 4. 12. "NS[0],Coarse-grained Non-secure exception catch/return bit NSE[0] and NSR[0]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 3. 11. "S[3],Coarse-grained Secure exception catch/return bit SE[3] and SR[3]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 2. 10. "S[2],Coarse-grained Secure exception catch/return bit SE[2] and SR[2]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
newline
bitfld.quad 0x00 1. 9. "S[1],Coarse-grained Secure exception catch/return bit SE[1] and SR[1]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
bitfld.quad 0x00 0. 8. "S[0],Coarse-grained Secure exception catch/return bit SE[0] and SR[0]" "No action/No action,Halt/Halt,No action/Halt,Halt/No action"
else
rgroup.quad spr:0x20062++0x00
line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register"
endif
rgroup.quad spr:0x20100++0x00
line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register"
hexmask.quad 0x00 12.--47. 0x10 "ROMADDR,ROM base physical address"
bitfld.quad 0x00 0.--1. "VALID,ROM address valid" "Invalid,Reserved,Reserved,Valid"
wgroup.quad spr:0x20104++0x00
line.quad 0x00 "OSLAR_EL1,OS Lock Access Register"
bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock"
rgroup.quad spr:0x20114++0x00
line.quad 0x00 "OSLSR_EL1,OS Lock Status Register"
bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,?..."
bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked"
bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Implemented,?..."
group.quad spr:0x20134++0x00
line.quad 0x00 "OSDLR_EL1,OS Double-lock Register"
bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.quad spr:0x20144++0x00
line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register"
bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "Powered down,Emulated"
group.quad spr:0x20786++0x00
line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag Register Set"
bitfld.quad 0x00 7. "CT7,Claim tag 7 set" "Not set,Set"
bitfld.quad 0x00 6. "CT6,Claim tag 6 set" "Not set,Set"
newline
bitfld.quad 0x00 5. "CT5,Claim tag 5 set" "Not set,Set"
bitfld.quad 0x00 4. "CT4,Claim tag 4 set" "Not set,Set"
newline
bitfld.quad 0x00 3. "CT3,Claim tag 3 set" "Not set,Set"
bitfld.quad 0x00 2. "CT2,Claim tag 2 set" "Not set,Set"
newline
bitfld.quad 0x00 1. "CT1,Claim tag 1 set" "Not set,Set"
bitfld.quad 0x00 0. "CT0,Claim tag 0 set" "Not set,Set"
group.quad spr:0x20796++0x00
line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag Register Clear"
bitfld.quad 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.quad 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
newline
bitfld.quad 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
bitfld.quad 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
newline
bitfld.quad 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.quad 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.quad 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.quad 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.quad spr:0x207E6++0x00
line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status Register"
bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled"
newline
bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented"
bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled"
newline
tree.end
tree "Activity Monitors Unit"
if (CORENAME()=="CORTEXA76")
group.quad spr:0x33F97++0x00
line.quad 0x00 "AMCNTENCLR_EL0,Activity Monitors Count Enable Clear Register"
bitfld.quad 0x00 4. "P4,AMEVCNTR4 disable bit [read/write]" "Disabled/No effect,Enabled/Disables"
newline
bitfld.quad 0x00 3. "P3,AMEVCNTR3 disable bit [read/write]" "Disabled/No effect,Enabled/Disables"
bitfld.quad 0x00 2. "P2,AMEVCNTR2 disable bit [read/write]" "Disabled/No effect,Enabled/Disables"
bitfld.quad 0x00 1. "P1,AMEVCNTR1 disable bit [read/write]" "Disabled/No effect,Enabled/Disables"
bitfld.quad 0x00 0. "P0,AMEVCNTR0 disable bit [read/write]" "Disabled/No effect,Enabled/Disables"
group.quad spr:0x33F96++0x00
line.quad 0x00 "AMCNTENSET_EL0,Activity Monitors Count Enable Set Register"
bitfld.quad 0x00 4. "P4,AMEVCNTR4 enable bit [read/write]" "Disabled/No effect,Enabled/Enables"
bitfld.quad 0x00 3. "P3,AMEVCNTR3 enable bit [read/write]" "Disabled/No effect,Enabled/Enables"
bitfld.quad 0x00 2. "P2,AMEVCNTR2 enable bit [read/write]" "Disabled/No effect,Enabled/Enables"
bitfld.quad 0x00 1. "P1,AMEVCNTR1 enable bit [read/write]" "Disabled/No effect,Enabled/Enables"
newline
bitfld.quad 0x00 0. "P0,AMEVCNTR0 enable bit" "Disabled/No effect,Enabled/Enables"
rgroup.quad spr:0x33FA6++0x00
line.quad 0x00 "AMCFGR_EL0,Activity Monitors Configuration Register"
bitfld.quad 0x00 8.--13. "SIZE,Size of counters" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64"
hexmask.quad.byte 0x00 0.--7. 1. 1. "N,Number of activity counters implemented"
group.quad spr:0x33FA7++0x00
line.quad 0x00 "AMUSERENR_EL0,Activity Monitor EL0 Enable access"
bitfld.quad 0x00 0. "EN,Traps EL0 accesses to the activity monitor Registers to EL1" "Trapped,Not trapped"
newline
group.quad spr:0x33F90++0x00
line.quad 0x00 "AMEVCNTR0_EL0,Activity Monitor Event Counter Register 0"
group.quad spr:(0x33F90+0x10)++0x00
line.quad 0x00 "AMEVTYPER0_EL0,Activity Monitor Event Type Register 0"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT"
group.quad spr:0x33F91++0x00
line.quad 0x00 "AMEVCNTR1_EL0,Activity Monitor Event Counter Register 1"
group.quad spr:(0x33F91+0x10)++0x00
line.quad 0x00 "AMEVTYPER1_EL0,Activity Monitor Event Type Register 1"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT"
group.quad spr:0x33F92++0x00
line.quad 0x00 "AMEVCNTR2_EL0,Activity Monitor Event Counter Register 2"
group.quad spr:(0x33F92+0x10)++0x00
line.quad 0x00 "AMEVTYPER2_EL0,Activity Monitor Event Type Register 2"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT"
group.quad spr:0x33F93++0x00
line.quad 0x00 "AMEVCNTR3_EL0,Activity Monitor Event Counter Register 3"
group.quad spr:(0x33F93+0x10)++0x00
line.quad 0x00 "AMEVTYPER3_EL0,Activity Monitor Event Type Register 3"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT"
group.quad spr:0x33F94++0x00
line.quad 0x00 "AMEVCNTR4_EL0,Activity Monitor Event Counter Register 4"
group.quad spr:(0x33F94+0x10)++0x00
line.quad 0x00 "AMEVTYPER4_EL0,Activity Monitor Event Type Register 4"
hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT"
elif (CORENAME()=="CORTEXA55")
textline "--------------------------------------------------------------------------------"
newline
textline "            These Registers are not available in CORTEXA55"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Breakpoint Registers"
tree "Breakpoint 0"
if (((per.q(spr:0x20005+0x0))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x0))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x0))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x0)++0x00
line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x0))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x0))&0xC000)==0x0000)
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x0))&0xC000)==0x4000)
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x0))&0xC000)==0x8000)
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x0))&0xC000)==0xC000)
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x0)++0x00
line.quad 0x00 "DBGBCR0_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Breakpoint 1"
if (((per.q(spr:0x20005+0x10))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x10))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x10))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x10)++0x00
line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x10))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x10))&0xC000)==0x0000)
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x10))&0xC000)==0x4000)
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x10))&0xC000)==0x8000)
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x10))&0xC000)==0xC000)
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x10)++0x00
line.quad 0x00 "DBGBCR1_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Breakpoint 2"
if (((per.q(spr:0x20005+0x20))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x20))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x20))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x20)++0x00
line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x20))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x20))&0xC000)==0x0000)
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x20))&0xC000)==0x4000)
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x20))&0xC000)==0x8000)
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x20))&0xC000)==0xC000)
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x20)++0x00
line.quad 0x00 "DBGBCR2_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Breakpoint 3"
if (((per.q(spr:0x20005+0x30))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x30))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x30))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x30)++0x00
line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x30))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x30))&0xC000)==0x0000)
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x30))&0xC000)==0x4000)
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x30))&0xC000)==0x8000)
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x30))&0xC000)==0xC000)
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x30)++0x00
line.quad 0x00 "DBGBCR3_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Breakpoint 4"
if (((per.q(spr:0x20005+0x40))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x40))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x40))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x40)++0x00
line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x40))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x40))&0xC000)==0x0000)
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x40))&0xC000)==0x4000)
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x40))&0xC000)==0x8000)
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x40))&0xC000)==0xC000)
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x40)++0x00
line.quad 0x00 "DBGBCR4_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Breakpoint 5"
if (((per.q(spr:0x20005+0x50))&0xF00000)<=0x100000)
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad 0x00 2.--48. 0x04 "VA,Bits[48:2] of the address value for comparison"
elif (((((per.q(spr:0x20005+0x50))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x50))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x700000)))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x900000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x00000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xB00000)&&(((per.q(spr:0x34212))&0x80000)==0x80000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.word 0x00 32.--47. 1. "VMID,VMID value for comparison"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison"
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xC00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xD00000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xE00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xF00000))
group.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
hexmask.quad.long 0x00 32.--63. 1. "CONTEXTID2,Context ID value for comparison against CONTEXTIDR_EL2"
hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison against CONTEXTIDR_EL1"
else
rgroup.quad spr:(0x20004+0x50)++0x00
line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register"
endif
if (((per.q(spr:0x20005+0x50))&0x2000)==0x2000)
if (((per.q(spr:0x20005+0x50))&0xC000)==0x0000)
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x50))&0xC000)==0x4000)
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
elif (((per.q(spr:0x20005+0x50))&0xC000)==0x8000)
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20005+0x50))&0xC000)==0xC000)
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.quad spr:(0x20005+0x50)++0x00
line.quad 0x00 "DBGBCR5_EL1,Debug Breakpoint Control Register"
bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DBGBVRn_EL1+2,Reserved,Reserved,DBGBVRn_EL1"
bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "Reserved,System,User,User/System"
newline
bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
tree.end
tree.end
tree "Watchpoint Registers"
tree "Watchpoint 0"
group.quad spr:(0x20006+0x0)++0x00
line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
if (((per.q(spr:0x20007+0x0))&0x2000)==0x2000)
if (((per.q(spr:0x20007+0x0))&0xC000)==0x0000)
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.q(spr:0x20007+0x0))&0xC000)==0x4000)
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.q(spr:0x20007+0x0))&0xC000)==0x8000)
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20007+0x0))&0xC000)==0xC000)
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x0)++0x00
line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Reserved,System,User,User/System"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Watchpoint 1"
group.quad spr:(0x20006+0x10)++0x00
line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
if (((per.q(spr:0x20007+0x10))&0x2000)==0x2000)
if (((per.q(spr:0x20007+0x10))&0xC000)==0x0000)
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.q(spr:0x20007+0x10))&0xC000)==0x4000)
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.q(spr:0x20007+0x10))&0xC000)==0x8000)
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20007+0x10))&0xC000)==0xC000)
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x10)++0x00
line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Reserved,System,User,User/System"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Watchpoint 2"
group.quad spr:(0x20006+0x20)++0x00
line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
if (((per.q(spr:0x20007+0x20))&0x2000)==0x2000)
if (((per.q(spr:0x20007+0x20))&0xC000)==0x0000)
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.q(spr:0x20007+0x20))&0xC000)==0x4000)
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.q(spr:0x20007+0x20))&0xC000)==0x8000)
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20007+0x20))&0xC000)==0xC000)
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x20)++0x00
line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Reserved,System,User,User/System"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
tree.end
tree "Watchpoint 3"
group.quad spr:(0x20006+0x30)++0x00
line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)"
hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address"
if (((per.q(spr:0x20007+0x30))&0x2000)==0x2000)
if (((per.q(spr:0x20007+0x30))&0xC000)==0x0000)
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Reserved,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.q(spr:0x20007+0x30))&0xC000)==0x4000)
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.q(spr:0x20007+0x30))&0xC000)==0x8000)
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "TrustZone,System/Supervisor/TrustZone,Reserved,User/System/Supervisor/TrustZone"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.q(spr:0x20007+0x30))&0xC000)==0xC000)
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.quad spr:(0x20007+0x30)++0x00
line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register"
bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.quad 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.quad 0x00 1.--2. "PAC,Privileged access control" "Reserved,System,User,User/System"
bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
tree.end
tree.end
tree "LORegions Registers"
group.quad spr:0x30A40++0x00
line.quad 0x00 "LORSA_EL1,LORegion Start Address"
hexmask.quad.long 0x00 16.--47. 0x01 "SA,Start physical address bits[47:16]"
bitfld.quad 0x00 0. "VALID,Indicates whether the LORegion Descriptor is enabled" "Not valid,Valid"
group.quad spr:0x30A41++0x00
line.quad 0x00 "LOREA_EL1,LORegion End Address"
hexmask.quad.long 0x00 16.--47. 0x01 "EA,End physical address bits[47:16]"
group.quad spr:0x30A42++0x00
line.quad 0x00 "LORN_EL1,LORegion Number Register"
bitfld.quad 0x00 0.--1. "NUM,Indicates the LORegion number" "0,1,2,3"
group.quad spr:0x30A43++0x00
line.quad 0x00 "LORC_EL1,LORegion Control Register"
bitfld.quad 0x00 2.--3. "DS,Descriptor Select" "0,1,2,3"
bitfld.quad 0x00 0. "EN,Enable" "Disabled,Enabled"
rgroup.quad spr:0x30A47++0x00
line.quad 0x00 "LORID_EL1,Limited Order Region Identification Register"
hexmask.quad.byte 0x00 16.--23. 1. "LD,Number of LOR Descriptors supported by the implementation"
hexmask.quad.byte 0x00 0.--7. 1. "LR,Number of LORegions supported by the implementation"
tree.end
tree "DynamIQ Shared Unit"
tree "Cluster Control Registers"
if (((per.q(spr:0x30F30))&0x2000)==0x00)
rgroup.quad spr:0x30F30++0x00
line.quad 0x00 "CLUSTERCFR_EL1,Cluster Configuration Register"
bitfld.quad 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..."
bitfld.quad 0x00 23. "L3_DATA_RAM_DELAY,L3 data RAM write delay" "Not delayed,Delayed"
newline
bitfld.quad 0x00 17. "CRSP3,Core 3 register slice present" "Not present,Present"
bitfld.quad 0x00 16. "CRSP2,Core 2 register slice present" "Not present,Present"
newline
bitfld.quad 0x00 15. "CRSP1,Core 1 register slice present" "Not present,Present"
bitfld.quad 0x00 14. "CRSP0,Core 0 register slice present" "Not present,Present"
bitfld.quad 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended"
newline
bitfld.quad 0x00 12. "PPP,Peripheral port present" "Not present,Present"
bitfld.quad 0x00 11. "ACP,ACP interface present" "Not present,Present"
bitfld.quad 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Single 256-bit CHI"
newline
bitfld.quad 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC"
bitfld.quad 0x00 7. "L3_DATA_RAM_RS,L3 data RAM register slice present" "Not present,Present"
bitfld.quad 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles"
newline
bitfld.quad 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles"
bitfld.quad 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present"
bitfld.quad 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..."
else
rgroup.quad spr:0x30F30++0x00
line.quad 0x00 "CLUSTERCFR_EL1,Cluster Configuration Register"
bitfld.quad 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..."
bitfld.quad 0x00 23. "L3_DATA_RAM_DELAY,L3 data RAM write delay" "Not delayed,Delayed"
newline
bitfld.quad 0x00 17. "CRSP3,Core 3 register slice present" "Not present,Present"
bitfld.quad 0x00 16. "CRSP2,Core 2 register slice present" "Not present,Present"
newline
bitfld.quad 0x00 15. "CRSP1,Core 1 register slice present" "Not present,Present"
bitfld.quad 0x00 14. "CRSP0,Core 0 register slice present" "Not present,Present"
bitfld.quad 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended"
newline
bitfld.quad 0x00 12. "PPP,Peripheral port present" "Not present,Present"
bitfld.quad 0x00 11. "ACP,ACP interface present" "Not present,Present"
bitfld.quad 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Dual 256-bit CHI"
newline
bitfld.quad 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC"
bitfld.quad 0x00 7. "L3_DATA_RAM_RS,L3 data RAM register slice present" "Not present,Present"
bitfld.quad 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles"
newline
bitfld.quad 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles"
bitfld.quad 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present"
bitfld.quad 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..."
endif
rgroup.quad spr:0x30F31++0x00
line.quad 0x00 "CLUSTERIDR_EL1,Cluster Main Revision ID"
hexmask.quad.byte 0x00 4.--7. 1. "VARIANT,Indicates the variant of the FCM"
hexmask.quad.byte 0x00 0.--3. 1. "REVISION,Indicates the minor revision number of the FCM"
rgroup.quad spr:0x30F32++0x00
line.quad 0x00 "CLUSTERREVIDR_EL1,Cluster ECO ID"
group.quad spr:0x30F33++0x00
line.quad 0x00 "CLUSTERACTLR_EL1,Cluster Auxiliary Control Register"
if (((per.q(spr:0x30F30))&0x600)==(0x00||0x200))
group.quad spr:0x30F34++0x00
line.quad 0x00 "CLUSTERECTLR_EL1,Cluster Extended Control Register"
bitfld.quad 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled"
bitfld.quad 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128"
bitfld.quad 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes"
newline
bitfld.quad 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported"
bitfld.quad 0x00 3. "CTEC,Disables send evict transactions on the ACE/CHI master" "No,Yes"
bitfld.quad 0x00 2. "CFUCEC,Disables WriteEvict requests on the ACE/CHI master (Powering down part/All L3 cache)" "No,Yes"
newline
bitfld.quad 0x00 0. "DNCWL,Disable the limit on the number of non-cacheable writes that are allowed on the ACE interface" "No,Yes"
else
group.quad spr:0x30F34++0x00
line.quad 0x00 "CLUSTERECTLR_EL1,Cluster Extended Control Register"
bitfld.quad 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled"
bitfld.quad 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128"
bitfld.quad 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes"
newline
bitfld.quad 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported"
bitfld.quad 0x00 3. "CTEC,Disables send evict transactions on the ACE/CHI master" "No,Yes"
bitfld.quad 0x00 2. "CFUCEC,Disables WriteEvict requests on the ACE/CHI master (Powering down part/All L3 cache)" "No,Yes"
endif
group.quad spr:0x30F35++0x00
line.quad 0x00 "CLUSTERPWRCTLR_EL1,Cluster Power Control Register"
bitfld.quad 0x00 4.--7. "CPPR,Cache portion power request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0.--2. "L3_DATA_RAM_RC,L3 data RAM retention control [Number of Architectural Timer ticks required before retention entry]" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
group.quad spr:0x30F36++0x00
line.quad 0x00 "CLUSTERPWRDN_EL1,Cluster Power Down Register"
bitfld.quad 0x00 1. "MRR,Memory retention required" "Not required,Required"
bitfld.quad 0x00 0. "CPR,Cluster power required" "Not required,Required"
rgroup.quad spr:0x30F37++0x00
line.quad 0x00 "CLUSTERPWRSTAT_EL1,Cluster Power Status Register"
bitfld.quad 0x00 4.--7. "CPPS,This bits indicates which cache portions are currently powered up and available" "No ways,Ways 0-3,Reserved,Ways 0-7,Reserved,Reserved,Reserved,Ways 0-11,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ways 0-15"
bitfld.quad 0x00 1. "RWPD,Enabled memory retention when all cores are powered down" "Disabled,Enabled"
bitfld.quad 0x00 0. "DCPD,Disabled cluster power down when all cores are powered down" "No,Yes"
group.quad spr:0x30F40++0x00
line.quad 0x00 "CLUSTERTHREADSID_EL1,Cluster Thread Scheme ID Register"
bitfld.quad 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for current thread" "0,1,2,3,4,5,6,7"
group.quad spr:0x30F41++0x00
line.quad 0x00 "CLUSTERACPSID_EL1,Cluster ACP Scheme ID Register"
bitfld.quad 0x00 0.--2. "SCHEME_ID_ACP,Scheme ID for ACP transactions" "0,1,2,3,4,5,6,7"
group.quad spr:0x30F42++0x00
line.quad 0x00 "CLUSTERSTASHSID_EL1,Cluster Stash Scheme ID Register"
bitfld.quad 0x00 0.--2. "SCHEME_ID_SR,Scheme ID for stash requests received from the interconnect" "0,1,2,3,4,5,6,7"
group.quad spr:0x30F43++0x00
line.quad 0x00 "CLUSTERPARTCR_EL1,Cluster Partition Control Register"
bitfld.quad 0x00 31. "W3_ID7,Way group 3 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.quad 0x00 30. "W2_ID7,Way group 2 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.quad 0x00 29. "W1_ID7,Way group 1 is assigned as private to scheme ID 7" "Not assigned,Assigned"
newline
bitfld.quad 0x00 28. "W0_ID7,Way group 0 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.quad 0x00 27. "W3_ID6,Way group 3 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.quad 0x00 26. "W2_ID6,Way group 2 is assigned as private to scheme ID 6" "Not assigned,Assigned"
newline
bitfld.quad 0x00 25. "W1_ID6,Way group 1 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.quad 0x00 24. "W0_ID6,Way group 0 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.quad 0x00 23. "W3_ID5,Way group 3 is assigned as private to scheme ID 5" "Not assigned,Assigned"
newline
bitfld.quad 0x00 22. "W2_ID5,Way group 2 is assigned as private to scheme ID 5" "Not assigned,Assigned"
bitfld.quad 0x00 21. "W1_ID5,Way group 1 is assigned as private to scheme ID 5" "Not assigned,Assigned"
bitfld.quad 0x00 20. "W0_ID5,Way group 0 is assigned as private to scheme ID 5" "Not assigned,Assigned"
newline
bitfld.quad 0x00 19. "W3_ID4,Way group 3 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.quad 0x00 18. "W2_ID4,Way group 2 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.quad 0x00 17. "W1_ID4,Way group 1 is assigned as private to scheme ID 4" "Not assigned,Assigned"
newline
bitfld.quad 0x00 16. "W0_ID4,Way group 0 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.quad 0x00 15. "W3_ID3,Way group 3 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.quad 0x00 14. "W2_ID3,Way group 2 is assigned as private to scheme ID 3" "Not assigned,Assigned"
newline
bitfld.quad 0x00 13. "W1_ID3,Way group 1 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.quad 0x00 12. "W0_ID3,Way group 0 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.quad 0x00 11. "W3_ID2,Way group 3 is assigned as private to scheme ID 2" "Not assigned,Assigned"
newline
bitfld.quad 0x00 10. "W2_ID2,Way group 2 is assigned as private to scheme ID 2" "Not assigned,Assigned"
bitfld.quad 0x00 9. "W1_ID2,Way group 1 is assigned as private to scheme ID 2" "Not assigned,Assigned"
bitfld.quad 0x00 8. "W0_ID2,Way group 0 is assigned as private to scheme ID 2" "Not assigned,Assigned"
newline
bitfld.quad 0x00 7. "W3_ID1,Way group 3 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.quad 0x00 6. "W2_ID1,Way group 2 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.quad 0x00 5. "W1_ID1,Way group 1 is assigned as private to scheme ID 1" "Not assigned,Assigned"
newline
bitfld.quad 0x00 4. "W0_ID1,Way group 0 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.quad 0x00 3. "W3_ID0,Way group 3 is assigned as private to scheme ID 0" "Not assigned,Assigned"
bitfld.quad 0x00 2. "W2_ID0,Way group 2 is assigned as private to scheme ID 0" "Not assigned,Assigned"
newline
bitfld.quad 0x00 1. "W1_ID0,Way group 1 is assigned as private to scheme ID 0" "Not assigned,Assigned"
bitfld.quad 0x00 0. "W0_ID0,Way group 0 is assigned as private to scheme ID 0" "Not assigned,Assigned"
group.quad spr:0x30F44++0x00
line.quad 0x00 "CLUSTERBUSQOS_EL1,Cluster Bus QoS Control Register"
bitfld.quad 0x00 28.--31. "CHI_BUS_QOS_SCHEME_ID7,Value driven on the CHI bus QoS field for scheme ID 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 24.--27. "CHI_BUS_QOS_SCHEME_ID6,Value driven on the CHI bus QoS field for scheme ID 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 20.--23. "CHI_BUS_QOS_SCHEME_ID5,Value driven on the CHI bus QoS field for scheme ID 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 16.--19. "CHI_BUS_QOS_SCHEME_ID4,Value driven on the CHI bus QoS field for scheme ID 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 12.--15. "CHI_BUS_QOS_SCHEME_ID3,Value driven on the CHI bus QoS field for scheme ID 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 8.--11. "CHI_BUS_QOS_SCHEME_ID2,Value driven on the CHI bus QoS field for scheme ID 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.quad 0x00 4.--7. "CHI_BUS_QOS_SCHEME_ID1,Value driven on the CHI bus QoS field for scheme ID 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 0.--3. "CHI_BUS_QOS_SCHEME_ID0,Value driven on the CHI bus QoS field for scheme ID 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.quad spr:0x30F45++0x00
line.quad 0x00 "CLUSTERL3HIT_EL1,Cluster L3 Hit Counter Register"
group.quad spr:0x30F46++0x00
line.quad 0x00 "CLUSTERL3MISS_EL1,Cluster L3 Miss Counter Register"
group.quad spr:0x30F47++0x00
line.quad 0x00 "CLUSTERTHREADSIDOVR_EL1,Cluster Thread Scheme ID Override Register"
bitfld.quad 0x00 16.--18. "SCHEME_ID_MASK,A bit set in the mask causes the matching bit to be taken from this register rather than from the CLUSTERTHREADSID_EL1 register" "0,1,2,3,4,5,6,7"
bitfld.quad 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for this thread if masked" "0,1,2,3,4,5,6,7"
tree.end
tree "Error System Registers"
rgroup.quad spr:0x30530++0x00
line.quad 0x00 "ERRIDR_EL1,Error ID Register"
hexmask.quad.word 0x00 0.--15. 1. "NUM,Number of records that can be accessed through the Error Record system registers"
group.quad spr:0x30531++0x00
line.quad 0x00 "ERRSELR_EL1,Error Record Select Register"
bitfld.quad 0x00 0. "SEL,Selects the record accessed through the ERX registers" "Record 0,Record 1"
if (((per.q(spr:0x30531))&0x01)==0x00)
if (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x30540++0x00
line.quad 0x00 "ERXFR_EL1,Error Record Feature Register"
bitfld.quad 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..."
bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented"
newline
bitfld.quad 0x00 12.--14. "CEC,Corrected error counter" "Reserved,Reserved,8-bit standard CE,?..."
bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..."
newline
bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Implemented,?..."
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30540++0x00
line.quad 0x00 "ERXFR_EL1,Error Record Feature Register"
bitfld.quad 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..."
bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented"
newline
bitfld.quad 0x00 12.--14. "CEC,Corrected error counter" "Reserved,Reserved,8-bit standard CE,?..."
bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 2.--3. "DE,Defers Errors always enable" "Reserved,Enabled,?..."
newline
bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Implemented,?..."
endif
group.quad spr:0x30541++0x00
line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register"
bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled"
if (CORENAME()=="CORTEXA76")
group.quad spr:0x30542++0x00
line.quad 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register"
bitfld.quad 0x00 31. "AV,Address valid" "Not valid,Valid"
bitfld.quad 0x00 30. "V,Status register valid" "Not valid,Valid"
bitfld.quad 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.quad 0x00 28. "ER,Error reported" "No error,Error"
bitfld.quad 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.quad 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid"
newline
bitfld.quad 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..."
bitfld.quad 0x00 23. "DE,Deferred errors" "No error,>=1 error"
bitfld.quad 0x00 22. "PN,Poison" "No distinction,?..."
newline
bitfld.quad 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..."
bitfld.quad 0x00 0.--4. "SERR,Primary error code" "No error,Fault injection,ECC/internal data buffer,Reserved,Reserved,Reserved,ECC/Cache data RAM,ECC/Cache tag/Dirty RAM,Parity error/TLB data RAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Cache copyback,Reserved,Reserved,Deferred error from slave not supported at the consumer,?..."
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x30542++0x00
line.quad 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register"
bitfld.quad 0x00 31. "AV,Address valid" "Not valid,?..."
bitfld.quad 0x00 30. "V,Status register valid" "Not valid,Valid"
bitfld.quad 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.quad 0x00 28. "ER,Error reported" "No error,Error"
bitfld.quad 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.quad 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid"
newline
bitfld.quad 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..."
bitfld.quad 0x00 23. "DE,Deferred errors" "No error,>=1 error"
bitfld.quad 0x00 22. "PN,Poison" "No distinction,?..."
newline
bitfld.quad 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..."
newline
bitfld.quad 0x00 8.--15. "IERR,Implementation defined error code" "No error/Other RAMs,Error/L1 dirty RAM,?..."
bitfld.quad 0x00 0.--7. "SERR,Primary error code" "No error,Reserved,ECC/internal data buffer,Reserved,Reserved,Reserved,ECC/Cache data RAM,ECC/Cache tag/Dirty RAM,Parity error/TLB data RAM,Parity error/TLB tag RAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Deferred error from slave not supported at the consumer,?..."
endif
if (CORENAME()=="CORTEXA76")
group.quad spr:0x30543++0x00
line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register"
bitfld.quad 0x00 63. "NS,Non-secure attribute" "No,Yes"
hexmask.quad 0x00 0.--39. 0x01 "PADDR,Physical address"
elif (CORENAME()=="CORTEXA55")
rgroup.quad spr:0x30543++0x00
line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register"
endif
if (CORENAME()=="CORTEXA76")
if (((per.q(spr:0x30550))&0x0F)==0x01)
if (((per.q(spr:0x30550))&0x30)==0x10)
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Corrected error count repeat"
bitfld.quad 0x00 28.--29. "WAY,Indicates which way has the error" "0,1,2,3"
newline
bitfld.quad 0x00 25. "SUBBANK,Indicates which subbank has the error" "0,1"
bitfld.quad 0x00 23.--24. "BANK,Bank detected the error" "0,1,2,3"
newline
hexmask.quad.word 0x00 6.--18. 1. "INDEX,Indicates which index has the error"
bitfld.quad 0x00 4.--5. "ARRAY,Indicates which array that detected the error" "Tag,Data,?..."
newline
bitfld.quad 0x00 0.--3. "UNIT,Unit detected the error" "Reserved,L1 instruction cache,L2 TLB,Reserved,L1 data cache,Reserved,Reserved,Reserved,L2 Cache,?..."
newline
else
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Corrected error count repeat"
bitfld.quad 0x00 28.--29. "WAY,Indicates which way has the error" "0,1,2,3"
newline
newline
hexmask.quad.word 0x00 6.--18. 1. "INDEX,Indicates which index has the error"
bitfld.quad 0x00 4.--5. "ARRAY,Indicates which array that detected the error" "Tag,Data,?..."
newline
bitfld.quad 0x00 0.--3. "UNIT,Unit detected the error" "Reserved,L1 instruction cache,L2 TLB,Reserved,L1 data cache,Reserved,Reserved,Reserved,L2 Cache,?..."
newline
endif
elif (((per.q(spr:0x30550))&0x0F)==0x02)
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Corrected error count repeat"
bitfld.quad 0x00 28.--31. "WAY,Indicates which RAM has an error" "RAM 1,RAM 2,RAM 3,RAM 4,RAM 5,RAM 6,RAM 7,RAM 8,RAM 9,RAM 10,?..."
newline
newline
hexmask.quad.word 0x00 6.--14. 1. "INDEX,Index of TLB RAM"
newline
bitfld.quad 0x00 0.--3. "UNIT,Unit detected the error" "Reserved,L1 instruction cache,L2 TLB,Reserved,L1 data cache,Reserved,Reserved,Reserved,L2 Cache,?..."
newline
elif (((per.q(spr:0x30550))&0x0F)==0x04)
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Corrected error count repeat"
bitfld.quad 0x00 28.--29. "WAY,Indicates which tag RAM way or data RAM way detected the error" "0,1,2,3"
newline
bitfld.quad 0x00 19.--22. "SUBARRAY,Indicates for L1 Data RAM which word had the error detected" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.quad.word 0x00 6.--18. 1. "INDEX,Indicates which index detected the error"
bitfld.quad 0x00 4.--5. "ARRAY,Indicates which array that detected the error" "LS0 copy of Tag RAM,LS1 copy of Tag RAM,LS Data RAM,?..."
newline
bitfld.quad 0x00 0.--3. "UNIT,Unit detected the error" "Reserved,L1 instruction cache,L2 TLB,Reserved,L1 data cache,Reserved,Reserved,Reserved,L2 Cache,?..."
newline
elif (((per.q(spr:0x30550))&0x0F)==0x08)
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Corrected error count repeat"
newline
bitfld.quad 0x00 23. "BANK,Indicates which L2 bank detected the error" "0,1"
bitfld.quad 0x00 19.--21. "SUBARRAY,Indicates which L2 tag way or data doubleword detected the error" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x00 6.--18. 1. "INDEX,Indicates which index detected the error"
bitfld.quad 0x00 4.--5. "ARRAY,Indicates which array that detected the error" "L2 tag RAM,L2 data RAM,TQ data RAM,CHI slave error"
newline
bitfld.quad 0x00 0.--3. "UNIT,Unit detected the error" "Reserved,L1 instruction cache,L2 TLB,Reserved,L1 data cache,Reserved,Reserved,Reserved,L2 Cache,?..."
newline
else
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Corrected error count repeat"
newline
newline
newline
bitfld.quad 0x00 0.--3. "UNIT,Unit detected the error" "Reserved,L1 instruction cache,L2 TLB,Reserved,L1 data cache,Reserved,Reserved,Reserved,L2 Cache,?..."
newline
endif
elif (CORENAME()=="CORTEXA55")
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0 (EL1)"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Repeat error count"
bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.quad 0x00 1.--3. "LVL,Indicates the level that contained the error" "Level 1,Level 2,?..."
bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "Data cache(L1)/Unified cache(L2)/TLB,Instruction cache(L1)"
endif
else
rgroup.quad spr:0x30540++0x00
line.quad 0x00 "ERXFR_EL1,Error Record Feature Register"
bitfld.quad 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..."
bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented"
newline
bitfld.quad 0x00 12.--14. "CEC,Corrected error counter" "Reserved,Reserved,8 bit standard CE,?..."
bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..."
newline
bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..."
bitfld.quad 0x00 2.--3. "DE,Defers errors always enable" "Reserved,Enabled,?..."
newline
bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Implemented,?..."
group.quad spr:0x30541++0x00
line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register"
bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "No interrupt,Interrupt"
bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "No interrupt,Interrupt"
bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "No interrupt,Interrupt"
newline
bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled"
group.quad spr:0x30542++0x00
line.quad 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register"
bitfld.quad 0x00 31. "AV,Address valid" "Not valid,?..."
bitfld.quad 0x00 30. "V,Status register valid" "Not valid,Valid"
bitfld.quad 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.quad 0x00 28. "ER,Error reported" "No error,?..."
bitfld.quad 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.quad 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid"
newline
bitfld.quad 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..."
bitfld.quad 0x00 23. "DE,Deferred errors" "No error,>=1 error"
bitfld.quad 0x00 22. "PN,Poison" "No distinction,Earlier"
newline
bitfld.quad 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..."
newline
bitfld.quad 0x00 8.--15. "IERR,Implementation defined error code" "No error/Other RAMs,Reserved,Error/L3 snoop RAM,?..."
bitfld.quad 0x00 0.--7. "SERR,Primary error code" "No error,Reserved,ECC/internal data buffer,Reserved,Reserved,Reserved,ECC/Cache data RAM,ECC/Cache tag/Dirty RAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Bus error,?..."
rgroup.quad spr:0x30543++0x00
line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register"
group.quad spr:0x30550++0x00
line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0"
bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow"
hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other"
bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow"
newline
hexmask.quad.byte 0x00 32.--38. 1. "CECR,Repeat error count"
bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.quad 0x00 1.--3. "LVL,Indicates the level that contained the error" "Reserved,Reserved,Level 3,?..."
bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "L3 cache,?..."
endif
group.quad spr:0x30551++0x00
line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1"
group.quad spr:0x30F22++0x00
line.quad 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register"
if (CORENAME()=="CORTEXA76")
group.quad spr:0x30F21++0x00
line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register"
bitfld.quad 0x00 31. "CDNEN,Count down enable.Control transfers from the value that is held in the ERR0PFGCDNR into the Error Generation Counter" "Disabled,Enabled"
bitfld.quad 0x00 30. "R,Restartable bit" "Disabled,Enabled"
bitfld.quad 0x00 6. "CE,Corrected error generation enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "DE,Deferred error generation enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
if (((per.q(spr:0x30531))&0x01)==0x00)
rgroup.quad spr:0x30F20++0x00
line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register"
bitfld.quad 0x00 31. "PGF,Pseudo fault generation" "Reserved,Supported"
bitfld.quad 0x00 30. "R,Restartable bit" "Reserved,Supported"
bitfld.quad 0x00 6. "CE,Corrected error generation" "Reserved,Supported"
newline
bitfld.quad 0x00 5. "DE,Deferred error generation" "Reserved,Supported"
bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..."
bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,?..."
newline
bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,?..."
bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Reserved,Supported"
else
rgroup.quad spr:0x30F20++0x00
line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register"
bitfld.quad 0x00 31. "PGF,Pseudo fault generation" "Not supported,Supported"
bitfld.quad 0x00 30. "R,Restartable bit" "Not supported,Supported"
bitfld.quad 0x00 6. "CE,Corrected error generation" "Not supported,Supported"
newline
bitfld.quad 0x00 5. "DE,Deferred error generation" "Not supported,Supported"
bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,Supported"
bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,Supported"
newline
bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,Supported"
bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Not supported,Supported"
endif
elif (CORENAME()=="CORTEXA55")
if (((per.q(spr:0x30531))&0x01)==0x00)
group.quad spr:0x30F21++0x00
line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register"
bitfld.quad 0x00 31. "CDNEN,Count down enable.Control transfers from the value that is held in the ERR0PFGCDNR into the Error Generation Counter" "Disabled,Enabled"
bitfld.quad 0x00 30. "R,Restartable bit" "Disabled,Enabled"
bitfld.quad 0x00 6. "CE,Corrected error generation enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "DE,Deferred error generation enable" "Disabled,Enabled"
bitfld.quad 0x00 3. "UER,Signaled or Recoverable Error generation" "Disabled,Enabled"
bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
rgroup.quad spr:0x30F20++0x00
line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register"
bitfld.quad 0x00 31. "PGF,Pseudo fault generation" "Not supported,Supported"
bitfld.quad 0x00 30. "R,Restartable bit" "Not supported,Supported"
bitfld.quad 0x00 6. "CE,Corrected error generation" "Not supported,Supported"
newline
bitfld.quad 0x00 5. "DE,Deferred error generation" "Not supported,Supported"
bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..."
bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,Supported"
newline
bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,?..."
bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Not supported,Supported"
else
group.quad spr:0x30F21++0x00
line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register"
bitfld.quad 0x00 31. "CDNEN,Count down enable.Control transfers from the value that is held in the ERR0PFGCDNR into the Error Generation Counter" "Disabled,Enabled"
bitfld.quad 0x00 30. "R,Restartable bit" "Disabled,Enabled"
bitfld.quad 0x00 6. "CE,Corrected error generation enable" "Disabled,Enabled"
newline
bitfld.quad 0x00 5. "DE,Deferred error generation enable" "Disabled,Enabled"
bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
rgroup.quad spr:0x30F20++0x00
line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register"
bitfld.quad 0x00 31. "PGF,Pseudo fault generation" "Not supported,Supported"
bitfld.quad 0x00 30. "R,Restartable bit" "Not supported,Supported"
bitfld.quad 0x00 6. "CE,Corrected error generation" "Not supported,Supported"
newline
bitfld.quad 0x00 5. "DE,Deferred error generation" "Not supported,Supported"
bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,Supported"
bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,Supported"
newline
bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,Supported"
bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Not supported,Supported"
endif
endif
tree.end
tree "Cluster PMU Registers"
group.quad spr:0x30F50++0x00
line.quad 0x00 "CLUSTERPMCR_EL1,Cluster Performance Monitors Control Register (EL1)"
hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.quad 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
bitfld.quad 0x00 1. "P,Event Counter Reset" "No reset,Reset"
newline
bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.quad spr:0x30F51++0x00
line.quad 0x00 "CLUSTERPMCNTENSET_EL1,Cluster Count Enable Set Register (EL1)"
bitfld.quad 0x00 31. "C,Enables the cycle counter register [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.quad 0x00 5. "P5,Event counter PMN 5 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.quad 0x00 4. "P4,Event counter PMN 4 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.quad 0x00 3. "P3,Event counter PMN 3 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.quad 0x00 2. "P2,Event counter PMN 2 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.quad 0x00 1. "P1,Event counter PMN 1 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.quad 0x00 0. "P0,Event counter PMN 0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
group.quad spr:0x30F52++0x00
line.quad 0x00 "CLUSTERPMCNTENCLR_EL1,Cluster Count Enable Clear Register (EL1)"
bitfld.quad 0x00 31. "C,Disables the cycle counter register [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
bitfld.quad 0x00 5. "P5,Event counter PMN 5 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.quad 0x00 4. "P4,Event counter PMN 4 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.quad 0x00 3. "P3,Event counter PMN 3 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
bitfld.quad 0x00 2. "P2,Event counter PMN 2 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.quad 0x00 1. "P1,Event counter PMN 1 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.quad 0x00 0. "P0,Event counter PMN 0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
group.quad spr:0x30F53++0x00
line.quad 0x00 "CLUSTERPMOVSSET_EL1,Cluster Overflow Flag Status Set (EL1)"
bitfld.quad 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Set"
newline
bitfld.quad 0x00 5. "P5,PMN5 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.quad 0x00 4. "P4,PMN4 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.quad 0x00 3. "P3,PMN3 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
newline
bitfld.quad 0x00 2. "P2,PMN2 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.quad 0x00 1. "P1,PMN1 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.quad 0x00 0. "P0,PMN0 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
group.quad spr:0x30F54++0x00
line.quad 0x00 "CLUSTERPMOVSCLR_EL1,Cluster Overflow Flag Status Clear (EL1)"
eventfld.quad 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.quad 0x00 5. "P5,PMN5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.quad 0x00 4. "P4,PMN4 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.quad 0x00 3. "P3,PMN3 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.quad 0x00 2. "P2,PMN2 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.quad 0x00 1. "P1,PMN1 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.quad 0x00 0. "P0,PMN0 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
group.quad spr:0x30F55++0x00
line.quad 0x00 "CLUSTERPMSELR_EL1,Cluster Event Counter Selection Register (EL1)"
bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.quad spr:0x30F56++0x00
line.quad 0x00 "CLUSTERPMINTENSET_EL1,Cluster Interrupt Enable Set Register (EL1)"
bitfld.quad 0x00 31. "C,PMCCNTR Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
group.quad spr:0x30F57++0x00
line.quad 0x00 "CLUSTERPMINTENCLR_EL1,Cluster Interrupt Enable Clear Register (EL1)"
eventfld.quad 0x00 31. "C,PMCCNTR Overflow Interrupt Request Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
if (CORENAME()=="CORTEXA55")
group.quad spr:0x30F60++0x00
line.quad 0x00 "CLUSTERPMCCNTR_EL1,Cluster Performance Monitors Cycle Counter (EL1)"
endif
if (((per.q(spr:0x30F55))&0x1F)<=0x05)
if (((per.q(spr:0x30F61))&0x80000000)==0x00)
group.quad spr:0x30F61++0x00
line.quad 0x00 "CLUSTERPMXEVTYPER_EL1,Cluster Selected Event Type and Filter Register (EL1)"
bitfld.quad 0x00 31. "S,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 28. "N,Count events in non-secure EL2 disable" "No,Yes"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
else
group.quad spr:0x30F61++0x00
line.quad 0x00 "CLUSTERPMXEVTYPER_EL1,Cluster Selected Event Type and Filter Register (EL1)"
bitfld.quad 0x00 31. "S,Count events in EL1 disable" "No,Yes"
bitfld.quad 0x00 28. "N,Count events in non-secure EL2 disable" "Yes,No"
newline
hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
endif
else
rgroup.quad spr:0x30F61++0x00
line.quad 0x00 "CLUSTERPMXEVTYPER_EL1,Cluster Selected Event Type and Filter Register (EL1)"
endif
group.quad spr:0x30F62++0x00
line.quad 0x00 "CLUSTERPMXEVCNTR_EL1,Cluster Selected Event Counter Register (EL1)"
if (CORENAME()=="CORTEXA55")
group.quad spr:0x36F63++0x00
line.quad 0x00 "CLUSTERPMMDCR_EL3,Cluster Monitor Debug Configuration Register (EL3)"
bitfld.quad 0x00 0. "SPME,Secure Performance Monitors Enable" "Disabled,Enabled"
elif (CORENAME()=="CORTEXA76")
rgroup.quad spr:0x36F63++0x00
line.quad 0x00 "CLUSTERPMMDCR_EL3,Cluster Monitor Debug Configuration Register (EL3)"
endif
tree.open "Common Event Identification Registers"
rgroup.quad spr:0x30F64++0x00
line.quad 0x00 "CLUSTERPMCEID0_EL1,Cluster Common Event Identification ID0 Register (EL1)"
bitfld.quad 0x00 30. "CHAIN,Chain" "Reserved,Implemented"
bitfld.quad 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented"
bitfld.quad 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented"
newline
bitfld.quad 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented"
bitfld.quad 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented"
rgroup.quad spr:0x30F65++0x00
line.quad 0x00 "CLUSTERPMCEID1_EL1,Cluster Common Event Identification ID1 Register (EL1)"
bitfld.quad 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Reserved,Implemented"
bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Reserved,Implemented"
bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Reserved,Implemented"
newline
bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented"
tree.end
newline
group.quad spr:0x30F66++0x00
line.quad 0x00 "CLUSTERPMCLAIMSET_EL1,Cluster Performance Monitor Claim Tag Set Register (EL1)"
bitfld.quad 0x00 3. "S[3],Set bit 3 [Read/Write]" "Not implemented/No effect,Implemented/Set"
bitfld.quad 0x00 2. "S[2],Set bit 2 [Read/Write]" "Not implemented/No effect,Implemented/Set"
bitfld.quad 0x00 1. "S[1],Set bit 1 [Read/Write]" "Not implemented/No effect,Implemented/Set"
newline
bitfld.quad 0x00 0. "S[0],Set bit 0 [Read/Write]" "Not implemented/No effect,Implemented/Set"
group.quad spr:0x30F67++0x00
line.quad 0x00 "CLUSTERPMCLAIMCLR_EL1,Cluster Performance Monitor Claim Tag Clear Register (EL1)"
bitfld.quad 0x00 3. "C[3],Clear bit 3 [Read/Write]" "Not implemented/No effect,Implemented/Set"
bitfld.quad 0x00 2. "C[2],Clear bit 2 [Read/Write]" "Not implemented/No effect,Implemented/Set"
bitfld.quad 0x00 1. "C[1],Clear bit 1 [Read/Write]" "Not implemented/No effect,Implemented/Set"
newline
bitfld.quad 0x00 0. "C[0],Clear bit 0 [Read/Write]" "Not implemented/No effect,Implemented/Set"
tree.end
tree.end
tree.end
tree.open "AArch32"
tree "ID Registers"
if corename()=="CORTEXA55"
rgroup.long c15:0x0010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..."
newline
bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Trivial,?..."
bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,After Thumb-2,?..."
newline
bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x0110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..."
newline
bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup.long c15:0x0310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c15:0x0410++0x00
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,HW coherency,?..."
bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,Control/Fault Status,?..."
newline
bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..."
bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,HW coherency,?..."
newline
bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7/PXN/L-DESC,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..."
bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,DSB/ISB/DMB,?..."
newline
bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,S2 operations,?..."
newline
bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
newline
bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..."
bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..."
bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Not required,?..."
newline
bitfld.long 0x00 16.--19. "PAN,Privileged Access Never Support" "Reserved,Reserved,Extended,?..."
bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Shareability/Defined behavior,?..."
bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Invalidate All/VA,?..."
newline
bitfld.long 0x00 4.--7. "CMSW,Cache maintenance by set/way" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "CMMVA,Cache maintenance by MVA" "Reserved,Supported,?..."
rgroup.long c15:0x0620++0x00
line.long 0x00 "ID_MMFR4,Memory Model Feature Register 4"
bitfld.long 0x00 20.--23. "LSM,LSMAOE and NTLSMD bits support" "Not supported,?..."
bitfld.long 0x00 16.--19. "HD,Hierarchical Permission Disables Support" "Reserved,Reserved,Extended,?..."
bitfld.long 0x00 12.--15. "CNP,Common not Private support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 8.--11. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "AC2,Indicates the extension of the HACTLR Register using HACTLR2" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SPECSEI,Describes whether the PE can generate SError interrupt exceptions" "Not possible,?..."
rgroup.long c15:0x0020++0x00
line.long 0x00 "ID_ISAR0,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,T32/A32,?..."
bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..."
rgroup.long c15:0x0120++0x00
line.long 0x00 "ID_ISAR1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,A32-BX like,?..."
bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Full support,?..."
bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0220++0x00
line.long 0x00 "ID_ISAR2,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,UMAAL,?..."
newline
bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..."
newline
bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLDW,?..."
bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0320++0x00
line.long 0x00 "ID_ISAR3,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. "T32EE,Thumb-EE Extensions Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x0420++0x00
line.long 0x00 "ID_ISAR4,Instruction Set Attribute Register 4"
bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..."
newline
bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5"
bitfld.long 0x00 24.--27. "RDM,Rounding Double Multiply Add/Subtract instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "CRC32,Indicates whether CRC32 instructions are implemented in AArch32 state" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "SHA2,Indicates whether SHA2 instructions are implemented in AArch32 state" "Not supported,Supported,?..."
newline
bitfld.long 0x00 8.--11. "SHA1,Indicates whether SHA1 instructions are implemented in AArch32 state" "Not supported,Supported,?..."
bitfld.long 0x00 4.--7. "AES,Indicates whether AES instructions are implemented in AArch32 state" "Not supported,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "SEVL,Indicates whether SEVL instruction is implemented in AArch32" "Reserved,Supported,?..."
rgroup.long c15:0x0720++0x00
line.long 0x00 "ID_ISAR6,Instruction Set Attribute Register 6"
bitfld.long 0x00 4.--7. "DP,Indicates UDOT and SDOT instructions in AArch32 state" "Reserved,Implemented,?..."
rgroup.long c15:0x0210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register"
bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Reserved,Supported/16bit evtCount,?..."
bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..."
newline
bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..."
newline
bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..."
rgroup.long c15:0x0000++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "ARCH,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme"
newline
hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number"
bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x0200++0x00
line.long 0x00 "TCMTR,TCM Type Register"
rgroup.long c15:0x0300++0x00
line.long 0x00 "TLBTR,TLB Type Register"
bitfld.long 0x00 0. "NU,Not Unified TLB" "Unified TLB,Separate Instruction and Data TLBs"
rgroup.long c15:0x0500++0x00
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..."
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Reserved,Implemented"
newline
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Identifies different clusters within the system"
bitfld.long 0x00 8.--15. "AFF1,Affinity level 1. Identifies individual cores within the local FCM cluster" "CORE0,CORE1,CORE2,CORE3,CORE4,CORE5,CORE6,CORE7,?..."
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Identifies individual threads within a multi-threaded core"
rgroup.long c15:0x0400++0x00
line.long 0x00 "MIDR,Main ID Register - alias 2"
hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "ARCH,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme"
newline
hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number"
bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x0600++0x00
line.long 0x00 "REVIDR,Revision ID Register"
rgroup.long c15:0x0700++0x00
line.long 0x00 "MIDR,Main ID Register - alias 3"
hexmask.long.byte 0x00 24.--31. 1. "IMPL,Implementer code"
bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "ARCH,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme"
newline
hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number"
bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x1700++0x00
line.long 0x00 "AIDR,Auxiliary ID Register"
elif corename()=="CORTEXA76"
textline "--------------------------------------------------------------------------------"
newline
textline "            These Registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "System Control and Configuration"
if corename()=="CORTEXA55"
group.long c15:0x0001++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 23. "SPAN,Set Privileged Access Never" "Disabled,Enabled"
bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes"
newline
bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes"
bitfld.long 0x00 13. "V,Base Location of Exception Registers" "VBAR value,0xFFFF0000"
newline
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
rgroup.quad c15:0x100F0++0x01
line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register"
group.quad c15:0x140F0++0x01
line.quad 0x00 "CPUECTLR,CPU Extended Control Register"
bitfld.quad 0x00 38.--39. "ATOM,Force most cacheable atomic instructions to be executed far in the L3 cache or beyond and near in the L1 cache" "Near - hit/unique | Far - miss/shared,Near,Far,Near - load | Far - store"
bitfld.quad 0x00 37. "L2FLUSH,L2 cache flush" "Enabled,Disabled"
newline
bitfld.quad 0x00 29.--30. "L3WSCTL,Write streaming no-L3-allocate threshold" "128th line,1024th line,4096th line,Disabled"
bitfld.quad 0x00 27.--28. "L2WSCTL,Write streaming no-L2-allocate threshold" "16th line,128th line,512th line,Disabled"
newline
bitfld.quad 0x00 25.--26. "L1WSCTL,Write streaming no-L1-allocate threshold" "4th line,64th line,128th line,Disabled"
bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control. Maximum number of outstanding data prefetches allowed in the L1 memory system" "Prefetch disabled,1,2,3,4,5,6,7"
newline
bitfld.quad 0x00 10.--12. "L3PCTL,L3 Data prefetch control. Maximum number of outstanding data prefetches allowed that can be sent to the L3 memory system" "16 lines,32 lines,Reserved,Reserved,Prefetch disabled,2 lines,4 lines,8 lines"
bitfld.quad 0x00 0. "EXTLLC,Type of last-level cache that is present in the system" "Internal,External"
rgroup.long c15:0x608F++0x00
line.long 0x00 "CPUPSELR,CPU Private Selection Register"
rgroup.quad c15:0x180F0++0x01
line.quad 0x00 "CPUPCR,CPU Private Control Register"
rgroup.quad c15:0x1A0F0++0x01
line.quad 0x00 "CPUPMR,CPU Private Mask Register"
rgroup.quad c15:0x190F0++0x01
line.quad 0x00 "CPUPOR,CPU Private Operation Register"
group.long c15:0x0101++0x00
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 12. "CLUSTERPMUEN,Performance Management Registers access control" "Not accessible,Accessible"
bitfld.long 0x00 11. "SMEN,Scheme Management Registers access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible"
bitfld.long 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 5. "ERXPFGEN,Error Record Registers access control" "Not accessible,Accessible"
bitfld.long 0x00 1. "ECTLREN,Extended Control Registers access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 0. "ACTLREN,Auxiliary Control Registers access control" "Not accessible,Accessible"
rgroup.long c15:0x0301++0x00
line.long 0x00 "ACTLR2,Auxiliary Control Register 2"
group.long c15:0x0201++0x00
line.long 0x00 "CPACR,Coprocessor Access Control Register 1"
bitfld.long 0x00 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x00 22.--23. "CP11,Coprocessor access control" "Denied,Privileged,Reserved,Full"
newline
bitfld.long 0x00 20.--21. "CP10,Coprocessor access control" "Denied,Privileged,Reserved,Full"
group.long c15:0x0011++0x00
line.long 0x00 "SCR,Secure Configuration Register"
bitfld.long 0x00 13. "TWE,Traps WFE instructions to Monitor mode" "No trap,Trap"
bitfld.long 0x00 12. "TWI,Traps WFI instructions to Monitor mode" "No trap,Trap"
newline
bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted"
bitfld.long 0x00 8. "HCE,Hypervisor Call instruction enable" "No,Yes"
newline
bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes"
bitfld.long 0x00 6. "NET,Disables early termination" "No,Yes"
newline
bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
newline
bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
newline
bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
bitfld.long 0x00 0. "NS,Secure mode" "Secure,Non-secure"
group.long c15:0x0111++0x00
line.long 0x00 "SDER,Secure Debug Enable Register"
bitfld.long 0x00 1. "SUNIDEN,Secure User Non-Invasive Debug Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "SUIDEN,Secure User Invasive Debug Enable" "Disabled,Enabled"
group.long c15:0x0131++0x00
line.long 0x00 "SDCR,Secure Debug Control Register"
bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors Registers disabled" "No,Yes"
bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint Registers disabled" "No,Yes"
newline
bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled"
bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled"
group.long c15:0x000C++0x00
line.long 0x00 "VBAR,Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
group.long c15:0x010C++0x00
line.long 0x00 "MVBAR,Monitor Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "MVBADDR,Monitor Vector Base Address"
rgroup.long c15:0x001C++0x00
line.long 0x00 "ISR,Interrupt Status Register"
bitfld.long 0x00 8. "A,Asynchronous external abort pending bit" "Not pending,Pending"
bitfld.long 0x00 7. "I,IRQ pending bit" "Not pending,Pending"
newline
bitfld.long 0x00 6. "F,FIQ pending bit" "Not pending,Pending"
group.long c15:0x020C++0x00
line.long 0x00 "RMR,Reset Management Register"
bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested"
bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64"
rgroup.long c15:0x0015++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
rgroup.long c15:0x0115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" ",Uncorrected/Unrecoverable,?..."
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault"
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault status bits" "Reserved,Alignment,Debug,Access flag/L1,Reserved,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..."
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "0,1"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/L1,Permission/section,Sync. external/on TTW/L2,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/L1,Reserved,Sync. parity/on TTW/L2,?..."
else
group.long c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" ",Uncorrected/Unrecoverable,?..."
newline
bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault"
bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Async. SError,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity error/ECC on TTW/L2,Sync. parity error/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,?..."
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid"
bitfld.long 0x00 12. "EXT,External Abort Qualifier" "0,1"
newline
bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
endif
group.long c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group.long c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
rgroup.long c15:0x000D++0x00
line.long 0x00 "FCSEIDR,FCSE PID Register"
endif
group.long c15:0x020D++0x00
line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register"
group.long c15:0x030D++0x00
line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register"
if (CORENAME()=="CORTEXA55")
group.long c15:0x040D++0x00
line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x011C++0x00
line.long 0x00 "DISR,Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor"
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status Code" "Reserved,Alignment,Debug,Access/L1,Instruction,Translation/L1,Access/L2,Translation/L2,External,Domain/L1,Reserved,Domain/L2,External/L1,Permission/L1,External/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,SError interrupt,?..."
group.long c15:0x411C++0x00
line.long 0x00 "VDISR,Virtual Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,?..."
newline
bitfld.long 0x00 0.--3. 10. "FS,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..."
else
group.long c15:0x011C++0x00
line.long 0x00 "DISR,Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Async. SError,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity error/ECC on TTW/L2,Sync. parity error/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,?..."
group.long c15:0x411C++0x00
line.long 0x00 "VDISR,Virtual Deferred Interrupt Status Register"
bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
newline
bitfld.long 0x00 9. "LPAE,Format" ",Long-descriptor"
newline
bitfld.long 0x00 0.--5. "STATUS,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..."
endif
group.long c15:0x4325++0x00
line.long 0x00 "VDFSR,Virtual SError Exception Syndrome Register"
bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..."
endif
tree "System Instructions"
wgroup.long c15:0x0068++0x00
line.long 0x00 "DTLBIALL,DTLBIALL"
wgroup.long c15:0x0268++0x00
line.long 0x00 "DTLBIASID,DTLBIASID"
wgroup.long c15:0x0168++0x00
line.long 0x00 "DTLBIMVA,DTLBIMVA"
wgroup.long c15:0x0058++0x00
line.long 0x00 "ITLBIALL,ITLBIALL"
wgroup.long c15:0x0258++0x00
line.long 0x00 "ITLBIASID,ITLBIASID"
wgroup.long c15:0x0158++0x00
line.long 0x00 "ITLBIMVA,ITLBIMVA"
wgroup.long c15:0x05A7++0x00
line.long 0x00 "CP15DMB,CP15DMB"
wgroup.long c15:0x04A7++0x00
line.long 0x00 "CP15DSB,CP15DSB"
wgroup.long c15:0x0457++0x00
line.long 0x00 "CP15ISB,CP15ISB"
wgroup.long c15:0x0657++0x00
line.long 0x00 "BPIALL,BPIALL"
wgroup.long c15:0x0617++0x00
line.long 0x00 "BPIALLIS,BPIALLIS"
wgroup.long c15:0x0757++0x00
line.long 0x00 "BPIMVA,BPIMVA"
wgroup.long c15:0x0017++0x00
line.long 0x00 "ICIALLUIS,ICIALLUIS"
wgroup.long c15:0x0057++0x00
line.long 0x00 "ICIALLU,ICIALLU"
wgroup.long c15:0x0157++0x00
line.long 0x00 "ICIMVAU,ICIMVAU"
wgroup.long c15:0x3147++0x00
line.long 0x00 "DCZVA,DCZVA"
wgroup.long c15:0x0167++0x00
line.long 0x00 "DCIMVAC,DCIMVAC"
wgroup.long c15:0x0267++0x00
line.long 0x00 "DCISW,DCISW"
wgroup.long c15:0x01A7++0x00
line.long 0x00 "DCCMVAC,DCCMVAC"
wgroup.long c15:0x02A7++0x00
line.long 0x00 "DCCSW,DCCSW"
wgroup.long c15:0x01B7++0x00
line.long 0x00 "DCCMVAU,DCCMVAU"
wgroup.long c15:0x01E7++0x00
line.long 0x00 "DCCIMVAC,DCCIMVAC"
wgroup.long c15:0x02E7++0x00
line.long 0x00 "DCCISW,DCCISW"
wgroup.long c15:0x0087++0x00
line.long 0x00 "ATS1CPR,ATS1CPR"
wgroup.long c15:0x0097++0x00
line.long 0x00 "ATS1CPRP,ATS1CPRP"
wgroup.long c15:0x0187++0x00
line.long 0x00 "ATS1CPW,ATS1CPW"
wgroup.long c15:0x0197++0x00
line.long 0x00 "ATS1CPWP,ATS1CPWP"
wgroup.long c15:0x0287++0x00
line.long 0x00 "ATS1CUR,ATS1CUR"
wgroup.long c15:0x0387++0x00
line.long 0x00 "ATS1CUW,ATS1CUW"
wgroup.long c15:0x0487++0x00
line.long 0x00 "ATS12NSOPR,ATS12NSOPR"
wgroup.long c15:0x0587++0x00
line.long 0x00 "ATS12NSOPW,ATS12NSOPW"
wgroup.long c15:0x0687++0x00
line.long 0x00 "ATS12NSOUR,ATS12NSOUR"
wgroup.long c15:0x0787++0x00
line.long 0x00 "ATS12NSOUW,ATS12NSOUW"
wgroup.long c15:0x4087++0x00
line.long 0x00 "ATS1HR,ATS1HR"
wgroup.long c15:0x4187++0x00
line.long 0x00 "ATS1HW,ATS1HW"
wgroup.long c15:0x0078++0x00
line.long 0x00 "TLBIALL,TLBIALL"
wgroup.long c15:0x0178++0x00
line.long 0x00 "TLBIMVA,TLBIMVA"
wgroup.long c15:0x4178++0x00
line.long 0x00 "TLBIMVAH,Invalidate Hyp unified TLB entry by MVA"
wgroup.long c15:0x0278++0x00
line.long 0x00 "TLBIASID,TLBIASID"
wgroup.long c15:0x0378++0x00
line.long 0x00 "TLBIMVAA,TLBIMVAA"
wgroup.long c15:0x0578++0x00
line.long 0x00 "TLBIMVAL,TLBIMVAL"
wgroup.long c15:0x0778++0x00
line.long 0x00 "TLBIMVAAL,TLBIMVAAL"
wgroup.long c15:0x0038++0x00
line.long 0x00 "TLBIALLIS,TLBIALLIS"
wgroup.long c15:0x0138++0x00
line.long 0x00 "TLBIMVAIS,TLBIMVAIS"
wgroup.long c15:0x0238++0x00
line.long 0x00 "TLBIASIDIS,TLBIASIDIS"
wgroup.long c15:0x0338++0x00
line.long 0x00 "TLBIMVAAIS,TLBIMVAAIS"
wgroup.long c15:0x0538++0x00
line.long 0x00 "TLBIMVALIS,TLBIMVALIS"
wgroup.long c15:0x0738++0x00
line.long 0x00 "TLBIMVAALI,TLBIMVAALI"
wgroup.long c15:0x4108++0x00
line.long 0x00 "TLBIIPAS2IS,TLBIIPAS2IS"
wgroup.long c15:0x4508++0x00
line.long 0x00 "TLBIIPAS2LIS,TLBIIPAS2LIS"
wgroup.long c15:0x4148++0x00
line.long 0x00 "TLBIIPAS2,TLBIIPAS2"
wgroup.long c15:0x4548++0x00
line.long 0x00 "TLBIIPAS2L,TLBIIPAS2L"
wgroup.long c15:0x4178++0x00
line.long 0x00 "TLBIIPAS2L,TLBIIPAS2L"
wgroup.long c15:0x4578++0x00
line.long 0x00 "TLBIMVALH,TLBIMVALH"
wgroup.long c15:0x4138++0x00
line.long 0x00 "TLBIMVAHIS,TLBIMVAHIS"
wgroup.long c15:0x4538++0x00
line.long 0x00 "TLBIMVALHIS,TLBIMVALHIS"
wgroup.long c15:0x4078++0x00
line.long 0x00 "TLBIALLH,TLBIALLH"
wgroup.long c15:0x4038++0x00
line.long 0x00 "TLBIALLHIS,TLBIALLHIS"
wgroup.long c15:0x4478++0x00
line.long 0x00 "TLBIALLNSNH,TLBIALLNSNH"
wgroup.long c15:0x4438++0x00
line.long 0x00 "TLBIALLNSNHIS,TLBIALLNSNHIS"
tree.end
tree.end
tree "Memory Management Unit"
if corename()=="CORTEXA55"
group.long c15:0x0001++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32"
bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 23. "SPAN,Set Privileged Access Never" "Disabled,Enabled"
bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced"
newline
bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced"
bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes"
newline
bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes"
bitfld.long 0x00 13. "V,Base Location of Exception Registers" "VBAR value,0xFFFF0000"
newline
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
newline
bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled"
group.long c15:0x4001++0x00
line.long 0x00 "HSCTLR,Hyp System Control Register"
bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced"
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT instruction functionality Disabled" "No,?..."
newline
bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x00 0. "M,Enable address translation" "Disabled,Enabled"
if (((per.l(c15:0x0202))&0x80000000)==0x00000000)
group.long c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Register"
hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base address"
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable"
group.long c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Register"
hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base address"
bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner"
bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes"
newline
bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes"
bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7"
else
group.quad c15:0x10020++0x01
line.quad 0x00 "TTBR0,Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 1. "BADDR,Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.quad c15:0x11020++0x01
line.quad 0x00 "TTBR1,Translation Table Base Register"
hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address"
hexmask.quad 0x00 1.--47. 1. "BADDR,Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.long c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit"
bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes"
bitfld.long 0x00 22. "A1,Selects whether TTBR0 or TTBR1 defines the ASID" "TTBR0,TTBR1"
newline
bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes"
bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7"
endif
group.long c15:0x0302++0x00
line.long 0x00 "TTBCR2,Translation Table Base Control Register 2"
bitfld.long 0x00 18. "HWU162,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible"
bitfld.long 0x00 17. "HWU161,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible"
newline
bitfld.long 0x00 16. "HWU160,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible"
bitfld.long 0x00 15. "HWU159,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible"
newline
bitfld.long 0x00 14. "HWU062,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
bitfld.long 0x00 13. "HWU061,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
newline
bitfld.long 0x00 12. "HWU060,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
bitfld.long 0x00 11. "HWU059,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
newline
bitfld.long 0x00 10. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes"
bitfld.long 0x00 9. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes"
group.long c15:0x007F++0x00
line.long 0x00 "ATTBCR,Auxiliary Translation Table Base Control Register"
bitfld.long 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1"
bitfld.long 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1"
newline
bitfld.long 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1"
bitfld.long 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1"
newline
bitfld.long 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
bitfld.long 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
bitfld.long 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hyp Translation Table Base Register"
hexmask.quad 0x00 1.--47. 0x02 "BADDR,Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hyp Translation Control Register"
bitfld.long 0x00 28. "HWU062,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
bitfld.long 0x00 27. "HWU061,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
newline
bitfld.long 0x00 26. "HWU060,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
bitfld.long 0x00 25. "HWU059,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible"
newline
bitfld.long 0x00 24. "HPD,Hierarchical Permission Disables" "No,Yes"
bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through no Write-Allocate Cacheable,Write-Back no Write-Allocate Cacheable"
bitfld.long 0x00 8.--9. "IRGN0,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through no Write-Allocate Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 0.--2. "T0SZ,The size offset of the memory region addressed by HTTBR" "0,1,2,3,4,5,6,7"
group.long c15:0x0003++0x00
line.long 0x00 "DACR,Domain Access Control Register"
bitfld.long 0x00 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager"
newline
bitfld.long 0x00 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x00 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager"
if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x01)==0x00))
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address"
bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,?..."
newline
bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "Outer,Inner"
bitfld.long 0x00 9. "NS,Non-secure" "No,Yes"
newline
bitfld.long 0x00 7. "SH,Shareability attribute for the region" "No,Yes"
bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Device-nGnRnE,Reserved,Device-nGnRE,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate"
newline
bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate"
bitfld.long 0x00 1. "SS,Used to indicate if the result is a Supersection" "No,Yes"
newline
bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x01)==0x01))
group.long c15:0x0047++0x00
line.long 0x00 "PAR,Physical Address Register"
bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,?..."
newline
bitfld.long 0x00 6. "FS[5],Fault status bit [5] - External abort type" "Internal,External"
newline
bitfld.long 0x00 1.--5. "FS[4:0],Fault status bit [4:0] - Abort source" "Reserved,Alignment,Debug,Access/L1,Instruction,Translation/L1,Access/L2,Translation/L2,External,Domain/L1,Reserved,Domain/L2,External/L1,Permission/L1,External/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive access,SError interrupt,?..."
newline
bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x01)==0x00))
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA"
hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address"
newline
bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" ",Long"
newline
bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes"
newline
bitfld.quad 0x00 7.--8. "SH,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
else
group.quad c15:0x10070++0x01
line.quad 0x00 "PAR,Physical Address Register"
bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" ",Long"
newline
bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2"
newline
bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes"
newline
bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size/TTBR,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC/on TTW/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..."
newline
bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted"
endif
rgroup.long c15:0x003A++0x00
line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0"
rgroup.long c15:0x013A++0x00
line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1"
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
else
rgroup.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0"
rgroup.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1"
endif
rgroup.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0"
rgroup.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1"
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x002A++0x00
line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.long c15:0x012A++0x00
line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
else
group.long c15:0x002A++0x00
line.long 0x00 "PRRR,Primary Region Remap Register"
bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner"
newline
bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "Not shareable,Shareable"
newline
bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "Not shareable,Shareable"
newline
bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "Not shareable,Shareable"
newline
bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "Not shareable,Shareable"
newline
bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
newline
bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..."
group.long c15:0x012A++0x00
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
newline
bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-Back Allocate,Write-Through no Allocate,Write-Back no Allocate"
endif
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x010D++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
else
group.long c15:0x010D++0x00
line.long 0x00 "CONTEXTIDR,Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process Identifier"
hexmask.long.byte 0x00 0.--7. 1. "ASID,Address Space Identifier"
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These Registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Virtualization Extensions"
if (CORENAME()=="CORTEXA55")
group.long c15:0x4000++0x00
line.long 0x00 "VPIDR,Virtualization Processor ID Register"
hexmask.long.byte 0x00 24.--31. 0x01 "IMPL,Implementer code"
bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "ARCH,Architecture" "0,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,8,9,10,11,12,13,14,CPUID scheme"
hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number"
newline
bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x4500++0x00
line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Register"
bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor"
bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented"
newline
hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Identifies different clusters within the system"
hexmask.long.byte 0x00 8.--15. 1. "AFF1,Affinity level 1. Identifies individual cores within the local FCM cluster"
newline
hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Identifies individual threads within a multi-threaded core"
group.long c15:0x420D++0x00
line.long 0x00 "HTPIDR,Hyp Software Thread ID Register"
group.long c15:0x4001++0x00
line.long 0x00 "HSCTLR,Hyp System Control Register"
bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32"
bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big"
newline
bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced"
bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes"
bitfld.long 0x00 7. "ITD,IT instruction functionality Disabled" "No,?..."
newline
bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled"
bitfld.long 0x00 0. "M,Enable address translation" "Disabled,Enabled"
group.long c15:0x4101++0x00
line.long 0x00 "HACTLR,Hyp Auxiliary Control Register"
bitfld.long 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible"
bitfld.long 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible"
bitfld.long 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible"
bitfld.long 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible"
newline
bitfld.long 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible"
rgroup.long c15:0x4301++0x00
line.long 0x00 "HACTLR2,Hyp Auxiliary Control Register 2"
rgroup.long c15:0x4711++0x00
line.long 0x00 "HACR,Hyp Auxiliary Configuration Register"
group.long c15:0x4011++0x00
line.long 0x00 "HCR,Hyp Configuration Register"
bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "No trap,Trap"
bitfld.long 0x00 27. "TGE,Trap General Exceptions from Non-secure EL0" "No trap,Trap"
newline
bitfld.long 0x00 26. "TVM,Trap Virtual Memory controls" "No trap,Trap"
bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "No trap,Trap"
newline
bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification" "No trap,Trap"
bitfld.long 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency" "No trap,Trap"
newline
bitfld.long 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way" "No trap,Trap"
bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register" "No trap,Trap"
newline
bitfld.long 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "No trap,Trap"
bitfld.long 0x00 19. "TSC,Trap SMC" "No trap,Trap"
newline
bitfld.long 0x00 18. "TID3,Trap ID Group 3" "No trap,Trap"
bitfld.long 0x00 17. "TID2,Trap ID Group 2" "No trap,Trap"
newline
bitfld.long 0x00 16. "TID1,Trap ID Group 1" "No trap,Trap"
bitfld.long 0x00 15. "TID0,Trap ID Group 0" "No trap,Trap"
newline
bitfld.long 0x00 14. "TWE,Trap WFE" "No trap,Trap"
bitfld.long 0x00 13. "TWI,Trap WFI" "No trap,Trap"
newline
bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "BSU,Barrier Shareability upgrade" "No effect,Inner Shareable,Outer Shareable,Full System"
newline
bitfld.long 0x00 9. "FB,Force broadcast" "Not forced,Forced"
bitfld.long 0x00 8. "VA,Virtual Asynchronous Abort exception" "Not pending,Pending"
newline
bitfld.long 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending"
bitfld.long 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending"
newline
bitfld.long 0x00 5. "AMO,Asynchronous Abort Mask Override" "Disabled,Enabled"
bitfld.long 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled"
bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled"
bitfld.long 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled"
group.long c15:0x4411++0x00
line.long 0x00 "HCR2,Hyp Configuration Register"
bitfld.long 0x00 5. "TEA,Route synchronous external aborts to EL2" "Not routed,Routed"
bitfld.long 0x00 4. "TERR,Trap Error record accesses" "No trap,Trap"
newline
bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes"
bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes"
endif
group.long c15:0x3054++0x00
line.long 0x00 "DSPSR,Debug Saved Program Status Register"
bitfld.long 0x00 31. "N,Negative condition flag" "Not negative,Negative"
bitfld.long 0x00 30. "Z,Zero condition flag" "Not zero,Zero"
newline
bitfld.long 0x00 29. "C,Carry condition flag" "Not carry,Carry"
bitfld.long 0x00 28. "V,Overflow condition flag" "No overflow,Overflow"
newline
bitfld.long 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred"
bitfld.long 0x00 23. "SSBS,Speculative store bypass" "0,1"
newline
bitfld.long 0x00 22. "PAN,Privileged access never" "No,Yes"
bitfld.long 0x00 21. "SS,Software step" "0,1"
newline
bitfld.long 0x00 20. "IL,Illegal Execution state" "0,1"
bitfld.long 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 9. "E,Endianness state bit" "Little,Big"
bitfld.long 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 7. "I,IRQ mask bit" "Not masked,Masked"
bitfld.long 0x00 6. "F,FIQ mask bit" "Not masked,Masked"
newline
bitfld.long 0x00 5. "T,T32 Instruction set state" "A32,T32"
bitfld.long 0x00 4. "M[4],Execution state that the exception was taken from" "Reserved,AArch32"
newline
bitfld.long 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,Reserved,Reserved,Monitor,Abort,Reserved,Reserved,Hyp,Undefined,Reserved,Reserved,Reserved,System"
group.long c15:0x4111++0x00
line.long 0x00 "HDCR,Hyp Debug Control Register"
bitfld.long 0x00 17. "HPMD,Guest Performance Monitors Disable" "Allowed,Prohibited"
bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No trap,Trap"
newline
bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related Register Access" "No trap,Trap"
bitfld.long 0x00 9. "TDA,Trap Debug Access" "No trap,Trap"
newline
bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No trap,Trap"
bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No trap,Trap"
bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No trap,Trap"
newline
bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if corename()=="CORTEXA55"
group.long c15:0x4211++0x00
line.long 0x00 "HCPTR,Hyp Coprocessor Trap Register"
bitfld.long 0x00 31. "TCPAC,Trap Coprocessor Access Control" "No trap,Trap"
bitfld.long 0x00 20. "TTA,Traps Non-secure System Register accesses to all implemented trace Registers to Hyp mode" "No trap,Trap"
newline
bitfld.long 0x00 15. "TASE,Trap Advanced SIMD extensions" "No trap,Trap"
bitfld.long 0x00 11. "TCP11,Trap coprocessor 11" "No trap,Trap"
newline
bitfld.long 0x00 10. "TCP10,Trap coprocessor 10" "No trap,Trap"
group.quad c15:0x14020++0x01
line.quad 0x00 "HTTBR,Hyp Translation Table Base Register"
hexmask.quad 0x00 1.--47. 0x02 "BADDR,Translation table base address"
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported"
group.long c15:0x4202++0x00
line.long 0x00 "HTCR,Hyp Translation Control Register"
bitfld.long 0x00 28. "HWU62,Hardware usage of bit[62] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.long 0x00 27. "HWU61,Hardware usage of bit[61] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.long 0x00 26. "HWU60,Hardware usage of bit[60] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
bitfld.long 0x00 25. "HWU59,Hardware usage of bit[59] of the stage2 translation table block or level 3 entry" "Not possible,Possible"
newline
bitfld.long 0x00 24. "HPD,Hierarchical Permission Disables" "No,Yes"
newline
bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through no Write-Allocate Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through no Write-Allocate Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 0.--2. "T0SZ,The size offset of the memory region addressed by HTTBR" "0,1,2,3,4,5,6,7"
group.long c15:0x407F++0x00
line.long 0x00 "AHTCR,Auxiliary Hypervisor Translation Control Register"
bitfld.long 0x00 9. "HWVAL60,Indicates the value of PBHA[1] page table walks memory access if HWEN60 is set" "0,1"
bitfld.long 0x00 8. "HWVAL59,Indicates the value of PBHA[1] page table walks memory access if HWEN59 is set" "0,1"
newline
bitfld.long 0x00 1. "HWEN60,Enables PBHA[1] page table walks memory access" "Disabled,Enabled"
bitfld.long 0x00 0. "HWEN59,Enables PBHA[0] page table walks memory access" "Disabled,Enabled"
group.quad c15:0x16020++0x01
line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register"
hexmask.quad.word 0x00 48.--63. 1. "VMID,VMID for the translation table base address"
newline
hexmask.quad 0x00 2.--47. 0x04 "BADDR,Translation table base address"
newline
bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,?..."
group.long c15:0x4212++0x00
line.long 0x00 "VTCR,Virtualization Translation Control Register"
bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable"
newline
bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 8.--9. "IRGN0,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable"
newline
bitfld.long 0x00 6.--7. "SL0,Starting level for translation table walks using VTTBR" "L2,L1,?..."
newline
bitfld.long 0x00 4. "S,Sign extension bit" "0,1"
newline
bitfld.long 0x00 0.--3. "T0SZ,Size offset of the memory region addressed by TTBR0" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1"
newline
group.long c15:0x417F++0x00
line.long 0x00 "AVTCR,Auxiliary Virtualized Translation Control Register"
bitfld.long 0x00 9. "HWVAL60,Indicates the value of PBHA[1] page table walks memory access if HWEN60 is set" "0,1"
newline
bitfld.long 0x00 8. "HWVAL59,Indicates the value of PBHA[1] page table walks memory access if HWEN59 is set" "0,1"
newline
bitfld.long 0x00 1. "HWEN60,Enables PBHA[1] page table walks memory access" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "HWEN59,Enables PBHA[0] page table walks memory access" "Disabled,Enabled"
rgroup.long c15:0x4015++0x00
line.long 0x00 "HADFSR,Hyp Auxiliary Data Fault Status Syndrome Register"
rgroup.long c15:0x4115++0x00
line.long 0x00 "HAIFSR,Hyp Auxiliary Instruction Fault Status Register"
group.long c15:0x4006++0x00
line.long 0x00 "HDFAR,Hyp Data Fault Address Register"
endif
group.long c15:0x3154++0x00
line.long 0x00 "DLR,Debug Link Register"
if corename()=="CORTEXA55"
if (((per.l(c15:0x4025))&0xFC000000)==(0x00||0x38000000||0x88000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
elif (((per.l(c15:0x4025))&0xFC000000)==0x4000000)
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE"
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0xC000000||0x14000000||0x20000000))
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 17.--19. "OPC2,The Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCR,MRC/VMRS"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 17.--19. "OPC2,The Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 14.--16. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCR,MRC/VMRS"
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000))
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--13. "RT2,The Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCRR,MRRC"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 16.--19. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 10.--13. "RT2,The Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCRR,MRRC"
endif
elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000)
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
if (((per.l(c15:0x4025))&0x08)==0x00)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.long 0x00 5.--8. "RN,The Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
newline
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..."
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
newline
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..."
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC"
endif
else
if (((per.l(c15:0x4025))&0x08)==0x00)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.long 0x00 5.--8. "RN,The Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
newline
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..."
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction"
newline
bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added"
newline
bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..."
bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC"
endif
endif
elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000)
if (((per.l(c15:0x4025))&0x1000000)==0x1000000)
if (((per.l(c15:0x4025))&0x20)==0x20)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred"
newline
bitfld.long 0x00 0.--3. "COPROC,The number of the coprocessor accessed by the trapped operation" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CP10,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred"
endif
else
if (((per.l(c15:0x4025))&0x20)==0x20)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred"
newline
bitfld.long 0x00 0.--3. "COPROC,The number of the coprocessor accessed by the trapped operation" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CP10,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred"
endif
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x48000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction"
elif (((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))
if (((per.l(c15:0x4025))&0x3F)==0x10)
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
bitfld.long 0x00 10. "FNV,FAR not Valid" "HIFAR valid,HIFAR invalid"
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SEA/On TTBW lvl1,SEAOn TTBW lvl2,SEA/On TTBW lvl3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug (only from Hyp mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
newline
bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SEA/On TTBW lvl1,SEAOn TTBW lvl2,SEA/On TTBW lvl3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Debug (only from Hyp mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,?..."
endif
elif (((per.l(c15:0x4025))&0xFD000000)==(0x91000000||0x95000000))
if (((per.l(c15:0x4025))&0x3F)==(0x11))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
newline
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
newline
bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present"
newline
bitfld.long 0x00 10.--11. "AET,Asynchronous Error Type" "UC,UEU,UEO/CE,UER"
newline
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
newline
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/On TTBW lvl1,SEA/On TTBW lvl2,SEA/On TTBW lvl3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug (only from Hyp mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
newline
bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword"
bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required"
newline
bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present"
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "Valid,Invalid"
newline
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
newline
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/On TTBW lvl1,SEA/On TTBW lvl2,SEA/On TTBW lvl3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug (only from Hyp mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0x90000000||0x94000000))
if (((per.l(c15:0x4025))&0x3F)==(0x11))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
newline
newline
newline
bitfld.long 0x00 10.--11. "AET,Asynchronous Error Type" "UC,UEU,UEO/CE,UER"
newline
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
newline
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/On TTBW lvl1,SEA/On TTBW lvl2,SEA/On TTBW lvl3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug (only from Hyp mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid"
newline
newline
newline
bitfld.long 0x00 10. "FNV,FAR not Valid" "Valid,Invalid"
newline
bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated"
bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred"
newline
bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write"
bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/On TTBW lvl1,SEA/On TTBW lvl2,SEA/On TTBW lvl3,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Alignment fault,Debug (only from Hyp mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..."
endif
elif (((per.l(c15:0x4025))&0xFC000000)==(0x4C000000))
if (((per.l(c15:0x4025))&0x80000)==(0x80000))
if (((per.l(c15:0x4025))&0x1000000)==(0x1000000))
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional"
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid"
newline
bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional"
endif
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
newline
bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional"
endif
else
group.long c15:0x4025++0x00
line.long 0x00 "HSR,Hyp Syndrome Register"
bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC,Trapped advanced SIMD or floating-point,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hyp mode Instruction Abort,Executing within Hyp mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hyp mode Data Abort,Executing within Hyp mode Data Abort,?..."
newline
bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit"
endif
rgroup.long c15:0x4115++0x00
line.long 0x00 "HAIFSR,Hyp Auxiliary Instruction Fault Status Register"
group.long c15:0x4206++0x00
line.long 0x00 "HIFAR,Hyp Instruction Fault Address Register"
group.long c15:0x4406++0x00
line.long 0x00 "HPFAR,Hyp IPA Fault Address Register"
hexmask.long 0x00 4.--31. 0x10 "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address"
if (((per.l(c15:0x0202))&0x80000000)==0x80000000)
group.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0"
bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
group.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1"
bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient/W allocate,Normal Memory/Outer Write-through transient/R allocate,Normal Memory/Outer Write-through transient/RW allocate,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient/W allocate,Normal Memory/Outer Write-back transient/R allocate,Normal Memory/Outer Write-back transient/RW allocate,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient/W allocate,Normal Memory/Outer Write-through non-transient/R allocate,Normal Memory/Outer Write-through non-transient/RW allocate,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient/W allocate,Normal Memory/Outer Write-back non-transient/R allocate,Normal Memory/Outer Write-back non-transient/RW allocate"
newline
bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient/W allocate,---/Inner Write-through transient/R allocate,---/Inner Write-through transient/RW allocate,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient/W allocate,---/Inner Write-back transient/R allocate,---/Inner Write-back transient/RW allocate,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient/W allocate,---/Inner Write-through non-transient/R allocate,---/Inner Write-through non-transient/RW allocate,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient/W allocate,---/Inner Write-back non-transient/R allocate,---/Inner Write-back non-transient/RW allocate"
else
rgroup.long c15:0x402A++0x00
line.long 0x00 "HMAIR0,Hyp Memory Attribute Indirection Register 0"
rgroup.long c15:0x412A++0x00
line.long 0x00 "HMAIR1,Hyp Memory Attribute Indirection Register 1"
endif
rgroup.long c15:0x403A++0x00
line.long 0x00 "HAMAIR0,Hyp Auxiliary Memory Attribute Indirection Register 0"
rgroup.long c15:0x413A++0x00
line.long 0x00 "HAMAIR1,Hyp Auxiliary Memory Attribute Indirection Register 1"
group.long c15:0x400C++0x00
line.long 0x00 "HVBAR,Hyp Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address"
endif
tree.end
tree "Cache Control and Configuration"
if corename()=="CORTEXA55"
rgroup.long c15:0x000F++0x00
line.long 0x00 "CPUCFR,CPU Configuration Register"
bitfld.long 0x00 2. "SCU,Indicates whether the SCU is present or not" "Present,?..."
bitfld.long 0x00 0.--1. "ECC,Indicates whether ECC is present or not" "Not present,Present,?..."
group.long c15:0x072F++0x00
line.long 0x00 "CPUPWRCTLR,Power Control Register"
bitfld.long 0x00 10.--12. "SIMD_RET_CTRL,Advanced SIMD and floating-point retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.long 0x00 7.--9. "WFE_RET_CTRL,CPU WFE retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
newline
bitfld.long 0x00 4.--6. "WFI_RET_CTRL,CPU WFI retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
bitfld.long 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFI state" "Not requested,Requested"
rgroup.long c15:0x0100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
newline
bitfld.long 0x00 14.--15. "VIPT,Instruction cache policy" "Reserved,Reserved,VIPT,?..."
bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..."
if (((per.l(c15:0x2000))&0x0F)>=0x04)
group.long c15:0x2000++0x00
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
elif (((per.l(c15:0x2000))&0xE)==0x02)
group.long c15:0x2000++0x00
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,?..."
elif (((per.l(c15:0x2000))&0x01)==0x01)
group.long c15:0x2000++0x00
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Reserved,Level 3,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
else
group.long c15:0x2000++0x00
line.long 0x00 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..."
bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction"
endif
rgroup.long c15:0x1000++0x00
line.long 0x00 "CCSIDR,Cache size ID Register"
bitfld.long 0x00 31. "WT,Write-Through" "Not supported,?..."
bitfld.long 0x00 30. "WB,Write-Back" "Not supported,Supported"
newline
bitfld.long 0x00 29. "RA,Read-Allocate" "Not supported,Supported"
bitfld.long 0x00 28. "WA,Write-Allocate" "Not supported,Supported"
newline
hexmask.long.word 0x00 13.--27. 1. "SETS,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. "ASSOC,Associativity"
newline
bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..."
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Reserved,Reserved,L2 highest,L3 highest"
newline
bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "No levels,?..."
bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,L3 not implemented,L2 and L3 implemented,?..."
newline
bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Clean/Invalidate not required,?..."
bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "L3 not implemented,Reserved,Reserved,Reserved,L3 implemented,?..."
newline
bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified L2 cache,?..."
bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..."
elif corename()=="CORTEXA76"
textline "--------------------------------------------------------------------------------"
newline
textline "            These Registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree "Level 1 memory system"
if corename()=="CORTEXA55"
rgroup.long c15:0x600F++0x00
line.long 0x00 "CDBGDR0,Data Register 0"
rgroup.long c15:0x610F++0x00
line.long 0x00 "CDBGDR1,Data Register 1"
rgroup.long c15:0x620F++0x00
line.long 0x00 "CDBGDR2,Data Register 2"
wgroup.long c15:0x602F++0x00
line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register"
bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.long.word 0x00 6.--13. 1. "SETIND,Set index"
wgroup.long c15:0x612F++0x00
line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register"
bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.long.word 0x00 6.--13. 1. "SETIND,Set index"
wgroup.long c15:0x622F++0x00
line.long 0x00 "CDBGTT,TLB Tag Read Operation Register"
bitfld.long 0x00 30.--31. "TLBW,TLB way" "0,1,2,3"
hexmask.long.word 0x00 0.--8. 1. "TLBINDEX,TLB index"
wgroup.long c15:0x604F++0x00
line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register"
bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.long.word 0x00 6.--13. 1. "SETIND,Set index"
bitfld.long 0x00 3.--5. "CDDO,Cache doubleword data offset" "0,1,2,3,4,5,6,7"
wgroup.long c15:0x614F++0x00
line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register"
bitfld.long 0x00 30.--31. "CW,Cache way" "0,1,2,3"
hexmask.long.word 0x00 6.--13. 1. "SETIND,Set index"
bitfld.long 0x00 2.--5. "CDDO,Cache doubleword data offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.long c15:0x624F++0x00
line.long 0x00 "CDBGTD,TLB Data Read Operation Register"
bitfld.long 0x00 30.--31. "TLBW,TLB way" "0,1,2,3"
hexmask.long.word 0x00 0.--8. 1. "TLBINDEX,TLB index"
elif corename()=="CORTEXA76"
textline "--------------------------------------------------------------------------------"
newline
textline "            These Registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree.end
tree "System Performance Monitor"
group.long c15:0x00C9++0x00
line.long 0x00 "PMCR,Performance Monitors Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
rbitfld.long 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
bitfld.long 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes"
bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset"
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
group.long c15:0x01C9++0x00
line.long 0x00 "PMCNTENSET,Performance Monitors Count Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled"
group.long c15:0x02C9++0x00
line.long 0x00 "PMCNTENCLR,Performance Monitors Count Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled"
group.long c15:0x03C9++0x00
line.long 0x00 "PMOVSR,Performance Monitors Overflow Status Flags Register"
eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow"
eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow"
eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow"
eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow"
newline
eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow"
wgroup.long c15:0x04C9++0x00
line.long 0x00 "PMSWINC,Performance Monitors Software Increment Register"
bitfld.long 0x00 5. "P5,PMN5 software increment" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMN4 software increment" "Disabled,Enabled"
bitfld.long 0x00 3. "P3,PMN3 software increment" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "P2,PMN2 software increment" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,PMN1 software increment" "Disabled,Enabled"
bitfld.long 0x00 0. "P0,PMN0 software increment" "Disabled,Enabled"
group.long c15:0x05C9++0x00
line.long 0x00 "PMSELR,Performance Monitors Event Counter Selection Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.open "Common Event Identification Registers"
if corename()=="CORTEXA76"
rgroup.long c15:0x06C9++0x00
line.long 0x00 "PMCEID0,Performance Monitors Common Event Identification Register"
bitfld.long 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,?..."
bitfld.long 0x00 30. "CHAIN,Chain" "Reserved,Implemented"
bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented"
newline
bitfld.long 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Reserved,Implemented"
bitfld.long 0x00 27. "INST_SPEC,Instruction speculatively executed" "Reserved,Implemented"
bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented"
newline
bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented"
bitfld.long 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Reserved,Implemented"
bitfld.long 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Reserved,Implemented"
newline
bitfld.long 0x00 22. "L2D_CACHE,Level 2 data cache access" "Reserved,Implemented"
bitfld.long 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Reserved,Implemented"
bitfld.long 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Reserved,Implemented"
newline
bitfld.long 0x00 19. "MEM_ACCESS,Data memory access" "Reserved,Implemented"
bitfld.long 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Reserved,Implemented"
bitfld.long 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented"
newline
bitfld.long 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented"
bitfld.long 0x00 15. "UNALIGNED_LDST_RETIRED,Unaligned load or store" "Not implemented,?..."
bitfld.long 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,?..."
newline
bitfld.long 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,?..."
bitfld.long 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,?..."
bitfld.long 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented"
newline
bitfld.long 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented"
bitfld.long 0x00 9. "EXC_TAKEN,Exception taken" "Reserved,Implemented"
bitfld.long 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Reserved,Implemented"
newline
bitfld.long 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,?..."
bitfld.long 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,?..."
bitfld.long 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Reserved,Implemented"
newline
bitfld.long 0x00 4. "L1D_CACHE,Level 1 data cache access" "Reserved,Implemented"
bitfld.long 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Reserved,Implemented"
bitfld.long 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Reserved,Implemented"
newline
bitfld.long 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Reserved,Implemented"
bitfld.long 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented"
rgroup.long c15:0x07C9++0x00
line.long 0x00 "PMCEID1,Common Event Identification Register"
bitfld.long 0x00 23. "LL_CACHE_MISS_RD,Attributable Last Level cache memory read miss" "Reserved,Implemented"
bitfld.long 0x00 22. "LL_CACHE_RD,Attributable Last Level cache memory read" "Reserved,Implemented"
bitfld.long 0x00 21. "ITLB_WALK,Attributable instruction TLB access with at least one translation table walk" "Reserved,Implemented"
newline
bitfld.long 0x00 20. "DTLB_WALK,Attributable data or unified TLB access with at least one translation table walk" "Reserved,Implemented"
bitfld.long 0x00 17. "REMOTE_ACCESS,Attributable access to another socket in a multi-socket system" "Reserved,Implemented"
bitfld.long 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Reserved,Implemented"
newline
bitfld.long 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Reserved,Implemented"
bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data cache access" "Reserved,Implemented"
bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data cache refill" "Reserved,Implemented"
newline
bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented"
bitfld.long 0x00 6. "L1I_TLB,Attributable Level 1 instruction TLB access" "Reserved,Implemented"
bitfld.long 0x00 5. "L1D_TLB,Attributable Level 1 data or unified TLB access" "Reserved,Implemented"
newline
bitfld.long 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Reserved,Implemented"
bitfld.long 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Reserved,Implemented"
bitfld.long 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Reserved,Implemented"
newline
bitfld.long 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Reserved,Implemented"
bitfld.long 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocation without refill" "Reserved,Implemented"
elif corename()=="CORTEXA55"
rgroup.long c15:0x06C9++0x00
line.long 0x00 "PMCEID0,Performance Monitors Common Event Identification Register"
bitfld.long 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,?..."
bitfld.long 0x00 30. "CHAIN,Chain" "Reserved,Implemented"
bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented"
newline
bitfld.long 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Reserved,Implemented"
bitfld.long 0x00 27. "INST_SPEC,Instruction speculatively executed" "Reserved,Implemented"
bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented"
newline
bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented"
bitfld.long 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Not implemented,Implemented"
bitfld.long 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 22. "L2D_CACHE,Level 2 data cache access" "Not implemented,Implemented"
bitfld.long 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Reserved,Implemented"
bitfld.long 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Reserved,Implemented"
newline
bitfld.long 0x00 19. "MEM_ACCESS,Data memory access" "Reserved,Implemented"
bitfld.long 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Reserved,Implemented"
bitfld.long 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented"
newline
bitfld.long 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Reserved,Implemented"
bitfld.long 0x00 15. "UNALIGNED_LDST_RETIRED,Unaligned load or store" "Reserved,Implemented"
bitfld.long 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Reserved,Implemented"
newline
bitfld.long 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Reserved,Implemented"
bitfld.long 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Reserved,Implemented"
bitfld.long 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Reserved,Implemented"
newline
bitfld.long 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Reserved,Implemented"
bitfld.long 0x00 9. "EXC_TAKEN,Exception taken" "Reserved,Implemented"
bitfld.long 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Reserved,Implemented"
newline
bitfld.long 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Reserved,Implemented"
bitfld.long 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Reserved,Implemented"
bitfld.long 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Reserved,Implemented"
newline
bitfld.long 0x00 4. "L1D_CACHE,Level 1 data cache access" "Reserved,Implemented"
bitfld.long 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Reserved,Implemented"
bitfld.long 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Reserved,Implemented"
newline
bitfld.long 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Reserved,Implemented"
bitfld.long 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Reserved,Implemented"
rgroup.long c15:0x07C9++0x00
line.long 0x00 "PMCEID1,Performance Monitors Common Event Identification Register"
bitfld.long 0x00 24. "REMOTE_ACCESS_RD,Access to another socket in a multi-socket system" "Reserved,Implemented"
bitfld.long 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Reserved,Implemented"
bitfld.long 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Reserved,Implemented"
newline
bitfld.long 0x00 21. "ITLB_WALK,Access to instruction TLB that caused a page table walk" "Reserved,Implemented"
bitfld.long 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Reserved,Implemented"
bitfld.long 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,?..."
newline
bitfld.long 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Reserved,Implemented"
bitfld.long 0x00 14. "L2I_TLB_REFILL,Attributable Level 2 instruction TLB refill" "Not implemented,?..."
bitfld.long 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Reserved,Implemented"
newline
bitfld.long 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Not implemented,?..."
bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented"
bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented"
newline
bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented"
bitfld.long 0x00 8. "L2I_CACHE_REFILL,Attributable Level 2 instruction cache refill" "Not implemented,?..."
bitfld.long 0x00 7. "L2I_CACHE,Attributable Level 2 instruction cache access" "Not implemented,?..."
newline
bitfld.long 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Reserved,Implemented"
bitfld.long 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Reserved,Implemented"
bitfld.long 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Reserved,Implemented"
newline
bitfld.long 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Reserved,Implemented"
bitfld.long 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed branch" "Reserved,Implemented"
bitfld.long 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Reserved,Implemented"
newline
bitfld.long 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocation without refill" "Reserved,Implemented"
endif
rgroup.long c15:0x04E9++0x00
line.long 0x00 "PMCEID2,Performance Monitors Common Event Identification Register 2"
rgroup.long c15:0x05E9++0x00
line.long 0x00 "PMCEID3,Performance Monitors Common Event Identification Register 3"
tree.end
newline
group.long c15:0x00D9++0x00
line.long 0x00 "PMCCNTR[31:0],Performance Monitors Cycle Counter (32bit access)"
group.quad c15:0x130D0++0x01
line.quad 0x00 "PMCCNTR[63:0],Performance Monitors Cycle Counter (64bit access)"
if (((per.l(c15:0x05C9))&0x1F)==0x1F)
group.long c15:0x01D9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type and Filter Register - PMCCFILTR"
bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
elif (((per.l(c15:0x05C9))&0x1F)<=0x05)
group.long c15:0x01D9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type and Filter Register - PMEVTYPER"
bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
else
rgroup.long c15:0x01D9++0x00
line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type and Filter Register"
endif
group.long c15:0x02D9++0x00
line.long 0x00 "PMXEVCNTR,Performance Monitors Selected Event Counter Register"
group.long c15:0x00E9++0x00
line.long 0x00 "PMUSERENR,Performance Monitors User Enable Register"
bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled"
bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,User enable" "Disabled,Enabled"
if corename()=="CORTEXA55"
group.long c15:0x01E9++0x00
line.long 0x00 "PMINTENSET,Performance Monitors Interrupt Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x02E9++0x00
line.long 0x00 "PMINTENCLR,Performance Monitors Interrupt Enable Clear Register"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled"
endif
group.long c15:0x03E9++0x00
line.long 0x00 "PMOVSSET,Performance Monitors Overflow Flag Status Set Register"
bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow"
bitfld.long 0x00 5. "P5,PMEVCNTR5 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "P4,PMEVCNTR4 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 3. "P3,PMEVCNTR3 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "P2,PMEVCNTR2 Overflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "P1,PMEVCNTR1 Overflow Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "P0,PMEVCNTR0 Overflow Interrupt Enable" "Disabled,Enabled"
group.long c15:0x8E++0x00
line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0"
group.long c15:(0x8E+0x0040)++0x00
line.long 0x00 "PMEVTYPER0,Performance Monitors Event Type Register 0"
bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.long c15:0x18E++0x00
line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1"
group.long c15:(0x18E+0x0040)++0x00
line.long 0x00 "PMEVTYPER1,Performance Monitors Event Type Register 1"
bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.long c15:0x28E++0x00
line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2"
group.long c15:(0x28E+0x0040)++0x00
line.long 0x00 "PMEVTYPER2,Performance Monitors Event Type Register 2"
bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.long c15:0x38E++0x00
line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3"
group.long c15:(0x38E+0x0040)++0x00
line.long 0x00 "PMEVTYPER3,Performance Monitors Event Type Register 3"
bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.long c15:0x48E++0x00
line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4"
group.long c15:(0x48E+0x0040)++0x00
line.long 0x00 "PMEVTYPER4,Performance Monitors Event Type Register 4"
bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.long c15:0x58E++0x00
line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5"
group.long c15:(0x58E+0x0040)++0x00
line.long 0x00 "PMEVTYPER5,Performance Monitors Event Type Register 5"
bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
newline
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
group.long c15:0x07FE++0x00
line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register"
bitfld.long 0x00 31. "P,Count events in EL1 disable" "No,Yes"
bitfld.long 0x00 30. "U,Count events in EL0 disable" "No,Yes"
bitfld.long 0x00 29. "NSK,Count events in non-secure EL1 [P=0/1]" "Yes/No,No/Yes"
newline
bitfld.long 0x00 28. "NSU,Count events in non-secure EL0 [U=0/1]" "Yes/No,No/Yes"
bitfld.long 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled"
tree.end
tree "System Timer Registers"
group.long c15:0x000E++0x00
line.long 0x00 "CNTFRQ,Counter Frequency Register"
group.quad c15:0x100E0++0x01
line.quad 0x00 "CNTPCT,Counter Physical Count Register"
group.quad c15:0x110E0++0x01
line.quad 0x00 "CNTVCT,Counter Virtual Count Register"
if corename()=="CORTEXA55"
group.quad c15:0x140E0++0x01
line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register"
group.long c15:0x001E++0x00
line.long 0x00 "CNTKCTL,Timer PL1 Control Register"
bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer Registers are accessible from EL0 mode" "Trapped,Not trapped"
bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer Registers are accessible from EL0 mode" "Trapped,Not trapped"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0"
newline
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency Register CNTFRQ, are accessible from EL0 mode" "Trapped,Not trapped"
bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency Register CNTFRQ, are accessible from EL0 mode" "Trapped,Not trapped"
group.long c15:0x401E++0x00
line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register"
bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTPCT trigger bit, defined by EVNTI" "0 to 1,1 to 0"
bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled"
bitfld.long 0x00 1. "EL1PCEN,Controls whether the Non-secure copies of the physical timer Registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
newline
bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible"
endif
group.long c15:0x002E++0x00
line.long 0x00 "CNTP_TVAL,Counter EL1 Physical Compare Value Register"
if (((per.l(c15:0x012E))&0x01)==0x01)
group.long c15:0x012E++0x00
line.long 0x00 "CNTP_CTL,Counter EL1 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.long c15:0x012E++0x00
line.long 0x00 "CNTP_CTL,Counter EL1 Physical Timer Control Register"
newline
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad c15:0x120E0++0x01
line.quad 0x00 "CNTP_CVAL,Counter EL1 Physical Compare Value Register"
group.long c15:0x003E++0x00
line.long 0x00 "CNTV_TVAL,Counter EL1 Virtual Timer Value Register"
if (((per.l(c15:0x013E))&0x01)==0x01)
group.long c15:0x013E++0x00
line.long 0x00 "CNTV_CTL,Counter EL1 Virtual Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.long c15:0x013E++0x00
line.long 0x00 "CNTV_CTL,Counter EL1 Virtual Timer Control Register"
newline
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad c15:0x130E0++0x01
line.quad 0x00 "CNTV_CVAL,Counter EL1 Virtual Compare Value Register"
if corename()=="CORTEXA55"
group.long c15:0x402E++0x00
line.long 0x00 "CNTHP_TVAL,Counter Non-secure EL2 Physical Timer Value Register"
if (((per.l(c15:0x412E))&0x01)==0x01)
group.long c15:0x412E++0x00
line.long 0x00 "CNTHP_CTL,Counter Non-secure EL2 Physical Timer Control Register"
rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt"
newline
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
else
group.long c15:0x412E++0x00
line.long 0x00 "CNTHP_CTL,Counter Non-secure EL2 Physical Timer Control Register"
newline
bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked"
bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled"
endif
group.quad c15:0x160E0++0x01
line.quad 0x00 "CNTHP_CVAL,Counter Non-secure EL2 Physical Compare Value Register"
endif
tree.end
tree "Generic Interrupt Controller System Registers"
if corename()=="CORTEXA55"
group.long c15:0x048C++0x00
line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active priority 31" "0,1"
bitfld.long 0x00 30. "P30,Group 0 interrupt active priority 30" "0,1"
bitfld.long 0x00 29. "P29,Group 0 interrupt active priority 29" "0,1"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active priority 28" "0,1"
bitfld.long 0x00 27. "P27,Group 0 interrupt active priority 27" "0,1"
bitfld.long 0x00 26. "P26,Group 0 interrupt active priority 26" "0,1"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active priority 25" "0,1"
bitfld.long 0x00 24. "P24,Group 0 interrupt active priority 24" "0,1"
bitfld.long 0x00 23. "P23,Group 0 interrupt active priority 23" "0,1"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active priority 22" "0,1"
bitfld.long 0x00 21. "P21,Group 0 interrupt active priority 21" "0,1"
bitfld.long 0x00 20. "P20,Group 0 interrupt active priority 20" "0,1"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active priority 19" "0,1"
bitfld.long 0x00 18. "P18,Group 0 interrupt active priority 18" "0,1"
bitfld.long 0x00 17. "P17,Group 0 interrupt active priority 17" "0,1"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active priority 16" "0,1"
bitfld.long 0x00 15. "P15,Group 0 interrupt active priority 15" "0,1"
bitfld.long 0x00 14. "P14,Group 0 interrupt active priority 14" "0,1"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active priority 13" "0,1"
bitfld.long 0x00 12. "P12,Group 0 interrupt active priority 12" "0,1"
bitfld.long 0x00 11. "P11,Group 0 interrupt active priority 11" "0,1"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active priority 10" "0,1"
bitfld.long 0x00 9. "P9,Group 0 interrupt active priority 9" "0,1"
bitfld.long 0x00 8. "P8,Group 0 interrupt active priority 8" "0,1"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active priority 7" "0,1"
bitfld.long 0x00 6. "P6,Group 0 interrupt active priority 6" "0,1"
bitfld.long 0x00 5. "P5,Group 0 interrupt active priority 5" "0,1"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active priority 4" "0,1"
bitfld.long 0x00 3. "P3,Group 0 interrupt active priority 3" "0,1"
bitfld.long 0x00 2. "P2,Group 0 interrupt active priority 2" "0,1"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active priority 1" "0,1"
bitfld.long 0x00 0. "P0,Group 0 interrupt active priority 0" "0,1"
group.long c15:0x009C++0x00
line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active priority 31" "0,1"
bitfld.long 0x00 30. "P30,Group 1 interrupt active priority 30" "0,1"
bitfld.long 0x00 29. "P29,Group 1 interrupt active priority 29" "0,1"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active priority 28" "0,1"
bitfld.long 0x00 27. "P27,Group 1 interrupt active priority 27" "0,1"
bitfld.long 0x00 26. "P26,Group 1 interrupt active priority 26" "0,1"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active priority 25" "0,1"
bitfld.long 0x00 24. "P24,Group 1 interrupt active priority 24" "0,1"
bitfld.long 0x00 23. "P23,Group 1 interrupt active priority 23" "0,1"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active priority 22" "0,1"
bitfld.long 0x00 21. "P21,Group 1 interrupt active priority 21" "0,1"
bitfld.long 0x00 20. "P20,Group 1 interrupt active priority 20" "0,1"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active priority 19" "0,1"
bitfld.long 0x00 18. "P18,Group 1 interrupt active priority 18" "0,1"
bitfld.long 0x00 17. "P17,Group 1 interrupt active priority 17" "0,1"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active priority 16" "0,1"
bitfld.long 0x00 15. "P15,Group 1 interrupt active priority 15" "0,1"
bitfld.long 0x00 14. "P14,Group 1 interrupt active priority 14" "0,1"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active priority 13" "0,1"
bitfld.long 0x00 12. "P12,Group 1 interrupt active priority 12" "0,1"
bitfld.long 0x00 11. "P11,Group 1 interrupt active priority 11" "0,1"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active priority 10" "0,1"
bitfld.long 0x00 9. "P9,Group 1 interrupt active priority 9" "0,1"
bitfld.long 0x00 8. "P8,Group 1 interrupt active priority 8" "0,1"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active priority 7" "0,1"
bitfld.long 0x00 6. "P6,Group 1 interrupt active priority 6" "0,1"
bitfld.long 0x00 5. "P5,Group 1 interrupt active priority 5" "0,1"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active priority 4" "0,1"
bitfld.long 0x00 3. "P3,Group 1 interrupt active priority 3" "0,1"
bitfld.long 0x00 2. "P2,Group 1 interrupt active priority 2" "0,1"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active priority 1" "0,1"
bitfld.long 0x00 0. "P0,Group 1 interrupt active priority 0" "0,1"
if (((per.q(c15:0x110C0))&0x10000000000)==0x00)
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
newline
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
else
wgroup.quad c15:0x110C0++0x01
line.quad 0x00 "ICC_ASGI1R,Alternate SGI Generation Register 1"
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long c15:0x038C++0x00
line.long 0x00 "ICC_BPR0,Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.long c15:0x03CC++0x00
line.long 0x00 "ICC_BPR1,Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control (Non-secure/Secure)" "Reserved/Reserved,Reserved/Reserved,Reserved/[7:3]-[2:0],[7:3]-[2:0]/[7:4]-[3:0],[7:4]-[3:0]/[7:5]-[4:0],[7:5]-[4:0]/[7:6]-[5:0],[7:6]-[5:0]/[7]-[6:0],[7]-[6:0]/No preemption-[7:0]"
group.long c15:0x04CC++0x00
line.long 0x00 "ICC_CTLR,Interrupt Control Register for EL1"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported"
rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,?..."
rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented minus one" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Both,Priority drop"
newline
bitfld.long 0x00 0. "CBPR,Common binary point Register" "Separate,Common"
group.long c15:0x64CC++0x00
line.long 0x00 "ICC_MCTLR,Interrupt Control Register for EL3"
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Reserved,Not supported"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,?..."
newline
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "RM,Routing Modifier" "Normal,?..."
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt(Non-secure EL1 and EL2)" "Both,Priority drop"
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt(Secure EL1)" "Both,Priority drop"
newline
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt(EL3)" "Both,Priority drop"
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate,Common"
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate,Common"
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICC_DIR,Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access."
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICC_HPPIR0,Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICC_HPPIR1,Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x008C++0x00
line.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x00CC++0x00
line.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
group.long c15:0x06CC++0x00
line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x07CC++0x00
line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICC_PMR,Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface"
if (((per.q(c15:0x120C0))&0x10000000000)==0x00)
wgroup.quad c15:0x120C0++0x01
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
newline
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
else
wgroup.quad c15:0x120C0++0x01
line.quad 0x00 "ICC_SGI0R,SGI Generation Register 0"
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
bitfld.quad 0x00 24.--27. "INTID,INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
if (((per.q(c15:0x100C0))&0x10000000000)==0x00)
wgroup.quad c15:0x100C0++0x01
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3"
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
newline
hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2"
bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1"
newline
hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,Target List"
else
wgroup.quad c15:0x100C0++0x01
line.quad 0x00 "ICC_SGI1R,SGI Generation Register 1"
textfld "                       "
bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40. "IRM,Interrupt Routing Mode" "Disabled,Enabled"
newline
bitfld.quad 0x00 24.--27. "INTID,INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long c15:0x05CC++0x00
line.long 0x00 "ICC_SRE,System Register Enable Register for EL1"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
rbitfld.long 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
group.long c15:0x459C++0x00
line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2"
rbitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Reserved,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
rbitfld.long 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
group.long c15:0x65CC++0x00
line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3"
rbitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Reserved,Enabled"
bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes"
bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes"
newline
rbitfld.long 0x00 0. "SRE,System Register Enable" "Reserved,Enabled"
group.long c15:0x67CC++0x00
line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable"
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.long c15:0x048C++0x00
line.long 0x00 "ICV_AP0R0,Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 30. "P30,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 29. "P29,Group 0 interrupt active priority" "0,1"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 27. "P27,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 26. "P26,Group 0 interrupt active priority" "0,1"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 24. "P24,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 23. "P23,Group 0 interrupt active priority" "0,1"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 21. "P21,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 20. "P20,Group 0 interrupt active priority" "0,1"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 18. "P18,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 17. "P17,Group 0 interrupt active priority" "0,1"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 15. "P15,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 14. "P14,Group 0 interrupt active priority" "0,1"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 12. "P12,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 11. "P11,Group 0 interrupt active priority" "0,1"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 9. "P9,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 8. "P8,Group 0 interrupt active priority" "0,1"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 6. "P6,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 5. "P5,Group 0 interrupt active priority" "0,1"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 3. "P3,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 2. "P2,Group 0 interrupt active priority" "0,1"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active priority" "0,1"
bitfld.long 0x00 0. "P0,Group 0 interrupt active priority" "0,1"
group.long c15:0x009C++0x00
line.long 0x00 "ICV_AP1R0,Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 30. "P30,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 29. "P29,Group 1 interrupt active priority" "0,1"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 27. "P27,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 26. "P26,Group 1 interrupt active priority" "0,1"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 24. "P24,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 23. "P23,Group 1 interrupt active priority" "0,1"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 21. "P21,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 20. "P20,Group 1 interrupt active priority" "0,1"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 18. "P18,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 17. "P17,Group 1 interrupt active priority" "0,1"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 15. "P15,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 14. "P14,Group 1 interrupt active priority" "0,1"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 12. "P12,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 11. "P11,Group 1 interrupt active priority" "0,1"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 9. "P9,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 8. "P8,Group 1 interrupt active priority" "0,1"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 6. "P6,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 5. "P5,Group 1 interrupt active priority" "0,1"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 3. "P3,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 2. "P2,Group 1 interrupt active priority" "0,1"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active priority" "0,1"
bitfld.long 0x00 0. "P0,Group 1 interrupt active priority" "0,1"
group.long c15:0x038C++0x00
line.long 0x00 "ICV_BPR0,Binary Point Register 0"
bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
group.long c15:0x03CC++0x00
line.long 0x00 "ICV_BPR1,Binary Point Register 1"
bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control (Non-secure/Secure)" "Reserved/Reserved,Reserved/Reserved,Reserved/[7:3]-[2:0],[7:3]-[2:0]/[7:4]-[3:0],[7:4]-[3:0]/[7:5]-[4:0],[7:5]-[4:0]/[7:6]-[5:0],[7:6]-[5:0]/[7]-[6:0],[7]-[6:0]/No preemption-[7:0]"
group.long c15:0x4CC++0x00
line.long 0x00 "ICV_CTLR,Control Register"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..."
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
newline
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.long 0x00 1. "VEOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Both,Priority drop"
bitfld.long 0x00 0. "VCBPR,Controls whether the same Register is used for interrupt preemption of both virtual Group 0 and virtual Group 1 interrupts" "Separate,Common"
wgroup.long c15:0x01BC++0x00
line.long 0x00 "ICV_DIR,Deactivate Interrupt Register"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated"
wgroup.long c15:0x018C++0x00
line.long 0x00 "ICV_EOIR0,End Of Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access"
wgroup.long c15:0x01CC++0x00
line.long 0x00 "ICV_EOIR1,End Of Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access"
rgroup.long c15:0x028C++0x00
line.long 0x00 "ICV_HPPIR0,Highest Priority Pending Interrupt Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x02CC++0x00
line.long 0x00 "ICV_HPPIR1,Highest Priority Pending Interrupt Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x008C++0x00
line.long 0x00 "ICV_IAR0,Interrupt Acknowledge Register 0"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
rgroup.long c15:0x00CC++0x00
line.long 0x00 "ICV_IAR1,Interrupt Acknowledge Register 1"
hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt"
group.long c15:0x06CC++0x00
line.long 0x00 "ICV_IGRPEN0,Interrupt Group 0 Enable Register"
bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled"
group.long c15:0x07CC++0x00
line.long 0x00 "ICV_IGRPEN1,Interrupt Group 1 Enable Register"
bitfld.long 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled"
group.long c15:0x064CC++0x00
line.long 0x00 "ICV_MCTLR,Monitor Control Register"
rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Reserved,Not supported"
rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported"
rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,?..."
newline
rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop"
bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Enabled,Disabled"
bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled"
newline
bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate Registers,Same Register"
bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate Registers,Same Register"
group.long c15:0x67CC++0x00
line.long 0x00 "ICV_MGRPEN1,Monitor Interrupt Group 1 Enable Register"
bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled"
group.long c15:0x0064++0x00
line.long 0x00 "ICV_PMR,Interrupt Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,The priority mask level for the CPU interface"
rgroup.long c15:0x03BC++0x00
line.long 0x00 "ICV_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,The current running priority on the CPU interface"
group.long c15:0x408C++0x00
line.long 0x00 "ICH_AP0R0,Hyp Active Priorities Group 0 Register 0"
bitfld.long 0x00 31. "P31,Group 0 interrupt active priority 31" "0,1"
bitfld.long 0x00 30. "P30,Group 0 interrupt active priority 30" "0,1"
bitfld.long 0x00 29. "P29,Group 0 interrupt active priority 29" "0,1"
newline
bitfld.long 0x00 28. "P28,Group 0 interrupt active priority 28" "0,1"
bitfld.long 0x00 27. "P27,Group 0 interrupt active priority 27" "0,1"
bitfld.long 0x00 26. "P26,Group 0 interrupt active priority 26" "0,1"
newline
bitfld.long 0x00 25. "P25,Group 0 interrupt active priority 25" "0,1"
bitfld.long 0x00 24. "P24,Group 0 interrupt active priority 24" "0,1"
bitfld.long 0x00 23. "P23,Group 0 interrupt active priority 23" "0,1"
newline
bitfld.long 0x00 22. "P22,Group 0 interrupt active priority 22" "0,1"
bitfld.long 0x00 21. "P21,Group 0 interrupt active priority 21" "0,1"
bitfld.long 0x00 20. "P20,Group 0 interrupt active priority 20" "0,1"
newline
bitfld.long 0x00 19. "P19,Group 0 interrupt active priority 19" "0,1"
bitfld.long 0x00 18. "P18,Group 0 interrupt active priority 18" "0,1"
bitfld.long 0x00 17. "P17,Group 0 interrupt active priority 17" "0,1"
newline
bitfld.long 0x00 16. "P16,Group 0 interrupt active priority 16" "0,1"
bitfld.long 0x00 15. "P15,Group 0 interrupt active priority 15" "0,1"
bitfld.long 0x00 14. "P14,Group 0 interrupt active priority 14" "0,1"
newline
bitfld.long 0x00 13. "P13,Group 0 interrupt active priority 13" "0,1"
bitfld.long 0x00 12. "P12,Group 0 interrupt active priority 12" "0,1"
bitfld.long 0x00 11. "P11,Group 0 interrupt active priority 11" "0,1"
newline
bitfld.long 0x00 10. "P10,Group 0 interrupt active priority 10" "0,1"
bitfld.long 0x00 9. "P9,Group 0 interrupt active priority 9" "0,1"
bitfld.long 0x00 8. "P8,Group 0 interrupt active priority 8" "0,1"
newline
bitfld.long 0x00 7. "P7,Group 0 interrupt active priority 7" "0,1"
bitfld.long 0x00 6. "P6,Group 0 interrupt active priority 6" "0,1"
bitfld.long 0x00 5. "P5,Group 0 interrupt active priority 5" "0,1"
newline
bitfld.long 0x00 4. "P4,Group 0 interrupt active priority 4" "0,1"
bitfld.long 0x00 3. "P3,Group 0 interrupt active priority 3" "0,1"
bitfld.long 0x00 2. "P2,Group 0 interrupt active priority 2" "0,1"
newline
bitfld.long 0x00 1. "P1,Group 0 interrupt active priority 1" "0,1"
bitfld.long 0x00 0. "P0,Group 0 interrupt active priority 0" "0,1"
group.long c15:0x409C++0x00
line.long 0x00 "ICH_AP1R0,Hyp Active Priorities Group 1 Register 0"
bitfld.long 0x00 31. "P31,Group 1 interrupt active priority 31" "0,1"
bitfld.long 0x00 30. "P30,Group 1 interrupt active priority 30" "0,1"
bitfld.long 0x00 29. "P29,Group 1 interrupt active priority 29" "0,1"
newline
bitfld.long 0x00 28. "P28,Group 1 interrupt active priority 28" "0,1"
bitfld.long 0x00 27. "P27,Group 1 interrupt active priority 27" "0,1"
bitfld.long 0x00 26. "P26,Group 1 interrupt active priority 26" "0,1"
newline
bitfld.long 0x00 25. "P25,Group 1 interrupt active priority 25" "0,1"
bitfld.long 0x00 24. "P24,Group 1 interrupt active priority 24" "0,1"
bitfld.long 0x00 23. "P23,Group 1 interrupt active priority 23" "0,1"
newline
bitfld.long 0x00 22. "P22,Group 1 interrupt active priority 22" "0,1"
bitfld.long 0x00 21. "P21,Group 1 interrupt active priority 21" "0,1"
bitfld.long 0x00 20. "P20,Group 1 interrupt active priority 20" "0,1"
newline
bitfld.long 0x00 19. "P19,Group 1 interrupt active priority 19" "0,1"
bitfld.long 0x00 18. "P18,Group 1 interrupt active priority 18" "0,1"
bitfld.long 0x00 17. "P17,Group 1 interrupt active priority 17" "0,1"
newline
bitfld.long 0x00 16. "P16,Group 1 interrupt active priority 16" "0,1"
bitfld.long 0x00 15. "P15,Group 1 interrupt active priority 15" "0,1"
bitfld.long 0x00 14. "P14,Group 1 interrupt active priority 14" "0,1"
newline
bitfld.long 0x00 13. "P13,Group 1 interrupt active priority 13" "0,1"
bitfld.long 0x00 12. "P12,Group 1 interrupt active priority 12" "0,1"
bitfld.long 0x00 11. "P11,Group 1 interrupt active priority 11" "0,1"
newline
bitfld.long 0x00 10. "P10,Group 1 interrupt active priority 10" "0,1"
bitfld.long 0x00 9. "P9,Group 1 interrupt active priority 9" "0,1"
bitfld.long 0x00 8. "P8,Group 1 interrupt active priority 8" "0,1"
newline
bitfld.long 0x00 7. "P7,Group 1 interrupt active priority 7" "0,1"
bitfld.long 0x00 6. "P6,Group 1 interrupt active priority 6" "0,1"
bitfld.long 0x00 5. "P5,Group 1 interrupt active priority 5" "0,1"
newline
bitfld.long 0x00 4. "P4,Group 1 interrupt active priority 4" "0,1"
bitfld.long 0x00 3. "P3,Group 1 interrupt active priority 3" "0,1"
bitfld.long 0x00 2. "P2,Group 1 interrupt active priority 2" "0,1"
newline
bitfld.long 0x00 1. "P1,Group 1 interrupt active priority 1" "0,1"
bitfld.long 0x00 0. "P0,Group 1 interrupt active priority 0" "0,1"
rgroup.long c15:0x43BC++0x00
line.long 0x00 "ICH_EISR,End of Interrupt Status Register"
bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List Register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List Register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List Register 1" "No interrupt,Interrupt"
newline
bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List Register 0" "No interrupt,Interrupt"
rgroup.long c15:0x45BC++0x00
line.long 0x00 "ICH_ELRSR,Empty List Register Status Register"
bitfld.long 0x00 3. "STATUS3,Status bit for List Register 3" "Interrupt,No interrupt"
bitfld.long 0x00 2. "STATUS2,Status bit for List Register 2" "Interrupt,No interrupt"
bitfld.long 0x00 1. "STATUS1,Status bit for List Register 1" "Interrupt,No interrupt"
newline
bitfld.long 0x00 0. "STATUS0,Status bit for List Register 0" "Interrupt,No interrupt"
group.long c15:0x40BC++0x00
line.long 0x00 "ICH_HCR,Hyp Control Register"
bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR Register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR and ICV_DIR" "No trap,Trap"
bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "No trap,?..."
newline
bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* and ICV_* System Registers for Group 1 interrupts to EL2" "No trap,Trap"
bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* and ICV_* System Registers for Group 0 interrupts to EL2" "No trap,Trap"
bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System Registers that are common to Group 0 and Group 1 to EL2" "No trap,Trap"
newline
bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled"
group.long c15:(0x40CC+0x0)++0x00
line.long 0x00 "ICH_LR0,List Register 0"
group.long c15:(0x40CC+0x100)++0x00
line.long 0x00 "ICH_LR1,List Register 1"
group.long c15:(0x40CC+0x200)++0x00
line.long 0x00 "ICH_LR2,List Register 2"
group.long c15:(0x40CC+0x300)++0x00
line.long 0x00 "ICH_LR3,List Register 3"
if (((per.l(c15:(0x40EC+0x0)))&0x20000000)==0x20000000)
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,List Register Extension 0"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--12. 1. "PINTID,Physical INTID for hardware interrupts"
else
group.long c15:(0x40EC+0x0)++0x00
line.long 0x00 "ICH_LRC0,List Register Extension 0"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
bitfld.long 0x00 9. "EOI,End of interrupt" "Not asserted,Asserted"
endif
if (((per.l(c15:(0x40EC+0x100)))&0x20000000)==0x20000000)
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,List Register Extension 1"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--12. 1. "PINTID,Physical INTID for hardware interrupts"
else
group.long c15:(0x40EC+0x100)++0x00
line.long 0x00 "ICH_LRC1,List Register Extension 1"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
bitfld.long 0x00 9. "EOI,End of interrupt" "Not asserted,Asserted"
endif
if (((per.l(c15:(0x40EC+0x200)))&0x20000000)==0x20000000)
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,List Register Extension 2"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--12. 1. "PINTID,Physical INTID for hardware interrupts"
else
group.long c15:(0x40EC+0x200)++0x00
line.long 0x00 "ICH_LRC2,List Register Extension 2"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
bitfld.long 0x00 9. "EOI,End of interrupt" "Not asserted,Asserted"
endif
if (((per.l(c15:(0x40EC+0x300)))&0x20000000)==0x20000000)
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,List Register Extension 3"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
hexmask.long.word 0x00 0.--12. 1. "PINTID,Physical INTID for hardware interrupts"
else
group.long c15:(0x40EC+0x300)++0x00
line.long 0x00 "ICH_LRC3,List Register Extension 3"
bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active"
bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt"
bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1"
newline
hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt"
bitfld.long 0x00 9. "EOI,End of interrupt" "Not asserted,Asserted"
endif
rgroup.long c15:0x42BC++0x00
line.long 0x00 "ICH_MISR,Maintenance Interrupt State Register"
bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted"
bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted"
newline
bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted"
bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted"
bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted"
newline
bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted"
bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted"
group.long c15:0x47BC++0x00
line.long 0x00 "ICH_VMCR,Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface"
bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]"
bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1 (Non-secure/Secure)" "Reserved/Reserved,Reserved/Reserved,Reserved/[7:3]-[2:0],[7:3]-[2:0]/[7:4]-[3:0],[7:4]-[3:0]/[7:5]-[4:0],[7:5]-[4:0]/[7:6]-[5:0],[7:6]-[5:0]/[7]-[6:0],[7]-[6:0]/No preemption-[7:0]"
newline
bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt Register also deactivates the virtual interrupt" "Both,Priority drop"
bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate,Common"
bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Reserved,Virtual FIQs"
newline
bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled"
rgroup.long c15:0x41BC++0x00
line.long 0x00 "ICH_VTR,VGIC Type Register"
bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "Reserved,Reserved,Reserved,Reserved,5,?..."
bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..."
newline
bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..."
bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Reserved,Supported"
bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,?..."
newline
bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Reserved,Supported"
bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List Registers minus one" "Reserved,Reserved,Reserved,4,?..."
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These Registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Debug Registers"
tree "Coresight Management Registers"
if (CORENAME()=="CORTEXA55")
rgroup.long c14:0x0000++0x00
line.long 0x00 "DBGDIDR,Debug ID Register"
bitfld.long 0x00 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..."
bitfld.long 0x00 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..."
newline
bitfld.long 0x00 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,2,?..."
bitfld.long 0x00 16.--19. "VERSION,Debug architecture version" ",,,,,,,,v8.2,?..."
newline
bitfld.long 0x00 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not supported"
bitfld.long 0x00 12. "SE,Security Extensions implemented" "Reserved,Implemented"
rgroup.long c14:0x0060++0x00
line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register"
group.long c14:0x0070++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 30. "IRQVCE_NS,IRQ vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled"
bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
newline
bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled"
bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 6. "IRQVCE_S,IRQ vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
newline
bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
group.long c14:0x0200++0x00
line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)"
endif
rgroup.long c14:0x0050++0x00
line.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)"
if corename()=="CORTEXA55"
group.long c14:0x0020++0x00
line.long 0x00 "DBGDCCINT,Debug Comms Channel Interrupt Enable register"
bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled"
bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled"
endif
rgroup.long c14:0x0010++0x00
line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
newline
bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
newline
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software Breakpoint (BKPT),Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..."
if corename()=="CORTEXA55"
if (((per.l(c14:0x0411))&0x02)==0x02)
group.long c14:0x0220++0x00
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
bitfld.long 0x00 27. "RXO,DBGDTRRX overflow" "No overflow,Overflow"
newline
bitfld.long 0x00 26. "TXU,DBGDTRTX underflow" "No underflow,Underflow"
bitfld.long 0x00 22.--23. "INTDIS,Interrupt disable" "Don't disable interrupts,Disable interrupts targeting non-sec EL1,Disable interrupts targeting EL1 & EL2,Disable all interrupts"
newline
bitfld.long 0x00 21. "TDA,Trap debug register access" "No trap,Trap"
rbitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
rbitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
rbitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
bitfld.long 0x00 14. "HDE,Halting debug-mode" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
bitfld.long 0x00 6. "ERR,Cumulative error flag" "Not error,Error"
newline
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software Breakpoint (BKPT),Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..."
else
group.long c14:0x0220++0x00
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)"
rbitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full"
rbitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full"
rbitfld.long 0x00 27. "RXO,DBGDTRRX overflow" "No overflow,Overflow"
newline
rbitfld.long 0x00 26. "TXU,DBGDTRTX underflow" "No underflow,Underflow"
rbitfld.long 0x00 22.--23. "INTDIS,Interrupt disable" "Don't disable interrupts,Disable interrupts targeting non-sec EL1,Disable interrupts targeting EL1 & EL2,Disable all interrupts"
newline
rbitfld.long 0x00 21. "TDA,Trap debug register access" "No trap,Trap"
rbitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure"
newline
rbitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
rbitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled"
newline
rbitfld.long 0x00 14. "HDE,Halting debug-mode" "Disabled,Enabled"
bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes"
rbitfld.long 0x00 6. "ERR,Cumulative error flag" "Not error,Error"
newline
bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software Breakpoint (BKPT),Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..."
endif
group.long c14:0x0230++0x0
line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)"
endif
wgroup.long c14:0x0050++0x0
line.long 0x00 "DBGDTRTXINT,Debug Transmit Register (Internal View)"
if corename()=="CORTEXA55"
if (((per.l(c14:0x0411))&0x02)==0x02)
group.long c14:0x0260++0x00
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
else
rgroup.long c14:0x0260++0x00
line.long 0x00 "DBGOSECCR,Debug OS Lock Exception Catch Control Register"
endif
rgroup.long c14:0x0707++0x00
line.long 0x00 "DBGDEVID2,Debug Device ID Register 2"
rgroup.long c14:0x0717++0x00
line.long 0x00 "DBGDEVID1,Debug Device ID Register 1"
rgroup.long c14:0x0727++0x00
line.long 0x00 "DBGDEVID,Debug Device ID Register 0"
bitfld.long 0x00 28.--31. "CIDMASK,Level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..."
bitfld.long 0x00 24.--27. "AR,Debug External Auxiliary Control Register support status" "Not supported,?..."
bitfld.long 0x00 20.--23. "DL,Support for Debug OS Double Lock Register" "Reserved,Supported,?..."
newline
bitfld.long 0x00 16.--19. "VE,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..."
bitfld.long 0x00 12.--15. "VC,Form of the vector catch event implemented" "Implemented,?..."
bitfld.long 0x00 8.--11. "BPAM,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented"
newline
bitfld.long 0x00 4.--7. "WPAM,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..."
endif
tree.end
newline
if corename()=="CORTEXA55"
rgroup.quad c14:0x10010++0x01
line.quad 0x00 "DBGDRAR,Debug ROM Address Register"
rgroup.quad c14:0x10020++0x01
line.quad 0x00 "DBGDSAR[63:0],Debug Self Address Offset Register"
rgroup.long c14:0x0202++0x00
line.long 0x00 "DBGDSAR[31:0],Debug Self Address Offset Register"
wgroup.long c14:0x0401++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup.long c14:0x0411++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required"
bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked"
newline
bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..."
group.long c14:0x0431++0x00
line.long 0x00 "DBGOSDLR,OS Double-lock Register"
bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked"
group.long c14:0x0441++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Powered down,Emulated"
group.long c14:0x0687++0x00
line.long 0x00 "DBGCLAIMSET,Claim Tag register Set"
bitfld.long 0x00 7. "CT7,Claim Tag 7 Set" "Not set,Set"
bitfld.long 0x00 6. "CT6,Claim Tag 6 Set" "Not set,Set"
newline
bitfld.long 0x00 5. "CT5,Claim Tag 5 Set" "Not set,Set"
bitfld.long 0x00 4. "CT4,Claim Tag 4 Set" "Not set,Set"
newline
bitfld.long 0x00 3. "CT3,Claim Tag 3 Set" "Not set,Set"
bitfld.long 0x00 2. "CT2,Claim Tag 2 Set" "Not set,Set"
newline
bitfld.long 0x00 1. "CT1,Claim Tag 1 Set" "Not set,Set"
bitfld.long 0x00 0. "CT0,Claim Tag 0 Set" "Not set,Set"
group.long c14:0x0697++0x00
line.long 0x00 "DBGCLAIMCLR,Claim Tag register Clear"
bitfld.long 0x00 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared"
bitfld.long 0x00 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x00 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared"
bitfld.long 0x00 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x00 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared"
bitfld.long 0x00 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared"
newline
bitfld.long 0x00 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared"
bitfld.long 0x00 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared"
rgroup.long c14:0x06E7++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status register"
bitfld.long 0x00 6.--7. "SNID,Secure non-invasive debug" "Not implemented,Reserved,Implemented/Disabled,Implemented/Enabled"
bitfld.long 0x00 4.--5. "SID,Secure invasive debug" "Not implemented,Reserved,Implemented/Disabled,Implemented/Enabled"
newline
bitfld.long 0x00 2.--3. "NSNID,Non-secure non-invasive debug" "Not implemented,Reserved,Implemented/Disabled,Implemented/Enabled"
bitfld.long 0x00 0.--1. "NSID,Non-secure invasive debug" "Not implemented,Reserved,Implemented/Disabled,Implemented/Enabled"
rgroup.long c14:0x7000++0x00 "Jazelle Registers"
line.long 0x0 "JIDR,Jazelle ID Register"
rgroup.long c14:0x7001++0x00
line.long 0x0 "JOSCR,Jazelle OS Control Register"
rgroup.long c14:0x7002++0x00
line.long 0x0 "JMCR,Jazelle Main Configuration Register"
endif
tree.end
tree "Breakpoint Registers"
tree "Breakpoint 0"
if corename()=="CORTEXA55"
if (((per.l(c14:0x500+0x0))&0xA00000)==0x00)
group.long c14:(0x0400+0x0)++0x00
line.long 0x00 "DBGBVR0,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:0x500+0x0))&0xE00000)==0x200000)||(((per.l(c14:0x500+0x0))&0xE00000)==0xA00000)||(((per.l(c14:0x500+0x0))&0x600000)==0x600000)
group.long c14:(0x0400+0x0)++0x00
line.long 0x00 "DBGBVR0,Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x0)++0x00
line.long 0x00 "DBGBVR0,Breakpoint Value Register"
endif
if (((per.l(c14:(0x0500+0x0))&0x2000))==0x00)
if (((per.l(c14:(0x0500+0x0))&0xC000))==(0x00||0x4000||0x8000))
group.long c14:(0x0500+0x0)++0x00
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x0)++0x00
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.l(c14:(0x0500+0x0))&0xC000))==(0x00||0x8000))
group.long c14:(0x0500+0x0)++0x00
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x0)++0x00
line.long 0x00 "DBGBCR0,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Breakpoint 1"
if corename()=="CORTEXA55"
if (((per.l(c14:0x500+0x10))&0xA00000)==0x00)
group.long c14:(0x0400+0x10)++0x00
line.long 0x00 "DBGBVR1,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:0x500+0x10))&0xE00000)==0x200000)||(((per.l(c14:0x500+0x10))&0xE00000)==0xA00000)||(((per.l(c14:0x500+0x10))&0x600000)==0x600000)
group.long c14:(0x0400+0x10)++0x00
line.long 0x00 "DBGBVR1,Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x10)++0x00
line.long 0x00 "DBGBVR1,Breakpoint Value Register"
endif
if (((per.l(c14:(0x0500+0x10))&0x2000))==0x00)
if (((per.l(c14:(0x0500+0x10))&0xC000))==(0x00||0x4000||0x8000))
group.long c14:(0x0500+0x10)++0x00
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x10)++0x00
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.l(c14:(0x0500+0x10))&0xC000))==(0x00||0x8000))
group.long c14:(0x0500+0x10)++0x00
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x10)++0x00
line.long 0x00 "DBGBCR1,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Breakpoint 2"
if corename()=="CORTEXA55"
if (((per.l(c14:0x500+0x20))&0xA00000)==0x00)
group.long c14:(0x0400+0x20)++0x00
line.long 0x00 "DBGBVR2,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:0x500+0x20))&0xE00000)==0x200000)||(((per.l(c14:0x500+0x20))&0xE00000)==0xA00000)||(((per.l(c14:0x500+0x20))&0x600000)==0x600000)
group.long c14:(0x0400+0x20)++0x00
line.long 0x00 "DBGBVR2,Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x20)++0x00
line.long 0x00 "DBGBVR2,Breakpoint Value Register"
endif
if (((per.l(c14:(0x0500+0x20))&0x2000))==0x00)
if (((per.l(c14:(0x0500+0x20))&0xC000))==(0x00||0x4000||0x8000))
group.long c14:(0x0500+0x20)++0x00
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x20)++0x00
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.l(c14:(0x0500+0x20))&0xC000))==(0x00||0x8000))
group.long c14:(0x0500+0x20)++0x00
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x20)++0x00
line.long 0x00 "DBGBCR2,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Breakpoint 3"
if corename()=="CORTEXA55"
if (((per.l(c14:0x500+0x30))&0xA00000)==0x00)
group.long c14:(0x0400+0x30)++0x00
line.long 0x00 "DBGBVR3,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:0x500+0x30))&0xE00000)==0x200000)||(((per.l(c14:0x500+0x30))&0xE00000)==0xA00000)||(((per.l(c14:0x500+0x30))&0x600000)==0x600000)
group.long c14:(0x0400+0x30)++0x00
line.long 0x00 "DBGBVR3,Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x30)++0x00
line.long 0x00 "DBGBVR3,Breakpoint Value Register"
endif
if (((per.l(c14:(0x0500+0x30))&0x2000))==0x00)
if (((per.l(c14:(0x0500+0x30))&0xC000))==(0x00||0x4000||0x8000))
group.long c14:(0x0500+0x30)++0x00
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x30)++0x00
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.l(c14:(0x0500+0x30))&0xC000))==(0x00||0x8000))
group.long c14:(0x0500+0x30)++0x00
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x30)++0x00
line.long 0x00 "DBGBCR3,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Breakpoint 4"
if corename()=="CORTEXA55"
if (((per.l(c14:0x500+0x40))&0xA00000)==0x00)
group.long c14:(0x0400+0x40)++0x00
line.long 0x00 "DBGBVR4,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:0x500+0x40))&0xE00000)==0x200000)||(((per.l(c14:0x500+0x40))&0xE00000)==0xA00000)||(((per.l(c14:0x500+0x40))&0x600000)==0x600000)
group.long c14:(0x0400+0x40)++0x00
line.long 0x00 "DBGBVR4,Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x40)++0x00
line.long 0x00 "DBGBVR4,Breakpoint Value Register"
endif
group.long c14:(0x0101+0x40)++0x00
line.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register"
if (((per.l(c14:(0x0500+0x40))&0x2000))==0x00)
if (((per.l(c14:(0x0500+0x40))&0xC000))==(0x00||0x4000||0x8000))
group.long c14:(0x0500+0x40)++0x00
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x40)++0x00
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.l(c14:(0x0500+0x40))&0xC000))==(0x00||0x8000))
group.long c14:(0x0500+0x40)++0x00
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x40)++0x00
line.long 0x00 "DBGBCR4,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Breakpoint 5"
if corename()=="CORTEXA55"
if (((per.l(c14:0x500+0x50))&0xA00000)==0x00)
group.long c14:(0x0400+0x50)++0x00
line.long 0x00 "DBGBVR5,Breakpoint Value Register"
hexmask.long 0x00 2.--31. 0x04 "VA,Bits[31:2] of the address value for comparison"
elif (((per.l(c14:0x500+0x50))&0xE00000)==0x200000)||(((per.l(c14:0x500+0x50))&0xE00000)==0xA00000)||(((per.l(c14:0x500+0x50))&0x600000)==0x600000)
group.long c14:(0x0400+0x50)++0x00
line.long 0x00 "DBGBVR5,Breakpoint Value Register"
else
rgroup.long c14:(0x0400+0x50)++0x00
line.long 0x00 "DBGBVR5,Breakpoint Value Register"
endif
group.long c14:(0x0101+0x50)++0x00
line.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register"
if (((per.l(c14:(0x0500+0x50))&0x2000))==0x00)
if (((per.l(c14:(0x0500+0x50))&0xC000))==(0x00||0x4000||0x8000))
group.long c14:(0x0500+0x50)++0x00
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System,System,User,User/System"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x50)++0x00
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
else
if (((per.l(c14:(0x0500+0x50))&0xC000))==(0x00||0x8000))
group.long c14:(0x0500+0x50)++0x00
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Reserved,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
else
group.long c14:(0x0500+0x50)++0x00
line.long 0x00 "DBGBCR5,Breakpoint Control Register"
bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Reserved,Reserved,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,?..."
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
newline
bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn"
bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "Supervisor,Supervisor/System,Reserved,Supervisor/System/User"
newline
bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled"
endif
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree.end
tree "Watchpoint Registers"
tree "Watchpoint 0"
if corename()=="CORTEXA55"
group.long c14:(0x0600+0x0)++0x00
line.long 0x00 "DBGWVR0,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x04 "ADDRESS,Data address"
if (((per.l(c14:(0x0700+0x0)))&0x2000)==0x00)
if (((per.l(c14:(0x0700+0x0)))&0xC000)==(0x00||0x4000||0x8000))
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.l(c14:(0x0700+0x0)))&0xC000)==0x00)
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(c14:(0x0700+0x0)))&0xC000)==(0x4000||0xC000))
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x0)++0x00
line.long 0x00 "DBGWCR0,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Watchpoint 1"
if corename()=="CORTEXA55"
group.long c14:(0x0600+0x10)++0x00
line.long 0x00 "DBGWVR1,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x04 "ADDRESS,Data address"
if (((per.l(c14:(0x0700+0x10)))&0x2000)==0x00)
if (((per.l(c14:(0x0700+0x10)))&0xC000)==(0x00||0x4000||0x8000))
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.l(c14:(0x0700+0x10)))&0xC000)==0x00)
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(c14:(0x0700+0x10)))&0xC000)==(0x4000||0xC000))
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x10)++0x00
line.long 0x00 "DBGWCR1,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Watchpoint 2"
if corename()=="CORTEXA55"
group.long c14:(0x0600+0x20)++0x00
line.long 0x00 "DBGWVR2,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x04 "ADDRESS,Data address"
if (((per.l(c14:(0x0700+0x20)))&0x2000)==0x00)
if (((per.l(c14:(0x0700+0x20)))&0xC000)==(0x00||0x4000||0x8000))
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.l(c14:(0x0700+0x20)))&0xC000)==0x00)
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(c14:(0x0700+0x20)))&0xC000)==(0x4000||0xC000))
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x20)++0x00
line.long 0x00 "DBGWCR2,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Watchpoint 3"
if corename()=="CORTEXA55"
group.long c14:(0x0600+0x30)++0x00
line.long 0x00 "DBGWVR3,Watchpoint Value Register"
hexmask.long 0x00 2.--31. 0x04 "ADDRESS,Data address"
if (((per.l(c14:(0x0700+0x30)))&0x2000)==0x00)
if (((per.l(c14:(0x0700+0x30)))&0xC000)==(0x00||0x4000||0x8000))
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,User,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Secure"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
else
if (((per.l(c14:(0x0700+0x30)))&0xC000)==0x00)
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
elif (((per.l(c14:(0x0700+0x30)))&0xC000)==(0x4000||0xC000))
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Supervisor,System/Supervisor,Reserved,User/System/Supervisor"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
else
group.long c14:(0x0700+0x30)++0x00
line.long 0x00 "DBGWCR3,Watchpoint Control Register"
bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked"
bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,Both"
bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled"
hexmask.long.word 0x00 5.--12. 1. "BAS,Byte address select"
newline
bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both"
bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "Reserved,System,Reserved,User/System"
bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled"
endif
endif
else
textline "--------------------------------------------------------------------------------"
newline
textline "            These registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree.end
tree "DynamIQ Shared Unit"
tree "Cluster Control Registers"
if corename()=="CORTEXA55"
if (((per.l(c15:0x003F))&0x2000)==0x00)
rgroup.long c15:0x003F++0x00
line.long 0x00 "CLUSTERCFR,Cluster Configuration Register"
bitfld.long 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..."
newline
bitfld.long 0x00 17. "CRSP3,Core 3 Register slice present" "Not present,Present"
bitfld.long 0x00 16. "CRSP2,Core 2 Register slice present" "Not present,Present"
bitfld.long 0x00 15. "CRSP1,Core 1 Register slice present" "Not present,Present"
newline
bitfld.long 0x00 14. "CRSP0,Core 0 Register slice present" "Not present,Present"
bitfld.long 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended"
bitfld.long 0x00 12. "PPP,Peripheral port present" "Not present,Present"
newline
bitfld.long 0x00 11. "ACP,ACP interface present" "Not present,Present"
bitfld.long 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Single 256-bit CHI"
bitfld.long 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC"
newline
bitfld.long 0x00 7. "L3_DATA_RAM_RS,L3 data RAM Register slice present" "Not present,Present"
bitfld.long 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles"
bitfld.long 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles"
newline
bitfld.long 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present"
bitfld.long 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..."
else
rgroup.long c15:0x003F++0x00
line.long 0x00 "CLUSTERCFR,Cluster Configuration Register"
bitfld.long 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..."
newline
bitfld.long 0x00 17. "CRSP3,Core 3 Register slice present" "Not present,Present"
bitfld.long 0x00 16. "CRSP2,Core 2 Register slice present" "Not present,Present"
bitfld.long 0x00 15. "CRSP1,Core 1 Register slice present" "Not present,Present"
newline
bitfld.long 0x00 14. "CRSP0,Core 0 Register slice present" "Not present,Present"
bitfld.long 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended"
bitfld.long 0x00 12. "PPP,Peripheral port present" "Not present,Present"
newline
bitfld.long 0x00 11. "ACP,ACP interface present" "Not present,Present"
bitfld.long 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Dual 256-bit CHI"
bitfld.long 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC"
newline
bitfld.long 0x00 7. "L3_DATA_RAM_RS,L3 data RAM Register slice present" "Not present,Present"
bitfld.long 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles"
bitfld.long 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles"
newline
bitfld.long 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present"
bitfld.long 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..."
endif
rgroup.long c15:0x013F++0x00
line.long 0x00 "CLUSTERIDR,Cluster Main Revision ID"
hexmask.long.byte 0x00 4.--7. 1. "VARIANT,Indicates the variant of the DSU"
hexmask.long.byte 0x00 0.--3. 1. "REVISION,Indicates the minor revision number of the DSU"
rgroup.long c15:0x023F++0x00
line.long 0x00 "CLUSTERREVIDR,Cluster ECO ID"
rgroup.long c15:0x033F++0x00
line.long 0x00 "CLUSTERACTLR,Cluster Auxiliary Control Register"
if (((per.l(c15:0x003F))&0x600)==(0x00||0x200))
group.long c15:0x043F++0x00
line.long 0x00 "CLUSTERECTLR,Cluster Extended Control Register"
bitfld.long 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled"
bitfld.long 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128"
bitfld.long 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes"
newline
bitfld.long 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported"
bitfld.long 0x00 3. "CTEC,Clean/evict to external control disable" "No,Yes"
bitfld.long 0x00 2. "CFUCEC,Cache flush UniqueClean eviction control" "No,Yes"
newline
bitfld.long 0x00 0. "DNCWL,Disable non-cacheable write limit" "No,Yes"
else
group.long c15:0x043F++0x00
line.long 0x00 "CLUSTERECTLR,Cluster Extended Control Register"
bitfld.long 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled"
bitfld.long 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128"
bitfld.long 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes"
newline
bitfld.long 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported"
bitfld.long 0x00 3. "CTEC,Clean/evict to external control disable" "No,Yes"
bitfld.long 0x00 2. "CFUCEC,Cache flush UniqueClean eviction control" "No,Yes"
endif
group.long c15:0x053F++0x00
line.long 0x00 "CLUSTERPWRCTLR,Cluster Power Control Register"
bitfld.long 0x00 4.--7. "CPPR,Cache portion power request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--2. "FUNC_RET_CTRL,Duration of inactivity before the DSU uses CLUSTERPACTIVE" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks"
group.long c15:0x063F++0x00
line.long 0x00 "CLUSTERPWRDN,Cluster Power Down Register"
bitfld.long 0x00 1. "MRR,Memory retention required" "Not required,Required"
bitfld.long 0x00 0. "CPR,Cluster power required" "Not required,Required"
rgroup.long c15:0x073F++0x00
line.long 0x00 "CLUSTERPWRSTAT,Cluster Power Status Register"
bitfld.long 0x00 4.--7. "CPPS,This bits indicates which cache portions are currently powered up and available" "No ways,Ways 0-3,Reserved,Ways 0-7,Reserved,Reserved,Reserved,Ways 0-11,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ways 0-15"
bitfld.long 0x00 1. "RWPD,Enabled memory retention when all cores are powered down" "Disabled,Enabled"
bitfld.long 0x00 0. "DCPD,Disabled cluster power down when all cores are powered down" "No,Yes"
group.long c15:0x004F++0x00
line.long 0x00 "CLUSTERTHREADSID,Cluster Thread Scheme ID Register"
bitfld.long 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for current thread" "0,1,2,3,4,5,6,7"
group.long c15:0x014F++0x00
line.long 0x00 "CLUSTERACPSID,Cluster ACP Scheme ID Register"
bitfld.long 0x00 0.--2. "SCHEME_ID_ACP,Scheme ID for ACP transactions" "0,1,2,3,4,5,6,7"
group.long c15:0x024F++0x00
line.long 0x00 "CLUSTERSTASHSID,Cluster Stash Scheme ID Register"
bitfld.long 0x00 0.--2. "SCHEME_ID_SR,Scheme ID for stash requests received from the interconnect" "0,1,2,3,4,5,6,7"
group.long c15:0x034F++0x00
line.long 0x00 "CLUSTERPARTCR,Cluster Partition Control Register"
bitfld.long 0x00 31. "W3_ID7,Way group 3 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.long 0x00 30. "W2_ID7,Way group 2 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.long 0x00 29. "W1_ID7,Way group 1 is assigned as private to scheme ID 7" "Not assigned,Assigned"
newline
bitfld.long 0x00 28. "W0_ID7,Way group 0 is assigned as private to scheme ID 7" "Not assigned,Assigned"
bitfld.long 0x00 27. "W3_ID6,Way group 3 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.long 0x00 26. "W2_ID6,Way group 2 is assigned as private to scheme ID 6" "Not assigned,Assigned"
newline
bitfld.long 0x00 25. "W1_ID6,Way group 1 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.long 0x00 24. "W0_ID6,Way group 0 is assigned as private to scheme ID 6" "Not assigned,Assigned"
bitfld.long 0x00 23. "W3_ID5,Way group 3 is assigned as private to scheme ID 5" "Not assigned,Assigned"
newline
bitfld.long 0x00 22. "W2_ID5,Way group 2 is assigned as private to scheme ID 5" "Not assigned,Assigned"
bitfld.long 0x00 21. "W1_ID5,Way group 1 is assigned as private to scheme ID 5" "Not assigned,Assigned"
bitfld.long 0x00 20. "W0_ID5,Way group 0 is assigned as private to scheme ID 5" "Not assigned,Assigned"
newline
bitfld.long 0x00 19. "W3_ID4,Way group 3 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.long 0x00 18. "W2_ID4,Way group 2 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.long 0x00 17. "W1_ID4,Way group 1 is assigned as private to scheme ID 4" "Not assigned,Assigned"
newline
bitfld.long 0x00 16. "W0_ID4,Way group 0 is assigned as private to scheme ID 4" "Not assigned,Assigned"
bitfld.long 0x00 15. "W3_ID3,Way group 3 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.long 0x00 14. "W2_ID3,Way group 2 is assigned as private to scheme ID 3" "Not assigned,Assigned"
newline
bitfld.long 0x00 13. "W1_ID3,Way group 1 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.long 0x00 12. "W0_ID3,Way group 0 is assigned as private to scheme ID 3" "Not assigned,Assigned"
bitfld.long 0x00 11. "W3_ID2,Way group 3 is assigned as private to scheme ID 2" "Not assigned,Assigned"
newline
bitfld.long 0x00 10. "W2_ID2,Way group 2 is assigned as private to scheme ID 2" "Not assigned,Assigned"
bitfld.long 0x00 9. "W1_ID2,Way group 1 is assigned as private to scheme ID 2" "Not assigned,Assigned"
bitfld.long 0x00 8. "W0_ID2,Way group 0 is assigned as private to scheme ID 2" "Not assigned,Assigned"
newline
bitfld.long 0x00 7. "W3_ID1,Way group 3 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.long 0x00 6. "W2_ID1,Way group 2 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.long 0x00 5. "W1_ID1,Way group 1 is assigned as private to scheme ID 1" "Not assigned,Assigned"
newline
bitfld.long 0x00 4. "W0_ID1,Way group 0 is assigned as private to scheme ID 1" "Not assigned,Assigned"
bitfld.long 0x00 3. "W3_ID0,Way group 3 is assigned as private to scheme ID 0" "Not assigned,Assigned"
bitfld.long 0x00 2. "W2_ID0,Way group 2 is assigned as private to scheme ID 0" "Not assigned,Assigned"
newline
bitfld.long 0x00 1. "W1_ID0,Way group 1 is assigned as private to scheme ID 0" "Not assigned,Assigned"
bitfld.long 0x00 0. "W0_ID0,Way group 0 is assigned as private to scheme ID 0" "Not assigned,Assigned"
newline
group.long c15:0x044F++0x00
line.long 0x00 "CLUSTERBUSQOS,Cluster Bus QoS Control Register"
bitfld.long 0x00 28.--31. "CHI_BUS_QOS_SCHEME_ID7,Value driven on the CHI bus QoS field for scheme ID 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "CHI_BUS_QOS_SCHEME_ID6,Value driven on the CHI bus QoS field for scheme ID 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "CHI_BUS_QOS_SCHEME_ID5,Value driven on the CHI bus QoS field for scheme ID 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "CHI_BUS_QOS_SCHEME_ID4,Value driven on the CHI bus QoS field for scheme ID 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "CHI_BUS_QOS_SCHEME_ID3,Value driven on the CHI bus QoS field for scheme ID 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "CHI_BUS_QOS_SCHEME_ID2,Value driven on the CHI bus QoS field for scheme ID 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "CHI_BUS_QOS_SCHEME_ID1,Value driven on the CHI bus QoS field for scheme ID 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "CHI_BUS_QOS_SCHEME_ID0,Value driven on the CHI bus QoS field for scheme ID 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long c15:0x054F++0x00
line.long 0x00 "CLUSTERL3HIT,Cluster L3 Hit Counter Register"
group.long c15:0x064F++0x00
line.long 0x00 "CLUSTERL3MISS,Cluster L3 Miss Counter Register"
group.long c15:0x074F++0x00
line.long 0x00 "CLUSTERTHREADSIDOVR,Cluster Thread Scheme ID Override Register"
bitfld.long 0x00 16.--18. "SCHEME_ID_MASK,A bit set in the mask causes the matching bit to be taken from this Register rather than from the CLUSTERTHREADSID_EL1 Register" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for this thread if masked" "0,1,2,3,4,5,6,7"
elif corename()=="CORTEXA76"
textline "--------------------------------------------------------------------------------"
newline
textline "            These Registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Error System Registers"
if corename()=="CORTEXA55"
rgroup.long c15:0x0035++0x00
line.long 0x00 "ERRIDR,Error Record ID Register"
hexmask.long.word 0x00 0.--15. 1. "NUM,Number of records that can be accessed through the Error Record system Registers"
group.long c15:0x0135++0x00
line.long 0x00 "ERRSELR,Error Record Select Register"
bitfld.long 0x00 0. "SEL,Selects the record accessed through the Error Record system Registers" "Record 0,Record 1"
if (((per.l(c15:0x0135))&0x01)==0x00)
rgroup.long c15:0x0345++0x00
line.long 0x00 "ERXADDR,Selected Error Record Address Register"
rgroup.long c15:0x0745++0x00
line.long 0x00 "ERXADDR2,Selected Error Record Address Register 2"
group.long c15:0x0145++0x00
line.long 0x00 "ERXCTLR,Selected Error Record Control Register"
bitfld.long 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled"
bitfld.long 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "ED,Enable error detection" "Disabled,Enabled"
rgroup.long c15:0x0545++0x00
line.long 0x00 "ERXCTLR2,Selected Error Record Control Register 2"
rgroup.long c15:0x0045++0x00
line.long 0x00 "ERXFR,Selected Error Record Feature Register"
bitfld.long 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..."
bitfld.long 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.long 0x00 15. "RP,Indicates whether a repeat counter is implemented" ",1st and 2nd counter implemented"
newline
bitfld.long 0x00 12.--14. "CEC,Defines whether the node implements a standard CE counter mechanism in ERR<n>MISC0" ",,8bit error counter,?..."
bitfld.long 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" ",,Controllable,?..."
bitfld.long 0x00 8.--9. "UE,Uncorrected error reporting" ",Supported,?..."
newline
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" ",,Controllable,?..."
bitfld.long 0x00 4.--5. "UI,Uncorrected error recovery interrupt" ",,Controllable,?..."
bitfld.long 0x00 2.--3. "DE,Deferred errors" ",Always enabled,?..."
newline
bitfld.long 0x00 0.--1. "ED,Error detection and correction" ",,Controllable,?..."
rgroup.long c15:0x0445++0x00
line.long 0x00 "ERXFR2,Selected Error Record Feature Register 2"
bitfld.long 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..."
bitfld.long 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.long 0x00 15. "RP,Indicates whether a repeat counter is implemented" ",1st and 2nd counter implemented"
newline
bitfld.long 0x00 12.--14. "CEC,Defines whether the node implements a standard CE counter mechanism in ERR<n>MISC0" ",,8bit error counter,?..."
bitfld.long 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" ",,Controllable,?..."
bitfld.long 0x00 8.--9. "UE,Uncorrected error reporting" ",Supported,?..."
newline
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" ",,Controllable,?..."
bitfld.long 0x00 4.--5. "UI,Uncorrected error recovery interrupt" ",,Controllable,?..."
bitfld.long 0x00 2.--3. "DE,Deferred errors" ",Always enabled,?..."
newline
bitfld.long 0x00 0.--1. "ED,Error detection and correction" ",,Controllable,?..."
group.long c15:0x0055++0x00
line.long 0x00 "ERXMISC0,Selected Error Miscellaneous Register 0"
bitfld.long 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.long 0x00 1.--3. "L,Indicates the level that contained the error" "Level 1,Level 2,?..."
bitfld.long 0x00 0. "IND,Indicates the type of cache that contained the error" "Data cache(L1)/Unified cache(L2)/TLB,Instruction cache(L1)"
group.long c15:0x0155++0x00
line.long 0x00 "ERXMISC1,Selected Error Miscellaneous Register 1"
bitfld.long 0x00 15. "OFO,Other Error Count Overflow" "No overflow,Overflow"
hexmask.long.byte 0x00 8.--14. 1. "CECO,Other Error Count"
bitfld.long 0x00 7. "OFR,Repeat Error Count Overflow" "No overflow,Overflow"
newline
hexmask.long.byte 0x00 0.--6. 1. "CECR,Repeat Error Count"
rgroup.long c15:0x0455++0x00
line.long 0x00 "ERXMISC2,Selected Error Miscellaneous Register 2"
rgroup.long c15:0x0555++0x00
line.long 0x00 "ERXMISC3,Selected Error Miscellaneous Register 3"
group.long c15:0x0245++0x00
line.long 0x00 "ERXSTATUS,Selected Error Record Primary Status Register"
bitfld.long 0x00 31. "AV,Address Valid" "Not valid,?..."
bitfld.long 0x00 30. "V,Status Register valid" "Not valid,Valid"
bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.long 0x00 28. "ER,Error Reported" "No error,Error"
bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.long 0x00 26. "MV,Miscellaneous Registers Valid" "Not valid,Valid"
newline
bitfld.long 0x00 24.--25. "CE,Corrected Errors" "No error,,>=1 error,?..."
bitfld.long 0x00 23. "DE,Deferred Errors" "No error,>=1 error"
bitfld.long 0x00 22. "PN,Poison" "No distinction,?..."
newline
bitfld.long 0x00 20.--21. "UET,Uncorrected Error Type" "Uncontainable,?..."
bitfld.long 0x00 8.--15. "IERR,Implementation defined error code" "No error/Error not on dirty RAM,Error on L1 dirty RAM,?..."
bitfld.long 0x00 0.--7. "SERR,Primary error code" "No error,,ECC/Internal data buffer,,,,ECC/Cache data RAM,ECC/Cache tag/Dirty RAM,Parity error/TLB data RAM,Parity error/TLB tag RAM,,,,,,Deferred error from slave not supported at the consumer,?..."
group.long c15:0x022F++0x00
line.long 0x00 "ERXPFGCDN,Selected Error Pseudo Fault Generation Count Down Register"
group.long c15:0x012F++0x00
line.long 0x00 "ERXPFGCTL,Selected Error Pseudo Fault Generation Control Register"
bitfld.long 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled"
bitfld.long 0x00 30. "R,Restartable bit. Controls whether Error Generation Counter restarts from the ERR0PFGCDNR value or stops after reaching 0" "Counter stops,Counter restarts"
bitfld.long 0x00 6. "CE,Corrected Error generation enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled"
bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation enable" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
rgroup.long c15:0x002F++0x00
line.long 0x00 "ERXPFGF,Selected Pseudo Fault Generation Feature Register"
bitfld.long 0x00 31. "PFG,Pseudo Fault Generation" "Not supported,Supported"
bitfld.long 0x00 30. "R,Restartable bit" "Not supported,Controllable"
bitfld.long 0x00 6. "CE,Corrected Error generation" "Not supported,Controllable"
newline
bitfld.long 0x00 5. "DE,Deferred Error generation" "Not supported,Controllable"
bitfld.long 0x00 4. "UEO,Latent or Restartable Error generation" "Not supported,?..."
bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation" "Not supported,Controllable"
newline
bitfld.long 0x00 2. "UEU,Unrecoverable Error generation" "Not supported,?..."
bitfld.long 0x00 1. "UC,Uncontainable Error generation" "Not supported,Controllable"
else
rgroup.long c15:0x0345++0x00
line.long 0x00 "ERXADDR,Selected Error Record Address Register"
rgroup.long c15:0x0745++0x00
line.long 0x00 "ERXADDR2,Selected Error Record Address Register 2"
group.long c15:0x0145++0x00
line.long 0x00 "ERXCTLR,Selected Error Record Control Register"
bitfld.long 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled"
bitfld.long 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled"
newline
bitfld.long 0x00 0. "ED,Error reporting and logging enable" "Disabled,Enabled"
rgroup.long c15:0x0545++0x00
line.long 0x00 "ERXCTLR2,Selected Error Record Control Register 2"
rgroup.long c15:0x0045++0x00
line.long 0x00 "ERXFR,Selected Error Record Feature Register"
bitfld.long 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..."
bitfld.long 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.long 0x00 15. "RP,Indicates whether a repeat counter is implemented" ",1st and 2nd counter implemented"
newline
bitfld.long 0x00 12.--14. "CEC,Defines whether the node implements a standard CE counter mechanism in ERR<n>MISC0" ",,8bit error counter,?..."
bitfld.long 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" ",,Controllable,?..."
bitfld.long 0x00 8.--9. "UE,Uncorrected error reporting" ",Supported,?..."
newline
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" ",,Controllable,?..."
bitfld.long 0x00 4.--5. "UI,Uncorrected error recovery interrupt" ",,Controllable,?..."
bitfld.long 0x00 2.--3. "DE,Deferred errors" ",Always enabled,?..."
newline
bitfld.long 0x00 0.--1. "ED,Error detection and correction" ",,Controllable,?..."
rgroup.long c15:0x0445++0x00
line.long 0x00 "ERXFR2,Selected Error Record Feature Register 2"
bitfld.long 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..."
bitfld.long 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..."
bitfld.long 0x00 15. "RP,Indicates whether a repeat counter is implemented" ",1st and 2nd counter implemented"
newline
bitfld.long 0x00 12.--14. "CEC,Defines whether the node implements a standard CE counter mechanism in ERR<n>MISC0" ",,8bit error counter,?..."
bitfld.long 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" ",,Controllable,?..."
bitfld.long 0x00 8.--9. "UE,Uncorrected error reporting" ",Supported,?..."
newline
bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" ",,Controllable,?..."
bitfld.long 0x00 4.--5. "UI,Uncorrected error recovery interrupt" ",,Controllable,?..."
bitfld.long 0x00 2.--3. "DE,Deferred errors" ",Always enabled,?..."
newline
bitfld.long 0x00 0.--1. "ED,Error detection and correction" ",,Controllable,?..."
group.long c15:0x0055++0x00
line.long 0x00 "ERXMISC0,Selected Error Miscellaneous Register 0"
bitfld.long 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error"
newline
bitfld.long 0x00 1.--3. "L,Indicates the level that contained the error" ",,Level 3,?..."
bitfld.long 0x00 0. "IND,Indicates the type of cache that contained the error" "L3 cache,"
group.long c15:0x0155++0x00
line.long 0x00 "ERXMISC1,Selected Error Miscellaneous Register 1"
bitfld.long 0x00 15. "OFO,Other Error Count Overflow" "No overflow,Overflow"
hexmask.long.byte 0x00 8.--14. 1. "CECO,Other Error Count"
bitfld.long 0x00 7. "OFR,Repeat Error Count Overflow" "No overflow,Overflow"
newline
hexmask.long.byte 0x00 0.--6. 1. "CECR,Repeat Error Count"
rgroup.long c15:0x0455++0x00
line.long 0x00 "ERXMISC2,Selected Error Miscellaneous Register 2"
rgroup.long c15:0x0555++0x00
line.long 0x00 "ERXMISC3,Selected Error Miscellaneous Register 3"
group.long c15:0x0245++0x00
line.long 0x00 "ERXSTATUS,Selected Error Record Primary Status Register"
bitfld.long 0x00 31. "AV,Address Valid" "Not valid,?..."
bitfld.long 0x00 30. "V,Status Register valid" "Not valid,Valid"
bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error"
newline
bitfld.long 0x00 28. "ER,Error Reported" "No error,?..."
bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error"
bitfld.long 0x00 26. "MV,Miscellaneous Registers Valid" "Not valid,Valid"
newline
bitfld.long 0x00 24.--25. "CE,Corrected Errors" "No error,,>=1 error,?..."
bitfld.long 0x00 23. "DE,Deferred Errors" "No error,>=1 error"
bitfld.long 0x00 22. "PN,Poison" "No distinction,Uncorrected error"
newline
bitfld.long 0x00 20.--21. "UET,Uncorrected Error Type" "Uncontainable,?..."
bitfld.long 0x00 8.--15. "IERR,Implementation defined error code" "No error/Error on other RAMs,,Error on a L3 snoop filter RAM,?..."
bitfld.long 0x00 0.--7. "SERR,Primary error code" "No error,,ECC/Internal data buffer,,,,ECC/Cache data RAM,ECC/Cache tag/Dirty RAM,,,,,,,,,,,Bus error,?..."
group.long c15:0x022F++0x00
line.long 0x00 "ERXPFGCDN,Selected Error Pseudo Fault Generation Count Down Register"
group.long c15:0x012F++0x00
line.long 0x00 "ERXPFGCTL,Selected Error Pseudo Fault Generation Control Register"
bitfld.long 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled"
bitfld.long 0x00 30. "R,Restartable bit. Controls whether Error Generation Counter restarts from the ERR0PFGCDNR value or stops after reaching 0" "Counter stops,Counter restarts"
bitfld.long 0x00 6. "CE,Corrected Error generation enable" "Disabled,Enabled"
newline
bitfld.long 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled"
bitfld.long 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled"
newline
rgroup.long c15:0x002F++0x00
line.long 0x00 "ERXPFGF,Selected Pseudo Fault Generation Feature Register"
bitfld.long 0x00 31. "PFG,Pseudo Fault Generation" "Not supported,Supported"
bitfld.long 0x00 30. "R,Restartable bit" "Not supported,Controllable"
bitfld.long 0x00 6. "CE,Corrected Error generation" "Not supported,Controllable"
newline
bitfld.long 0x00 5. "DE,Deferred Error generation" "Not supported,Controllable"
bitfld.long 0x00 4. "UEO,Latent or Restartable Error generation" "Not supported,Controllable"
bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation" "Not supported,Controllable"
newline
bitfld.long 0x00 2. "UEU,Unrecoverable Error generation" "Not supported,Controllable"
bitfld.long 0x00 1. "UC,Uncontainable Error generation" "Not supported,Controllable"
endif
newline
elif corename()=="CORTEXA76"
textline "--------------------------------------------------------------------------------"
newline
textline "            These Registers are not available in CORTEXA76"
newline
textline "--------------------------------------------------------------------------------"
endif
tree.end
tree "Cluster PMU Registers"
group.long c15:0x005F++0x00
line.long 0x00 "CLUSTERPMCR,Cluster Performance Monitors Control Register"
hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code"
bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 4. "X,Export of events Enable" "Disabled,"
bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset"
bitfld.long 0x00 1. "P,Event Counter Reset" "No reset,Reset"
newline
bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled"
newline
group.long c15:0x015F++0x00
line.long 0x00 "CLUSTERPMCNTENSET,Cluster Count Enable Set Register"
bitfld.long 0x00 31. "C,Enables the cycle counter Register [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable"
group.long c15:0x025F++0x00
line.long 0x00 "CLUSTERPMCNTENCLR,Cluster Count Enable Clear Register"
bitfld.long 0x00 31. "C,Disables the cycle counter Register [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
bitfld.long 0x00 5. "P5,Event counter PMN 5 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 4. "P4,Event counter PMN 4 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 3. "P3,Event counter PMN 3 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
bitfld.long 0x00 2. "P2,Event counter PMN 2 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 1. "P1,Event counter PMN 1 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
bitfld.long 0x00 0. "P0,Event counter PMN 0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable"
group.long c15:0x035F++0x00
line.long 0x00 "CLUSTERPMOVSSET,Cluster Overflow Flag Status Set"
bitfld.long 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Set"
newline
bitfld.long 0x00 5. "P5,PMN5 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 4. "P4,PMN4 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 3. "P3,PMN3 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
newline
bitfld.long 0x00 2. "P2,PMN2 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 1. "P1,PMN1 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
bitfld.long 0x00 0. "P0,PMN0 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set"
group.long c15:0x045F++0x00
line.long 0x00 "CLUSTERPMOVSCLR,Cluster Overflow Flag Status Clear"
eventfld.long 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.long 0x00 5. "P5,PMN5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 4. "P4,PMN4 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 3. "P3,PMN3 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
newline
eventfld.long 0x00 2. "P2,PMN2 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 1. "P1,PMN1 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
eventfld.long 0x00 0. "P0,PMN0 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear"
group.long c15:0x055F++0x00
line.long 0x00 "CLUSTERPMSELR,Cluster Event Counter Selection Register"
bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long c15:0x065F++0x00
line.long 0x00 "CLUSTERPMINTENSET,Cluster Interrupt Enable Set Register"
bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
newline
bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable"
group.long c15:0x075F++0x00
line.long 0x00 "CLUSTERPMINTENCLR,Cluster Interrupt Enable Clear Register"
eventfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Request Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
newline
eventfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
eventfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable"
group.quad c15:0x006F++0x01
line.quad 0x00 "CLUSTERPMCCNTR,Cluster Performance Monitors Cycle Counter"
if (((per.l(c15:0x016F))&0x80000000)==0x80000000)
group.long c15:0x016F++0x00
line.long 0x00 "CLUSTERPMXEVTYPER,Cluster Selected Event Type and Filter Register"
bitfld.long 0x00 31. "S,Secure events filtering bit. Controls counting of events that are generated by Secure transactions" "Count Secure events,Not count Secure events"
bitfld.long 0x00 29. "NS,Non-secure events filtering bit. Controls counting of events that are generated by Non-secure transactions" "Not count Non-secure events,Count Non-secure events"
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
else
group.long c15:0x016F++0x00
line.long 0x00 "CLUSTERPMXEVTYPER,Cluster Selected Event Type and Filter Register"
bitfld.long 0x00 31. "S,Secure events filtering bit. Controls counting of events that are generated by Secure transactions" "Count Secure events,Not count Secure events"
bitfld.long 0x00 29. "NS,Non-secure events filtering bit. Controls counting of events that are generated by Non-secure transactions" "Count Non-secure events,Not count Non-secure events"
hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number"
endif
group.long c15:0x026F++0x00
line.long 0x00 "CLUSTERPMXEVCNTR,Cluster Selected Event Counter Register"
group.long c15:0x036F++0x00
line.long 0x00 "CLUSTERPMMDCR,Cluster Monitor Debug Configuration Register"
bitfld.long 0x00 0. "SPME,Secure Performance Monitors Enable" "Disabled,Enabled"
tree.open "Common Event Identification Registers"
rgroup.long c15:0x046F++0x00
line.long 0x00 "CLUSTERPMCEID0,Cluster Common Event Identification ID0 Register"
bitfld.long 0x00 30. "CHAIN,Chain" "Reserved,Implemented"
bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented"
bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented"
newline
bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented"
bitfld.long 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented"
rgroup.long c15:0x056F++0x00
line.long 0x00 "CLUSTERPMCEID1,Cluster Common Event Identification ID1 Register"
bitfld.long 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Reserved,Implemented"
bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Reserved,Implemented"
bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Reserved,Implemented"
newline
bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented"
tree.end
newline
group.long c15:0x066F++0x00
line.long 0x00 "CLUSTERPMCLAIMSET,Cluster Performance Monitor Claim Tag Set Register"
bitfld.long 0x00 3. "S[3],Set bit 3" "Low,High"
bitfld.long 0x00 2. "S[2],Set bit 2" "Low,High"
bitfld.long 0x00 1. "S[1],Set bit 1" "Low,High"
newline
bitfld.long 0x00 0. "S[0],Set bit 0" "Low,High"
group.long c15:0x076F++0x00
line.long 0x00 "CLUSTERPMCLAIMCLR,Cluster Performance Monitor Claim Tag Clear Register"
bitfld.long 0x00 3. "C[3],Clear bit 3" "Low,High"
bitfld.long 0x00 2. "C[2],Clear bit 2" "Low,High"
bitfld.long 0x00 1. "C[1],Clear bit 1" "Low,High"
newline
bitfld.long 0x00 0. "C[0],Clear bit 0" "Low,High"
tree.end
tree.end
tree.end
AUTOINDENT.OFF
AUTOINDENT.POP
tree.open "Interrupt Controller (GIC-600)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
base COMP.BASE("GICD",-1.)
width 17.
tree "Distributor Interface"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)))
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
bitfld.long 0x00 6. "       DS            ,Disable Security" "No,Yes"
textline "                          "
bitfld.long 0x00 5. " ARE_NS       ,Affinity Routing Enable" "Disabled,Enabled"
bitfld.long 0x00 4. "       ARE_S      ,Affinity Routing Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "       ENABLEGRP1S   ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1NS ,Enable Secure Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP0 ,Enable Group 0 interrupts" "Disabled,Enabled"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
bitfld.long 0x00 4. "       ARE_NS        ,Affinity Routing Enable" "Reserved,Enabled"
textline "                          "
bitfld.long 0x00 1. " ENABLEGRP1A  ,Enable Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICD_CTLR,Distributor Control Register"
rbitfld.long 0x00 31. " RWP          ,Register Write Pending. Indicates whether a register write is in progress or not" "Not pending,Pending"
bitfld.long 0x00 7. "    E1NWF      ,Enable 1 of N Wakeup Functionality" "Disabled,Enabled"
rbitfld.long 0x00 6. "       DS            ,Disable Security" "Reserved,Yes"
textline "                          "
bitfld.long 0x00 4. " ARE          ,Affinity Routing Enable" "Reserved,Enabled"
bitfld.long 0x00 1. "       ENABLEGRP1 ,Enable Group 1 interrupts" "Disabled,Enabled"
bitfld.long 0x00 0. "       ENABLEGRP0    ,Enable Group 0 interrupts" "Disabled,Enabled"
endif
rgroup.long 0x0004++0x03
line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register"
bitfld.long 0x00 25. " NO1N          ,Indicates whether 1 of N SPI interrupts are supported" "Supported,Not supported"
bitfld.long 0x00 24. "    A3V        ,Indicates whether the Distributor supports nonzero values of Affinity level 3" "Not supported,Supported"
bitfld.long 0x00 19.--23. "  IDBITS     ,The number of interrupt identifier bits supported" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..."
textline "                          "
bitfld.long 0x00 18. " DVIS          ,Direct virtual LPI injection support" "Not supported,Supported"
bitfld.long 0x00 17. "    LPIS       ,Indicates whether the implementation supports LPIs" "Not supported,Supported"
bitfld.long 0x00 16. "  MBIS       ,Indicates whether the implementation supports message-based interrupts by writing to Distributor registers" "Not supported,Supported"
textline "                          "
bitfld.long 0x00 10. " SECURITYEXTN  ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented"
bitfld.long 0x00 5.--7. "  CPUNUMBER  ,Reports the number of PEs that can be used when affinity routing is not enabled" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 0.--4. "              ITLN       ,Indicates the maximum SPI INTID that the GIC implementation supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Reserved"
rgroup.long 0x0008++0x03
line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. " PRODID        ,Indicates the product ID" "GIC-500,?,GIC-600,?..."
bitfld.long 0x00 16.--19. "          VAR        ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                          "
bitfld.long 0x00 12.--15. " REV           ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "               IMP        ,Implementer"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0020))
group.long 0x0020++0x03
line.long 0x00 "GICD_FCTLR,Function Control Register"
bitfld.long 0x00 21. " DCC           ,Disable Cache Conversion (DCC)" "Disable,Enable"
bitfld.long 0x00 18. "          SLPIA      ,Strict LPI Allocation (SLPIA).Controls whether LPI reverts to a fixed index behavior. This bit can only be written when in full sleep (quiescent)." "Not Strict,Strict"
bitfld.long 0x00 16.--17. "     NSACR      , Non-secure Access Control. This is the value that is used ifa SPI has an error." "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                          "
hexmask.long.word 0x00 4.--13. 1. " CGO           ,One bit per clock gate: 1 = Leave clock running. 0 = Use full clock gating."
bitfld.long 0x00 0. "             SIP        ,Scrub in progress. This bit is read and written by software. When a scrub is complete, the GIC clears the bit to 0." "Completed,In Progress"
else
group.long 0x0020++0x03
line.long 0x00 "GICD_FCTLR,Function Control Register"
bitfld.long 0x00 21. " DCC           ,Disable Cache Conversion (DCC)" "Disable,Enable"
bitfld.long 0x00 18. "          SLPIA      ,Strict LPI Allocation (SLPIA).Controls whether LPI reverts to a fixed index behavior. This bit can only be written when in full sleep (quiescent)." "Not Strict,Strict"
textline "                          "
hexmask.long.word 0x00 4.--13. 1. " CGO           ,One bit per clock gate: 1 = Leave clock running. 0 = Use full clock gating."
bitfld.long 0x00 0. "             SIP        ,Scrub in progress. This bit is read and written by software. When a scrub is complete, the GIC clears the bit to 0." "Completed,In Progress"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0024)))
group.long 0xE08++0x03
line.long 0x00 "GICD_SAC,Secure Access Control Register"
bitfld.long 0x00 2. " GICPNS        ,Allow Non-secure access to the GICP registers. This enables Non-secure access to Secure PMU data." "Not Allowed,Allowed"
bitfld.long 0x00 1. "      GICTNS     ,Allow Non-secure access to the GICT registers. This enables Non-secure access to Secure trace data." "Not Allowed,Allowed"
bitfld.long 0x00 0. "    DSL        ,Disable Security Lock. WriteOnce (WO) bit to lock GICD_CTLR.DS to be WO at its current value." "0,1"
else
hgroup.long 0xE08++0x03
hide.long 0x00 "GICD_SAC,Secure Access Control Register"
endif
wgroup.long 0x40++0x03
line.long 0x00 "GICD_SETSPI_NSR,Non-secure SPI Set Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
wgroup.long 0x48++0x03
line.long 0x00 "GICD_CLRSPI_NSR,Non-secure SPI Clear Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50))
wgroup.long 0x50++0x03
line.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x50++0x03
hide.long 0x00 "GICD_SETSPI_SR,Secure SPI Set Register (Non-secure access)"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58))
wgroup.long 0x58++0x03
line.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x58++0x03
hide.long 0x00 "GICD_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)"
endif
tree "Message Based Alias Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x10000)==0x10000)
wgroup.long 0x40++0x03
line.long 0x00 "GICA_SETSPI_NSR,Non-secure SPI Set Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
wgroup.long 0x48++0x03
line.long 0x00 "GICA_CLRSPI_NSR,Non-secure SPI Clear Register"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x50))
wgroup.long 0x50++0x03
line.long 0x00 "GICA_SETSPI_SR,Secure SPI Set Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x50++0x03
hide.long 0x00 "GICA_SETSPI_SR,Secure SPI Set Register (Non-secure access)"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x58))
wgroup.long 0x58++0x03
line.long 0x00 "GICA_CLRSPI_SR,Secure SPI Clear Register (Secure access)"
hexmask.long.word 0x00 0.--9. 1. " INTID        ,The INTID of the SPI"
else
hgroup.long 0x58++0x03
hide.long 0x00 "GICA_CLRSPI_SR,Secure SPI Clear Register (Non-secure access)"
endif
else
hgroup.long 0x40++0x03
hide.long 0x00 "GICA_SETSPI_NSR,Non-secure SPI Set Register"
hgroup.long 0x48++0x03
hide.long 0x00 "GICA_CLRSPI_NSR,Non-secure SPI Clear Register"
hgroup.long 0x50++0x03
hide.long 0x00 "GICA_SETSPI_SR,Secure SPI Set Register"
hgroup.long 0x58++0x03
hide.long 0x00 "GICA_CLRSPI_SR,Secure SPI Clear Register"
endif
tree.end
width 17.
tree "Group Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0080))
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)"
bitfld.long 0x00 31. " GSB31  ,Group Status Bit 31" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB30  ,Group Status Bit 30" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB29  ,Group Status Bit 29" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28  ,Group Status Bit 28" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB27  ,Group Status Bit 27" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB26  ,Group Status Bit 26" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25  ,Group Status Bit 25" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB24  ,Group Status Bit 24" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB23  ,Group Status Bit 23" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22  ,Group Status Bit 22" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB21  ,Group Status Bit 21" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB20  ,Group Status Bit 20" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19  ,Group Status Bit 19" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB18  ,Group Status Bit 18" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB17  ,Group Status Bit 17" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16  ,Group Status Bit 16" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB15  ,Group Status Bit 15" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB14  ,Group Status Bit 14" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13  ,Group Status Bit 13" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB12  ,Group Status Bit 12" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB11  ,Group Status Bit 11" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10  ,Group Status Bit 10" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB9   ,Group Status Bit 9" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB8   ,Group Status Bit 8" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7   ,Group Status Bit 7" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB6   ,Group Status Bit 6" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB5   ,Group Status Bit 5" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4   ,Group Status Bit 4" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB3   ,Group Status Bit 3" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB2   ,Group Status Bit 2" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1   ,Group Status Bit 1" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB0   ,Group Status Bit 0" "Secure,Non-secure Group 1"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)
group.long 0x0080++0x03
line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. " GSB31  ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB30  ,Group Status Bit 30" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB29  ,Group Status Bit 29" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB28  ,Group Status Bit 28" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB27  ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB26  ,Group Status Bit 26" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB25  ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB24  ,Group Status Bit 24" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB23  ,Group Status Bit 23" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB22  ,Group Status Bit 22" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB21  ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB20  ,Group Status Bit 20" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB19  ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB18  ,Group Status Bit 18" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB17  ,Group Status Bit 17" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB16  ,Group Status Bit 16" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB15  ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB14  ,Group Status Bit 14" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB13  ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB12  ,Group Status Bit 12" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB11  ,Group Status Bit 11" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB10  ,Group Status Bit 10" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB9   ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB8   ,Group Status Bit 8" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB7   ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB6   ,Group Status Bit 6" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB5   ,Group Status Bit 5" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB4   ,Group Status Bit 4" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB3   ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB2   ,Group Status Bit 2" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB1   ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB0   ,Group Status Bit 0" "Group 0,Group 1"
else
hgroup.long 0x0080++0x03
hide.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x84))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 (Secure Access)"
bitfld.long 0x00 31. " GSB63  ,Group Status Bit 63" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB62  ,Group Status Bit 62" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB61  ,Group Status Bit 61" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60  ,Group Status Bit 60" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB59  ,Group Status Bit 59" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB58  ,Group Status Bit 58" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57  ,Group Status Bit 57" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB56  ,Group Status Bit 56" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB55  ,Group Status Bit 55" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54  ,Group Status Bit 54" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB53  ,Group Status Bit 53" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB52  ,Group Status Bit 52" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51  ,Group Status Bit 51" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB50  ,Group Status Bit 50" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB49  ,Group Status Bit 49" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48  ,Group Status Bit 48" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB47  ,Group Status Bit 47" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB46  ,Group Status Bit 46" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45  ,Group Status Bit 45" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB44  ,Group Status Bit 44" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB43  ,Group Status Bit 43" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42  ,Group Status Bit 42" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB41  ,Group Status Bit 41" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB40  ,Group Status Bit 40" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39  ,Group Status Bit 39" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB38  ,Group Status Bit 38" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB37  ,Group Status Bit 37" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36  ,Group Status Bit 36" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB35  ,Group Status Bit 35" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB34  ,Group Status Bit 34" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33  ,Group Status Bit 33" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB32  ,Group Status Bit 32" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1))
group.long 0x0084++0x03
line.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
bitfld.long 0x00 31. " GSB63  ,Group Status Bit 63" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB62  ,Group Status Bit 62" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB61  ,Group Status Bit 61" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB60  ,Group Status Bit 60" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB59  ,Group Status Bit 59" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB58  ,Group Status Bit 58" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB57  ,Group Status Bit 57" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB56  ,Group Status Bit 56" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB55  ,Group Status Bit 55" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB54  ,Group Status Bit 54" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB53  ,Group Status Bit 53" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB52  ,Group Status Bit 52" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB51  ,Group Status Bit 51" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB50  ,Group Status Bit 50" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB49  ,Group Status Bit 49" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB48  ,Group Status Bit 48" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB47  ,Group Status Bit 47" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB46  ,Group Status Bit 46" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB45  ,Group Status Bit 45" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB44  ,Group Status Bit 44" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB43  ,Group Status Bit 43" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB42  ,Group Status Bit 42" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB41  ,Group Status Bit 41" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB40  ,Group Status Bit 40" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB39  ,Group Status Bit 39" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB38  ,Group Status Bit 38" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB37  ,Group Status Bit 37" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB36  ,Group Status Bit 36" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB35  ,Group Status Bit 35" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB34  ,Group Status Bit 34" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB33  ,Group Status Bit 33" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB32  ,Group Status Bit 32" "Group 0,Group 1"
else
hgroup.long 0x0084++0x03
hide.long 0x0 "GICD_IGROUPR1 ,Interrupt Group Register 1 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x88))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 (Secure Access)"
bitfld.long 0x00 31. " GSB95  ,Group Status Bit 95" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB94  ,Group Status Bit 94" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB93  ,Group Status Bit 93" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92  ,Group Status Bit 92" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB91  ,Group Status Bit 91" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB90  ,Group Status Bit 90" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89  ,Group Status Bit 89" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB88  ,Group Status Bit 88" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB87  ,Group Status Bit 87" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86  ,Group Status Bit 86" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB85  ,Group Status Bit 85" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB84  ,Group Status Bit 84" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83  ,Group Status Bit 83" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB82  ,Group Status Bit 82" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB81  ,Group Status Bit 81" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80  ,Group Status Bit 80" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB79  ,Group Status Bit 79" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB78  ,Group Status Bit 78" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77  ,Group Status Bit 77" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB76  ,Group Status Bit 76" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB75  ,Group Status Bit 75" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74  ,Group Status Bit 74" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB73  ,Group Status Bit 73" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB72  ,Group Status Bit 72" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71  ,Group Status Bit 71" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB70  ,Group Status Bit 70" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB69  ,Group Status Bit 69" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68  ,Group Status Bit 68" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB67  ,Group Status Bit 67" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB66  ,Group Status Bit 66" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65  ,Group Status Bit 65" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB64  ,Group Status Bit 64" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2))
group.long 0x0088++0x03
line.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
bitfld.long 0x00 31. " GSB95  ,Group Status Bit 95" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB94  ,Group Status Bit 94" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB93  ,Group Status Bit 93" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB92  ,Group Status Bit 92" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB91  ,Group Status Bit 91" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB90  ,Group Status Bit 90" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB89  ,Group Status Bit 89" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB88  ,Group Status Bit 88" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB87  ,Group Status Bit 87" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB86  ,Group Status Bit 86" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB85  ,Group Status Bit 85" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB84  ,Group Status Bit 84" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB83  ,Group Status Bit 83" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB82  ,Group Status Bit 82" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB81  ,Group Status Bit 81" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB80  ,Group Status Bit 80" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB79  ,Group Status Bit 79" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB78  ,Group Status Bit 78" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB77  ,Group Status Bit 77" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB76  ,Group Status Bit 76" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB75  ,Group Status Bit 75" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB74  ,Group Status Bit 74" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB73  ,Group Status Bit 73" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB72  ,Group Status Bit 72" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB71  ,Group Status Bit 71" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB70  ,Group Status Bit 70" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB69  ,Group Status Bit 69" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB68  ,Group Status Bit 68" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB67  ,Group Status Bit 67" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB66  ,Group Status Bit 66" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB65  ,Group Status Bit 65" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB64  ,Group Status Bit 64" "Group 0,Group 1"
else
hgroup.long 0x0088++0x03
hide.long 0x0 "GICD_IGROUPR2 ,Interrupt Group Register 2 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x8C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 (Secure Access)"
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB126 ,Group Status Bit 126" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB125 ,Group Status Bit 125" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB123 ,Group Status Bit 123" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB122 ,Group Status Bit 122" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB120 ,Group Status Bit 120" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB119 ,Group Status Bit 119" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB117 ,Group Status Bit 117" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB116 ,Group Status Bit 116" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB114 ,Group Status Bit 114" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB113 ,Group Status Bit 113" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB111 ,Group Status Bit 111" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB110 ,Group Status Bit 110" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB108 ,Group Status Bit 108" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB107 ,Group Status Bit 107" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB105 ,Group Status Bit 105" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB104 ,Group Status Bit 104" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB102 ,Group Status Bit 102" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB101 ,Group Status Bit 101" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB99  ,Group Status Bit 99" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB98  ,Group Status Bit 98" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97  ,Group Status Bit 97" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB96  ,Group Status Bit 96" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3))
group.long 0x008C++0x03
line.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB126 ,Group Status Bit 126" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB125 ,Group Status Bit 125" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB123 ,Group Status Bit 123" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB122 ,Group Status Bit 122" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB120 ,Group Status Bit 120" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB119 ,Group Status Bit 119" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB117 ,Group Status Bit 117" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB116 ,Group Status Bit 116" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB114 ,Group Status Bit 114" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB113 ,Group Status Bit 113" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB111 ,Group Status Bit 111" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB110 ,Group Status Bit 110" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB108 ,Group Status Bit 108" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB107 ,Group Status Bit 107" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB105 ,Group Status Bit 105" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB104 ,Group Status Bit 104" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB102 ,Group Status Bit 102" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB101 ,Group Status Bit 101" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB99  ,Group Status Bit 99" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB98  ,Group Status Bit 98" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB97  ,Group Status Bit 97" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB96  ,Group Status Bit 96" "Group 0,Group 1"
else
hgroup.long 0x008C++0x03
hide.long 0x0 "GICD_IGROUPR3 ,Interrupt Group Register 3 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x90))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 (Secure Access)"
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB158 ,Group Status Bit 158" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB157 ,Group Status Bit 157" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB155 ,Group Status Bit 155" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB154 ,Group Status Bit 154" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB152 ,Group Status Bit 152" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB151 ,Group Status Bit 151" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB149 ,Group Status Bit 149" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB148 ,Group Status Bit 148" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB146 ,Group Status Bit 146" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB145 ,Group Status Bit 145" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB143 ,Group Status Bit 143" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB142 ,Group Status Bit 142" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB140 ,Group Status Bit 140" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB139 ,Group Status Bit 139" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB137 ,Group Status Bit 137" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB136 ,Group Status Bit 136" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB134 ,Group Status Bit 134" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB133 ,Group Status Bit 133" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB131 ,Group Status Bit 131" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB130 ,Group Status Bit 130" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB128 ,Group Status Bit 128" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4))
group.long 0x0090++0x03
line.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB158 ,Group Status Bit 158" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB157 ,Group Status Bit 157" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB155 ,Group Status Bit 155" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB154 ,Group Status Bit 154" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB152 ,Group Status Bit 152" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB151 ,Group Status Bit 151" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB149 ,Group Status Bit 149" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB148 ,Group Status Bit 148" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB146 ,Group Status Bit 146" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB145 ,Group Status Bit 145" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB143 ,Group Status Bit 143" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB142 ,Group Status Bit 142" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB140 ,Group Status Bit 140" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB139 ,Group Status Bit 139" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB137 ,Group Status Bit 137" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB136 ,Group Status Bit 136" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB134 ,Group Status Bit 134" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB133 ,Group Status Bit 133" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB131 ,Group Status Bit 131" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB130 ,Group Status Bit 130" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB128 ,Group Status Bit 128" "Group 0,Group 1"
else
hgroup.long 0x0090++0x03
hide.long 0x0 "GICD_IGROUPR4 ,Interrupt Group Register 4 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x94))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 (Secure Access)"
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB190 ,Group Status Bit 190" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB189 ,Group Status Bit 189" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB187 ,Group Status Bit 187" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB186 ,Group Status Bit 186" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB184 ,Group Status Bit 184" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB183 ,Group Status Bit 183" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB181 ,Group Status Bit 181" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB180 ,Group Status Bit 180" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB178 ,Group Status Bit 178" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB177 ,Group Status Bit 177" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB175 ,Group Status Bit 175" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB174 ,Group Status Bit 174" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB172 ,Group Status Bit 172" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB171 ,Group Status Bit 171" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB169 ,Group Status Bit 169" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB168 ,Group Status Bit 168" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB166 ,Group Status Bit 166" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB165 ,Group Status Bit 165" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB163 ,Group Status Bit 163" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB162 ,Group Status Bit 162" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB160 ,Group Status Bit 160" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5))
group.long 0x0094++0x03
line.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB190 ,Group Status Bit 190" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB189 ,Group Status Bit 189" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB187 ,Group Status Bit 187" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB186 ,Group Status Bit 186" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB184 ,Group Status Bit 184" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB183 ,Group Status Bit 183" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB181 ,Group Status Bit 181" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB180 ,Group Status Bit 180" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB178 ,Group Status Bit 178" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB177 ,Group Status Bit 177" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB175 ,Group Status Bit 175" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB174 ,Group Status Bit 174" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB172 ,Group Status Bit 172" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB171 ,Group Status Bit 171" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB169 ,Group Status Bit 169" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB168 ,Group Status Bit 168" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB166 ,Group Status Bit 166" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB165 ,Group Status Bit 165" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB163 ,Group Status Bit 163" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB162 ,Group Status Bit 162" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB160 ,Group Status Bit 160" "Group 0,Group 1"
else
hgroup.long 0x0094++0x03
hide.long 0x0 "GICD_IGROUPR5 ,Interrupt Group Register 5 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x98))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 (Secure Access)"
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB222 ,Group Status Bit 222" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB221 ,Group Status Bit 221" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB219 ,Group Status Bit 219" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB218 ,Group Status Bit 218" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB216 ,Group Status Bit 216" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB215 ,Group Status Bit 215" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB213 ,Group Status Bit 213" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB212 ,Group Status Bit 212" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB210 ,Group Status Bit 210" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB209 ,Group Status Bit 209" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB207 ,Group Status Bit 207" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB206 ,Group Status Bit 206" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB204 ,Group Status Bit 204" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB203 ,Group Status Bit 203" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB201 ,Group Status Bit 201" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB200 ,Group Status Bit 200" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB198 ,Group Status Bit 198" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB197 ,Group Status Bit 197" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB195 ,Group Status Bit 195" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB194 ,Group Status Bit 194" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB192 ,Group Status Bit 192" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6))
group.long 0x0098++0x03
line.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB222 ,Group Status Bit 222" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB221 ,Group Status Bit 221" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB219 ,Group Status Bit 219" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB218 ,Group Status Bit 218" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB216 ,Group Status Bit 216" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB215 ,Group Status Bit 215" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB213 ,Group Status Bit 213" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB212 ,Group Status Bit 212" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB210 ,Group Status Bit 210" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB209 ,Group Status Bit 209" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB207 ,Group Status Bit 207" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB206 ,Group Status Bit 206" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB204 ,Group Status Bit 204" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB203 ,Group Status Bit 203" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB201 ,Group Status Bit 201" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB200 ,Group Status Bit 200" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB198 ,Group Status Bit 198" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB197 ,Group Status Bit 197" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB195 ,Group Status Bit 195" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB194 ,Group Status Bit 194" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB192 ,Group Status Bit 192" "Group 0,Group 1"
else
hgroup.long 0x0098++0x03
hide.long 0x0 "GICD_IGROUPR6 ,Interrupt Group Register 6 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x9C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 (Secure Access)"
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB254 ,Group Status Bit 254" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB253 ,Group Status Bit 253" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB251 ,Group Status Bit 251" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB250 ,Group Status Bit 250" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB248 ,Group Status Bit 248" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB247 ,Group Status Bit 247" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB245 ,Group Status Bit 245" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB244 ,Group Status Bit 244" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB242 ,Group Status Bit 242" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB241 ,Group Status Bit 241" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB239 ,Group Status Bit 239" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB238 ,Group Status Bit 238" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB236 ,Group Status Bit 236" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB235 ,Group Status Bit 235" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB233 ,Group Status Bit 233" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB232 ,Group Status Bit 232" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB230 ,Group Status Bit 230" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB229 ,Group Status Bit 229" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB227 ,Group Status Bit 227" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB226 ,Group Status Bit 226" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB224 ,Group Status Bit 224" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7))
group.long 0x009C++0x03
line.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB254 ,Group Status Bit 254" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB253 ,Group Status Bit 253" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB251 ,Group Status Bit 251" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB250 ,Group Status Bit 250" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB248 ,Group Status Bit 248" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB247 ,Group Status Bit 247" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB245 ,Group Status Bit 245" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB244 ,Group Status Bit 244" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB242 ,Group Status Bit 242" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB241 ,Group Status Bit 241" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB239 ,Group Status Bit 239" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB238 ,Group Status Bit 238" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB236 ,Group Status Bit 236" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB235 ,Group Status Bit 235" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB233 ,Group Status Bit 233" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB232 ,Group Status Bit 232" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB230 ,Group Status Bit 230" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB229 ,Group Status Bit 229" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB227 ,Group Status Bit 227" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB226 ,Group Status Bit 226" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB224 ,Group Status Bit 224" "Group 0,Group 1"
else
hgroup.long 0x009C++0x03
hide.long 0x0 "GICD_IGROUPR7 ,Interrupt Group Register 7 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 (Secure Access)"
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB286 ,Group Status Bit 286" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB285 ,Group Status Bit 285" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB283 ,Group Status Bit 283" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB282 ,Group Status Bit 282" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB280 ,Group Status Bit 280" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB279 ,Group Status Bit 279" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB277 ,Group Status Bit 277" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB276 ,Group Status Bit 276" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB274 ,Group Status Bit 274" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB273 ,Group Status Bit 273" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB271 ,Group Status Bit 271" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB270 ,Group Status Bit 270" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB268 ,Group Status Bit 268" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB267 ,Group Status Bit 267" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB265 ,Group Status Bit 265" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB264 ,Group Status Bit 264" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB262 ,Group Status Bit 262" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB261 ,Group Status Bit 261" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB259 ,Group Status Bit 259" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB258 ,Group Status Bit 258" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB256 ,Group Status Bit 256" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8))
group.long 0x00A0++0x03
line.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB286 ,Group Status Bit 286" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB285 ,Group Status Bit 285" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB283 ,Group Status Bit 283" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB282 ,Group Status Bit 282" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB280 ,Group Status Bit 280" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB279 ,Group Status Bit 279" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB277 ,Group Status Bit 277" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB276 ,Group Status Bit 276" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB274 ,Group Status Bit 274" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB273 ,Group Status Bit 273" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB271 ,Group Status Bit 271" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB270 ,Group Status Bit 270" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB268 ,Group Status Bit 268" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB267 ,Group Status Bit 267" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB265 ,Group Status Bit 265" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB264 ,Group Status Bit 264" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB262 ,Group Status Bit 262" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB261 ,Group Status Bit 261" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB259 ,Group Status Bit 259" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB258 ,Group Status Bit 258" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB256 ,Group Status Bit 256" "Group 0,Group 1"
else
hgroup.long 0x00A0++0x03
hide.long 0x0 "GICD_IGROUPR8 ,Interrupt Group Register 8 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 (Secure Access)"
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB318 ,Group Status Bit 318" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB317 ,Group Status Bit 317" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB315 ,Group Status Bit 315" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB314 ,Group Status Bit 314" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB312 ,Group Status Bit 312" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB311 ,Group Status Bit 311" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB309 ,Group Status Bit 309" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB308 ,Group Status Bit 308" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB306 ,Group Status Bit 306" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB305 ,Group Status Bit 305" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB303 ,Group Status Bit 303" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB302 ,Group Status Bit 302" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB300 ,Group Status Bit 300" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB299 ,Group Status Bit 299" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB297 ,Group Status Bit 297" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB296 ,Group Status Bit 296" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB294 ,Group Status Bit 294" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB293 ,Group Status Bit 293" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB291 ,Group Status Bit 291" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB290 ,Group Status Bit 290" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB288 ,Group Status Bit 288" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9))
group.long 0x00A4++0x03
line.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB318 ,Group Status Bit 318" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB317 ,Group Status Bit 317" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB315 ,Group Status Bit 315" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB314 ,Group Status Bit 314" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB312 ,Group Status Bit 312" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB311 ,Group Status Bit 311" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB309 ,Group Status Bit 309" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB308 ,Group Status Bit 308" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB306 ,Group Status Bit 306" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB305 ,Group Status Bit 305" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB303 ,Group Status Bit 303" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB302 ,Group Status Bit 302" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB300 ,Group Status Bit 300" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB299 ,Group Status Bit 299" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB297 ,Group Status Bit 297" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB296 ,Group Status Bit 296" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB294 ,Group Status Bit 294" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB293 ,Group Status Bit 293" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB291 ,Group Status Bit 291" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB290 ,Group Status Bit 290" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB288 ,Group Status Bit 288" "Group 0,Group 1"
else
hgroup.long 0x00A4++0x03
hide.long 0x0 "GICD_IGROUPR9 ,Interrupt Group Register 9 "
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xA8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure Access)"
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB350 ,Group Status Bit 350" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB349 ,Group Status Bit 349" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB347 ,Group Status Bit 347" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB346 ,Group Status Bit 346" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB344 ,Group Status Bit 344" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB343 ,Group Status Bit 343" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB341 ,Group Status Bit 341" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB340 ,Group Status Bit 340" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB338 ,Group Status Bit 338" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB337 ,Group Status Bit 337" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB335 ,Group Status Bit 335" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB334 ,Group Status Bit 334" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB332 ,Group Status Bit 332" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB331 ,Group Status Bit 331" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB329 ,Group Status Bit 329" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB328 ,Group Status Bit 328" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB326 ,Group Status Bit 326" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB325 ,Group Status Bit 325" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB323 ,Group Status Bit 323" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB322 ,Group Status Bit 322" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB320 ,Group Status Bit 320" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA))
group.long 0x00A8++0x03
line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB350 ,Group Status Bit 350" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB349 ,Group Status Bit 349" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB347 ,Group Status Bit 347" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB346 ,Group Status Bit 346" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB344 ,Group Status Bit 344" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB343 ,Group Status Bit 343" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB341 ,Group Status Bit 341" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB340 ,Group Status Bit 340" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB338 ,Group Status Bit 338" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB337 ,Group Status Bit 337" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB335 ,Group Status Bit 335" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB334 ,Group Status Bit 334" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB332 ,Group Status Bit 332" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB331 ,Group Status Bit 331" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB329 ,Group Status Bit 329" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB328 ,Group Status Bit 328" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB326 ,Group Status Bit 326" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB325 ,Group Status Bit 325" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB323 ,Group Status Bit 323" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB322 ,Group Status Bit 322" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB320 ,Group Status Bit 320" "Group 0,Group 1"
else
hgroup.long 0x00A8++0x03
hide.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xAC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure Access)"
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB382 ,Group Status Bit 382" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB381 ,Group Status Bit 381" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB379 ,Group Status Bit 379" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB378 ,Group Status Bit 378" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB376 ,Group Status Bit 376" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB375 ,Group Status Bit 375" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB373 ,Group Status Bit 373" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB372 ,Group Status Bit 372" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB370 ,Group Status Bit 370" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB369 ,Group Status Bit 369" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB367 ,Group Status Bit 367" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB366 ,Group Status Bit 366" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB364 ,Group Status Bit 364" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB363 ,Group Status Bit 363" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB361 ,Group Status Bit 361" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB360 ,Group Status Bit 360" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB358 ,Group Status Bit 358" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB357 ,Group Status Bit 357" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB355 ,Group Status Bit 355" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB354 ,Group Status Bit 354" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB352 ,Group Status Bit 352" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB))
group.long 0x00AC++0x03
line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB382 ,Group Status Bit 382" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB381 ,Group Status Bit 381" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB379 ,Group Status Bit 379" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB378 ,Group Status Bit 378" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB376 ,Group Status Bit 376" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB375 ,Group Status Bit 375" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB373 ,Group Status Bit 373" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB372 ,Group Status Bit 372" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB370 ,Group Status Bit 370" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB369 ,Group Status Bit 369" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB367 ,Group Status Bit 367" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB366 ,Group Status Bit 366" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB364 ,Group Status Bit 364" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB363 ,Group Status Bit 363" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB361 ,Group Status Bit 361" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB360 ,Group Status Bit 360" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB358 ,Group Status Bit 358" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB357 ,Group Status Bit 357" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB355 ,Group Status Bit 355" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB354 ,Group Status Bit 354" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB352 ,Group Status Bit 352" "Group 0,Group 1"
else
hgroup.long 0x00AC++0x03
hide.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure Access)"
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB414 ,Group Status Bit 414" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB413 ,Group Status Bit 413" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB411 ,Group Status Bit 411" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB410 ,Group Status Bit 410" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB408 ,Group Status Bit 408" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB407 ,Group Status Bit 407" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB405 ,Group Status Bit 405" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB404 ,Group Status Bit 404" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB402 ,Group Status Bit 402" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB401 ,Group Status Bit 401" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB399 ,Group Status Bit 399" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB398 ,Group Status Bit 398" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB396 ,Group Status Bit 396" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB395 ,Group Status Bit 395" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB393 ,Group Status Bit 393" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB392 ,Group Status Bit 392" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB390 ,Group Status Bit 390" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB389 ,Group Status Bit 389" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB387 ,Group Status Bit 387" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB386 ,Group Status Bit 386" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB384 ,Group Status Bit 384" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC))
group.long 0x00B0++0x03
line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB414 ,Group Status Bit 414" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB413 ,Group Status Bit 413" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB411 ,Group Status Bit 411" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB410 ,Group Status Bit 410" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB408 ,Group Status Bit 408" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB407 ,Group Status Bit 407" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB405 ,Group Status Bit 405" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB404 ,Group Status Bit 404" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB402 ,Group Status Bit 402" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB401 ,Group Status Bit 401" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB399 ,Group Status Bit 399" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB398 ,Group Status Bit 398" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB396 ,Group Status Bit 396" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB395 ,Group Status Bit 395" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB393 ,Group Status Bit 393" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB392 ,Group Status Bit 392" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB390 ,Group Status Bit 390" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB389 ,Group Status Bit 389" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB387 ,Group Status Bit 387" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB386 ,Group Status Bit 386" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB384 ,Group Status Bit 384" "Group 0,Group 1"
else
hgroup.long 0x00B0++0x03
hide.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure Access)"
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB446 ,Group Status Bit 446" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB445 ,Group Status Bit 445" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB443 ,Group Status Bit 443" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB442 ,Group Status Bit 442" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB440 ,Group Status Bit 440" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB439 ,Group Status Bit 439" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB437 ,Group Status Bit 437" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB436 ,Group Status Bit 436" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB434 ,Group Status Bit 434" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB433 ,Group Status Bit 433" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB431 ,Group Status Bit 431" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB430 ,Group Status Bit 430" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB428 ,Group Status Bit 428" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB427 ,Group Status Bit 427" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB425 ,Group Status Bit 425" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB424 ,Group Status Bit 424" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB422 ,Group Status Bit 422" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB421 ,Group Status Bit 421" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB419 ,Group Status Bit 419" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB418 ,Group Status Bit 418" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB416 ,Group Status Bit 416" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD))
group.long 0x00B4++0x03
line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB446 ,Group Status Bit 446" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB445 ,Group Status Bit 445" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB443 ,Group Status Bit 443" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB442 ,Group Status Bit 442" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB440 ,Group Status Bit 440" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB439 ,Group Status Bit 439" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB437 ,Group Status Bit 437" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB436 ,Group Status Bit 436" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB434 ,Group Status Bit 434" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB433 ,Group Status Bit 433" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB431 ,Group Status Bit 431" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB430 ,Group Status Bit 430" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB428 ,Group Status Bit 428" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB427 ,Group Status Bit 427" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB425 ,Group Status Bit 425" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB424 ,Group Status Bit 424" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB422 ,Group Status Bit 422" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB421 ,Group Status Bit 421" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB419 ,Group Status Bit 419" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB418 ,Group Status Bit 418" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB416 ,Group Status Bit 416" "Group 0,Group 1"
else
hgroup.long 0x00B4++0x03
hide.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xB8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure Access)"
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB478 ,Group Status Bit 478" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB477 ,Group Status Bit 477" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB475 ,Group Status Bit 475" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB474 ,Group Status Bit 474" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB472 ,Group Status Bit 472" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB471 ,Group Status Bit 471" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB469 ,Group Status Bit 469" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB468 ,Group Status Bit 468" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB466 ,Group Status Bit 466" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB465 ,Group Status Bit 465" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB463 ,Group Status Bit 463" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB462 ,Group Status Bit 462" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB460 ,Group Status Bit 460" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB459 ,Group Status Bit 459" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB457 ,Group Status Bit 457" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB456 ,Group Status Bit 456" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB454 ,Group Status Bit 454" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB453 ,Group Status Bit 453" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB451 ,Group Status Bit 451" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB450 ,Group Status Bit 450" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB448 ,Group Status Bit 448" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE))
group.long 0x00B8++0x03
line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB478 ,Group Status Bit 478" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB477 ,Group Status Bit 477" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB475 ,Group Status Bit 475" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB474 ,Group Status Bit 474" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB472 ,Group Status Bit 472" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB471 ,Group Status Bit 471" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB469 ,Group Status Bit 469" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB468 ,Group Status Bit 468" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB466 ,Group Status Bit 466" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB465 ,Group Status Bit 465" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB463 ,Group Status Bit 463" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB462 ,Group Status Bit 462" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB460 ,Group Status Bit 460" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB459 ,Group Status Bit 459" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB457 ,Group Status Bit 457" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB456 ,Group Status Bit 456" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB454 ,Group Status Bit 454" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB453 ,Group Status Bit 453" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB451 ,Group Status Bit 451" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB450 ,Group Status Bit 450" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB448 ,Group Status Bit 448" "Group 0,Group 1"
else
hgroup.long 0x00B8++0x03
hide.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xBC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure Access)"
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB510 ,Group Status Bit 510" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB509 ,Group Status Bit 509" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB507 ,Group Status Bit 507" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB506 ,Group Status Bit 506" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB504 ,Group Status Bit 504" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB503 ,Group Status Bit 503" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB501 ,Group Status Bit 501" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB500 ,Group Status Bit 500" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB498 ,Group Status Bit 498" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB497 ,Group Status Bit 497" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB495 ,Group Status Bit 495" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB494 ,Group Status Bit 494" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB492 ,Group Status Bit 492" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB491 ,Group Status Bit 491" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB489 ,Group Status Bit 489" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB488 ,Group Status Bit 488" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB486 ,Group Status Bit 486" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB485 ,Group Status Bit 485" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB483 ,Group Status Bit 483" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB482 ,Group Status Bit 482" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB480 ,Group Status Bit 480" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF))
group.long 0x00BC++0x03
line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB510 ,Group Status Bit 510" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB509 ,Group Status Bit 509" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB507 ,Group Status Bit 507" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB506 ,Group Status Bit 506" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB504 ,Group Status Bit 504" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB503 ,Group Status Bit 503" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB501 ,Group Status Bit 501" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB500 ,Group Status Bit 500" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB498 ,Group Status Bit 498" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB497 ,Group Status Bit 497" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB495 ,Group Status Bit 495" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB494 ,Group Status Bit 494" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB492 ,Group Status Bit 492" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB491 ,Group Status Bit 491" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB489 ,Group Status Bit 489" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB488 ,Group Status Bit 488" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB486 ,Group Status Bit 486" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB485 ,Group Status Bit 485" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB483 ,Group Status Bit 483" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB482 ,Group Status Bit 482" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB480 ,Group Status Bit 480" "Group 0,Group 1"
else
hgroup.long 0x00BC++0x03
hide.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure Access)"
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB542 ,Group Status Bit 542" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB541 ,Group Status Bit 541" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB539 ,Group Status Bit 539" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB538 ,Group Status Bit 538" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB536 ,Group Status Bit 536" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB535 ,Group Status Bit 535" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB533 ,Group Status Bit 533" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB532 ,Group Status Bit 532" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB530 ,Group Status Bit 530" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB529 ,Group Status Bit 529" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB527 ,Group Status Bit 527" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB526 ,Group Status Bit 526" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB524 ,Group Status Bit 524" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB523 ,Group Status Bit 523" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB521 ,Group Status Bit 521" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB520 ,Group Status Bit 520" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB518 ,Group Status Bit 518" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB517 ,Group Status Bit 517" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB515 ,Group Status Bit 515" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB514 ,Group Status Bit 514" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB512 ,Group Status Bit 512" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x00C0++0x03
line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB542 ,Group Status Bit 542" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB541 ,Group Status Bit 541" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB539 ,Group Status Bit 539" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB538 ,Group Status Bit 538" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB536 ,Group Status Bit 536" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB535 ,Group Status Bit 535" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB533 ,Group Status Bit 533" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB532 ,Group Status Bit 532" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB530 ,Group Status Bit 530" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB529 ,Group Status Bit 529" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB527 ,Group Status Bit 527" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB526 ,Group Status Bit 526" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB524 ,Group Status Bit 524" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB523 ,Group Status Bit 523" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB521 ,Group Status Bit 521" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB520 ,Group Status Bit 520" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB518 ,Group Status Bit 518" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB517 ,Group Status Bit 517" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB515 ,Group Status Bit 515" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB514 ,Group Status Bit 514" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB512 ,Group Status Bit 512" "Group 0,Group 1"
else
hgroup.long 0x00C0++0x03
hide.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure Access)"
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB574 ,Group Status Bit 574" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB573 ,Group Status Bit 573" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB571 ,Group Status Bit 571" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB570 ,Group Status Bit 570" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB568 ,Group Status Bit 568" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB567 ,Group Status Bit 567" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB565 ,Group Status Bit 565" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB564 ,Group Status Bit 564" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB562 ,Group Status Bit 562" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB561 ,Group Status Bit 561" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB559 ,Group Status Bit 559" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB558 ,Group Status Bit 558" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB556 ,Group Status Bit 556" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB555 ,Group Status Bit 555" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB553 ,Group Status Bit 553" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB552 ,Group Status Bit 552" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB550 ,Group Status Bit 550" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB549 ,Group Status Bit 549" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB547 ,Group Status Bit 547" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB546 ,Group Status Bit 546" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB544 ,Group Status Bit 544" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x00C4++0x03
line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB574 ,Group Status Bit 574" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB573 ,Group Status Bit 573" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB571 ,Group Status Bit 571" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB570 ,Group Status Bit 570" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB568 ,Group Status Bit 568" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB567 ,Group Status Bit 567" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB565 ,Group Status Bit 565" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB564 ,Group Status Bit 564" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB562 ,Group Status Bit 562" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB561 ,Group Status Bit 561" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB559 ,Group Status Bit 559" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB558 ,Group Status Bit 558" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB556 ,Group Status Bit 556" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB555 ,Group Status Bit 555" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB553 ,Group Status Bit 553" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB552 ,Group Status Bit 552" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB550 ,Group Status Bit 550" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB549 ,Group Status Bit 549" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB547 ,Group Status Bit 547" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB546 ,Group Status Bit 546" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB544 ,Group Status Bit 544" "Group 0,Group 1"
else
hgroup.long 0x00C4++0x03
hide.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xC8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure Access)"
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB606 ,Group Status Bit 606" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB605 ,Group Status Bit 605" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB603 ,Group Status Bit 603" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB602 ,Group Status Bit 602" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB600 ,Group Status Bit 600" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB599 ,Group Status Bit 599" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB597 ,Group Status Bit 597" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB596 ,Group Status Bit 596" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB594 ,Group Status Bit 594" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB593 ,Group Status Bit 593" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB591 ,Group Status Bit 591" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB590 ,Group Status Bit 590" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB588 ,Group Status Bit 588" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB587 ,Group Status Bit 587" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB585 ,Group Status Bit 585" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB584 ,Group Status Bit 584" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB582 ,Group Status Bit 582" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB581 ,Group Status Bit 581" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB579 ,Group Status Bit 579" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB578 ,Group Status Bit 578" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB576 ,Group Status Bit 576" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x00C8++0x03
line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB606 ,Group Status Bit 606" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB605 ,Group Status Bit 605" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB603 ,Group Status Bit 603" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB602 ,Group Status Bit 602" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB600 ,Group Status Bit 600" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB599 ,Group Status Bit 599" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB597 ,Group Status Bit 597" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB596 ,Group Status Bit 596" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB594 ,Group Status Bit 594" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB593 ,Group Status Bit 593" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB591 ,Group Status Bit 591" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB590 ,Group Status Bit 590" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB588 ,Group Status Bit 588" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB587 ,Group Status Bit 587" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB585 ,Group Status Bit 585" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB584 ,Group Status Bit 584" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB582 ,Group Status Bit 582" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB581 ,Group Status Bit 581" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB579 ,Group Status Bit 579" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB578 ,Group Status Bit 578" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB576 ,Group Status Bit 576" "Group 0,Group 1"
else
hgroup.long 0x00C8++0x03
hide.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xCC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure Access)"
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB638 ,Group Status Bit 638" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB637 ,Group Status Bit 637" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB635 ,Group Status Bit 635" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB634 ,Group Status Bit 634" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB632 ,Group Status Bit 632" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB631 ,Group Status Bit 631" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB629 ,Group Status Bit 629" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB628 ,Group Status Bit 628" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB626 ,Group Status Bit 626" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB625 ,Group Status Bit 625" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB623 ,Group Status Bit 623" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB622 ,Group Status Bit 622" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB620 ,Group Status Bit 620" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB619 ,Group Status Bit 619" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB617 ,Group Status Bit 617" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB616 ,Group Status Bit 616" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB614 ,Group Status Bit 614" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB613 ,Group Status Bit 613" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB611 ,Group Status Bit 611" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB610 ,Group Status Bit 610" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB608 ,Group Status Bit 608" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x00CC++0x03
line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB638 ,Group Status Bit 638" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB637 ,Group Status Bit 637" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB635 ,Group Status Bit 635" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB634 ,Group Status Bit 634" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB632 ,Group Status Bit 632" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB631 ,Group Status Bit 631" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB629 ,Group Status Bit 629" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB628 ,Group Status Bit 628" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB626 ,Group Status Bit 626" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB625 ,Group Status Bit 625" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB623 ,Group Status Bit 623" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB622 ,Group Status Bit 622" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB620 ,Group Status Bit 620" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB619 ,Group Status Bit 619" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB617 ,Group Status Bit 617" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB616 ,Group Status Bit 616" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB614 ,Group Status Bit 614" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB613 ,Group Status Bit 613" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB611 ,Group Status Bit 611" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB610 ,Group Status Bit 610" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB608 ,Group Status Bit 608" "Group 0,Group 1"
else
hgroup.long 0x00CC++0x03
hide.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure Access)"
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB670 ,Group Status Bit 670" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB669 ,Group Status Bit 669" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB667 ,Group Status Bit 667" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB666 ,Group Status Bit 666" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB664 ,Group Status Bit 664" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB663 ,Group Status Bit 663" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB661 ,Group Status Bit 661" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB660 ,Group Status Bit 660" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB658 ,Group Status Bit 658" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB657 ,Group Status Bit 657" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB655 ,Group Status Bit 655" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB654 ,Group Status Bit 654" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB652 ,Group Status Bit 652" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB651 ,Group Status Bit 651" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB649 ,Group Status Bit 649" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB648 ,Group Status Bit 648" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB646 ,Group Status Bit 646" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB645 ,Group Status Bit 645" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB643 ,Group Status Bit 643" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB642 ,Group Status Bit 642" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB640 ,Group Status Bit 640" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x00D0++0x03
line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB670 ,Group Status Bit 670" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB669 ,Group Status Bit 669" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB667 ,Group Status Bit 667" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB666 ,Group Status Bit 666" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB664 ,Group Status Bit 664" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB663 ,Group Status Bit 663" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB661 ,Group Status Bit 661" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB660 ,Group Status Bit 660" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB658 ,Group Status Bit 658" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB657 ,Group Status Bit 657" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB655 ,Group Status Bit 655" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB654 ,Group Status Bit 654" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB652 ,Group Status Bit 652" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB651 ,Group Status Bit 651" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB649 ,Group Status Bit 649" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB648 ,Group Status Bit 648" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB646 ,Group Status Bit 646" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB645 ,Group Status Bit 645" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB643 ,Group Status Bit 643" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB642 ,Group Status Bit 642" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB640 ,Group Status Bit 640" "Group 0,Group 1"
else
hgroup.long 0x00D0++0x03
hide.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure Access)"
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB702 ,Group Status Bit 702" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB701 ,Group Status Bit 701" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB699 ,Group Status Bit 699" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB698 ,Group Status Bit 698" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB696 ,Group Status Bit 696" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB695 ,Group Status Bit 695" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB693 ,Group Status Bit 693" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB692 ,Group Status Bit 692" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB690 ,Group Status Bit 690" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB689 ,Group Status Bit 689" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB687 ,Group Status Bit 687" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB686 ,Group Status Bit 686" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB684 ,Group Status Bit 684" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB683 ,Group Status Bit 683" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB681 ,Group Status Bit 681" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB680 ,Group Status Bit 680" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB678 ,Group Status Bit 678" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB677 ,Group Status Bit 677" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB675 ,Group Status Bit 675" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB674 ,Group Status Bit 674" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB672 ,Group Status Bit 672" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x00D4++0x03
line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB702 ,Group Status Bit 702" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB701 ,Group Status Bit 701" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB699 ,Group Status Bit 699" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB698 ,Group Status Bit 698" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB696 ,Group Status Bit 696" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB695 ,Group Status Bit 695" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB693 ,Group Status Bit 693" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB692 ,Group Status Bit 692" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB690 ,Group Status Bit 690" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB689 ,Group Status Bit 689" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB687 ,Group Status Bit 687" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB686 ,Group Status Bit 686" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB684 ,Group Status Bit 684" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB683 ,Group Status Bit 683" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB681 ,Group Status Bit 681" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB680 ,Group Status Bit 680" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB678 ,Group Status Bit 678" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB677 ,Group Status Bit 677" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB675 ,Group Status Bit 675" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB674 ,Group Status Bit 674" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB672 ,Group Status Bit 672" "Group 0,Group 1"
else
hgroup.long 0x00D4++0x03
hide.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xD8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure Access)"
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB734 ,Group Status Bit 734" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB733 ,Group Status Bit 733" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB731 ,Group Status Bit 731" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB730 ,Group Status Bit 730" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB728 ,Group Status Bit 728" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB727 ,Group Status Bit 727" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB725 ,Group Status Bit 725" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB724 ,Group Status Bit 724" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB722 ,Group Status Bit 722" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB721 ,Group Status Bit 721" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB719 ,Group Status Bit 719" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB718 ,Group Status Bit 718" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB716 ,Group Status Bit 716" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB715 ,Group Status Bit 715" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB713 ,Group Status Bit 713" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB712 ,Group Status Bit 712" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB710 ,Group Status Bit 710" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB709 ,Group Status Bit 709" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB707 ,Group Status Bit 707" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB706 ,Group Status Bit 706" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB704 ,Group Status Bit 704" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x00D8++0x03
line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB734 ,Group Status Bit 734" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB733 ,Group Status Bit 733" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB731 ,Group Status Bit 731" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB730 ,Group Status Bit 730" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB728 ,Group Status Bit 728" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB727 ,Group Status Bit 727" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB725 ,Group Status Bit 725" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB724 ,Group Status Bit 724" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB722 ,Group Status Bit 722" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB721 ,Group Status Bit 721" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB719 ,Group Status Bit 719" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB718 ,Group Status Bit 718" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB716 ,Group Status Bit 716" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB715 ,Group Status Bit 715" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB713 ,Group Status Bit 713" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB712 ,Group Status Bit 712" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB710 ,Group Status Bit 710" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB709 ,Group Status Bit 709" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB707 ,Group Status Bit 707" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB706 ,Group Status Bit 706" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB704 ,Group Status Bit 704" "Group 0,Group 1"
else
hgroup.long 0x00D8++0x03
hide.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xDC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure Access)"
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB766 ,Group Status Bit 766" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB765 ,Group Status Bit 765" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB763 ,Group Status Bit 763" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB762 ,Group Status Bit 762" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB760 ,Group Status Bit 760" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB759 ,Group Status Bit 759" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB757 ,Group Status Bit 757" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB756 ,Group Status Bit 756" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB754 ,Group Status Bit 754" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB753 ,Group Status Bit 753" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB751 ,Group Status Bit 751" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB750 ,Group Status Bit 750" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB748 ,Group Status Bit 748" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB747 ,Group Status Bit 747" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB745 ,Group Status Bit 745" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB744 ,Group Status Bit 744" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB742 ,Group Status Bit 742" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB741 ,Group Status Bit 741" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB739 ,Group Status Bit 739" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB738 ,Group Status Bit 738" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB736 ,Group Status Bit 736" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x00DC++0x03
line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB766 ,Group Status Bit 766" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB765 ,Group Status Bit 765" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB763 ,Group Status Bit 763" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB762 ,Group Status Bit 762" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB760 ,Group Status Bit 760" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB759 ,Group Status Bit 759" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB757 ,Group Status Bit 757" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB756 ,Group Status Bit 756" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB754 ,Group Status Bit 754" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB753 ,Group Status Bit 753" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB751 ,Group Status Bit 751" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB750 ,Group Status Bit 750" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB748 ,Group Status Bit 748" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB747 ,Group Status Bit 747" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB745 ,Group Status Bit 745" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB744 ,Group Status Bit 744" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB742 ,Group Status Bit 742" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB741 ,Group Status Bit 741" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB739 ,Group Status Bit 739" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB738 ,Group Status Bit 738" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB736 ,Group Status Bit 736" "Group 0,Group 1"
else
hgroup.long 0x00DC++0x03
hide.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure Access)"
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB798 ,Group Status Bit 798" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB797 ,Group Status Bit 797" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB795 ,Group Status Bit 795" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB794 ,Group Status Bit 794" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB792 ,Group Status Bit 792" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB791 ,Group Status Bit 791" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB789 ,Group Status Bit 789" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB788 ,Group Status Bit 788" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB786 ,Group Status Bit 786" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB785 ,Group Status Bit 785" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB783 ,Group Status Bit 783" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB782 ,Group Status Bit 782" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB780 ,Group Status Bit 780" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB779 ,Group Status Bit 779" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB777 ,Group Status Bit 777" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB776 ,Group Status Bit 776" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB774 ,Group Status Bit 774" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB773 ,Group Status Bit 773" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB771 ,Group Status Bit 771" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB770 ,Group Status Bit 770" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB768 ,Group Status Bit 768" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x00E0++0x03
line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB798 ,Group Status Bit 798" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB797 ,Group Status Bit 797" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB795 ,Group Status Bit 795" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB794 ,Group Status Bit 794" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB792 ,Group Status Bit 792" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB791 ,Group Status Bit 791" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB789 ,Group Status Bit 789" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB788 ,Group Status Bit 788" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB786 ,Group Status Bit 786" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB785 ,Group Status Bit 785" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB783 ,Group Status Bit 783" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB782 ,Group Status Bit 782" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB780 ,Group Status Bit 780" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB779 ,Group Status Bit 779" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB777 ,Group Status Bit 777" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB776 ,Group Status Bit 776" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB774 ,Group Status Bit 774" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB773 ,Group Status Bit 773" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB771 ,Group Status Bit 771" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB770 ,Group Status Bit 770" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB768 ,Group Status Bit 768" "Group 0,Group 1"
else
hgroup.long 0x00E0++0x03
hide.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure Access)"
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB830 ,Group Status Bit 830" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB829 ,Group Status Bit 829" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB827 ,Group Status Bit 827" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB826 ,Group Status Bit 826" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB824 ,Group Status Bit 824" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB823 ,Group Status Bit 823" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB821 ,Group Status Bit 821" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB820 ,Group Status Bit 820" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB818 ,Group Status Bit 818" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB817 ,Group Status Bit 817" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB815 ,Group Status Bit 815" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB814 ,Group Status Bit 814" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB812 ,Group Status Bit 812" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB811 ,Group Status Bit 811" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB809 ,Group Status Bit 809" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB808 ,Group Status Bit 808" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB806 ,Group Status Bit 806" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB805 ,Group Status Bit 805" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB803 ,Group Status Bit 803" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB802 ,Group Status Bit 802" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB800 ,Group Status Bit 800" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x00E4++0x03
line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB830 ,Group Status Bit 830" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB829 ,Group Status Bit 829" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB827 ,Group Status Bit 827" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB826 ,Group Status Bit 826" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB824 ,Group Status Bit 824" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB823 ,Group Status Bit 823" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB821 ,Group Status Bit 821" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB820 ,Group Status Bit 820" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB818 ,Group Status Bit 818" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB817 ,Group Status Bit 817" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB815 ,Group Status Bit 815" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB814 ,Group Status Bit 814" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB812 ,Group Status Bit 812" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB811 ,Group Status Bit 811" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB809 ,Group Status Bit 809" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB808 ,Group Status Bit 808" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB806 ,Group Status Bit 806" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB805 ,Group Status Bit 805" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB803 ,Group Status Bit 803" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB802 ,Group Status Bit 802" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB800 ,Group Status Bit 800" "Group 0,Group 1"
else
hgroup.long 0x00E4++0x03
hide.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure Access)"
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB862 ,Group Status Bit 862" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB861 ,Group Status Bit 861" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB859 ,Group Status Bit 859" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB858 ,Group Status Bit 858" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB856 ,Group Status Bit 856" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB855 ,Group Status Bit 855" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB853 ,Group Status Bit 853" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB852 ,Group Status Bit 852" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB850 ,Group Status Bit 850" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB849 ,Group Status Bit 849" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB847 ,Group Status Bit 847" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB846 ,Group Status Bit 846" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB844 ,Group Status Bit 844" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB843 ,Group Status Bit 843" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB841 ,Group Status Bit 841" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB840 ,Group Status Bit 840" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB838 ,Group Status Bit 838" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB837 ,Group Status Bit 837" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB835 ,Group Status Bit 835" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB834 ,Group Status Bit 834" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB832 ,Group Status Bit 832" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A))
group.long 0x00E8++0x03
line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB862 ,Group Status Bit 862" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB861 ,Group Status Bit 861" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB859 ,Group Status Bit 859" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB858 ,Group Status Bit 858" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB856 ,Group Status Bit 856" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB855 ,Group Status Bit 855" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB853 ,Group Status Bit 853" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB852 ,Group Status Bit 852" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB850 ,Group Status Bit 850" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB849 ,Group Status Bit 849" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB847 ,Group Status Bit 847" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB846 ,Group Status Bit 846" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB844 ,Group Status Bit 844" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB843 ,Group Status Bit 843" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB841 ,Group Status Bit 841" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB840 ,Group Status Bit 840" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB838 ,Group Status Bit 838" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB837 ,Group Status Bit 837" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB835 ,Group Status Bit 835" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB834 ,Group Status Bit 834" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB832 ,Group Status Bit 832" "Group 0,Group 1"
else
hgroup.long 0x00E8++0x03
hide.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure Access)"
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB894 ,Group Status Bit 894" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB893 ,Group Status Bit 893" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB891 ,Group Status Bit 891" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB890 ,Group Status Bit 890" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB888 ,Group Status Bit 888" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB887 ,Group Status Bit 887" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB885 ,Group Status Bit 885" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB884 ,Group Status Bit 884" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB882 ,Group Status Bit 882" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB881 ,Group Status Bit 881" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB879 ,Group Status Bit 879" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB878 ,Group Status Bit 878" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB876 ,Group Status Bit 876" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB875 ,Group Status Bit 875" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB873 ,Group Status Bit 873" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB872 ,Group Status Bit 872" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB870 ,Group Status Bit 870" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB869 ,Group Status Bit 869" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB867 ,Group Status Bit 867" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB866 ,Group Status Bit 866" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB864 ,Group Status Bit 864" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x00EC++0x03
line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB894 ,Group Status Bit 894" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB893 ,Group Status Bit 893" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB891 ,Group Status Bit 891" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB890 ,Group Status Bit 890" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB888 ,Group Status Bit 888" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB887 ,Group Status Bit 887" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB885 ,Group Status Bit 885" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB884 ,Group Status Bit 884" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB882 ,Group Status Bit 882" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB881 ,Group Status Bit 881" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB879 ,Group Status Bit 879" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB878 ,Group Status Bit 878" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB876 ,Group Status Bit 876" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB875 ,Group Status Bit 875" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB873 ,Group Status Bit 873" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB872 ,Group Status Bit 872" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB870 ,Group Status Bit 870" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB869 ,Group Status Bit 869" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB867 ,Group Status Bit 867" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB866 ,Group Status Bit 866" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB864 ,Group Status Bit 864" "Group 0,Group 1"
else
hgroup.long 0x00EC++0x03
hide.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF0))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure Access)"
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB926 ,Group Status Bit 926" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB925 ,Group Status Bit 925" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB923 ,Group Status Bit 923" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB922 ,Group Status Bit 922" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB920 ,Group Status Bit 920" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB919 ,Group Status Bit 919" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB917 ,Group Status Bit 917" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB916 ,Group Status Bit 916" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB914 ,Group Status Bit 914" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB913 ,Group Status Bit 913" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB911 ,Group Status Bit 911" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB910 ,Group Status Bit 910" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB908 ,Group Status Bit 908" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB907 ,Group Status Bit 907" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB905 ,Group Status Bit 905" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB904 ,Group Status Bit 904" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB902 ,Group Status Bit 902" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB901 ,Group Status Bit 901" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB899 ,Group Status Bit 899" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB898 ,Group Status Bit 898" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB896 ,Group Status Bit 896" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x00F0++0x03
line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB926 ,Group Status Bit 926" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB925 ,Group Status Bit 925" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB923 ,Group Status Bit 923" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB922 ,Group Status Bit 922" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB920 ,Group Status Bit 920" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB919 ,Group Status Bit 919" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB917 ,Group Status Bit 917" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB916 ,Group Status Bit 916" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB914 ,Group Status Bit 914" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB913 ,Group Status Bit 913" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB911 ,Group Status Bit 911" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB910 ,Group Status Bit 910" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB908 ,Group Status Bit 908" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB907 ,Group Status Bit 907" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB905 ,Group Status Bit 905" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB904 ,Group Status Bit 904" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB902 ,Group Status Bit 902" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB901 ,Group Status Bit 901" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB899 ,Group Status Bit 899" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB898 ,Group Status Bit 898" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB896 ,Group Status Bit 896" "Group 0,Group 1"
else
hgroup.long 0x00F0++0x03
hide.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF4))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure Access)"
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB958 ,Group Status Bit 958" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB957 ,Group Status Bit 957" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB955 ,Group Status Bit 955" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB954 ,Group Status Bit 954" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB952 ,Group Status Bit 952" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB951 ,Group Status Bit 951" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB949 ,Group Status Bit 949" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB948 ,Group Status Bit 948" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB946 ,Group Status Bit 946" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB945 ,Group Status Bit 945" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB943 ,Group Status Bit 943" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB942 ,Group Status Bit 942" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB940 ,Group Status Bit 940" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB939 ,Group Status Bit 939" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB937 ,Group Status Bit 937" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB936 ,Group Status Bit 936" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB934 ,Group Status Bit 934" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB933 ,Group Status Bit 933" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB931 ,Group Status Bit 931" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB930 ,Group Status Bit 930" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB928 ,Group Status Bit 928" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x00F4++0x03
line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB958 ,Group Status Bit 958" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB957 ,Group Status Bit 957" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB955 ,Group Status Bit 955" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB954 ,Group Status Bit 954" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB952 ,Group Status Bit 952" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB951 ,Group Status Bit 951" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB949 ,Group Status Bit 949" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB948 ,Group Status Bit 948" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB946 ,Group Status Bit 946" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB945 ,Group Status Bit 945" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB943 ,Group Status Bit 943" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB942 ,Group Status Bit 942" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB940 ,Group Status Bit 940" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB939 ,Group Status Bit 939" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB937 ,Group Status Bit 937" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB936 ,Group Status Bit 936" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB934 ,Group Status Bit 934" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB933 ,Group Status Bit 933" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB931 ,Group Status Bit 931" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB930 ,Group Status Bit 930" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB928 ,Group Status Bit 928" "Group 0,Group 1"
else
hgroup.long 0x00F4++0x03
hide.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xF8))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure Access)"
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB990 ,Group Status Bit 990" "Secure,Non-secure Group 1"
bitfld.long 0x00 29. "  GSB989 ,Group Status Bit 989" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Secure,Non-secure Group 1"
bitfld.long 0x00 27. "  GSB987 ,Group Status Bit 987" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB986 ,Group Status Bit 986" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB984 ,Group Status Bit 984" "Secure,Non-secure Group 1"
bitfld.long 0x00 23. "  GSB983 ,Group Status Bit 983" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Secure,Non-secure Group 1"
bitfld.long 0x00 21. "  GSB981 ,Group Status Bit 981" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB980 ,Group Status Bit 980" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB978 ,Group Status Bit 978" "Secure,Non-secure Group 1"
bitfld.long 0x00 17. "  GSB977 ,Group Status Bit 977" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Secure,Non-secure Group 1"
bitfld.long 0x00 15. "  GSB975 ,Group Status Bit 975" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB974 ,Group Status Bit 974" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB972 ,Group Status Bit 972" "Secure,Non-secure Group 1"
bitfld.long 0x00 11. "  GSB971 ,Group Status Bit 971" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Secure,Non-secure Group 1"
bitfld.long 0x00 9. "  GSB969 ,Group Status Bit 969" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB968 ,Group Status Bit 968" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB966 ,Group Status Bit 966" "Secure,Non-secure Group 1"
bitfld.long 0x00 5. "  GSB965 ,Group Status Bit 965" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Secure,Non-secure Group 1"
bitfld.long 0x00 3. "  GSB963 ,Group Status Bit 963" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB962 ,Group Status Bit 962" "Secure,Non-secure Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB960 ,Group Status Bit 960" "Secure,Non-secure Group 1"
elif ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x00F8++0x03
line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB990 ,Group Status Bit 990" "Group 0,Group 1"
bitfld.long 0x00 29. "             GSB989 ,Group Status Bit 989" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1"
bitfld.long 0x00 27. "             GSB987 ,Group Status Bit 987" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB986 ,Group Status Bit 986" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB984 ,Group Status Bit 984" "Group 0,Group 1"
bitfld.long 0x00 23. "             GSB983 ,Group Status Bit 983" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1"
bitfld.long 0x00 21. "             GSB981 ,Group Status Bit 981" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB980 ,Group Status Bit 980" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB978 ,Group Status Bit 978" "Group 0,Group 1"
bitfld.long 0x00 17. "             GSB977 ,Group Status Bit 977" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1"
bitfld.long 0x00 15. "             GSB975 ,Group Status Bit 975" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB974 ,Group Status Bit 974" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB972 ,Group Status Bit 972" "Group 0,Group 1"
bitfld.long 0x00 11. "             GSB971 ,Group Status Bit 971" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1"
bitfld.long 0x00 9. "             GSB969 ,Group Status Bit 969" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB968 ,Group Status Bit 968" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB966 ,Group Status Bit 966" "Group 0,Group 1"
bitfld.long 0x00 5. "             GSB965 ,Group Status Bit 965" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1"
bitfld.long 0x00 3. "             GSB963 ,Group Status Bit 963" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB962 ,Group Status Bit 962" "Group 0,Group 1"
textline "                          "
bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB960 ,Group Status Bit 960" "Group 0,Group 1"
else
hgroup.long 0x00F8++0x03
hide.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30"
endif
tree.end
width 24.
tree "Set/Clear Enable Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0100++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0100++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31   ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB30   ,Set/Clear Enable Bit 30" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB29   ,Set/Clear Enable Bit 29" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28   ,Set/Clear Enable Bit 28" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB27   ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB26   ,Set/Clear Enable Bit 26" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25   ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB24   ,Set/Clear Enable Bit 24" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB23   ,Set/Clear Enable Bit 23" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22   ,Set/Clear Enable Bit 22" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB21   ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB20   ,Set/Clear Enable Bit 20" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19   ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB18   ,Set/Clear Enable Bit 18" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB17   ,Set/Clear Enable Bit 17" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16   ,Set/Clear Enable Bit 16" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB15   ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB14   ,Set/Clear Enable Bit 14" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13   ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB12   ,Set/Clear Enable Bit 12" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB11   ,Set/Clear Enable Bit 11" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10   ,Set/Clear Enable Bit 10" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB9    ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB8    ,Set/Clear Enable Bit 8" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7    ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB6    ,Set/Clear Enable Bit 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB5    ,Set/Clear Enable Bit 5" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4    ,Set/Clear Enable Bit 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB3    ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB2    ,Set/Clear Enable Bit 2" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1    ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB0    ,Set/Clear Enable Bit 0" "Disabled,Enabled"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0104++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63   ,Set/Clear Enable Bit 63" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB62   ,Set/Clear Enable Bit 62" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB61   ,Set/Clear Enable Bit 61" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60   ,Set/Clear Enable Bit 60" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB59   ,Set/Clear Enable Bit 59" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB58   ,Set/Clear Enable Bit 58" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57   ,Set/Clear Enable Bit 57" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB56   ,Set/Clear Enable Bit 56" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB55   ,Set/Clear Enable Bit 55" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54   ,Set/Clear Enable Bit 54" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB53   ,Set/Clear Enable Bit 53" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB52   ,Set/Clear Enable Bit 52" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51   ,Set/Clear Enable Bit 51" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB50   ,Set/Clear Enable Bit 50" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB49   ,Set/Clear Enable Bit 49" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48   ,Set/Clear Enable Bit 48" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB47   ,Set/Clear Enable Bit 47" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB46   ,Set/Clear Enable Bit 46" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45   ,Set/Clear Enable Bit 45" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB44   ,Set/Clear Enable Bit 44" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB43   ,Set/Clear Enable Bit 43" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42   ,Set/Clear Enable Bit 42" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB41   ,Set/Clear Enable Bit 41" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB40   ,Set/Clear Enable Bit 40" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39   ,Set/Clear Enable Bit 39" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB38   ,Set/Clear Enable Bit 38" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB37   ,Set/Clear Enable Bit 37" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36   ,Set/Clear Enable Bit 36" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB35   ,Set/Clear Enable Bit 35" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB34   ,Set/Clear Enable Bit 34" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33   ,Set/Clear Enable Bit 33" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB32   ,Set/Clear Enable Bit 32" "Disabled,Enabled"
else
hgroup.long 0x0104++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0108++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95   ,Set/Clear Enable Bit 95" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB94   ,Set/Clear Enable Bit 94" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB93   ,Set/Clear Enable Bit 93" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92   ,Set/Clear Enable Bit 92" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB91   ,Set/Clear Enable Bit 91" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB90   ,Set/Clear Enable Bit 90" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89   ,Set/Clear Enable Bit 89" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB88   ,Set/Clear Enable Bit 88" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB87   ,Set/Clear Enable Bit 87" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86   ,Set/Clear Enable Bit 86" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB85   ,Set/Clear Enable Bit 85" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB84   ,Set/Clear Enable Bit 84" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83   ,Set/Clear Enable Bit 83" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB82   ,Set/Clear Enable Bit 82" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB81   ,Set/Clear Enable Bit 81" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80   ,Set/Clear Enable Bit 80" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB79   ,Set/Clear Enable Bit 79" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB78   ,Set/Clear Enable Bit 78" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77   ,Set/Clear Enable Bit 77" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB76   ,Set/Clear Enable Bit 76" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB75   ,Set/Clear Enable Bit 75" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74   ,Set/Clear Enable Bit 74" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB73   ,Set/Clear Enable Bit 73" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB72   ,Set/Clear Enable Bit 72" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71   ,Set/Clear Enable Bit 71" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB70   ,Set/Clear Enable Bit 70" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB69   ,Set/Clear Enable Bit 69" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68   ,Set/Clear Enable Bit 68" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB67   ,Set/Clear Enable Bit 67" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB66   ,Set/Clear Enable Bit 66" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65   ,Set/Clear Enable Bit 65" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB64   ,Set/Clear Enable Bit 64" "Disabled,Enabled"
else
hgroup.long 0x0108++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x010C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127  ,Set/Clear Enable Bit 127" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB126  ,Set/Clear Enable Bit 126" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB125  ,Set/Clear Enable Bit 125" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124  ,Set/Clear Enable Bit 124" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB123  ,Set/Clear Enable Bit 123" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB122  ,Set/Clear Enable Bit 122" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121  ,Set/Clear Enable Bit 121" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB120  ,Set/Clear Enable Bit 120" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB119  ,Set/Clear Enable Bit 119" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118  ,Set/Clear Enable Bit 118" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB117  ,Set/Clear Enable Bit 117" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB116  ,Set/Clear Enable Bit 116" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115  ,Set/Clear Enable Bit 115" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB114  ,Set/Clear Enable Bit 114" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB113  ,Set/Clear Enable Bit 113" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112  ,Set/Clear Enable Bit 112" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB111  ,Set/Clear Enable Bit 111" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB110  ,Set/Clear Enable Bit 110" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109  ,Set/Clear Enable Bit 109" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB108  ,Set/Clear Enable Bit 108" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB107  ,Set/Clear Enable Bit 107" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106  ,Set/Clear Enable Bit 106" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB105  ,Set/Clear Enable Bit 105" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB104  ,Set/Clear Enable Bit 104" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103  ,Set/Clear Enable Bit 103" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB102  ,Set/Clear Enable Bit 102" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB101  ,Set/Clear Enable Bit 101" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100  ,Set/Clear Enable Bit 100" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB99   ,Set/Clear Enable Bit 99" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB98   ,Set/Clear Enable Bit 98" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97   ,Set/Clear Enable Bit 97" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB96   ,Set/Clear Enable Bit 96" "Disabled,Enabled"
else
hgroup.long 0x010C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0110++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159  ,Set/Clear Enable Bit 159" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB158  ,Set/Clear Enable Bit 158" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB157  ,Set/Clear Enable Bit 157" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156  ,Set/Clear Enable Bit 156" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB155  ,Set/Clear Enable Bit 155" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB154  ,Set/Clear Enable Bit 154" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153  ,Set/Clear Enable Bit 153" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB152  ,Set/Clear Enable Bit 152" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB151  ,Set/Clear Enable Bit 151" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150  ,Set/Clear Enable Bit 150" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB149  ,Set/Clear Enable Bit 149" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB148  ,Set/Clear Enable Bit 148" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147  ,Set/Clear Enable Bit 147" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB146  ,Set/Clear Enable Bit 146" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB145  ,Set/Clear Enable Bit 145" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144  ,Set/Clear Enable Bit 144" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB143  ,Set/Clear Enable Bit 143" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB142  ,Set/Clear Enable Bit 142" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141  ,Set/Clear Enable Bit 141" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB140  ,Set/Clear Enable Bit 140" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB139  ,Set/Clear Enable Bit 139" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138  ,Set/Clear Enable Bit 138" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB137  ,Set/Clear Enable Bit 137" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB136  ,Set/Clear Enable Bit 136" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135  ,Set/Clear Enable Bit 135" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB134  ,Set/Clear Enable Bit 134" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB133  ,Set/Clear Enable Bit 133" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132  ,Set/Clear Enable Bit 132" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB131  ,Set/Clear Enable Bit 131" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB130  ,Set/Clear Enable Bit 130" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129  ,Set/Clear Enable Bit 129" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB128  ,Set/Clear Enable Bit 128" "Disabled,Enabled"
else
hgroup.long 0x0110++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0114++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191  ,Set/Clear Enable Bit 191" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB190  ,Set/Clear Enable Bit 190" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB189  ,Set/Clear Enable Bit 189" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188  ,Set/Clear Enable Bit 188" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB187  ,Set/Clear Enable Bit 187" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB186  ,Set/Clear Enable Bit 186" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185  ,Set/Clear Enable Bit 185" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB184  ,Set/Clear Enable Bit 184" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB183  ,Set/Clear Enable Bit 183" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182  ,Set/Clear Enable Bit 182" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB181  ,Set/Clear Enable Bit 181" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB180  ,Set/Clear Enable Bit 180" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179  ,Set/Clear Enable Bit 179" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB178  ,Set/Clear Enable Bit 178" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB177  ,Set/Clear Enable Bit 177" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176  ,Set/Clear Enable Bit 176" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB175  ,Set/Clear Enable Bit 175" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB174  ,Set/Clear Enable Bit 174" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173  ,Set/Clear Enable Bit 173" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB172  ,Set/Clear Enable Bit 172" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB171  ,Set/Clear Enable Bit 171" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170  ,Set/Clear Enable Bit 170" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB169  ,Set/Clear Enable Bit 169" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB168  ,Set/Clear Enable Bit 168" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167  ,Set/Clear Enable Bit 167" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB166  ,Set/Clear Enable Bit 166" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB165  ,Set/Clear Enable Bit 165" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164  ,Set/Clear Enable Bit 164" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB163  ,Set/Clear Enable Bit 163" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB162  ,Set/Clear Enable Bit 162" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161  ,Set/Clear Enable Bit 161" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB160  ,Set/Clear Enable Bit 160" "Disabled,Enabled"
else
hgroup.long 0x0114++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0118++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223  ,Set/Clear Enable Bit 223" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB222  ,Set/Clear Enable Bit 222" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB221  ,Set/Clear Enable Bit 221" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220  ,Set/Clear Enable Bit 220" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB219  ,Set/Clear Enable Bit 219" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB218  ,Set/Clear Enable Bit 218" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217  ,Set/Clear Enable Bit 217" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB216  ,Set/Clear Enable Bit 216" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB215  ,Set/Clear Enable Bit 215" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214  ,Set/Clear Enable Bit 214" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB213  ,Set/Clear Enable Bit 213" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB212  ,Set/Clear Enable Bit 212" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211  ,Set/Clear Enable Bit 211" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB210  ,Set/Clear Enable Bit 210" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB209  ,Set/Clear Enable Bit 209" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208  ,Set/Clear Enable Bit 208" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB207  ,Set/Clear Enable Bit 207" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB206  ,Set/Clear Enable Bit 206" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205  ,Set/Clear Enable Bit 205" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB204  ,Set/Clear Enable Bit 204" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB203  ,Set/Clear Enable Bit 203" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202  ,Set/Clear Enable Bit 202" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB201  ,Set/Clear Enable Bit 201" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB200  ,Set/Clear Enable Bit 200" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199  ,Set/Clear Enable Bit 199" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB198  ,Set/Clear Enable Bit 198" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB197  ,Set/Clear Enable Bit 197" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196  ,Set/Clear Enable Bit 196" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB195  ,Set/Clear Enable Bit 195" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB194  ,Set/Clear Enable Bit 194" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193  ,Set/Clear Enable Bit 193" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB192  ,Set/Clear Enable Bit 192" "Disabled,Enabled"
else
hgroup.long 0x0118++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x011C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255  ,Set/Clear Enable Bit 255" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB254  ,Set/Clear Enable Bit 254" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB253  ,Set/Clear Enable Bit 253" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252  ,Set/Clear Enable Bit 252" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB251  ,Set/Clear Enable Bit 251" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB250  ,Set/Clear Enable Bit 250" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249  ,Set/Clear Enable Bit 249" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB248  ,Set/Clear Enable Bit 248" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB247  ,Set/Clear Enable Bit 247" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246  ,Set/Clear Enable Bit 246" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB245  ,Set/Clear Enable Bit 245" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB244  ,Set/Clear Enable Bit 244" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243  ,Set/Clear Enable Bit 243" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB242  ,Set/Clear Enable Bit 242" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB241  ,Set/Clear Enable Bit 241" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240  ,Set/Clear Enable Bit 240" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB239  ,Set/Clear Enable Bit 239" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB238  ,Set/Clear Enable Bit 238" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237  ,Set/Clear Enable Bit 237" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB236  ,Set/Clear Enable Bit 236" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB235  ,Set/Clear Enable Bit 235" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234  ,Set/Clear Enable Bit 234" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB233  ,Set/Clear Enable Bit 233" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB232  ,Set/Clear Enable Bit 232" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231  ,Set/Clear Enable Bit 231" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB230  ,Set/Clear Enable Bit 230" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB229  ,Set/Clear Enable Bit 229" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228  ,Set/Clear Enable Bit 228" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB227  ,Set/Clear Enable Bit 227" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB226  ,Set/Clear Enable Bit 226" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225  ,Set/Clear Enable Bit 225" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB224  ,Set/Clear Enable Bit 224" "Disabled,Enabled"
else
hgroup.long 0x011C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0120++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287  ,Set/Clear Enable Bit 287" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB286  ,Set/Clear Enable Bit 286" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB285  ,Set/Clear Enable Bit 285" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284  ,Set/Clear Enable Bit 284" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB283  ,Set/Clear Enable Bit 283" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB282  ,Set/Clear Enable Bit 282" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281  ,Set/Clear Enable Bit 281" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB280  ,Set/Clear Enable Bit 280" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB279  ,Set/Clear Enable Bit 279" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278  ,Set/Clear Enable Bit 278" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB277  ,Set/Clear Enable Bit 277" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB276  ,Set/Clear Enable Bit 276" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275  ,Set/Clear Enable Bit 275" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB274  ,Set/Clear Enable Bit 274" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB273  ,Set/Clear Enable Bit 273" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272  ,Set/Clear Enable Bit 272" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB271  ,Set/Clear Enable Bit 271" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB270  ,Set/Clear Enable Bit 270" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269  ,Set/Clear Enable Bit 269" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB268  ,Set/Clear Enable Bit 268" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB267  ,Set/Clear Enable Bit 267" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266  ,Set/Clear Enable Bit 266" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB265  ,Set/Clear Enable Bit 265" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB264  ,Set/Clear Enable Bit 264" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263  ,Set/Clear Enable Bit 263" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB262  ,Set/Clear Enable Bit 262" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB261  ,Set/Clear Enable Bit 261" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260  ,Set/Clear Enable Bit 260" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB259  ,Set/Clear Enable Bit 259" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB258  ,Set/Clear Enable Bit 258" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257  ,Set/Clear Enable Bit 257" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB256  ,Set/Clear Enable Bit 256" "Disabled,Enabled"
else
hgroup.long 0x0120++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0124++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319  ,Set/Clear Enable Bit 319" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB318  ,Set/Clear Enable Bit 318" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB317  ,Set/Clear Enable Bit 317" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316  ,Set/Clear Enable Bit 316" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB315  ,Set/Clear Enable Bit 315" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB314  ,Set/Clear Enable Bit 314" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313  ,Set/Clear Enable Bit 313" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB312  ,Set/Clear Enable Bit 312" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB311  ,Set/Clear Enable Bit 311" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310  ,Set/Clear Enable Bit 310" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB309  ,Set/Clear Enable Bit 309" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB308  ,Set/Clear Enable Bit 308" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307  ,Set/Clear Enable Bit 307" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB306  ,Set/Clear Enable Bit 306" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB305  ,Set/Clear Enable Bit 305" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304  ,Set/Clear Enable Bit 304" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB303  ,Set/Clear Enable Bit 303" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB302  ,Set/Clear Enable Bit 302" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301  ,Set/Clear Enable Bit 301" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB300  ,Set/Clear Enable Bit 300" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB299  ,Set/Clear Enable Bit 299" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298  ,Set/Clear Enable Bit 298" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB297  ,Set/Clear Enable Bit 297" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB296  ,Set/Clear Enable Bit 296" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295  ,Set/Clear Enable Bit 295" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB294  ,Set/Clear Enable Bit 294" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB293  ,Set/Clear Enable Bit 293" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292  ,Set/Clear Enable Bit 292" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB291  ,Set/Clear Enable Bit 291" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB290  ,Set/Clear Enable Bit 290" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289  ,Set/Clear Enable Bit 289" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB288  ,Set/Clear Enable Bit 288" "Disabled,Enabled"
else
hgroup.long 0x0124++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0128++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351  ,Set/Clear Enable Bit 351" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB350  ,Set/Clear Enable Bit 350" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB349  ,Set/Clear Enable Bit 349" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348  ,Set/Clear Enable Bit 348" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB347  ,Set/Clear Enable Bit 347" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB346  ,Set/Clear Enable Bit 346" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345  ,Set/Clear Enable Bit 345" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB344  ,Set/Clear Enable Bit 344" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB343  ,Set/Clear Enable Bit 343" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342  ,Set/Clear Enable Bit 342" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB341  ,Set/Clear Enable Bit 341" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB340  ,Set/Clear Enable Bit 340" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339  ,Set/Clear Enable Bit 339" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB338  ,Set/Clear Enable Bit 338" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB337  ,Set/Clear Enable Bit 337" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336  ,Set/Clear Enable Bit 336" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB335  ,Set/Clear Enable Bit 335" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB334  ,Set/Clear Enable Bit 334" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333  ,Set/Clear Enable Bit 333" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB332  ,Set/Clear Enable Bit 332" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB331  ,Set/Clear Enable Bit 331" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330  ,Set/Clear Enable Bit 330" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB329  ,Set/Clear Enable Bit 329" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB328  ,Set/Clear Enable Bit 328" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327  ,Set/Clear Enable Bit 327" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB326  ,Set/Clear Enable Bit 326" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB325  ,Set/Clear Enable Bit 325" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324  ,Set/Clear Enable Bit 324" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB323  ,Set/Clear Enable Bit 323" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB322  ,Set/Clear Enable Bit 322" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321  ,Set/Clear Enable Bit 321" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB320  ,Set/Clear Enable Bit 320" "Disabled,Enabled"
else
hgroup.long 0x0128++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x012C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383  ,Set/Clear Enable Bit 383" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB382  ,Set/Clear Enable Bit 382" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB381  ,Set/Clear Enable Bit 381" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380  ,Set/Clear Enable Bit 380" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB379  ,Set/Clear Enable Bit 379" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB378  ,Set/Clear Enable Bit 378" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377  ,Set/Clear Enable Bit 377" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB376  ,Set/Clear Enable Bit 376" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB375  ,Set/Clear Enable Bit 375" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374  ,Set/Clear Enable Bit 374" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB373  ,Set/Clear Enable Bit 373" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB372  ,Set/Clear Enable Bit 372" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371  ,Set/Clear Enable Bit 371" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB370  ,Set/Clear Enable Bit 370" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB369  ,Set/Clear Enable Bit 369" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368  ,Set/Clear Enable Bit 368" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB367  ,Set/Clear Enable Bit 367" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB366  ,Set/Clear Enable Bit 366" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365  ,Set/Clear Enable Bit 365" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB364  ,Set/Clear Enable Bit 364" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB363  ,Set/Clear Enable Bit 363" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362  ,Set/Clear Enable Bit 362" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB361  ,Set/Clear Enable Bit 361" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB360  ,Set/Clear Enable Bit 360" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359  ,Set/Clear Enable Bit 359" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB358  ,Set/Clear Enable Bit 358" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB357  ,Set/Clear Enable Bit 357" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356  ,Set/Clear Enable Bit 356" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB355  ,Set/Clear Enable Bit 355" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB354  ,Set/Clear Enable Bit 354" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353  ,Set/Clear Enable Bit 353" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB352  ,Set/Clear Enable Bit 352" "Disabled,Enabled"
else
hgroup.long 0x012C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0130++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415  ,Set/Clear Enable Bit 415" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB414  ,Set/Clear Enable Bit 414" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB413  ,Set/Clear Enable Bit 413" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412  ,Set/Clear Enable Bit 412" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB411  ,Set/Clear Enable Bit 411" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB410  ,Set/Clear Enable Bit 410" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409  ,Set/Clear Enable Bit 409" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB408  ,Set/Clear Enable Bit 408" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB407  ,Set/Clear Enable Bit 407" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406  ,Set/Clear Enable Bit 406" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB405  ,Set/Clear Enable Bit 405" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB404  ,Set/Clear Enable Bit 404" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403  ,Set/Clear Enable Bit 403" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB402  ,Set/Clear Enable Bit 402" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB401  ,Set/Clear Enable Bit 401" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400  ,Set/Clear Enable Bit 400" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB399  ,Set/Clear Enable Bit 399" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB398  ,Set/Clear Enable Bit 398" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397  ,Set/Clear Enable Bit 397" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB396  ,Set/Clear Enable Bit 396" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB395  ,Set/Clear Enable Bit 395" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394  ,Set/Clear Enable Bit 394" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB393  ,Set/Clear Enable Bit 393" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB392  ,Set/Clear Enable Bit 392" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391  ,Set/Clear Enable Bit 391" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB390  ,Set/Clear Enable Bit 390" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB389  ,Set/Clear Enable Bit 389" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388  ,Set/Clear Enable Bit 388" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB387  ,Set/Clear Enable Bit 387" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB386  ,Set/Clear Enable Bit 386" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385  ,Set/Clear Enable Bit 385" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB384  ,Set/Clear Enable Bit 384" "Disabled,Enabled"
else
hgroup.long 0x0130++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0134++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447  ,Set/Clear Enable Bit 447" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB446  ,Set/Clear Enable Bit 446" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB445  ,Set/Clear Enable Bit 445" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444  ,Set/Clear Enable Bit 444" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB443  ,Set/Clear Enable Bit 443" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB442  ,Set/Clear Enable Bit 442" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441  ,Set/Clear Enable Bit 441" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB440  ,Set/Clear Enable Bit 440" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB439  ,Set/Clear Enable Bit 439" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438  ,Set/Clear Enable Bit 438" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB437  ,Set/Clear Enable Bit 437" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB436  ,Set/Clear Enable Bit 436" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435  ,Set/Clear Enable Bit 435" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB434  ,Set/Clear Enable Bit 434" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB433  ,Set/Clear Enable Bit 433" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432  ,Set/Clear Enable Bit 432" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB431  ,Set/Clear Enable Bit 431" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB430  ,Set/Clear Enable Bit 430" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429  ,Set/Clear Enable Bit 429" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB428  ,Set/Clear Enable Bit 428" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB427  ,Set/Clear Enable Bit 427" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426  ,Set/Clear Enable Bit 426" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB425  ,Set/Clear Enable Bit 425" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB424  ,Set/Clear Enable Bit 424" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423  ,Set/Clear Enable Bit 423" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB422  ,Set/Clear Enable Bit 422" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB421  ,Set/Clear Enable Bit 421" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420  ,Set/Clear Enable Bit 420" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB419  ,Set/Clear Enable Bit 419" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB418  ,Set/Clear Enable Bit 418" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417  ,Set/Clear Enable Bit 417" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB416  ,Set/Clear Enable Bit 416" "Disabled,Enabled"
else
hgroup.long 0x0134++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0138++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479  ,Set/Clear Enable Bit 479" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB478  ,Set/Clear Enable Bit 478" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB477  ,Set/Clear Enable Bit 477" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476  ,Set/Clear Enable Bit 476" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB475  ,Set/Clear Enable Bit 475" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB474  ,Set/Clear Enable Bit 474" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473  ,Set/Clear Enable Bit 473" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB472  ,Set/Clear Enable Bit 472" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB471  ,Set/Clear Enable Bit 471" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470  ,Set/Clear Enable Bit 470" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB469  ,Set/Clear Enable Bit 469" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB468  ,Set/Clear Enable Bit 468" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467  ,Set/Clear Enable Bit 467" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB466  ,Set/Clear Enable Bit 466" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB465  ,Set/Clear Enable Bit 465" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464  ,Set/Clear Enable Bit 464" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB463  ,Set/Clear Enable Bit 463" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB462  ,Set/Clear Enable Bit 462" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461  ,Set/Clear Enable Bit 461" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB460  ,Set/Clear Enable Bit 460" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB459  ,Set/Clear Enable Bit 459" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458  ,Set/Clear Enable Bit 458" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB457  ,Set/Clear Enable Bit 457" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB456  ,Set/Clear Enable Bit 456" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455  ,Set/Clear Enable Bit 455" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB454  ,Set/Clear Enable Bit 454" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB453  ,Set/Clear Enable Bit 453" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452  ,Set/Clear Enable Bit 452" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB451  ,Set/Clear Enable Bit 451" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB450  ,Set/Clear Enable Bit 450" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449  ,Set/Clear Enable Bit 449" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB448  ,Set/Clear Enable Bit 448" "Disabled,Enabled"
else
hgroup.long 0x0138++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x013C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511  ,Set/Clear Enable Bit 511" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB510  ,Set/Clear Enable Bit 510" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB509  ,Set/Clear Enable Bit 509" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508  ,Set/Clear Enable Bit 508" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB507  ,Set/Clear Enable Bit 507" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB506  ,Set/Clear Enable Bit 506" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505  ,Set/Clear Enable Bit 505" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB504  ,Set/Clear Enable Bit 504" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB503  ,Set/Clear Enable Bit 503" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502  ,Set/Clear Enable Bit 502" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB501  ,Set/Clear Enable Bit 501" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB500  ,Set/Clear Enable Bit 500" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499  ,Set/Clear Enable Bit 499" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB498  ,Set/Clear Enable Bit 498" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB497  ,Set/Clear Enable Bit 497" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496  ,Set/Clear Enable Bit 496" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB495  ,Set/Clear Enable Bit 495" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB494  ,Set/Clear Enable Bit 494" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493  ,Set/Clear Enable Bit 493" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB492  ,Set/Clear Enable Bit 492" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB491  ,Set/Clear Enable Bit 491" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490  ,Set/Clear Enable Bit 490" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB489  ,Set/Clear Enable Bit 489" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB488  ,Set/Clear Enable Bit 488" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487  ,Set/Clear Enable Bit 487" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB486  ,Set/Clear Enable Bit 486" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB485  ,Set/Clear Enable Bit 485" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484  ,Set/Clear Enable Bit 484" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB483  ,Set/Clear Enable Bit 483" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB482  ,Set/Clear Enable Bit 482" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481  ,Set/Clear Enable Bit 481" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB480  ,Set/Clear Enable Bit 480" "Disabled,Enabled"
else
hgroup.long 0x013C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0140++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543  ,Set/Clear Enable Bit 543" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB542  ,Set/Clear Enable Bit 542" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB541  ,Set/Clear Enable Bit 541" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540  ,Set/Clear Enable Bit 540" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB539  ,Set/Clear Enable Bit 539" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB538  ,Set/Clear Enable Bit 538" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537  ,Set/Clear Enable Bit 537" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB536  ,Set/Clear Enable Bit 536" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB535  ,Set/Clear Enable Bit 535" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534  ,Set/Clear Enable Bit 534" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB533  ,Set/Clear Enable Bit 533" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB532  ,Set/Clear Enable Bit 532" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531  ,Set/Clear Enable Bit 531" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB530  ,Set/Clear Enable Bit 530" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB529  ,Set/Clear Enable Bit 529" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528  ,Set/Clear Enable Bit 528" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB527  ,Set/Clear Enable Bit 527" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB526  ,Set/Clear Enable Bit 526" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525  ,Set/Clear Enable Bit 525" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB524  ,Set/Clear Enable Bit 524" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB523  ,Set/Clear Enable Bit 523" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522  ,Set/Clear Enable Bit 522" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB521  ,Set/Clear Enable Bit 521" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB520  ,Set/Clear Enable Bit 520" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519  ,Set/Clear Enable Bit 519" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB518  ,Set/Clear Enable Bit 518" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB517  ,Set/Clear Enable Bit 517" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516  ,Set/Clear Enable Bit 516" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB515  ,Set/Clear Enable Bit 515" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB514  ,Set/Clear Enable Bit 514" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513  ,Set/Clear Enable Bit 513" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB512  ,Set/Clear Enable Bit 512" "Disabled,Enabled"
else
hgroup.long 0x0140++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0144++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575  ,Set/Clear Enable Bit 575" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB574  ,Set/Clear Enable Bit 574" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB573  ,Set/Clear Enable Bit 573" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572  ,Set/Clear Enable Bit 572" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB571  ,Set/Clear Enable Bit 571" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB570  ,Set/Clear Enable Bit 570" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569  ,Set/Clear Enable Bit 569" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB568  ,Set/Clear Enable Bit 568" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB567  ,Set/Clear Enable Bit 567" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566  ,Set/Clear Enable Bit 566" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB565  ,Set/Clear Enable Bit 565" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB564  ,Set/Clear Enable Bit 564" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563  ,Set/Clear Enable Bit 563" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB562  ,Set/Clear Enable Bit 562" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB561  ,Set/Clear Enable Bit 561" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560  ,Set/Clear Enable Bit 560" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB559  ,Set/Clear Enable Bit 559" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB558  ,Set/Clear Enable Bit 558" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557  ,Set/Clear Enable Bit 557" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB556  ,Set/Clear Enable Bit 556" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB555  ,Set/Clear Enable Bit 555" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554  ,Set/Clear Enable Bit 554" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB553  ,Set/Clear Enable Bit 553" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB552  ,Set/Clear Enable Bit 552" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551  ,Set/Clear Enable Bit 551" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB550  ,Set/Clear Enable Bit 550" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB549  ,Set/Clear Enable Bit 549" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548  ,Set/Clear Enable Bit 548" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB547  ,Set/Clear Enable Bit 547" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB546  ,Set/Clear Enable Bit 546" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545  ,Set/Clear Enable Bit 545" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB544  ,Set/Clear Enable Bit 544" "Disabled,Enabled"
else
hgroup.long 0x0144++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0148++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607  ,Set/Clear Enable Bit 607" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB606  ,Set/Clear Enable Bit 606" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB605  ,Set/Clear Enable Bit 605" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604  ,Set/Clear Enable Bit 604" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB603  ,Set/Clear Enable Bit 603" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB602  ,Set/Clear Enable Bit 602" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601  ,Set/Clear Enable Bit 601" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB600  ,Set/Clear Enable Bit 600" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB599  ,Set/Clear Enable Bit 599" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598  ,Set/Clear Enable Bit 598" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB597  ,Set/Clear Enable Bit 597" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB596  ,Set/Clear Enable Bit 596" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595  ,Set/Clear Enable Bit 595" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB594  ,Set/Clear Enable Bit 594" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB593  ,Set/Clear Enable Bit 593" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592  ,Set/Clear Enable Bit 592" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB591  ,Set/Clear Enable Bit 591" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB590  ,Set/Clear Enable Bit 590" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589  ,Set/Clear Enable Bit 589" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB588  ,Set/Clear Enable Bit 588" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB587  ,Set/Clear Enable Bit 587" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586  ,Set/Clear Enable Bit 586" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB585  ,Set/Clear Enable Bit 585" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB584  ,Set/Clear Enable Bit 584" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583  ,Set/Clear Enable Bit 583" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB582  ,Set/Clear Enable Bit 582" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB581  ,Set/Clear Enable Bit 581" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580  ,Set/Clear Enable Bit 580" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB579  ,Set/Clear Enable Bit 579" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB578  ,Set/Clear Enable Bit 578" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577  ,Set/Clear Enable Bit 577" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB576  ,Set/Clear Enable Bit 576" "Disabled,Enabled"
else
hgroup.long 0x0148++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x014C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639  ,Set/Clear Enable Bit 639" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB638  ,Set/Clear Enable Bit 638" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB637  ,Set/Clear Enable Bit 637" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636  ,Set/Clear Enable Bit 636" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB635  ,Set/Clear Enable Bit 635" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB634  ,Set/Clear Enable Bit 634" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633  ,Set/Clear Enable Bit 633" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB632  ,Set/Clear Enable Bit 632" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB631  ,Set/Clear Enable Bit 631" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630  ,Set/Clear Enable Bit 630" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB629  ,Set/Clear Enable Bit 629" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB628  ,Set/Clear Enable Bit 628" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627  ,Set/Clear Enable Bit 627" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB626  ,Set/Clear Enable Bit 626" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB625  ,Set/Clear Enable Bit 625" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624  ,Set/Clear Enable Bit 624" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB623  ,Set/Clear Enable Bit 623" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB622  ,Set/Clear Enable Bit 622" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621  ,Set/Clear Enable Bit 621" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB620  ,Set/Clear Enable Bit 620" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB619  ,Set/Clear Enable Bit 619" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618  ,Set/Clear Enable Bit 618" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB617  ,Set/Clear Enable Bit 617" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB616  ,Set/Clear Enable Bit 616" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615  ,Set/Clear Enable Bit 615" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB614  ,Set/Clear Enable Bit 614" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB613  ,Set/Clear Enable Bit 613" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612  ,Set/Clear Enable Bit 612" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB611  ,Set/Clear Enable Bit 611" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB610  ,Set/Clear Enable Bit 610" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609  ,Set/Clear Enable Bit 609" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB608  ,Set/Clear Enable Bit 608" "Disabled,Enabled"
else
hgroup.long 0x014C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0150++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671  ,Set/Clear Enable Bit 671" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB670  ,Set/Clear Enable Bit 670" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB669  ,Set/Clear Enable Bit 669" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668  ,Set/Clear Enable Bit 668" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB667  ,Set/Clear Enable Bit 667" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB666  ,Set/Clear Enable Bit 666" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665  ,Set/Clear Enable Bit 665" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB664  ,Set/Clear Enable Bit 664" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB663  ,Set/Clear Enable Bit 663" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662  ,Set/Clear Enable Bit 662" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB661  ,Set/Clear Enable Bit 661" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB660  ,Set/Clear Enable Bit 660" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659  ,Set/Clear Enable Bit 659" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB658  ,Set/Clear Enable Bit 658" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB657  ,Set/Clear Enable Bit 657" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656  ,Set/Clear Enable Bit 656" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB655  ,Set/Clear Enable Bit 655" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB654  ,Set/Clear Enable Bit 654" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653  ,Set/Clear Enable Bit 653" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB652  ,Set/Clear Enable Bit 652" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB651  ,Set/Clear Enable Bit 651" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650  ,Set/Clear Enable Bit 650" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB649  ,Set/Clear Enable Bit 649" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB648  ,Set/Clear Enable Bit 648" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647  ,Set/Clear Enable Bit 647" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB646  ,Set/Clear Enable Bit 646" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB645  ,Set/Clear Enable Bit 645" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644  ,Set/Clear Enable Bit 644" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB643  ,Set/Clear Enable Bit 643" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB642  ,Set/Clear Enable Bit 642" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641  ,Set/Clear Enable Bit 641" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB640  ,Set/Clear Enable Bit 640" "Disabled,Enabled"
else
hgroup.long 0x0150++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0154++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703  ,Set/Clear Enable Bit 703" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB702  ,Set/Clear Enable Bit 702" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB701  ,Set/Clear Enable Bit 701" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700  ,Set/Clear Enable Bit 700" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB699  ,Set/Clear Enable Bit 699" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB698  ,Set/Clear Enable Bit 698" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697  ,Set/Clear Enable Bit 697" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB696  ,Set/Clear Enable Bit 696" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB695  ,Set/Clear Enable Bit 695" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694  ,Set/Clear Enable Bit 694" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB693  ,Set/Clear Enable Bit 693" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB692  ,Set/Clear Enable Bit 692" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691  ,Set/Clear Enable Bit 691" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB690  ,Set/Clear Enable Bit 690" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB689  ,Set/Clear Enable Bit 689" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688  ,Set/Clear Enable Bit 688" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB687  ,Set/Clear Enable Bit 687" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB686  ,Set/Clear Enable Bit 686" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685  ,Set/Clear Enable Bit 685" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB684  ,Set/Clear Enable Bit 684" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB683  ,Set/Clear Enable Bit 683" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682  ,Set/Clear Enable Bit 682" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB681  ,Set/Clear Enable Bit 681" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB680  ,Set/Clear Enable Bit 680" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679  ,Set/Clear Enable Bit 679" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB678  ,Set/Clear Enable Bit 678" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB677  ,Set/Clear Enable Bit 677" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676  ,Set/Clear Enable Bit 676" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB675  ,Set/Clear Enable Bit 675" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB674  ,Set/Clear Enable Bit 674" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673  ,Set/Clear Enable Bit 673" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB672  ,Set/Clear Enable Bit 672" "Disabled,Enabled"
else
hgroup.long 0x0154++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0158++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735  ,Set/Clear Enable Bit 735" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB734  ,Set/Clear Enable Bit 734" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB733  ,Set/Clear Enable Bit 733" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732  ,Set/Clear Enable Bit 732" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB731  ,Set/Clear Enable Bit 731" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB730  ,Set/Clear Enable Bit 730" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729  ,Set/Clear Enable Bit 729" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB728  ,Set/Clear Enable Bit 728" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB727  ,Set/Clear Enable Bit 727" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726  ,Set/Clear Enable Bit 726" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB725  ,Set/Clear Enable Bit 725" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB724  ,Set/Clear Enable Bit 724" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723  ,Set/Clear Enable Bit 723" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB722  ,Set/Clear Enable Bit 722" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB721  ,Set/Clear Enable Bit 721" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720  ,Set/Clear Enable Bit 720" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB719  ,Set/Clear Enable Bit 719" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB718  ,Set/Clear Enable Bit 718" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717  ,Set/Clear Enable Bit 717" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB716  ,Set/Clear Enable Bit 716" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB715  ,Set/Clear Enable Bit 715" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714  ,Set/Clear Enable Bit 714" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB713  ,Set/Clear Enable Bit 713" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB712  ,Set/Clear Enable Bit 712" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711  ,Set/Clear Enable Bit 711" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB710  ,Set/Clear Enable Bit 710" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB709  ,Set/Clear Enable Bit 709" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708  ,Set/Clear Enable Bit 708" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB707  ,Set/Clear Enable Bit 707" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB706  ,Set/Clear Enable Bit 706" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705  ,Set/Clear Enable Bit 705" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB704  ,Set/Clear Enable Bit 704" "Disabled,Enabled"
else
hgroup.long 0x0158++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x015C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767  ,Set/Clear Enable Bit 767" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB766  ,Set/Clear Enable Bit 766" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB765  ,Set/Clear Enable Bit 765" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764  ,Set/Clear Enable Bit 764" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB763  ,Set/Clear Enable Bit 763" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB762  ,Set/Clear Enable Bit 762" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761  ,Set/Clear Enable Bit 761" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB760  ,Set/Clear Enable Bit 760" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB759  ,Set/Clear Enable Bit 759" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758  ,Set/Clear Enable Bit 758" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB757  ,Set/Clear Enable Bit 757" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB756  ,Set/Clear Enable Bit 756" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755  ,Set/Clear Enable Bit 755" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB754  ,Set/Clear Enable Bit 754" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB753  ,Set/Clear Enable Bit 753" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752  ,Set/Clear Enable Bit 752" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB751  ,Set/Clear Enable Bit 751" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB750  ,Set/Clear Enable Bit 750" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749  ,Set/Clear Enable Bit 749" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB748  ,Set/Clear Enable Bit 748" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB747  ,Set/Clear Enable Bit 747" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746  ,Set/Clear Enable Bit 746" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB745  ,Set/Clear Enable Bit 745" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB744  ,Set/Clear Enable Bit 744" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743  ,Set/Clear Enable Bit 743" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB742  ,Set/Clear Enable Bit 742" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB741  ,Set/Clear Enable Bit 741" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740  ,Set/Clear Enable Bit 740" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB739  ,Set/Clear Enable Bit 739" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB738  ,Set/Clear Enable Bit 738" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737  ,Set/Clear Enable Bit 737" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB736  ,Set/Clear Enable Bit 736" "Disabled,Enabled"
else
hgroup.long 0x015C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0160++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799  ,Set/Clear Enable Bit 799" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB798  ,Set/Clear Enable Bit 798" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB797  ,Set/Clear Enable Bit 797" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796  ,Set/Clear Enable Bit 796" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB795  ,Set/Clear Enable Bit 795" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB794  ,Set/Clear Enable Bit 794" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793  ,Set/Clear Enable Bit 793" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB792  ,Set/Clear Enable Bit 792" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB791  ,Set/Clear Enable Bit 791" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790  ,Set/Clear Enable Bit 790" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB789  ,Set/Clear Enable Bit 789" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB788  ,Set/Clear Enable Bit 788" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787  ,Set/Clear Enable Bit 787" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB786  ,Set/Clear Enable Bit 786" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB785  ,Set/Clear Enable Bit 785" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784  ,Set/Clear Enable Bit 784" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB783  ,Set/Clear Enable Bit 783" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB782  ,Set/Clear Enable Bit 782" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781  ,Set/Clear Enable Bit 781" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB780  ,Set/Clear Enable Bit 780" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB779  ,Set/Clear Enable Bit 779" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778  ,Set/Clear Enable Bit 778" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB777  ,Set/Clear Enable Bit 777" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB776  ,Set/Clear Enable Bit 776" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775  ,Set/Clear Enable Bit 775" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB774  ,Set/Clear Enable Bit 774" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB773  ,Set/Clear Enable Bit 773" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772  ,Set/Clear Enable Bit 772" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB771  ,Set/Clear Enable Bit 771" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB770  ,Set/Clear Enable Bit 770" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769  ,Set/Clear Enable Bit 769" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB768  ,Set/Clear Enable Bit 768" "Disabled,Enabled"
else
hgroup.long 0x0160++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0164++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831  ,Set/Clear Enable Bit 831" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB830  ,Set/Clear Enable Bit 830" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB829  ,Set/Clear Enable Bit 829" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828  ,Set/Clear Enable Bit 828" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB827  ,Set/Clear Enable Bit 827" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB826  ,Set/Clear Enable Bit 826" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825  ,Set/Clear Enable Bit 825" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB824  ,Set/Clear Enable Bit 824" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB823  ,Set/Clear Enable Bit 823" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822  ,Set/Clear Enable Bit 822" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB821  ,Set/Clear Enable Bit 821" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB820  ,Set/Clear Enable Bit 820" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819  ,Set/Clear Enable Bit 819" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB818  ,Set/Clear Enable Bit 818" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB817  ,Set/Clear Enable Bit 817" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816  ,Set/Clear Enable Bit 816" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB815  ,Set/Clear Enable Bit 815" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB814  ,Set/Clear Enable Bit 814" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813  ,Set/Clear Enable Bit 813" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB812  ,Set/Clear Enable Bit 812" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB811  ,Set/Clear Enable Bit 811" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810  ,Set/Clear Enable Bit 810" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB809  ,Set/Clear Enable Bit 809" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB808  ,Set/Clear Enable Bit 808" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807  ,Set/Clear Enable Bit 807" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB806  ,Set/Clear Enable Bit 806" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB805  ,Set/Clear Enable Bit 805" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804  ,Set/Clear Enable Bit 804" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB803  ,Set/Clear Enable Bit 803" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB802  ,Set/Clear Enable Bit 802" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801  ,Set/Clear Enable Bit 801" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB800  ,Set/Clear Enable Bit 800" "Disabled,Enabled"
else
hgroup.long 0x0164++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0168++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863  ,Set/Clear Enable Bit 863" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB862  ,Set/Clear Enable Bit 862" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB861  ,Set/Clear Enable Bit 861" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860  ,Set/Clear Enable Bit 860" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB859  ,Set/Clear Enable Bit 859" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB858  ,Set/Clear Enable Bit 858" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857  ,Set/Clear Enable Bit 857" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB856  ,Set/Clear Enable Bit 856" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB855  ,Set/Clear Enable Bit 855" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854  ,Set/Clear Enable Bit 854" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB853  ,Set/Clear Enable Bit 853" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB852  ,Set/Clear Enable Bit 852" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851  ,Set/Clear Enable Bit 851" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB850  ,Set/Clear Enable Bit 850" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB849  ,Set/Clear Enable Bit 849" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848  ,Set/Clear Enable Bit 848" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB847  ,Set/Clear Enable Bit 847" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB846  ,Set/Clear Enable Bit 846" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845  ,Set/Clear Enable Bit 845" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB844  ,Set/Clear Enable Bit 844" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB843  ,Set/Clear Enable Bit 843" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842  ,Set/Clear Enable Bit 842" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB841  ,Set/Clear Enable Bit 841" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB840  ,Set/Clear Enable Bit 840" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839  ,Set/Clear Enable Bit 839" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB838  ,Set/Clear Enable Bit 838" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB837  ,Set/Clear Enable Bit 837" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836  ,Set/Clear Enable Bit 836" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB835  ,Set/Clear Enable Bit 835" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB834  ,Set/Clear Enable Bit 834" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833  ,Set/Clear Enable Bit 833" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB832  ,Set/Clear Enable Bit 832" "Disabled,Enabled"
else
hgroup.long 0x0168++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x016C++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895  ,Set/Clear Enable Bit 895" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB894  ,Set/Clear Enable Bit 894" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB893  ,Set/Clear Enable Bit 893" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892  ,Set/Clear Enable Bit 892" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB891  ,Set/Clear Enable Bit 891" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB890  ,Set/Clear Enable Bit 890" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889  ,Set/Clear Enable Bit 889" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB888  ,Set/Clear Enable Bit 888" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB887  ,Set/Clear Enable Bit 887" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886  ,Set/Clear Enable Bit 886" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB885  ,Set/Clear Enable Bit 885" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB884  ,Set/Clear Enable Bit 884" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883  ,Set/Clear Enable Bit 883" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB882  ,Set/Clear Enable Bit 882" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB881  ,Set/Clear Enable Bit 881" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880  ,Set/Clear Enable Bit 880" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB879  ,Set/Clear Enable Bit 879" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB878  ,Set/Clear Enable Bit 878" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877  ,Set/Clear Enable Bit 877" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB876  ,Set/Clear Enable Bit 876" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB875  ,Set/Clear Enable Bit 875" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874  ,Set/Clear Enable Bit 874" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB873  ,Set/Clear Enable Bit 873" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB872  ,Set/Clear Enable Bit 872" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871  ,Set/Clear Enable Bit 871" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB870  ,Set/Clear Enable Bit 870" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB869  ,Set/Clear Enable Bit 869" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868  ,Set/Clear Enable Bit 868" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB867  ,Set/Clear Enable Bit 867" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB866  ,Set/Clear Enable Bit 866" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865  ,Set/Clear Enable Bit 865" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB864  ,Set/Clear Enable Bit 864" "Disabled,Enabled"
else
hgroup.long 0x016C++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0170++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927  ,Set/Clear Enable Bit 927" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB926  ,Set/Clear Enable Bit 926" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB925  ,Set/Clear Enable Bit 925" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924  ,Set/Clear Enable Bit 924" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB923  ,Set/Clear Enable Bit 923" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB922  ,Set/Clear Enable Bit 922" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921  ,Set/Clear Enable Bit 921" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB920  ,Set/Clear Enable Bit 920" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB919  ,Set/Clear Enable Bit 919" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918  ,Set/Clear Enable Bit 918" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB917  ,Set/Clear Enable Bit 917" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB916  ,Set/Clear Enable Bit 916" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915  ,Set/Clear Enable Bit 915" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB914  ,Set/Clear Enable Bit 914" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB913  ,Set/Clear Enable Bit 913" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912  ,Set/Clear Enable Bit 912" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB911  ,Set/Clear Enable Bit 911" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB910  ,Set/Clear Enable Bit 910" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909  ,Set/Clear Enable Bit 909" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB908  ,Set/Clear Enable Bit 908" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB907  ,Set/Clear Enable Bit 907" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906  ,Set/Clear Enable Bit 906" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB905  ,Set/Clear Enable Bit 905" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB904  ,Set/Clear Enable Bit 904" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903  ,Set/Clear Enable Bit 903" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB902  ,Set/Clear Enable Bit 902" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB901  ,Set/Clear Enable Bit 901" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900  ,Set/Clear Enable Bit 900" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB899  ,Set/Clear Enable Bit 899" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB898  ,Set/Clear Enable Bit 898" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897  ,Set/Clear Enable Bit 897" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB896  ,Set/Clear Enable Bit 896" "Disabled,Enabled"
else
hgroup.long 0x0170++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0174++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959  ,Set/Clear Enable Bit 959" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB958  ,Set/Clear Enable Bit 958" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB957  ,Set/Clear Enable Bit 957" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956  ,Set/Clear Enable Bit 956" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB955  ,Set/Clear Enable Bit 955" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB954  ,Set/Clear Enable Bit 954" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953  ,Set/Clear Enable Bit 953" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB952  ,Set/Clear Enable Bit 952" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB951  ,Set/Clear Enable Bit 951" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950  ,Set/Clear Enable Bit 950" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB949  ,Set/Clear Enable Bit 949" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB948  ,Set/Clear Enable Bit 948" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947  ,Set/Clear Enable Bit 947" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB946  ,Set/Clear Enable Bit 946" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB945  ,Set/Clear Enable Bit 945" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944  ,Set/Clear Enable Bit 944" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB943  ,Set/Clear Enable Bit 943" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB942  ,Set/Clear Enable Bit 942" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941  ,Set/Clear Enable Bit 941" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB940  ,Set/Clear Enable Bit 940" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB939  ,Set/Clear Enable Bit 939" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938  ,Set/Clear Enable Bit 938" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB937  ,Set/Clear Enable Bit 937" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB936  ,Set/Clear Enable Bit 936" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935  ,Set/Clear Enable Bit 935" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB934  ,Set/Clear Enable Bit 934" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB933  ,Set/Clear Enable Bit 933" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932  ,Set/Clear Enable Bit 932" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB931  ,Set/Clear Enable Bit 931" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB930  ,Set/Clear Enable Bit 930" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929  ,Set/Clear Enable Bit 929" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB928  ,Set/Clear Enable Bit 928" "Disabled,Enabled"
else
hgroup.long 0x0174++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0178++0x03
line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991  ,Set/Clear Enable Bit 991" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRENB990  ,Set/Clear Enable Bit 990" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRENB989  ,Set/Clear Enable Bit 989" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988  ,Set/Clear Enable Bit 988" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRENB987  ,Set/Clear Enable Bit 987" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRENB986  ,Set/Clear Enable Bit 986" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985  ,Set/Clear Enable Bit 985" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRENB984  ,Set/Clear Enable Bit 984" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRENB983  ,Set/Clear Enable Bit 983" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982  ,Set/Clear Enable Bit 982" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRENB981  ,Set/Clear Enable Bit 981" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRENB980  ,Set/Clear Enable Bit 980" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979  ,Set/Clear Enable Bit 979" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRENB978  ,Set/Clear Enable Bit 978" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRENB977  ,Set/Clear Enable Bit 977" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976  ,Set/Clear Enable Bit 976" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRENB975  ,Set/Clear Enable Bit 975" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRENB974  ,Set/Clear Enable Bit 974" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973  ,Set/Clear Enable Bit 973" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRENB972  ,Set/Clear Enable Bit 972" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRENB971  ,Set/Clear Enable Bit 971" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970  ,Set/Clear Enable Bit 970" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRENB969  ,Set/Clear Enable Bit 969" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRENB968  ,Set/Clear Enable Bit 968" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967  ,Set/Clear Enable Bit 967" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRENB966  ,Set/Clear Enable Bit 966" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRENB965  ,Set/Clear Enable Bit 965" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964  ,Set/Clear Enable Bit 964" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRENB963  ,Set/Clear Enable Bit 963" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRENB962  ,Set/Clear Enable Bit 962" "Disabled,Enabled"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961  ,Set/Clear Enable Bit 961" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRENB960  ,Set/Clear Enable Bit 960" "Disabled,Enabled"
else
hgroup.long 0x0178++0x03
hide.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30"
endif
tree.end
width 22.
tree "Set/Clear Pending Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0200++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0200++0x03
line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0204++0x03
line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63   ,Set/Clear Pending Bit 63" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND62   ,Set/Clear Pending Bit 62" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND61   ,Set/Clear Pending Bit 61" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60   ,Set/Clear Pending Bit 60" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND59   ,Set/Clear Pending Bit 59" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND58   ,Set/Clear Pending Bit 58" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57   ,Set/Clear Pending Bit 57" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND56   ,Set/Clear Pending Bit 56" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND55   ,Set/Clear Pending Bit 55" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54   ,Set/Clear Pending Bit 54" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND53   ,Set/Clear Pending Bit 53" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND52   ,Set/Clear Pending Bit 52" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51   ,Set/Clear Pending Bit 51" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND50   ,Set/Clear Pending Bit 50" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND49   ,Set/Clear Pending Bit 49" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48   ,Set/Clear Pending Bit 48" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND47   ,Set/Clear Pending Bit 47" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND46   ,Set/Clear Pending Bit 46" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45   ,Set/Clear Pending Bit 45" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND44   ,Set/Clear Pending Bit 44" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND43   ,Set/Clear Pending Bit 43" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42   ,Set/Clear Pending Bit 42" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND41   ,Set/Clear Pending Bit 41" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND40   ,Set/Clear Pending Bit 40" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39   ,Set/Clear Pending Bit 39" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND38   ,Set/Clear Pending Bit 38" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND37   ,Set/Clear Pending Bit 37" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36   ,Set/Clear Pending Bit 36" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND35   ,Set/Clear Pending Bit 35" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND34   ,Set/Clear Pending Bit 34" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33   ,Set/Clear Pending Bit 33" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND32   ,Set/Clear Pending Bit 32" "Not pending,Pending"
else
hgroup.long 0x0204++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0208++0x03
line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95   ,Set/Clear Pending Bit 95" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND94   ,Set/Clear Pending Bit 94" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND93   ,Set/Clear Pending Bit 93" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92   ,Set/Clear Pending Bit 92" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND91   ,Set/Clear Pending Bit 91" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND90   ,Set/Clear Pending Bit 90" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89   ,Set/Clear Pending Bit 89" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND88   ,Set/Clear Pending Bit 88" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND87   ,Set/Clear Pending Bit 87" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86   ,Set/Clear Pending Bit 86" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND85   ,Set/Clear Pending Bit 85" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND84   ,Set/Clear Pending Bit 84" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83   ,Set/Clear Pending Bit 83" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND82   ,Set/Clear Pending Bit 82" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND81   ,Set/Clear Pending Bit 81" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80   ,Set/Clear Pending Bit 80" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND79   ,Set/Clear Pending Bit 79" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND78   ,Set/Clear Pending Bit 78" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77   ,Set/Clear Pending Bit 77" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND76   ,Set/Clear Pending Bit 76" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND75   ,Set/Clear Pending Bit 75" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74   ,Set/Clear Pending Bit 74" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND73   ,Set/Clear Pending Bit 73" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND72   ,Set/Clear Pending Bit 72" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71   ,Set/Clear Pending Bit 71" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND70   ,Set/Clear Pending Bit 70" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND69   ,Set/Clear Pending Bit 69" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68   ,Set/Clear Pending Bit 68" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND67   ,Set/Clear Pending Bit 67" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND66   ,Set/Clear Pending Bit 66" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65   ,Set/Clear Pending Bit 65" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND64   ,Set/Clear Pending Bit 64" "Not pending,Pending"
else
hgroup.long 0x0208++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x020C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127  ,Set/Clear Pending Bit 127" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND126  ,Set/Clear Pending Bit 126" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND125  ,Set/Clear Pending Bit 125" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124  ,Set/Clear Pending Bit 124" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND123  ,Set/Clear Pending Bit 123" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND122  ,Set/Clear Pending Bit 122" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121  ,Set/Clear Pending Bit 121" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND120  ,Set/Clear Pending Bit 120" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND119  ,Set/Clear Pending Bit 119" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118  ,Set/Clear Pending Bit 118" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND117  ,Set/Clear Pending Bit 117" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND116  ,Set/Clear Pending Bit 116" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115  ,Set/Clear Pending Bit 115" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND114  ,Set/Clear Pending Bit 114" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND113  ,Set/Clear Pending Bit 113" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112  ,Set/Clear Pending Bit 112" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND111  ,Set/Clear Pending Bit 111" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND110  ,Set/Clear Pending Bit 110" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109  ,Set/Clear Pending Bit 109" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND108  ,Set/Clear Pending Bit 108" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND107  ,Set/Clear Pending Bit 107" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106  ,Set/Clear Pending Bit 106" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND105  ,Set/Clear Pending Bit 105" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND104  ,Set/Clear Pending Bit 104" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103  ,Set/Clear Pending Bit 103" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND102  ,Set/Clear Pending Bit 102" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND101  ,Set/Clear Pending Bit 101" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100  ,Set/Clear Pending Bit 100" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND99   ,Set/Clear Pending Bit 99" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND98   ,Set/Clear Pending Bit 98" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97   ,Set/Clear Pending Bit 97" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND96   ,Set/Clear Pending Bit 96" "Not pending,Pending"
else
hgroup.long 0x020C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0210++0x03
line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159  ,Set/Clear Pending Bit 159" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND158  ,Set/Clear Pending Bit 158" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND157  ,Set/Clear Pending Bit 157" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156  ,Set/Clear Pending Bit 156" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND155  ,Set/Clear Pending Bit 155" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND154  ,Set/Clear Pending Bit 154" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153  ,Set/Clear Pending Bit 153" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND152  ,Set/Clear Pending Bit 152" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND151  ,Set/Clear Pending Bit 151" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150  ,Set/Clear Pending Bit 150" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND149  ,Set/Clear Pending Bit 149" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND148  ,Set/Clear Pending Bit 148" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147  ,Set/Clear Pending Bit 147" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND146  ,Set/Clear Pending Bit 146" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND145  ,Set/Clear Pending Bit 145" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144  ,Set/Clear Pending Bit 144" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND143  ,Set/Clear Pending Bit 143" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND142  ,Set/Clear Pending Bit 142" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141  ,Set/Clear Pending Bit 141" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND140  ,Set/Clear Pending Bit 140" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND139  ,Set/Clear Pending Bit 139" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138  ,Set/Clear Pending Bit 138" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND137  ,Set/Clear Pending Bit 137" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND136  ,Set/Clear Pending Bit 136" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135  ,Set/Clear Pending Bit 135" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND134  ,Set/Clear Pending Bit 134" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND133  ,Set/Clear Pending Bit 133" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132  ,Set/Clear Pending Bit 132" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND131  ,Set/Clear Pending Bit 131" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND130  ,Set/Clear Pending Bit 130" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129  ,Set/Clear Pending Bit 129" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND128  ,Set/Clear Pending Bit 128" "Not pending,Pending"
else
hgroup.long 0x0210++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0214++0x03
line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191  ,Set/Clear Pending Bit 191" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND190  ,Set/Clear Pending Bit 190" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND189  ,Set/Clear Pending Bit 189" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188  ,Set/Clear Pending Bit 188" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND187  ,Set/Clear Pending Bit 187" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND186  ,Set/Clear Pending Bit 186" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185  ,Set/Clear Pending Bit 185" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND184  ,Set/Clear Pending Bit 184" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND183  ,Set/Clear Pending Bit 183" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182  ,Set/Clear Pending Bit 182" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND181  ,Set/Clear Pending Bit 181" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND180  ,Set/Clear Pending Bit 180" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179  ,Set/Clear Pending Bit 179" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND178  ,Set/Clear Pending Bit 178" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND177  ,Set/Clear Pending Bit 177" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176  ,Set/Clear Pending Bit 176" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND175  ,Set/Clear Pending Bit 175" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND174  ,Set/Clear Pending Bit 174" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173  ,Set/Clear Pending Bit 173" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND172  ,Set/Clear Pending Bit 172" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND171  ,Set/Clear Pending Bit 171" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170  ,Set/Clear Pending Bit 170" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND169  ,Set/Clear Pending Bit 169" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND168  ,Set/Clear Pending Bit 168" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167  ,Set/Clear Pending Bit 167" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND166  ,Set/Clear Pending Bit 166" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND165  ,Set/Clear Pending Bit 165" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164  ,Set/Clear Pending Bit 164" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND163  ,Set/Clear Pending Bit 163" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND162  ,Set/Clear Pending Bit 162" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161  ,Set/Clear Pending Bit 161" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND160  ,Set/Clear Pending Bit 160" "Not pending,Pending"
else
hgroup.long 0x0214++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0218++0x03
line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223  ,Set/Clear Pending Bit 223" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND222  ,Set/Clear Pending Bit 222" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND221  ,Set/Clear Pending Bit 221" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220  ,Set/Clear Pending Bit 220" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND219  ,Set/Clear Pending Bit 219" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND218  ,Set/Clear Pending Bit 218" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217  ,Set/Clear Pending Bit 217" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND216  ,Set/Clear Pending Bit 216" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND215  ,Set/Clear Pending Bit 215" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214  ,Set/Clear Pending Bit 214" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND213  ,Set/Clear Pending Bit 213" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND212  ,Set/Clear Pending Bit 212" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211  ,Set/Clear Pending Bit 211" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND210  ,Set/Clear Pending Bit 210" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND209  ,Set/Clear Pending Bit 209" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208  ,Set/Clear Pending Bit 208" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND207  ,Set/Clear Pending Bit 207" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND206  ,Set/Clear Pending Bit 206" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205  ,Set/Clear Pending Bit 205" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND204  ,Set/Clear Pending Bit 204" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND203  ,Set/Clear Pending Bit 203" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202  ,Set/Clear Pending Bit 202" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND201  ,Set/Clear Pending Bit 201" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND200  ,Set/Clear Pending Bit 200" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199  ,Set/Clear Pending Bit 199" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND198  ,Set/Clear Pending Bit 198" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND197  ,Set/Clear Pending Bit 197" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196  ,Set/Clear Pending Bit 196" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND195  ,Set/Clear Pending Bit 195" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND194  ,Set/Clear Pending Bit 194" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193  ,Set/Clear Pending Bit 193" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND192  ,Set/Clear Pending Bit 192" "Not pending,Pending"
else
hgroup.long 0x0218++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x021C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255  ,Set/Clear Pending Bit 255" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND254  ,Set/Clear Pending Bit 254" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND253  ,Set/Clear Pending Bit 253" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252  ,Set/Clear Pending Bit 252" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND251  ,Set/Clear Pending Bit 251" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND250  ,Set/Clear Pending Bit 250" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249  ,Set/Clear Pending Bit 249" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND248  ,Set/Clear Pending Bit 248" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND247  ,Set/Clear Pending Bit 247" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246  ,Set/Clear Pending Bit 246" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND245  ,Set/Clear Pending Bit 245" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND244  ,Set/Clear Pending Bit 244" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243  ,Set/Clear Pending Bit 243" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND242  ,Set/Clear Pending Bit 242" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND241  ,Set/Clear Pending Bit 241" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240  ,Set/Clear Pending Bit 240" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND239  ,Set/Clear Pending Bit 239" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND238  ,Set/Clear Pending Bit 238" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237  ,Set/Clear Pending Bit 237" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND236  ,Set/Clear Pending Bit 236" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND235  ,Set/Clear Pending Bit 235" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234  ,Set/Clear Pending Bit 234" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND233  ,Set/Clear Pending Bit 233" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND232  ,Set/Clear Pending Bit 232" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231  ,Set/Clear Pending Bit 231" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND230  ,Set/Clear Pending Bit 230" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND229  ,Set/Clear Pending Bit 229" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228  ,Set/Clear Pending Bit 228" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND227  ,Set/Clear Pending Bit 227" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND226  ,Set/Clear Pending Bit 226" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225  ,Set/Clear Pending Bit 225" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND224  ,Set/Clear Pending Bit 224" "Not pending,Pending"
else
hgroup.long 0x021C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0220++0x03
line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287  ,Set/Clear Pending Bit 287" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND286  ,Set/Clear Pending Bit 286" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND285  ,Set/Clear Pending Bit 285" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284  ,Set/Clear Pending Bit 284" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND283  ,Set/Clear Pending Bit 283" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND282  ,Set/Clear Pending Bit 282" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281  ,Set/Clear Pending Bit 281" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND280  ,Set/Clear Pending Bit 280" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND279  ,Set/Clear Pending Bit 279" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278  ,Set/Clear Pending Bit 278" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND277  ,Set/Clear Pending Bit 277" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND276  ,Set/Clear Pending Bit 276" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275  ,Set/Clear Pending Bit 275" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND274  ,Set/Clear Pending Bit 274" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND273  ,Set/Clear Pending Bit 273" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272  ,Set/Clear Pending Bit 272" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND271  ,Set/Clear Pending Bit 271" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND270  ,Set/Clear Pending Bit 270" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269  ,Set/Clear Pending Bit 269" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND268  ,Set/Clear Pending Bit 268" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND267  ,Set/Clear Pending Bit 267" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266  ,Set/Clear Pending Bit 266" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND265  ,Set/Clear Pending Bit 265" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND264  ,Set/Clear Pending Bit 264" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263  ,Set/Clear Pending Bit 263" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND262  ,Set/Clear Pending Bit 262" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND261  ,Set/Clear Pending Bit 261" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260  ,Set/Clear Pending Bit 260" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND259  ,Set/Clear Pending Bit 259" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND258  ,Set/Clear Pending Bit 258" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257  ,Set/Clear Pending Bit 257" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND256  ,Set/Clear Pending Bit 256" "Not pending,Pending"
else
hgroup.long 0x0220++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0224++0x03
line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319  ,Set/Clear Pending Bit 319" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND318  ,Set/Clear Pending Bit 318" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND317  ,Set/Clear Pending Bit 317" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316  ,Set/Clear Pending Bit 316" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND315  ,Set/Clear Pending Bit 315" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND314  ,Set/Clear Pending Bit 314" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313  ,Set/Clear Pending Bit 313" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND312  ,Set/Clear Pending Bit 312" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND311  ,Set/Clear Pending Bit 311" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310  ,Set/Clear Pending Bit 310" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND309  ,Set/Clear Pending Bit 309" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND308  ,Set/Clear Pending Bit 308" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307  ,Set/Clear Pending Bit 307" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND306  ,Set/Clear Pending Bit 306" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND305  ,Set/Clear Pending Bit 305" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304  ,Set/Clear Pending Bit 304" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND303  ,Set/Clear Pending Bit 303" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND302  ,Set/Clear Pending Bit 302" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301  ,Set/Clear Pending Bit 301" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND300  ,Set/Clear Pending Bit 300" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND299  ,Set/Clear Pending Bit 299" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298  ,Set/Clear Pending Bit 298" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND297  ,Set/Clear Pending Bit 297" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND296  ,Set/Clear Pending Bit 296" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295  ,Set/Clear Pending Bit 295" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND294  ,Set/Clear Pending Bit 294" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND293  ,Set/Clear Pending Bit 293" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292  ,Set/Clear Pending Bit 292" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND291  ,Set/Clear Pending Bit 291" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND290  ,Set/Clear Pending Bit 290" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289  ,Set/Clear Pending Bit 289" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND288  ,Set/Clear Pending Bit 288" "Not pending,Pending"
else
hgroup.long 0x0224++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0228++0x03
line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351  ,Set/Clear Pending Bit 351" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND350  ,Set/Clear Pending Bit 350" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND349  ,Set/Clear Pending Bit 349" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348  ,Set/Clear Pending Bit 348" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND347  ,Set/Clear Pending Bit 347" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND346  ,Set/Clear Pending Bit 346" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345  ,Set/Clear Pending Bit 345" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND344  ,Set/Clear Pending Bit 344" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND343  ,Set/Clear Pending Bit 343" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342  ,Set/Clear Pending Bit 342" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND341  ,Set/Clear Pending Bit 341" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND340  ,Set/Clear Pending Bit 340" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339  ,Set/Clear Pending Bit 339" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND338  ,Set/Clear Pending Bit 338" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND337  ,Set/Clear Pending Bit 337" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336  ,Set/Clear Pending Bit 336" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND335  ,Set/Clear Pending Bit 335" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND334  ,Set/Clear Pending Bit 334" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333  ,Set/Clear Pending Bit 333" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND332  ,Set/Clear Pending Bit 332" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND331  ,Set/Clear Pending Bit 331" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330  ,Set/Clear Pending Bit 330" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND329  ,Set/Clear Pending Bit 329" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND328  ,Set/Clear Pending Bit 328" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327  ,Set/Clear Pending Bit 327" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND326  ,Set/Clear Pending Bit 326" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND325  ,Set/Clear Pending Bit 325" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324  ,Set/Clear Pending Bit 324" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND323  ,Set/Clear Pending Bit 323" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND322  ,Set/Clear Pending Bit 322" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321  ,Set/Clear Pending Bit 321" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND320  ,Set/Clear Pending Bit 320" "Not pending,Pending"
else
hgroup.long 0x0228++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x022C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383  ,Set/Clear Pending Bit 383" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND382  ,Set/Clear Pending Bit 382" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND381  ,Set/Clear Pending Bit 381" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380  ,Set/Clear Pending Bit 380" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND379  ,Set/Clear Pending Bit 379" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND378  ,Set/Clear Pending Bit 378" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377  ,Set/Clear Pending Bit 377" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND376  ,Set/Clear Pending Bit 376" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND375  ,Set/Clear Pending Bit 375" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374  ,Set/Clear Pending Bit 374" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND373  ,Set/Clear Pending Bit 373" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND372  ,Set/Clear Pending Bit 372" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371  ,Set/Clear Pending Bit 371" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND370  ,Set/Clear Pending Bit 370" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND369  ,Set/Clear Pending Bit 369" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368  ,Set/Clear Pending Bit 368" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND367  ,Set/Clear Pending Bit 367" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND366  ,Set/Clear Pending Bit 366" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365  ,Set/Clear Pending Bit 365" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND364  ,Set/Clear Pending Bit 364" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND363  ,Set/Clear Pending Bit 363" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362  ,Set/Clear Pending Bit 362" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND361  ,Set/Clear Pending Bit 361" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND360  ,Set/Clear Pending Bit 360" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359  ,Set/Clear Pending Bit 359" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND358  ,Set/Clear Pending Bit 358" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND357  ,Set/Clear Pending Bit 357" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356  ,Set/Clear Pending Bit 356" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND355  ,Set/Clear Pending Bit 355" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND354  ,Set/Clear Pending Bit 354" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353  ,Set/Clear Pending Bit 353" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND352  ,Set/Clear Pending Bit 352" "Not pending,Pending"
else
hgroup.long 0x022C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0230++0x03
line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415  ,Set/Clear Pending Bit 415" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND414  ,Set/Clear Pending Bit 414" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND413  ,Set/Clear Pending Bit 413" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412  ,Set/Clear Pending Bit 412" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND411  ,Set/Clear Pending Bit 411" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND410  ,Set/Clear Pending Bit 410" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409  ,Set/Clear Pending Bit 409" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND408  ,Set/Clear Pending Bit 408" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND407  ,Set/Clear Pending Bit 407" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406  ,Set/Clear Pending Bit 406" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND405  ,Set/Clear Pending Bit 405" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND404  ,Set/Clear Pending Bit 404" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403  ,Set/Clear Pending Bit 403" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND402  ,Set/Clear Pending Bit 402" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND401  ,Set/Clear Pending Bit 401" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400  ,Set/Clear Pending Bit 400" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND399  ,Set/Clear Pending Bit 399" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND398  ,Set/Clear Pending Bit 398" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397  ,Set/Clear Pending Bit 397" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND396  ,Set/Clear Pending Bit 396" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND395  ,Set/Clear Pending Bit 395" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394  ,Set/Clear Pending Bit 394" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND393  ,Set/Clear Pending Bit 393" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND392  ,Set/Clear Pending Bit 392" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391  ,Set/Clear Pending Bit 391" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND390  ,Set/Clear Pending Bit 390" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND389  ,Set/Clear Pending Bit 389" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388  ,Set/Clear Pending Bit 388" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND387  ,Set/Clear Pending Bit 387" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND386  ,Set/Clear Pending Bit 386" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385  ,Set/Clear Pending Bit 385" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND384  ,Set/Clear Pending Bit 384" "Not pending,Pending"
else
hgroup.long 0x0230++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0234++0x03
line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447  ,Set/Clear Pending Bit 447" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND446  ,Set/Clear Pending Bit 446" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND445  ,Set/Clear Pending Bit 445" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444  ,Set/Clear Pending Bit 444" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND443  ,Set/Clear Pending Bit 443" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND442  ,Set/Clear Pending Bit 442" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441  ,Set/Clear Pending Bit 441" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND440  ,Set/Clear Pending Bit 440" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND439  ,Set/Clear Pending Bit 439" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438  ,Set/Clear Pending Bit 438" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND437  ,Set/Clear Pending Bit 437" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND436  ,Set/Clear Pending Bit 436" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435  ,Set/Clear Pending Bit 435" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND434  ,Set/Clear Pending Bit 434" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND433  ,Set/Clear Pending Bit 433" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432  ,Set/Clear Pending Bit 432" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND431  ,Set/Clear Pending Bit 431" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND430  ,Set/Clear Pending Bit 430" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429  ,Set/Clear Pending Bit 429" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND428  ,Set/Clear Pending Bit 428" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND427  ,Set/Clear Pending Bit 427" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426  ,Set/Clear Pending Bit 426" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND425  ,Set/Clear Pending Bit 425" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND424  ,Set/Clear Pending Bit 424" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423  ,Set/Clear Pending Bit 423" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND422  ,Set/Clear Pending Bit 422" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND421  ,Set/Clear Pending Bit 421" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420  ,Set/Clear Pending Bit 420" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND419  ,Set/Clear Pending Bit 419" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND418  ,Set/Clear Pending Bit 418" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417  ,Set/Clear Pending Bit 417" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND416  ,Set/Clear Pending Bit 416" "Not pending,Pending"
else
hgroup.long 0x0234++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0238++0x03
line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479  ,Set/Clear Pending Bit 479" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND478  ,Set/Clear Pending Bit 478" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND477  ,Set/Clear Pending Bit 477" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476  ,Set/Clear Pending Bit 476" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND475  ,Set/Clear Pending Bit 475" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND474  ,Set/Clear Pending Bit 474" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473  ,Set/Clear Pending Bit 473" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND472  ,Set/Clear Pending Bit 472" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND471  ,Set/Clear Pending Bit 471" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470  ,Set/Clear Pending Bit 470" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND469  ,Set/Clear Pending Bit 469" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND468  ,Set/Clear Pending Bit 468" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467  ,Set/Clear Pending Bit 467" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND466  ,Set/Clear Pending Bit 466" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND465  ,Set/Clear Pending Bit 465" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464  ,Set/Clear Pending Bit 464" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND463  ,Set/Clear Pending Bit 463" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND462  ,Set/Clear Pending Bit 462" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461  ,Set/Clear Pending Bit 461" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND460  ,Set/Clear Pending Bit 460" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND459  ,Set/Clear Pending Bit 459" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458  ,Set/Clear Pending Bit 458" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND457  ,Set/Clear Pending Bit 457" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND456  ,Set/Clear Pending Bit 456" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455  ,Set/Clear Pending Bit 455" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND454  ,Set/Clear Pending Bit 454" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND453  ,Set/Clear Pending Bit 453" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452  ,Set/Clear Pending Bit 452" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND451  ,Set/Clear Pending Bit 451" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND450  ,Set/Clear Pending Bit 450" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449  ,Set/Clear Pending Bit 449" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND448  ,Set/Clear Pending Bit 448" "Not pending,Pending"
else
hgroup.long 0x0238++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x023C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511  ,Set/Clear Pending Bit 511" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND510  ,Set/Clear Pending Bit 510" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND509  ,Set/Clear Pending Bit 509" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508  ,Set/Clear Pending Bit 508" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND507  ,Set/Clear Pending Bit 507" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND506  ,Set/Clear Pending Bit 506" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505  ,Set/Clear Pending Bit 505" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND504  ,Set/Clear Pending Bit 504" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND503  ,Set/Clear Pending Bit 503" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502  ,Set/Clear Pending Bit 502" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND501  ,Set/Clear Pending Bit 501" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND500  ,Set/Clear Pending Bit 500" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499  ,Set/Clear Pending Bit 499" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND498  ,Set/Clear Pending Bit 498" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND497  ,Set/Clear Pending Bit 497" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496  ,Set/Clear Pending Bit 496" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND495  ,Set/Clear Pending Bit 495" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND494  ,Set/Clear Pending Bit 494" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493  ,Set/Clear Pending Bit 493" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND492  ,Set/Clear Pending Bit 492" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND491  ,Set/Clear Pending Bit 491" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490  ,Set/Clear Pending Bit 490" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND489  ,Set/Clear Pending Bit 489" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND488  ,Set/Clear Pending Bit 488" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487  ,Set/Clear Pending Bit 487" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND486  ,Set/Clear Pending Bit 486" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND485  ,Set/Clear Pending Bit 485" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484  ,Set/Clear Pending Bit 484" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND483  ,Set/Clear Pending Bit 483" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND482  ,Set/Clear Pending Bit 482" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481  ,Set/Clear Pending Bit 481" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND480  ,Set/Clear Pending Bit 480" "Not pending,Pending"
else
hgroup.long 0x023C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0240++0x03
line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543  ,Set/Clear Pending Bit 543" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND542  ,Set/Clear Pending Bit 542" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND541  ,Set/Clear Pending Bit 541" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540  ,Set/Clear Pending Bit 540" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND539  ,Set/Clear Pending Bit 539" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND538  ,Set/Clear Pending Bit 538" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537  ,Set/Clear Pending Bit 537" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND536  ,Set/Clear Pending Bit 536" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND535  ,Set/Clear Pending Bit 535" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534  ,Set/Clear Pending Bit 534" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND533  ,Set/Clear Pending Bit 533" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND532  ,Set/Clear Pending Bit 532" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531  ,Set/Clear Pending Bit 531" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND530  ,Set/Clear Pending Bit 530" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND529  ,Set/Clear Pending Bit 529" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528  ,Set/Clear Pending Bit 528" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND527  ,Set/Clear Pending Bit 527" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND526  ,Set/Clear Pending Bit 526" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525  ,Set/Clear Pending Bit 525" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND524  ,Set/Clear Pending Bit 524" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND523  ,Set/Clear Pending Bit 523" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522  ,Set/Clear Pending Bit 522" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND521  ,Set/Clear Pending Bit 521" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND520  ,Set/Clear Pending Bit 520" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519  ,Set/Clear Pending Bit 519" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND518  ,Set/Clear Pending Bit 518" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND517  ,Set/Clear Pending Bit 517" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516  ,Set/Clear Pending Bit 516" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND515  ,Set/Clear Pending Bit 515" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND514  ,Set/Clear Pending Bit 514" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513  ,Set/Clear Pending Bit 513" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND512  ,Set/Clear Pending Bit 512" "Not pending,Pending"
else
hgroup.long 0x0240++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0244++0x03
line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575  ,Set/Clear Pending Bit 575" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND574  ,Set/Clear Pending Bit 574" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND573  ,Set/Clear Pending Bit 573" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572  ,Set/Clear Pending Bit 572" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND571  ,Set/Clear Pending Bit 571" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND570  ,Set/Clear Pending Bit 570" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569  ,Set/Clear Pending Bit 569" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND568  ,Set/Clear Pending Bit 568" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND567  ,Set/Clear Pending Bit 567" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566  ,Set/Clear Pending Bit 566" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND565  ,Set/Clear Pending Bit 565" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND564  ,Set/Clear Pending Bit 564" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563  ,Set/Clear Pending Bit 563" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND562  ,Set/Clear Pending Bit 562" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND561  ,Set/Clear Pending Bit 561" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560  ,Set/Clear Pending Bit 560" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND559  ,Set/Clear Pending Bit 559" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND558  ,Set/Clear Pending Bit 558" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557  ,Set/Clear Pending Bit 557" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND556  ,Set/Clear Pending Bit 556" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND555  ,Set/Clear Pending Bit 555" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554  ,Set/Clear Pending Bit 554" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND553  ,Set/Clear Pending Bit 553" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND552  ,Set/Clear Pending Bit 552" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551  ,Set/Clear Pending Bit 551" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND550  ,Set/Clear Pending Bit 550" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND549  ,Set/Clear Pending Bit 549" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548  ,Set/Clear Pending Bit 548" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND547  ,Set/Clear Pending Bit 547" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND546  ,Set/Clear Pending Bit 546" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545  ,Set/Clear Pending Bit 545" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND544  ,Set/Clear Pending Bit 544" "Not pending,Pending"
else
hgroup.long 0x0244++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0248++0x03
line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607  ,Set/Clear Pending Bit 607" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND606  ,Set/Clear Pending Bit 606" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND605  ,Set/Clear Pending Bit 605" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604  ,Set/Clear Pending Bit 604" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND603  ,Set/Clear Pending Bit 603" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND602  ,Set/Clear Pending Bit 602" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601  ,Set/Clear Pending Bit 601" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND600  ,Set/Clear Pending Bit 600" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND599  ,Set/Clear Pending Bit 599" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598  ,Set/Clear Pending Bit 598" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND597  ,Set/Clear Pending Bit 597" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND596  ,Set/Clear Pending Bit 596" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595  ,Set/Clear Pending Bit 595" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND594  ,Set/Clear Pending Bit 594" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND593  ,Set/Clear Pending Bit 593" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592  ,Set/Clear Pending Bit 592" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND591  ,Set/Clear Pending Bit 591" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND590  ,Set/Clear Pending Bit 590" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589  ,Set/Clear Pending Bit 589" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND588  ,Set/Clear Pending Bit 588" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND587  ,Set/Clear Pending Bit 587" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586  ,Set/Clear Pending Bit 586" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND585  ,Set/Clear Pending Bit 585" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND584  ,Set/Clear Pending Bit 584" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583  ,Set/Clear Pending Bit 583" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND582  ,Set/Clear Pending Bit 582" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND581  ,Set/Clear Pending Bit 581" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580  ,Set/Clear Pending Bit 580" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND579  ,Set/Clear Pending Bit 579" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND578  ,Set/Clear Pending Bit 578" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577  ,Set/Clear Pending Bit 577" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND576  ,Set/Clear Pending Bit 576" "Not pending,Pending"
else
hgroup.long 0x0248++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x024C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639  ,Set/Clear Pending Bit 639" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND638  ,Set/Clear Pending Bit 638" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND637  ,Set/Clear Pending Bit 637" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636  ,Set/Clear Pending Bit 636" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND635  ,Set/Clear Pending Bit 635" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND634  ,Set/Clear Pending Bit 634" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633  ,Set/Clear Pending Bit 633" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND632  ,Set/Clear Pending Bit 632" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND631  ,Set/Clear Pending Bit 631" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630  ,Set/Clear Pending Bit 630" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND629  ,Set/Clear Pending Bit 629" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND628  ,Set/Clear Pending Bit 628" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627  ,Set/Clear Pending Bit 627" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND626  ,Set/Clear Pending Bit 626" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND625  ,Set/Clear Pending Bit 625" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624  ,Set/Clear Pending Bit 624" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND623  ,Set/Clear Pending Bit 623" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND622  ,Set/Clear Pending Bit 622" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621  ,Set/Clear Pending Bit 621" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND620  ,Set/Clear Pending Bit 620" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND619  ,Set/Clear Pending Bit 619" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618  ,Set/Clear Pending Bit 618" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND617  ,Set/Clear Pending Bit 617" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND616  ,Set/Clear Pending Bit 616" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615  ,Set/Clear Pending Bit 615" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND614  ,Set/Clear Pending Bit 614" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND613  ,Set/Clear Pending Bit 613" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612  ,Set/Clear Pending Bit 612" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND611  ,Set/Clear Pending Bit 611" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND610  ,Set/Clear Pending Bit 610" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609  ,Set/Clear Pending Bit 609" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND608  ,Set/Clear Pending Bit 608" "Not pending,Pending"
else
hgroup.long 0x024C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0250++0x03
line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671  ,Set/Clear Pending Bit 671" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND670  ,Set/Clear Pending Bit 670" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND669  ,Set/Clear Pending Bit 669" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668  ,Set/Clear Pending Bit 668" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND667  ,Set/Clear Pending Bit 667" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND666  ,Set/Clear Pending Bit 666" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665  ,Set/Clear Pending Bit 665" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND664  ,Set/Clear Pending Bit 664" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND663  ,Set/Clear Pending Bit 663" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662  ,Set/Clear Pending Bit 662" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND661  ,Set/Clear Pending Bit 661" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND660  ,Set/Clear Pending Bit 660" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659  ,Set/Clear Pending Bit 659" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND658  ,Set/Clear Pending Bit 658" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND657  ,Set/Clear Pending Bit 657" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656  ,Set/Clear Pending Bit 656" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND655  ,Set/Clear Pending Bit 655" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND654  ,Set/Clear Pending Bit 654" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653  ,Set/Clear Pending Bit 653" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND652  ,Set/Clear Pending Bit 652" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND651  ,Set/Clear Pending Bit 651" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650  ,Set/Clear Pending Bit 650" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND649  ,Set/Clear Pending Bit 649" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND648  ,Set/Clear Pending Bit 648" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647  ,Set/Clear Pending Bit 647" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND646  ,Set/Clear Pending Bit 646" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND645  ,Set/Clear Pending Bit 645" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644  ,Set/Clear Pending Bit 644" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND643  ,Set/Clear Pending Bit 643" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND642  ,Set/Clear Pending Bit 642" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641  ,Set/Clear Pending Bit 641" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND640  ,Set/Clear Pending Bit 640" "Not pending,Pending"
else
hgroup.long 0x0250++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0254++0x03
line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703  ,Set/Clear Pending Bit 703" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND702  ,Set/Clear Pending Bit 702" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND701  ,Set/Clear Pending Bit 701" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700  ,Set/Clear Pending Bit 700" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND699  ,Set/Clear Pending Bit 699" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND698  ,Set/Clear Pending Bit 698" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697  ,Set/Clear Pending Bit 697" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND696  ,Set/Clear Pending Bit 696" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND695  ,Set/Clear Pending Bit 695" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694  ,Set/Clear Pending Bit 694" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND693  ,Set/Clear Pending Bit 693" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND692  ,Set/Clear Pending Bit 692" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691  ,Set/Clear Pending Bit 691" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND690  ,Set/Clear Pending Bit 690" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND689  ,Set/Clear Pending Bit 689" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688  ,Set/Clear Pending Bit 688" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND687  ,Set/Clear Pending Bit 687" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND686  ,Set/Clear Pending Bit 686" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685  ,Set/Clear Pending Bit 685" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND684  ,Set/Clear Pending Bit 684" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND683  ,Set/Clear Pending Bit 683" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682  ,Set/Clear Pending Bit 682" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND681  ,Set/Clear Pending Bit 681" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND680  ,Set/Clear Pending Bit 680" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679  ,Set/Clear Pending Bit 679" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND678  ,Set/Clear Pending Bit 678" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND677  ,Set/Clear Pending Bit 677" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676  ,Set/Clear Pending Bit 676" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND675  ,Set/Clear Pending Bit 675" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND674  ,Set/Clear Pending Bit 674" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673  ,Set/Clear Pending Bit 673" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND672  ,Set/Clear Pending Bit 672" "Not pending,Pending"
else
hgroup.long 0x0254++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0258++0x03
line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735  ,Set/Clear Pending Bit 735" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND734  ,Set/Clear Pending Bit 734" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND733  ,Set/Clear Pending Bit 733" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732  ,Set/Clear Pending Bit 732" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND731  ,Set/Clear Pending Bit 731" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND730  ,Set/Clear Pending Bit 730" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729  ,Set/Clear Pending Bit 729" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND728  ,Set/Clear Pending Bit 728" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND727  ,Set/Clear Pending Bit 727" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726  ,Set/Clear Pending Bit 726" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND725  ,Set/Clear Pending Bit 725" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND724  ,Set/Clear Pending Bit 724" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723  ,Set/Clear Pending Bit 723" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND722  ,Set/Clear Pending Bit 722" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND721  ,Set/Clear Pending Bit 721" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720  ,Set/Clear Pending Bit 720" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND719  ,Set/Clear Pending Bit 719" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND718  ,Set/Clear Pending Bit 718" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717  ,Set/Clear Pending Bit 717" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND716  ,Set/Clear Pending Bit 716" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND715  ,Set/Clear Pending Bit 715" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714  ,Set/Clear Pending Bit 714" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND713  ,Set/Clear Pending Bit 713" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND712  ,Set/Clear Pending Bit 712" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711  ,Set/Clear Pending Bit 711" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND710  ,Set/Clear Pending Bit 710" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND709  ,Set/Clear Pending Bit 709" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708  ,Set/Clear Pending Bit 708" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND707  ,Set/Clear Pending Bit 707" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND706  ,Set/Clear Pending Bit 706" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705  ,Set/Clear Pending Bit 705" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND704  ,Set/Clear Pending Bit 704" "Not pending,Pending"
else
hgroup.long 0x0258++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x025C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767  ,Set/Clear Pending Bit 767" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND766  ,Set/Clear Pending Bit 766" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND765  ,Set/Clear Pending Bit 765" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764  ,Set/Clear Pending Bit 764" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND763  ,Set/Clear Pending Bit 763" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND762  ,Set/Clear Pending Bit 762" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761  ,Set/Clear Pending Bit 761" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND760  ,Set/Clear Pending Bit 760" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND759  ,Set/Clear Pending Bit 759" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758  ,Set/Clear Pending Bit 758" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND757  ,Set/Clear Pending Bit 757" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND756  ,Set/Clear Pending Bit 756" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755  ,Set/Clear Pending Bit 755" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND754  ,Set/Clear Pending Bit 754" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND753  ,Set/Clear Pending Bit 753" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752  ,Set/Clear Pending Bit 752" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND751  ,Set/Clear Pending Bit 751" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND750  ,Set/Clear Pending Bit 750" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749  ,Set/Clear Pending Bit 749" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND748  ,Set/Clear Pending Bit 748" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND747  ,Set/Clear Pending Bit 747" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746  ,Set/Clear Pending Bit 746" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND745  ,Set/Clear Pending Bit 745" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND744  ,Set/Clear Pending Bit 744" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743  ,Set/Clear Pending Bit 743" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND742  ,Set/Clear Pending Bit 742" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND741  ,Set/Clear Pending Bit 741" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740  ,Set/Clear Pending Bit 740" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND739  ,Set/Clear Pending Bit 739" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND738  ,Set/Clear Pending Bit 738" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737  ,Set/Clear Pending Bit 737" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND736  ,Set/Clear Pending Bit 736" "Not pending,Pending"
else
hgroup.long 0x025C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0260++0x03
line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799  ,Set/Clear Pending Bit 799" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND798  ,Set/Clear Pending Bit 798" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND797  ,Set/Clear Pending Bit 797" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796  ,Set/Clear Pending Bit 796" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND795  ,Set/Clear Pending Bit 795" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND794  ,Set/Clear Pending Bit 794" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793  ,Set/Clear Pending Bit 793" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND792  ,Set/Clear Pending Bit 792" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND791  ,Set/Clear Pending Bit 791" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790  ,Set/Clear Pending Bit 790" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND789  ,Set/Clear Pending Bit 789" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND788  ,Set/Clear Pending Bit 788" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787  ,Set/Clear Pending Bit 787" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND786  ,Set/Clear Pending Bit 786" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND785  ,Set/Clear Pending Bit 785" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784  ,Set/Clear Pending Bit 784" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND783  ,Set/Clear Pending Bit 783" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND782  ,Set/Clear Pending Bit 782" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781  ,Set/Clear Pending Bit 781" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND780  ,Set/Clear Pending Bit 780" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND779  ,Set/Clear Pending Bit 779" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778  ,Set/Clear Pending Bit 778" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND777  ,Set/Clear Pending Bit 777" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND776  ,Set/Clear Pending Bit 776" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775  ,Set/Clear Pending Bit 775" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND774  ,Set/Clear Pending Bit 774" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND773  ,Set/Clear Pending Bit 773" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772  ,Set/Clear Pending Bit 772" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND771  ,Set/Clear Pending Bit 771" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND770  ,Set/Clear Pending Bit 770" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769  ,Set/Clear Pending Bit 769" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND768  ,Set/Clear Pending Bit 768" "Not pending,Pending"
else
hgroup.long 0x0260++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0264++0x03
line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831  ,Set/Clear Pending Bit 831" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND830  ,Set/Clear Pending Bit 830" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND829  ,Set/Clear Pending Bit 829" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828  ,Set/Clear Pending Bit 828" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND827  ,Set/Clear Pending Bit 827" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND826  ,Set/Clear Pending Bit 826" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825  ,Set/Clear Pending Bit 825" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND824  ,Set/Clear Pending Bit 824" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND823  ,Set/Clear Pending Bit 823" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822  ,Set/Clear Pending Bit 822" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND821  ,Set/Clear Pending Bit 821" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND820  ,Set/Clear Pending Bit 820" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819  ,Set/Clear Pending Bit 819" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND818  ,Set/Clear Pending Bit 818" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND817  ,Set/Clear Pending Bit 817" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816  ,Set/Clear Pending Bit 816" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND815  ,Set/Clear Pending Bit 815" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND814  ,Set/Clear Pending Bit 814" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813  ,Set/Clear Pending Bit 813" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND812  ,Set/Clear Pending Bit 812" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND811  ,Set/Clear Pending Bit 811" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810  ,Set/Clear Pending Bit 810" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND809  ,Set/Clear Pending Bit 809" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND808  ,Set/Clear Pending Bit 808" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807  ,Set/Clear Pending Bit 807" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND806  ,Set/Clear Pending Bit 806" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND805  ,Set/Clear Pending Bit 805" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804  ,Set/Clear Pending Bit 804" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND803  ,Set/Clear Pending Bit 803" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND802  ,Set/Clear Pending Bit 802" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801  ,Set/Clear Pending Bit 801" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND800  ,Set/Clear Pending Bit 800" "Not pending,Pending"
else
hgroup.long 0x0264++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0268++0x03
line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863  ,Set/Clear Pending Bit 863" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND862  ,Set/Clear Pending Bit 862" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND861  ,Set/Clear Pending Bit 861" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860  ,Set/Clear Pending Bit 860" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND859  ,Set/Clear Pending Bit 859" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND858  ,Set/Clear Pending Bit 858" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857  ,Set/Clear Pending Bit 857" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND856  ,Set/Clear Pending Bit 856" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND855  ,Set/Clear Pending Bit 855" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854  ,Set/Clear Pending Bit 854" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND853  ,Set/Clear Pending Bit 853" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND852  ,Set/Clear Pending Bit 852" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851  ,Set/Clear Pending Bit 851" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND850  ,Set/Clear Pending Bit 850" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND849  ,Set/Clear Pending Bit 849" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848  ,Set/Clear Pending Bit 848" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND847  ,Set/Clear Pending Bit 847" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND846  ,Set/Clear Pending Bit 846" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845  ,Set/Clear Pending Bit 845" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND844  ,Set/Clear Pending Bit 844" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND843  ,Set/Clear Pending Bit 843" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842  ,Set/Clear Pending Bit 842" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND841  ,Set/Clear Pending Bit 841" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND840  ,Set/Clear Pending Bit 840" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839  ,Set/Clear Pending Bit 839" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND838  ,Set/Clear Pending Bit 838" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND837  ,Set/Clear Pending Bit 837" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836  ,Set/Clear Pending Bit 836" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND835  ,Set/Clear Pending Bit 835" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND834  ,Set/Clear Pending Bit 834" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833  ,Set/Clear Pending Bit 833" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND832  ,Set/Clear Pending Bit 832" "Not pending,Pending"
else
hgroup.long 0x0268++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x026C++0x03
line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895  ,Set/Clear Pending Bit 895" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND894  ,Set/Clear Pending Bit 894" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND893  ,Set/Clear Pending Bit 893" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892  ,Set/Clear Pending Bit 892" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND891  ,Set/Clear Pending Bit 891" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND890  ,Set/Clear Pending Bit 890" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889  ,Set/Clear Pending Bit 889" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND888  ,Set/Clear Pending Bit 888" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND887  ,Set/Clear Pending Bit 887" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886  ,Set/Clear Pending Bit 886" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND885  ,Set/Clear Pending Bit 885" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND884  ,Set/Clear Pending Bit 884" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883  ,Set/Clear Pending Bit 883" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND882  ,Set/Clear Pending Bit 882" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND881  ,Set/Clear Pending Bit 881" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880  ,Set/Clear Pending Bit 880" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND879  ,Set/Clear Pending Bit 879" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND878  ,Set/Clear Pending Bit 878" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877  ,Set/Clear Pending Bit 877" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND876  ,Set/Clear Pending Bit 876" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND875  ,Set/Clear Pending Bit 875" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874  ,Set/Clear Pending Bit 874" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND873  ,Set/Clear Pending Bit 873" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND872  ,Set/Clear Pending Bit 872" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871  ,Set/Clear Pending Bit 871" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND870  ,Set/Clear Pending Bit 870" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND869  ,Set/Clear Pending Bit 869" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868  ,Set/Clear Pending Bit 868" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND867  ,Set/Clear Pending Bit 867" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND866  ,Set/Clear Pending Bit 866" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865  ,Set/Clear Pending Bit 865" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND864  ,Set/Clear Pending Bit 864" "Not pending,Pending"
else
hgroup.long 0x026C++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0270++0x03
line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927  ,Set/Clear Pending Bit 927" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND926  ,Set/Clear Pending Bit 926" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND925  ,Set/Clear Pending Bit 925" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924  ,Set/Clear Pending Bit 924" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND923  ,Set/Clear Pending Bit 923" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND922  ,Set/Clear Pending Bit 922" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921  ,Set/Clear Pending Bit 921" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND920  ,Set/Clear Pending Bit 920" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND919  ,Set/Clear Pending Bit 919" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918  ,Set/Clear Pending Bit 918" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND917  ,Set/Clear Pending Bit 917" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND916  ,Set/Clear Pending Bit 916" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915  ,Set/Clear Pending Bit 915" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND914  ,Set/Clear Pending Bit 914" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND913  ,Set/Clear Pending Bit 913" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912  ,Set/Clear Pending Bit 912" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND911  ,Set/Clear Pending Bit 911" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND910  ,Set/Clear Pending Bit 910" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909  ,Set/Clear Pending Bit 909" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND908  ,Set/Clear Pending Bit 908" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND907  ,Set/Clear Pending Bit 907" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906  ,Set/Clear Pending Bit 906" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND905  ,Set/Clear Pending Bit 905" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND904  ,Set/Clear Pending Bit 904" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903  ,Set/Clear Pending Bit 903" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND902  ,Set/Clear Pending Bit 902" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND901  ,Set/Clear Pending Bit 901" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900  ,Set/Clear Pending Bit 900" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND899  ,Set/Clear Pending Bit 899" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND898  ,Set/Clear Pending Bit 898" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897  ,Set/Clear Pending Bit 897" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND896  ,Set/Clear Pending Bit 896" "Not pending,Pending"
else
hgroup.long 0x0270++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0274++0x03
line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959  ,Set/Clear Pending Bit 959" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND958  ,Set/Clear Pending Bit 958" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND957  ,Set/Clear Pending Bit 957" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956  ,Set/Clear Pending Bit 956" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND955  ,Set/Clear Pending Bit 955" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND954  ,Set/Clear Pending Bit 954" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953  ,Set/Clear Pending Bit 953" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND952  ,Set/Clear Pending Bit 952" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND951  ,Set/Clear Pending Bit 951" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950  ,Set/Clear Pending Bit 950" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND949  ,Set/Clear Pending Bit 949" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND948  ,Set/Clear Pending Bit 948" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947  ,Set/Clear Pending Bit 947" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND946  ,Set/Clear Pending Bit 946" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND945  ,Set/Clear Pending Bit 945" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944  ,Set/Clear Pending Bit 944" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND943  ,Set/Clear Pending Bit 943" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND942  ,Set/Clear Pending Bit 942" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941  ,Set/Clear Pending Bit 941" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND940  ,Set/Clear Pending Bit 940" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND939  ,Set/Clear Pending Bit 939" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938  ,Set/Clear Pending Bit 938" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND937  ,Set/Clear Pending Bit 937" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND936  ,Set/Clear Pending Bit 936" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935  ,Set/Clear Pending Bit 935" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND934  ,Set/Clear Pending Bit 934" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND933  ,Set/Clear Pending Bit 933" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932  ,Set/Clear Pending Bit 932" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND931  ,Set/Clear Pending Bit 931" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND930  ,Set/Clear Pending Bit 930" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929  ,Set/Clear Pending Bit 929" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND928  ,Set/Clear Pending Bit 928" "Not pending,Pending"
else
hgroup.long 0x0274++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0278++0x03
line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991  ,Set/Clear Pending Bit 991" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRPEND990  ,Set/Clear Pending Bit 990" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRPEND989  ,Set/Clear Pending Bit 989" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988  ,Set/Clear Pending Bit 988" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRPEND987  ,Set/Clear Pending Bit 987" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRPEND986  ,Set/Clear Pending Bit 986" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985  ,Set/Clear Pending Bit 985" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRPEND984  ,Set/Clear Pending Bit 984" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRPEND983  ,Set/Clear Pending Bit 983" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982  ,Set/Clear Pending Bit 982" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRPEND981  ,Set/Clear Pending Bit 981" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRPEND980  ,Set/Clear Pending Bit 980" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979  ,Set/Clear Pending Bit 979" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRPEND978  ,Set/Clear Pending Bit 978" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRPEND977  ,Set/Clear Pending Bit 977" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976  ,Set/Clear Pending Bit 976" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRPEND975  ,Set/Clear Pending Bit 975" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRPEND974  ,Set/Clear Pending Bit 974" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973  ,Set/Clear Pending Bit 973" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRPEND972  ,Set/Clear Pending Bit 972" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRPEND971  ,Set/Clear Pending Bit 971" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970  ,Set/Clear Pending Bit 970" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRPEND969  ,Set/Clear Pending Bit 969" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRPEND968  ,Set/Clear Pending Bit 968" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967  ,Set/Clear Pending Bit 967" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRPEND966  ,Set/Clear Pending Bit 966" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRPEND965  ,Set/Clear Pending Bit 965" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964  ,Set/Clear Pending Bit 964" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRPEND963  ,Set/Clear Pending Bit 963" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRPEND962  ,Set/Clear Pending Bit 962" "Not pending,Pending"
textline "                               "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961  ,Set/Clear Pending Bit 961" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRPEND960  ,Set/Clear Pending Bit 960" "Not pending,Pending"
else
hgroup.long 0x0278++0x03
hide.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30"
endif
tree.end
width 24.
tree "Set/Clear Active Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0300++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
newline
newline
newline
newline
newline
newline
newline
newline
newline
newline
else
group.long 0x0300++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31  ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE30  ,Set/Clear Active Bit 30" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE29  ,Set/Clear Active Bit 29" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28  ,Set/Clear Active Bit 28" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE27  ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE26  ,Set/Clear Active Bit 26" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25  ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE24  ,Set/Clear Active Bit 24" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE23  ,Set/Clear Active Bit 23" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22  ,Set/Clear Active Bit 22" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE21  ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE20  ,Set/Clear Active Bit 20" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19  ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE18  ,Set/Clear Active Bit 18" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE17  ,Set/Clear Active Bit 17" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16  ,Set/Clear Active Bit 16" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE15  ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE14  ,Set/Clear Active Bit 14" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13  ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE12  ,Set/Clear Active Bit 12" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE11  ,Set/Clear Active Bit 11" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10  ,Set/Clear Active Bit 10" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE9   ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE8   ,Set/Clear Active Bit 8" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7   ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE6   ,Set/Clear Active Bit 6" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE5   ,Set/Clear Active Bit 5" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4   ,Set/Clear Active Bit 4" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE3   ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE2   ,Set/Clear Active Bit 2" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1   ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE0   ,Set/Clear Active Bit 0" "Not active,Active"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x0304++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63  ,Set/Clear Active Bit 63" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE62  ,Set/Clear Active Bit 62" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE61  ,Set/Clear Active Bit 61" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60  ,Set/Clear Active Bit 60" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE59  ,Set/Clear Active Bit 59" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE58  ,Set/Clear Active Bit 58" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57  ,Set/Clear Active Bit 57" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE56  ,Set/Clear Active Bit 56" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE55  ,Set/Clear Active Bit 55" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54  ,Set/Clear Active Bit 54" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE53  ,Set/Clear Active Bit 53" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE52  ,Set/Clear Active Bit 52" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51  ,Set/Clear Active Bit 51" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE50  ,Set/Clear Active Bit 50" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE49  ,Set/Clear Active Bit 49" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48  ,Set/Clear Active Bit 48" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE47  ,Set/Clear Active Bit 47" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE46  ,Set/Clear Active Bit 46" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45  ,Set/Clear Active Bit 45" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE44  ,Set/Clear Active Bit 44" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE43  ,Set/Clear Active Bit 43" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42  ,Set/Clear Active Bit 42" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE41  ,Set/Clear Active Bit 41" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE40  ,Set/Clear Active Bit 40" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39  ,Set/Clear Active Bit 39" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE38  ,Set/Clear Active Bit 38" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE37  ,Set/Clear Active Bit 37" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36  ,Set/Clear Active Bit 36" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE35  ,Set/Clear Active Bit 35" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE34  ,Set/Clear Active Bit 34" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33  ,Set/Clear Active Bit 33" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE32  ,Set/Clear Active Bit 32" "Not active,Active"
else
hgroup.long 0x0304++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x0308++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95  ,Set/Clear Active Bit 95" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE94  ,Set/Clear Active Bit 94" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE93  ,Set/Clear Active Bit 93" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92  ,Set/Clear Active Bit 92" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE91  ,Set/Clear Active Bit 91" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE90  ,Set/Clear Active Bit 90" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89  ,Set/Clear Active Bit 89" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE88  ,Set/Clear Active Bit 88" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE87  ,Set/Clear Active Bit 87" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86  ,Set/Clear Active Bit 86" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE85  ,Set/Clear Active Bit 85" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE84  ,Set/Clear Active Bit 84" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83  ,Set/Clear Active Bit 83" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE82  ,Set/Clear Active Bit 82" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE81  ,Set/Clear Active Bit 81" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80  ,Set/Clear Active Bit 80" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE79  ,Set/Clear Active Bit 79" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE78  ,Set/Clear Active Bit 78" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77  ,Set/Clear Active Bit 77" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE76  ,Set/Clear Active Bit 76" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE75  ,Set/Clear Active Bit 75" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74  ,Set/Clear Active Bit 74" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE73  ,Set/Clear Active Bit 73" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE72  ,Set/Clear Active Bit 72" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71  ,Set/Clear Active Bit 71" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE70  ,Set/Clear Active Bit 70" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE69  ,Set/Clear Active Bit 69" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68  ,Set/Clear Active Bit 68" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE67  ,Set/Clear Active Bit 67" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE66  ,Set/Clear Active Bit 66" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65  ,Set/Clear Active Bit 65" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE64  ,Set/Clear Active Bit 64" "Not active,Active"
else
hgroup.long 0x0308++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x030C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE99  ,Set/Clear Active Bit 99" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE98  ,Set/Clear Active Bit 98" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97  ,Set/Clear Active Bit 97" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE96  ,Set/Clear Active Bit 96" "Not active,Active"
else
hgroup.long 0x030C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x0310++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active"
else
hgroup.long 0x0310++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x0314++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active"
else
hgroup.long 0x0314++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x0318++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active"
else
hgroup.long 0x0318++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x031C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active"
else
hgroup.long 0x031C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x0320++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active"
else
hgroup.long 0x0320++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x0324++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active"
else
hgroup.long 0x0324++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x0328++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active"
else
hgroup.long 0x0328++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x032C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active"
else
hgroup.long 0x032C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x0330++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active"
else
hgroup.long 0x0330++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x0334++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active"
else
hgroup.long 0x0334++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x0338++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active"
else
hgroup.long 0x0338++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x033C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active"
else
hgroup.long 0x033C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x0340++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE543 ,Set/Clear Active Bit 543" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE542 ,Set/Clear Active Bit 542" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE541 ,Set/Clear Active Bit 541" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE540 ,Set/Clear Active Bit 540" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE539 ,Set/Clear Active Bit 539" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE538 ,Set/Clear Active Bit 538" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE537 ,Set/Clear Active Bit 537" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE536 ,Set/Clear Active Bit 536" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE535 ,Set/Clear Active Bit 535" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE534 ,Set/Clear Active Bit 534" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE533 ,Set/Clear Active Bit 533" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE532 ,Set/Clear Active Bit 532" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE531 ,Set/Clear Active Bit 531" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE530 ,Set/Clear Active Bit 530" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE529 ,Set/Clear Active Bit 529" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE528 ,Set/Clear Active Bit 528" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE527 ,Set/Clear Active Bit 527" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE526 ,Set/Clear Active Bit 526" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE525 ,Set/Clear Active Bit 525" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE524 ,Set/Clear Active Bit 524" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE523 ,Set/Clear Active Bit 523" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE522 ,Set/Clear Active Bit 522" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE521 ,Set/Clear Active Bit 521" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE520 ,Set/Clear Active Bit 520" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE519 ,Set/Clear Active Bit 519" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE518 ,Set/Clear Active Bit 518" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE517 ,Set/Clear Active Bit 517" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE516 ,Set/Clear Active Bit 516" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE515 ,Set/Clear Active Bit 515" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE514 ,Set/Clear Active Bit 514" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE513 ,Set/Clear Active Bit 513" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE512 ,Set/Clear Active Bit 512" "Not active,Active"
else
hgroup.long 0x0340++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x0344++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE575 ,Set/Clear Active Bit 575" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE574 ,Set/Clear Active Bit 574" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE573 ,Set/Clear Active Bit 573" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE572 ,Set/Clear Active Bit 572" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE571 ,Set/Clear Active Bit 571" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE570 ,Set/Clear Active Bit 570" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE569 ,Set/Clear Active Bit 569" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE568 ,Set/Clear Active Bit 568" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE567 ,Set/Clear Active Bit 567" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE566 ,Set/Clear Active Bit 566" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE565 ,Set/Clear Active Bit 565" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE564 ,Set/Clear Active Bit 564" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE563 ,Set/Clear Active Bit 563" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE562 ,Set/Clear Active Bit 562" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE561 ,Set/Clear Active Bit 561" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE560 ,Set/Clear Active Bit 560" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE559 ,Set/Clear Active Bit 559" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE558 ,Set/Clear Active Bit 558" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE557 ,Set/Clear Active Bit 557" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE556 ,Set/Clear Active Bit 556" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE555 ,Set/Clear Active Bit 555" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE554 ,Set/Clear Active Bit 554" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE553 ,Set/Clear Active Bit 553" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE552 ,Set/Clear Active Bit 552" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE551 ,Set/Clear Active Bit 551" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE550 ,Set/Clear Active Bit 550" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE549 ,Set/Clear Active Bit 549" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE548 ,Set/Clear Active Bit 548" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE547 ,Set/Clear Active Bit 547" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE546 ,Set/Clear Active Bit 546" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE545 ,Set/Clear Active Bit 545" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE544 ,Set/Clear Active Bit 544" "Not active,Active"
else
hgroup.long 0x0344++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x0348++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE607 ,Set/Clear Active Bit 607" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE606 ,Set/Clear Active Bit 606" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE605 ,Set/Clear Active Bit 605" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE604 ,Set/Clear Active Bit 604" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE603 ,Set/Clear Active Bit 603" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE602 ,Set/Clear Active Bit 602" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE601 ,Set/Clear Active Bit 601" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE600 ,Set/Clear Active Bit 600" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE599 ,Set/Clear Active Bit 599" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE598 ,Set/Clear Active Bit 598" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE597 ,Set/Clear Active Bit 597" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE596 ,Set/Clear Active Bit 596" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE595 ,Set/Clear Active Bit 595" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE594 ,Set/Clear Active Bit 594" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE593 ,Set/Clear Active Bit 593" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE592 ,Set/Clear Active Bit 592" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE591 ,Set/Clear Active Bit 591" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE590 ,Set/Clear Active Bit 590" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE589 ,Set/Clear Active Bit 589" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE588 ,Set/Clear Active Bit 588" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE587 ,Set/Clear Active Bit 587" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE586 ,Set/Clear Active Bit 586" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE585 ,Set/Clear Active Bit 585" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE584 ,Set/Clear Active Bit 584" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE583 ,Set/Clear Active Bit 583" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE582 ,Set/Clear Active Bit 582" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE581 ,Set/Clear Active Bit 581" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE580 ,Set/Clear Active Bit 580" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE579 ,Set/Clear Active Bit 579" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE578 ,Set/Clear Active Bit 578" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE577 ,Set/Clear Active Bit 577" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE576 ,Set/Clear Active Bit 576" "Not active,Active"
else
hgroup.long 0x0348++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x034C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE639 ,Set/Clear Active Bit 639" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE638 ,Set/Clear Active Bit 638" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE637 ,Set/Clear Active Bit 637" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE636 ,Set/Clear Active Bit 636" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE635 ,Set/Clear Active Bit 635" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE634 ,Set/Clear Active Bit 634" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE633 ,Set/Clear Active Bit 633" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE632 ,Set/Clear Active Bit 632" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE631 ,Set/Clear Active Bit 631" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE630 ,Set/Clear Active Bit 630" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE629 ,Set/Clear Active Bit 629" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE628 ,Set/Clear Active Bit 628" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE627 ,Set/Clear Active Bit 627" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE626 ,Set/Clear Active Bit 626" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE625 ,Set/Clear Active Bit 625" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE624 ,Set/Clear Active Bit 624" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE623 ,Set/Clear Active Bit 623" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE622 ,Set/Clear Active Bit 622" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE621 ,Set/Clear Active Bit 621" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE620 ,Set/Clear Active Bit 620" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE619 ,Set/Clear Active Bit 619" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE618 ,Set/Clear Active Bit 618" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE617 ,Set/Clear Active Bit 617" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE616 ,Set/Clear Active Bit 616" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE615 ,Set/Clear Active Bit 615" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE614 ,Set/Clear Active Bit 614" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE613 ,Set/Clear Active Bit 613" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE612 ,Set/Clear Active Bit 612" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE611 ,Set/Clear Active Bit 611" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE610 ,Set/Clear Active Bit 610" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE609 ,Set/Clear Active Bit 609" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE608 ,Set/Clear Active Bit 608" "Not active,Active"
else
hgroup.long 0x034C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x0350++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE671 ,Set/Clear Active Bit 671" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE670 ,Set/Clear Active Bit 670" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE669 ,Set/Clear Active Bit 669" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE668 ,Set/Clear Active Bit 668" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE667 ,Set/Clear Active Bit 667" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE666 ,Set/Clear Active Bit 666" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE665 ,Set/Clear Active Bit 665" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE664 ,Set/Clear Active Bit 664" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE663 ,Set/Clear Active Bit 663" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE662 ,Set/Clear Active Bit 662" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE661 ,Set/Clear Active Bit 661" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE660 ,Set/Clear Active Bit 660" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE659 ,Set/Clear Active Bit 659" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE658 ,Set/Clear Active Bit 658" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE657 ,Set/Clear Active Bit 657" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE656 ,Set/Clear Active Bit 656" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE655 ,Set/Clear Active Bit 655" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE654 ,Set/Clear Active Bit 654" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE653 ,Set/Clear Active Bit 653" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE652 ,Set/Clear Active Bit 652" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE651 ,Set/Clear Active Bit 651" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE650 ,Set/Clear Active Bit 650" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE649 ,Set/Clear Active Bit 649" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE648 ,Set/Clear Active Bit 648" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE647 ,Set/Clear Active Bit 647" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE646 ,Set/Clear Active Bit 646" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE645 ,Set/Clear Active Bit 645" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE644 ,Set/Clear Active Bit 644" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE643 ,Set/Clear Active Bit 643" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE642 ,Set/Clear Active Bit 642" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE641 ,Set/Clear Active Bit 641" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE640 ,Set/Clear Active Bit 640" "Not active,Active"
else
hgroup.long 0x0350++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x0354++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE703 ,Set/Clear Active Bit 703" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE702 ,Set/Clear Active Bit 702" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE701 ,Set/Clear Active Bit 701" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE700 ,Set/Clear Active Bit 700" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE699 ,Set/Clear Active Bit 699" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE698 ,Set/Clear Active Bit 698" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE697 ,Set/Clear Active Bit 697" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE696 ,Set/Clear Active Bit 696" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE695 ,Set/Clear Active Bit 695" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE694 ,Set/Clear Active Bit 694" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE693 ,Set/Clear Active Bit 693" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE692 ,Set/Clear Active Bit 692" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE691 ,Set/Clear Active Bit 691" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE690 ,Set/Clear Active Bit 690" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE689 ,Set/Clear Active Bit 689" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE688 ,Set/Clear Active Bit 688" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE687 ,Set/Clear Active Bit 687" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE686 ,Set/Clear Active Bit 686" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE685 ,Set/Clear Active Bit 685" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE684 ,Set/Clear Active Bit 684" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE683 ,Set/Clear Active Bit 683" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE682 ,Set/Clear Active Bit 682" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE681 ,Set/Clear Active Bit 681" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE680 ,Set/Clear Active Bit 680" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE679 ,Set/Clear Active Bit 679" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE678 ,Set/Clear Active Bit 678" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE677 ,Set/Clear Active Bit 677" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE676 ,Set/Clear Active Bit 676" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE675 ,Set/Clear Active Bit 675" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE674 ,Set/Clear Active Bit 674" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE673 ,Set/Clear Active Bit 673" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE672 ,Set/Clear Active Bit 672" "Not active,Active"
else
hgroup.long 0x0354++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x0358++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE735 ,Set/Clear Active Bit 735" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE734 ,Set/Clear Active Bit 734" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE733 ,Set/Clear Active Bit 733" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE732 ,Set/Clear Active Bit 732" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE731 ,Set/Clear Active Bit 731" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE730 ,Set/Clear Active Bit 730" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE729 ,Set/Clear Active Bit 729" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE728 ,Set/Clear Active Bit 728" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE727 ,Set/Clear Active Bit 727" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE726 ,Set/Clear Active Bit 726" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE725 ,Set/Clear Active Bit 725" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE724 ,Set/Clear Active Bit 724" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE723 ,Set/Clear Active Bit 723" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE722 ,Set/Clear Active Bit 722" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE721 ,Set/Clear Active Bit 721" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE720 ,Set/Clear Active Bit 720" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE719 ,Set/Clear Active Bit 719" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE718 ,Set/Clear Active Bit 718" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE717 ,Set/Clear Active Bit 717" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE716 ,Set/Clear Active Bit 716" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE715 ,Set/Clear Active Bit 715" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE714 ,Set/Clear Active Bit 714" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE713 ,Set/Clear Active Bit 713" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE712 ,Set/Clear Active Bit 712" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE711 ,Set/Clear Active Bit 711" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE710 ,Set/Clear Active Bit 710" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE709 ,Set/Clear Active Bit 709" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE708 ,Set/Clear Active Bit 708" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE707 ,Set/Clear Active Bit 707" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE706 ,Set/Clear Active Bit 706" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE705 ,Set/Clear Active Bit 705" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE704 ,Set/Clear Active Bit 704" "Not active,Active"
else
hgroup.long 0x0358++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x035C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE767 ,Set/Clear Active Bit 767" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE766 ,Set/Clear Active Bit 766" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE765 ,Set/Clear Active Bit 765" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE764 ,Set/Clear Active Bit 764" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE763 ,Set/Clear Active Bit 763" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE762 ,Set/Clear Active Bit 762" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE761 ,Set/Clear Active Bit 761" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE760 ,Set/Clear Active Bit 760" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE759 ,Set/Clear Active Bit 759" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE758 ,Set/Clear Active Bit 758" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE757 ,Set/Clear Active Bit 757" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE756 ,Set/Clear Active Bit 756" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE755 ,Set/Clear Active Bit 755" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE754 ,Set/Clear Active Bit 754" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE753 ,Set/Clear Active Bit 753" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE752 ,Set/Clear Active Bit 752" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE751 ,Set/Clear Active Bit 751" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE750 ,Set/Clear Active Bit 750" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE749 ,Set/Clear Active Bit 749" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE748 ,Set/Clear Active Bit 748" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE747 ,Set/Clear Active Bit 747" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE746 ,Set/Clear Active Bit 746" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE745 ,Set/Clear Active Bit 745" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE744 ,Set/Clear Active Bit 744" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE743 ,Set/Clear Active Bit 743" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE742 ,Set/Clear Active Bit 742" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE741 ,Set/Clear Active Bit 741" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE740 ,Set/Clear Active Bit 740" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE739 ,Set/Clear Active Bit 739" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE738 ,Set/Clear Active Bit 738" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE737 ,Set/Clear Active Bit 737" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE736 ,Set/Clear Active Bit 736" "Not active,Active"
else
hgroup.long 0x035C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x0360++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE799 ,Set/Clear Active Bit 799" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE798 ,Set/Clear Active Bit 798" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE797 ,Set/Clear Active Bit 797" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE796 ,Set/Clear Active Bit 796" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE795 ,Set/Clear Active Bit 795" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE794 ,Set/Clear Active Bit 794" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE793 ,Set/Clear Active Bit 793" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE792 ,Set/Clear Active Bit 792" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE791 ,Set/Clear Active Bit 791" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE790 ,Set/Clear Active Bit 790" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE789 ,Set/Clear Active Bit 789" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE788 ,Set/Clear Active Bit 788" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE787 ,Set/Clear Active Bit 787" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE786 ,Set/Clear Active Bit 786" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE785 ,Set/Clear Active Bit 785" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE784 ,Set/Clear Active Bit 784" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE783 ,Set/Clear Active Bit 783" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE782 ,Set/Clear Active Bit 782" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE781 ,Set/Clear Active Bit 781" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE780 ,Set/Clear Active Bit 780" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE779 ,Set/Clear Active Bit 779" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE778 ,Set/Clear Active Bit 778" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE777 ,Set/Clear Active Bit 777" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE776 ,Set/Clear Active Bit 776" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE775 ,Set/Clear Active Bit 775" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE774 ,Set/Clear Active Bit 774" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE773 ,Set/Clear Active Bit 773" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE772 ,Set/Clear Active Bit 772" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE771 ,Set/Clear Active Bit 771" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE770 ,Set/Clear Active Bit 770" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE769 ,Set/Clear Active Bit 769" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE768 ,Set/Clear Active Bit 768" "Not active,Active"
else
hgroup.long 0x0360++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x0364++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE831 ,Set/Clear Active Bit 831" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE830 ,Set/Clear Active Bit 830" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE829 ,Set/Clear Active Bit 829" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE828 ,Set/Clear Active Bit 828" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE827 ,Set/Clear Active Bit 827" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE826 ,Set/Clear Active Bit 826" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE825 ,Set/Clear Active Bit 825" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE824 ,Set/Clear Active Bit 824" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE823 ,Set/Clear Active Bit 823" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE822 ,Set/Clear Active Bit 822" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE821 ,Set/Clear Active Bit 821" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE820 ,Set/Clear Active Bit 820" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE819 ,Set/Clear Active Bit 819" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE818 ,Set/Clear Active Bit 818" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE817 ,Set/Clear Active Bit 817" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE816 ,Set/Clear Active Bit 816" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE815 ,Set/Clear Active Bit 815" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE814 ,Set/Clear Active Bit 814" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE813 ,Set/Clear Active Bit 813" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE812 ,Set/Clear Active Bit 812" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE811 ,Set/Clear Active Bit 811" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE810 ,Set/Clear Active Bit 810" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE809 ,Set/Clear Active Bit 809" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE808 ,Set/Clear Active Bit 808" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE807 ,Set/Clear Active Bit 807" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE806 ,Set/Clear Active Bit 806" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE805 ,Set/Clear Active Bit 805" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE804 ,Set/Clear Active Bit 804" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE803 ,Set/Clear Active Bit 803" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE802 ,Set/Clear Active Bit 802" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE801 ,Set/Clear Active Bit 801" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE800 ,Set/Clear Active Bit 800" "Not active,Active"
else
hgroup.long 0x0364++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x0368++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE863 ,Set/Clear Active Bit 863" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE862 ,Set/Clear Active Bit 862" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE861 ,Set/Clear Active Bit 861" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE860 ,Set/Clear Active Bit 860" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE859 ,Set/Clear Active Bit 859" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE858 ,Set/Clear Active Bit 858" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE857 ,Set/Clear Active Bit 857" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE856 ,Set/Clear Active Bit 856" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE855 ,Set/Clear Active Bit 855" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE854 ,Set/Clear Active Bit 854" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE853 ,Set/Clear Active Bit 853" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE852 ,Set/Clear Active Bit 852" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE851 ,Set/Clear Active Bit 851" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE850 ,Set/Clear Active Bit 850" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE849 ,Set/Clear Active Bit 849" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE848 ,Set/Clear Active Bit 848" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE847 ,Set/Clear Active Bit 847" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE846 ,Set/Clear Active Bit 846" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE845 ,Set/Clear Active Bit 845" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE844 ,Set/Clear Active Bit 844" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE843 ,Set/Clear Active Bit 843" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE842 ,Set/Clear Active Bit 842" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE841 ,Set/Clear Active Bit 841" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE840 ,Set/Clear Active Bit 840" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE839 ,Set/Clear Active Bit 839" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE838 ,Set/Clear Active Bit 838" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE837 ,Set/Clear Active Bit 837" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE836 ,Set/Clear Active Bit 836" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE835 ,Set/Clear Active Bit 835" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE834 ,Set/Clear Active Bit 834" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE833 ,Set/Clear Active Bit 833" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE832 ,Set/Clear Active Bit 832" "Not active,Active"
else
hgroup.long 0x0368++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x036C++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE895 ,Set/Clear Active Bit 895" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE894 ,Set/Clear Active Bit 894" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE893 ,Set/Clear Active Bit 893" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE892 ,Set/Clear Active Bit 892" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE891 ,Set/Clear Active Bit 891" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE890 ,Set/Clear Active Bit 890" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE889 ,Set/Clear Active Bit 889" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE888 ,Set/Clear Active Bit 888" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE887 ,Set/Clear Active Bit 887" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE886 ,Set/Clear Active Bit 886" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE885 ,Set/Clear Active Bit 885" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE884 ,Set/Clear Active Bit 884" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE883 ,Set/Clear Active Bit 883" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE882 ,Set/Clear Active Bit 882" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE881 ,Set/Clear Active Bit 881" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE880 ,Set/Clear Active Bit 880" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE879 ,Set/Clear Active Bit 879" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE878 ,Set/Clear Active Bit 878" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE877 ,Set/Clear Active Bit 877" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE876 ,Set/Clear Active Bit 876" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE875 ,Set/Clear Active Bit 875" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE874 ,Set/Clear Active Bit 874" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE873 ,Set/Clear Active Bit 873" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE872 ,Set/Clear Active Bit 872" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE871 ,Set/Clear Active Bit 871" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE870 ,Set/Clear Active Bit 870" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE869 ,Set/Clear Active Bit 869" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE868 ,Set/Clear Active Bit 868" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE867 ,Set/Clear Active Bit 867" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE866 ,Set/Clear Active Bit 866" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE865 ,Set/Clear Active Bit 865" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE864 ,Set/Clear Active Bit 864" "Not active,Active"
else
hgroup.long 0x036C++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x0370++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE927 ,Set/Clear Active Bit 927" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE926 ,Set/Clear Active Bit 926" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE925 ,Set/Clear Active Bit 925" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE924 ,Set/Clear Active Bit 924" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE923 ,Set/Clear Active Bit 923" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE922 ,Set/Clear Active Bit 922" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE921 ,Set/Clear Active Bit 921" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE920 ,Set/Clear Active Bit 920" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE919 ,Set/Clear Active Bit 919" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE918 ,Set/Clear Active Bit 918" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE917 ,Set/Clear Active Bit 917" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE916 ,Set/Clear Active Bit 916" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE915 ,Set/Clear Active Bit 915" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE914 ,Set/Clear Active Bit 914" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE913 ,Set/Clear Active Bit 913" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE912 ,Set/Clear Active Bit 912" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE911 ,Set/Clear Active Bit 911" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE910 ,Set/Clear Active Bit 910" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE909 ,Set/Clear Active Bit 909" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE908 ,Set/Clear Active Bit 908" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE907 ,Set/Clear Active Bit 907" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE906 ,Set/Clear Active Bit 906" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE905 ,Set/Clear Active Bit 905" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE904 ,Set/Clear Active Bit 904" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE903 ,Set/Clear Active Bit 903" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE902 ,Set/Clear Active Bit 902" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE901 ,Set/Clear Active Bit 901" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE900 ,Set/Clear Active Bit 900" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE899 ,Set/Clear Active Bit 899" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE898 ,Set/Clear Active Bit 898" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE897 ,Set/Clear Active Bit 897" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE896 ,Set/Clear Active Bit 896" "Not active,Active"
else
hgroup.long 0x0370++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x0374++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE959 ,Set/Clear Active Bit 959" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE958 ,Set/Clear Active Bit 958" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE957 ,Set/Clear Active Bit 957" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE956 ,Set/Clear Active Bit 956" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE955 ,Set/Clear Active Bit 955" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE954 ,Set/Clear Active Bit 954" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE953 ,Set/Clear Active Bit 953" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE952 ,Set/Clear Active Bit 952" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE951 ,Set/Clear Active Bit 951" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE950 ,Set/Clear Active Bit 950" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE949 ,Set/Clear Active Bit 949" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE948 ,Set/Clear Active Bit 948" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE947 ,Set/Clear Active Bit 947" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE946 ,Set/Clear Active Bit 946" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE945 ,Set/Clear Active Bit 945" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE944 ,Set/Clear Active Bit 944" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE943 ,Set/Clear Active Bit 943" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE942 ,Set/Clear Active Bit 942" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE941 ,Set/Clear Active Bit 941" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE940 ,Set/Clear Active Bit 940" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE939 ,Set/Clear Active Bit 939" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE938 ,Set/Clear Active Bit 938" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE937 ,Set/Clear Active Bit 937" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE936 ,Set/Clear Active Bit 936" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE935 ,Set/Clear Active Bit 935" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE934 ,Set/Clear Active Bit 934" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE933 ,Set/Clear Active Bit 933" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE932 ,Set/Clear Active Bit 932" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE931 ,Set/Clear Active Bit 931" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE930 ,Set/Clear Active Bit 930" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE929 ,Set/Clear Active Bit 929" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE928 ,Set/Clear Active Bit 928" "Not active,Active"
else
hgroup.long 0x0374++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x0378++0x03
line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE991 ,Set/Clear Active Bit 991" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE990 ,Set/Clear Active Bit 990" "Not active,Active"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE989 ,Set/Clear Active Bit 989" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE988 ,Set/Clear Active Bit 988" "Not active,Active"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE987 ,Set/Clear Active Bit 987" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE986 ,Set/Clear Active Bit 986" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE985 ,Set/Clear Active Bit 985" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE984 ,Set/Clear Active Bit 984" "Not active,Active"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE983 ,Set/Clear Active Bit 983" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE982 ,Set/Clear Active Bit 982" "Not active,Active"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE981 ,Set/Clear Active Bit 981" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE980 ,Set/Clear Active Bit 980" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE979 ,Set/Clear Active Bit 979" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE978 ,Set/Clear Active Bit 978" "Not active,Active"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE977 ,Set/Clear Active Bit 977" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE976 ,Set/Clear Active Bit 976" "Not active,Active"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE975 ,Set/Clear Active Bit 975" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE974 ,Set/Clear Active Bit 974" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE973 ,Set/Clear Active Bit 973" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE972 ,Set/Clear Active Bit 972" "Not active,Active"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE971 ,Set/Clear Active Bit 971" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE970 ,Set/Clear Active Bit 970" "Not active,Active"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE969 ,Set/Clear Active Bit 969" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE968 ,Set/Clear Active Bit 968" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE967 ,Set/Clear Active Bit 967" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE966 ,Set/Clear Active Bit 966" "Not active,Active"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE965 ,Set/Clear Active Bit 965" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE964 ,Set/Clear Active Bit 964" "Not active,Active"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE963 ,Set/Clear Active Bit 963" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE962 ,Set/Clear Active Bit 962" "Not active,Active"
textline "                                 "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE961 ,Set/Clear Active Bit 961" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE960 ,Set/Clear Active Bit 960" "Not active,Active"
else
hgroup.long 0x0378++0x03
hide.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30"
endif
tree.end
width 20.
tree "Priority Registers"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x400++0x03
hide.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hgroup.long 0x404++0x03
hide.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hgroup.long 0x408++0x03
hide.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hgroup.long 0x40C++0x03
hide.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hgroup.long 0x410++0x03
hide.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hgroup.long 0x414++0x03
hide.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hgroup.long 0x418++0x03
hide.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hgroup.long 0x41C++0x03
hide.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
else
group.long 0x400++0x03
line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID2    ,Interrupt ID2     Priority/Priority Byte Offset 2   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID0    ,Interrupt ID0     Priority/Priority Byte Offset 0   "
group.long 0x404++0x03
line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "  INTID6    ,Interrupt ID6     Priority/Priority Byte Offset 6   "
hexmask.long.byte 0x00 8.--15. 1. "  INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID4    ,Interrupt ID4     Priority/Priority Byte Offset 4   "
group.long 0x408++0x03
line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID10   ,Interrupt ID10    Priority/Priority Byte Offset 10  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "  INTID8    ,Interrupt ID8     Priority/Priority Byte Offset 8   "
group.long 0x40C++0x03
line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID14   ,Interrupt ID14    Priority/Priority Byte Offset 14  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID12   ,Interrupt ID12    Priority/Priority Byte Offset 12  "
group.long 0x410++0x03
line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID18   ,Interrupt ID18    Priority/Priority Byte Offset 18  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID16   ,Interrupt ID16    Priority/Priority Byte Offset 16  "
group.long 0x414++0x03
line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID22   ,Interrupt ID22    Priority/Priority Byte Offset 22  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID20   ,Interrupt ID20    Priority/Priority Byte Offset 20  "
group.long 0x418++0x03
line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID26   ,Interrupt ID26    Priority/Priority Byte Offset 26  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID24   ,Interrupt ID24    Priority/Priority Byte Offset 24  "
group.long 0x41C++0x03
line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID30   ,Interrupt ID30    Priority/Priority Byte Offset 30  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID28   ,Interrupt ID28    Priority/Priority Byte Offset 28  "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x420++0x03
line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hexmask.long.byte 0x00 24.--31. 1. " INTID35   ,Interrupt ID35   Priority/Priority Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID34   ,Interrupt ID34    Priority/Priority Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID33   ,Interrupt ID33   Priority/Priority Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID32   ,Interrupt ID32    Priority/Priority Byte Offset 32  "
group.long 0x424++0x03
line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hexmask.long.byte 0x00 24.--31. 1. " INTID39   ,Interrupt ID39   Priority/Priority Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID38   ,Interrupt ID38    Priority/Priority Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID37   ,Interrupt ID37   Priority/Priority Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID36   ,Interrupt ID36    Priority/Priority Byte Offset 36  "
group.long 0x428++0x03
line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hexmask.long.byte 0x00 24.--31. 1. " INTID43   ,Interrupt ID43   Priority/Priority Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID42   ,Interrupt ID42    Priority/Priority Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID41   ,Interrupt ID41   Priority/Priority Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID40   ,Interrupt ID40    Priority/Priority Byte Offset 40  "
group.long 0x42C++0x03
line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hexmask.long.byte 0x00 24.--31. 1. " INTID47   ,Interrupt ID47   Priority/Priority Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID46   ,Interrupt ID46    Priority/Priority Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID45   ,Interrupt ID45   Priority/Priority Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID44   ,Interrupt ID44    Priority/Priority Byte Offset 44  "
group.long 0x430++0x03
line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hexmask.long.byte 0x00 24.--31. 1. " INTID51   ,Interrupt ID51   Priority/Priority Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID50   ,Interrupt ID50    Priority/Priority Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID49   ,Interrupt ID49   Priority/Priority Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID48   ,Interrupt ID48    Priority/Priority Byte Offset 48  "
group.long 0x434++0x03
line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hexmask.long.byte 0x00 24.--31. 1. " INTID55   ,Interrupt ID55   Priority/Priority Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID54   ,Interrupt ID54    Priority/Priority Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID53   ,Interrupt ID53   Priority/Priority Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID52   ,Interrupt ID52    Priority/Priority Byte Offset 52  "
group.long 0x438++0x03
line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hexmask.long.byte 0x00 24.--31. 1. " INTID59   ,Interrupt ID59   Priority/Priority Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID58   ,Interrupt ID58    Priority/Priority Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID57   ,Interrupt ID57   Priority/Priority Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID56   ,Interrupt ID56    Priority/Priority Byte Offset 56  "
group.long 0x43C++0x03
line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
hexmask.long.byte 0x00 24.--31. 1. " INTID63   ,Interrupt ID63   Priority/Priority Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID62   ,Interrupt ID62    Priority/Priority Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID61   ,Interrupt ID61   Priority/Priority Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID60   ,Interrupt ID60    Priority/Priority Byte Offset 60  "
else
hgroup.long 0x420++0x03
hide.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8"
hgroup.long 0x424++0x03
hide.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9"
hgroup.long 0x428++0x03
hide.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10"
hgroup.long 0x42C++0x03
hide.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11"
hgroup.long 0x430++0x03
hide.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12"
hgroup.long 0x434++0x03
hide.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13"
hgroup.long 0x438++0x03
hide.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14"
hgroup.long 0x43C++0x03
hide.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x440++0x03
line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hexmask.long.byte 0x00 24.--31. 1. " INTID67   ,Interrupt ID67   Priority/Priority Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID66   ,Interrupt ID66    Priority/Priority Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID65   ,Interrupt ID65   Priority/Priority Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID64   ,Interrupt ID64    Priority/Priority Byte Offset 64  "
group.long 0x444++0x03
line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hexmask.long.byte 0x00 24.--31. 1. " INTID71   ,Interrupt ID71   Priority/Priority Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID70   ,Interrupt ID70    Priority/Priority Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID69   ,Interrupt ID69   Priority/Priority Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID68   ,Interrupt ID68    Priority/Priority Byte Offset 68  "
group.long 0x448++0x03
line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hexmask.long.byte 0x00 24.--31. 1. " INTID75   ,Interrupt ID75   Priority/Priority Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID74   ,Interrupt ID74    Priority/Priority Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID73   ,Interrupt ID73   Priority/Priority Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID72   ,Interrupt ID72    Priority/Priority Byte Offset 72  "
group.long 0x44C++0x03
line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hexmask.long.byte 0x00 24.--31. 1. " INTID79   ,Interrupt ID79   Priority/Priority Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID78   ,Interrupt ID78    Priority/Priority Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID77   ,Interrupt ID77   Priority/Priority Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID76   ,Interrupt ID76    Priority/Priority Byte Offset 76  "
group.long 0x450++0x03
line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hexmask.long.byte 0x00 24.--31. 1. " INTID83   ,Interrupt ID83   Priority/Priority Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID82   ,Interrupt ID82    Priority/Priority Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID81   ,Interrupt ID81   Priority/Priority Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID80   ,Interrupt ID80    Priority/Priority Byte Offset 80  "
group.long 0x454++0x03
line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hexmask.long.byte 0x00 24.--31. 1. " INTID87   ,Interrupt ID87   Priority/Priority Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID86   ,Interrupt ID86    Priority/Priority Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID85   ,Interrupt ID85   Priority/Priority Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID84   ,Interrupt ID84    Priority/Priority Byte Offset 84  "
group.long 0x458++0x03
line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hexmask.long.byte 0x00 24.--31. 1. " INTID91   ,Interrupt ID91   Priority/Priority Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID90   ,Interrupt ID90    Priority/Priority Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID89   ,Interrupt ID89   Priority/Priority Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID88   ,Interrupt ID88    Priority/Priority Byte Offset 88  "
group.long 0x45C++0x03
line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
hexmask.long.byte 0x00 24.--31. 1. " INTID95   ,Interrupt ID95   Priority/Priority Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID94   ,Interrupt ID94    Priority/Priority Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID93   ,Interrupt ID93   Priority/Priority Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID92   ,Interrupt ID92    Priority/Priority Byte Offset 92  "
else
hgroup.long 0x440++0x03
hide.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16"
hgroup.long 0x444++0x03
hide.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17"
hgroup.long 0x448++0x03
hide.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18"
hgroup.long 0x44C++0x03
hide.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19"
hgroup.long 0x450++0x03
hide.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20"
hgroup.long 0x454++0x03
hide.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21"
hgroup.long 0x458++0x03
hide.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22"
hgroup.long 0x45C++0x03
hide.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x460++0x03
line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hexmask.long.byte 0x00 24.--31. 1. " INTID99   ,Interrupt ID99   Priority/Priority Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  INTID98   ,Interrupt ID98    Priority/Priority Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  INTID97   ,Interrupt ID97   Priority/Priority Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  INTID96   ,Interrupt ID96    Priority/Priority Byte Offset 96  "
group.long 0x464++0x03
line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hexmask.long.byte 0x00 24.--31. 1. " INTID103  ,Interrupt ID103  Priority/Priority Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID102  ,Interrupt ID102   Priority/Priority Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID101  ,Interrupt ID101  Priority/Priority Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID100  ,Interrupt ID100   Priority/Priority Byte Offset 100 "
group.long 0x468++0x03
line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hexmask.long.byte 0x00 24.--31. 1. " INTID107  ,Interrupt ID107  Priority/Priority Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID106  ,Interrupt ID106   Priority/Priority Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID105  ,Interrupt ID105  Priority/Priority Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID104  ,Interrupt ID104   Priority/Priority Byte Offset 104 "
group.long 0x46C++0x03
line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hexmask.long.byte 0x00 24.--31. 1. " INTID111  ,Interrupt ID111  Priority/Priority Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID110  ,Interrupt ID110   Priority/Priority Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID109  ,Interrupt ID109  Priority/Priority Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID108  ,Interrupt ID108   Priority/Priority Byte Offset 108 "
group.long 0x470++0x03
line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hexmask.long.byte 0x00 24.--31. 1. " INTID115  ,Interrupt ID115  Priority/Priority Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID114  ,Interrupt ID114   Priority/Priority Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID113  ,Interrupt ID113  Priority/Priority Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID112  ,Interrupt ID112   Priority/Priority Byte Offset 112 "
group.long 0x474++0x03
line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hexmask.long.byte 0x00 24.--31. 1. " INTID119  ,Interrupt ID119  Priority/Priority Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID118  ,Interrupt ID118   Priority/Priority Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID117  ,Interrupt ID117  Priority/Priority Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID116  ,Interrupt ID116   Priority/Priority Byte Offset 116 "
group.long 0x478++0x03
line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hexmask.long.byte 0x00 24.--31. 1. " INTID123  ,Interrupt ID123  Priority/Priority Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID122  ,Interrupt ID122   Priority/Priority Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID121  ,Interrupt ID121  Priority/Priority Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID120  ,Interrupt ID120   Priority/Priority Byte Offset 120 "
group.long 0x47C++0x03
line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
hexmask.long.byte 0x00 24.--31. 1. " INTID127  ,Interrupt ID127  Priority/Priority Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID126  ,Interrupt ID126   Priority/Priority Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID125  ,Interrupt ID125  Priority/Priority Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID124  ,Interrupt ID124   Priority/Priority Byte Offset 124 "
else
hgroup.long 0x460++0x03
hide.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24"
hgroup.long 0x464++0x03
hide.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25"
hgroup.long 0x468++0x03
hide.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26"
hgroup.long 0x46C++0x03
hide.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27"
hgroup.long 0x470++0x03
hide.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28"
hgroup.long 0x474++0x03
hide.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29"
hgroup.long 0x478++0x03
hide.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30"
hgroup.long 0x47C++0x03
hide.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x480++0x03
line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hexmask.long.byte 0x00 24.--31. 1. " INTID131  ,Interrupt ID131  Priority/Priority Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID130  ,Interrupt ID130   Priority/Priority Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID129  ,Interrupt ID129  Priority/Priority Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID128  ,Interrupt ID128   Priority/Priority Byte Offset 128 "
group.long 0x484++0x03
line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hexmask.long.byte 0x00 24.--31. 1. " INTID135  ,Interrupt ID135  Priority/Priority Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID134  ,Interrupt ID134   Priority/Priority Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID133  ,Interrupt ID133  Priority/Priority Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID132  ,Interrupt ID132   Priority/Priority Byte Offset 132 "
group.long 0x488++0x03
line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hexmask.long.byte 0x00 24.--31. 1. " INTID139  ,Interrupt ID139  Priority/Priority Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID138  ,Interrupt ID138   Priority/Priority Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID137  ,Interrupt ID137  Priority/Priority Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID136  ,Interrupt ID136   Priority/Priority Byte Offset 136 "
group.long 0x48C++0x03
line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hexmask.long.byte 0x00 24.--31. 1. " INTID143  ,Interrupt ID143  Priority/Priority Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID142  ,Interrupt ID142   Priority/Priority Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID141  ,Interrupt ID141  Priority/Priority Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID140  ,Interrupt ID140   Priority/Priority Byte Offset 140 "
group.long 0x490++0x03
line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hexmask.long.byte 0x00 24.--31. 1. " INTID147  ,Interrupt ID147  Priority/Priority Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID146  ,Interrupt ID146   Priority/Priority Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID145  ,Interrupt ID145  Priority/Priority Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID144  ,Interrupt ID144   Priority/Priority Byte Offset 144 "
group.long 0x494++0x03
line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hexmask.long.byte 0x00 24.--31. 1. " INTID151  ,Interrupt ID151  Priority/Priority Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID150  ,Interrupt ID150   Priority/Priority Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID149  ,Interrupt ID149  Priority/Priority Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID148  ,Interrupt ID148   Priority/Priority Byte Offset 148 "
group.long 0x498++0x03
line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hexmask.long.byte 0x00 24.--31. 1. " INTID155  ,Interrupt ID155  Priority/Priority Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID154  ,Interrupt ID154   Priority/Priority Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID153  ,Interrupt ID153  Priority/Priority Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID152  ,Interrupt ID152   Priority/Priority Byte Offset 152 "
group.long 0x49C++0x03
line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
hexmask.long.byte 0x00 24.--31. 1. " INTID159  ,Interrupt ID159  Priority/Priority Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID158  ,Interrupt ID158   Priority/Priority Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID157  ,Interrupt ID157  Priority/Priority Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID156  ,Interrupt ID156   Priority/Priority Byte Offset 156 "
else
hgroup.long 0x480++0x03
hide.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32"
hgroup.long 0x484++0x03
hide.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33"
hgroup.long 0x488++0x03
hide.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34"
hgroup.long 0x48C++0x03
hide.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35"
hgroup.long 0x490++0x03
hide.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36"
hgroup.long 0x494++0x03
hide.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37"
hgroup.long 0x498++0x03
hide.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38"
hgroup.long 0x49C++0x03
hide.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x4A0++0x03
line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hexmask.long.byte 0x00 24.--31. 1. " INTID163  ,Interrupt ID163  Priority/Priority Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID162  ,Interrupt ID162   Priority/Priority Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID161  ,Interrupt ID161  Priority/Priority Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID160  ,Interrupt ID160   Priority/Priority Byte Offset 160 "
group.long 0x4A4++0x03
line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hexmask.long.byte 0x00 24.--31. 1. " INTID167  ,Interrupt ID167  Priority/Priority Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID166  ,Interrupt ID166   Priority/Priority Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID165  ,Interrupt ID165  Priority/Priority Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID164  ,Interrupt ID164   Priority/Priority Byte Offset 164 "
group.long 0x4A8++0x03
line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hexmask.long.byte 0x00 24.--31. 1. " INTID171  ,Interrupt ID171  Priority/Priority Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID170  ,Interrupt ID170   Priority/Priority Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID169  ,Interrupt ID169  Priority/Priority Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID168  ,Interrupt ID168   Priority/Priority Byte Offset 168 "
group.long 0x4AC++0x03
line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hexmask.long.byte 0x00 24.--31. 1. " INTID175  ,Interrupt ID175  Priority/Priority Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID174  ,Interrupt ID174   Priority/Priority Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID173  ,Interrupt ID173  Priority/Priority Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID172  ,Interrupt ID172   Priority/Priority Byte Offset 172 "
group.long 0x4B0++0x03
line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hexmask.long.byte 0x00 24.--31. 1. " INTID179  ,Interrupt ID179  Priority/Priority Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID178  ,Interrupt ID178   Priority/Priority Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID177  ,Interrupt ID177  Priority/Priority Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID176  ,Interrupt ID176   Priority/Priority Byte Offset 176 "
group.long 0x4B4++0x03
line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hexmask.long.byte 0x00 24.--31. 1. " INTID183  ,Interrupt ID183  Priority/Priority Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID182  ,Interrupt ID182   Priority/Priority Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID181  ,Interrupt ID181  Priority/Priority Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID180  ,Interrupt ID180   Priority/Priority Byte Offset 180 "
group.long 0x4B8++0x03
line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hexmask.long.byte 0x00 24.--31. 1. " INTID187  ,Interrupt ID187  Priority/Priority Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID186  ,Interrupt ID186   Priority/Priority Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID185  ,Interrupt ID185  Priority/Priority Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID184  ,Interrupt ID184   Priority/Priority Byte Offset 184 "
group.long 0x4BC++0x03
line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
hexmask.long.byte 0x00 24.--31. 1. " INTID191  ,Interrupt ID191  Priority/Priority Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID190  ,Interrupt ID190   Priority/Priority Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID189  ,Interrupt ID189  Priority/Priority Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID188  ,Interrupt ID188   Priority/Priority Byte Offset 188 "
else
hgroup.long 0x4A0++0x03
hide.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40"
hgroup.long 0x4A4++0x03
hide.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41"
hgroup.long 0x4A8++0x03
hide.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42"
hgroup.long 0x4AC++0x03
hide.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43"
hgroup.long 0x4B0++0x03
hide.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44"
hgroup.long 0x4B4++0x03
hide.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45"
hgroup.long 0x4B8++0x03
hide.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46"
hgroup.long 0x4BC++0x03
hide.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x4C0++0x03
line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hexmask.long.byte 0x00 24.--31. 1. " INTID195  ,Interrupt ID195  Priority/Priority Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID194  ,Interrupt ID194   Priority/Priority Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID193  ,Interrupt ID193  Priority/Priority Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID192  ,Interrupt ID192   Priority/Priority Byte Offset 192 "
group.long 0x4C4++0x03
line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hexmask.long.byte 0x00 24.--31. 1. " INTID199  ,Interrupt ID199  Priority/Priority Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID198  ,Interrupt ID198   Priority/Priority Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID197  ,Interrupt ID197  Priority/Priority Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID196  ,Interrupt ID196   Priority/Priority Byte Offset 196 "
group.long 0x4C8++0x03
line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hexmask.long.byte 0x00 24.--31. 1. " INTID203  ,Interrupt ID203  Priority/Priority Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID202  ,Interrupt ID202   Priority/Priority Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID201  ,Interrupt ID201  Priority/Priority Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID200  ,Interrupt ID200   Priority/Priority Byte Offset 200 "
group.long 0x4CC++0x03
line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hexmask.long.byte 0x00 24.--31. 1. " INTID207  ,Interrupt ID207  Priority/Priority Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID206  ,Interrupt ID206   Priority/Priority Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID205  ,Interrupt ID205  Priority/Priority Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID204  ,Interrupt ID204   Priority/Priority Byte Offset 204 "
group.long 0x4D0++0x03
line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hexmask.long.byte 0x00 24.--31. 1. " INTID211  ,Interrupt ID211  Priority/Priority Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID210  ,Interrupt ID210   Priority/Priority Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID209  ,Interrupt ID209  Priority/Priority Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID208  ,Interrupt ID208   Priority/Priority Byte Offset 208 "
group.long 0x4D4++0x03
line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hexmask.long.byte 0x00 24.--31. 1. " INTID215  ,Interrupt ID215  Priority/Priority Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID214  ,Interrupt ID214   Priority/Priority Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID213  ,Interrupt ID213  Priority/Priority Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID212  ,Interrupt ID212   Priority/Priority Byte Offset 212 "
group.long 0x4D8++0x03
line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hexmask.long.byte 0x00 24.--31. 1. " INTID219  ,Interrupt ID219  Priority/Priority Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID218  ,Interrupt ID218   Priority/Priority Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID217  ,Interrupt ID217  Priority/Priority Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID216  ,Interrupt ID216   Priority/Priority Byte Offset 216 "
group.long 0x4DC++0x03
line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
hexmask.long.byte 0x00 24.--31. 1. " INTID223  ,Interrupt ID223  Priority/Priority Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID222  ,Interrupt ID222   Priority/Priority Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID221  ,Interrupt ID221  Priority/Priority Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID220  ,Interrupt ID220   Priority/Priority Byte Offset 220 "
else
hgroup.long 0x4C0++0x03
hide.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48"
hgroup.long 0x4C4++0x03
hide.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49"
hgroup.long 0x4C8++0x03
hide.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50"
hgroup.long 0x4CC++0x03
hide.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51"
hgroup.long 0x4D0++0x03
hide.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52"
hgroup.long 0x4D4++0x03
hide.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53"
hgroup.long 0x4D8++0x03
hide.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54"
hgroup.long 0x4DC++0x03
hide.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x4E0++0x03
line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hexmask.long.byte 0x00 24.--31. 1. " INTID227  ,Interrupt ID227  Priority/Priority Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID226  ,Interrupt ID226   Priority/Priority Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID225  ,Interrupt ID225  Priority/Priority Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID224  ,Interrupt ID224   Priority/Priority Byte Offset 224 "
group.long 0x4E4++0x03
line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hexmask.long.byte 0x00 24.--31. 1. " INTID231  ,Interrupt ID231  Priority/Priority Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID230  ,Interrupt ID230   Priority/Priority Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID229  ,Interrupt ID229  Priority/Priority Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID228  ,Interrupt ID228   Priority/Priority Byte Offset 228 "
group.long 0x4E8++0x03
line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hexmask.long.byte 0x00 24.--31. 1. " INTID235  ,Interrupt ID235  Priority/Priority Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID234  ,Interrupt ID234   Priority/Priority Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID233  ,Interrupt ID233  Priority/Priority Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID232  ,Interrupt ID232   Priority/Priority Byte Offset 232 "
group.long 0x4EC++0x03
line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hexmask.long.byte 0x00 24.--31. 1. " INTID239  ,Interrupt ID239  Priority/Priority Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID238  ,Interrupt ID238   Priority/Priority Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID237  ,Interrupt ID237  Priority/Priority Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID236  ,Interrupt ID236   Priority/Priority Byte Offset 236 "
group.long 0x4F0++0x03
line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hexmask.long.byte 0x00 24.--31. 1. " INTID243  ,Interrupt ID243  Priority/Priority Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID242  ,Interrupt ID242   Priority/Priority Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID241  ,Interrupt ID241  Priority/Priority Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID240  ,Interrupt ID240   Priority/Priority Byte Offset 240 "
group.long 0x4F4++0x03
line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hexmask.long.byte 0x00 24.--31. 1. " INTID247  ,Interrupt ID247  Priority/Priority Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID246  ,Interrupt ID246   Priority/Priority Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID245  ,Interrupt ID245  Priority/Priority Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID244  ,Interrupt ID244   Priority/Priority Byte Offset 244 "
group.long 0x4F8++0x03
line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hexmask.long.byte 0x00 24.--31. 1. " INTID251  ,Interrupt ID251  Priority/Priority Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID250  ,Interrupt ID250   Priority/Priority Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID249  ,Interrupt ID249  Priority/Priority Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID248  ,Interrupt ID248   Priority/Priority Byte Offset 248 "
group.long 0x4FC++0x03
line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
hexmask.long.byte 0x00 24.--31. 1. " INTID255  ,Interrupt ID255  Priority/Priority Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID254  ,Interrupt ID254   Priority/Priority Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID253  ,Interrupt ID253  Priority/Priority Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID252  ,Interrupt ID252   Priority/Priority Byte Offset 252 "
else
hgroup.long 0x4E0++0x03
hide.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56"
hgroup.long 0x4E4++0x03
hide.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57"
hgroup.long 0x4E8++0x03
hide.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58"
hgroup.long 0x4EC++0x03
hide.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59"
hgroup.long 0x4F0++0x03
hide.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60"
hgroup.long 0x4F4++0x03
hide.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61"
hgroup.long 0x4F8++0x03
hide.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62"
hgroup.long 0x4FC++0x03
hide.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x500++0x03
line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hexmask.long.byte 0x00 24.--31. 1. " INTID259  ,Interrupt ID259  Priority/Priority Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID258  ,Interrupt ID258   Priority/Priority Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID257  ,Interrupt ID257  Priority/Priority Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID256  ,Interrupt ID256   Priority/Priority Byte Offset 256 "
group.long 0x504++0x03
line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hexmask.long.byte 0x00 24.--31. 1. " INTID263  ,Interrupt ID263  Priority/Priority Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID262  ,Interrupt ID262   Priority/Priority Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID261  ,Interrupt ID261  Priority/Priority Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID260  ,Interrupt ID260   Priority/Priority Byte Offset 260 "
group.long 0x508++0x03
line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hexmask.long.byte 0x00 24.--31. 1. " INTID267  ,Interrupt ID267  Priority/Priority Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID266  ,Interrupt ID266   Priority/Priority Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID265  ,Interrupt ID265  Priority/Priority Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID264  ,Interrupt ID264   Priority/Priority Byte Offset 264 "
group.long 0x50C++0x03
line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hexmask.long.byte 0x00 24.--31. 1. " INTID271  ,Interrupt ID271  Priority/Priority Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID270  ,Interrupt ID270   Priority/Priority Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID269  ,Interrupt ID269  Priority/Priority Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID268  ,Interrupt ID268   Priority/Priority Byte Offset 268 "
group.long 0x510++0x03
line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hexmask.long.byte 0x00 24.--31. 1. " INTID275  ,Interrupt ID275  Priority/Priority Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID274  ,Interrupt ID274   Priority/Priority Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID273  ,Interrupt ID273  Priority/Priority Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID272  ,Interrupt ID272   Priority/Priority Byte Offset 272 "
group.long 0x514++0x03
line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hexmask.long.byte 0x00 24.--31. 1. " INTID279  ,Interrupt ID279  Priority/Priority Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID278  ,Interrupt ID278   Priority/Priority Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID277  ,Interrupt ID277  Priority/Priority Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID276  ,Interrupt ID276   Priority/Priority Byte Offset 276 "
group.long 0x518++0x03
line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hexmask.long.byte 0x00 24.--31. 1. " INTID283  ,Interrupt ID283  Priority/Priority Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID282  ,Interrupt ID282   Priority/Priority Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID281  ,Interrupt ID281  Priority/Priority Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID280  ,Interrupt ID280   Priority/Priority Byte Offset 280 "
group.long 0x51C++0x03
line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
hexmask.long.byte 0x00 24.--31. 1. " INTID287  ,Interrupt ID287  Priority/Priority Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID286  ,Interrupt ID286   Priority/Priority Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID285  ,Interrupt ID285  Priority/Priority Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID284  ,Interrupt ID284   Priority/Priority Byte Offset 284 "
else
hgroup.long 0x500++0x03
hide.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64"
hgroup.long 0x504++0x03
hide.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65"
hgroup.long 0x508++0x03
hide.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66"
hgroup.long 0x50C++0x03
hide.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67"
hgroup.long 0x510++0x03
hide.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68"
hgroup.long 0x514++0x03
hide.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69"
hgroup.long 0x518++0x03
hide.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70"
hgroup.long 0x51C++0x03
hide.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x520++0x03
line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hexmask.long.byte 0x00 24.--31. 1. " INTID291  ,Interrupt ID291  Priority/Priority Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID290  ,Interrupt ID290   Priority/Priority Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID289  ,Interrupt ID289  Priority/Priority Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID288  ,Interrupt ID288   Priority/Priority Byte Offset 288 "
group.long 0x524++0x03
line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hexmask.long.byte 0x00 24.--31. 1. " INTID295  ,Interrupt ID295  Priority/Priority Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID294  ,Interrupt ID294   Priority/Priority Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID293  ,Interrupt ID293  Priority/Priority Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID292  ,Interrupt ID292   Priority/Priority Byte Offset 292 "
group.long 0x528++0x03
line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hexmask.long.byte 0x00 24.--31. 1. " INTID299  ,Interrupt ID299  Priority/Priority Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID298  ,Interrupt ID298   Priority/Priority Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID297  ,Interrupt ID297  Priority/Priority Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID296  ,Interrupt ID296   Priority/Priority Byte Offset 296 "
group.long 0x52C++0x03
line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hexmask.long.byte 0x00 24.--31. 1. " INTID303  ,Interrupt ID303  Priority/Priority Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID302  ,Interrupt ID302   Priority/Priority Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID301  ,Interrupt ID301  Priority/Priority Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID300  ,Interrupt ID300   Priority/Priority Byte Offset 300 "
group.long 0x530++0x03
line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hexmask.long.byte 0x00 24.--31. 1. " INTID307  ,Interrupt ID307  Priority/Priority Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID306  ,Interrupt ID306   Priority/Priority Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID305  ,Interrupt ID305  Priority/Priority Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID304  ,Interrupt ID304   Priority/Priority Byte Offset 304 "
group.long 0x534++0x03
line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hexmask.long.byte 0x00 24.--31. 1. " INTID311  ,Interrupt ID311  Priority/Priority Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID310  ,Interrupt ID310   Priority/Priority Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID309  ,Interrupt ID309  Priority/Priority Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID308  ,Interrupt ID308   Priority/Priority Byte Offset 308 "
group.long 0x538++0x03
line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hexmask.long.byte 0x00 24.--31. 1. " INTID315  ,Interrupt ID315  Priority/Priority Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID314  ,Interrupt ID314   Priority/Priority Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID313  ,Interrupt ID313  Priority/Priority Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID312  ,Interrupt ID312   Priority/Priority Byte Offset 312 "
group.long 0x53C++0x03
line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
hexmask.long.byte 0x00 24.--31. 1. " INTID319  ,Interrupt ID319  Priority/Priority Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID318  ,Interrupt ID318   Priority/Priority Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID317  ,Interrupt ID317  Priority/Priority Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID316  ,Interrupt ID316   Priority/Priority Byte Offset 316 "
else
hgroup.long 0x520++0x03
hide.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72"
hgroup.long 0x524++0x03
hide.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73"
hgroup.long 0x528++0x03
hide.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74"
hgroup.long 0x52C++0x03
hide.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75"
hgroup.long 0x530++0x03
hide.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76"
hgroup.long 0x534++0x03
hide.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77"
hgroup.long 0x538++0x03
hide.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78"
hgroup.long 0x53C++0x03
hide.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x540++0x03
line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hexmask.long.byte 0x00 24.--31. 1. " INTID323  ,Interrupt ID323  Priority/Priority Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID322  ,Interrupt ID322   Priority/Priority Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID321  ,Interrupt ID321  Priority/Priority Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID320  ,Interrupt ID320   Priority/Priority Byte Offset 320 "
group.long 0x544++0x03
line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hexmask.long.byte 0x00 24.--31. 1. " INTID327  ,Interrupt ID327  Priority/Priority Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID326  ,Interrupt ID326   Priority/Priority Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID325  ,Interrupt ID325  Priority/Priority Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID324  ,Interrupt ID324   Priority/Priority Byte Offset 324 "
group.long 0x548++0x03
line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hexmask.long.byte 0x00 24.--31. 1. " INTID331  ,Interrupt ID331  Priority/Priority Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID330  ,Interrupt ID330   Priority/Priority Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID329  ,Interrupt ID329  Priority/Priority Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID328  ,Interrupt ID328   Priority/Priority Byte Offset 328 "
group.long 0x54C++0x03
line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hexmask.long.byte 0x00 24.--31. 1. " INTID335  ,Interrupt ID335  Priority/Priority Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID334  ,Interrupt ID334   Priority/Priority Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID333  ,Interrupt ID333  Priority/Priority Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID332  ,Interrupt ID332   Priority/Priority Byte Offset 332 "
group.long 0x550++0x03
line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hexmask.long.byte 0x00 24.--31. 1. " INTID339  ,Interrupt ID339  Priority/Priority Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID338  ,Interrupt ID338   Priority/Priority Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID337  ,Interrupt ID337  Priority/Priority Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID336  ,Interrupt ID336   Priority/Priority Byte Offset 336 "
group.long 0x554++0x03
line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hexmask.long.byte 0x00 24.--31. 1. " INTID343  ,Interrupt ID343  Priority/Priority Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID342  ,Interrupt ID342   Priority/Priority Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID341  ,Interrupt ID341  Priority/Priority Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID340  ,Interrupt ID340   Priority/Priority Byte Offset 340 "
group.long 0x558++0x03
line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hexmask.long.byte 0x00 24.--31. 1. " INTID347  ,Interrupt ID347  Priority/Priority Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID346  ,Interrupt ID346   Priority/Priority Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID345  ,Interrupt ID345  Priority/Priority Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID344  ,Interrupt ID344   Priority/Priority Byte Offset 344 "
group.long 0x55C++0x03
line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
hexmask.long.byte 0x00 24.--31. 1. " INTID351  ,Interrupt ID351  Priority/Priority Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID350  ,Interrupt ID350   Priority/Priority Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID349  ,Interrupt ID349  Priority/Priority Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID348  ,Interrupt ID348   Priority/Priority Byte Offset 348 "
else
hgroup.long 0x540++0x03
hide.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80"
hgroup.long 0x544++0x03
hide.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81"
hgroup.long 0x548++0x03
hide.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82"
hgroup.long 0x54C++0x03
hide.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83"
hgroup.long 0x550++0x03
hide.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84"
hgroup.long 0x554++0x03
hide.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85"
hgroup.long 0x558++0x03
hide.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86"
hgroup.long 0x55C++0x03
hide.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x560++0x03
line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hexmask.long.byte 0x00 24.--31. 1. " INTID355  ,Interrupt ID355  Priority/Priority Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID354  ,Interrupt ID354   Priority/Priority Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID353  ,Interrupt ID353  Priority/Priority Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID352  ,Interrupt ID352   Priority/Priority Byte Offset 352 "
group.long 0x564++0x03
line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hexmask.long.byte 0x00 24.--31. 1. " INTID359  ,Interrupt ID359  Priority/Priority Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID358  ,Interrupt ID358   Priority/Priority Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID357  ,Interrupt ID357  Priority/Priority Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID356  ,Interrupt ID356   Priority/Priority Byte Offset 356 "
group.long 0x568++0x03
line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hexmask.long.byte 0x00 24.--31. 1. " INTID363  ,Interrupt ID363  Priority/Priority Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID362  ,Interrupt ID362   Priority/Priority Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID361  ,Interrupt ID361  Priority/Priority Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID360  ,Interrupt ID360   Priority/Priority Byte Offset 360 "
group.long 0x56C++0x03
line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hexmask.long.byte 0x00 24.--31. 1. " INTID367  ,Interrupt ID367  Priority/Priority Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID366  ,Interrupt ID366   Priority/Priority Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID365  ,Interrupt ID365  Priority/Priority Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID364  ,Interrupt ID364   Priority/Priority Byte Offset 364 "
group.long 0x570++0x03
line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hexmask.long.byte 0x00 24.--31. 1. " INTID371  ,Interrupt ID371  Priority/Priority Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID370  ,Interrupt ID370   Priority/Priority Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID369  ,Interrupt ID369  Priority/Priority Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID368  ,Interrupt ID368   Priority/Priority Byte Offset 368 "
group.long 0x574++0x03
line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hexmask.long.byte 0x00 24.--31. 1. " INTID375  ,Interrupt ID375  Priority/Priority Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID374  ,Interrupt ID374   Priority/Priority Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID373  ,Interrupt ID373  Priority/Priority Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID372  ,Interrupt ID372   Priority/Priority Byte Offset 372 "
group.long 0x578++0x03
line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hexmask.long.byte 0x00 24.--31. 1. " INTID379  ,Interrupt ID379  Priority/Priority Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID378  ,Interrupt ID378   Priority/Priority Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID377  ,Interrupt ID377  Priority/Priority Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID376  ,Interrupt ID376   Priority/Priority Byte Offset 376 "
group.long 0x57C++0x03
line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
hexmask.long.byte 0x00 24.--31. 1. " INTID383  ,Interrupt ID383  Priority/Priority Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID382  ,Interrupt ID382   Priority/Priority Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID381  ,Interrupt ID381  Priority/Priority Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID380  ,Interrupt ID380   Priority/Priority Byte Offset 380 "
else
hgroup.long 0x560++0x03
hide.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88"
hgroup.long 0x564++0x03
hide.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89"
hgroup.long 0x568++0x03
hide.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90"
hgroup.long 0x56C++0x03
hide.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91"
hgroup.long 0x570++0x03
hide.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92"
hgroup.long 0x574++0x03
hide.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93"
hgroup.long 0x578++0x03
hide.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94"
hgroup.long 0x57C++0x03
hide.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x580++0x03
line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hexmask.long.byte 0x00 24.--31. 1. " INTID387  ,Interrupt ID387  Priority/Priority Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID386  ,Interrupt ID386   Priority/Priority Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID385  ,Interrupt ID385  Priority/Priority Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID384  ,Interrupt ID384   Priority/Priority Byte Offset 384 "
group.long 0x584++0x03
line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hexmask.long.byte 0x00 24.--31. 1. " INTID391  ,Interrupt ID391  Priority/Priority Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID390  ,Interrupt ID390   Priority/Priority Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID389  ,Interrupt ID389  Priority/Priority Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID388  ,Interrupt ID388   Priority/Priority Byte Offset 388 "
group.long 0x588++0x03
line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hexmask.long.byte 0x00 24.--31. 1. " INTID395  ,Interrupt ID395  Priority/Priority Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID394  ,Interrupt ID394   Priority/Priority Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID393  ,Interrupt ID393  Priority/Priority Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID392  ,Interrupt ID392   Priority/Priority Byte Offset 392 "
group.long 0x58C++0x03
line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hexmask.long.byte 0x00 24.--31. 1. " INTID399  ,Interrupt ID399  Priority/Priority Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID398  ,Interrupt ID398   Priority/Priority Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID397  ,Interrupt ID397  Priority/Priority Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID396  ,Interrupt ID396   Priority/Priority Byte Offset 396 "
group.long 0x590++0x03
line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hexmask.long.byte 0x00 24.--31. 1. " INTID403  ,Interrupt ID403  Priority/Priority Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID402  ,Interrupt ID402   Priority/Priority Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID401  ,Interrupt ID401  Priority/Priority Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID400  ,Interrupt ID400   Priority/Priority Byte Offset 400 "
group.long 0x594++0x03
line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hexmask.long.byte 0x00 24.--31. 1. " INTID407  ,Interrupt ID407  Priority/Priority Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID406  ,Interrupt ID406   Priority/Priority Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID405  ,Interrupt ID405  Priority/Priority Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID404  ,Interrupt ID404   Priority/Priority Byte Offset 404 "
group.long 0x598++0x03
line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hexmask.long.byte 0x00 24.--31. 1. " INTID411  ,Interrupt ID411  Priority/Priority Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID410  ,Interrupt ID410   Priority/Priority Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID409  ,Interrupt ID409  Priority/Priority Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID408  ,Interrupt ID408   Priority/Priority Byte Offset 408 "
group.long 0x59C++0x03
line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
hexmask.long.byte 0x00 24.--31. 1. " INTID415  ,Interrupt ID415  Priority/Priority Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID414  ,Interrupt ID414   Priority/Priority Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID413  ,Interrupt ID413  Priority/Priority Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID412  ,Interrupt ID412   Priority/Priority Byte Offset 412 "
else
hgroup.long 0x580++0x03
hide.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96"
hgroup.long 0x584++0x03
hide.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97"
hgroup.long 0x588++0x03
hide.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98"
hgroup.long 0x58C++0x03
hide.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99"
hgroup.long 0x590++0x03
hide.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100"
hgroup.long 0x594++0x03
hide.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101"
hgroup.long 0x598++0x03
hide.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102"
hgroup.long 0x59C++0x03
hide.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x5A0++0x03
line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hexmask.long.byte 0x00 24.--31. 1. " INTID419  ,Interrupt ID419  Priority/Priority Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID418  ,Interrupt ID418   Priority/Priority Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID417  ,Interrupt ID417  Priority/Priority Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID416  ,Interrupt ID416   Priority/Priority Byte Offset 416 "
group.long 0x5A4++0x03
line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hexmask.long.byte 0x00 24.--31. 1. " INTID423  ,Interrupt ID423  Priority/Priority Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID422  ,Interrupt ID422   Priority/Priority Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID421  ,Interrupt ID421  Priority/Priority Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID420  ,Interrupt ID420   Priority/Priority Byte Offset 420 "
group.long 0x5A8++0x03
line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hexmask.long.byte 0x00 24.--31. 1. " INTID427  ,Interrupt ID427  Priority/Priority Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID426  ,Interrupt ID426   Priority/Priority Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID425  ,Interrupt ID425  Priority/Priority Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID424  ,Interrupt ID424   Priority/Priority Byte Offset 424 "
group.long 0x5AC++0x03
line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hexmask.long.byte 0x00 24.--31. 1. " INTID431  ,Interrupt ID431  Priority/Priority Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID430  ,Interrupt ID430   Priority/Priority Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID429  ,Interrupt ID429  Priority/Priority Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID428  ,Interrupt ID428   Priority/Priority Byte Offset 428 "
group.long 0x5B0++0x03
line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hexmask.long.byte 0x00 24.--31. 1. " INTID435  ,Interrupt ID435  Priority/Priority Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID434  ,Interrupt ID434   Priority/Priority Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID433  ,Interrupt ID433  Priority/Priority Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID432  ,Interrupt ID432   Priority/Priority Byte Offset 432 "
group.long 0x5B4++0x03
line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hexmask.long.byte 0x00 24.--31. 1. " INTID439  ,Interrupt ID439  Priority/Priority Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID438  ,Interrupt ID438   Priority/Priority Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID437  ,Interrupt ID437  Priority/Priority Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID436  ,Interrupt ID436   Priority/Priority Byte Offset 436 "
group.long 0x5B8++0x03
line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hexmask.long.byte 0x00 24.--31. 1. " INTID443  ,Interrupt ID443  Priority/Priority Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID442  ,Interrupt ID442   Priority/Priority Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID441  ,Interrupt ID441  Priority/Priority Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID440  ,Interrupt ID440   Priority/Priority Byte Offset 440 "
group.long 0x5BC++0x03
line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
hexmask.long.byte 0x00 24.--31. 1. " INTID447  ,Interrupt ID447  Priority/Priority Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID446  ,Interrupt ID446   Priority/Priority Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID445  ,Interrupt ID445  Priority/Priority Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID444  ,Interrupt ID444   Priority/Priority Byte Offset 444 "
else
hgroup.long 0x5A0++0x03
hide.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104"
hgroup.long 0x5A4++0x03
hide.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105"
hgroup.long 0x5A8++0x03
hide.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106"
hgroup.long 0x5AC++0x03
hide.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107"
hgroup.long 0x5B0++0x03
hide.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108"
hgroup.long 0x5B4++0x03
hide.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109"
hgroup.long 0x5B8++0x03
hide.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110"
hgroup.long 0x5BC++0x03
hide.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x5C0++0x03
line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hexmask.long.byte 0x00 24.--31. 1. " INTID451  ,Interrupt ID451  Priority/Priority Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID450  ,Interrupt ID450   Priority/Priority Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID449  ,Interrupt ID449  Priority/Priority Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID448  ,Interrupt ID448   Priority/Priority Byte Offset 448 "
group.long 0x5C4++0x03
line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hexmask.long.byte 0x00 24.--31. 1. " INTID455  ,Interrupt ID455  Priority/Priority Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID454  ,Interrupt ID454   Priority/Priority Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID453  ,Interrupt ID453  Priority/Priority Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID452  ,Interrupt ID452   Priority/Priority Byte Offset 452 "
group.long 0x5C8++0x03
line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hexmask.long.byte 0x00 24.--31. 1. " INTID459  ,Interrupt ID459  Priority/Priority Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID458  ,Interrupt ID458   Priority/Priority Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID457  ,Interrupt ID457  Priority/Priority Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID456  ,Interrupt ID456   Priority/Priority Byte Offset 456 "
group.long 0x5CC++0x03
line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hexmask.long.byte 0x00 24.--31. 1. " INTID463  ,Interrupt ID463  Priority/Priority Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID462  ,Interrupt ID462   Priority/Priority Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID461  ,Interrupt ID461  Priority/Priority Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID460  ,Interrupt ID460   Priority/Priority Byte Offset 460 "
group.long 0x5D0++0x03
line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hexmask.long.byte 0x00 24.--31. 1. " INTID467  ,Interrupt ID467  Priority/Priority Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID466  ,Interrupt ID466   Priority/Priority Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID465  ,Interrupt ID465  Priority/Priority Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID464  ,Interrupt ID464   Priority/Priority Byte Offset 464 "
group.long 0x5D4++0x03
line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hexmask.long.byte 0x00 24.--31. 1. " INTID471  ,Interrupt ID471  Priority/Priority Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID470  ,Interrupt ID470   Priority/Priority Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID469  ,Interrupt ID469  Priority/Priority Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID468  ,Interrupt ID468   Priority/Priority Byte Offset 468 "
group.long 0x5D8++0x03
line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hexmask.long.byte 0x00 24.--31. 1. " INTID475  ,Interrupt ID475  Priority/Priority Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID474  ,Interrupt ID474   Priority/Priority Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID473  ,Interrupt ID473  Priority/Priority Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID472  ,Interrupt ID472   Priority/Priority Byte Offset 472 "
group.long 0x5DC++0x03
line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
hexmask.long.byte 0x00 24.--31. 1. " INTID479  ,Interrupt ID479  Priority/Priority Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID478  ,Interrupt ID478   Priority/Priority Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID477  ,Interrupt ID477  Priority/Priority Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID476  ,Interrupt ID476   Priority/Priority Byte Offset 476 "
else
hgroup.long 0x5C0++0x03
hide.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112"
hgroup.long 0x5C4++0x03
hide.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113"
hgroup.long 0x5C8++0x03
hide.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114"
hgroup.long 0x5CC++0x03
hide.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115"
hgroup.long 0x5D0++0x03
hide.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116"
hgroup.long 0x5D4++0x03
hide.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117"
hgroup.long 0x5D8++0x03
hide.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118"
hgroup.long 0x5DC++0x03
hide.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x5E0++0x03
line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hexmask.long.byte 0x00 24.--31. 1. " INTID483  ,Interrupt ID483  Priority/Priority Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID482  ,Interrupt ID482   Priority/Priority Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID481  ,Interrupt ID481  Priority/Priority Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID480  ,Interrupt ID480   Priority/Priority Byte Offset 480 "
group.long 0x5E4++0x03
line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hexmask.long.byte 0x00 24.--31. 1. " INTID487  ,Interrupt ID487  Priority/Priority Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID486  ,Interrupt ID486   Priority/Priority Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID485  ,Interrupt ID485  Priority/Priority Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID484  ,Interrupt ID484   Priority/Priority Byte Offset 484 "
group.long 0x5E8++0x03
line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hexmask.long.byte 0x00 24.--31. 1. " INTID491  ,Interrupt ID491  Priority/Priority Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID490  ,Interrupt ID490   Priority/Priority Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID489  ,Interrupt ID489  Priority/Priority Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID488  ,Interrupt ID488   Priority/Priority Byte Offset 488 "
group.long 0x5EC++0x03
line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hexmask.long.byte 0x00 24.--31. 1. " INTID495  ,Interrupt ID495  Priority/Priority Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID494  ,Interrupt ID494   Priority/Priority Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID493  ,Interrupt ID493  Priority/Priority Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID492  ,Interrupt ID492   Priority/Priority Byte Offset 492 "
group.long 0x5F0++0x03
line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hexmask.long.byte 0x00 24.--31. 1. " INTID499  ,Interrupt ID499  Priority/Priority Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID498  ,Interrupt ID498   Priority/Priority Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID497  ,Interrupt ID497  Priority/Priority Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID496  ,Interrupt ID496   Priority/Priority Byte Offset 496 "
group.long 0x5F4++0x03
line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hexmask.long.byte 0x00 24.--31. 1. " INTID503  ,Interrupt ID503  Priority/Priority Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID502  ,Interrupt ID502   Priority/Priority Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID501  ,Interrupt ID501  Priority/Priority Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID500  ,Interrupt ID500   Priority/Priority Byte Offset 500 "
group.long 0x5F8++0x03
line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hexmask.long.byte 0x00 24.--31. 1. " INTID507  ,Interrupt ID507  Priority/Priority Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID506  ,Interrupt ID506   Priority/Priority Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID505  ,Interrupt ID505  Priority/Priority Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID504  ,Interrupt ID504   Priority/Priority Byte Offset 504 "
group.long 0x5FC++0x03
line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
hexmask.long.byte 0x00 24.--31. 1. " INTID511  ,Interrupt ID511  Priority/Priority Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID510  ,Interrupt ID510   Priority/Priority Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID509  ,Interrupt ID509  Priority/Priority Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID508  ,Interrupt ID508   Priority/Priority Byte Offset 508 "
else
hgroup.long 0x5E0++0x03
hide.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120"
hgroup.long 0x5E4++0x03
hide.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121"
hgroup.long 0x5E8++0x03
hide.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122"
hgroup.long 0x5EC++0x03
hide.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123"
hgroup.long 0x5F0++0x03
hide.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124"
hgroup.long 0x5F4++0x03
hide.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125"
hgroup.long 0x5F8++0x03
hide.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126"
hgroup.long 0x5FC++0x03
hide.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0x600++0x03
line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hexmask.long.byte 0x00 24.--31. 1. " INTID515  ,Interrupt ID515  Priority/Priority Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID514  ,Interrupt ID514   Priority/Priority Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID513  ,Interrupt ID513  Priority/Priority Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID512  ,Interrupt ID512   Priority/Priority Byte Offset 512 "
group.long 0x604++0x03
line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hexmask.long.byte 0x00 24.--31. 1. " INTID519  ,Interrupt ID519  Priority/Priority Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID518  ,Interrupt ID518   Priority/Priority Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID517  ,Interrupt ID517  Priority/Priority Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID516  ,Interrupt ID516   Priority/Priority Byte Offset 516 "
group.long 0x608++0x03
line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hexmask.long.byte 0x00 24.--31. 1. " INTID523  ,Interrupt ID523  Priority/Priority Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID522  ,Interrupt ID522   Priority/Priority Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID521  ,Interrupt ID521  Priority/Priority Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID520  ,Interrupt ID520   Priority/Priority Byte Offset 520 "
group.long 0x60C++0x03
line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hexmask.long.byte 0x00 24.--31. 1. " INTID527  ,Interrupt ID527  Priority/Priority Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID526  ,Interrupt ID526   Priority/Priority Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID525  ,Interrupt ID525  Priority/Priority Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID524  ,Interrupt ID524   Priority/Priority Byte Offset 524 "
group.long 0x610++0x03
line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hexmask.long.byte 0x00 24.--31. 1. " INTID531  ,Interrupt ID531  Priority/Priority Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID530  ,Interrupt ID530   Priority/Priority Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID529  ,Interrupt ID529  Priority/Priority Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID528  ,Interrupt ID528   Priority/Priority Byte Offset 528 "
group.long 0x614++0x03
line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hexmask.long.byte 0x00 24.--31. 1. " INTID535  ,Interrupt ID535  Priority/Priority Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID534  ,Interrupt ID534   Priority/Priority Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID533  ,Interrupt ID533  Priority/Priority Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID532  ,Interrupt ID532   Priority/Priority Byte Offset 532 "
group.long 0x618++0x03
line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hexmask.long.byte 0x00 24.--31. 1. " INTID539  ,Interrupt ID539  Priority/Priority Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID538  ,Interrupt ID538   Priority/Priority Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID537  ,Interrupt ID537  Priority/Priority Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID536  ,Interrupt ID536   Priority/Priority Byte Offset 536 "
group.long 0x61C++0x03
line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
hexmask.long.byte 0x00 24.--31. 1. " INTID543  ,Interrupt ID543  Priority/Priority Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID542  ,Interrupt ID542   Priority/Priority Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID541  ,Interrupt ID541  Priority/Priority Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID540  ,Interrupt ID540   Priority/Priority Byte Offset 540 "
else
hgroup.long 0x600++0x03
hide.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128"
hgroup.long 0x604++0x03
hide.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129"
hgroup.long 0x608++0x03
hide.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130"
hgroup.long 0x60C++0x03
hide.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131"
hgroup.long 0x610++0x03
hide.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132"
hgroup.long 0x614++0x03
hide.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133"
hgroup.long 0x618++0x03
hide.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134"
hgroup.long 0x61C++0x03
hide.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0x620++0x03
line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hexmask.long.byte 0x00 24.--31. 1. " INTID547  ,Interrupt ID547  Priority/Priority Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID546  ,Interrupt ID546   Priority/Priority Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID545  ,Interrupt ID545  Priority/Priority Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID544  ,Interrupt ID544   Priority/Priority Byte Offset 544 "
group.long 0x624++0x03
line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hexmask.long.byte 0x00 24.--31. 1. " INTID551  ,Interrupt ID551  Priority/Priority Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID550  ,Interrupt ID550   Priority/Priority Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID549  ,Interrupt ID549  Priority/Priority Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID548  ,Interrupt ID548   Priority/Priority Byte Offset 548 "
group.long 0x628++0x03
line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hexmask.long.byte 0x00 24.--31. 1. " INTID555  ,Interrupt ID555  Priority/Priority Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID554  ,Interrupt ID554   Priority/Priority Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID553  ,Interrupt ID553  Priority/Priority Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID552  ,Interrupt ID552   Priority/Priority Byte Offset 552 "
group.long 0x62C++0x03
line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hexmask.long.byte 0x00 24.--31. 1. " INTID559  ,Interrupt ID559  Priority/Priority Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID558  ,Interrupt ID558   Priority/Priority Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID557  ,Interrupt ID557  Priority/Priority Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID556  ,Interrupt ID556   Priority/Priority Byte Offset 556 "
group.long 0x630++0x03
line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hexmask.long.byte 0x00 24.--31. 1. " INTID563  ,Interrupt ID563  Priority/Priority Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID562  ,Interrupt ID562   Priority/Priority Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID561  ,Interrupt ID561  Priority/Priority Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID560  ,Interrupt ID560   Priority/Priority Byte Offset 560 "
group.long 0x634++0x03
line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hexmask.long.byte 0x00 24.--31. 1. " INTID567  ,Interrupt ID567  Priority/Priority Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID566  ,Interrupt ID566   Priority/Priority Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID565  ,Interrupt ID565  Priority/Priority Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID564  ,Interrupt ID564   Priority/Priority Byte Offset 564 "
group.long 0x638++0x03
line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hexmask.long.byte 0x00 24.--31. 1. " INTID571  ,Interrupt ID571  Priority/Priority Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID570  ,Interrupt ID570   Priority/Priority Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID569  ,Interrupt ID569  Priority/Priority Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID568  ,Interrupt ID568   Priority/Priority Byte Offset 568 "
group.long 0x63C++0x03
line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
hexmask.long.byte 0x00 24.--31. 1. " INTID575  ,Interrupt ID575  Priority/Priority Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID574  ,Interrupt ID574   Priority/Priority Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID573  ,Interrupt ID573  Priority/Priority Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID572  ,Interrupt ID572   Priority/Priority Byte Offset 572 "
else
hgroup.long 0x620++0x03
hide.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136"
hgroup.long 0x624++0x03
hide.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137"
hgroup.long 0x628++0x03
hide.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138"
hgroup.long 0x62C++0x03
hide.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139"
hgroup.long 0x630++0x03
hide.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140"
hgroup.long 0x634++0x03
hide.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141"
hgroup.long 0x638++0x03
hide.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142"
hgroup.long 0x63C++0x03
hide.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0x640++0x03
line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hexmask.long.byte 0x00 24.--31. 1. " INTID579  ,Interrupt ID579  Priority/Priority Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID578  ,Interrupt ID578   Priority/Priority Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID577  ,Interrupt ID577  Priority/Priority Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID576  ,Interrupt ID576   Priority/Priority Byte Offset 576 "
group.long 0x644++0x03
line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hexmask.long.byte 0x00 24.--31. 1. " INTID583  ,Interrupt ID583  Priority/Priority Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID582  ,Interrupt ID582   Priority/Priority Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID581  ,Interrupt ID581  Priority/Priority Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID580  ,Interrupt ID580   Priority/Priority Byte Offset 580 "
group.long 0x648++0x03
line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hexmask.long.byte 0x00 24.--31. 1. " INTID587  ,Interrupt ID587  Priority/Priority Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID586  ,Interrupt ID586   Priority/Priority Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID585  ,Interrupt ID585  Priority/Priority Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID584  ,Interrupt ID584   Priority/Priority Byte Offset 584 "
group.long 0x64C++0x03
line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hexmask.long.byte 0x00 24.--31. 1. " INTID591  ,Interrupt ID591  Priority/Priority Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID590  ,Interrupt ID590   Priority/Priority Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID589  ,Interrupt ID589  Priority/Priority Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID588  ,Interrupt ID588   Priority/Priority Byte Offset 588 "
group.long 0x650++0x03
line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hexmask.long.byte 0x00 24.--31. 1. " INTID595  ,Interrupt ID595  Priority/Priority Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID594  ,Interrupt ID594   Priority/Priority Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID593  ,Interrupt ID593  Priority/Priority Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID592  ,Interrupt ID592   Priority/Priority Byte Offset 592 "
group.long 0x654++0x03
line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hexmask.long.byte 0x00 24.--31. 1. " INTID599  ,Interrupt ID599  Priority/Priority Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID598  ,Interrupt ID598   Priority/Priority Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID597  ,Interrupt ID597  Priority/Priority Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID596  ,Interrupt ID596   Priority/Priority Byte Offset 596 "
group.long 0x658++0x03
line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hexmask.long.byte 0x00 24.--31. 1. " INTID603  ,Interrupt ID603  Priority/Priority Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID602  ,Interrupt ID602   Priority/Priority Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID601  ,Interrupt ID601  Priority/Priority Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID600  ,Interrupt ID600   Priority/Priority Byte Offset 600 "
group.long 0x65C++0x03
line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
hexmask.long.byte 0x00 24.--31. 1. " INTID607  ,Interrupt ID607  Priority/Priority Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID606  ,Interrupt ID606   Priority/Priority Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID605  ,Interrupt ID605  Priority/Priority Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID604  ,Interrupt ID604   Priority/Priority Byte Offset 604 "
else
hgroup.long 0x640++0x03
hide.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144"
hgroup.long 0x644++0x03
hide.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145"
hgroup.long 0x648++0x03
hide.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146"
hgroup.long 0x64C++0x03
hide.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147"
hgroup.long 0x650++0x03
hide.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148"
hgroup.long 0x654++0x03
hide.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149"
hgroup.long 0x658++0x03
hide.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150"
hgroup.long 0x65C++0x03
hide.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0x660++0x03
line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hexmask.long.byte 0x00 24.--31. 1. " INTID611  ,Interrupt ID611  Priority/Priority Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID610  ,Interrupt ID610   Priority/Priority Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID609  ,Interrupt ID609  Priority/Priority Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID608  ,Interrupt ID608   Priority/Priority Byte Offset 608 "
group.long 0x664++0x03
line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hexmask.long.byte 0x00 24.--31. 1. " INTID615  ,Interrupt ID615  Priority/Priority Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID614  ,Interrupt ID614   Priority/Priority Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID613  ,Interrupt ID613  Priority/Priority Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID612  ,Interrupt ID612   Priority/Priority Byte Offset 612 "
group.long 0x668++0x03
line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hexmask.long.byte 0x00 24.--31. 1. " INTID619  ,Interrupt ID619  Priority/Priority Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID618  ,Interrupt ID618   Priority/Priority Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID617  ,Interrupt ID617  Priority/Priority Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID616  ,Interrupt ID616   Priority/Priority Byte Offset 616 "
group.long 0x66C++0x03
line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hexmask.long.byte 0x00 24.--31. 1. " INTID623  ,Interrupt ID623  Priority/Priority Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID622  ,Interrupt ID622   Priority/Priority Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID621  ,Interrupt ID621  Priority/Priority Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID620  ,Interrupt ID620   Priority/Priority Byte Offset 620 "
group.long 0x670++0x03
line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hexmask.long.byte 0x00 24.--31. 1. " INTID627  ,Interrupt ID627  Priority/Priority Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID626  ,Interrupt ID626   Priority/Priority Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID625  ,Interrupt ID625  Priority/Priority Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID624  ,Interrupt ID624   Priority/Priority Byte Offset 624 "
group.long 0x674++0x03
line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hexmask.long.byte 0x00 24.--31. 1. " INTID631  ,Interrupt ID631  Priority/Priority Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID630  ,Interrupt ID630   Priority/Priority Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID629  ,Interrupt ID629  Priority/Priority Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID628  ,Interrupt ID628   Priority/Priority Byte Offset 628 "
group.long 0x678++0x03
line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hexmask.long.byte 0x00 24.--31. 1. " INTID635  ,Interrupt ID635  Priority/Priority Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID634  ,Interrupt ID634   Priority/Priority Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID633  ,Interrupt ID633  Priority/Priority Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID632  ,Interrupt ID632   Priority/Priority Byte Offset 632 "
group.long 0x67C++0x03
line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
hexmask.long.byte 0x00 24.--31. 1. " INTID639  ,Interrupt ID639  Priority/Priority Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID638  ,Interrupt ID638   Priority/Priority Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID637  ,Interrupt ID637  Priority/Priority Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID636  ,Interrupt ID636   Priority/Priority Byte Offset 636 "
else
hgroup.long 0x660++0x03
hide.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152"
hgroup.long 0x664++0x03
hide.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153"
hgroup.long 0x668++0x03
hide.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154"
hgroup.long 0x66C++0x03
hide.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155"
hgroup.long 0x670++0x03
hide.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156"
hgroup.long 0x674++0x03
hide.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157"
hgroup.long 0x678++0x03
hide.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158"
hgroup.long 0x67C++0x03
hide.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0x680++0x03
line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hexmask.long.byte 0x00 24.--31. 1. " INTID643  ,Interrupt ID643  Priority/Priority Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID642  ,Interrupt ID642   Priority/Priority Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID641  ,Interrupt ID641  Priority/Priority Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID640  ,Interrupt ID640   Priority/Priority Byte Offset 640 "
group.long 0x684++0x03
line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hexmask.long.byte 0x00 24.--31. 1. " INTID647  ,Interrupt ID647  Priority/Priority Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID646  ,Interrupt ID646   Priority/Priority Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID645  ,Interrupt ID645  Priority/Priority Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID644  ,Interrupt ID644   Priority/Priority Byte Offset 644 "
group.long 0x688++0x03
line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hexmask.long.byte 0x00 24.--31. 1. " INTID651  ,Interrupt ID651  Priority/Priority Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID650  ,Interrupt ID650   Priority/Priority Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID649  ,Interrupt ID649  Priority/Priority Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID648  ,Interrupt ID648   Priority/Priority Byte Offset 648 "
group.long 0x68C++0x03
line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hexmask.long.byte 0x00 24.--31. 1. " INTID655  ,Interrupt ID655  Priority/Priority Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID654  ,Interrupt ID654   Priority/Priority Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID653  ,Interrupt ID653  Priority/Priority Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID652  ,Interrupt ID652   Priority/Priority Byte Offset 652 "
group.long 0x690++0x03
line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hexmask.long.byte 0x00 24.--31. 1. " INTID659  ,Interrupt ID659  Priority/Priority Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID658  ,Interrupt ID658   Priority/Priority Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID657  ,Interrupt ID657  Priority/Priority Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID656  ,Interrupt ID656   Priority/Priority Byte Offset 656 "
group.long 0x694++0x03
line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hexmask.long.byte 0x00 24.--31. 1. " INTID663  ,Interrupt ID663  Priority/Priority Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID662  ,Interrupt ID662   Priority/Priority Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID661  ,Interrupt ID661  Priority/Priority Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID660  ,Interrupt ID660   Priority/Priority Byte Offset 660 "
group.long 0x698++0x03
line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hexmask.long.byte 0x00 24.--31. 1. " INTID667  ,Interrupt ID667  Priority/Priority Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID666  ,Interrupt ID666   Priority/Priority Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID665  ,Interrupt ID665  Priority/Priority Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID664  ,Interrupt ID664   Priority/Priority Byte Offset 664 "
group.long 0x69C++0x03
line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
hexmask.long.byte 0x00 24.--31. 1. " INTID671  ,Interrupt ID671  Priority/Priority Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID670  ,Interrupt ID670   Priority/Priority Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID669  ,Interrupt ID669  Priority/Priority Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID668  ,Interrupt ID668   Priority/Priority Byte Offset 668 "
else
hgroup.long 0x680++0x03
hide.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160"
hgroup.long 0x684++0x03
hide.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161"
hgroup.long 0x688++0x03
hide.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162"
hgroup.long 0x68C++0x03
hide.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163"
hgroup.long 0x690++0x03
hide.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164"
hgroup.long 0x694++0x03
hide.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165"
hgroup.long 0x698++0x03
hide.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166"
hgroup.long 0x69C++0x03
hide.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0x6A0++0x03
line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hexmask.long.byte 0x00 24.--31. 1. " INTID675  ,Interrupt ID675  Priority/Priority Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID674  ,Interrupt ID674   Priority/Priority Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID673  ,Interrupt ID673  Priority/Priority Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID672  ,Interrupt ID672   Priority/Priority Byte Offset 672 "
group.long 0x6A4++0x03
line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hexmask.long.byte 0x00 24.--31. 1. " INTID679  ,Interrupt ID679  Priority/Priority Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID678  ,Interrupt ID678   Priority/Priority Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID677  ,Interrupt ID677  Priority/Priority Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID676  ,Interrupt ID676   Priority/Priority Byte Offset 676 "
group.long 0x6A8++0x03
line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hexmask.long.byte 0x00 24.--31. 1. " INTID683  ,Interrupt ID683  Priority/Priority Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID682  ,Interrupt ID682   Priority/Priority Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID681  ,Interrupt ID681  Priority/Priority Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID680  ,Interrupt ID680   Priority/Priority Byte Offset 680 "
group.long 0x6AC++0x03
line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hexmask.long.byte 0x00 24.--31. 1. " INTID687  ,Interrupt ID687  Priority/Priority Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID686  ,Interrupt ID686   Priority/Priority Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID685  ,Interrupt ID685  Priority/Priority Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID684  ,Interrupt ID684   Priority/Priority Byte Offset 684 "
group.long 0x6B0++0x03
line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hexmask.long.byte 0x00 24.--31. 1. " INTID691  ,Interrupt ID691  Priority/Priority Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID690  ,Interrupt ID690   Priority/Priority Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID689  ,Interrupt ID689  Priority/Priority Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID688  ,Interrupt ID688   Priority/Priority Byte Offset 688 "
group.long 0x6B4++0x03
line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hexmask.long.byte 0x00 24.--31. 1. " INTID695  ,Interrupt ID695  Priority/Priority Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID694  ,Interrupt ID694   Priority/Priority Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID693  ,Interrupt ID693  Priority/Priority Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID692  ,Interrupt ID692   Priority/Priority Byte Offset 692 "
group.long 0x6B8++0x03
line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hexmask.long.byte 0x00 24.--31. 1. " INTID699  ,Interrupt ID699  Priority/Priority Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID698  ,Interrupt ID698   Priority/Priority Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID697  ,Interrupt ID697  Priority/Priority Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID696  ,Interrupt ID696   Priority/Priority Byte Offset 696 "
group.long 0x6BC++0x03
line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
hexmask.long.byte 0x00 24.--31. 1. " INTID703  ,Interrupt ID703  Priority/Priority Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID702  ,Interrupt ID702   Priority/Priority Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID701  ,Interrupt ID701  Priority/Priority Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID700  ,Interrupt ID700   Priority/Priority Byte Offset 700 "
else
hgroup.long 0x6A0++0x03
hide.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168"
hgroup.long 0x6A4++0x03
hide.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169"
hgroup.long 0x6A8++0x03
hide.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170"
hgroup.long 0x6AC++0x03
hide.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171"
hgroup.long 0x6B0++0x03
hide.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172"
hgroup.long 0x6B4++0x03
hide.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173"
hgroup.long 0x6B8++0x03
hide.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174"
hgroup.long 0x6BC++0x03
hide.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0x6C0++0x03
line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hexmask.long.byte 0x00 24.--31. 1. " INTID707  ,Interrupt ID707  Priority/Priority Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID706  ,Interrupt ID706   Priority/Priority Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID705  ,Interrupt ID705  Priority/Priority Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID704  ,Interrupt ID704   Priority/Priority Byte Offset 704 "
group.long 0x6C4++0x03
line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hexmask.long.byte 0x00 24.--31. 1. " INTID711  ,Interrupt ID711  Priority/Priority Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID710  ,Interrupt ID710   Priority/Priority Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID709  ,Interrupt ID709  Priority/Priority Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID708  ,Interrupt ID708   Priority/Priority Byte Offset 708 "
group.long 0x6C8++0x03
line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hexmask.long.byte 0x00 24.--31. 1. " INTID715  ,Interrupt ID715  Priority/Priority Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID714  ,Interrupt ID714   Priority/Priority Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID713  ,Interrupt ID713  Priority/Priority Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID712  ,Interrupt ID712   Priority/Priority Byte Offset 712 "
group.long 0x6CC++0x03
line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hexmask.long.byte 0x00 24.--31. 1. " INTID719  ,Interrupt ID719  Priority/Priority Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID718  ,Interrupt ID718   Priority/Priority Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID717  ,Interrupt ID717  Priority/Priority Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID716  ,Interrupt ID716   Priority/Priority Byte Offset 716 "
group.long 0x6D0++0x03
line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hexmask.long.byte 0x00 24.--31. 1. " INTID723  ,Interrupt ID723  Priority/Priority Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID722  ,Interrupt ID722   Priority/Priority Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID721  ,Interrupt ID721  Priority/Priority Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID720  ,Interrupt ID720   Priority/Priority Byte Offset 720 "
group.long 0x6D4++0x03
line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hexmask.long.byte 0x00 24.--31. 1. " INTID727  ,Interrupt ID727  Priority/Priority Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID726  ,Interrupt ID726   Priority/Priority Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID725  ,Interrupt ID725  Priority/Priority Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID724  ,Interrupt ID724   Priority/Priority Byte Offset 724 "
group.long 0x6D8++0x03
line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hexmask.long.byte 0x00 24.--31. 1. " INTID731  ,Interrupt ID731  Priority/Priority Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID730  ,Interrupt ID730   Priority/Priority Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID729  ,Interrupt ID729  Priority/Priority Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID728  ,Interrupt ID728   Priority/Priority Byte Offset 728 "
group.long 0x6DC++0x03
line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
hexmask.long.byte 0x00 24.--31. 1. " INTID735  ,Interrupt ID735  Priority/Priority Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID734  ,Interrupt ID734   Priority/Priority Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID733  ,Interrupt ID733  Priority/Priority Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID732  ,Interrupt ID732   Priority/Priority Byte Offset 732 "
else
hgroup.long 0x6C0++0x03
hide.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176"
hgroup.long 0x6C4++0x03
hide.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177"
hgroup.long 0x6C8++0x03
hide.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178"
hgroup.long 0x6CC++0x03
hide.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179"
hgroup.long 0x6D0++0x03
hide.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180"
hgroup.long 0x6D4++0x03
hide.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181"
hgroup.long 0x6D8++0x03
hide.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182"
hgroup.long 0x6DC++0x03
hide.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0x6E0++0x03
line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hexmask.long.byte 0x00 24.--31. 1. " INTID739  ,Interrupt ID739  Priority/Priority Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID738  ,Interrupt ID738   Priority/Priority Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID737  ,Interrupt ID737  Priority/Priority Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID736  ,Interrupt ID736   Priority/Priority Byte Offset 736 "
group.long 0x6E4++0x03
line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hexmask.long.byte 0x00 24.--31. 1. " INTID743  ,Interrupt ID743  Priority/Priority Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID742  ,Interrupt ID742   Priority/Priority Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID741  ,Interrupt ID741  Priority/Priority Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID740  ,Interrupt ID740   Priority/Priority Byte Offset 740 "
group.long 0x6E8++0x03
line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hexmask.long.byte 0x00 24.--31. 1. " INTID747  ,Interrupt ID747  Priority/Priority Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID746  ,Interrupt ID746   Priority/Priority Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID745  ,Interrupt ID745  Priority/Priority Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID744  ,Interrupt ID744   Priority/Priority Byte Offset 744 "
group.long 0x6EC++0x03
line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hexmask.long.byte 0x00 24.--31. 1. " INTID751  ,Interrupt ID751  Priority/Priority Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID750  ,Interrupt ID750   Priority/Priority Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID749  ,Interrupt ID749  Priority/Priority Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID748  ,Interrupt ID748   Priority/Priority Byte Offset 748 "
group.long 0x6F0++0x03
line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hexmask.long.byte 0x00 24.--31. 1. " INTID755  ,Interrupt ID755  Priority/Priority Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID754  ,Interrupt ID754   Priority/Priority Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID753  ,Interrupt ID753  Priority/Priority Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID752  ,Interrupt ID752   Priority/Priority Byte Offset 752 "
group.long 0x6F4++0x03
line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hexmask.long.byte 0x00 24.--31. 1. " INTID759  ,Interrupt ID759  Priority/Priority Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID758  ,Interrupt ID758   Priority/Priority Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID757  ,Interrupt ID757  Priority/Priority Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID756  ,Interrupt ID756   Priority/Priority Byte Offset 756 "
group.long 0x6F8++0x03
line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hexmask.long.byte 0x00 24.--31. 1. " INTID763  ,Interrupt ID763  Priority/Priority Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID762  ,Interrupt ID762   Priority/Priority Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID761  ,Interrupt ID761  Priority/Priority Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID760  ,Interrupt ID760   Priority/Priority Byte Offset 760 "
group.long 0x6FC++0x03
line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
hexmask.long.byte 0x00 24.--31. 1. " INTID767  ,Interrupt ID767  Priority/Priority Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID766  ,Interrupt ID766   Priority/Priority Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID765  ,Interrupt ID765  Priority/Priority Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID764  ,Interrupt ID764   Priority/Priority Byte Offset 764 "
else
hgroup.long 0x6E0++0x03
hide.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184"
hgroup.long 0x6E4++0x03
hide.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185"
hgroup.long 0x6E8++0x03
hide.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186"
hgroup.long 0x6EC++0x03
hide.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187"
hgroup.long 0x6F0++0x03
hide.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188"
hgroup.long 0x6F4++0x03
hide.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189"
hgroup.long 0x6F8++0x03
hide.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190"
hgroup.long 0x6FC++0x03
hide.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0x700++0x03
line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hexmask.long.byte 0x00 24.--31. 1. " INTID771  ,Interrupt ID771  Priority/Priority Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID770  ,Interrupt ID770   Priority/Priority Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID769  ,Interrupt ID769  Priority/Priority Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID768  ,Interrupt ID768   Priority/Priority Byte Offset 768 "
group.long 0x704++0x03
line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hexmask.long.byte 0x00 24.--31. 1. " INTID775  ,Interrupt ID775  Priority/Priority Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID774  ,Interrupt ID774   Priority/Priority Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID773  ,Interrupt ID773  Priority/Priority Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID772  ,Interrupt ID772   Priority/Priority Byte Offset 772 "
group.long 0x708++0x03
line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hexmask.long.byte 0x00 24.--31. 1. " INTID779  ,Interrupt ID779  Priority/Priority Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID778  ,Interrupt ID778   Priority/Priority Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID777  ,Interrupt ID777  Priority/Priority Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID776  ,Interrupt ID776   Priority/Priority Byte Offset 776 "
group.long 0x70C++0x03
line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hexmask.long.byte 0x00 24.--31. 1. " INTID783  ,Interrupt ID783  Priority/Priority Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID782  ,Interrupt ID782   Priority/Priority Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID781  ,Interrupt ID781  Priority/Priority Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID780  ,Interrupt ID780   Priority/Priority Byte Offset 780 "
group.long 0x710++0x03
line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hexmask.long.byte 0x00 24.--31. 1. " INTID787  ,Interrupt ID787  Priority/Priority Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID786  ,Interrupt ID786   Priority/Priority Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID785  ,Interrupt ID785  Priority/Priority Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID784  ,Interrupt ID784   Priority/Priority Byte Offset 784 "
group.long 0x714++0x03
line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hexmask.long.byte 0x00 24.--31. 1. " INTID791  ,Interrupt ID791  Priority/Priority Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID790  ,Interrupt ID790   Priority/Priority Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID789  ,Interrupt ID789  Priority/Priority Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID788  ,Interrupt ID788   Priority/Priority Byte Offset 788 "
group.long 0x718++0x03
line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hexmask.long.byte 0x00 24.--31. 1. " INTID795  ,Interrupt ID795  Priority/Priority Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID794  ,Interrupt ID794   Priority/Priority Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID793  ,Interrupt ID793  Priority/Priority Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID792  ,Interrupt ID792   Priority/Priority Byte Offset 792 "
group.long 0x71C++0x03
line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
hexmask.long.byte 0x00 24.--31. 1. " INTID799  ,Interrupt ID799  Priority/Priority Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID798  ,Interrupt ID798   Priority/Priority Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID797  ,Interrupt ID797  Priority/Priority Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID796  ,Interrupt ID796   Priority/Priority Byte Offset 796 "
else
hgroup.long 0x700++0x03
hide.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192"
hgroup.long 0x704++0x03
hide.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193"
hgroup.long 0x708++0x03
hide.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194"
hgroup.long 0x70C++0x03
hide.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195"
hgroup.long 0x710++0x03
hide.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196"
hgroup.long 0x714++0x03
hide.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197"
hgroup.long 0x718++0x03
hide.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198"
hgroup.long 0x71C++0x03
hide.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0x720++0x03
line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hexmask.long.byte 0x00 24.--31. 1. " INTID803  ,Interrupt ID803  Priority/Priority Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID802  ,Interrupt ID802   Priority/Priority Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID801  ,Interrupt ID801  Priority/Priority Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID800  ,Interrupt ID800   Priority/Priority Byte Offset 800 "
group.long 0x724++0x03
line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hexmask.long.byte 0x00 24.--31. 1. " INTID807  ,Interrupt ID807  Priority/Priority Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID806  ,Interrupt ID806   Priority/Priority Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID805  ,Interrupt ID805  Priority/Priority Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID804  ,Interrupt ID804   Priority/Priority Byte Offset 804 "
group.long 0x728++0x03
line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hexmask.long.byte 0x00 24.--31. 1. " INTID811  ,Interrupt ID811  Priority/Priority Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID810  ,Interrupt ID810   Priority/Priority Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID809  ,Interrupt ID809  Priority/Priority Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID808  ,Interrupt ID808   Priority/Priority Byte Offset 808 "
group.long 0x72C++0x03
line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hexmask.long.byte 0x00 24.--31. 1. " INTID815  ,Interrupt ID815  Priority/Priority Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID814  ,Interrupt ID814   Priority/Priority Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID813  ,Interrupt ID813  Priority/Priority Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID812  ,Interrupt ID812   Priority/Priority Byte Offset 812 "
group.long 0x730++0x03
line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hexmask.long.byte 0x00 24.--31. 1. " INTID819  ,Interrupt ID819  Priority/Priority Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID818  ,Interrupt ID818   Priority/Priority Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID817  ,Interrupt ID817  Priority/Priority Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID816  ,Interrupt ID816   Priority/Priority Byte Offset 816 "
group.long 0x734++0x03
line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hexmask.long.byte 0x00 24.--31. 1. " INTID823  ,Interrupt ID823  Priority/Priority Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID822  ,Interrupt ID822   Priority/Priority Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID821  ,Interrupt ID821  Priority/Priority Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID820  ,Interrupt ID820   Priority/Priority Byte Offset 820 "
group.long 0x738++0x03
line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hexmask.long.byte 0x00 24.--31. 1. " INTID827  ,Interrupt ID827  Priority/Priority Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID826  ,Interrupt ID826   Priority/Priority Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID825  ,Interrupt ID825  Priority/Priority Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID824  ,Interrupt ID824   Priority/Priority Byte Offset 824 "
group.long 0x73C++0x03
line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
hexmask.long.byte 0x00 24.--31. 1. " INTID831  ,Interrupt ID831  Priority/Priority Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID830  ,Interrupt ID830   Priority/Priority Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID829  ,Interrupt ID829  Priority/Priority Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID828  ,Interrupt ID828   Priority/Priority Byte Offset 828 "
else
hgroup.long 0x720++0x03
hide.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200"
hgroup.long 0x724++0x03
hide.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201"
hgroup.long 0x728++0x03
hide.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202"
hgroup.long 0x72C++0x03
hide.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203"
hgroup.long 0x730++0x03
hide.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204"
hgroup.long 0x734++0x03
hide.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205"
hgroup.long 0x738++0x03
hide.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206"
hgroup.long 0x73C++0x03
hide.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0x740++0x03
line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hexmask.long.byte 0x00 24.--31. 1. " INTID835  ,Interrupt ID835  Priority/Priority Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID834  ,Interrupt ID834   Priority/Priority Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID833  ,Interrupt ID833  Priority/Priority Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID832  ,Interrupt ID832   Priority/Priority Byte Offset 832 "
group.long 0x744++0x03
line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hexmask.long.byte 0x00 24.--31. 1. " INTID839  ,Interrupt ID839  Priority/Priority Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID838  ,Interrupt ID838   Priority/Priority Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID837  ,Interrupt ID837  Priority/Priority Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID836  ,Interrupt ID836   Priority/Priority Byte Offset 836 "
group.long 0x748++0x03
line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hexmask.long.byte 0x00 24.--31. 1. " INTID843  ,Interrupt ID843  Priority/Priority Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID842  ,Interrupt ID842   Priority/Priority Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID841  ,Interrupt ID841  Priority/Priority Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID840  ,Interrupt ID840   Priority/Priority Byte Offset 840 "
group.long 0x74C++0x03
line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hexmask.long.byte 0x00 24.--31. 1. " INTID847  ,Interrupt ID847  Priority/Priority Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID846  ,Interrupt ID846   Priority/Priority Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID845  ,Interrupt ID845  Priority/Priority Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID844  ,Interrupt ID844   Priority/Priority Byte Offset 844 "
group.long 0x750++0x03
line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hexmask.long.byte 0x00 24.--31. 1. " INTID851  ,Interrupt ID851  Priority/Priority Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID850  ,Interrupt ID850   Priority/Priority Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID849  ,Interrupt ID849  Priority/Priority Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID848  ,Interrupt ID848   Priority/Priority Byte Offset 848 "
group.long 0x754++0x03
line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hexmask.long.byte 0x00 24.--31. 1. " INTID855  ,Interrupt ID855  Priority/Priority Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID854  ,Interrupt ID854   Priority/Priority Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID853  ,Interrupt ID853  Priority/Priority Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID852  ,Interrupt ID852   Priority/Priority Byte Offset 852 "
group.long 0x758++0x03
line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hexmask.long.byte 0x00 24.--31. 1. " INTID859  ,Interrupt ID859  Priority/Priority Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID858  ,Interrupt ID858   Priority/Priority Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID857  ,Interrupt ID857  Priority/Priority Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID856  ,Interrupt ID856   Priority/Priority Byte Offset 856 "
group.long 0x75C++0x03
line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
hexmask.long.byte 0x00 24.--31. 1. " INTID863  ,Interrupt ID863  Priority/Priority Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID862  ,Interrupt ID862   Priority/Priority Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID861  ,Interrupt ID861  Priority/Priority Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID860  ,Interrupt ID860   Priority/Priority Byte Offset 860 "
else
hgroup.long 0x740++0x03
hide.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208"
hgroup.long 0x744++0x03
hide.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209"
hgroup.long 0x748++0x03
hide.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210"
hgroup.long 0x74C++0x03
hide.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211"
hgroup.long 0x750++0x03
hide.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212"
hgroup.long 0x754++0x03
hide.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213"
hgroup.long 0x758++0x03
hide.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214"
hgroup.long 0x75C++0x03
hide.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0x760++0x03
line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hexmask.long.byte 0x00 24.--31. 1. " INTID867  ,Interrupt ID867  Priority/Priority Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID866  ,Interrupt ID866   Priority/Priority Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID865  ,Interrupt ID865  Priority/Priority Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID864  ,Interrupt ID864   Priority/Priority Byte Offset 864 "
group.long 0x764++0x03
line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hexmask.long.byte 0x00 24.--31. 1. " INTID871  ,Interrupt ID871  Priority/Priority Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID870  ,Interrupt ID870   Priority/Priority Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID869  ,Interrupt ID869  Priority/Priority Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID868  ,Interrupt ID868   Priority/Priority Byte Offset 868 "
group.long 0x768++0x03
line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hexmask.long.byte 0x00 24.--31. 1. " INTID875  ,Interrupt ID875  Priority/Priority Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID874  ,Interrupt ID874   Priority/Priority Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID873  ,Interrupt ID873  Priority/Priority Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID872  ,Interrupt ID872   Priority/Priority Byte Offset 872 "
group.long 0x76C++0x03
line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hexmask.long.byte 0x00 24.--31. 1. " INTID879  ,Interrupt ID879  Priority/Priority Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID878  ,Interrupt ID878   Priority/Priority Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID877  ,Interrupt ID877  Priority/Priority Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID876  ,Interrupt ID876   Priority/Priority Byte Offset 876 "
group.long 0x770++0x03
line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hexmask.long.byte 0x00 24.--31. 1. " INTID883  ,Interrupt ID883  Priority/Priority Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID882  ,Interrupt ID882   Priority/Priority Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID881  ,Interrupt ID881  Priority/Priority Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID880  ,Interrupt ID880   Priority/Priority Byte Offset 880 "
group.long 0x774++0x03
line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hexmask.long.byte 0x00 24.--31. 1. " INTID887  ,Interrupt ID887  Priority/Priority Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID886  ,Interrupt ID886   Priority/Priority Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID885  ,Interrupt ID885  Priority/Priority Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID884  ,Interrupt ID884   Priority/Priority Byte Offset 884 "
group.long 0x778++0x03
line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hexmask.long.byte 0x00 24.--31. 1. " INTID891  ,Interrupt ID891  Priority/Priority Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID890  ,Interrupt ID890   Priority/Priority Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID889  ,Interrupt ID889  Priority/Priority Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID888  ,Interrupt ID888   Priority/Priority Byte Offset 888 "
group.long 0x77C++0x03
line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
hexmask.long.byte 0x00 24.--31. 1. " INTID895  ,Interrupt ID895  Priority/Priority Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID894  ,Interrupt ID894   Priority/Priority Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID893  ,Interrupt ID893  Priority/Priority Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID892  ,Interrupt ID892   Priority/Priority Byte Offset 892 "
else
hgroup.long 0x760++0x03
hide.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216"
hgroup.long 0x764++0x03
hide.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217"
hgroup.long 0x768++0x03
hide.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218"
hgroup.long 0x76C++0x03
hide.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219"
hgroup.long 0x770++0x03
hide.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220"
hgroup.long 0x774++0x03
hide.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221"
hgroup.long 0x778++0x03
hide.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222"
hgroup.long 0x77C++0x03
hide.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0x780++0x03
line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hexmask.long.byte 0x00 24.--31. 1. " INTID899  ,Interrupt ID899  Priority/Priority Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID898  ,Interrupt ID898   Priority/Priority Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID897  ,Interrupt ID897  Priority/Priority Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID896  ,Interrupt ID896   Priority/Priority Byte Offset 896 "
group.long 0x784++0x03
line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hexmask.long.byte 0x00 24.--31. 1. " INTID903  ,Interrupt ID903  Priority/Priority Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID902  ,Interrupt ID902   Priority/Priority Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID901  ,Interrupt ID901  Priority/Priority Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID900  ,Interrupt ID900   Priority/Priority Byte Offset 900 "
group.long 0x788++0x03
line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hexmask.long.byte 0x00 24.--31. 1. " INTID907  ,Interrupt ID907  Priority/Priority Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID906  ,Interrupt ID906   Priority/Priority Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID905  ,Interrupt ID905  Priority/Priority Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID904  ,Interrupt ID904   Priority/Priority Byte Offset 904 "
group.long 0x78C++0x03
line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hexmask.long.byte 0x00 24.--31. 1. " INTID911  ,Interrupt ID911  Priority/Priority Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID910  ,Interrupt ID910   Priority/Priority Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID909  ,Interrupt ID909  Priority/Priority Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID908  ,Interrupt ID908   Priority/Priority Byte Offset 908 "
group.long 0x790++0x03
line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hexmask.long.byte 0x00 24.--31. 1. " INTID915  ,Interrupt ID915  Priority/Priority Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID914  ,Interrupt ID914   Priority/Priority Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID913  ,Interrupt ID913  Priority/Priority Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID912  ,Interrupt ID912   Priority/Priority Byte Offset 912 "
group.long 0x794++0x03
line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hexmask.long.byte 0x00 24.--31. 1. " INTID919  ,Interrupt ID919  Priority/Priority Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID918  ,Interrupt ID918   Priority/Priority Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID917  ,Interrupt ID917  Priority/Priority Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID916  ,Interrupt ID916   Priority/Priority Byte Offset 916 "
group.long 0x798++0x03
line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hexmask.long.byte 0x00 24.--31. 1. " INTID923  ,Interrupt ID923  Priority/Priority Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID922  ,Interrupt ID922   Priority/Priority Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID921  ,Interrupt ID921  Priority/Priority Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID920  ,Interrupt ID920   Priority/Priority Byte Offset 920 "
group.long 0x79C++0x03
line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
hexmask.long.byte 0x00 24.--31. 1. " INTID927  ,Interrupt ID927  Priority/Priority Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID926  ,Interrupt ID926   Priority/Priority Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID925  ,Interrupt ID925  Priority/Priority Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID924  ,Interrupt ID924   Priority/Priority Byte Offset 924 "
else
hgroup.long 0x780++0x03
hide.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224"
hgroup.long 0x784++0x03
hide.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225"
hgroup.long 0x788++0x03
hide.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226"
hgroup.long 0x78C++0x03
hide.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227"
hgroup.long 0x790++0x03
hide.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228"
hgroup.long 0x794++0x03
hide.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229"
hgroup.long 0x798++0x03
hide.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230"
hgroup.long 0x79C++0x03
hide.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0x7A0++0x03
line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hexmask.long.byte 0x00 24.--31. 1. " INTID931  ,Interrupt ID931  Priority/Priority Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID930  ,Interrupt ID930   Priority/Priority Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID929  ,Interrupt ID929  Priority/Priority Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID928  ,Interrupt ID928   Priority/Priority Byte Offset 928 "
group.long 0x7A4++0x03
line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hexmask.long.byte 0x00 24.--31. 1. " INTID935  ,Interrupt ID935  Priority/Priority Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID934  ,Interrupt ID934   Priority/Priority Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID933  ,Interrupt ID933  Priority/Priority Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID932  ,Interrupt ID932   Priority/Priority Byte Offset 932 "
group.long 0x7A8++0x03
line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hexmask.long.byte 0x00 24.--31. 1. " INTID939  ,Interrupt ID939  Priority/Priority Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID938  ,Interrupt ID938   Priority/Priority Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID937  ,Interrupt ID937  Priority/Priority Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID936  ,Interrupt ID936   Priority/Priority Byte Offset 936 "
group.long 0x7AC++0x03
line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hexmask.long.byte 0x00 24.--31. 1. " INTID943  ,Interrupt ID943  Priority/Priority Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID942  ,Interrupt ID942   Priority/Priority Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID941  ,Interrupt ID941  Priority/Priority Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID940  ,Interrupt ID940   Priority/Priority Byte Offset 940 "
group.long 0x7B0++0x03
line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hexmask.long.byte 0x00 24.--31. 1. " INTID947  ,Interrupt ID947  Priority/Priority Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID946  ,Interrupt ID946   Priority/Priority Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID945  ,Interrupt ID945  Priority/Priority Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID944  ,Interrupt ID944   Priority/Priority Byte Offset 944 "
group.long 0x7B4++0x03
line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hexmask.long.byte 0x00 24.--31. 1. " INTID951  ,Interrupt ID951  Priority/Priority Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID950  ,Interrupt ID950   Priority/Priority Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID949  ,Interrupt ID949  Priority/Priority Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID948  ,Interrupt ID948   Priority/Priority Byte Offset 948 "
group.long 0x7B8++0x03
line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hexmask.long.byte 0x00 24.--31. 1. " INTID955  ,Interrupt ID955  Priority/Priority Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID954  ,Interrupt ID954   Priority/Priority Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID953  ,Interrupt ID953  Priority/Priority Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID952  ,Interrupt ID952   Priority/Priority Byte Offset 952 "
group.long 0x7BC++0x03
line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
hexmask.long.byte 0x00 24.--31. 1. " INTID959  ,Interrupt ID959  Priority/Priority Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID958  ,Interrupt ID958   Priority/Priority Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID957  ,Interrupt ID957  Priority/Priority Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID956  ,Interrupt ID956   Priority/Priority Byte Offset 956 "
else
hgroup.long 0x7A0++0x03
hide.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232"
hgroup.long 0x7A4++0x03
hide.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233"
hgroup.long 0x7A8++0x03
hide.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234"
hgroup.long 0x7AC++0x03
hide.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235"
hgroup.long 0x7B0++0x03
hide.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236"
hgroup.long 0x7B4++0x03
hide.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237"
hgroup.long 0x7B8++0x03
hide.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238"
hgroup.long 0x7BC++0x03
hide.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0x7C0++0x03
line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hexmask.long.byte 0x00 24.--31. 1. " INTID963  ,Interrupt ID963  Priority/Priority Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID962  ,Interrupt ID962   Priority/Priority Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID961  ,Interrupt ID961  Priority/Priority Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID960  ,Interrupt ID960   Priority/Priority Byte Offset 960 "
group.long 0x7C4++0x03
line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hexmask.long.byte 0x00 24.--31. 1. " INTID967  ,Interrupt ID967  Priority/Priority Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID966  ,Interrupt ID966   Priority/Priority Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID965  ,Interrupt ID965  Priority/Priority Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID964  ,Interrupt ID964   Priority/Priority Byte Offset 964 "
group.long 0x7C8++0x03
line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hexmask.long.byte 0x00 24.--31. 1. " INTID971  ,Interrupt ID971  Priority/Priority Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID970  ,Interrupt ID970   Priority/Priority Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID969  ,Interrupt ID969  Priority/Priority Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID968  ,Interrupt ID968   Priority/Priority Byte Offset 968 "
group.long 0x7CC++0x03
line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hexmask.long.byte 0x00 24.--31. 1. " INTID975  ,Interrupt ID975  Priority/Priority Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID974  ,Interrupt ID974   Priority/Priority Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID973  ,Interrupt ID973  Priority/Priority Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID972  ,Interrupt ID972   Priority/Priority Byte Offset 972 "
group.long 0x7D0++0x03
line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hexmask.long.byte 0x00 24.--31. 1. " INTID979  ,Interrupt ID979  Priority/Priority Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID978  ,Interrupt ID978   Priority/Priority Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID977  ,Interrupt ID977  Priority/Priority Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID976  ,Interrupt ID976   Priority/Priority Byte Offset 976 "
group.long 0x7D4++0x03
line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hexmask.long.byte 0x00 24.--31. 1. " INTID983  ,Interrupt ID983  Priority/Priority Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID982  ,Interrupt ID982   Priority/Priority Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID981  ,Interrupt ID981  Priority/Priority Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID980  ,Interrupt ID980   Priority/Priority Byte Offset 980 "
group.long 0x7D8++0x03
line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hexmask.long.byte 0x00 24.--31. 1. " INTID987  ,Interrupt ID987  Priority/Priority Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID986  ,Interrupt ID986   Priority/Priority Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID985  ,Interrupt ID985  Priority/Priority Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID984  ,Interrupt ID984   Priority/Priority Byte Offset 984 "
group.long 0x7DC++0x03
line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
hexmask.long.byte 0x00 24.--31. 1. " INTID991  ,Interrupt ID991  Priority/Priority Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  INTID990  ,Interrupt ID990   Priority/Priority Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  INTID989  ,Interrupt ID989  Priority/Priority Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  INTID988  ,Interrupt ID988   Priority/Priority Byte Offset 988 "
else
hgroup.long 0x7C0++0x03
hide.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240"
hgroup.long 0x7C4++0x03
hide.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241"
hgroup.long 0x7C8++0x03
hide.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242"
hgroup.long 0x7CC++0x03
hide.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243"
hgroup.long 0x7D0++0x03
hide.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244"
hgroup.long 0x7D4++0x03
hide.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245"
hgroup.long 0x7D8++0x03
hide.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246"
hgroup.long 0x7DC++0x03
hide.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247"
endif
tree.end
width 19.
tree "Interrupt Targets Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x000000E0)>0x1)
hgroup.long 0x800++0x03
hide.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0"
hgroup.long 0x804++0x03
hide.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1"
hgroup.long 0x808++0x03
hide.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2"
hgroup.long 0x80C++0x03
hide.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3"
hgroup.long 0x810++0x03
hide.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4"
hgroup.long 0x814++0x03
hide.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5"
hgroup.long 0x818++0x03
hide.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6"
hgroup.long 0x81C++0x03
hide.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01)
group.long 0x820++0x03
line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35   ,CPU Targets Byte Offset 35  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO34   ,CPU Targets Byte Offset 34  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO33   ,CPU Targets Byte Offset 33  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO32   ,CPU Targets Byte Offset 32  "
group.long 0x824++0x03
line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39   ,CPU Targets Byte Offset 39  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO38   ,CPU Targets Byte Offset 38  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO37   ,CPU Targets Byte Offset 37  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO36   ,CPU Targets Byte Offset 36  "
group.long 0x828++0x03
line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43   ,CPU Targets Byte Offset 43  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO42   ,CPU Targets Byte Offset 42  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO41   ,CPU Targets Byte Offset 41  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO40   ,CPU Targets Byte Offset 40  "
group.long 0x82C++0x03
line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47   ,CPU Targets Byte Offset 47  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO46   ,CPU Targets Byte Offset 46  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO45   ,CPU Targets Byte Offset 45  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO44   ,CPU Targets Byte Offset 44  "
group.long 0x830++0x03
line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51   ,CPU Targets Byte Offset 51  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO50   ,CPU Targets Byte Offset 50  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO49   ,CPU Targets Byte Offset 49  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO48   ,CPU Targets Byte Offset 48  "
group.long 0x834++0x03
line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55   ,CPU Targets Byte Offset 55  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO54   ,CPU Targets Byte Offset 54  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO53   ,CPU Targets Byte Offset 53  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO52   ,CPU Targets Byte Offset 52  "
group.long 0x838++0x03
line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59   ,CPU Targets Byte Offset 59  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO58   ,CPU Targets Byte Offset 58  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO57   ,CPU Targets Byte Offset 57  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO56   ,CPU Targets Byte Offset 56  "
group.long 0x83C++0x03
line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63   ,CPU Targets Byte Offset 63  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO62   ,CPU Targets Byte Offset 62  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO61   ,CPU Targets Byte Offset 61  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO60   ,CPU Targets Byte Offset 60  "
else
hgroup.long 0x820++0x03
hide.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8"
hgroup.long 0x824++0x03
hide.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9"
hgroup.long 0x828++0x03
hide.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10"
hgroup.long 0x82C++0x03
hide.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11"
hgroup.long 0x830++0x03
hide.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12"
hgroup.long 0x834++0x03
hide.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13"
hgroup.long 0x838++0x03
hide.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14"
hgroup.long 0x83C++0x03
hide.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02)
group.long 0x840++0x03
line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67   ,CPU Targets Byte Offset 67  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO66   ,CPU Targets Byte Offset 66  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO65   ,CPU Targets Byte Offset 65  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO64   ,CPU Targets Byte Offset 64  "
group.long 0x844++0x03
line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71   ,CPU Targets Byte Offset 71  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO70   ,CPU Targets Byte Offset 70  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO69   ,CPU Targets Byte Offset 69  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO68   ,CPU Targets Byte Offset 68  "
group.long 0x848++0x03
line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75   ,CPU Targets Byte Offset 75  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO74   ,CPU Targets Byte Offset 74  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO73   ,CPU Targets Byte Offset 73  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO72   ,CPU Targets Byte Offset 72  "
group.long 0x84C++0x03
line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79   ,CPU Targets Byte Offset 79  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO78   ,CPU Targets Byte Offset 78  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO77   ,CPU Targets Byte Offset 77  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO76   ,CPU Targets Byte Offset 76  "
group.long 0x850++0x03
line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83   ,CPU Targets Byte Offset 83  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO82   ,CPU Targets Byte Offset 82  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO81   ,CPU Targets Byte Offset 81  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO80   ,CPU Targets Byte Offset 80  "
group.long 0x854++0x03
line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87   ,CPU Targets Byte Offset 87  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO86   ,CPU Targets Byte Offset 86  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO85   ,CPU Targets Byte Offset 85  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO84   ,CPU Targets Byte Offset 84  "
group.long 0x858++0x03
line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91   ,CPU Targets Byte Offset 91  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO90   ,CPU Targets Byte Offset 90  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO89   ,CPU Targets Byte Offset 89  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO88   ,CPU Targets Byte Offset 88  "
group.long 0x85C++0x03
line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95   ,CPU Targets Byte Offset 95  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO94   ,CPU Targets Byte Offset 94  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO93   ,CPU Targets Byte Offset 93  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO92   ,CPU Targets Byte Offset 92  "
else
hgroup.long 0x840++0x03
hide.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16"
hgroup.long 0x844++0x03
hide.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17"
hgroup.long 0x848++0x03
hide.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18"
hgroup.long 0x84C++0x03
hide.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19"
hgroup.long 0x850++0x03
hide.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20"
hgroup.long 0x854++0x03
hide.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21"
hgroup.long 0x858++0x03
hide.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22"
hgroup.long 0x85C++0x03
hide.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03)
group.long 0x860++0x03
line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99   ,CPU Targets Byte Offset 99  "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO98   ,CPU Targets Byte Offset 98  "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO97   ,CPU Targets Byte Offset 97  "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO96   ,CPU Targets Byte Offset 96  "
group.long 0x864++0x03
line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103  ,CPU Targets Byte Offset 103 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO102  ,CPU Targets Byte Offset 102 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO101  ,CPU Targets Byte Offset 101 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO100  ,CPU Targets Byte Offset 100 "
group.long 0x868++0x03
line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107  ,CPU Targets Byte Offset 107 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO106  ,CPU Targets Byte Offset 106 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO105  ,CPU Targets Byte Offset 105 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO104  ,CPU Targets Byte Offset 104 "
group.long 0x86C++0x03
line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111  ,CPU Targets Byte Offset 111 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO110  ,CPU Targets Byte Offset 110 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO109  ,CPU Targets Byte Offset 109 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO108  ,CPU Targets Byte Offset 108 "
group.long 0x870++0x03
line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115  ,CPU Targets Byte Offset 115 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO114  ,CPU Targets Byte Offset 114 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO113  ,CPU Targets Byte Offset 113 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO112  ,CPU Targets Byte Offset 112 "
group.long 0x874++0x03
line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119  ,CPU Targets Byte Offset 119 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO118  ,CPU Targets Byte Offset 118 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO117  ,CPU Targets Byte Offset 117 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO116  ,CPU Targets Byte Offset 116 "
group.long 0x878++0x03
line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123  ,CPU Targets Byte Offset 123 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO122  ,CPU Targets Byte Offset 122 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO121  ,CPU Targets Byte Offset 121 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO120  ,CPU Targets Byte Offset 120 "
group.long 0x87C++0x03
line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127  ,CPU Targets Byte Offset 127 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO126  ,CPU Targets Byte Offset 126 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO125  ,CPU Targets Byte Offset 125 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO124  ,CPU Targets Byte Offset 124 "
else
hgroup.long 0x860++0x03
hide.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24"
hgroup.long 0x864++0x03
hide.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25"
hgroup.long 0x868++0x03
hide.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26"
hgroup.long 0x86C++0x03
hide.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27"
hgroup.long 0x870++0x03
hide.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28"
hgroup.long 0x874++0x03
hide.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29"
hgroup.long 0x878++0x03
hide.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30"
hgroup.long 0x87C++0x03
hide.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04)
group.long 0x880++0x03
line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131  ,CPU Targets Byte Offset 131 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO130  ,CPU Targets Byte Offset 130 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO129  ,CPU Targets Byte Offset 129 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO128  ,CPU Targets Byte Offset 128 "
group.long 0x884++0x03
line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135  ,CPU Targets Byte Offset 135 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO134  ,CPU Targets Byte Offset 134 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO133  ,CPU Targets Byte Offset 133 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO132  ,CPU Targets Byte Offset 132 "
group.long 0x888++0x03
line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139  ,CPU Targets Byte Offset 139 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO138  ,CPU Targets Byte Offset 138 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO137  ,CPU Targets Byte Offset 137 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO136  ,CPU Targets Byte Offset 136 "
group.long 0x88C++0x03
line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143  ,CPU Targets Byte Offset 143 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO142  ,CPU Targets Byte Offset 142 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO141  ,CPU Targets Byte Offset 141 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO140  ,CPU Targets Byte Offset 140 "
group.long 0x890++0x03
line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147  ,CPU Targets Byte Offset 147 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO146  ,CPU Targets Byte Offset 146 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO145  ,CPU Targets Byte Offset 145 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO144  ,CPU Targets Byte Offset 144 "
group.long 0x894++0x03
line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151  ,CPU Targets Byte Offset 151 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO150  ,CPU Targets Byte Offset 150 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO149  ,CPU Targets Byte Offset 149 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO148  ,CPU Targets Byte Offset 148 "
group.long 0x898++0x03
line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155  ,CPU Targets Byte Offset 155 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO154  ,CPU Targets Byte Offset 154 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO153  ,CPU Targets Byte Offset 153 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO152  ,CPU Targets Byte Offset 152 "
group.long 0x89C++0x03
line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159  ,CPU Targets Byte Offset 159 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO158  ,CPU Targets Byte Offset 158 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO157  ,CPU Targets Byte Offset 157 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO156  ,CPU Targets Byte Offset 156 "
else
hgroup.long 0x880++0x03
hide.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32"
hgroup.long 0x884++0x03
hide.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33"
hgroup.long 0x888++0x03
hide.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34"
hgroup.long 0x88C++0x03
hide.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35"
hgroup.long 0x890++0x03
hide.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36"
hgroup.long 0x894++0x03
hide.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37"
hgroup.long 0x898++0x03
hide.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38"
hgroup.long 0x89C++0x03
hide.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05)
group.long 0x8A0++0x03
line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163  ,CPU Targets Byte Offset 163 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO162  ,CPU Targets Byte Offset 162 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO161  ,CPU Targets Byte Offset 161 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO160  ,CPU Targets Byte Offset 160 "
group.long 0x8A4++0x03
line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167  ,CPU Targets Byte Offset 167 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO166  ,CPU Targets Byte Offset 166 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO165  ,CPU Targets Byte Offset 165 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO164  ,CPU Targets Byte Offset 164 "
group.long 0x8A8++0x03
line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171  ,CPU Targets Byte Offset 171 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO170  ,CPU Targets Byte Offset 170 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO169  ,CPU Targets Byte Offset 169 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO168  ,CPU Targets Byte Offset 168 "
group.long 0x8AC++0x03
line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175  ,CPU Targets Byte Offset 175 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO174  ,CPU Targets Byte Offset 174 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO173  ,CPU Targets Byte Offset 173 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO172  ,CPU Targets Byte Offset 172 "
group.long 0x8B0++0x03
line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179  ,CPU Targets Byte Offset 179 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO178  ,CPU Targets Byte Offset 178 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO177  ,CPU Targets Byte Offset 177 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO176  ,CPU Targets Byte Offset 176 "
group.long 0x8B4++0x03
line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183  ,CPU Targets Byte Offset 183 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO182  ,CPU Targets Byte Offset 182 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO181  ,CPU Targets Byte Offset 181 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO180  ,CPU Targets Byte Offset 180 "
group.long 0x8B8++0x03
line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187  ,CPU Targets Byte Offset 187 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO186  ,CPU Targets Byte Offset 186 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO185  ,CPU Targets Byte Offset 185 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO184  ,CPU Targets Byte Offset 184 "
group.long 0x8BC++0x03
line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191  ,CPU Targets Byte Offset 191 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO190  ,CPU Targets Byte Offset 190 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO189  ,CPU Targets Byte Offset 189 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO188  ,CPU Targets Byte Offset 188 "
else
hgroup.long 0x8A0++0x03
hide.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40"
hgroup.long 0x8A4++0x03
hide.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41"
hgroup.long 0x8A8++0x03
hide.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42"
hgroup.long 0x8AC++0x03
hide.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43"
hgroup.long 0x8B0++0x03
hide.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44"
hgroup.long 0x8B4++0x03
hide.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45"
hgroup.long 0x8B8++0x03
hide.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46"
hgroup.long 0x8BC++0x03
hide.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06)
group.long 0x8C0++0x03
line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195  ,CPU Targets Byte Offset 195 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO194  ,CPU Targets Byte Offset 194 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO193  ,CPU Targets Byte Offset 193 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO192  ,CPU Targets Byte Offset 192 "
group.long 0x8C4++0x03
line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199  ,CPU Targets Byte Offset 199 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO198  ,CPU Targets Byte Offset 198 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO197  ,CPU Targets Byte Offset 197 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO196  ,CPU Targets Byte Offset 196 "
group.long 0x8C8++0x03
line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203  ,CPU Targets Byte Offset 203 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO202  ,CPU Targets Byte Offset 202 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO201  ,CPU Targets Byte Offset 201 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO200  ,CPU Targets Byte Offset 200 "
group.long 0x8CC++0x03
line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207  ,CPU Targets Byte Offset 207 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO206  ,CPU Targets Byte Offset 206 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO205  ,CPU Targets Byte Offset 205 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO204  ,CPU Targets Byte Offset 204 "
group.long 0x8D0++0x03
line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211  ,CPU Targets Byte Offset 211 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO210  ,CPU Targets Byte Offset 210 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO209  ,CPU Targets Byte Offset 209 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO208  ,CPU Targets Byte Offset 208 "
group.long 0x8D4++0x03
line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215  ,CPU Targets Byte Offset 215 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO214  ,CPU Targets Byte Offset 214 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO213  ,CPU Targets Byte Offset 213 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO212  ,CPU Targets Byte Offset 212 "
group.long 0x8D8++0x03
line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219  ,CPU Targets Byte Offset 219 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO218  ,CPU Targets Byte Offset 218 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO217  ,CPU Targets Byte Offset 217 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO216  ,CPU Targets Byte Offset 216 "
group.long 0x8DC++0x03
line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223  ,CPU Targets Byte Offset 223 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO222  ,CPU Targets Byte Offset 222 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO221  ,CPU Targets Byte Offset 221 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO220  ,CPU Targets Byte Offset 220 "
else
hgroup.long 0x8C0++0x03
hide.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48"
hgroup.long 0x8C4++0x03
hide.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49"
hgroup.long 0x8C8++0x03
hide.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50"
hgroup.long 0x8CC++0x03
hide.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51"
hgroup.long 0x8D0++0x03
hide.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52"
hgroup.long 0x8D4++0x03
hide.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53"
hgroup.long 0x8D8++0x03
hide.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54"
hgroup.long 0x8DC++0x03
hide.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07)
group.long 0x8E0++0x03
line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227  ,CPU Targets Byte Offset 227 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO226  ,CPU Targets Byte Offset 226 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO225  ,CPU Targets Byte Offset 225 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO224  ,CPU Targets Byte Offset 224 "
group.long 0x8E4++0x03
line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231  ,CPU Targets Byte Offset 231 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO230  ,CPU Targets Byte Offset 230 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO229  ,CPU Targets Byte Offset 229 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO228  ,CPU Targets Byte Offset 228 "
group.long 0x8E8++0x03
line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235  ,CPU Targets Byte Offset 235 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO234  ,CPU Targets Byte Offset 234 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO233  ,CPU Targets Byte Offset 233 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO232  ,CPU Targets Byte Offset 232 "
group.long 0x8EC++0x03
line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239  ,CPU Targets Byte Offset 239 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO238  ,CPU Targets Byte Offset 238 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO237  ,CPU Targets Byte Offset 237 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO236  ,CPU Targets Byte Offset 236 "
group.long 0x8F0++0x03
line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243  ,CPU Targets Byte Offset 243 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO242  ,CPU Targets Byte Offset 242 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO241  ,CPU Targets Byte Offset 241 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO240  ,CPU Targets Byte Offset 240 "
group.long 0x8F4++0x03
line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247  ,CPU Targets Byte Offset 247 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO246  ,CPU Targets Byte Offset 246 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO245  ,CPU Targets Byte Offset 245 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO244  ,CPU Targets Byte Offset 244 "
group.long 0x8F8++0x03
line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251  ,CPU Targets Byte Offset 251 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO250  ,CPU Targets Byte Offset 250 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO249  ,CPU Targets Byte Offset 249 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO248  ,CPU Targets Byte Offset 248 "
group.long 0x8FC++0x03
line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255  ,CPU Targets Byte Offset 255 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO254  ,CPU Targets Byte Offset 254 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO253  ,CPU Targets Byte Offset 253 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO252  ,CPU Targets Byte Offset 252 "
else
hgroup.long 0x8E0++0x03
hide.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56"
hgroup.long 0x8E4++0x03
hide.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57"
hgroup.long 0x8E8++0x03
hide.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58"
hgroup.long 0x8EC++0x03
hide.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59"
hgroup.long 0x8F0++0x03
hide.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60"
hgroup.long 0x8F4++0x03
hide.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61"
hgroup.long 0x8F8++0x03
hide.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62"
hgroup.long 0x8FC++0x03
hide.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08)
group.long 0x900++0x03
line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259  ,CPU Targets Byte Offset 259 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO258  ,CPU Targets Byte Offset 258 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO257  ,CPU Targets Byte Offset 257 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO256  ,CPU Targets Byte Offset 256 "
group.long 0x904++0x03
line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263  ,CPU Targets Byte Offset 263 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO262  ,CPU Targets Byte Offset 262 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO261  ,CPU Targets Byte Offset 261 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO260  ,CPU Targets Byte Offset 260 "
group.long 0x908++0x03
line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267  ,CPU Targets Byte Offset 267 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO266  ,CPU Targets Byte Offset 266 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO265  ,CPU Targets Byte Offset 265 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO264  ,CPU Targets Byte Offset 264 "
group.long 0x90C++0x03
line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271  ,CPU Targets Byte Offset 271 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO270  ,CPU Targets Byte Offset 270 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO269  ,CPU Targets Byte Offset 269 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO268  ,CPU Targets Byte Offset 268 "
group.long 0x910++0x03
line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275  ,CPU Targets Byte Offset 275 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO274  ,CPU Targets Byte Offset 274 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO273  ,CPU Targets Byte Offset 273 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO272  ,CPU Targets Byte Offset 272 "
group.long 0x914++0x03
line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279  ,CPU Targets Byte Offset 279 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO278  ,CPU Targets Byte Offset 278 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO277  ,CPU Targets Byte Offset 277 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO276  ,CPU Targets Byte Offset 276 "
group.long 0x918++0x03
line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283  ,CPU Targets Byte Offset 283 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO282  ,CPU Targets Byte Offset 282 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO281  ,CPU Targets Byte Offset 281 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO280  ,CPU Targets Byte Offset 280 "
group.long 0x91C++0x03
line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287  ,CPU Targets Byte Offset 287 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO286  ,CPU Targets Byte Offset 286 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO285  ,CPU Targets Byte Offset 285 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO284  ,CPU Targets Byte Offset 284 "
else
hgroup.long 0x900++0x03
hide.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64"
hgroup.long 0x904++0x03
hide.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65"
hgroup.long 0x908++0x03
hide.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66"
hgroup.long 0x90C++0x03
hide.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67"
hgroup.long 0x910++0x03
hide.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68"
hgroup.long 0x914++0x03
hide.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69"
hgroup.long 0x918++0x03
hide.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70"
hgroup.long 0x91C++0x03
hide.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09)
group.long 0x920++0x03
line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291  ,CPU Targets Byte Offset 291 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO290  ,CPU Targets Byte Offset 290 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO289  ,CPU Targets Byte Offset 289 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO288  ,CPU Targets Byte Offset 288 "
group.long 0x924++0x03
line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295  ,CPU Targets Byte Offset 295 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO294  ,CPU Targets Byte Offset 294 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO293  ,CPU Targets Byte Offset 293 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO292  ,CPU Targets Byte Offset 292 "
group.long 0x928++0x03
line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299  ,CPU Targets Byte Offset 299 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO298  ,CPU Targets Byte Offset 298 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO297  ,CPU Targets Byte Offset 297 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO296  ,CPU Targets Byte Offset 296 "
group.long 0x92C++0x03
line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303  ,CPU Targets Byte Offset 303 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO302  ,CPU Targets Byte Offset 302 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO301  ,CPU Targets Byte Offset 301 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO300  ,CPU Targets Byte Offset 300 "
group.long 0x930++0x03
line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307  ,CPU Targets Byte Offset 307 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO306  ,CPU Targets Byte Offset 306 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO305  ,CPU Targets Byte Offset 305 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO304  ,CPU Targets Byte Offset 304 "
group.long 0x934++0x03
line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311  ,CPU Targets Byte Offset 311 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO310  ,CPU Targets Byte Offset 310 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO309  ,CPU Targets Byte Offset 309 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO308  ,CPU Targets Byte Offset 308 "
group.long 0x938++0x03
line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315  ,CPU Targets Byte Offset 315 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO314  ,CPU Targets Byte Offset 314 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO313  ,CPU Targets Byte Offset 313 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO312  ,CPU Targets Byte Offset 312 "
group.long 0x93C++0x03
line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319  ,CPU Targets Byte Offset 319 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO318  ,CPU Targets Byte Offset 318 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO317  ,CPU Targets Byte Offset 317 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO316  ,CPU Targets Byte Offset 316 "
else
hgroup.long 0x920++0x03
hide.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72"
hgroup.long 0x924++0x03
hide.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73"
hgroup.long 0x928++0x03
hide.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74"
hgroup.long 0x92C++0x03
hide.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75"
hgroup.long 0x930++0x03
hide.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76"
hgroup.long 0x934++0x03
hide.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77"
hgroup.long 0x938++0x03
hide.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78"
hgroup.long 0x93C++0x03
hide.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A)
group.long 0x940++0x03
line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323  ,CPU Targets Byte Offset 323 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO322  ,CPU Targets Byte Offset 322 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO321  ,CPU Targets Byte Offset 321 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO320  ,CPU Targets Byte Offset 320 "
group.long 0x944++0x03
line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327  ,CPU Targets Byte Offset 327 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO326  ,CPU Targets Byte Offset 326 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO325  ,CPU Targets Byte Offset 325 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO324  ,CPU Targets Byte Offset 324 "
group.long 0x948++0x03
line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331  ,CPU Targets Byte Offset 331 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO330  ,CPU Targets Byte Offset 330 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO329  ,CPU Targets Byte Offset 329 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO328  ,CPU Targets Byte Offset 328 "
group.long 0x94C++0x03
line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335  ,CPU Targets Byte Offset 335 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO334  ,CPU Targets Byte Offset 334 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO333  ,CPU Targets Byte Offset 333 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO332  ,CPU Targets Byte Offset 332 "
group.long 0x950++0x03
line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339  ,CPU Targets Byte Offset 339 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO338  ,CPU Targets Byte Offset 338 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO337  ,CPU Targets Byte Offset 337 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO336  ,CPU Targets Byte Offset 336 "
group.long 0x954++0x03
line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343  ,CPU Targets Byte Offset 343 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO342  ,CPU Targets Byte Offset 342 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO341  ,CPU Targets Byte Offset 341 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO340  ,CPU Targets Byte Offset 340 "
group.long 0x958++0x03
line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347  ,CPU Targets Byte Offset 347 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO346  ,CPU Targets Byte Offset 346 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO345  ,CPU Targets Byte Offset 345 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO344  ,CPU Targets Byte Offset 344 "
group.long 0x95C++0x03
line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351  ,CPU Targets Byte Offset 351 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO350  ,CPU Targets Byte Offset 350 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO349  ,CPU Targets Byte Offset 349 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO348  ,CPU Targets Byte Offset 348 "
else
hgroup.long 0x940++0x03
hide.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80"
hgroup.long 0x944++0x03
hide.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81"
hgroup.long 0x948++0x03
hide.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82"
hgroup.long 0x94C++0x03
hide.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83"
hgroup.long 0x950++0x03
hide.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84"
hgroup.long 0x954++0x03
hide.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85"
hgroup.long 0x958++0x03
hide.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86"
hgroup.long 0x95C++0x03
hide.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B)
group.long 0x960++0x03
line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355  ,CPU Targets Byte Offset 355 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO354  ,CPU Targets Byte Offset 354 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO353  ,CPU Targets Byte Offset 353 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO352  ,CPU Targets Byte Offset 352 "
group.long 0x964++0x03
line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359  ,CPU Targets Byte Offset 359 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO358  ,CPU Targets Byte Offset 358 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO357  ,CPU Targets Byte Offset 357 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO356  ,CPU Targets Byte Offset 356 "
group.long 0x968++0x03
line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363  ,CPU Targets Byte Offset 363 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO362  ,CPU Targets Byte Offset 362 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO361  ,CPU Targets Byte Offset 361 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO360  ,CPU Targets Byte Offset 360 "
group.long 0x96C++0x03
line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367  ,CPU Targets Byte Offset 367 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO366  ,CPU Targets Byte Offset 366 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO365  ,CPU Targets Byte Offset 365 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO364  ,CPU Targets Byte Offset 364 "
group.long 0x970++0x03
line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371  ,CPU Targets Byte Offset 371 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO370  ,CPU Targets Byte Offset 370 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO369  ,CPU Targets Byte Offset 369 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO368  ,CPU Targets Byte Offset 368 "
group.long 0x974++0x03
line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375  ,CPU Targets Byte Offset 375 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO374  ,CPU Targets Byte Offset 374 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO373  ,CPU Targets Byte Offset 373 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO372  ,CPU Targets Byte Offset 372 "
group.long 0x978++0x03
line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379  ,CPU Targets Byte Offset 379 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO378  ,CPU Targets Byte Offset 378 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO377  ,CPU Targets Byte Offset 377 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO376  ,CPU Targets Byte Offset 376 "
group.long 0x97C++0x03
line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383  ,CPU Targets Byte Offset 383 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO382  ,CPU Targets Byte Offset 382 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO381  ,CPU Targets Byte Offset 381 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO380  ,CPU Targets Byte Offset 380 "
else
hgroup.long 0x960++0x03
hide.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88"
hgroup.long 0x964++0x03
hide.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89"
hgroup.long 0x968++0x03
hide.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90"
hgroup.long 0x96C++0x03
hide.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91"
hgroup.long 0x970++0x03
hide.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92"
hgroup.long 0x974++0x03
hide.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93"
hgroup.long 0x978++0x03
hide.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94"
hgroup.long 0x97C++0x03
hide.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C)
group.long 0x980++0x03
line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387  ,CPU Targets Byte Offset 387 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO386  ,CPU Targets Byte Offset 386 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO385  ,CPU Targets Byte Offset 385 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO384  ,CPU Targets Byte Offset 384 "
group.long 0x984++0x03
line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391  ,CPU Targets Byte Offset 391 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO390  ,CPU Targets Byte Offset 390 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO389  ,CPU Targets Byte Offset 389 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO388  ,CPU Targets Byte Offset 388 "
group.long 0x988++0x03
line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395  ,CPU Targets Byte Offset 395 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO394  ,CPU Targets Byte Offset 394 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO393  ,CPU Targets Byte Offset 393 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO392  ,CPU Targets Byte Offset 392 "
group.long 0x98C++0x03
line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399  ,CPU Targets Byte Offset 399 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO398  ,CPU Targets Byte Offset 398 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO397  ,CPU Targets Byte Offset 397 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO396  ,CPU Targets Byte Offset 396 "
group.long 0x990++0x03
line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403  ,CPU Targets Byte Offset 403 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO402  ,CPU Targets Byte Offset 402 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO401  ,CPU Targets Byte Offset 401 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO400  ,CPU Targets Byte Offset 400 "
group.long 0x994++0x03
line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407  ,CPU Targets Byte Offset 407 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO406  ,CPU Targets Byte Offset 406 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO405  ,CPU Targets Byte Offset 405 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO404  ,CPU Targets Byte Offset 404 "
group.long 0x998++0x03
line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411  ,CPU Targets Byte Offset 411 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO410  ,CPU Targets Byte Offset 410 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO409  ,CPU Targets Byte Offset 409 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO408  ,CPU Targets Byte Offset 408 "
group.long 0x99C++0x03
line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415  ,CPU Targets Byte Offset 415 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO414  ,CPU Targets Byte Offset 414 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO413  ,CPU Targets Byte Offset 413 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO412  ,CPU Targets Byte Offset 412 "
else
hgroup.long 0x980++0x03
hide.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96"
hgroup.long 0x984++0x03
hide.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97"
hgroup.long 0x988++0x03
hide.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98"
hgroup.long 0x98C++0x03
hide.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99"
hgroup.long 0x990++0x03
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hgroup.long 0x994++0x03
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hgroup.long 0x998++0x03
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hgroup.long 0x99C++0x03
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D)
group.long 0x9A0++0x03
line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419  ,CPU Targets Byte Offset 419 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO418  ,CPU Targets Byte Offset 418 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO417  ,CPU Targets Byte Offset 417 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO416  ,CPU Targets Byte Offset 416 "
group.long 0x9A4++0x03
line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423  ,CPU Targets Byte Offset 423 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO422  ,CPU Targets Byte Offset 422 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO421  ,CPU Targets Byte Offset 421 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO420  ,CPU Targets Byte Offset 420 "
group.long 0x9A8++0x03
line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427  ,CPU Targets Byte Offset 427 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO426  ,CPU Targets Byte Offset 426 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO425  ,CPU Targets Byte Offset 425 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO424  ,CPU Targets Byte Offset 424 "
group.long 0x9AC++0x03
line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431  ,CPU Targets Byte Offset 431 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO430  ,CPU Targets Byte Offset 430 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO429  ,CPU Targets Byte Offset 429 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO428  ,CPU Targets Byte Offset 428 "
group.long 0x9B0++0x03
line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435  ,CPU Targets Byte Offset 435 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO434  ,CPU Targets Byte Offset 434 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO433  ,CPU Targets Byte Offset 433 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO432  ,CPU Targets Byte Offset 432 "
group.long 0x9B4++0x03
line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439  ,CPU Targets Byte Offset 439 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO438  ,CPU Targets Byte Offset 438 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO437  ,CPU Targets Byte Offset 437 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO436  ,CPU Targets Byte Offset 436 "
group.long 0x9B8++0x03
line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443  ,CPU Targets Byte Offset 443 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO442  ,CPU Targets Byte Offset 442 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO441  ,CPU Targets Byte Offset 441 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO440  ,CPU Targets Byte Offset 440 "
group.long 0x9BC++0x03
line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447  ,CPU Targets Byte Offset 447 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO446  ,CPU Targets Byte Offset 446 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO445  ,CPU Targets Byte Offset 445 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO444  ,CPU Targets Byte Offset 444 "
else
hgroup.long 0x9A0++0x03
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hgroup.long 0x9A4++0x03
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hgroup.long 0x9A8++0x03
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hgroup.long 0x9AC++0x03
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hgroup.long 0x9B0++0x03
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hgroup.long 0x9B4++0x03
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hgroup.long 0x9B8++0x03
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hgroup.long 0x9BC++0x03
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E)
group.long 0x9C0++0x03
line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451  ,CPU Targets Byte Offset 451 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO450  ,CPU Targets Byte Offset 450 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO449  ,CPU Targets Byte Offset 449 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO448  ,CPU Targets Byte Offset 448 "
group.long 0x9C4++0x03
line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455  ,CPU Targets Byte Offset 455 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO454  ,CPU Targets Byte Offset 454 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO453  ,CPU Targets Byte Offset 453 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO452  ,CPU Targets Byte Offset 452 "
group.long 0x9C8++0x03
line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459  ,CPU Targets Byte Offset 459 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO458  ,CPU Targets Byte Offset 458 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO457  ,CPU Targets Byte Offset 457 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO456  ,CPU Targets Byte Offset 456 "
group.long 0x9CC++0x03
line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463  ,CPU Targets Byte Offset 463 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO462  ,CPU Targets Byte Offset 462 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO461  ,CPU Targets Byte Offset 461 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO460  ,CPU Targets Byte Offset 460 "
group.long 0x9D0++0x03
line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467  ,CPU Targets Byte Offset 467 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO466  ,CPU Targets Byte Offset 466 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO465  ,CPU Targets Byte Offset 465 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO464  ,CPU Targets Byte Offset 464 "
group.long 0x9D4++0x03
line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471  ,CPU Targets Byte Offset 471 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO470  ,CPU Targets Byte Offset 470 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO469  ,CPU Targets Byte Offset 469 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO468  ,CPU Targets Byte Offset 468 "
group.long 0x9D8++0x03
line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475  ,CPU Targets Byte Offset 475 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO474  ,CPU Targets Byte Offset 474 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO473  ,CPU Targets Byte Offset 473 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO472  ,CPU Targets Byte Offset 472 "
group.long 0x9DC++0x03
line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479  ,CPU Targets Byte Offset 479 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO478  ,CPU Targets Byte Offset 478 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO477  ,CPU Targets Byte Offset 477 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO476  ,CPU Targets Byte Offset 476 "
else
hgroup.long 0x9C0++0x03
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hgroup.long 0x9C4++0x03
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hgroup.long 0x9C8++0x03
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hgroup.long 0x9CC++0x03
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hgroup.long 0x9D0++0x03
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hgroup.long 0x9D4++0x03
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hgroup.long 0x9D8++0x03
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hgroup.long 0x9DC++0x03
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F)
group.long 0x9E0++0x03
line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483  ,CPU Targets Byte Offset 483 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO482  ,CPU Targets Byte Offset 482 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO481  ,CPU Targets Byte Offset 481 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO480  ,CPU Targets Byte Offset 480 "
group.long 0x9E4++0x03
line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487  ,CPU Targets Byte Offset 487 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO486  ,CPU Targets Byte Offset 486 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO485  ,CPU Targets Byte Offset 485 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO484  ,CPU Targets Byte Offset 484 "
group.long 0x9E8++0x03
line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491  ,CPU Targets Byte Offset 491 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO490  ,CPU Targets Byte Offset 490 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO489  ,CPU Targets Byte Offset 489 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO488  ,CPU Targets Byte Offset 488 "
group.long 0x9EC++0x03
line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495  ,CPU Targets Byte Offset 495 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO494  ,CPU Targets Byte Offset 494 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO493  ,CPU Targets Byte Offset 493 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO492  ,CPU Targets Byte Offset 492 "
group.long 0x9F0++0x03
line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499  ,CPU Targets Byte Offset 499 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO498  ,CPU Targets Byte Offset 498 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO497  ,CPU Targets Byte Offset 497 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO496  ,CPU Targets Byte Offset 496 "
group.long 0x9F4++0x03
line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503  ,CPU Targets Byte Offset 503 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO502  ,CPU Targets Byte Offset 502 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO501  ,CPU Targets Byte Offset 501 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO500  ,CPU Targets Byte Offset 500 "
group.long 0x9F8++0x03
line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507  ,CPU Targets Byte Offset 507 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO506  ,CPU Targets Byte Offset 506 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO505  ,CPU Targets Byte Offset 505 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO504  ,CPU Targets Byte Offset 504 "
group.long 0x9FC++0x03
line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511  ,CPU Targets Byte Offset 511 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO510  ,CPU Targets Byte Offset 510 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO509  ,CPU Targets Byte Offset 509 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO508  ,CPU Targets Byte Offset 508 "
else
hgroup.long 0x9E0++0x03
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hgroup.long 0x9E4++0x03
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hgroup.long 0x9E8++0x03
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hgroup.long 0x9EC++0x03
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hgroup.long 0x9F0++0x03
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hgroup.long 0x9F4++0x03
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hgroup.long 0x9F8++0x03
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hgroup.long 0x9FC++0x03
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0xA00++0x03
line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515  ,CPU Targets Byte Offset 515 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO514  ,CPU Targets Byte Offset 514 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO513  ,CPU Targets Byte Offset 513 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO512  ,CPU Targets Byte Offset 512 "
group.long 0xA04++0x03
line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519  ,CPU Targets Byte Offset 519 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO518  ,CPU Targets Byte Offset 518 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO517  ,CPU Targets Byte Offset 517 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO516  ,CPU Targets Byte Offset 516 "
group.long 0xA08++0x03
line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523  ,CPU Targets Byte Offset 523 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO522  ,CPU Targets Byte Offset 522 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO521  ,CPU Targets Byte Offset 521 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO520  ,CPU Targets Byte Offset 520 "
group.long 0xA0C++0x03
line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527  ,CPU Targets Byte Offset 527 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO526  ,CPU Targets Byte Offset 526 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO525  ,CPU Targets Byte Offset 525 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO524  ,CPU Targets Byte Offset 524 "
group.long 0xA10++0x03
line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531  ,CPU Targets Byte Offset 531 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO530  ,CPU Targets Byte Offset 530 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO529  ,CPU Targets Byte Offset 529 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO528  ,CPU Targets Byte Offset 528 "
group.long 0xA14++0x03
line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535  ,CPU Targets Byte Offset 535 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO534  ,CPU Targets Byte Offset 534 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO533  ,CPU Targets Byte Offset 533 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO532  ,CPU Targets Byte Offset 532 "
group.long 0xA18++0x03
line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539  ,CPU Targets Byte Offset 539 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO538  ,CPU Targets Byte Offset 538 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO537  ,CPU Targets Byte Offset 537 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO536  ,CPU Targets Byte Offset 536 "
group.long 0xA1C++0x03
line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543  ,CPU Targets Byte Offset 543 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO542  ,CPU Targets Byte Offset 542 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO541  ,CPU Targets Byte Offset 541 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO540  ,CPU Targets Byte Offset 540 "
else
hgroup.long 0xA00++0x03
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hgroup.long 0xA04++0x03
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hgroup.long 0xA08++0x03
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hgroup.long 0xA0C++0x03
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hgroup.long 0xA10++0x03
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hgroup.long 0xA14++0x03
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hgroup.long 0xA18++0x03
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hgroup.long 0xA1C++0x03
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0xA20++0x03
line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547  ,CPU Targets Byte Offset 547 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO546  ,CPU Targets Byte Offset 546 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO545  ,CPU Targets Byte Offset 545 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO544  ,CPU Targets Byte Offset 544 "
group.long 0xA24++0x03
line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551  ,CPU Targets Byte Offset 551 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO550  ,CPU Targets Byte Offset 550 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO549  ,CPU Targets Byte Offset 549 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO548  ,CPU Targets Byte Offset 548 "
group.long 0xA28++0x03
line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555  ,CPU Targets Byte Offset 555 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO554  ,CPU Targets Byte Offset 554 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO553  ,CPU Targets Byte Offset 553 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO552  ,CPU Targets Byte Offset 552 "
group.long 0xA2C++0x03
line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559  ,CPU Targets Byte Offset 559 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO558  ,CPU Targets Byte Offset 558 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO557  ,CPU Targets Byte Offset 557 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO556  ,CPU Targets Byte Offset 556 "
group.long 0xA30++0x03
line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563  ,CPU Targets Byte Offset 563 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO562  ,CPU Targets Byte Offset 562 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO561  ,CPU Targets Byte Offset 561 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO560  ,CPU Targets Byte Offset 560 "
group.long 0xA34++0x03
line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567  ,CPU Targets Byte Offset 567 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO566  ,CPU Targets Byte Offset 566 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO565  ,CPU Targets Byte Offset 565 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO564  ,CPU Targets Byte Offset 564 "
group.long 0xA38++0x03
line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571  ,CPU Targets Byte Offset 571 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO570  ,CPU Targets Byte Offset 570 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO569  ,CPU Targets Byte Offset 569 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO568  ,CPU Targets Byte Offset 568 "
group.long 0xA3C++0x03
line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575  ,CPU Targets Byte Offset 575 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO574  ,CPU Targets Byte Offset 574 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO573  ,CPU Targets Byte Offset 573 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO572  ,CPU Targets Byte Offset 572 "
else
hgroup.long 0xA20++0x03
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hgroup.long 0xA24++0x03
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hgroup.long 0xA28++0x03
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hgroup.long 0xA2C++0x03
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hgroup.long 0xA30++0x03
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hgroup.long 0xA34++0x03
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hgroup.long 0xA38++0x03
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hgroup.long 0xA3C++0x03
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0xA40++0x03
line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579  ,CPU Targets Byte Offset 579 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO578  ,CPU Targets Byte Offset 578 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO577  ,CPU Targets Byte Offset 577 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO576  ,CPU Targets Byte Offset 576 "
group.long 0xA44++0x03
line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583  ,CPU Targets Byte Offset 583 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO582  ,CPU Targets Byte Offset 582 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO581  ,CPU Targets Byte Offset 581 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO580  ,CPU Targets Byte Offset 580 "
group.long 0xA48++0x03
line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587  ,CPU Targets Byte Offset 587 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO586  ,CPU Targets Byte Offset 586 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO585  ,CPU Targets Byte Offset 585 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO584  ,CPU Targets Byte Offset 584 "
group.long 0xA4C++0x03
line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591  ,CPU Targets Byte Offset 591 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO590  ,CPU Targets Byte Offset 590 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO589  ,CPU Targets Byte Offset 589 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO588  ,CPU Targets Byte Offset 588 "
group.long 0xA50++0x03
line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595  ,CPU Targets Byte Offset 595 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO594  ,CPU Targets Byte Offset 594 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO593  ,CPU Targets Byte Offset 593 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO592  ,CPU Targets Byte Offset 592 "
group.long 0xA54++0x03
line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599  ,CPU Targets Byte Offset 599 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO598  ,CPU Targets Byte Offset 598 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO597  ,CPU Targets Byte Offset 597 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO596  ,CPU Targets Byte Offset 596 "
group.long 0xA58++0x03
line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603  ,CPU Targets Byte Offset 603 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO602  ,CPU Targets Byte Offset 602 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO601  ,CPU Targets Byte Offset 601 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO600  ,CPU Targets Byte Offset 600 "
group.long 0xA5C++0x03
line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607  ,CPU Targets Byte Offset 607 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO606  ,CPU Targets Byte Offset 606 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO605  ,CPU Targets Byte Offset 605 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO604  ,CPU Targets Byte Offset 604 "
else
hgroup.long 0xA40++0x03
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hgroup.long 0xA44++0x03
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hgroup.long 0xA48++0x03
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hgroup.long 0xA4C++0x03
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hgroup.long 0xA50++0x03
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hgroup.long 0xA54++0x03
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hgroup.long 0xA58++0x03
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hgroup.long 0xA5C++0x03
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0xA60++0x03
line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611  ,CPU Targets Byte Offset 611 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO610  ,CPU Targets Byte Offset 610 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO609  ,CPU Targets Byte Offset 609 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO608  ,CPU Targets Byte Offset 608 "
group.long 0xA64++0x03
line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615  ,CPU Targets Byte Offset 615 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO614  ,CPU Targets Byte Offset 614 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO613  ,CPU Targets Byte Offset 613 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO612  ,CPU Targets Byte Offset 612 "
group.long 0xA68++0x03
line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619  ,CPU Targets Byte Offset 619 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO618  ,CPU Targets Byte Offset 618 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO617  ,CPU Targets Byte Offset 617 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO616  ,CPU Targets Byte Offset 616 "
group.long 0xA6C++0x03
line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623  ,CPU Targets Byte Offset 623 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO622  ,CPU Targets Byte Offset 622 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO621  ,CPU Targets Byte Offset 621 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO620  ,CPU Targets Byte Offset 620 "
group.long 0xA70++0x03
line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627  ,CPU Targets Byte Offset 627 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO626  ,CPU Targets Byte Offset 626 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO625  ,CPU Targets Byte Offset 625 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO624  ,CPU Targets Byte Offset 624 "
group.long 0xA74++0x03
line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631  ,CPU Targets Byte Offset 631 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO630  ,CPU Targets Byte Offset 630 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO629  ,CPU Targets Byte Offset 629 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO628  ,CPU Targets Byte Offset 628 "
group.long 0xA78++0x03
line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635  ,CPU Targets Byte Offset 635 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO634  ,CPU Targets Byte Offset 634 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO633  ,CPU Targets Byte Offset 633 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO632  ,CPU Targets Byte Offset 632 "
group.long 0xA7C++0x03
line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639  ,CPU Targets Byte Offset 639 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO638  ,CPU Targets Byte Offset 638 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO637  ,CPU Targets Byte Offset 637 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO636  ,CPU Targets Byte Offset 636 "
else
hgroup.long 0xA60++0x03
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hgroup.long 0xA64++0x03
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hgroup.long 0xA68++0x03
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hgroup.long 0xA6C++0x03
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hgroup.long 0xA70++0x03
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hgroup.long 0xA74++0x03
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hgroup.long 0xA78++0x03
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hgroup.long 0xA7C++0x03
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0xA80++0x03
line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643  ,CPU Targets Byte Offset 643 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO642  ,CPU Targets Byte Offset 642 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO641  ,CPU Targets Byte Offset 641 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO640  ,CPU Targets Byte Offset 640 "
group.long 0xA84++0x03
line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647  ,CPU Targets Byte Offset 647 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO646  ,CPU Targets Byte Offset 646 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO645  ,CPU Targets Byte Offset 645 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO644  ,CPU Targets Byte Offset 644 "
group.long 0xA88++0x03
line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651  ,CPU Targets Byte Offset 651 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO650  ,CPU Targets Byte Offset 650 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO649  ,CPU Targets Byte Offset 649 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO648  ,CPU Targets Byte Offset 648 "
group.long 0xA8C++0x03
line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655  ,CPU Targets Byte Offset 655 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO654  ,CPU Targets Byte Offset 654 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO653  ,CPU Targets Byte Offset 653 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO652  ,CPU Targets Byte Offset 652 "
group.long 0xA90++0x03
line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659  ,CPU Targets Byte Offset 659 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO658  ,CPU Targets Byte Offset 658 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO657  ,CPU Targets Byte Offset 657 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO656  ,CPU Targets Byte Offset 656 "
group.long 0xA94++0x03
line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663  ,CPU Targets Byte Offset 663 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO662  ,CPU Targets Byte Offset 662 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO661  ,CPU Targets Byte Offset 661 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO660  ,CPU Targets Byte Offset 660 "
group.long 0xA98++0x03
line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667  ,CPU Targets Byte Offset 667 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO666  ,CPU Targets Byte Offset 666 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO665  ,CPU Targets Byte Offset 665 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO664  ,CPU Targets Byte Offset 664 "
group.long 0xA9C++0x03
line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671  ,CPU Targets Byte Offset 671 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO670  ,CPU Targets Byte Offset 670 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO669  ,CPU Targets Byte Offset 669 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO668  ,CPU Targets Byte Offset 668 "
else
hgroup.long 0xA80++0x03
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hgroup.long 0xA84++0x03
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hgroup.long 0xA88++0x03
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hgroup.long 0xA8C++0x03
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hgroup.long 0xA90++0x03
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hgroup.long 0xA94++0x03
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hgroup.long 0xA98++0x03
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hgroup.long 0xA9C++0x03
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0xAA0++0x03
line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675  ,CPU Targets Byte Offset 675 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO674  ,CPU Targets Byte Offset 674 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO673  ,CPU Targets Byte Offset 673 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO672  ,CPU Targets Byte Offset 672 "
group.long 0xAA4++0x03
line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679  ,CPU Targets Byte Offset 679 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO678  ,CPU Targets Byte Offset 678 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO677  ,CPU Targets Byte Offset 677 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO676  ,CPU Targets Byte Offset 676 "
group.long 0xAA8++0x03
line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683  ,CPU Targets Byte Offset 683 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO682  ,CPU Targets Byte Offset 682 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO681  ,CPU Targets Byte Offset 681 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO680  ,CPU Targets Byte Offset 680 "
group.long 0xAAC++0x03
line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687  ,CPU Targets Byte Offset 687 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO686  ,CPU Targets Byte Offset 686 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO685  ,CPU Targets Byte Offset 685 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO684  ,CPU Targets Byte Offset 684 "
group.long 0xAB0++0x03
line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691  ,CPU Targets Byte Offset 691 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO690  ,CPU Targets Byte Offset 690 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO689  ,CPU Targets Byte Offset 689 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO688  ,CPU Targets Byte Offset 688 "
group.long 0xAB4++0x03
line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695  ,CPU Targets Byte Offset 695 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO694  ,CPU Targets Byte Offset 694 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO693  ,CPU Targets Byte Offset 693 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO692  ,CPU Targets Byte Offset 692 "
group.long 0xAB8++0x03
line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699  ,CPU Targets Byte Offset 699 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO698  ,CPU Targets Byte Offset 698 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO697  ,CPU Targets Byte Offset 697 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO696  ,CPU Targets Byte Offset 696 "
group.long 0xABC++0x03
line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703  ,CPU Targets Byte Offset 703 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO702  ,CPU Targets Byte Offset 702 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO701  ,CPU Targets Byte Offset 701 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO700  ,CPU Targets Byte Offset 700 "
else
hgroup.long 0xAA0++0x03
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hgroup.long 0xAA4++0x03
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hgroup.long 0xAA8++0x03
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hgroup.long 0xAAC++0x03
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hgroup.long 0xAB0++0x03
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hgroup.long 0xAB4++0x03
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hgroup.long 0xAB8++0x03
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hgroup.long 0xABC++0x03
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0xAC0++0x03
line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707  ,CPU Targets Byte Offset 707 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO706  ,CPU Targets Byte Offset 706 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO705  ,CPU Targets Byte Offset 705 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO704  ,CPU Targets Byte Offset 704 "
group.long 0xAC4++0x03
line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711  ,CPU Targets Byte Offset 711 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO710  ,CPU Targets Byte Offset 710 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO709  ,CPU Targets Byte Offset 709 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO708  ,CPU Targets Byte Offset 708 "
group.long 0xAC8++0x03
line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715  ,CPU Targets Byte Offset 715 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO714  ,CPU Targets Byte Offset 714 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO713  ,CPU Targets Byte Offset 713 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO712  ,CPU Targets Byte Offset 712 "
group.long 0xACC++0x03
line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719  ,CPU Targets Byte Offset 719 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO718  ,CPU Targets Byte Offset 718 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO717  ,CPU Targets Byte Offset 717 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO716  ,CPU Targets Byte Offset 716 "
group.long 0xAD0++0x03
line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723  ,CPU Targets Byte Offset 723 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO722  ,CPU Targets Byte Offset 722 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO721  ,CPU Targets Byte Offset 721 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO720  ,CPU Targets Byte Offset 720 "
group.long 0xAD4++0x03
line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727  ,CPU Targets Byte Offset 727 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO726  ,CPU Targets Byte Offset 726 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO725  ,CPU Targets Byte Offset 725 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO724  ,CPU Targets Byte Offset 724 "
group.long 0xAD8++0x03
line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731  ,CPU Targets Byte Offset 731 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO730  ,CPU Targets Byte Offset 730 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO729  ,CPU Targets Byte Offset 729 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO728  ,CPU Targets Byte Offset 728 "
group.long 0xADC++0x03
line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735  ,CPU Targets Byte Offset 735 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO734  ,CPU Targets Byte Offset 734 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO733  ,CPU Targets Byte Offset 733 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO732  ,CPU Targets Byte Offset 732 "
else
hgroup.long 0xAC0++0x03
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hgroup.long 0xAC4++0x03
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hgroup.long 0xAC8++0x03
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hgroup.long 0xACC++0x03
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hgroup.long 0xAD0++0x03
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hgroup.long 0xAD4++0x03
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hgroup.long 0xAD8++0x03
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hgroup.long 0xADC++0x03
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0xAE0++0x03
line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739  ,CPU Targets Byte Offset 739 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO738  ,CPU Targets Byte Offset 738 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO737  ,CPU Targets Byte Offset 737 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO736  ,CPU Targets Byte Offset 736 "
group.long 0xAE4++0x03
line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743  ,CPU Targets Byte Offset 743 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO742  ,CPU Targets Byte Offset 742 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO741  ,CPU Targets Byte Offset 741 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO740  ,CPU Targets Byte Offset 740 "
group.long 0xAE8++0x03
line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747  ,CPU Targets Byte Offset 747 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO746  ,CPU Targets Byte Offset 746 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO745  ,CPU Targets Byte Offset 745 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO744  ,CPU Targets Byte Offset 744 "
group.long 0xAEC++0x03
line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751  ,CPU Targets Byte Offset 751 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO750  ,CPU Targets Byte Offset 750 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO749  ,CPU Targets Byte Offset 749 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO748  ,CPU Targets Byte Offset 748 "
group.long 0xAF0++0x03
line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755  ,CPU Targets Byte Offset 755 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO754  ,CPU Targets Byte Offset 754 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO753  ,CPU Targets Byte Offset 753 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO752  ,CPU Targets Byte Offset 752 "
group.long 0xAF4++0x03
line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759  ,CPU Targets Byte Offset 759 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO758  ,CPU Targets Byte Offset 758 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO757  ,CPU Targets Byte Offset 757 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO756  ,CPU Targets Byte Offset 756 "
group.long 0xAF8++0x03
line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763  ,CPU Targets Byte Offset 763 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO762  ,CPU Targets Byte Offset 762 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO761  ,CPU Targets Byte Offset 761 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO760  ,CPU Targets Byte Offset 760 "
group.long 0xAFC++0x03
line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767  ,CPU Targets Byte Offset 767 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO766  ,CPU Targets Byte Offset 766 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO765  ,CPU Targets Byte Offset 765 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO764  ,CPU Targets Byte Offset 764 "
else
hgroup.long 0xAE0++0x03
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hgroup.long 0xAE4++0x03
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hgroup.long 0xAE8++0x03
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hgroup.long 0xAEC++0x03
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hgroup.long 0xAF0++0x03
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hgroup.long 0xAF4++0x03
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hgroup.long 0xAF8++0x03
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hgroup.long 0xAFC++0x03
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0xB00++0x03
line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771  ,CPU Targets Byte Offset 771 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO770  ,CPU Targets Byte Offset 770 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO769  ,CPU Targets Byte Offset 769 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO768  ,CPU Targets Byte Offset 768 "
group.long 0xB04++0x03
line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775  ,CPU Targets Byte Offset 775 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO774  ,CPU Targets Byte Offset 774 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO773  ,CPU Targets Byte Offset 773 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO772  ,CPU Targets Byte Offset 772 "
group.long 0xB08++0x03
line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779  ,CPU Targets Byte Offset 779 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO778  ,CPU Targets Byte Offset 778 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO777  ,CPU Targets Byte Offset 777 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO776  ,CPU Targets Byte Offset 776 "
group.long 0xB0C++0x03
line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783  ,CPU Targets Byte Offset 783 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO782  ,CPU Targets Byte Offset 782 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO781  ,CPU Targets Byte Offset 781 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO780  ,CPU Targets Byte Offset 780 "
group.long 0xB10++0x03
line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787  ,CPU Targets Byte Offset 787 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO786  ,CPU Targets Byte Offset 786 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO785  ,CPU Targets Byte Offset 785 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO784  ,CPU Targets Byte Offset 784 "
group.long 0xB14++0x03
line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791  ,CPU Targets Byte Offset 791 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO790  ,CPU Targets Byte Offset 790 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO789  ,CPU Targets Byte Offset 789 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO788  ,CPU Targets Byte Offset 788 "
group.long 0xB18++0x03
line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795  ,CPU Targets Byte Offset 795 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO794  ,CPU Targets Byte Offset 794 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO793  ,CPU Targets Byte Offset 793 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO792  ,CPU Targets Byte Offset 792 "
group.long 0xB1C++0x03
line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799  ,CPU Targets Byte Offset 799 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO798  ,CPU Targets Byte Offset 798 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO797  ,CPU Targets Byte Offset 797 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO796  ,CPU Targets Byte Offset 796 "
else
hgroup.long 0xB00++0x03
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hgroup.long 0xB04++0x03
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hgroup.long 0xB08++0x03
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hgroup.long 0xB0C++0x03
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hgroup.long 0xB10++0x03
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hgroup.long 0xB14++0x03
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hgroup.long 0xB18++0x03
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hgroup.long 0xB1C++0x03
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0xB20++0x03
line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803  ,CPU Targets Byte Offset 803 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO802  ,CPU Targets Byte Offset 802 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO801  ,CPU Targets Byte Offset 801 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO800  ,CPU Targets Byte Offset 800 "
group.long 0xB24++0x03
line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807  ,CPU Targets Byte Offset 807 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO806  ,CPU Targets Byte Offset 806 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO805  ,CPU Targets Byte Offset 805 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO804  ,CPU Targets Byte Offset 804 "
group.long 0xB28++0x03
line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811  ,CPU Targets Byte Offset 811 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO810  ,CPU Targets Byte Offset 810 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO809  ,CPU Targets Byte Offset 809 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO808  ,CPU Targets Byte Offset 808 "
group.long 0xB2C++0x03
line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815  ,CPU Targets Byte Offset 815 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO814  ,CPU Targets Byte Offset 814 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO813  ,CPU Targets Byte Offset 813 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO812  ,CPU Targets Byte Offset 812 "
group.long 0xB30++0x03
line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819  ,CPU Targets Byte Offset 819 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO818  ,CPU Targets Byte Offset 818 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO817  ,CPU Targets Byte Offset 817 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO816  ,CPU Targets Byte Offset 816 "
group.long 0xB34++0x03
line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823  ,CPU Targets Byte Offset 823 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO822  ,CPU Targets Byte Offset 822 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO821  ,CPU Targets Byte Offset 821 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO820  ,CPU Targets Byte Offset 820 "
group.long 0xB38++0x03
line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827  ,CPU Targets Byte Offset 827 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO826  ,CPU Targets Byte Offset 826 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO825  ,CPU Targets Byte Offset 825 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO824  ,CPU Targets Byte Offset 824 "
group.long 0xB3C++0x03
line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831  ,CPU Targets Byte Offset 831 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO830  ,CPU Targets Byte Offset 830 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO829  ,CPU Targets Byte Offset 829 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO828  ,CPU Targets Byte Offset 828 "
else
hgroup.long 0xB20++0x03
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hgroup.long 0xB24++0x03
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hgroup.long 0xB28++0x03
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hgroup.long 0xB2C++0x03
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hgroup.long 0xB30++0x03
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hgroup.long 0xB34++0x03
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hgroup.long 0xB38++0x03
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hgroup.long 0xB3C++0x03
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0xB40++0x03
line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835  ,CPU Targets Byte Offset 835 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO834  ,CPU Targets Byte Offset 834 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO833  ,CPU Targets Byte Offset 833 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO832  ,CPU Targets Byte Offset 832 "
group.long 0xB44++0x03
line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839  ,CPU Targets Byte Offset 839 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO838  ,CPU Targets Byte Offset 838 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO837  ,CPU Targets Byte Offset 837 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO836  ,CPU Targets Byte Offset 836 "
group.long 0xB48++0x03
line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843  ,CPU Targets Byte Offset 843 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO842  ,CPU Targets Byte Offset 842 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO841  ,CPU Targets Byte Offset 841 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO840  ,CPU Targets Byte Offset 840 "
group.long 0xB4C++0x03
line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847  ,CPU Targets Byte Offset 847 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO846  ,CPU Targets Byte Offset 846 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO845  ,CPU Targets Byte Offset 845 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO844  ,CPU Targets Byte Offset 844 "
group.long 0xB50++0x03
line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851  ,CPU Targets Byte Offset 851 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO850  ,CPU Targets Byte Offset 850 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO849  ,CPU Targets Byte Offset 849 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO848  ,CPU Targets Byte Offset 848 "
group.long 0xB54++0x03
line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855  ,CPU Targets Byte Offset 855 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO854  ,CPU Targets Byte Offset 854 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO853  ,CPU Targets Byte Offset 853 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO852  ,CPU Targets Byte Offset 852 "
group.long 0xB58++0x03
line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859  ,CPU Targets Byte Offset 859 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO858  ,CPU Targets Byte Offset 858 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO857  ,CPU Targets Byte Offset 857 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO856  ,CPU Targets Byte Offset 856 "
group.long 0xB5C++0x03
line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863  ,CPU Targets Byte Offset 863 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO862  ,CPU Targets Byte Offset 862 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO861  ,CPU Targets Byte Offset 861 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO860  ,CPU Targets Byte Offset 860 "
else
hgroup.long 0xB40++0x03
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hgroup.long 0xB44++0x03
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hgroup.long 0xB48++0x03
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hgroup.long 0xB4C++0x03
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hgroup.long 0xB50++0x03
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hgroup.long 0xB54++0x03
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hgroup.long 0xB58++0x03
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hgroup.long 0xB5C++0x03
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0xB60++0x03
line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867  ,CPU Targets Byte Offset 867 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO866  ,CPU Targets Byte Offset 866 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO865  ,CPU Targets Byte Offset 865 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO864  ,CPU Targets Byte Offset 864 "
group.long 0xB64++0x03
line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871  ,CPU Targets Byte Offset 871 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO870  ,CPU Targets Byte Offset 870 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO869  ,CPU Targets Byte Offset 869 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO868  ,CPU Targets Byte Offset 868 "
group.long 0xB68++0x03
line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875  ,CPU Targets Byte Offset 875 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO874  ,CPU Targets Byte Offset 874 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO873  ,CPU Targets Byte Offset 873 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO872  ,CPU Targets Byte Offset 872 "
group.long 0xB6C++0x03
line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879  ,CPU Targets Byte Offset 879 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO878  ,CPU Targets Byte Offset 878 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO877  ,CPU Targets Byte Offset 877 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO876  ,CPU Targets Byte Offset 876 "
group.long 0xB70++0x03
line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883  ,CPU Targets Byte Offset 883 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO882  ,CPU Targets Byte Offset 882 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO881  ,CPU Targets Byte Offset 881 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO880  ,CPU Targets Byte Offset 880 "
group.long 0xB74++0x03
line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887  ,CPU Targets Byte Offset 887 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO886  ,CPU Targets Byte Offset 886 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO885  ,CPU Targets Byte Offset 885 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO884  ,CPU Targets Byte Offset 884 "
group.long 0xB78++0x03
line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891  ,CPU Targets Byte Offset 891 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO890  ,CPU Targets Byte Offset 890 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO889  ,CPU Targets Byte Offset 889 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO888  ,CPU Targets Byte Offset 888 "
group.long 0xB7C++0x03
line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895  ,CPU Targets Byte Offset 895 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO894  ,CPU Targets Byte Offset 894 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO893  ,CPU Targets Byte Offset 893 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO892  ,CPU Targets Byte Offset 892 "
else
hgroup.long 0xB60++0x03
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hgroup.long 0xB64++0x03
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hgroup.long 0xB68++0x03
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hgroup.long 0xB6C++0x03
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hgroup.long 0xB70++0x03
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hgroup.long 0xB74++0x03
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hgroup.long 0xB78++0x03
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hgroup.long 0xB7C++0x03
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0xB80++0x03
line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899  ,CPU Targets Byte Offset 899 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO898  ,CPU Targets Byte Offset 898 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO897  ,CPU Targets Byte Offset 897 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO896  ,CPU Targets Byte Offset 896 "
group.long 0xB84++0x03
line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903  ,CPU Targets Byte Offset 903 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO902  ,CPU Targets Byte Offset 902 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO901  ,CPU Targets Byte Offset 901 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO900  ,CPU Targets Byte Offset 900 "
group.long 0xB88++0x03
line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907  ,CPU Targets Byte Offset 907 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO906  ,CPU Targets Byte Offset 906 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO905  ,CPU Targets Byte Offset 905 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO904  ,CPU Targets Byte Offset 904 "
group.long 0xB8C++0x03
line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911  ,CPU Targets Byte Offset 911 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO910  ,CPU Targets Byte Offset 910 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO909  ,CPU Targets Byte Offset 909 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO908  ,CPU Targets Byte Offset 908 "
group.long 0xB90++0x03
line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915  ,CPU Targets Byte Offset 915 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO914  ,CPU Targets Byte Offset 914 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO913  ,CPU Targets Byte Offset 913 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO912  ,CPU Targets Byte Offset 912 "
group.long 0xB94++0x03
line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919  ,CPU Targets Byte Offset 919 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO918  ,CPU Targets Byte Offset 918 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO917  ,CPU Targets Byte Offset 917 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO916  ,CPU Targets Byte Offset 916 "
group.long 0xB98++0x03
line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923  ,CPU Targets Byte Offset 923 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO922  ,CPU Targets Byte Offset 922 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO921  ,CPU Targets Byte Offset 921 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO920  ,CPU Targets Byte Offset 920 "
group.long 0xB9C++0x03
line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927  ,CPU Targets Byte Offset 927 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO926  ,CPU Targets Byte Offset 926 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO925  ,CPU Targets Byte Offset 925 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO924  ,CPU Targets Byte Offset 924 "
else
hgroup.long 0xB80++0x03
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hgroup.long 0xB84++0x03
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hgroup.long 0xB88++0x03
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hgroup.long 0xB8C++0x03
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hgroup.long 0xB90++0x03
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hgroup.long 0xB94++0x03
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hgroup.long 0xB98++0x03
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hgroup.long 0xB9C++0x03
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0xBA0++0x03
line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931  ,CPU Targets Byte Offset 931 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO930  ,CPU Targets Byte Offset 930 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO929  ,CPU Targets Byte Offset 929 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO928  ,CPU Targets Byte Offset 928 "
group.long 0xBA4++0x03
line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935  ,CPU Targets Byte Offset 935 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO934  ,CPU Targets Byte Offset 934 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO933  ,CPU Targets Byte Offset 933 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO932  ,CPU Targets Byte Offset 932 "
group.long 0xBA8++0x03
line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939  ,CPU Targets Byte Offset 939 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO938  ,CPU Targets Byte Offset 938 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO937  ,CPU Targets Byte Offset 937 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO936  ,CPU Targets Byte Offset 936 "
group.long 0xBAC++0x03
line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943  ,CPU Targets Byte Offset 943 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO942  ,CPU Targets Byte Offset 942 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO941  ,CPU Targets Byte Offset 941 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO940  ,CPU Targets Byte Offset 940 "
group.long 0xBB0++0x03
line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947  ,CPU Targets Byte Offset 947 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO946  ,CPU Targets Byte Offset 946 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO945  ,CPU Targets Byte Offset 945 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO944  ,CPU Targets Byte Offset 944 "
group.long 0xBB4++0x03
line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951  ,CPU Targets Byte Offset 951 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO950  ,CPU Targets Byte Offset 950 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO949  ,CPU Targets Byte Offset 949 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO948  ,CPU Targets Byte Offset 948 "
group.long 0xBB8++0x03
line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955  ,CPU Targets Byte Offset 955 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO954  ,CPU Targets Byte Offset 954 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO953  ,CPU Targets Byte Offset 953 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO952  ,CPU Targets Byte Offset 952 "
group.long 0xBBC++0x03
line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959  ,CPU Targets Byte Offset 959 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO958  ,CPU Targets Byte Offset 958 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO957  ,CPU Targets Byte Offset 957 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO956  ,CPU Targets Byte Offset 956 "
else
hgroup.long 0xBA0++0x03
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hgroup.long 0xBA4++0x03
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hgroup.long 0xBA8++0x03
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hgroup.long 0xBAC++0x03
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hgroup.long 0xBB0++0x03
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hgroup.long 0xBB4++0x03
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hgroup.long 0xBB8++0x03
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hgroup.long 0xBBC++0x03
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0xBC0++0x03
line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963  ,CPU Targets Byte Offset 963 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO962  ,CPU Targets Byte Offset 962 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO961  ,CPU Targets Byte Offset 961 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO960  ,CPU Targets Byte Offset 960 "
group.long 0xBC4++0x03
line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967  ,CPU Targets Byte Offset 967 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO966  ,CPU Targets Byte Offset 966 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO965  ,CPU Targets Byte Offset 965 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO964  ,CPU Targets Byte Offset 964 "
group.long 0xBC8++0x03
line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971  ,CPU Targets Byte Offset 971 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO970  ,CPU Targets Byte Offset 970 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO969  ,CPU Targets Byte Offset 969 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO968  ,CPU Targets Byte Offset 968 "
group.long 0xBCC++0x03
line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975  ,CPU Targets Byte Offset 975 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO974  ,CPU Targets Byte Offset 974 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO973  ,CPU Targets Byte Offset 973 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO972  ,CPU Targets Byte Offset 972 "
group.long 0xBD0++0x03
line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979  ,CPU Targets Byte Offset 979 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO978  ,CPU Targets Byte Offset 978 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO977  ,CPU Targets Byte Offset 977 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO976  ,CPU Targets Byte Offset 976 "
group.long 0xBD4++0x03
line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983  ,CPU Targets Byte Offset 983 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO982  ,CPU Targets Byte Offset 982 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO981  ,CPU Targets Byte Offset 981 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO980  ,CPU Targets Byte Offset 980 "
group.long 0xBD8++0x03
line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987  ,CPU Targets Byte Offset 987 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO986  ,CPU Targets Byte Offset 986 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO985  ,CPU Targets Byte Offset 985 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO984  ,CPU Targets Byte Offset 984 "
group.long 0xBDC++0x03
line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991  ,CPU Targets Byte Offset 991 "
hexmask.long.byte 0x00 16.--23. 1. "  CPUTBO990  ,CPU Targets Byte Offset 990 "
hexmask.long.byte 0x00 8.--15. 1. "  CPUTBO989  ,CPU Targets Byte Offset 989 "
hexmask.long.byte 0x00 0.--7. 1. "  CPUTBO988  ,CPU Targets Byte Offset 988 "
else
hgroup.long 0xBC0++0x03
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hgroup.long 0xBC4++0x03
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hgroup.long 0xBC8++0x03
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hgroup.long 0xBCC++0x03
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hgroup.long 0xBD0++0x03
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hgroup.long 0xBD4++0x03
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hgroup.long 0xBD8++0x03
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hgroup.long 0xBDC++0x03
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
else
hgroup.long 0x800++0x03
hide.long 0x00 "GICD_ITARGETSR0  ,Interrupt Processor Targets Register 0  "
hgroup.long 0x804++0x03
hide.long 0x00 "GICD_ITARGETSR1  ,Interrupt Processor Targets Register 1  "
hgroup.long 0x808++0x03
hide.long 0x00 "GICD_ITARGETSR2  ,Interrupt Processor Targets Register 2  "
hgroup.long 0x80C++0x03
hide.long 0x00 "GICD_ITARGETSR3  ,Interrupt Processor Targets Register 3  "
hgroup.long 0x810++0x03
hide.long 0x00 "GICD_ITARGETSR4  ,Interrupt Processor Targets Register 4  "
hgroup.long 0x814++0x03
hide.long 0x00 "GICD_ITARGETSR5  ,Interrupt Processor Targets Register 5  "
hgroup.long 0x818++0x03
hide.long 0x00 "GICD_ITARGETSR6  ,Interrupt Processor Targets Register 6  "
hgroup.long 0x81C++0x03
hide.long 0x00 "GICD_ITARGETSR7  ,Interrupt Processor Targets Register 7  "
hgroup.long 0x820++0x03
hide.long 0x00 "GICD_ITARGETSR8  ,Interrupt Processor Targets Register 8  "
hgroup.long 0x824++0x03
hide.long 0x00 "GICD_ITARGETSR9  ,Interrupt Processor Targets Register 9  "
hgroup.long 0x828++0x03
hide.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 "
hgroup.long 0x82C++0x03
hide.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 "
hgroup.long 0x830++0x03
hide.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 "
hgroup.long 0x834++0x03
hide.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 "
hgroup.long 0x838++0x03
hide.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 "
hgroup.long 0x83C++0x03
hide.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 "
hgroup.long 0x840++0x03
hide.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 "
hgroup.long 0x844++0x03
hide.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 "
hgroup.long 0x848++0x03
hide.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 "
hgroup.long 0x84C++0x03
hide.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 "
hgroup.long 0x850++0x03
hide.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 "
hgroup.long 0x854++0x03
hide.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 "
hgroup.long 0x858++0x03
hide.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 "
hgroup.long 0x85C++0x03
hide.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 "
hgroup.long 0x860++0x03
hide.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 "
hgroup.long 0x864++0x03
hide.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 "
hgroup.long 0x868++0x03
hide.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 "
hgroup.long 0x86C++0x03
hide.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 "
hgroup.long 0x870++0x03
hide.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 "
hgroup.long 0x874++0x03
hide.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 "
hgroup.long 0x878++0x03
hide.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 "
hgroup.long 0x87C++0x03
hide.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 "
hgroup.long 0x880++0x03
hide.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 "
hgroup.long 0x884++0x03
hide.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 "
hgroup.long 0x888++0x03
hide.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 "
hgroup.long 0x88C++0x03
hide.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 "
hgroup.long 0x890++0x03
hide.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 "
hgroup.long 0x894++0x03
hide.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 "
hgroup.long 0x898++0x03
hide.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 "
hgroup.long 0x89C++0x03
hide.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 "
hgroup.long 0x8A0++0x03
hide.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 "
hgroup.long 0x8A4++0x03
hide.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 "
hgroup.long 0x8A8++0x03
hide.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 "
hgroup.long 0x8AC++0x03
hide.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 "
hgroup.long 0x8B0++0x03
hide.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 "
hgroup.long 0x8B4++0x03
hide.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 "
hgroup.long 0x8B8++0x03
hide.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 "
hgroup.long 0x8BC++0x03
hide.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 "
hgroup.long 0x8C0++0x03
hide.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 "
hgroup.long 0x8C4++0x03
hide.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 "
hgroup.long 0x8C8++0x03
hide.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 "
hgroup.long 0x8CC++0x03
hide.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 "
hgroup.long 0x8D0++0x03
hide.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 "
hgroup.long 0x8D4++0x03
hide.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 "
hgroup.long 0x8D8++0x03
hide.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 "
hgroup.long 0x8DC++0x03
hide.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 "
hgroup.long 0x8E0++0x03
hide.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 "
hgroup.long 0x8E4++0x03
hide.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 "
hgroup.long 0x8E8++0x03
hide.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 "
hgroup.long 0x8EC++0x03
hide.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 "
hgroup.long 0x8F0++0x03
hide.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 "
hgroup.long 0x8F4++0x03
hide.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 "
hgroup.long 0x8F8++0x03
hide.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 "
hgroup.long 0x8FC++0x03
hide.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 "
hgroup.long 0x900++0x03
hide.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 "
hgroup.long 0x904++0x03
hide.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 "
hgroup.long 0x908++0x03
hide.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 "
hgroup.long 0x90C++0x03
hide.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 "
hgroup.long 0x910++0x03
hide.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 "
hgroup.long 0x914++0x03
hide.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 "
hgroup.long 0x918++0x03
hide.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 "
hgroup.long 0x91C++0x03
hide.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 "
hgroup.long 0x920++0x03
hide.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 "
hgroup.long 0x924++0x03
hide.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 "
hgroup.long 0x928++0x03
hide.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 "
hgroup.long 0x92C++0x03
hide.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 "
hgroup.long 0x930++0x03
hide.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 "
hgroup.long 0x934++0x03
hide.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 "
hgroup.long 0x938++0x03
hide.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 "
hgroup.long 0x93C++0x03
hide.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 "
hgroup.long 0x940++0x03
hide.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 "
hgroup.long 0x944++0x03
hide.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 "
hgroup.long 0x948++0x03
hide.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 "
hgroup.long 0x94C++0x03
hide.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 "
hgroup.long 0x950++0x03
hide.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 "
hgroup.long 0x954++0x03
hide.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 "
hgroup.long 0x958++0x03
hide.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 "
hgroup.long 0x95C++0x03
hide.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 "
hgroup.long 0x960++0x03
hide.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 "
hgroup.long 0x964++0x03
hide.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 "
hgroup.long 0x968++0x03
hide.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 "
hgroup.long 0x96C++0x03
hide.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 "
hgroup.long 0x970++0x03
hide.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 "
hgroup.long 0x974++0x03
hide.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 "
hgroup.long 0x978++0x03
hide.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 "
hgroup.long 0x97C++0x03
hide.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 "
hgroup.long 0x980++0x03
hide.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 "
hgroup.long 0x984++0x03
hide.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 "
hgroup.long 0x988++0x03
hide.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 "
hgroup.long 0x98C++0x03
hide.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 "
hgroup.long 0x990++0x03
hide.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100"
hgroup.long 0x994++0x03
hide.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101"
hgroup.long 0x998++0x03
hide.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102"
hgroup.long 0x99C++0x03
hide.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103"
hgroup.long 0x9A0++0x03
hide.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104"
hgroup.long 0x9A4++0x03
hide.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105"
hgroup.long 0x9A8++0x03
hide.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106"
hgroup.long 0x9AC++0x03
hide.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107"
hgroup.long 0x9B0++0x03
hide.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108"
hgroup.long 0x9B4++0x03
hide.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109"
hgroup.long 0x9B8++0x03
hide.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110"
hgroup.long 0x9BC++0x03
hide.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111"
hgroup.long 0x9C0++0x03
hide.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112"
hgroup.long 0x9C4++0x03
hide.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113"
hgroup.long 0x9C8++0x03
hide.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114"
hgroup.long 0x9CC++0x03
hide.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115"
hgroup.long 0x9D0++0x03
hide.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116"
hgroup.long 0x9D4++0x03
hide.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117"
hgroup.long 0x9D8++0x03
hide.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118"
hgroup.long 0x9DC++0x03
hide.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119"
hgroup.long 0x9E0++0x03
hide.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120"
hgroup.long 0x9E4++0x03
hide.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121"
hgroup.long 0x9E8++0x03
hide.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122"
hgroup.long 0x9EC++0x03
hide.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123"
hgroup.long 0x9F0++0x03
hide.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124"
hgroup.long 0x9F4++0x03
hide.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125"
hgroup.long 0x9F8++0x03
hide.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126"
hgroup.long 0x9FC++0x03
hide.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127"
hgroup.long 0xA00++0x03
hide.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128"
hgroup.long 0xA04++0x03
hide.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129"
hgroup.long 0xA08++0x03
hide.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130"
hgroup.long 0xA0C++0x03
hide.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131"
hgroup.long 0xA10++0x03
hide.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132"
hgroup.long 0xA14++0x03
hide.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133"
hgroup.long 0xA18++0x03
hide.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134"
hgroup.long 0xA1C++0x03
hide.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135"
hgroup.long 0xA20++0x03
hide.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136"
hgroup.long 0xA24++0x03
hide.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137"
hgroup.long 0xA28++0x03
hide.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138"
hgroup.long 0xA2C++0x03
hide.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139"
hgroup.long 0xA30++0x03
hide.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140"
hgroup.long 0xA34++0x03
hide.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141"
hgroup.long 0xA38++0x03
hide.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142"
hgroup.long 0xA3C++0x03
hide.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143"
hgroup.long 0xA40++0x03
hide.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144"
hgroup.long 0xA44++0x03
hide.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145"
hgroup.long 0xA48++0x03
hide.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146"
hgroup.long 0xA4C++0x03
hide.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147"
hgroup.long 0xA50++0x03
hide.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148"
hgroup.long 0xA54++0x03
hide.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149"
hgroup.long 0xA58++0x03
hide.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150"
hgroup.long 0xA5C++0x03
hide.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151"
hgroup.long 0xA60++0x03
hide.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152"
hgroup.long 0xA64++0x03
hide.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153"
hgroup.long 0xA68++0x03
hide.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154"
hgroup.long 0xA6C++0x03
hide.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155"
hgroup.long 0xA70++0x03
hide.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156"
hgroup.long 0xA74++0x03
hide.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157"
hgroup.long 0xA78++0x03
hide.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158"
hgroup.long 0xA7C++0x03
hide.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159"
hgroup.long 0xA80++0x03
hide.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160"
hgroup.long 0xA84++0x03
hide.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161"
hgroup.long 0xA88++0x03
hide.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162"
hgroup.long 0xA8C++0x03
hide.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163"
hgroup.long 0xA90++0x03
hide.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164"
hgroup.long 0xA94++0x03
hide.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165"
hgroup.long 0xA98++0x03
hide.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166"
hgroup.long 0xA9C++0x03
hide.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167"
hgroup.long 0xAA0++0x03
hide.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168"
hgroup.long 0xAA4++0x03
hide.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169"
hgroup.long 0xAA8++0x03
hide.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170"
hgroup.long 0xAAC++0x03
hide.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171"
hgroup.long 0xAB0++0x03
hide.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172"
hgroup.long 0xAB4++0x03
hide.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173"
hgroup.long 0xAB8++0x03
hide.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174"
hgroup.long 0xABC++0x03
hide.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175"
hgroup.long 0xAC0++0x03
hide.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176"
hgroup.long 0xAC4++0x03
hide.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177"
hgroup.long 0xAC8++0x03
hide.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178"
hgroup.long 0xACC++0x03
hide.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179"
hgroup.long 0xAD0++0x03
hide.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180"
hgroup.long 0xAD4++0x03
hide.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181"
hgroup.long 0xAD8++0x03
hide.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182"
hgroup.long 0xADC++0x03
hide.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183"
hgroup.long 0xAE0++0x03
hide.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184"
hgroup.long 0xAE4++0x03
hide.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185"
hgroup.long 0xAE8++0x03
hide.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186"
hgroup.long 0xAEC++0x03
hide.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187"
hgroup.long 0xAF0++0x03
hide.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188"
hgroup.long 0xAF4++0x03
hide.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189"
hgroup.long 0xAF8++0x03
hide.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190"
hgroup.long 0xAFC++0x03
hide.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191"
hgroup.long 0xB00++0x03
hide.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192"
hgroup.long 0xB04++0x03
hide.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193"
hgroup.long 0xB08++0x03
hide.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194"
hgroup.long 0xB0C++0x03
hide.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195"
hgroup.long 0xB10++0x03
hide.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196"
hgroup.long 0xB14++0x03
hide.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197"
hgroup.long 0xB18++0x03
hide.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198"
hgroup.long 0xB1C++0x03
hide.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199"
hgroup.long 0xB20++0x03
hide.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200"
hgroup.long 0xB24++0x03
hide.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201"
hgroup.long 0xB28++0x03
hide.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202"
hgroup.long 0xB2C++0x03
hide.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203"
hgroup.long 0xB30++0x03
hide.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204"
hgroup.long 0xB34++0x03
hide.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205"
hgroup.long 0xB38++0x03
hide.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206"
hgroup.long 0xB3C++0x03
hide.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207"
hgroup.long 0xB40++0x03
hide.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208"
hgroup.long 0xB44++0x03
hide.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209"
hgroup.long 0xB48++0x03
hide.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210"
hgroup.long 0xB4C++0x03
hide.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211"
hgroup.long 0xB50++0x03
hide.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212"
hgroup.long 0xB54++0x03
hide.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213"
hgroup.long 0xB58++0x03
hide.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214"
hgroup.long 0xB5C++0x03
hide.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215"
hgroup.long 0xB60++0x03
hide.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216"
hgroup.long 0xB64++0x03
hide.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217"
hgroup.long 0xB68++0x03
hide.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218"
hgroup.long 0xB6C++0x03
hide.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219"
hgroup.long 0xB70++0x03
hide.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220"
hgroup.long 0xB74++0x03
hide.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221"
hgroup.long 0xB78++0x03
hide.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222"
hgroup.long 0xB7C++0x03
hide.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223"
hgroup.long 0xB80++0x03
hide.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224"
hgroup.long 0xB84++0x03
hide.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225"
hgroup.long 0xB88++0x03
hide.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226"
hgroup.long 0xB8C++0x03
hide.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227"
hgroup.long 0xB90++0x03
hide.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228"
hgroup.long 0xB94++0x03
hide.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229"
hgroup.long 0xB98++0x03
hide.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230"
hgroup.long 0xB9C++0x03
hide.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231"
hgroup.long 0xBA0++0x03
hide.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232"
hgroup.long 0xBA4++0x03
hide.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233"
hgroup.long 0xBA8++0x03
hide.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234"
hgroup.long 0xBAC++0x03
hide.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235"
hgroup.long 0xBB0++0x03
hide.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236"
hgroup.long 0xBB4++0x03
hide.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237"
hgroup.long 0xBB8++0x03
hide.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238"
hgroup.long 0xBBC++0x03
hide.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239"
hgroup.long 0xBC0++0x03
hide.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240"
hgroup.long 0xBC4++0x03
hide.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241"
hgroup.long 0xBC8++0x03
hide.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242"
hgroup.long 0xBCC++0x03
hide.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243"
hgroup.long 0xBD0++0x03
hide.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244"
hgroup.long 0xBD4++0x03
hide.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245"
hgroup.long 0xBD8++0x03
hide.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246"
hgroup.long 0xBDC++0x03
hide.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247"
endif
tree.end
width 14.
tree "Configuration Registers"
rgroup.long 0xC00++0x03
line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SGI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SGI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SGI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SGI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SGI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SGI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SGI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SGI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SGI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SGI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SGI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SGI)" "Level,Edge"
group.long 0xC04++0x03
line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (PPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (PPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (PPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (PPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (PPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (PPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (PPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (PPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (PPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (PPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (PPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (PPI)" "Level,Edge"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1)
group.long 0xC08++0x03
line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC0C++0x03
line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC08++0x03
hide.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2"
hgroup.long 0xC0C++0x03
hide.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x2)
group.long 0xC10++0x03
line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC14++0x03
line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC10++0x03
hide.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4"
hgroup.long 0xC14++0x03
hide.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x3)
group.long 0xC18++0x03
line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC1C++0x03
line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC18++0x03
hide.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6"
hgroup.long 0xC1C++0x03
hide.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x4)
group.long 0xC20++0x03
line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC24++0x03
line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC20++0x03
hide.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8"
hgroup.long 0xC24++0x03
hide.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x5)
group.long 0xC28++0x03
line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC2C++0x03
line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC28++0x03
hide.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10"
hgroup.long 0xC2C++0x03
hide.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x6)
group.long 0xC30++0x03
line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC34++0x03
line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC30++0x03
hide.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12"
hgroup.long 0xC34++0x03
hide.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x7)
group.long 0xC38++0x03
line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC3C++0x03
line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC38++0x03
hide.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14"
hgroup.long 0xC3C++0x03
hide.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x8)
group.long 0xC40++0x03
line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC44++0x03
line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC40++0x03
hide.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16"
hgroup.long 0xC44++0x03
hide.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x9)
group.long 0xC48++0x03
line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC4C++0x03
line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC48++0x03
hide.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18"
hgroup.long 0xC4C++0x03
hide.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xA)
group.long 0xC50++0x03
line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC54++0x03
line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC50++0x03
hide.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20"
hgroup.long 0xC54++0x03
hide.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xB)
group.long 0xC58++0x03
line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC5C++0x03
line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC58++0x03
hide.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22"
hgroup.long 0xC5C++0x03
hide.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xC)
group.long 0xC60++0x03
line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC64++0x03
line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC60++0x03
hide.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24"
hgroup.long 0xC64++0x03
hide.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xD)
group.long 0xC68++0x03
line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC6C++0x03
line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC68++0x03
hide.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26"
hgroup.long 0xC6C++0x03
hide.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xE)
group.long 0xC70++0x03
line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC74++0x03
line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC70++0x03
hide.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28"
hgroup.long 0xC74++0x03
hide.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0xF)
group.long 0xC78++0x03
line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC7C++0x03
line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC78++0x03
hide.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30"
hgroup.long 0xC7C++0x03
hide.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10)
group.long 0xC80++0x03
line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC84++0x03
line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC80++0x03
hide.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32"
hgroup.long 0xC84++0x03
hide.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11)
group.long 0xC88++0x03
line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC8C++0x03
line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC88++0x03
hide.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34"
hgroup.long 0xC8C++0x03
hide.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12)
group.long 0xC90++0x03
line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC94++0x03
line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC90++0x03
hide.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36"
hgroup.long 0xC94++0x03
hide.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13)
group.long 0xC98++0x03
line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xC9C++0x03
line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xC98++0x03
hide.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38"
hgroup.long 0xC9C++0x03
hide.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14)
group.long 0xCA0++0x03
line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCA4++0x03
line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCA0++0x03
hide.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40"
hgroup.long 0xCA4++0x03
hide.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15)
group.long 0xCA8++0x03
line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCAC++0x03
line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCA8++0x03
hide.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42"
hgroup.long 0xCAC++0x03
hide.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16)
group.long 0xCB0++0x03
line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCB4++0x03
line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCB0++0x03
hide.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44"
hgroup.long 0xCB4++0x03
hide.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17)
group.long 0xCB8++0x03
line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCBC++0x03
line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCB8++0x03
hide.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46"
hgroup.long 0xCBC++0x03
hide.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18)
group.long 0xCC0++0x03
line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCC4++0x03
line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCC0++0x03
hide.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48"
hgroup.long 0xCC4++0x03
hide.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19)
group.long 0xCC8++0x03
line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCCC++0x03
line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCC8++0x03
hide.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50"
hgroup.long 0xCCC++0x03
hide.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1A)
group.long 0xCD0++0x03
line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCD4++0x03
line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCD0++0x03
hide.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52"
hgroup.long 0xCD4++0x03
hide.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B)
group.long 0xCD8++0x03
line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCDC++0x03
line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCD8++0x03
hide.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54"
hgroup.long 0xCDC++0x03
hide.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C)
group.long 0xCE0++0x03
line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCE4++0x03
line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCE0++0x03
hide.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56"
hgroup.long 0xCE4++0x03
hide.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D)
group.long 0xCE8++0x03
line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCEC++0x03
line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCE8++0x03
hide.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58"
hgroup.long 0xCEC++0x03
hide.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59"
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E)
group.long 0xCF0++0x03
line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
group.long 0xCF4++0x03
line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15 (SPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14 ,Interrupt Configuration 14 (SPI)" "Level,Edge"
bitfld.long 0x00 27. "  ICF13 ,Interrupt Configuration 13 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12 (SPI)" "Level,Edge"
bitfld.long 0x00 23. "  ICF11 ,Interrupt Configuration 11 (SPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10 ,Interrupt Configuration 10 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 19. " ICF9  ,Interrupt Configuration 9 (SPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8  ,Interrupt Configuration 8 (SPI)" "Level,Edge"
bitfld.long 0x00 15. "  ICF7  ,Interrupt Configuration 7 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 13. " ICF6  ,Interrupt Configuration 6 (SPI)" "Level,Edge"
bitfld.long 0x00 11. "  ICF5  ,Interrupt Configuration 5 (SPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4  ,Interrupt Configuration 4 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 7. " ICF3  ,Interrupt Configuration 3 (SPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2  ,Interrupt Configuration 2 (SPI)" "Level,Edge"
bitfld.long 0x00 3. "  ICF1  ,Interrupt Configuration 1 (SPI)" "Level,Edge"
textline "                       "
bitfld.long 0x00 1. " ICF0  ,Interrupt Configuration 0 (SPI)" "Level,Edge"
else
hgroup.long 0xCF0++0x03
hide.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60"
hgroup.long 0xCF4++0x03
hide.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61"
endif
tree.end
width 17.
tree "Interrupt Group Modifier Registers"
hgroup.long 0x0D00++0x03
hide.long 0x0 "GICD_IGRPMODR0,Interrupt Group Modifier Register 0"
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
textline "                          "
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D00))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01))
group.long 0x0D04++0x03
line.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
bitfld.long 0x00 31. " GMB63  ,Group Modifier Bit 63" "0,1"
bitfld.long 0x00 30. "  GMB62  ,Group Modifier Bit 62" "0,1"
bitfld.long 0x00 29. "  GMB61  ,Group Modifier Bit 61" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB60  ,Group Modifier Bit 60" "0,1"
bitfld.long 0x00 27. "  GMB59  ,Group Modifier Bit 59" "0,1"
bitfld.long 0x00 26. "  GMB58  ,Group Modifier Bit 58" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB57  ,Group Modifier Bit 57" "0,1"
bitfld.long 0x00 24. "  GMB56  ,Group Modifier Bit 56" "0,1"
bitfld.long 0x00 23. "  GMB55  ,Group Modifier Bit 55" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB54  ,Group Modifier Bit 54" "0,1"
bitfld.long 0x00 21. "  GMB53  ,Group Modifier Bit 53" "0,1"
bitfld.long 0x00 20. "  GMB52  ,Group Modifier Bit 52" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB51  ,Group Modifier Bit 51" "0,1"
bitfld.long 0x00 18. "  GMB50  ,Group Modifier Bit 50" "0,1"
bitfld.long 0x00 17. "  GMB49  ,Group Modifier Bit 49" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB48  ,Group Modifier Bit 48" "0,1"
bitfld.long 0x00 15. "  GMB47  ,Group Modifier Bit 47" "0,1"
bitfld.long 0x00 14. "  GMB46  ,Group Modifier Bit 46" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB45  ,Group Modifier Bit 45" "0,1"
bitfld.long 0x00 12. "  GMB44  ,Group Modifier Bit 44" "0,1"
bitfld.long 0x00 11. "  GMB43  ,Group Modifier Bit 43" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB42  ,Group Modifier Bit 42" "0,1"
bitfld.long 0x00 9. "  GMB41  ,Group Modifier Bit 41" "0,1"
bitfld.long 0x00 8. "  GMB40  ,Group Modifier Bit 40" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB39  ,Group Modifier Bit 39" "0,1"
bitfld.long 0x00 6. "  GMB38  ,Group Modifier Bit 38" "0,1"
bitfld.long 0x00 5. "  GMB37  ,Group Modifier Bit 37" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB36  ,Group Modifier Bit 36" "0,1"
bitfld.long 0x00 3. "  GMB35  ,Group Modifier Bit 35" "0,1"
bitfld.long 0x00 2. "  GMB34  ,Group Modifier Bit 34" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB33  ,Group Modifier Bit 33" "0,1"
bitfld.long 0x00 0. "  GMB32  ,Group Modifier Bit 32" "0,1"
else
hgroup.long 0x0D04++0x03
hide.long 0x0 "GICD_IGRPMODR1,Interrupt Group Modifier Register 1"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D08))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x02))
group.long 0x0D08++0x03
line.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
bitfld.long 0x00 31. " GMB95  ,Group Modifier Bit 95" "0,1"
bitfld.long 0x00 30. "  GMB94  ,Group Modifier Bit 94" "0,1"
bitfld.long 0x00 29. "  GMB93  ,Group Modifier Bit 93" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB92  ,Group Modifier Bit 92" "0,1"
bitfld.long 0x00 27. "  GMB91  ,Group Modifier Bit 91" "0,1"
bitfld.long 0x00 26. "  GMB90  ,Group Modifier Bit 90" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB89  ,Group Modifier Bit 89" "0,1"
bitfld.long 0x00 24. "  GMB88  ,Group Modifier Bit 88" "0,1"
bitfld.long 0x00 23. "  GMB87  ,Group Modifier Bit 87" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB86  ,Group Modifier Bit 86" "0,1"
bitfld.long 0x00 21. "  GMB85  ,Group Modifier Bit 85" "0,1"
bitfld.long 0x00 20. "  GMB84  ,Group Modifier Bit 84" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB83  ,Group Modifier Bit 83" "0,1"
bitfld.long 0x00 18. "  GMB82  ,Group Modifier Bit 82" "0,1"
bitfld.long 0x00 17. "  GMB81  ,Group Modifier Bit 81" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB80  ,Group Modifier Bit 80" "0,1"
bitfld.long 0x00 15. "  GMB79  ,Group Modifier Bit 79" "0,1"
bitfld.long 0x00 14. "  GMB78  ,Group Modifier Bit 78" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB77  ,Group Modifier Bit 77" "0,1"
bitfld.long 0x00 12. "  GMB76  ,Group Modifier Bit 76" "0,1"
bitfld.long 0x00 11. "  GMB75  ,Group Modifier Bit 75" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB74  ,Group Modifier Bit 74" "0,1"
bitfld.long 0x00 9. "  GMB73  ,Group Modifier Bit 73" "0,1"
bitfld.long 0x00 8. "  GMB72  ,Group Modifier Bit 72" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB71  ,Group Modifier Bit 71" "0,1"
bitfld.long 0x00 6. "  GMB70  ,Group Modifier Bit 70" "0,1"
bitfld.long 0x00 5. "  GMB69  ,Group Modifier Bit 69" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB68  ,Group Modifier Bit 68" "0,1"
bitfld.long 0x00 3. "  GMB67  ,Group Modifier Bit 67" "0,1"
bitfld.long 0x00 2. "  GMB66  ,Group Modifier Bit 66" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB65  ,Group Modifier Bit 65" "0,1"
bitfld.long 0x00 0. "  GMB64  ,Group Modifier Bit 64" "0,1"
else
hgroup.long 0x0D08++0x03
hide.long 0x0 "GICD_IGRPMODR2,Interrupt Group Modifier Register 2"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D0C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x03))
group.long 0x0D0C++0x03
line.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
bitfld.long 0x00 31. " GMB127 ,Group Modifier Bit 127" "0,1"
bitfld.long 0x00 30. "  GMB126 ,Group Modifier Bit 126" "0,1"
bitfld.long 0x00 29. "  GMB125 ,Group Modifier Bit 125" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB124 ,Group Modifier Bit 124" "0,1"
bitfld.long 0x00 27. "  GMB123 ,Group Modifier Bit 123" "0,1"
bitfld.long 0x00 26. "  GMB122 ,Group Modifier Bit 122" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB121 ,Group Modifier Bit 121" "0,1"
bitfld.long 0x00 24. "  GMB120 ,Group Modifier Bit 120" "0,1"
bitfld.long 0x00 23. "  GMB119 ,Group Modifier Bit 119" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB118 ,Group Modifier Bit 118" "0,1"
bitfld.long 0x00 21. "  GMB117 ,Group Modifier Bit 117" "0,1"
bitfld.long 0x00 20. "  GMB116 ,Group Modifier Bit 116" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB115 ,Group Modifier Bit 115" "0,1"
bitfld.long 0x00 18. "  GMB114 ,Group Modifier Bit 114" "0,1"
bitfld.long 0x00 17. "  GMB113 ,Group Modifier Bit 113" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB112 ,Group Modifier Bit 112" "0,1"
bitfld.long 0x00 15. "  GMB111 ,Group Modifier Bit 111" "0,1"
bitfld.long 0x00 14. "  GMB110 ,Group Modifier Bit 110" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB109 ,Group Modifier Bit 109" "0,1"
bitfld.long 0x00 12. "  GMB108 ,Group Modifier Bit 108" "0,1"
bitfld.long 0x00 11. "  GMB107 ,Group Modifier Bit 107" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB106 ,Group Modifier Bit 106" "0,1"
bitfld.long 0x00 9. "  GMB105 ,Group Modifier Bit 105" "0,1"
bitfld.long 0x00 8. "  GMB104 ,Group Modifier Bit 104" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB103 ,Group Modifier Bit 103" "0,1"
bitfld.long 0x00 6. "  GMB102 ,Group Modifier Bit 102" "0,1"
bitfld.long 0x00 5. "  GMB101 ,Group Modifier Bit 101" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB100 ,Group Modifier Bit 100" "0,1"
bitfld.long 0x00 3. "  GMB99  ,Group Modifier Bit 99" "0,1"
bitfld.long 0x00 2. "  GMB98  ,Group Modifier Bit 98" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB97  ,Group Modifier Bit 97" "0,1"
bitfld.long 0x00 0. "  GMB96  ,Group Modifier Bit 96" "0,1"
else
hgroup.long 0x0D0C++0x03
hide.long 0x0 "GICD_IGRPMODR3,Interrupt Group Modifier Register 3"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D10))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x04))
group.long 0x0D10++0x03
line.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
bitfld.long 0x00 31. " GMB159 ,Group Modifier Bit 159" "0,1"
bitfld.long 0x00 30. "  GMB158 ,Group Modifier Bit 158" "0,1"
bitfld.long 0x00 29. "  GMB157 ,Group Modifier Bit 157" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB156 ,Group Modifier Bit 156" "0,1"
bitfld.long 0x00 27. "  GMB155 ,Group Modifier Bit 155" "0,1"
bitfld.long 0x00 26. "  GMB154 ,Group Modifier Bit 154" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB153 ,Group Modifier Bit 153" "0,1"
bitfld.long 0x00 24. "  GMB152 ,Group Modifier Bit 152" "0,1"
bitfld.long 0x00 23. "  GMB151 ,Group Modifier Bit 151" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB150 ,Group Modifier Bit 150" "0,1"
bitfld.long 0x00 21. "  GMB149 ,Group Modifier Bit 149" "0,1"
bitfld.long 0x00 20. "  GMB148 ,Group Modifier Bit 148" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB147 ,Group Modifier Bit 147" "0,1"
bitfld.long 0x00 18. "  GMB146 ,Group Modifier Bit 146" "0,1"
bitfld.long 0x00 17. "  GMB145 ,Group Modifier Bit 145" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB144 ,Group Modifier Bit 144" "0,1"
bitfld.long 0x00 15. "  GMB143 ,Group Modifier Bit 143" "0,1"
bitfld.long 0x00 14. "  GMB142 ,Group Modifier Bit 142" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB141 ,Group Modifier Bit 141" "0,1"
bitfld.long 0x00 12. "  GMB140 ,Group Modifier Bit 140" "0,1"
bitfld.long 0x00 11. "  GMB139 ,Group Modifier Bit 139" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB138 ,Group Modifier Bit 138" "0,1"
bitfld.long 0x00 9. "  GMB137 ,Group Modifier Bit 137" "0,1"
bitfld.long 0x00 8. "  GMB136 ,Group Modifier Bit 136" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB135 ,Group Modifier Bit 135" "0,1"
bitfld.long 0x00 6. "  GMB134 ,Group Modifier Bit 134" "0,1"
bitfld.long 0x00 5. "  GMB133 ,Group Modifier Bit 133" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB132 ,Group Modifier Bit 132" "0,1"
bitfld.long 0x00 3. "  GMB131 ,Group Modifier Bit 131" "0,1"
bitfld.long 0x00 2. "  GMB130 ,Group Modifier Bit 130" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB129 ,Group Modifier Bit 129" "0,1"
bitfld.long 0x00 0. "  GMB128 ,Group Modifier Bit 128" "0,1"
else
hgroup.long 0x0D10++0x03
hide.long 0x0 "GICD_IGRPMODR4,Interrupt Group Modifier Register 4"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D14))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x05))
group.long 0x0D14++0x03
line.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
bitfld.long 0x00 31. " GMB191 ,Group Modifier Bit 191" "0,1"
bitfld.long 0x00 30. "  GMB190 ,Group Modifier Bit 190" "0,1"
bitfld.long 0x00 29. "  GMB189 ,Group Modifier Bit 189" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB188 ,Group Modifier Bit 188" "0,1"
bitfld.long 0x00 27. "  GMB187 ,Group Modifier Bit 187" "0,1"
bitfld.long 0x00 26. "  GMB186 ,Group Modifier Bit 186" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB185 ,Group Modifier Bit 185" "0,1"
bitfld.long 0x00 24. "  GMB184 ,Group Modifier Bit 184" "0,1"
bitfld.long 0x00 23. "  GMB183 ,Group Modifier Bit 183" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB182 ,Group Modifier Bit 182" "0,1"
bitfld.long 0x00 21. "  GMB181 ,Group Modifier Bit 181" "0,1"
bitfld.long 0x00 20. "  GMB180 ,Group Modifier Bit 180" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB179 ,Group Modifier Bit 179" "0,1"
bitfld.long 0x00 18. "  GMB178 ,Group Modifier Bit 178" "0,1"
bitfld.long 0x00 17. "  GMB177 ,Group Modifier Bit 177" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB176 ,Group Modifier Bit 176" "0,1"
bitfld.long 0x00 15. "  GMB175 ,Group Modifier Bit 175" "0,1"
bitfld.long 0x00 14. "  GMB174 ,Group Modifier Bit 174" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB173 ,Group Modifier Bit 173" "0,1"
bitfld.long 0x00 12. "  GMB172 ,Group Modifier Bit 172" "0,1"
bitfld.long 0x00 11. "  GMB171 ,Group Modifier Bit 171" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB170 ,Group Modifier Bit 170" "0,1"
bitfld.long 0x00 9. "  GMB169 ,Group Modifier Bit 169" "0,1"
bitfld.long 0x00 8. "  GMB168 ,Group Modifier Bit 168" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB167 ,Group Modifier Bit 167" "0,1"
bitfld.long 0x00 6. "  GMB166 ,Group Modifier Bit 166" "0,1"
bitfld.long 0x00 5. "  GMB165 ,Group Modifier Bit 165" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB164 ,Group Modifier Bit 164" "0,1"
bitfld.long 0x00 3. "  GMB163 ,Group Modifier Bit 163" "0,1"
bitfld.long 0x00 2. "  GMB162 ,Group Modifier Bit 162" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB161 ,Group Modifier Bit 161" "0,1"
bitfld.long 0x00 0. "  GMB160 ,Group Modifier Bit 160" "0,1"
else
hgroup.long 0x0D14++0x03
hide.long 0x0 "GICD_IGRPMODR5,Interrupt Group Modifier Register 5"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D18))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x06))
group.long 0x0D18++0x03
line.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
bitfld.long 0x00 31. " GMB223 ,Group Modifier Bit 223" "0,1"
bitfld.long 0x00 30. "  GMB222 ,Group Modifier Bit 222" "0,1"
bitfld.long 0x00 29. "  GMB221 ,Group Modifier Bit 221" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB220 ,Group Modifier Bit 220" "0,1"
bitfld.long 0x00 27. "  GMB219 ,Group Modifier Bit 219" "0,1"
bitfld.long 0x00 26. "  GMB218 ,Group Modifier Bit 218" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB217 ,Group Modifier Bit 217" "0,1"
bitfld.long 0x00 24. "  GMB216 ,Group Modifier Bit 216" "0,1"
bitfld.long 0x00 23. "  GMB215 ,Group Modifier Bit 215" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB214 ,Group Modifier Bit 214" "0,1"
bitfld.long 0x00 21. "  GMB213 ,Group Modifier Bit 213" "0,1"
bitfld.long 0x00 20. "  GMB212 ,Group Modifier Bit 212" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB211 ,Group Modifier Bit 211" "0,1"
bitfld.long 0x00 18. "  GMB210 ,Group Modifier Bit 210" "0,1"
bitfld.long 0x00 17. "  GMB209 ,Group Modifier Bit 209" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB208 ,Group Modifier Bit 208" "0,1"
bitfld.long 0x00 15. "  GMB207 ,Group Modifier Bit 207" "0,1"
bitfld.long 0x00 14. "  GMB206 ,Group Modifier Bit 206" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB205 ,Group Modifier Bit 205" "0,1"
bitfld.long 0x00 12. "  GMB204 ,Group Modifier Bit 204" "0,1"
bitfld.long 0x00 11. "  GMB203 ,Group Modifier Bit 203" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB202 ,Group Modifier Bit 202" "0,1"
bitfld.long 0x00 9. "  GMB201 ,Group Modifier Bit 201" "0,1"
bitfld.long 0x00 8. "  GMB200 ,Group Modifier Bit 200" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB199 ,Group Modifier Bit 199" "0,1"
bitfld.long 0x00 6. "  GMB198 ,Group Modifier Bit 198" "0,1"
bitfld.long 0x00 5. "  GMB197 ,Group Modifier Bit 197" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB196 ,Group Modifier Bit 196" "0,1"
bitfld.long 0x00 3. "  GMB195 ,Group Modifier Bit 195" "0,1"
bitfld.long 0x00 2. "  GMB194 ,Group Modifier Bit 194" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB193 ,Group Modifier Bit 193" "0,1"
bitfld.long 0x00 0. "  GMB192 ,Group Modifier Bit 192" "0,1"
else
hgroup.long 0x0D18++0x03
hide.long 0x0 "GICD_IGRPMODR6,Interrupt Group Modifier Register 6"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D1C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x07))
group.long 0x0D1C++0x03
line.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
bitfld.long 0x00 31. " GMB255 ,Group Modifier Bit 255" "0,1"
bitfld.long 0x00 30. "  GMB254 ,Group Modifier Bit 254" "0,1"
bitfld.long 0x00 29. "  GMB253 ,Group Modifier Bit 253" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB252 ,Group Modifier Bit 252" "0,1"
bitfld.long 0x00 27. "  GMB251 ,Group Modifier Bit 251" "0,1"
bitfld.long 0x00 26. "  GMB250 ,Group Modifier Bit 250" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB249 ,Group Modifier Bit 249" "0,1"
bitfld.long 0x00 24. "  GMB248 ,Group Modifier Bit 248" "0,1"
bitfld.long 0x00 23. "  GMB247 ,Group Modifier Bit 247" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB246 ,Group Modifier Bit 246" "0,1"
bitfld.long 0x00 21. "  GMB245 ,Group Modifier Bit 245" "0,1"
bitfld.long 0x00 20. "  GMB244 ,Group Modifier Bit 244" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB243 ,Group Modifier Bit 243" "0,1"
bitfld.long 0x00 18. "  GMB242 ,Group Modifier Bit 242" "0,1"
bitfld.long 0x00 17. "  GMB241 ,Group Modifier Bit 241" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB240 ,Group Modifier Bit 240" "0,1"
bitfld.long 0x00 15. "  GMB239 ,Group Modifier Bit 239" "0,1"
bitfld.long 0x00 14. "  GMB238 ,Group Modifier Bit 238" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB237 ,Group Modifier Bit 237" "0,1"
bitfld.long 0x00 12. "  GMB236 ,Group Modifier Bit 236" "0,1"
bitfld.long 0x00 11. "  GMB235 ,Group Modifier Bit 235" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB234 ,Group Modifier Bit 234" "0,1"
bitfld.long 0x00 9. "  GMB233 ,Group Modifier Bit 233" "0,1"
bitfld.long 0x00 8. "  GMB232 ,Group Modifier Bit 232" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB231 ,Group Modifier Bit 231" "0,1"
bitfld.long 0x00 6. "  GMB230 ,Group Modifier Bit 230" "0,1"
bitfld.long 0x00 5. "  GMB229 ,Group Modifier Bit 229" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB228 ,Group Modifier Bit 228" "0,1"
bitfld.long 0x00 3. "  GMB227 ,Group Modifier Bit 227" "0,1"
bitfld.long 0x00 2. "  GMB226 ,Group Modifier Bit 226" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB225 ,Group Modifier Bit 225" "0,1"
bitfld.long 0x00 0. "  GMB224 ,Group Modifier Bit 224" "0,1"
else
hgroup.long 0x0D1C++0x03
hide.long 0x0 "GICD_IGRPMODR7,Interrupt Group Modifier Register 7"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D20))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x08))
group.long 0x0D20++0x03
line.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
bitfld.long 0x00 31. " GMB287 ,Group Modifier Bit 287" "0,1"
bitfld.long 0x00 30. "  GMB286 ,Group Modifier Bit 286" "0,1"
bitfld.long 0x00 29. "  GMB285 ,Group Modifier Bit 285" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB284 ,Group Modifier Bit 284" "0,1"
bitfld.long 0x00 27. "  GMB283 ,Group Modifier Bit 283" "0,1"
bitfld.long 0x00 26. "  GMB282 ,Group Modifier Bit 282" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB281 ,Group Modifier Bit 281" "0,1"
bitfld.long 0x00 24. "  GMB280 ,Group Modifier Bit 280" "0,1"
bitfld.long 0x00 23. "  GMB279 ,Group Modifier Bit 279" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB278 ,Group Modifier Bit 278" "0,1"
bitfld.long 0x00 21. "  GMB277 ,Group Modifier Bit 277" "0,1"
bitfld.long 0x00 20. "  GMB276 ,Group Modifier Bit 276" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB275 ,Group Modifier Bit 275" "0,1"
bitfld.long 0x00 18. "  GMB274 ,Group Modifier Bit 274" "0,1"
bitfld.long 0x00 17. "  GMB273 ,Group Modifier Bit 273" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB272 ,Group Modifier Bit 272" "0,1"
bitfld.long 0x00 15. "  GMB271 ,Group Modifier Bit 271" "0,1"
bitfld.long 0x00 14. "  GMB270 ,Group Modifier Bit 270" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB269 ,Group Modifier Bit 269" "0,1"
bitfld.long 0x00 12. "  GMB268 ,Group Modifier Bit 268" "0,1"
bitfld.long 0x00 11. "  GMB267 ,Group Modifier Bit 267" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB266 ,Group Modifier Bit 266" "0,1"
bitfld.long 0x00 9. "  GMB265 ,Group Modifier Bit 265" "0,1"
bitfld.long 0x00 8. "  GMB264 ,Group Modifier Bit 264" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB263 ,Group Modifier Bit 263" "0,1"
bitfld.long 0x00 6. "  GMB262 ,Group Modifier Bit 262" "0,1"
bitfld.long 0x00 5. "  GMB261 ,Group Modifier Bit 261" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB260 ,Group Modifier Bit 260" "0,1"
bitfld.long 0x00 3. "  GMB259 ,Group Modifier Bit 259" "0,1"
bitfld.long 0x00 2. "  GMB258 ,Group Modifier Bit 258" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB257 ,Group Modifier Bit 257" "0,1"
bitfld.long 0x00 0. "  GMB256 ,Group Modifier Bit 256" "0,1"
else
hgroup.long 0x0D20++0x03
hide.long 0x0 "GICD_IGRPMODR8,Interrupt Group Modifier Register 8"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D24))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x09))
group.long 0x0D24++0x03
line.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
bitfld.long 0x00 31. " GMB319 ,Group Modifier Bit 319" "0,1"
bitfld.long 0x00 30. "  GMB318 ,Group Modifier Bit 318" "0,1"
bitfld.long 0x00 29. "  GMB317 ,Group Modifier Bit 317" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB316 ,Group Modifier Bit 316" "0,1"
bitfld.long 0x00 27. "  GMB315 ,Group Modifier Bit 315" "0,1"
bitfld.long 0x00 26. "  GMB314 ,Group Modifier Bit 314" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB313 ,Group Modifier Bit 313" "0,1"
bitfld.long 0x00 24. "  GMB312 ,Group Modifier Bit 312" "0,1"
bitfld.long 0x00 23. "  GMB311 ,Group Modifier Bit 311" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB310 ,Group Modifier Bit 310" "0,1"
bitfld.long 0x00 21. "  GMB309 ,Group Modifier Bit 309" "0,1"
bitfld.long 0x00 20. "  GMB308 ,Group Modifier Bit 308" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB307 ,Group Modifier Bit 307" "0,1"
bitfld.long 0x00 18. "  GMB306 ,Group Modifier Bit 306" "0,1"
bitfld.long 0x00 17. "  GMB305 ,Group Modifier Bit 305" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB304 ,Group Modifier Bit 304" "0,1"
bitfld.long 0x00 15. "  GMB303 ,Group Modifier Bit 303" "0,1"
bitfld.long 0x00 14. "  GMB302 ,Group Modifier Bit 302" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB301 ,Group Modifier Bit 301" "0,1"
bitfld.long 0x00 12. "  GMB300 ,Group Modifier Bit 300" "0,1"
bitfld.long 0x00 11. "  GMB299 ,Group Modifier Bit 299" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB298 ,Group Modifier Bit 298" "0,1"
bitfld.long 0x00 9. "  GMB297 ,Group Modifier Bit 297" "0,1"
bitfld.long 0x00 8. "  GMB296 ,Group Modifier Bit 296" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB295 ,Group Modifier Bit 295" "0,1"
bitfld.long 0x00 6. "  GMB294 ,Group Modifier Bit 294" "0,1"
bitfld.long 0x00 5. "  GMB293 ,Group Modifier Bit 293" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB292 ,Group Modifier Bit 292" "0,1"
bitfld.long 0x00 3. "  GMB291 ,Group Modifier Bit 291" "0,1"
bitfld.long 0x00 2. "  GMB290 ,Group Modifier Bit 290" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB289 ,Group Modifier Bit 289" "0,1"
bitfld.long 0x00 0. "  GMB288 ,Group Modifier Bit 288" "0,1"
else
hgroup.long 0x0D24++0x03
hide.long 0x0 "GICD_IGRPMODR9,Interrupt Group Modifier Register 9"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D28))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0A))
group.long 0x0D28++0x03
line.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
bitfld.long 0x00 31. " GMB351 ,Group Modifier Bit 351" "0,1"
bitfld.long 0x00 30. "  GMB350 ,Group Modifier Bit 350" "0,1"
bitfld.long 0x00 29. "  GMB349 ,Group Modifier Bit 349" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB348 ,Group Modifier Bit 348" "0,1"
bitfld.long 0x00 27. "  GMB347 ,Group Modifier Bit 347" "0,1"
bitfld.long 0x00 26. "  GMB346 ,Group Modifier Bit 346" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB345 ,Group Modifier Bit 345" "0,1"
bitfld.long 0x00 24. "  GMB344 ,Group Modifier Bit 344" "0,1"
bitfld.long 0x00 23. "  GMB343 ,Group Modifier Bit 343" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB342 ,Group Modifier Bit 342" "0,1"
bitfld.long 0x00 21. "  GMB341 ,Group Modifier Bit 341" "0,1"
bitfld.long 0x00 20. "  GMB340 ,Group Modifier Bit 340" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB339 ,Group Modifier Bit 339" "0,1"
bitfld.long 0x00 18. "  GMB338 ,Group Modifier Bit 338" "0,1"
bitfld.long 0x00 17. "  GMB337 ,Group Modifier Bit 337" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB336 ,Group Modifier Bit 336" "0,1"
bitfld.long 0x00 15. "  GMB335 ,Group Modifier Bit 335" "0,1"
bitfld.long 0x00 14. "  GMB334 ,Group Modifier Bit 334" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB333 ,Group Modifier Bit 333" "0,1"
bitfld.long 0x00 12. "  GMB332 ,Group Modifier Bit 332" "0,1"
bitfld.long 0x00 11. "  GMB331 ,Group Modifier Bit 331" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB330 ,Group Modifier Bit 330" "0,1"
bitfld.long 0x00 9. "  GMB329 ,Group Modifier Bit 329" "0,1"
bitfld.long 0x00 8. "  GMB328 ,Group Modifier Bit 328" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB327 ,Group Modifier Bit 327" "0,1"
bitfld.long 0x00 6. "  GMB326 ,Group Modifier Bit 326" "0,1"
bitfld.long 0x00 5. "  GMB325 ,Group Modifier Bit 325" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB324 ,Group Modifier Bit 324" "0,1"
bitfld.long 0x00 3. "  GMB323 ,Group Modifier Bit 323" "0,1"
bitfld.long 0x00 2. "  GMB322 ,Group Modifier Bit 322" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB321 ,Group Modifier Bit 321" "0,1"
bitfld.long 0x00 0. "  GMB320 ,Group Modifier Bit 320" "0,1"
else
hgroup.long 0x0D28++0x03
hide.long 0x0 "GICD_IGRPMODR10,Interrupt Group Modifier Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D2C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0B))
group.long 0x0D2C++0x03
line.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
bitfld.long 0x00 31. " GMB383 ,Group Modifier Bit 383" "0,1"
bitfld.long 0x00 30. "  GMB382 ,Group Modifier Bit 382" "0,1"
bitfld.long 0x00 29. "  GMB381 ,Group Modifier Bit 381" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB380 ,Group Modifier Bit 380" "0,1"
bitfld.long 0x00 27. "  GMB379 ,Group Modifier Bit 379" "0,1"
bitfld.long 0x00 26. "  GMB378 ,Group Modifier Bit 378" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB377 ,Group Modifier Bit 377" "0,1"
bitfld.long 0x00 24. "  GMB376 ,Group Modifier Bit 376" "0,1"
bitfld.long 0x00 23. "  GMB375 ,Group Modifier Bit 375" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB374 ,Group Modifier Bit 374" "0,1"
bitfld.long 0x00 21. "  GMB373 ,Group Modifier Bit 373" "0,1"
bitfld.long 0x00 20. "  GMB372 ,Group Modifier Bit 372" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB371 ,Group Modifier Bit 371" "0,1"
bitfld.long 0x00 18. "  GMB370 ,Group Modifier Bit 370" "0,1"
bitfld.long 0x00 17. "  GMB369 ,Group Modifier Bit 369" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB368 ,Group Modifier Bit 368" "0,1"
bitfld.long 0x00 15. "  GMB367 ,Group Modifier Bit 367" "0,1"
bitfld.long 0x00 14. "  GMB366 ,Group Modifier Bit 366" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB365 ,Group Modifier Bit 365" "0,1"
bitfld.long 0x00 12. "  GMB364 ,Group Modifier Bit 364" "0,1"
bitfld.long 0x00 11. "  GMB363 ,Group Modifier Bit 363" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB362 ,Group Modifier Bit 362" "0,1"
bitfld.long 0x00 9. "  GMB361 ,Group Modifier Bit 361" "0,1"
bitfld.long 0x00 8. "  GMB360 ,Group Modifier Bit 360" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB359 ,Group Modifier Bit 359" "0,1"
bitfld.long 0x00 6. "  GMB358 ,Group Modifier Bit 358" "0,1"
bitfld.long 0x00 5. "  GMB357 ,Group Modifier Bit 357" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB356 ,Group Modifier Bit 356" "0,1"
bitfld.long 0x00 3. "  GMB355 ,Group Modifier Bit 355" "0,1"
bitfld.long 0x00 2. "  GMB354 ,Group Modifier Bit 354" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB353 ,Group Modifier Bit 353" "0,1"
bitfld.long 0x00 0. "  GMB352 ,Group Modifier Bit 352" "0,1"
else
hgroup.long 0x0D2C++0x03
hide.long 0x0 "GICD_IGRPMODR11,Interrupt Group Modifier Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D30))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0C))
group.long 0x0D30++0x03
line.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
bitfld.long 0x00 31. " GMB415 ,Group Modifier Bit 415" "0,1"
bitfld.long 0x00 30. "  GMB414 ,Group Modifier Bit 414" "0,1"
bitfld.long 0x00 29. "  GMB413 ,Group Modifier Bit 413" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB412 ,Group Modifier Bit 412" "0,1"
bitfld.long 0x00 27. "  GMB411 ,Group Modifier Bit 411" "0,1"
bitfld.long 0x00 26. "  GMB410 ,Group Modifier Bit 410" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB409 ,Group Modifier Bit 409" "0,1"
bitfld.long 0x00 24. "  GMB408 ,Group Modifier Bit 408" "0,1"
bitfld.long 0x00 23. "  GMB407 ,Group Modifier Bit 407" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB406 ,Group Modifier Bit 406" "0,1"
bitfld.long 0x00 21. "  GMB405 ,Group Modifier Bit 405" "0,1"
bitfld.long 0x00 20. "  GMB404 ,Group Modifier Bit 404" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB403 ,Group Modifier Bit 403" "0,1"
bitfld.long 0x00 18. "  GMB402 ,Group Modifier Bit 402" "0,1"
bitfld.long 0x00 17. "  GMB401 ,Group Modifier Bit 401" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB400 ,Group Modifier Bit 400" "0,1"
bitfld.long 0x00 15. "  GMB399 ,Group Modifier Bit 399" "0,1"
bitfld.long 0x00 14. "  GMB398 ,Group Modifier Bit 398" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB397 ,Group Modifier Bit 397" "0,1"
bitfld.long 0x00 12. "  GMB396 ,Group Modifier Bit 396" "0,1"
bitfld.long 0x00 11. "  GMB395 ,Group Modifier Bit 395" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB394 ,Group Modifier Bit 394" "0,1"
bitfld.long 0x00 9. "  GMB393 ,Group Modifier Bit 393" "0,1"
bitfld.long 0x00 8. "  GMB392 ,Group Modifier Bit 392" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB391 ,Group Modifier Bit 391" "0,1"
bitfld.long 0x00 6. "  GMB390 ,Group Modifier Bit 390" "0,1"
bitfld.long 0x00 5. "  GMB389 ,Group Modifier Bit 389" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB388 ,Group Modifier Bit 388" "0,1"
bitfld.long 0x00 3. "  GMB387 ,Group Modifier Bit 387" "0,1"
bitfld.long 0x00 2. "  GMB386 ,Group Modifier Bit 386" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB385 ,Group Modifier Bit 385" "0,1"
bitfld.long 0x00 0. "  GMB384 ,Group Modifier Bit 384" "0,1"
else
hgroup.long 0x0D30++0x03
hide.long 0x0 "GICD_IGRPMODR12,Interrupt Group Modifier Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D34))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0D))
group.long 0x0D34++0x03
line.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
bitfld.long 0x00 31. " GMB447 ,Group Modifier Bit 447" "0,1"
bitfld.long 0x00 30. "  GMB446 ,Group Modifier Bit 446" "0,1"
bitfld.long 0x00 29. "  GMB445 ,Group Modifier Bit 445" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB444 ,Group Modifier Bit 444" "0,1"
bitfld.long 0x00 27. "  GMB443 ,Group Modifier Bit 443" "0,1"
bitfld.long 0x00 26. "  GMB442 ,Group Modifier Bit 442" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB441 ,Group Modifier Bit 441" "0,1"
bitfld.long 0x00 24. "  GMB440 ,Group Modifier Bit 440" "0,1"
bitfld.long 0x00 23. "  GMB439 ,Group Modifier Bit 439" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB438 ,Group Modifier Bit 438" "0,1"
bitfld.long 0x00 21. "  GMB437 ,Group Modifier Bit 437" "0,1"
bitfld.long 0x00 20. "  GMB436 ,Group Modifier Bit 436" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB435 ,Group Modifier Bit 435" "0,1"
bitfld.long 0x00 18. "  GMB434 ,Group Modifier Bit 434" "0,1"
bitfld.long 0x00 17. "  GMB433 ,Group Modifier Bit 433" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB432 ,Group Modifier Bit 432" "0,1"
bitfld.long 0x00 15. "  GMB431 ,Group Modifier Bit 431" "0,1"
bitfld.long 0x00 14. "  GMB430 ,Group Modifier Bit 430" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB429 ,Group Modifier Bit 429" "0,1"
bitfld.long 0x00 12. "  GMB428 ,Group Modifier Bit 428" "0,1"
bitfld.long 0x00 11. "  GMB427 ,Group Modifier Bit 427" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB426 ,Group Modifier Bit 426" "0,1"
bitfld.long 0x00 9. "  GMB425 ,Group Modifier Bit 425" "0,1"
bitfld.long 0x00 8. "  GMB424 ,Group Modifier Bit 424" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB423 ,Group Modifier Bit 423" "0,1"
bitfld.long 0x00 6. "  GMB422 ,Group Modifier Bit 422" "0,1"
bitfld.long 0x00 5. "  GMB421 ,Group Modifier Bit 421" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB420 ,Group Modifier Bit 420" "0,1"
bitfld.long 0x00 3. "  GMB419 ,Group Modifier Bit 419" "0,1"
bitfld.long 0x00 2. "  GMB418 ,Group Modifier Bit 418" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB417 ,Group Modifier Bit 417" "0,1"
bitfld.long 0x00 0. "  GMB416 ,Group Modifier Bit 416" "0,1"
else
hgroup.long 0x0D34++0x03
hide.long 0x0 "GICD_IGRPMODR13,Interrupt Group Modifier Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D38))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0E))
group.long 0x0D38++0x03
line.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
bitfld.long 0x00 31. " GMB479 ,Group Modifier Bit 479" "0,1"
bitfld.long 0x00 30. "  GMB478 ,Group Modifier Bit 478" "0,1"
bitfld.long 0x00 29. "  GMB477 ,Group Modifier Bit 477" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB476 ,Group Modifier Bit 476" "0,1"
bitfld.long 0x00 27. "  GMB475 ,Group Modifier Bit 475" "0,1"
bitfld.long 0x00 26. "  GMB474 ,Group Modifier Bit 474" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB473 ,Group Modifier Bit 473" "0,1"
bitfld.long 0x00 24. "  GMB472 ,Group Modifier Bit 472" "0,1"
bitfld.long 0x00 23. "  GMB471 ,Group Modifier Bit 471" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB470 ,Group Modifier Bit 470" "0,1"
bitfld.long 0x00 21. "  GMB469 ,Group Modifier Bit 469" "0,1"
bitfld.long 0x00 20. "  GMB468 ,Group Modifier Bit 468" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB467 ,Group Modifier Bit 467" "0,1"
bitfld.long 0x00 18. "  GMB466 ,Group Modifier Bit 466" "0,1"
bitfld.long 0x00 17. "  GMB465 ,Group Modifier Bit 465" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB464 ,Group Modifier Bit 464" "0,1"
bitfld.long 0x00 15. "  GMB463 ,Group Modifier Bit 463" "0,1"
bitfld.long 0x00 14. "  GMB462 ,Group Modifier Bit 462" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB461 ,Group Modifier Bit 461" "0,1"
bitfld.long 0x00 12. "  GMB460 ,Group Modifier Bit 460" "0,1"
bitfld.long 0x00 11. "  GMB459 ,Group Modifier Bit 459" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB458 ,Group Modifier Bit 458" "0,1"
bitfld.long 0x00 9. "  GMB457 ,Group Modifier Bit 457" "0,1"
bitfld.long 0x00 8. "  GMB456 ,Group Modifier Bit 456" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB455 ,Group Modifier Bit 455" "0,1"
bitfld.long 0x00 6. "  GMB454 ,Group Modifier Bit 454" "0,1"
bitfld.long 0x00 5. "  GMB453 ,Group Modifier Bit 453" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB452 ,Group Modifier Bit 452" "0,1"
bitfld.long 0x00 3. "  GMB451 ,Group Modifier Bit 451" "0,1"
bitfld.long 0x00 2. "  GMB450 ,Group Modifier Bit 450" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB449 ,Group Modifier Bit 449" "0,1"
bitfld.long 0x00 0. "  GMB448 ,Group Modifier Bit 448" "0,1"
else
hgroup.long 0x0D38++0x03
hide.long 0x0 "GICD_IGRPMODR14,Interrupt Group Modifier Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D3C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x0F))
group.long 0x0D3C++0x03
line.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
bitfld.long 0x00 31. " GMB511 ,Group Modifier Bit 511" "0,1"
bitfld.long 0x00 30. "  GMB510 ,Group Modifier Bit 510" "0,1"
bitfld.long 0x00 29. "  GMB509 ,Group Modifier Bit 509" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB508 ,Group Modifier Bit 508" "0,1"
bitfld.long 0x00 27. "  GMB507 ,Group Modifier Bit 507" "0,1"
bitfld.long 0x00 26. "  GMB506 ,Group Modifier Bit 506" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB505 ,Group Modifier Bit 505" "0,1"
bitfld.long 0x00 24. "  GMB504 ,Group Modifier Bit 504" "0,1"
bitfld.long 0x00 23. "  GMB503 ,Group Modifier Bit 503" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB502 ,Group Modifier Bit 502" "0,1"
bitfld.long 0x00 21. "  GMB501 ,Group Modifier Bit 501" "0,1"
bitfld.long 0x00 20. "  GMB500 ,Group Modifier Bit 500" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB499 ,Group Modifier Bit 499" "0,1"
bitfld.long 0x00 18. "  GMB498 ,Group Modifier Bit 498" "0,1"
bitfld.long 0x00 17. "  GMB497 ,Group Modifier Bit 497" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB496 ,Group Modifier Bit 496" "0,1"
bitfld.long 0x00 15. "  GMB495 ,Group Modifier Bit 495" "0,1"
bitfld.long 0x00 14. "  GMB494 ,Group Modifier Bit 494" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB493 ,Group Modifier Bit 493" "0,1"
bitfld.long 0x00 12. "  GMB492 ,Group Modifier Bit 492" "0,1"
bitfld.long 0x00 11. "  GMB491 ,Group Modifier Bit 491" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB490 ,Group Modifier Bit 490" "0,1"
bitfld.long 0x00 9. "  GMB489 ,Group Modifier Bit 489" "0,1"
bitfld.long 0x00 8. "  GMB488 ,Group Modifier Bit 488" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB487 ,Group Modifier Bit 487" "0,1"
bitfld.long 0x00 6. "  GMB486 ,Group Modifier Bit 486" "0,1"
bitfld.long 0x00 5. "  GMB485 ,Group Modifier Bit 485" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB484 ,Group Modifier Bit 484" "0,1"
bitfld.long 0x00 3. "  GMB483 ,Group Modifier Bit 483" "0,1"
bitfld.long 0x00 2. "  GMB482 ,Group Modifier Bit 482" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB481 ,Group Modifier Bit 481" "0,1"
bitfld.long 0x00 0. "  GMB480 ,Group Modifier Bit 480" "0,1"
else
hgroup.long 0x0D3C++0x03
hide.long 0x0 "GICD_IGRPMODR15,Interrupt Group Modifier Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D40))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x10))
group.long 0x0D40++0x03
line.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
bitfld.long 0x00 31. " GMB543 ,Group Modifier Bit 543" "0,1"
bitfld.long 0x00 30. "  GMB542 ,Group Modifier Bit 542" "0,1"
bitfld.long 0x00 29. "  GMB541 ,Group Modifier Bit 541" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB540 ,Group Modifier Bit 540" "0,1"
bitfld.long 0x00 27. "  GMB539 ,Group Modifier Bit 539" "0,1"
bitfld.long 0x00 26. "  GMB538 ,Group Modifier Bit 538" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB537 ,Group Modifier Bit 537" "0,1"
bitfld.long 0x00 24. "  GMB536 ,Group Modifier Bit 536" "0,1"
bitfld.long 0x00 23. "  GMB535 ,Group Modifier Bit 535" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB534 ,Group Modifier Bit 534" "0,1"
bitfld.long 0x00 21. "  GMB533 ,Group Modifier Bit 533" "0,1"
bitfld.long 0x00 20. "  GMB532 ,Group Modifier Bit 532" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB531 ,Group Modifier Bit 531" "0,1"
bitfld.long 0x00 18. "  GMB530 ,Group Modifier Bit 530" "0,1"
bitfld.long 0x00 17. "  GMB529 ,Group Modifier Bit 529" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB528 ,Group Modifier Bit 528" "0,1"
bitfld.long 0x00 15. "  GMB527 ,Group Modifier Bit 527" "0,1"
bitfld.long 0x00 14. "  GMB526 ,Group Modifier Bit 526" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB525 ,Group Modifier Bit 525" "0,1"
bitfld.long 0x00 12. "  GMB524 ,Group Modifier Bit 524" "0,1"
bitfld.long 0x00 11. "  GMB523 ,Group Modifier Bit 523" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB522 ,Group Modifier Bit 522" "0,1"
bitfld.long 0x00 9. "  GMB521 ,Group Modifier Bit 521" "0,1"
bitfld.long 0x00 8. "  GMB520 ,Group Modifier Bit 520" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB519 ,Group Modifier Bit 519" "0,1"
bitfld.long 0x00 6. "  GMB518 ,Group Modifier Bit 518" "0,1"
bitfld.long 0x00 5. "  GMB517 ,Group Modifier Bit 517" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB516 ,Group Modifier Bit 516" "0,1"
bitfld.long 0x00 3. "  GMB515 ,Group Modifier Bit 515" "0,1"
bitfld.long 0x00 2. "  GMB514 ,Group Modifier Bit 514" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB513 ,Group Modifier Bit 513" "0,1"
bitfld.long 0x00 0. "  GMB512 ,Group Modifier Bit 512" "0,1"
else
hgroup.long 0x0D40++0x03
hide.long 0x0 "GICD_IGRPMODR16,Interrupt Group Modifier Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D44))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x11))
group.long 0x0D44++0x03
line.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
bitfld.long 0x00 31. " GMB575 ,Group Modifier Bit 575" "0,1"
bitfld.long 0x00 30. "  GMB574 ,Group Modifier Bit 574" "0,1"
bitfld.long 0x00 29. "  GMB573 ,Group Modifier Bit 573" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB572 ,Group Modifier Bit 572" "0,1"
bitfld.long 0x00 27. "  GMB571 ,Group Modifier Bit 571" "0,1"
bitfld.long 0x00 26. "  GMB570 ,Group Modifier Bit 570" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB569 ,Group Modifier Bit 569" "0,1"
bitfld.long 0x00 24. "  GMB568 ,Group Modifier Bit 568" "0,1"
bitfld.long 0x00 23. "  GMB567 ,Group Modifier Bit 567" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB566 ,Group Modifier Bit 566" "0,1"
bitfld.long 0x00 21. "  GMB565 ,Group Modifier Bit 565" "0,1"
bitfld.long 0x00 20. "  GMB564 ,Group Modifier Bit 564" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB563 ,Group Modifier Bit 563" "0,1"
bitfld.long 0x00 18. "  GMB562 ,Group Modifier Bit 562" "0,1"
bitfld.long 0x00 17. "  GMB561 ,Group Modifier Bit 561" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB560 ,Group Modifier Bit 560" "0,1"
bitfld.long 0x00 15. "  GMB559 ,Group Modifier Bit 559" "0,1"
bitfld.long 0x00 14. "  GMB558 ,Group Modifier Bit 558" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB557 ,Group Modifier Bit 557" "0,1"
bitfld.long 0x00 12. "  GMB556 ,Group Modifier Bit 556" "0,1"
bitfld.long 0x00 11. "  GMB555 ,Group Modifier Bit 555" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB554 ,Group Modifier Bit 554" "0,1"
bitfld.long 0x00 9. "  GMB553 ,Group Modifier Bit 553" "0,1"
bitfld.long 0x00 8. "  GMB552 ,Group Modifier Bit 552" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB551 ,Group Modifier Bit 551" "0,1"
bitfld.long 0x00 6. "  GMB550 ,Group Modifier Bit 550" "0,1"
bitfld.long 0x00 5. "  GMB549 ,Group Modifier Bit 549" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB548 ,Group Modifier Bit 548" "0,1"
bitfld.long 0x00 3. "  GMB547 ,Group Modifier Bit 547" "0,1"
bitfld.long 0x00 2. "  GMB546 ,Group Modifier Bit 546" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB545 ,Group Modifier Bit 545" "0,1"
bitfld.long 0x00 0. "  GMB544 ,Group Modifier Bit 544" "0,1"
else
hgroup.long 0x0D44++0x03
hide.long 0x0 "GICD_IGRPMODR17,Interrupt Group Modifier Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D48))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x12))
group.long 0x0D48++0x03
line.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
bitfld.long 0x00 31. " GMB607 ,Group Modifier Bit 607" "0,1"
bitfld.long 0x00 30. "  GMB606 ,Group Modifier Bit 606" "0,1"
bitfld.long 0x00 29. "  GMB605 ,Group Modifier Bit 605" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB604 ,Group Modifier Bit 604" "0,1"
bitfld.long 0x00 27. "  GMB603 ,Group Modifier Bit 603" "0,1"
bitfld.long 0x00 26. "  GMB602 ,Group Modifier Bit 602" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB601 ,Group Modifier Bit 601" "0,1"
bitfld.long 0x00 24. "  GMB600 ,Group Modifier Bit 600" "0,1"
bitfld.long 0x00 23. "  GMB599 ,Group Modifier Bit 599" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB598 ,Group Modifier Bit 598" "0,1"
bitfld.long 0x00 21. "  GMB597 ,Group Modifier Bit 597" "0,1"
bitfld.long 0x00 20. "  GMB596 ,Group Modifier Bit 596" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB595 ,Group Modifier Bit 595" "0,1"
bitfld.long 0x00 18. "  GMB594 ,Group Modifier Bit 594" "0,1"
bitfld.long 0x00 17. "  GMB593 ,Group Modifier Bit 593" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB592 ,Group Modifier Bit 592" "0,1"
bitfld.long 0x00 15. "  GMB591 ,Group Modifier Bit 591" "0,1"
bitfld.long 0x00 14. "  GMB590 ,Group Modifier Bit 590" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB589 ,Group Modifier Bit 589" "0,1"
bitfld.long 0x00 12. "  GMB588 ,Group Modifier Bit 588" "0,1"
bitfld.long 0x00 11. "  GMB587 ,Group Modifier Bit 587" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB586 ,Group Modifier Bit 586" "0,1"
bitfld.long 0x00 9. "  GMB585 ,Group Modifier Bit 585" "0,1"
bitfld.long 0x00 8. "  GMB584 ,Group Modifier Bit 584" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB583 ,Group Modifier Bit 583" "0,1"
bitfld.long 0x00 6. "  GMB582 ,Group Modifier Bit 582" "0,1"
bitfld.long 0x00 5. "  GMB581 ,Group Modifier Bit 581" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB580 ,Group Modifier Bit 580" "0,1"
bitfld.long 0x00 3. "  GMB579 ,Group Modifier Bit 579" "0,1"
bitfld.long 0x00 2. "  GMB578 ,Group Modifier Bit 578" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB577 ,Group Modifier Bit 577" "0,1"
bitfld.long 0x00 0. "  GMB576 ,Group Modifier Bit 576" "0,1"
else
hgroup.long 0x0D48++0x03
hide.long 0x0 "GICD_IGRPMODR18,Interrupt Group Modifier Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D4C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x13))
group.long 0x0D4C++0x03
line.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
bitfld.long 0x00 31. " GMB639 ,Group Modifier Bit 639" "0,1"
bitfld.long 0x00 30. "  GMB638 ,Group Modifier Bit 638" "0,1"
bitfld.long 0x00 29. "  GMB637 ,Group Modifier Bit 637" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB636 ,Group Modifier Bit 636" "0,1"
bitfld.long 0x00 27. "  GMB635 ,Group Modifier Bit 635" "0,1"
bitfld.long 0x00 26. "  GMB634 ,Group Modifier Bit 634" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB633 ,Group Modifier Bit 633" "0,1"
bitfld.long 0x00 24. "  GMB632 ,Group Modifier Bit 632" "0,1"
bitfld.long 0x00 23. "  GMB631 ,Group Modifier Bit 631" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB630 ,Group Modifier Bit 630" "0,1"
bitfld.long 0x00 21. "  GMB629 ,Group Modifier Bit 629" "0,1"
bitfld.long 0x00 20. "  GMB628 ,Group Modifier Bit 628" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB627 ,Group Modifier Bit 627" "0,1"
bitfld.long 0x00 18. "  GMB626 ,Group Modifier Bit 626" "0,1"
bitfld.long 0x00 17. "  GMB625 ,Group Modifier Bit 625" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB624 ,Group Modifier Bit 624" "0,1"
bitfld.long 0x00 15. "  GMB623 ,Group Modifier Bit 623" "0,1"
bitfld.long 0x00 14. "  GMB622 ,Group Modifier Bit 622" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB621 ,Group Modifier Bit 621" "0,1"
bitfld.long 0x00 12. "  GMB620 ,Group Modifier Bit 620" "0,1"
bitfld.long 0x00 11. "  GMB619 ,Group Modifier Bit 619" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB618 ,Group Modifier Bit 618" "0,1"
bitfld.long 0x00 9. "  GMB617 ,Group Modifier Bit 617" "0,1"
bitfld.long 0x00 8. "  GMB616 ,Group Modifier Bit 616" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB615 ,Group Modifier Bit 615" "0,1"
bitfld.long 0x00 6. "  GMB614 ,Group Modifier Bit 614" "0,1"
bitfld.long 0x00 5. "  GMB613 ,Group Modifier Bit 613" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB612 ,Group Modifier Bit 612" "0,1"
bitfld.long 0x00 3. "  GMB611 ,Group Modifier Bit 611" "0,1"
bitfld.long 0x00 2. "  GMB610 ,Group Modifier Bit 610" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB609 ,Group Modifier Bit 609" "0,1"
bitfld.long 0x00 0. "  GMB608 ,Group Modifier Bit 608" "0,1"
else
hgroup.long 0x0D4C++0x03
hide.long 0x0 "GICD_IGRPMODR19,Interrupt Group Modifier Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D50))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x14))
group.long 0x0D50++0x03
line.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
bitfld.long 0x00 31. " GMB671 ,Group Modifier Bit 671" "0,1"
bitfld.long 0x00 30. "  GMB670 ,Group Modifier Bit 670" "0,1"
bitfld.long 0x00 29. "  GMB669 ,Group Modifier Bit 669" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB668 ,Group Modifier Bit 668" "0,1"
bitfld.long 0x00 27. "  GMB667 ,Group Modifier Bit 667" "0,1"
bitfld.long 0x00 26. "  GMB666 ,Group Modifier Bit 666" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB665 ,Group Modifier Bit 665" "0,1"
bitfld.long 0x00 24. "  GMB664 ,Group Modifier Bit 664" "0,1"
bitfld.long 0x00 23. "  GMB663 ,Group Modifier Bit 663" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB662 ,Group Modifier Bit 662" "0,1"
bitfld.long 0x00 21. "  GMB661 ,Group Modifier Bit 661" "0,1"
bitfld.long 0x00 20. "  GMB660 ,Group Modifier Bit 660" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB659 ,Group Modifier Bit 659" "0,1"
bitfld.long 0x00 18. "  GMB658 ,Group Modifier Bit 658" "0,1"
bitfld.long 0x00 17. "  GMB657 ,Group Modifier Bit 657" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB656 ,Group Modifier Bit 656" "0,1"
bitfld.long 0x00 15. "  GMB655 ,Group Modifier Bit 655" "0,1"
bitfld.long 0x00 14. "  GMB654 ,Group Modifier Bit 654" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB653 ,Group Modifier Bit 653" "0,1"
bitfld.long 0x00 12. "  GMB652 ,Group Modifier Bit 652" "0,1"
bitfld.long 0x00 11. "  GMB651 ,Group Modifier Bit 651" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB650 ,Group Modifier Bit 650" "0,1"
bitfld.long 0x00 9. "  GMB649 ,Group Modifier Bit 649" "0,1"
bitfld.long 0x00 8. "  GMB648 ,Group Modifier Bit 648" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB647 ,Group Modifier Bit 647" "0,1"
bitfld.long 0x00 6. "  GMB646 ,Group Modifier Bit 646" "0,1"
bitfld.long 0x00 5. "  GMB645 ,Group Modifier Bit 645" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB644 ,Group Modifier Bit 644" "0,1"
bitfld.long 0x00 3. "  GMB643 ,Group Modifier Bit 643" "0,1"
bitfld.long 0x00 2. "  GMB642 ,Group Modifier Bit 642" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB641 ,Group Modifier Bit 641" "0,1"
bitfld.long 0x00 0. "  GMB640 ,Group Modifier Bit 640" "0,1"
else
hgroup.long 0x0D50++0x03
hide.long 0x0 "GICD_IGRPMODR20,Interrupt Group Modifier Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D54))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x15))
group.long 0x0D54++0x03
line.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
bitfld.long 0x00 31. " GMB703 ,Group Modifier Bit 703" "0,1"
bitfld.long 0x00 30. "  GMB702 ,Group Modifier Bit 702" "0,1"
bitfld.long 0x00 29. "  GMB701 ,Group Modifier Bit 701" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB700 ,Group Modifier Bit 700" "0,1"
bitfld.long 0x00 27. "  GMB699 ,Group Modifier Bit 699" "0,1"
bitfld.long 0x00 26. "  GMB698 ,Group Modifier Bit 698" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB697 ,Group Modifier Bit 697" "0,1"
bitfld.long 0x00 24. "  GMB696 ,Group Modifier Bit 696" "0,1"
bitfld.long 0x00 23. "  GMB695 ,Group Modifier Bit 695" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB694 ,Group Modifier Bit 694" "0,1"
bitfld.long 0x00 21. "  GMB693 ,Group Modifier Bit 693" "0,1"
bitfld.long 0x00 20. "  GMB692 ,Group Modifier Bit 692" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB691 ,Group Modifier Bit 691" "0,1"
bitfld.long 0x00 18. "  GMB690 ,Group Modifier Bit 690" "0,1"
bitfld.long 0x00 17. "  GMB689 ,Group Modifier Bit 689" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB688 ,Group Modifier Bit 688" "0,1"
bitfld.long 0x00 15. "  GMB687 ,Group Modifier Bit 687" "0,1"
bitfld.long 0x00 14. "  GMB686 ,Group Modifier Bit 686" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB685 ,Group Modifier Bit 685" "0,1"
bitfld.long 0x00 12. "  GMB684 ,Group Modifier Bit 684" "0,1"
bitfld.long 0x00 11. "  GMB683 ,Group Modifier Bit 683" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB682 ,Group Modifier Bit 682" "0,1"
bitfld.long 0x00 9. "  GMB681 ,Group Modifier Bit 681" "0,1"
bitfld.long 0x00 8. "  GMB680 ,Group Modifier Bit 680" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB679 ,Group Modifier Bit 679" "0,1"
bitfld.long 0x00 6. "  GMB678 ,Group Modifier Bit 678" "0,1"
bitfld.long 0x00 5. "  GMB677 ,Group Modifier Bit 677" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB676 ,Group Modifier Bit 676" "0,1"
bitfld.long 0x00 3. "  GMB675 ,Group Modifier Bit 675" "0,1"
bitfld.long 0x00 2. "  GMB674 ,Group Modifier Bit 674" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB673 ,Group Modifier Bit 673" "0,1"
bitfld.long 0x00 0. "  GMB672 ,Group Modifier Bit 672" "0,1"
else
hgroup.long 0x0D54++0x03
hide.long 0x0 "GICD_IGRPMODR21,Interrupt Group Modifier Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D58))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x16))
group.long 0x0D58++0x03
line.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
bitfld.long 0x00 31. " GMB735 ,Group Modifier Bit 735" "0,1"
bitfld.long 0x00 30. "  GMB734 ,Group Modifier Bit 734" "0,1"
bitfld.long 0x00 29. "  GMB733 ,Group Modifier Bit 733" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB732 ,Group Modifier Bit 732" "0,1"
bitfld.long 0x00 27. "  GMB731 ,Group Modifier Bit 731" "0,1"
bitfld.long 0x00 26. "  GMB730 ,Group Modifier Bit 730" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB729 ,Group Modifier Bit 729" "0,1"
bitfld.long 0x00 24. "  GMB728 ,Group Modifier Bit 728" "0,1"
bitfld.long 0x00 23. "  GMB727 ,Group Modifier Bit 727" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB726 ,Group Modifier Bit 726" "0,1"
bitfld.long 0x00 21. "  GMB725 ,Group Modifier Bit 725" "0,1"
bitfld.long 0x00 20. "  GMB724 ,Group Modifier Bit 724" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB723 ,Group Modifier Bit 723" "0,1"
bitfld.long 0x00 18. "  GMB722 ,Group Modifier Bit 722" "0,1"
bitfld.long 0x00 17. "  GMB721 ,Group Modifier Bit 721" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB720 ,Group Modifier Bit 720" "0,1"
bitfld.long 0x00 15. "  GMB719 ,Group Modifier Bit 719" "0,1"
bitfld.long 0x00 14. "  GMB718 ,Group Modifier Bit 718" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB717 ,Group Modifier Bit 717" "0,1"
bitfld.long 0x00 12. "  GMB716 ,Group Modifier Bit 716" "0,1"
bitfld.long 0x00 11. "  GMB715 ,Group Modifier Bit 715" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB714 ,Group Modifier Bit 714" "0,1"
bitfld.long 0x00 9. "  GMB713 ,Group Modifier Bit 713" "0,1"
bitfld.long 0x00 8. "  GMB712 ,Group Modifier Bit 712" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB711 ,Group Modifier Bit 711" "0,1"
bitfld.long 0x00 6. "  GMB710 ,Group Modifier Bit 710" "0,1"
bitfld.long 0x00 5. "  GMB709 ,Group Modifier Bit 709" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB708 ,Group Modifier Bit 708" "0,1"
bitfld.long 0x00 3. "  GMB707 ,Group Modifier Bit 707" "0,1"
bitfld.long 0x00 2. "  GMB706 ,Group Modifier Bit 706" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB705 ,Group Modifier Bit 705" "0,1"
bitfld.long 0x00 0. "  GMB704 ,Group Modifier Bit 704" "0,1"
else
hgroup.long 0x0D58++0x03
hide.long 0x0 "GICD_IGRPMODR22,Interrupt Group Modifier Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D5C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x17))
group.long 0x0D5C++0x03
line.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
bitfld.long 0x00 31. " GMB767 ,Group Modifier Bit 767" "0,1"
bitfld.long 0x00 30. "  GMB766 ,Group Modifier Bit 766" "0,1"
bitfld.long 0x00 29. "  GMB765 ,Group Modifier Bit 765" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB764 ,Group Modifier Bit 764" "0,1"
bitfld.long 0x00 27. "  GMB763 ,Group Modifier Bit 763" "0,1"
bitfld.long 0x00 26. "  GMB762 ,Group Modifier Bit 762" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB761 ,Group Modifier Bit 761" "0,1"
bitfld.long 0x00 24. "  GMB760 ,Group Modifier Bit 760" "0,1"
bitfld.long 0x00 23. "  GMB759 ,Group Modifier Bit 759" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB758 ,Group Modifier Bit 758" "0,1"
bitfld.long 0x00 21. "  GMB757 ,Group Modifier Bit 757" "0,1"
bitfld.long 0x00 20. "  GMB756 ,Group Modifier Bit 756" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB755 ,Group Modifier Bit 755" "0,1"
bitfld.long 0x00 18. "  GMB754 ,Group Modifier Bit 754" "0,1"
bitfld.long 0x00 17. "  GMB753 ,Group Modifier Bit 753" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB752 ,Group Modifier Bit 752" "0,1"
bitfld.long 0x00 15. "  GMB751 ,Group Modifier Bit 751" "0,1"
bitfld.long 0x00 14. "  GMB750 ,Group Modifier Bit 750" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB749 ,Group Modifier Bit 749" "0,1"
bitfld.long 0x00 12. "  GMB748 ,Group Modifier Bit 748" "0,1"
bitfld.long 0x00 11. "  GMB747 ,Group Modifier Bit 747" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB746 ,Group Modifier Bit 746" "0,1"
bitfld.long 0x00 9. "  GMB745 ,Group Modifier Bit 745" "0,1"
bitfld.long 0x00 8. "  GMB744 ,Group Modifier Bit 744" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB743 ,Group Modifier Bit 743" "0,1"
bitfld.long 0x00 6. "  GMB742 ,Group Modifier Bit 742" "0,1"
bitfld.long 0x00 5. "  GMB741 ,Group Modifier Bit 741" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB740 ,Group Modifier Bit 740" "0,1"
bitfld.long 0x00 3. "  GMB739 ,Group Modifier Bit 739" "0,1"
bitfld.long 0x00 2. "  GMB738 ,Group Modifier Bit 738" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB737 ,Group Modifier Bit 737" "0,1"
bitfld.long 0x00 0. "  GMB736 ,Group Modifier Bit 736" "0,1"
else
hgroup.long 0x0D5C++0x03
hide.long 0x0 "GICD_IGRPMODR23,Interrupt Group Modifier Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D60))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x18))
group.long 0x0D60++0x03
line.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
bitfld.long 0x00 31. " GMB799 ,Group Modifier Bit 799" "0,1"
bitfld.long 0x00 30. "  GMB798 ,Group Modifier Bit 798" "0,1"
bitfld.long 0x00 29. "  GMB797 ,Group Modifier Bit 797" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB796 ,Group Modifier Bit 796" "0,1"
bitfld.long 0x00 27. "  GMB795 ,Group Modifier Bit 795" "0,1"
bitfld.long 0x00 26. "  GMB794 ,Group Modifier Bit 794" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB793 ,Group Modifier Bit 793" "0,1"
bitfld.long 0x00 24. "  GMB792 ,Group Modifier Bit 792" "0,1"
bitfld.long 0x00 23. "  GMB791 ,Group Modifier Bit 791" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB790 ,Group Modifier Bit 790" "0,1"
bitfld.long 0x00 21. "  GMB789 ,Group Modifier Bit 789" "0,1"
bitfld.long 0x00 20. "  GMB788 ,Group Modifier Bit 788" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB787 ,Group Modifier Bit 787" "0,1"
bitfld.long 0x00 18. "  GMB786 ,Group Modifier Bit 786" "0,1"
bitfld.long 0x00 17. "  GMB785 ,Group Modifier Bit 785" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB784 ,Group Modifier Bit 784" "0,1"
bitfld.long 0x00 15. "  GMB783 ,Group Modifier Bit 783" "0,1"
bitfld.long 0x00 14. "  GMB782 ,Group Modifier Bit 782" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB781 ,Group Modifier Bit 781" "0,1"
bitfld.long 0x00 12. "  GMB780 ,Group Modifier Bit 780" "0,1"
bitfld.long 0x00 11. "  GMB779 ,Group Modifier Bit 779" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB778 ,Group Modifier Bit 778" "0,1"
bitfld.long 0x00 9. "  GMB777 ,Group Modifier Bit 777" "0,1"
bitfld.long 0x00 8. "  GMB776 ,Group Modifier Bit 776" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB775 ,Group Modifier Bit 775" "0,1"
bitfld.long 0x00 6. "  GMB774 ,Group Modifier Bit 774" "0,1"
bitfld.long 0x00 5. "  GMB773 ,Group Modifier Bit 773" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB772 ,Group Modifier Bit 772" "0,1"
bitfld.long 0x00 3. "  GMB771 ,Group Modifier Bit 771" "0,1"
bitfld.long 0x00 2. "  GMB770 ,Group Modifier Bit 770" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB769 ,Group Modifier Bit 769" "0,1"
bitfld.long 0x00 0. "  GMB768 ,Group Modifier Bit 768" "0,1"
else
hgroup.long 0x0D60++0x03
hide.long 0x0 "GICD_IGRPMODR24,Interrupt Group Modifier Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D64))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x19))
group.long 0x0D64++0x03
line.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
bitfld.long 0x00 31. " GMB831 ,Group Modifier Bit 831" "0,1"
bitfld.long 0x00 30. "  GMB830 ,Group Modifier Bit 830" "0,1"
bitfld.long 0x00 29. "  GMB829 ,Group Modifier Bit 829" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB828 ,Group Modifier Bit 828" "0,1"
bitfld.long 0x00 27. "  GMB827 ,Group Modifier Bit 827" "0,1"
bitfld.long 0x00 26. "  GMB826 ,Group Modifier Bit 826" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB825 ,Group Modifier Bit 825" "0,1"
bitfld.long 0x00 24. "  GMB824 ,Group Modifier Bit 824" "0,1"
bitfld.long 0x00 23. "  GMB823 ,Group Modifier Bit 823" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB822 ,Group Modifier Bit 822" "0,1"
bitfld.long 0x00 21. "  GMB821 ,Group Modifier Bit 821" "0,1"
bitfld.long 0x00 20. "  GMB820 ,Group Modifier Bit 820" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB819 ,Group Modifier Bit 819" "0,1"
bitfld.long 0x00 18. "  GMB818 ,Group Modifier Bit 818" "0,1"
bitfld.long 0x00 17. "  GMB817 ,Group Modifier Bit 817" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB816 ,Group Modifier Bit 816" "0,1"
bitfld.long 0x00 15. "  GMB815 ,Group Modifier Bit 815" "0,1"
bitfld.long 0x00 14. "  GMB814 ,Group Modifier Bit 814" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB813 ,Group Modifier Bit 813" "0,1"
bitfld.long 0x00 12. "  GMB812 ,Group Modifier Bit 812" "0,1"
bitfld.long 0x00 11. "  GMB811 ,Group Modifier Bit 811" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB810 ,Group Modifier Bit 810" "0,1"
bitfld.long 0x00 9. "  GMB809 ,Group Modifier Bit 809" "0,1"
bitfld.long 0x00 8. "  GMB808 ,Group Modifier Bit 808" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB807 ,Group Modifier Bit 807" "0,1"
bitfld.long 0x00 6. "  GMB806 ,Group Modifier Bit 806" "0,1"
bitfld.long 0x00 5. "  GMB805 ,Group Modifier Bit 805" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB804 ,Group Modifier Bit 804" "0,1"
bitfld.long 0x00 3. "  GMB803 ,Group Modifier Bit 803" "0,1"
bitfld.long 0x00 2. "  GMB802 ,Group Modifier Bit 802" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB801 ,Group Modifier Bit 801" "0,1"
bitfld.long 0x00 0. "  GMB800 ,Group Modifier Bit 800" "0,1"
else
hgroup.long 0x0D64++0x03
hide.long 0x0 "GICD_IGRPMODR25,Interrupt Group Modifier Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D68))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x01A))
group.long 0x0D68++0x03
line.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
bitfld.long 0x00 31. " GMB863 ,Group Modifier Bit 863" "0,1"
bitfld.long 0x00 30. "  GMB862 ,Group Modifier Bit 862" "0,1"
bitfld.long 0x00 29. "  GMB861 ,Group Modifier Bit 861" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB860 ,Group Modifier Bit 860" "0,1"
bitfld.long 0x00 27. "  GMB859 ,Group Modifier Bit 859" "0,1"
bitfld.long 0x00 26. "  GMB858 ,Group Modifier Bit 858" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB857 ,Group Modifier Bit 857" "0,1"
bitfld.long 0x00 24. "  GMB856 ,Group Modifier Bit 856" "0,1"
bitfld.long 0x00 23. "  GMB855 ,Group Modifier Bit 855" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB854 ,Group Modifier Bit 854" "0,1"
bitfld.long 0x00 21. "  GMB853 ,Group Modifier Bit 853" "0,1"
bitfld.long 0x00 20. "  GMB852 ,Group Modifier Bit 852" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB851 ,Group Modifier Bit 851" "0,1"
bitfld.long 0x00 18. "  GMB850 ,Group Modifier Bit 850" "0,1"
bitfld.long 0x00 17. "  GMB849 ,Group Modifier Bit 849" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB848 ,Group Modifier Bit 848" "0,1"
bitfld.long 0x00 15. "  GMB847 ,Group Modifier Bit 847" "0,1"
bitfld.long 0x00 14. "  GMB846 ,Group Modifier Bit 846" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB845 ,Group Modifier Bit 845" "0,1"
bitfld.long 0x00 12. "  GMB844 ,Group Modifier Bit 844" "0,1"
bitfld.long 0x00 11. "  GMB843 ,Group Modifier Bit 843" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB842 ,Group Modifier Bit 842" "0,1"
bitfld.long 0x00 9. "  GMB841 ,Group Modifier Bit 841" "0,1"
bitfld.long 0x00 8. "  GMB840 ,Group Modifier Bit 840" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB839 ,Group Modifier Bit 839" "0,1"
bitfld.long 0x00 6. "  GMB838 ,Group Modifier Bit 838" "0,1"
bitfld.long 0x00 5. "  GMB837 ,Group Modifier Bit 837" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB836 ,Group Modifier Bit 836" "0,1"
bitfld.long 0x00 3. "  GMB835 ,Group Modifier Bit 835" "0,1"
bitfld.long 0x00 2. "  GMB834 ,Group Modifier Bit 834" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB833 ,Group Modifier Bit 833" "0,1"
bitfld.long 0x00 0. "  GMB832 ,Group Modifier Bit 832" "0,1"
else
hgroup.long 0x0D68++0x03
hide.long 0x0 "GICD_IGRPMODR26,Interrupt Group Modifier Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D6C))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1B))
group.long 0x0D6C++0x03
line.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
bitfld.long 0x00 31. " GMB895 ,Group Modifier Bit 895" "0,1"
bitfld.long 0x00 30. "  GMB894 ,Group Modifier Bit 894" "0,1"
bitfld.long 0x00 29. "  GMB893 ,Group Modifier Bit 893" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB892 ,Group Modifier Bit 892" "0,1"
bitfld.long 0x00 27. "  GMB891 ,Group Modifier Bit 891" "0,1"
bitfld.long 0x00 26. "  GMB890 ,Group Modifier Bit 890" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB889 ,Group Modifier Bit 889" "0,1"
bitfld.long 0x00 24. "  GMB888 ,Group Modifier Bit 888" "0,1"
bitfld.long 0x00 23. "  GMB887 ,Group Modifier Bit 887" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB886 ,Group Modifier Bit 886" "0,1"
bitfld.long 0x00 21. "  GMB885 ,Group Modifier Bit 885" "0,1"
bitfld.long 0x00 20. "  GMB884 ,Group Modifier Bit 884" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB883 ,Group Modifier Bit 883" "0,1"
bitfld.long 0x00 18. "  GMB882 ,Group Modifier Bit 882" "0,1"
bitfld.long 0x00 17. "  GMB881 ,Group Modifier Bit 881" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB880 ,Group Modifier Bit 880" "0,1"
bitfld.long 0x00 15. "  GMB879 ,Group Modifier Bit 879" "0,1"
bitfld.long 0x00 14. "  GMB878 ,Group Modifier Bit 878" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB877 ,Group Modifier Bit 877" "0,1"
bitfld.long 0x00 12. "  GMB876 ,Group Modifier Bit 876" "0,1"
bitfld.long 0x00 11. "  GMB875 ,Group Modifier Bit 875" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB874 ,Group Modifier Bit 874" "0,1"
bitfld.long 0x00 9. "  GMB873 ,Group Modifier Bit 873" "0,1"
bitfld.long 0x00 8. "  GMB872 ,Group Modifier Bit 872" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB871 ,Group Modifier Bit 871" "0,1"
bitfld.long 0x00 6. "  GMB870 ,Group Modifier Bit 870" "0,1"
bitfld.long 0x00 5. "  GMB869 ,Group Modifier Bit 869" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB868 ,Group Modifier Bit 868" "0,1"
bitfld.long 0x00 3. "  GMB867 ,Group Modifier Bit 867" "0,1"
bitfld.long 0x00 2. "  GMB866 ,Group Modifier Bit 866" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB865 ,Group Modifier Bit 865" "0,1"
bitfld.long 0x00 0. "  GMB864 ,Group Modifier Bit 864" "0,1"
else
hgroup.long 0x0D6C++0x03
hide.long 0x0 "GICD_IGRPMODR27,Interrupt Group Modifier Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D70))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1C))
group.long 0x0D70++0x03
line.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
bitfld.long 0x00 31. " GMB927 ,Group Modifier Bit 927" "0,1"
bitfld.long 0x00 30. "  GMB926 ,Group Modifier Bit 926" "0,1"
bitfld.long 0x00 29. "  GMB925 ,Group Modifier Bit 925" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB924 ,Group Modifier Bit 924" "0,1"
bitfld.long 0x00 27. "  GMB923 ,Group Modifier Bit 923" "0,1"
bitfld.long 0x00 26. "  GMB922 ,Group Modifier Bit 922" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB921 ,Group Modifier Bit 921" "0,1"
bitfld.long 0x00 24. "  GMB920 ,Group Modifier Bit 920" "0,1"
bitfld.long 0x00 23. "  GMB919 ,Group Modifier Bit 919" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB918 ,Group Modifier Bit 918" "0,1"
bitfld.long 0x00 21. "  GMB917 ,Group Modifier Bit 917" "0,1"
bitfld.long 0x00 20. "  GMB916 ,Group Modifier Bit 916" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB915 ,Group Modifier Bit 915" "0,1"
bitfld.long 0x00 18. "  GMB914 ,Group Modifier Bit 914" "0,1"
bitfld.long 0x00 17. "  GMB913 ,Group Modifier Bit 913" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB912 ,Group Modifier Bit 912" "0,1"
bitfld.long 0x00 15. "  GMB911 ,Group Modifier Bit 911" "0,1"
bitfld.long 0x00 14. "  GMB910 ,Group Modifier Bit 910" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB909 ,Group Modifier Bit 909" "0,1"
bitfld.long 0x00 12. "  GMB908 ,Group Modifier Bit 908" "0,1"
bitfld.long 0x00 11. "  GMB907 ,Group Modifier Bit 907" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB906 ,Group Modifier Bit 906" "0,1"
bitfld.long 0x00 9. "  GMB905 ,Group Modifier Bit 905" "0,1"
bitfld.long 0x00 8. "  GMB904 ,Group Modifier Bit 904" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB903 ,Group Modifier Bit 903" "0,1"
bitfld.long 0x00 6. "  GMB902 ,Group Modifier Bit 902" "0,1"
bitfld.long 0x00 5. "  GMB901 ,Group Modifier Bit 901" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB900 ,Group Modifier Bit 900" "0,1"
bitfld.long 0x00 3. "  GMB899 ,Group Modifier Bit 899" "0,1"
bitfld.long 0x00 2. "  GMB898 ,Group Modifier Bit 898" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB897 ,Group Modifier Bit 897" "0,1"
bitfld.long 0x00 0. "  GMB896 ,Group Modifier Bit 896" "0,1"
else
hgroup.long 0x0D70++0x03
hide.long 0x0 "GICD_IGRPMODR28,Interrupt Group Modifier Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D74))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1D))
group.long 0x0D74++0x03
line.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
bitfld.long 0x00 31. " GMB959 ,Group Modifier Bit 959" "0,1"
bitfld.long 0x00 30. "  GMB958 ,Group Modifier Bit 958" "0,1"
bitfld.long 0x00 29. "  GMB957 ,Group Modifier Bit 957" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB956 ,Group Modifier Bit 956" "0,1"
bitfld.long 0x00 27. "  GMB955 ,Group Modifier Bit 955" "0,1"
bitfld.long 0x00 26. "  GMB954 ,Group Modifier Bit 954" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB953 ,Group Modifier Bit 953" "0,1"
bitfld.long 0x00 24. "  GMB952 ,Group Modifier Bit 952" "0,1"
bitfld.long 0x00 23. "  GMB951 ,Group Modifier Bit 951" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB950 ,Group Modifier Bit 950" "0,1"
bitfld.long 0x00 21. "  GMB949 ,Group Modifier Bit 949" "0,1"
bitfld.long 0x00 20. "  GMB948 ,Group Modifier Bit 948" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB947 ,Group Modifier Bit 947" "0,1"
bitfld.long 0x00 18. "  GMB946 ,Group Modifier Bit 946" "0,1"
bitfld.long 0x00 17. "  GMB945 ,Group Modifier Bit 945" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB944 ,Group Modifier Bit 944" "0,1"
bitfld.long 0x00 15. "  GMB943 ,Group Modifier Bit 943" "0,1"
bitfld.long 0x00 14. "  GMB942 ,Group Modifier Bit 942" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB941 ,Group Modifier Bit 941" "0,1"
bitfld.long 0x00 12. "  GMB940 ,Group Modifier Bit 940" "0,1"
bitfld.long 0x00 11. "  GMB939 ,Group Modifier Bit 939" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB938 ,Group Modifier Bit 938" "0,1"
bitfld.long 0x00 9. "  GMB937 ,Group Modifier Bit 937" "0,1"
bitfld.long 0x00 8. "  GMB936 ,Group Modifier Bit 936" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB935 ,Group Modifier Bit 935" "0,1"
bitfld.long 0x00 6. "  GMB934 ,Group Modifier Bit 934" "0,1"
bitfld.long 0x00 5. "  GMB933 ,Group Modifier Bit 933" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB932 ,Group Modifier Bit 932" "0,1"
bitfld.long 0x00 3. "  GMB931 ,Group Modifier Bit 931" "0,1"
bitfld.long 0x00 2. "  GMB930 ,Group Modifier Bit 930" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB929 ,Group Modifier Bit 929" "0,1"
bitfld.long 0x00 0. "  GMB928 ,Group Modifier Bit 928" "0,1"
else
hgroup.long 0x0D74++0x03
hide.long 0x0 "GICD_IGRPMODR29,Interrupt Group Modifier Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0x0D78))&&(((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=0x1E))
group.long 0x0D78++0x03
line.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
bitfld.long 0x00 31. " GMB991 ,Group Modifier Bit 991" "0,1"
bitfld.long 0x00 30. "  GMB990 ,Group Modifier Bit 990" "0,1"
bitfld.long 0x00 29. "  GMB989 ,Group Modifier Bit 989" "0,1"
textline "                          "
bitfld.long 0x00 28. " GMB988 ,Group Modifier Bit 988" "0,1"
bitfld.long 0x00 27. "  GMB987 ,Group Modifier Bit 987" "0,1"
bitfld.long 0x00 26. "  GMB986 ,Group Modifier Bit 986" "0,1"
textline "                          "
bitfld.long 0x00 25. " GMB985 ,Group Modifier Bit 985" "0,1"
bitfld.long 0x00 24. "  GMB984 ,Group Modifier Bit 984" "0,1"
bitfld.long 0x00 23. "  GMB983 ,Group Modifier Bit 983" "0,1"
textline "                          "
bitfld.long 0x00 22. " GMB982 ,Group Modifier Bit 982" "0,1"
bitfld.long 0x00 21. "  GMB981 ,Group Modifier Bit 981" "0,1"
bitfld.long 0x00 20. "  GMB980 ,Group Modifier Bit 980" "0,1"
textline "                          "
bitfld.long 0x00 19. " GMB979 ,Group Modifier Bit 979" "0,1"
bitfld.long 0x00 18. "  GMB978 ,Group Modifier Bit 978" "0,1"
bitfld.long 0x00 17. "  GMB977 ,Group Modifier Bit 977" "0,1"
textline "                          "
bitfld.long 0x00 16. " GMB976 ,Group Modifier Bit 976" "0,1"
bitfld.long 0x00 15. "  GMB975 ,Group Modifier Bit 975" "0,1"
bitfld.long 0x00 14. "  GMB974 ,Group Modifier Bit 974" "0,1"
textline "                          "
bitfld.long 0x00 13. " GMB973 ,Group Modifier Bit 973" "0,1"
bitfld.long 0x00 12. "  GMB972 ,Group Modifier Bit 972" "0,1"
bitfld.long 0x00 11. "  GMB971 ,Group Modifier Bit 971" "0,1"
textline "                          "
bitfld.long 0x00 10. " GMB970 ,Group Modifier Bit 970" "0,1"
bitfld.long 0x00 9. "  GMB969 ,Group Modifier Bit 969" "0,1"
bitfld.long 0x00 8. "  GMB968 ,Group Modifier Bit 968" "0,1"
textline "                          "
bitfld.long 0x00 7. " GMB967 ,Group Modifier Bit 967" "0,1"
bitfld.long 0x00 6. "  GMB966 ,Group Modifier Bit 966" "0,1"
bitfld.long 0x00 5. "  GMB965 ,Group Modifier Bit 965" "0,1"
textline "                          "
bitfld.long 0x00 4. " GMB964 ,Group Modifier Bit 964" "0,1"
bitfld.long 0x00 3. "  GMB963 ,Group Modifier Bit 963" "0,1"
bitfld.long 0x00 2. "  GMB962 ,Group Modifier Bit 962" "0,1"
textline "                          "
bitfld.long 0x00 1. " GMB961 ,Group Modifier Bit 961" "0,1"
bitfld.long 0x00 0. "  GMB960 ,Group Modifier Bit 960" "0,1"
else
hgroup.long 0x0D78++0x03
hide.long 0x0 "GICD_IGRPMODR30,Interrupt Group Modifier Register 30"
endif
tree.end
width 14.
tree "Non-secure Access Control Registers"
hgroup.long 0x0E00++0x03
hide.long 0x00 "GICD_NSACR0,Non-secure Access Control Register 0"
hgroup.long 0xE04++0x03
hide.long 0x00 "GICD_NSACR1,Non-secure Access Control Register 1"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE08)))
group.long 0xE08++0x03
line.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
bitfld.long 0x00 30.--31. " NS_ACCESS47  ,Controls Non-secure access of the interrupt with ID47 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS46  ,Controls Non-secure access of the interrupt with ID46 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS45  ,Controls Non-secure access of the interrupt with ID45 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS44  ,Controls Non-secure access of the interrupt with ID44 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS43  ,Controls Non-secure access of the interrupt with ID43 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS42  ,Controls Non-secure access of the interrupt with ID42 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS41  ,Controls Non-secure access of the interrupt with ID41 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS40  ,Controls Non-secure access of the interrupt with ID40 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS39  ,Controls Non-secure access of the interrupt with ID39 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS38  ,Controls Non-secure access of the interrupt with ID38 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS37  ,Controls Non-secure access of the interrupt with ID37 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS36  ,Controls Non-secure access of the interrupt with ID36 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS35  ,Controls Non-secure access of the interrupt with ID35 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS34  ,Controls Non-secure access of the interrupt with ID34 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS33  ,Controls Non-secure access of the interrupt with ID33 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS32  ,Controls Non-secure access of the interrupt with ID32 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE08++0x03
hide.long 0x00 "GICD_NSACR2,Non-secure Access Control Register 2"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE0C)))
group.long 0xE0C++0x03
line.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
bitfld.long 0x00 30.--31. " NS_ACCESS63  ,Controls Non-secure access of the interrupt with ID63 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS62  ,Controls Non-secure access of the interrupt with ID62 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS61  ,Controls Non-secure access of the interrupt with ID61 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS60  ,Controls Non-secure access of the interrupt with ID60 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS59  ,Controls Non-secure access of the interrupt with ID59 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS58  ,Controls Non-secure access of the interrupt with ID58 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS57  ,Controls Non-secure access of the interrupt with ID57 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS56  ,Controls Non-secure access of the interrupt with ID56 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS55  ,Controls Non-secure access of the interrupt with ID55 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS54  ,Controls Non-secure access of the interrupt with ID54 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS53  ,Controls Non-secure access of the interrupt with ID53 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS52  ,Controls Non-secure access of the interrupt with ID52 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS51  ,Controls Non-secure access of the interrupt with ID51 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS50  ,Controls Non-secure access of the interrupt with ID50 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS49  ,Controls Non-secure access of the interrupt with ID49 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS48  ,Controls Non-secure access of the interrupt with ID48 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE0C++0x03
hide.long 0x00 "GICD_NSACR3,Non-secure Access Control Register 3"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE10)))
group.long 0xE10++0x03
line.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
bitfld.long 0x00 30.--31. " NS_ACCESS79  ,Controls Non-secure access of the interrupt with ID79 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS78  ,Controls Non-secure access of the interrupt with ID78 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS77  ,Controls Non-secure access of the interrupt with ID77 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS76  ,Controls Non-secure access of the interrupt with ID76 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS75  ,Controls Non-secure access of the interrupt with ID75 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS74  ,Controls Non-secure access of the interrupt with ID74 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS73  ,Controls Non-secure access of the interrupt with ID73 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS72  ,Controls Non-secure access of the interrupt with ID72 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS71  ,Controls Non-secure access of the interrupt with ID71 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS70  ,Controls Non-secure access of the interrupt with ID70 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS69  ,Controls Non-secure access of the interrupt with ID69 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS68  ,Controls Non-secure access of the interrupt with ID68 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS67  ,Controls Non-secure access of the interrupt with ID67 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS66  ,Controls Non-secure access of the interrupt with ID66 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS65  ,Controls Non-secure access of the interrupt with ID65 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS64  ,Controls Non-secure access of the interrupt with ID64 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE10++0x03
hide.long 0x00 "GICD_NSACR4,Non-secure Access Control Register 4"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE14)))
group.long 0xE14++0x03
line.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
bitfld.long 0x00 30.--31. " NS_ACCESS95  ,Controls Non-secure access of the interrupt with ID95 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS94  ,Controls Non-secure access of the interrupt with ID94 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS93  ,Controls Non-secure access of the interrupt with ID93 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS92  ,Controls Non-secure access of the interrupt with ID92 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS91  ,Controls Non-secure access of the interrupt with ID91 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS90  ,Controls Non-secure access of the interrupt with ID90 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS89  ,Controls Non-secure access of the interrupt with ID89 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS88  ,Controls Non-secure access of the interrupt with ID88 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS87  ,Controls Non-secure access of the interrupt with ID87 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS86  ,Controls Non-secure access of the interrupt with ID86 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS85  ,Controls Non-secure access of the interrupt with ID85 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS84  ,Controls Non-secure access of the interrupt with ID84 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS83  ,Controls Non-secure access of the interrupt with ID83 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS82  ,Controls Non-secure access of the interrupt with ID82 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS81  ,Controls Non-secure access of the interrupt with ID81 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS80  ,Controls Non-secure access of the interrupt with ID80 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE14++0x03
hide.long 0x00 "GICD_NSACR5,Non-secure Access Control Register 5"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE18)))
group.long 0xE18++0x03
line.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
bitfld.long 0x00 30.--31. " NS_ACCESS111 ,Controls Non-secure access of the interrupt with ID111" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS110 ,Controls Non-secure access of the interrupt with ID110" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS109 ,Controls Non-secure access of the interrupt with ID109" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS108 ,Controls Non-secure access of the interrupt with ID108" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS107 ,Controls Non-secure access of the interrupt with ID107" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS106 ,Controls Non-secure access of the interrupt with ID106" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS105 ,Controls Non-secure access of the interrupt with ID105" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS104 ,Controls Non-secure access of the interrupt with ID104" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS103 ,Controls Non-secure access of the interrupt with ID103" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS102 ,Controls Non-secure access of the interrupt with ID102" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS101 ,Controls Non-secure access of the interrupt with ID101" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS100 ,Controls Non-secure access of the interrupt with ID100" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS99  ,Controls Non-secure access of the interrupt with ID99 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS98  ,Controls Non-secure access of the interrupt with ID98 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS97  ,Controls Non-secure access of the interrupt with ID97 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS96  ,Controls Non-secure access of the interrupt with ID96 " "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE18++0x03
hide.long 0x00 "GICD_NSACR6,Non-secure Access Control Register 6"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE1C)))
group.long 0xE1C++0x03
line.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
bitfld.long 0x00 30.--31. " NS_ACCESS127 ,Controls Non-secure access of the interrupt with ID127" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS126 ,Controls Non-secure access of the interrupt with ID126" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS125 ,Controls Non-secure access of the interrupt with ID125" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS124 ,Controls Non-secure access of the interrupt with ID124" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS123 ,Controls Non-secure access of the interrupt with ID123" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS122 ,Controls Non-secure access of the interrupt with ID122" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS121 ,Controls Non-secure access of the interrupt with ID121" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS120 ,Controls Non-secure access of the interrupt with ID120" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS119 ,Controls Non-secure access of the interrupt with ID119" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS118 ,Controls Non-secure access of the interrupt with ID118" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS117 ,Controls Non-secure access of the interrupt with ID117" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS116 ,Controls Non-secure access of the interrupt with ID116" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS115 ,Controls Non-secure access of the interrupt with ID115" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS114 ,Controls Non-secure access of the interrupt with ID114" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS113 ,Controls Non-secure access of the interrupt with ID113" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS112 ,Controls Non-secure access of the interrupt with ID112" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE1C++0x03
hide.long 0x00 "GICD_NSACR7,Non-secure Access Control Register 7"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE20)))
group.long 0xE20++0x03
line.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
bitfld.long 0x00 30.--31. " NS_ACCESS143 ,Controls Non-secure access of the interrupt with ID143" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS142 ,Controls Non-secure access of the interrupt with ID142" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS141 ,Controls Non-secure access of the interrupt with ID141" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS140 ,Controls Non-secure access of the interrupt with ID140" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS139 ,Controls Non-secure access of the interrupt with ID139" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS138 ,Controls Non-secure access of the interrupt with ID138" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS137 ,Controls Non-secure access of the interrupt with ID137" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS136 ,Controls Non-secure access of the interrupt with ID136" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS135 ,Controls Non-secure access of the interrupt with ID135" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS134 ,Controls Non-secure access of the interrupt with ID134" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS133 ,Controls Non-secure access of the interrupt with ID133" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS132 ,Controls Non-secure access of the interrupt with ID132" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS131 ,Controls Non-secure access of the interrupt with ID131" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS130 ,Controls Non-secure access of the interrupt with ID130" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS129 ,Controls Non-secure access of the interrupt with ID129" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS128 ,Controls Non-secure access of the interrupt with ID128" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE20++0x03
hide.long 0x00 "GICD_NSACR8,Non-secure Access Control Register 8"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE24)))
group.long 0xE24++0x03
line.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
bitfld.long 0x00 30.--31. " NS_ACCESS159 ,Controls Non-secure access of the interrupt with ID159" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS158 ,Controls Non-secure access of the interrupt with ID158" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS157 ,Controls Non-secure access of the interrupt with ID157" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS156 ,Controls Non-secure access of the interrupt with ID156" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS155 ,Controls Non-secure access of the interrupt with ID155" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS154 ,Controls Non-secure access of the interrupt with ID154" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS153 ,Controls Non-secure access of the interrupt with ID153" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS152 ,Controls Non-secure access of the interrupt with ID152" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS151 ,Controls Non-secure access of the interrupt with ID151" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS150 ,Controls Non-secure access of the interrupt with ID150" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS149 ,Controls Non-secure access of the interrupt with ID149" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS148 ,Controls Non-secure access of the interrupt with ID148" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS147 ,Controls Non-secure access of the interrupt with ID147" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS146 ,Controls Non-secure access of the interrupt with ID146" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS145 ,Controls Non-secure access of the interrupt with ID145" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS144 ,Controls Non-secure access of the interrupt with ID144" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE24++0x03
hide.long 0x00 "GICD_NSACR9,Non-secure Access Control Register 9"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE28)))
group.long 0xE28++0x03
line.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
bitfld.long 0x00 30.--31. " NS_ACCESS175 ,Controls Non-secure access of the interrupt with ID175" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS174 ,Controls Non-secure access of the interrupt with ID174" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS173 ,Controls Non-secure access of the interrupt with ID173" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS172 ,Controls Non-secure access of the interrupt with ID172" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS171 ,Controls Non-secure access of the interrupt with ID171" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS170 ,Controls Non-secure access of the interrupt with ID170" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS169 ,Controls Non-secure access of the interrupt with ID169" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS168 ,Controls Non-secure access of the interrupt with ID168" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS167 ,Controls Non-secure access of the interrupt with ID167" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS166 ,Controls Non-secure access of the interrupt with ID166" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS165 ,Controls Non-secure access of the interrupt with ID165" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS164 ,Controls Non-secure access of the interrupt with ID164" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS163 ,Controls Non-secure access of the interrupt with ID163" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS162 ,Controls Non-secure access of the interrupt with ID162" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS161 ,Controls Non-secure access of the interrupt with ID161" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS160 ,Controls Non-secure access of the interrupt with ID160" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE28++0x03
hide.long 0x00 "GICD_NSACR10,Non-secure Access Control Register 10"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE2C)))
group.long 0xE2C++0x03
line.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
bitfld.long 0x00 30.--31. " NS_ACCESS191 ,Controls Non-secure access of the interrupt with ID191" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS190 ,Controls Non-secure access of the interrupt with ID190" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS189 ,Controls Non-secure access of the interrupt with ID189" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS188 ,Controls Non-secure access of the interrupt with ID188" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS187 ,Controls Non-secure access of the interrupt with ID187" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS186 ,Controls Non-secure access of the interrupt with ID186" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS185 ,Controls Non-secure access of the interrupt with ID185" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS184 ,Controls Non-secure access of the interrupt with ID184" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS183 ,Controls Non-secure access of the interrupt with ID183" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS182 ,Controls Non-secure access of the interrupt with ID182" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS181 ,Controls Non-secure access of the interrupt with ID181" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS180 ,Controls Non-secure access of the interrupt with ID180" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS179 ,Controls Non-secure access of the interrupt with ID179" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS178 ,Controls Non-secure access of the interrupt with ID178" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS177 ,Controls Non-secure access of the interrupt with ID177" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS176 ,Controls Non-secure access of the interrupt with ID176" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE2C++0x03
hide.long 0x00 "GICD_NSACR11,Non-secure Access Control Register 11"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE30)))
group.long 0xE30++0x03
line.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
bitfld.long 0x00 30.--31. " NS_ACCESS207 ,Controls Non-secure access of the interrupt with ID207" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS206 ,Controls Non-secure access of the interrupt with ID206" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS205 ,Controls Non-secure access of the interrupt with ID205" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS204 ,Controls Non-secure access of the interrupt with ID204" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS203 ,Controls Non-secure access of the interrupt with ID203" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS202 ,Controls Non-secure access of the interrupt with ID202" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS201 ,Controls Non-secure access of the interrupt with ID201" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS200 ,Controls Non-secure access of the interrupt with ID200" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS199 ,Controls Non-secure access of the interrupt with ID199" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS198 ,Controls Non-secure access of the interrupt with ID198" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS197 ,Controls Non-secure access of the interrupt with ID197" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS196 ,Controls Non-secure access of the interrupt with ID196" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS195 ,Controls Non-secure access of the interrupt with ID195" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS194 ,Controls Non-secure access of the interrupt with ID194" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS193 ,Controls Non-secure access of the interrupt with ID193" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS192 ,Controls Non-secure access of the interrupt with ID192" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE30++0x03
hide.long 0x00 "GICD_NSACR12,Non-secure Access Control Register 12"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE34)))
group.long 0xE34++0x03
line.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
bitfld.long 0x00 30.--31. " NS_ACCESS223 ,Controls Non-secure access of the interrupt with ID223" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS222 ,Controls Non-secure access of the interrupt with ID222" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS221 ,Controls Non-secure access of the interrupt with ID221" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS220 ,Controls Non-secure access of the interrupt with ID220" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS219 ,Controls Non-secure access of the interrupt with ID219" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS218 ,Controls Non-secure access of the interrupt with ID218" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS217 ,Controls Non-secure access of the interrupt with ID217" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS216 ,Controls Non-secure access of the interrupt with ID216" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS215 ,Controls Non-secure access of the interrupt with ID215" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS214 ,Controls Non-secure access of the interrupt with ID214" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS213 ,Controls Non-secure access of the interrupt with ID213" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS212 ,Controls Non-secure access of the interrupt with ID212" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS211 ,Controls Non-secure access of the interrupt with ID211" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS210 ,Controls Non-secure access of the interrupt with ID210" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS209 ,Controls Non-secure access of the interrupt with ID209" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS208 ,Controls Non-secure access of the interrupt with ID208" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE34++0x03
hide.long 0x00 "GICD_NSACR13,Non-secure Access Control Register 13"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE38)))
group.long 0xE38++0x03
line.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
bitfld.long 0x00 30.--31. " NS_ACCESS239 ,Controls Non-secure access of the interrupt with ID239" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS238 ,Controls Non-secure access of the interrupt with ID238" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS237 ,Controls Non-secure access of the interrupt with ID237" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS236 ,Controls Non-secure access of the interrupt with ID236" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS235 ,Controls Non-secure access of the interrupt with ID235" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS234 ,Controls Non-secure access of the interrupt with ID234" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS233 ,Controls Non-secure access of the interrupt with ID233" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS232 ,Controls Non-secure access of the interrupt with ID232" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS231 ,Controls Non-secure access of the interrupt with ID231" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS230 ,Controls Non-secure access of the interrupt with ID230" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS229 ,Controls Non-secure access of the interrupt with ID229" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS228 ,Controls Non-secure access of the interrupt with ID228" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS227 ,Controls Non-secure access of the interrupt with ID227" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS226 ,Controls Non-secure access of the interrupt with ID226" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS225 ,Controls Non-secure access of the interrupt with ID225" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS224 ,Controls Non-secure access of the interrupt with ID224" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE38++0x03
hide.long 0x00 "GICD_NSACR14,Non-secure Access Control Register 14"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE3C)))
group.long 0xE3C++0x03
line.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
bitfld.long 0x00 30.--31. " NS_ACCESS255 ,Controls Non-secure access of the interrupt with ID255" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS254 ,Controls Non-secure access of the interrupt with ID254" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS253 ,Controls Non-secure access of the interrupt with ID253" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS252 ,Controls Non-secure access of the interrupt with ID252" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS251 ,Controls Non-secure access of the interrupt with ID251" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS250 ,Controls Non-secure access of the interrupt with ID250" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS249 ,Controls Non-secure access of the interrupt with ID249" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS248 ,Controls Non-secure access of the interrupt with ID248" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS247 ,Controls Non-secure access of the interrupt with ID247" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS246 ,Controls Non-secure access of the interrupt with ID246" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS245 ,Controls Non-secure access of the interrupt with ID245" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS244 ,Controls Non-secure access of the interrupt with ID244" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS243 ,Controls Non-secure access of the interrupt with ID243" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS242 ,Controls Non-secure access of the interrupt with ID242" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS241 ,Controls Non-secure access of the interrupt with ID241" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS240 ,Controls Non-secure access of the interrupt with ID240" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE3C++0x03
hide.long 0x00 "GICD_NSACR15,Non-secure Access Control Register 15"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE40)))
group.long 0xE40++0x03
line.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
bitfld.long 0x00 30.--31. " NS_ACCESS271 ,Controls Non-secure access of the interrupt with ID271" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS270 ,Controls Non-secure access of the interrupt with ID270" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS269 ,Controls Non-secure access of the interrupt with ID269" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS268 ,Controls Non-secure access of the interrupt with ID268" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS267 ,Controls Non-secure access of the interrupt with ID267" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS266 ,Controls Non-secure access of the interrupt with ID266" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS265 ,Controls Non-secure access of the interrupt with ID265" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS264 ,Controls Non-secure access of the interrupt with ID264" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS263 ,Controls Non-secure access of the interrupt with ID263" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS262 ,Controls Non-secure access of the interrupt with ID262" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS261 ,Controls Non-secure access of the interrupt with ID261" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS260 ,Controls Non-secure access of the interrupt with ID260" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS259 ,Controls Non-secure access of the interrupt with ID259" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS258 ,Controls Non-secure access of the interrupt with ID258" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS257 ,Controls Non-secure access of the interrupt with ID257" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS256 ,Controls Non-secure access of the interrupt with ID256" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE40++0x03
hide.long 0x00 "GICD_NSACR16,Non-secure Access Control Register 16"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE44)))
group.long 0xE44++0x03
line.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
bitfld.long 0x00 30.--31. " NS_ACCESS287 ,Controls Non-secure access of the interrupt with ID287" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS286 ,Controls Non-secure access of the interrupt with ID286" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS285 ,Controls Non-secure access of the interrupt with ID285" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS284 ,Controls Non-secure access of the interrupt with ID284" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS283 ,Controls Non-secure access of the interrupt with ID283" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS282 ,Controls Non-secure access of the interrupt with ID282" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS281 ,Controls Non-secure access of the interrupt with ID281" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS280 ,Controls Non-secure access of the interrupt with ID280" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS279 ,Controls Non-secure access of the interrupt with ID279" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS278 ,Controls Non-secure access of the interrupt with ID278" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS277 ,Controls Non-secure access of the interrupt with ID277" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS276 ,Controls Non-secure access of the interrupt with ID276" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS275 ,Controls Non-secure access of the interrupt with ID275" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS274 ,Controls Non-secure access of the interrupt with ID274" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS273 ,Controls Non-secure access of the interrupt with ID273" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS272 ,Controls Non-secure access of the interrupt with ID272" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE44++0x03
hide.long 0x00 "GICD_NSACR17,Non-secure Access Control Register 17"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE48)))
group.long 0xE48++0x03
line.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
bitfld.long 0x00 30.--31. " NS_ACCESS303 ,Controls Non-secure access of the interrupt with ID303" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS302 ,Controls Non-secure access of the interrupt with ID302" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS301 ,Controls Non-secure access of the interrupt with ID301" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS300 ,Controls Non-secure access of the interrupt with ID300" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS299 ,Controls Non-secure access of the interrupt with ID299" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS298 ,Controls Non-secure access of the interrupt with ID298" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS297 ,Controls Non-secure access of the interrupt with ID297" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS296 ,Controls Non-secure access of the interrupt with ID296" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS295 ,Controls Non-secure access of the interrupt with ID295" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS294 ,Controls Non-secure access of the interrupt with ID294" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS293 ,Controls Non-secure access of the interrupt with ID293" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS292 ,Controls Non-secure access of the interrupt with ID292" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS291 ,Controls Non-secure access of the interrupt with ID291" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS290 ,Controls Non-secure access of the interrupt with ID290" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS289 ,Controls Non-secure access of the interrupt with ID289" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS288 ,Controls Non-secure access of the interrupt with ID288" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE48++0x03
hide.long 0x00 "GICD_NSACR18,Non-secure Access Control Register 18"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE4C)))
group.long 0xE4C++0x03
line.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
bitfld.long 0x00 30.--31. " NS_ACCESS319 ,Controls Non-secure access of the interrupt with ID319" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS318 ,Controls Non-secure access of the interrupt with ID318" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS317 ,Controls Non-secure access of the interrupt with ID317" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS316 ,Controls Non-secure access of the interrupt with ID316" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS315 ,Controls Non-secure access of the interrupt with ID315" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS314 ,Controls Non-secure access of the interrupt with ID314" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS313 ,Controls Non-secure access of the interrupt with ID313" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS312 ,Controls Non-secure access of the interrupt with ID312" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS311 ,Controls Non-secure access of the interrupt with ID311" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS310 ,Controls Non-secure access of the interrupt with ID310" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS309 ,Controls Non-secure access of the interrupt with ID309" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS308 ,Controls Non-secure access of the interrupt with ID308" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS307 ,Controls Non-secure access of the interrupt with ID307" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS306 ,Controls Non-secure access of the interrupt with ID306" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS305 ,Controls Non-secure access of the interrupt with ID305" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS304 ,Controls Non-secure access of the interrupt with ID304" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE4C++0x03
hide.long 0x00 "GICD_NSACR19,Non-secure Access Control Register 19"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE50)))
group.long 0xE50++0x03
line.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
bitfld.long 0x00 30.--31. " NS_ACCESS335 ,Controls Non-secure access of the interrupt with ID335" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS334 ,Controls Non-secure access of the interrupt with ID334" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS333 ,Controls Non-secure access of the interrupt with ID333" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS332 ,Controls Non-secure access of the interrupt with ID332" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS331 ,Controls Non-secure access of the interrupt with ID331" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS330 ,Controls Non-secure access of the interrupt with ID330" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS329 ,Controls Non-secure access of the interrupt with ID329" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS328 ,Controls Non-secure access of the interrupt with ID328" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS327 ,Controls Non-secure access of the interrupt with ID327" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS326 ,Controls Non-secure access of the interrupt with ID326" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS325 ,Controls Non-secure access of the interrupt with ID325" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS324 ,Controls Non-secure access of the interrupt with ID324" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS323 ,Controls Non-secure access of the interrupt with ID323" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS322 ,Controls Non-secure access of the interrupt with ID322" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS321 ,Controls Non-secure access of the interrupt with ID321" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS320 ,Controls Non-secure access of the interrupt with ID320" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE50++0x03
hide.long 0x00 "GICD_NSACR20,Non-secure Access Control Register 20"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE54)))
group.long 0xE54++0x03
line.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
bitfld.long 0x00 30.--31. " NS_ACCESS351 ,Controls Non-secure access of the interrupt with ID351" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS350 ,Controls Non-secure access of the interrupt with ID350" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS349 ,Controls Non-secure access of the interrupt with ID349" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS348 ,Controls Non-secure access of the interrupt with ID348" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS347 ,Controls Non-secure access of the interrupt with ID347" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS346 ,Controls Non-secure access of the interrupt with ID346" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS345 ,Controls Non-secure access of the interrupt with ID345" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS344 ,Controls Non-secure access of the interrupt with ID344" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS343 ,Controls Non-secure access of the interrupt with ID343" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS342 ,Controls Non-secure access of the interrupt with ID342" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS341 ,Controls Non-secure access of the interrupt with ID341" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS340 ,Controls Non-secure access of the interrupt with ID340" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS339 ,Controls Non-secure access of the interrupt with ID339" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS338 ,Controls Non-secure access of the interrupt with ID338" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS337 ,Controls Non-secure access of the interrupt with ID337" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS336 ,Controls Non-secure access of the interrupt with ID336" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE54++0x03
hide.long 0x00 "GICD_NSACR21,Non-secure Access Control Register 21"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE58)))
group.long 0xE58++0x03
line.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
bitfld.long 0x00 30.--31. " NS_ACCESS367 ,Controls Non-secure access of the interrupt with ID367" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS366 ,Controls Non-secure access of the interrupt with ID366" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS365 ,Controls Non-secure access of the interrupt with ID365" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS364 ,Controls Non-secure access of the interrupt with ID364" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS363 ,Controls Non-secure access of the interrupt with ID363" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS362 ,Controls Non-secure access of the interrupt with ID362" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS361 ,Controls Non-secure access of the interrupt with ID361" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS360 ,Controls Non-secure access of the interrupt with ID360" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS359 ,Controls Non-secure access of the interrupt with ID359" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS358 ,Controls Non-secure access of the interrupt with ID358" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS357 ,Controls Non-secure access of the interrupt with ID357" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS356 ,Controls Non-secure access of the interrupt with ID356" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS355 ,Controls Non-secure access of the interrupt with ID355" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS354 ,Controls Non-secure access of the interrupt with ID354" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS353 ,Controls Non-secure access of the interrupt with ID353" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS352 ,Controls Non-secure access of the interrupt with ID352" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE58++0x03
hide.long 0x00 "GICD_NSACR22,Non-secure Access Control Register 22"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE5C)))
group.long 0xE5C++0x03
line.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
bitfld.long 0x00 30.--31. " NS_ACCESS383 ,Controls Non-secure access of the interrupt with ID383" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS382 ,Controls Non-secure access of the interrupt with ID382" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS381 ,Controls Non-secure access of the interrupt with ID381" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS380 ,Controls Non-secure access of the interrupt with ID380" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS379 ,Controls Non-secure access of the interrupt with ID379" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS378 ,Controls Non-secure access of the interrupt with ID378" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS377 ,Controls Non-secure access of the interrupt with ID377" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS376 ,Controls Non-secure access of the interrupt with ID376" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS375 ,Controls Non-secure access of the interrupt with ID375" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS374 ,Controls Non-secure access of the interrupt with ID374" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS373 ,Controls Non-secure access of the interrupt with ID373" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS372 ,Controls Non-secure access of the interrupt with ID372" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS371 ,Controls Non-secure access of the interrupt with ID371" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS370 ,Controls Non-secure access of the interrupt with ID370" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS369 ,Controls Non-secure access of the interrupt with ID369" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS368 ,Controls Non-secure access of the interrupt with ID368" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE5C++0x03
hide.long 0x00 "GICD_NSACR23,Non-secure Access Control Register 23"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE60)))
group.long 0xE60++0x03
line.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
bitfld.long 0x00 30.--31. " NS_ACCESS399 ,Controls Non-secure access of the interrupt with ID399" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS398 ,Controls Non-secure access of the interrupt with ID398" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS397 ,Controls Non-secure access of the interrupt with ID397" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS396 ,Controls Non-secure access of the interrupt with ID396" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS395 ,Controls Non-secure access of the interrupt with ID395" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS394 ,Controls Non-secure access of the interrupt with ID394" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS393 ,Controls Non-secure access of the interrupt with ID393" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS392 ,Controls Non-secure access of the interrupt with ID392" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS391 ,Controls Non-secure access of the interrupt with ID391" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS390 ,Controls Non-secure access of the interrupt with ID390" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS389 ,Controls Non-secure access of the interrupt with ID389" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS388 ,Controls Non-secure access of the interrupt with ID388" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS387 ,Controls Non-secure access of the interrupt with ID387" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS386 ,Controls Non-secure access of the interrupt with ID386" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS385 ,Controls Non-secure access of the interrupt with ID385" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS384 ,Controls Non-secure access of the interrupt with ID384" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE60++0x03
hide.long 0x00 "GICD_NSACR24,Non-secure Access Control Register 24"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE64)))
group.long 0xE64++0x03
line.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
bitfld.long 0x00 30.--31. " NS_ACCESS415 ,Controls Non-secure access of the interrupt with ID415" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS414 ,Controls Non-secure access of the interrupt with ID414" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS413 ,Controls Non-secure access of the interrupt with ID413" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS412 ,Controls Non-secure access of the interrupt with ID412" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS411 ,Controls Non-secure access of the interrupt with ID411" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS410 ,Controls Non-secure access of the interrupt with ID410" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS409 ,Controls Non-secure access of the interrupt with ID409" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS408 ,Controls Non-secure access of the interrupt with ID408" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS407 ,Controls Non-secure access of the interrupt with ID407" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS406 ,Controls Non-secure access of the interrupt with ID406" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS405 ,Controls Non-secure access of the interrupt with ID405" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS404 ,Controls Non-secure access of the interrupt with ID404" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS403 ,Controls Non-secure access of the interrupt with ID403" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS402 ,Controls Non-secure access of the interrupt with ID402" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS401 ,Controls Non-secure access of the interrupt with ID401" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS400 ,Controls Non-secure access of the interrupt with ID400" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE64++0x03
hide.long 0x00 "GICD_NSACR25,Non-secure Access Control Register 25"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE68)))
group.long 0xE68++0x03
line.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
bitfld.long 0x00 30.--31. " NS_ACCESS431 ,Controls Non-secure access of the interrupt with ID431" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS430 ,Controls Non-secure access of the interrupt with ID430" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS429 ,Controls Non-secure access of the interrupt with ID429" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS428 ,Controls Non-secure access of the interrupt with ID428" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS427 ,Controls Non-secure access of the interrupt with ID427" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS426 ,Controls Non-secure access of the interrupt with ID426" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS425 ,Controls Non-secure access of the interrupt with ID425" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS424 ,Controls Non-secure access of the interrupt with ID424" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS423 ,Controls Non-secure access of the interrupt with ID423" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS422 ,Controls Non-secure access of the interrupt with ID422" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS421 ,Controls Non-secure access of the interrupt with ID421" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS420 ,Controls Non-secure access of the interrupt with ID420" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS419 ,Controls Non-secure access of the interrupt with ID419" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS418 ,Controls Non-secure access of the interrupt with ID418" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS417 ,Controls Non-secure access of the interrupt with ID417" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS416 ,Controls Non-secure access of the interrupt with ID416" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE68++0x03
hide.long 0x00 "GICD_NSACR26,Non-secure Access Control Register 26"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE6C)))
group.long 0xE6C++0x03
line.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
bitfld.long 0x00 30.--31. " NS_ACCESS447 ,Controls Non-secure access of the interrupt with ID447" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS446 ,Controls Non-secure access of the interrupt with ID446" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS445 ,Controls Non-secure access of the interrupt with ID445" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS444 ,Controls Non-secure access of the interrupt with ID444" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS443 ,Controls Non-secure access of the interrupt with ID443" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS442 ,Controls Non-secure access of the interrupt with ID442" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS441 ,Controls Non-secure access of the interrupt with ID441" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS440 ,Controls Non-secure access of the interrupt with ID440" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS439 ,Controls Non-secure access of the interrupt with ID439" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS438 ,Controls Non-secure access of the interrupt with ID438" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS437 ,Controls Non-secure access of the interrupt with ID437" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS436 ,Controls Non-secure access of the interrupt with ID436" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS435 ,Controls Non-secure access of the interrupt with ID435" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS434 ,Controls Non-secure access of the interrupt with ID434" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS433 ,Controls Non-secure access of the interrupt with ID433" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS432 ,Controls Non-secure access of the interrupt with ID432" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE6C++0x03
hide.long 0x00 "GICD_NSACR27,Non-secure Access Control Register 27"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE70)))
group.long 0xE70++0x03
line.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
bitfld.long 0x00 30.--31. " NS_ACCESS463 ,Controls Non-secure access of the interrupt with ID463" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS462 ,Controls Non-secure access of the interrupt with ID462" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS461 ,Controls Non-secure access of the interrupt with ID461" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS460 ,Controls Non-secure access of the interrupt with ID460" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS459 ,Controls Non-secure access of the interrupt with ID459" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS458 ,Controls Non-secure access of the interrupt with ID458" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS457 ,Controls Non-secure access of the interrupt with ID457" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS456 ,Controls Non-secure access of the interrupt with ID456" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS455 ,Controls Non-secure access of the interrupt with ID455" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS454 ,Controls Non-secure access of the interrupt with ID454" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS453 ,Controls Non-secure access of the interrupt with ID453" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS452 ,Controls Non-secure access of the interrupt with ID452" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS451 ,Controls Non-secure access of the interrupt with ID451" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS450 ,Controls Non-secure access of the interrupt with ID450" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS449 ,Controls Non-secure access of the interrupt with ID449" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS448 ,Controls Non-secure access of the interrupt with ID448" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE70++0x03
hide.long 0x00 "GICD_NSACR28,Non-secure Access Control Register 28"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE74)))
group.long 0xE74++0x03
line.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
bitfld.long 0x00 30.--31. " NS_ACCESS479 ,Controls Non-secure access of the interrupt with ID479" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS478 ,Controls Non-secure access of the interrupt with ID478" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS477 ,Controls Non-secure access of the interrupt with ID477" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS476 ,Controls Non-secure access of the interrupt with ID476" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS475 ,Controls Non-secure access of the interrupt with ID475" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS474 ,Controls Non-secure access of the interrupt with ID474" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS473 ,Controls Non-secure access of the interrupt with ID473" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS472 ,Controls Non-secure access of the interrupt with ID472" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS471 ,Controls Non-secure access of the interrupt with ID471" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS470 ,Controls Non-secure access of the interrupt with ID470" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS469 ,Controls Non-secure access of the interrupt with ID469" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS468 ,Controls Non-secure access of the interrupt with ID468" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS467 ,Controls Non-secure access of the interrupt with ID467" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS466 ,Controls Non-secure access of the interrupt with ID466" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS465 ,Controls Non-secure access of the interrupt with ID465" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS464 ,Controls Non-secure access of the interrupt with ID464" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE74++0x03
hide.long 0x00 "GICD_NSACR29,Non-secure Access Control Register 29"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE78)))
group.long 0xE78++0x03
line.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
bitfld.long 0x00 30.--31. " NS_ACCESS495 ,Controls Non-secure access of the interrupt with ID495" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS494 ,Controls Non-secure access of the interrupt with ID494" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS493 ,Controls Non-secure access of the interrupt with ID493" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS492 ,Controls Non-secure access of the interrupt with ID492" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS491 ,Controls Non-secure access of the interrupt with ID491" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS490 ,Controls Non-secure access of the interrupt with ID490" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS489 ,Controls Non-secure access of the interrupt with ID489" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS488 ,Controls Non-secure access of the interrupt with ID488" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS487 ,Controls Non-secure access of the interrupt with ID487" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS486 ,Controls Non-secure access of the interrupt with ID486" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS485 ,Controls Non-secure access of the interrupt with ID485" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS484 ,Controls Non-secure access of the interrupt with ID484" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS483 ,Controls Non-secure access of the interrupt with ID483" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS482 ,Controls Non-secure access of the interrupt with ID482" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS481 ,Controls Non-secure access of the interrupt with ID481" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS480 ,Controls Non-secure access of the interrupt with ID480" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE78++0x03
hide.long 0x00 "GICD_NSACR30,Non-secure Access Control Register 30"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE7C)))
group.long 0xE7C++0x03
line.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
bitfld.long 0x00 30.--31. " NS_ACCESS511 ,Controls Non-secure access of the interrupt with ID511" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS510 ,Controls Non-secure access of the interrupt with ID510" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS509 ,Controls Non-secure access of the interrupt with ID509" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS508 ,Controls Non-secure access of the interrupt with ID508" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS507 ,Controls Non-secure access of the interrupt with ID507" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS506 ,Controls Non-secure access of the interrupt with ID506" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS505 ,Controls Non-secure access of the interrupt with ID505" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS504 ,Controls Non-secure access of the interrupt with ID504" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS503 ,Controls Non-secure access of the interrupt with ID503" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS502 ,Controls Non-secure access of the interrupt with ID502" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS501 ,Controls Non-secure access of the interrupt with ID501" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS500 ,Controls Non-secure access of the interrupt with ID500" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS499 ,Controls Non-secure access of the interrupt with ID499" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS498 ,Controls Non-secure access of the interrupt with ID498" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS497 ,Controls Non-secure access of the interrupt with ID497" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS496 ,Controls Non-secure access of the interrupt with ID496" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE7C++0x03
hide.long 0x00 "GICD_NSACR31,Non-secure Access Control Register 31"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE80)))
group.long 0xE80++0x03
line.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
bitfld.long 0x00 30.--31. " NS_ACCESS527 ,Controls Non-secure access of the interrupt with ID527" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS526 ,Controls Non-secure access of the interrupt with ID526" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS525 ,Controls Non-secure access of the interrupt with ID525" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS524 ,Controls Non-secure access of the interrupt with ID524" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS523 ,Controls Non-secure access of the interrupt with ID523" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS522 ,Controls Non-secure access of the interrupt with ID522" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS521 ,Controls Non-secure access of the interrupt with ID521" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS520 ,Controls Non-secure access of the interrupt with ID520" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS519 ,Controls Non-secure access of the interrupt with ID519" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS518 ,Controls Non-secure access of the interrupt with ID518" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS517 ,Controls Non-secure access of the interrupt with ID517" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS516 ,Controls Non-secure access of the interrupt with ID516" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS515 ,Controls Non-secure access of the interrupt with ID515" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS514 ,Controls Non-secure access of the interrupt with ID514" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS513 ,Controls Non-secure access of the interrupt with ID513" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS512 ,Controls Non-secure access of the interrupt with ID512" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE80++0x03
hide.long 0x00 "GICD_NSACR32,Non-secure Access Control Register 32"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE84)))
group.long 0xE84++0x03
line.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
bitfld.long 0x00 30.--31. " NS_ACCESS543 ,Controls Non-secure access of the interrupt with ID543" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS542 ,Controls Non-secure access of the interrupt with ID542" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS541 ,Controls Non-secure access of the interrupt with ID541" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS540 ,Controls Non-secure access of the interrupt with ID540" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS539 ,Controls Non-secure access of the interrupt with ID539" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS538 ,Controls Non-secure access of the interrupt with ID538" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS537 ,Controls Non-secure access of the interrupt with ID537" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS536 ,Controls Non-secure access of the interrupt with ID536" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS535 ,Controls Non-secure access of the interrupt with ID535" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS534 ,Controls Non-secure access of the interrupt with ID534" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS533 ,Controls Non-secure access of the interrupt with ID533" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS532 ,Controls Non-secure access of the interrupt with ID532" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS531 ,Controls Non-secure access of the interrupt with ID531" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS530 ,Controls Non-secure access of the interrupt with ID530" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS529 ,Controls Non-secure access of the interrupt with ID529" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS528 ,Controls Non-secure access of the interrupt with ID528" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE84++0x03
hide.long 0x00 "GICD_NSACR33,Non-secure Access Control Register 33"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE88)))
group.long 0xE88++0x03
line.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
bitfld.long 0x00 30.--31. " NS_ACCESS559 ,Controls Non-secure access of the interrupt with ID559" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS558 ,Controls Non-secure access of the interrupt with ID558" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS557 ,Controls Non-secure access of the interrupt with ID557" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS556 ,Controls Non-secure access of the interrupt with ID556" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS555 ,Controls Non-secure access of the interrupt with ID555" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS554 ,Controls Non-secure access of the interrupt with ID554" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS553 ,Controls Non-secure access of the interrupt with ID553" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS552 ,Controls Non-secure access of the interrupt with ID552" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS551 ,Controls Non-secure access of the interrupt with ID551" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS550 ,Controls Non-secure access of the interrupt with ID550" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS549 ,Controls Non-secure access of the interrupt with ID549" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS548 ,Controls Non-secure access of the interrupt with ID548" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS547 ,Controls Non-secure access of the interrupt with ID547" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS546 ,Controls Non-secure access of the interrupt with ID546" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS545 ,Controls Non-secure access of the interrupt with ID545" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS544 ,Controls Non-secure access of the interrupt with ID544" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE88++0x03
hide.long 0x00 "GICD_NSACR34,Non-secure Access Control Register 34"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE8C)))
group.long 0xE8C++0x03
line.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
bitfld.long 0x00 30.--31. " NS_ACCESS575 ,Controls Non-secure access of the interrupt with ID575" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS574 ,Controls Non-secure access of the interrupt with ID574" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS573 ,Controls Non-secure access of the interrupt with ID573" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS572 ,Controls Non-secure access of the interrupt with ID572" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS571 ,Controls Non-secure access of the interrupt with ID571" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS570 ,Controls Non-secure access of the interrupt with ID570" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS569 ,Controls Non-secure access of the interrupt with ID569" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS568 ,Controls Non-secure access of the interrupt with ID568" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS567 ,Controls Non-secure access of the interrupt with ID567" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS566 ,Controls Non-secure access of the interrupt with ID566" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS565 ,Controls Non-secure access of the interrupt with ID565" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS564 ,Controls Non-secure access of the interrupt with ID564" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS563 ,Controls Non-secure access of the interrupt with ID563" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS562 ,Controls Non-secure access of the interrupt with ID562" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS561 ,Controls Non-secure access of the interrupt with ID561" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS560 ,Controls Non-secure access of the interrupt with ID560" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE8C++0x03
hide.long 0x00 "GICD_NSACR35,Non-secure Access Control Register 35"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE90)))
group.long 0xE90++0x03
line.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
bitfld.long 0x00 30.--31. " NS_ACCESS591 ,Controls Non-secure access of the interrupt with ID591" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS590 ,Controls Non-secure access of the interrupt with ID590" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS589 ,Controls Non-secure access of the interrupt with ID589" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS588 ,Controls Non-secure access of the interrupt with ID588" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS587 ,Controls Non-secure access of the interrupt with ID587" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS586 ,Controls Non-secure access of the interrupt with ID586" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS585 ,Controls Non-secure access of the interrupt with ID585" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS584 ,Controls Non-secure access of the interrupt with ID584" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS583 ,Controls Non-secure access of the interrupt with ID583" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS582 ,Controls Non-secure access of the interrupt with ID582" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS581 ,Controls Non-secure access of the interrupt with ID581" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS580 ,Controls Non-secure access of the interrupt with ID580" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS579 ,Controls Non-secure access of the interrupt with ID579" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS578 ,Controls Non-secure access of the interrupt with ID578" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS577 ,Controls Non-secure access of the interrupt with ID577" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS576 ,Controls Non-secure access of the interrupt with ID576" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE90++0x03
hide.long 0x00 "GICD_NSACR36,Non-secure Access Control Register 36"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE94)))
group.long 0xE94++0x03
line.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
bitfld.long 0x00 30.--31. " NS_ACCESS607 ,Controls Non-secure access of the interrupt with ID607" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS606 ,Controls Non-secure access of the interrupt with ID606" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS605 ,Controls Non-secure access of the interrupt with ID605" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS604 ,Controls Non-secure access of the interrupt with ID604" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS603 ,Controls Non-secure access of the interrupt with ID603" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS602 ,Controls Non-secure access of the interrupt with ID602" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS601 ,Controls Non-secure access of the interrupt with ID601" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS600 ,Controls Non-secure access of the interrupt with ID600" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS599 ,Controls Non-secure access of the interrupt with ID599" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS598 ,Controls Non-secure access of the interrupt with ID598" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS597 ,Controls Non-secure access of the interrupt with ID597" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS596 ,Controls Non-secure access of the interrupt with ID596" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS595 ,Controls Non-secure access of the interrupt with ID595" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS594 ,Controls Non-secure access of the interrupt with ID594" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS593 ,Controls Non-secure access of the interrupt with ID593" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS592 ,Controls Non-secure access of the interrupt with ID592" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE94++0x03
hide.long 0x00 "GICD_NSACR37,Non-secure Access Control Register 37"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE98)))
group.long 0xE98++0x03
line.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
bitfld.long 0x00 30.--31. " NS_ACCESS623 ,Controls Non-secure access of the interrupt with ID623" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS622 ,Controls Non-secure access of the interrupt with ID622" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS621 ,Controls Non-secure access of the interrupt with ID621" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS620 ,Controls Non-secure access of the interrupt with ID620" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS619 ,Controls Non-secure access of the interrupt with ID619" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS618 ,Controls Non-secure access of the interrupt with ID618" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS617 ,Controls Non-secure access of the interrupt with ID617" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS616 ,Controls Non-secure access of the interrupt with ID616" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS615 ,Controls Non-secure access of the interrupt with ID615" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS614 ,Controls Non-secure access of the interrupt with ID614" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS613 ,Controls Non-secure access of the interrupt with ID613" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS612 ,Controls Non-secure access of the interrupt with ID612" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS611 ,Controls Non-secure access of the interrupt with ID611" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS610 ,Controls Non-secure access of the interrupt with ID610" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS609 ,Controls Non-secure access of the interrupt with ID609" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS608 ,Controls Non-secure access of the interrupt with ID608" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE98++0x03
hide.long 0x00 "GICD_NSACR38,Non-secure Access Control Register 38"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xE9C)))
group.long 0xE9C++0x03
line.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
bitfld.long 0x00 30.--31. " NS_ACCESS639 ,Controls Non-secure access of the interrupt with ID639" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS638 ,Controls Non-secure access of the interrupt with ID638" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS637 ,Controls Non-secure access of the interrupt with ID637" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS636 ,Controls Non-secure access of the interrupt with ID636" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS635 ,Controls Non-secure access of the interrupt with ID635" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS634 ,Controls Non-secure access of the interrupt with ID634" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS633 ,Controls Non-secure access of the interrupt with ID633" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS632 ,Controls Non-secure access of the interrupt with ID632" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS631 ,Controls Non-secure access of the interrupt with ID631" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS630 ,Controls Non-secure access of the interrupt with ID630" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS629 ,Controls Non-secure access of the interrupt with ID629" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS628 ,Controls Non-secure access of the interrupt with ID628" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS627 ,Controls Non-secure access of the interrupt with ID627" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS626 ,Controls Non-secure access of the interrupt with ID626" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS625 ,Controls Non-secure access of the interrupt with ID625" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS624 ,Controls Non-secure access of the interrupt with ID624" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xE9C++0x03
hide.long 0x00 "GICD_NSACR39,Non-secure Access Control Register 39"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA0)))
group.long 0xEA0++0x03
line.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
bitfld.long 0x00 30.--31. " NS_ACCESS655 ,Controls Non-secure access of the interrupt with ID655" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS654 ,Controls Non-secure access of the interrupt with ID654" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS653 ,Controls Non-secure access of the interrupt with ID653" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS652 ,Controls Non-secure access of the interrupt with ID652" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS651 ,Controls Non-secure access of the interrupt with ID651" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS650 ,Controls Non-secure access of the interrupt with ID650" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS649 ,Controls Non-secure access of the interrupt with ID649" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS648 ,Controls Non-secure access of the interrupt with ID648" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS647 ,Controls Non-secure access of the interrupt with ID647" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS646 ,Controls Non-secure access of the interrupt with ID646" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS645 ,Controls Non-secure access of the interrupt with ID645" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS644 ,Controls Non-secure access of the interrupt with ID644" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS643 ,Controls Non-secure access of the interrupt with ID643" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS642 ,Controls Non-secure access of the interrupt with ID642" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS641 ,Controls Non-secure access of the interrupt with ID641" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS640 ,Controls Non-secure access of the interrupt with ID640" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA0++0x03
hide.long 0x00 "GICD_NSACR40,Non-secure Access Control Register 40"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA4)))
group.long 0xEA4++0x03
line.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
bitfld.long 0x00 30.--31. " NS_ACCESS671 ,Controls Non-secure access of the interrupt with ID671" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS670 ,Controls Non-secure access of the interrupt with ID670" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS669 ,Controls Non-secure access of the interrupt with ID669" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS668 ,Controls Non-secure access of the interrupt with ID668" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS667 ,Controls Non-secure access of the interrupt with ID667" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS666 ,Controls Non-secure access of the interrupt with ID666" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS665 ,Controls Non-secure access of the interrupt with ID665" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS664 ,Controls Non-secure access of the interrupt with ID664" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS663 ,Controls Non-secure access of the interrupt with ID663" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS662 ,Controls Non-secure access of the interrupt with ID662" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS661 ,Controls Non-secure access of the interrupt with ID661" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS660 ,Controls Non-secure access of the interrupt with ID660" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS659 ,Controls Non-secure access of the interrupt with ID659" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS658 ,Controls Non-secure access of the interrupt with ID658" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS657 ,Controls Non-secure access of the interrupt with ID657" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS656 ,Controls Non-secure access of the interrupt with ID656" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA4++0x03
hide.long 0x00 "GICD_NSACR41,Non-secure Access Control Register 41"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEA8)))
group.long 0xEA8++0x03
line.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
bitfld.long 0x00 30.--31. " NS_ACCESS687 ,Controls Non-secure access of the interrupt with ID687" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS686 ,Controls Non-secure access of the interrupt with ID686" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS685 ,Controls Non-secure access of the interrupt with ID685" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS684 ,Controls Non-secure access of the interrupt with ID684" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS683 ,Controls Non-secure access of the interrupt with ID683" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS682 ,Controls Non-secure access of the interrupt with ID682" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS681 ,Controls Non-secure access of the interrupt with ID681" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS680 ,Controls Non-secure access of the interrupt with ID680" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS679 ,Controls Non-secure access of the interrupt with ID679" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS678 ,Controls Non-secure access of the interrupt with ID678" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS677 ,Controls Non-secure access of the interrupt with ID677" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS676 ,Controls Non-secure access of the interrupt with ID676" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS675 ,Controls Non-secure access of the interrupt with ID675" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS674 ,Controls Non-secure access of the interrupt with ID674" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS673 ,Controls Non-secure access of the interrupt with ID673" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS672 ,Controls Non-secure access of the interrupt with ID672" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEA8++0x03
hide.long 0x00 "GICD_NSACR42,Non-secure Access Control Register 42"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEAC)))
group.long 0xEAC++0x03
line.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
bitfld.long 0x00 30.--31. " NS_ACCESS703 ,Controls Non-secure access of the interrupt with ID703" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS702 ,Controls Non-secure access of the interrupt with ID702" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS701 ,Controls Non-secure access of the interrupt with ID701" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS700 ,Controls Non-secure access of the interrupt with ID700" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS699 ,Controls Non-secure access of the interrupt with ID699" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS698 ,Controls Non-secure access of the interrupt with ID698" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS697 ,Controls Non-secure access of the interrupt with ID697" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS696 ,Controls Non-secure access of the interrupt with ID696" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS695 ,Controls Non-secure access of the interrupt with ID695" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS694 ,Controls Non-secure access of the interrupt with ID694" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS693 ,Controls Non-secure access of the interrupt with ID693" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS692 ,Controls Non-secure access of the interrupt with ID692" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS691 ,Controls Non-secure access of the interrupt with ID691" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS690 ,Controls Non-secure access of the interrupt with ID690" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS689 ,Controls Non-secure access of the interrupt with ID689" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS688 ,Controls Non-secure access of the interrupt with ID688" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEAC++0x03
hide.long 0x00 "GICD_NSACR43,Non-secure Access Control Register 43"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB0)))
group.long 0xEB0++0x03
line.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
bitfld.long 0x00 30.--31. " NS_ACCESS719 ,Controls Non-secure access of the interrupt with ID719" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS718 ,Controls Non-secure access of the interrupt with ID718" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS717 ,Controls Non-secure access of the interrupt with ID717" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS716 ,Controls Non-secure access of the interrupt with ID716" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS715 ,Controls Non-secure access of the interrupt with ID715" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS714 ,Controls Non-secure access of the interrupt with ID714" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS713 ,Controls Non-secure access of the interrupt with ID713" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS712 ,Controls Non-secure access of the interrupt with ID712" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS711 ,Controls Non-secure access of the interrupt with ID711" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS710 ,Controls Non-secure access of the interrupt with ID710" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS709 ,Controls Non-secure access of the interrupt with ID709" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS708 ,Controls Non-secure access of the interrupt with ID708" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS707 ,Controls Non-secure access of the interrupt with ID707" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS706 ,Controls Non-secure access of the interrupt with ID706" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS705 ,Controls Non-secure access of the interrupt with ID705" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS704 ,Controls Non-secure access of the interrupt with ID704" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB0++0x03
hide.long 0x00 "GICD_NSACR44,Non-secure Access Control Register 44"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB4)))
group.long 0xEB4++0x03
line.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
bitfld.long 0x00 30.--31. " NS_ACCESS735 ,Controls Non-secure access of the interrupt with ID735" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS734 ,Controls Non-secure access of the interrupt with ID734" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS733 ,Controls Non-secure access of the interrupt with ID733" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS732 ,Controls Non-secure access of the interrupt with ID732" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS731 ,Controls Non-secure access of the interrupt with ID731" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS730 ,Controls Non-secure access of the interrupt with ID730" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS729 ,Controls Non-secure access of the interrupt with ID729" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS728 ,Controls Non-secure access of the interrupt with ID728" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS727 ,Controls Non-secure access of the interrupt with ID727" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS726 ,Controls Non-secure access of the interrupt with ID726" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS725 ,Controls Non-secure access of the interrupt with ID725" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS724 ,Controls Non-secure access of the interrupt with ID724" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS723 ,Controls Non-secure access of the interrupt with ID723" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS722 ,Controls Non-secure access of the interrupt with ID722" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS721 ,Controls Non-secure access of the interrupt with ID721" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS720 ,Controls Non-secure access of the interrupt with ID720" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB4++0x03
hide.long 0x00 "GICD_NSACR45,Non-secure Access Control Register 45"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEB8)))
group.long 0xEB8++0x03
line.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
bitfld.long 0x00 30.--31. " NS_ACCESS751 ,Controls Non-secure access of the interrupt with ID751" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS750 ,Controls Non-secure access of the interrupt with ID750" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS749 ,Controls Non-secure access of the interrupt with ID749" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS748 ,Controls Non-secure access of the interrupt with ID748" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS747 ,Controls Non-secure access of the interrupt with ID747" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS746 ,Controls Non-secure access of the interrupt with ID746" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS745 ,Controls Non-secure access of the interrupt with ID745" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS744 ,Controls Non-secure access of the interrupt with ID744" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS743 ,Controls Non-secure access of the interrupt with ID743" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS742 ,Controls Non-secure access of the interrupt with ID742" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS741 ,Controls Non-secure access of the interrupt with ID741" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS740 ,Controls Non-secure access of the interrupt with ID740" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS739 ,Controls Non-secure access of the interrupt with ID739" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS738 ,Controls Non-secure access of the interrupt with ID738" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS737 ,Controls Non-secure access of the interrupt with ID737" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS736 ,Controls Non-secure access of the interrupt with ID736" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEB8++0x03
hide.long 0x00 "GICD_NSACR46,Non-secure Access Control Register 46"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEBC)))
group.long 0xEBC++0x03
line.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
bitfld.long 0x00 30.--31. " NS_ACCESS767 ,Controls Non-secure access of the interrupt with ID767" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS766 ,Controls Non-secure access of the interrupt with ID766" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS765 ,Controls Non-secure access of the interrupt with ID765" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS764 ,Controls Non-secure access of the interrupt with ID764" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS763 ,Controls Non-secure access of the interrupt with ID763" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS762 ,Controls Non-secure access of the interrupt with ID762" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS761 ,Controls Non-secure access of the interrupt with ID761" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS760 ,Controls Non-secure access of the interrupt with ID760" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS759 ,Controls Non-secure access of the interrupt with ID759" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS758 ,Controls Non-secure access of the interrupt with ID758" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS757 ,Controls Non-secure access of the interrupt with ID757" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS756 ,Controls Non-secure access of the interrupt with ID756" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS755 ,Controls Non-secure access of the interrupt with ID755" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS754 ,Controls Non-secure access of the interrupt with ID754" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS753 ,Controls Non-secure access of the interrupt with ID753" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS752 ,Controls Non-secure access of the interrupt with ID752" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEBC++0x03
hide.long 0x00 "GICD_NSACR47,Non-secure Access Control Register 47"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC0)))
group.long 0xEC0++0x03
line.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
bitfld.long 0x00 30.--31. " NS_ACCESS783 ,Controls Non-secure access of the interrupt with ID783" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS782 ,Controls Non-secure access of the interrupt with ID782" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS781 ,Controls Non-secure access of the interrupt with ID781" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS780 ,Controls Non-secure access of the interrupt with ID780" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS779 ,Controls Non-secure access of the interrupt with ID779" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS778 ,Controls Non-secure access of the interrupt with ID778" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS777 ,Controls Non-secure access of the interrupt with ID777" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS776 ,Controls Non-secure access of the interrupt with ID776" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS775 ,Controls Non-secure access of the interrupt with ID775" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS774 ,Controls Non-secure access of the interrupt with ID774" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS773 ,Controls Non-secure access of the interrupt with ID773" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS772 ,Controls Non-secure access of the interrupt with ID772" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS771 ,Controls Non-secure access of the interrupt with ID771" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS770 ,Controls Non-secure access of the interrupt with ID770" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS769 ,Controls Non-secure access of the interrupt with ID769" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS768 ,Controls Non-secure access of the interrupt with ID768" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC0++0x03
hide.long 0x00 "GICD_NSACR48,Non-secure Access Control Register 48"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC4)))
group.long 0xEC4++0x03
line.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
bitfld.long 0x00 30.--31. " NS_ACCESS799 ,Controls Non-secure access of the interrupt with ID799" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS798 ,Controls Non-secure access of the interrupt with ID798" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS797 ,Controls Non-secure access of the interrupt with ID797" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS796 ,Controls Non-secure access of the interrupt with ID796" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS795 ,Controls Non-secure access of the interrupt with ID795" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS794 ,Controls Non-secure access of the interrupt with ID794" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS793 ,Controls Non-secure access of the interrupt with ID793" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS792 ,Controls Non-secure access of the interrupt with ID792" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS791 ,Controls Non-secure access of the interrupt with ID791" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS790 ,Controls Non-secure access of the interrupt with ID790" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS789 ,Controls Non-secure access of the interrupt with ID789" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS788 ,Controls Non-secure access of the interrupt with ID788" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS787 ,Controls Non-secure access of the interrupt with ID787" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS786 ,Controls Non-secure access of the interrupt with ID786" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS785 ,Controls Non-secure access of the interrupt with ID785" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS784 ,Controls Non-secure access of the interrupt with ID784" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC4++0x03
hide.long 0x00 "GICD_NSACR49,Non-secure Access Control Register 49"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEC8)))
group.long 0xEC8++0x03
line.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
bitfld.long 0x00 30.--31. " NS_ACCESS815 ,Controls Non-secure access of the interrupt with ID815" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS814 ,Controls Non-secure access of the interrupt with ID814" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS813 ,Controls Non-secure access of the interrupt with ID813" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS812 ,Controls Non-secure access of the interrupt with ID812" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS811 ,Controls Non-secure access of the interrupt with ID811" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS810 ,Controls Non-secure access of the interrupt with ID810" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS809 ,Controls Non-secure access of the interrupt with ID809" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS808 ,Controls Non-secure access of the interrupt with ID808" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS807 ,Controls Non-secure access of the interrupt with ID807" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS806 ,Controls Non-secure access of the interrupt with ID806" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS805 ,Controls Non-secure access of the interrupt with ID805" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS804 ,Controls Non-secure access of the interrupt with ID804" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS803 ,Controls Non-secure access of the interrupt with ID803" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS802 ,Controls Non-secure access of the interrupt with ID802" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS801 ,Controls Non-secure access of the interrupt with ID801" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS800 ,Controls Non-secure access of the interrupt with ID800" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEC8++0x03
hide.long 0x00 "GICD_NSACR50,Non-secure Access Control Register 50"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xECC)))
group.long 0xECC++0x03
line.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
bitfld.long 0x00 30.--31. " NS_ACCESS831 ,Controls Non-secure access of the interrupt with ID831" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS830 ,Controls Non-secure access of the interrupt with ID830" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS829 ,Controls Non-secure access of the interrupt with ID829" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS828 ,Controls Non-secure access of the interrupt with ID828" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS827 ,Controls Non-secure access of the interrupt with ID827" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS826 ,Controls Non-secure access of the interrupt with ID826" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS825 ,Controls Non-secure access of the interrupt with ID825" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS824 ,Controls Non-secure access of the interrupt with ID824" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS823 ,Controls Non-secure access of the interrupt with ID823" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS822 ,Controls Non-secure access of the interrupt with ID822" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS821 ,Controls Non-secure access of the interrupt with ID821" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS820 ,Controls Non-secure access of the interrupt with ID820" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS819 ,Controls Non-secure access of the interrupt with ID819" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS818 ,Controls Non-secure access of the interrupt with ID818" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS817 ,Controls Non-secure access of the interrupt with ID817" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS816 ,Controls Non-secure access of the interrupt with ID816" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xECC++0x03
hide.long 0x00 "GICD_NSACR51,Non-secure Access Control Register 51"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED0)))
group.long 0xED0++0x03
line.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
bitfld.long 0x00 30.--31. " NS_ACCESS847 ,Controls Non-secure access of the interrupt with ID847" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS846 ,Controls Non-secure access of the interrupt with ID846" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS845 ,Controls Non-secure access of the interrupt with ID845" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS844 ,Controls Non-secure access of the interrupt with ID844" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS843 ,Controls Non-secure access of the interrupt with ID843" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS842 ,Controls Non-secure access of the interrupt with ID842" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS841 ,Controls Non-secure access of the interrupt with ID841" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS840 ,Controls Non-secure access of the interrupt with ID840" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS839 ,Controls Non-secure access of the interrupt with ID839" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS838 ,Controls Non-secure access of the interrupt with ID838" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS837 ,Controls Non-secure access of the interrupt with ID837" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS836 ,Controls Non-secure access of the interrupt with ID836" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS835 ,Controls Non-secure access of the interrupt with ID835" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS834 ,Controls Non-secure access of the interrupt with ID834" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS833 ,Controls Non-secure access of the interrupt with ID833" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS832 ,Controls Non-secure access of the interrupt with ID832" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED0++0x03
hide.long 0x00 "GICD_NSACR52,Non-secure Access Control Register 52"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED4)))
group.long 0xED4++0x03
line.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
bitfld.long 0x00 30.--31. " NS_ACCESS863 ,Controls Non-secure access of the interrupt with ID863" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS862 ,Controls Non-secure access of the interrupt with ID862" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS861 ,Controls Non-secure access of the interrupt with ID861" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS860 ,Controls Non-secure access of the interrupt with ID860" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS859 ,Controls Non-secure access of the interrupt with ID859" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS858 ,Controls Non-secure access of the interrupt with ID858" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS857 ,Controls Non-secure access of the interrupt with ID857" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS856 ,Controls Non-secure access of the interrupt with ID856" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS855 ,Controls Non-secure access of the interrupt with ID855" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS854 ,Controls Non-secure access of the interrupt with ID854" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS853 ,Controls Non-secure access of the interrupt with ID853" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS852 ,Controls Non-secure access of the interrupt with ID852" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS851 ,Controls Non-secure access of the interrupt with ID851" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS850 ,Controls Non-secure access of the interrupt with ID850" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS849 ,Controls Non-secure access of the interrupt with ID849" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS848 ,Controls Non-secure access of the interrupt with ID848" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED4++0x03
hide.long 0x00 "GICD_NSACR53,Non-secure Access Control Register 53"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xED8)))
group.long 0xED8++0x03
line.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
bitfld.long 0x00 30.--31. " NS_ACCESS879 ,Controls Non-secure access of the interrupt with ID879" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS878 ,Controls Non-secure access of the interrupt with ID878" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS877 ,Controls Non-secure access of the interrupt with ID877" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS876 ,Controls Non-secure access of the interrupt with ID876" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS875 ,Controls Non-secure access of the interrupt with ID875" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS874 ,Controls Non-secure access of the interrupt with ID874" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS873 ,Controls Non-secure access of the interrupt with ID873" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS872 ,Controls Non-secure access of the interrupt with ID872" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS871 ,Controls Non-secure access of the interrupt with ID871" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS870 ,Controls Non-secure access of the interrupt with ID870" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS869 ,Controls Non-secure access of the interrupt with ID869" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS868 ,Controls Non-secure access of the interrupt with ID868" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS867 ,Controls Non-secure access of the interrupt with ID867" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS866 ,Controls Non-secure access of the interrupt with ID866" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS865 ,Controls Non-secure access of the interrupt with ID865" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS864 ,Controls Non-secure access of the interrupt with ID864" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xED8++0x03
hide.long 0x00 "GICD_NSACR54,Non-secure Access Control Register 54"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEDC)))
group.long 0xEDC++0x03
line.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
bitfld.long 0x00 30.--31. " NS_ACCESS895 ,Controls Non-secure access of the interrupt with ID895" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS894 ,Controls Non-secure access of the interrupt with ID894" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS893 ,Controls Non-secure access of the interrupt with ID893" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS892 ,Controls Non-secure access of the interrupt with ID892" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS891 ,Controls Non-secure access of the interrupt with ID891" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS890 ,Controls Non-secure access of the interrupt with ID890" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS889 ,Controls Non-secure access of the interrupt with ID889" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS888 ,Controls Non-secure access of the interrupt with ID888" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS887 ,Controls Non-secure access of the interrupt with ID887" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS886 ,Controls Non-secure access of the interrupt with ID886" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS885 ,Controls Non-secure access of the interrupt with ID885" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS884 ,Controls Non-secure access of the interrupt with ID884" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS883 ,Controls Non-secure access of the interrupt with ID883" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS882 ,Controls Non-secure access of the interrupt with ID882" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS881 ,Controls Non-secure access of the interrupt with ID881" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS880 ,Controls Non-secure access of the interrupt with ID880" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEDC++0x03
hide.long 0x00 "GICD_NSACR55,Non-secure Access Control Register 55"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE0)))
group.long 0xEE0++0x03
line.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
bitfld.long 0x00 30.--31. " NS_ACCESS911 ,Controls Non-secure access of the interrupt with ID911" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS910 ,Controls Non-secure access of the interrupt with ID910" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS909 ,Controls Non-secure access of the interrupt with ID909" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS908 ,Controls Non-secure access of the interrupt with ID908" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS907 ,Controls Non-secure access of the interrupt with ID907" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS906 ,Controls Non-secure access of the interrupt with ID906" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS905 ,Controls Non-secure access of the interrupt with ID905" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS904 ,Controls Non-secure access of the interrupt with ID904" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS903 ,Controls Non-secure access of the interrupt with ID903" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS902 ,Controls Non-secure access of the interrupt with ID902" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS901 ,Controls Non-secure access of the interrupt with ID901" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS900 ,Controls Non-secure access of the interrupt with ID900" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS899 ,Controls Non-secure access of the interrupt with ID899" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS898 ,Controls Non-secure access of the interrupt with ID898" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS897 ,Controls Non-secure access of the interrupt with ID897" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS896 ,Controls Non-secure access of the interrupt with ID896" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE0++0x03
hide.long 0x00 "GICD_NSACR56,Non-secure Access Control Register 56"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE4)))
group.long 0xEE4++0x03
line.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
bitfld.long 0x00 30.--31. " NS_ACCESS927 ,Controls Non-secure access of the interrupt with ID927" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS926 ,Controls Non-secure access of the interrupt with ID926" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS925 ,Controls Non-secure access of the interrupt with ID925" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS924 ,Controls Non-secure access of the interrupt with ID924" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS923 ,Controls Non-secure access of the interrupt with ID923" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS922 ,Controls Non-secure access of the interrupt with ID922" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS921 ,Controls Non-secure access of the interrupt with ID921" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS920 ,Controls Non-secure access of the interrupt with ID920" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS919 ,Controls Non-secure access of the interrupt with ID919" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS918 ,Controls Non-secure access of the interrupt with ID918" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS917 ,Controls Non-secure access of the interrupt with ID917" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS916 ,Controls Non-secure access of the interrupt with ID916" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS915 ,Controls Non-secure access of the interrupt with ID915" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS914 ,Controls Non-secure access of the interrupt with ID914" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS913 ,Controls Non-secure access of the interrupt with ID913" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS912 ,Controls Non-secure access of the interrupt with ID912" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE4++0x03
hide.long 0x00 "GICD_NSACR57,Non-secure Access Control Register 57"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEE8)))
group.long 0xEE8++0x03
line.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
bitfld.long 0x00 30.--31. " NS_ACCESS943 ,Controls Non-secure access of the interrupt with ID943" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS942 ,Controls Non-secure access of the interrupt with ID942" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS941 ,Controls Non-secure access of the interrupt with ID941" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS940 ,Controls Non-secure access of the interrupt with ID940" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS939 ,Controls Non-secure access of the interrupt with ID939" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS938 ,Controls Non-secure access of the interrupt with ID938" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS937 ,Controls Non-secure access of the interrupt with ID937" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS936 ,Controls Non-secure access of the interrupt with ID936" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS935 ,Controls Non-secure access of the interrupt with ID935" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS934 ,Controls Non-secure access of the interrupt with ID934" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS933 ,Controls Non-secure access of the interrupt with ID933" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS932 ,Controls Non-secure access of the interrupt with ID932" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS931 ,Controls Non-secure access of the interrupt with ID931" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS930 ,Controls Non-secure access of the interrupt with ID930" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS929 ,Controls Non-secure access of the interrupt with ID929" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS928 ,Controls Non-secure access of the interrupt with ID928" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEE8++0x03
hide.long 0x00 "GICD_NSACR58,Non-secure Access Control Register 58"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEEC)))
group.long 0xEEC++0x03
line.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
bitfld.long 0x00 30.--31. " NS_ACCESS959 ,Controls Non-secure access of the interrupt with ID959" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS958 ,Controls Non-secure access of the interrupt with ID958" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS957 ,Controls Non-secure access of the interrupt with ID957" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS956 ,Controls Non-secure access of the interrupt with ID956" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS955 ,Controls Non-secure access of the interrupt with ID955" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS954 ,Controls Non-secure access of the interrupt with ID954" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS953 ,Controls Non-secure access of the interrupt with ID953" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS952 ,Controls Non-secure access of the interrupt with ID952" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS951 ,Controls Non-secure access of the interrupt with ID951" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS950 ,Controls Non-secure access of the interrupt with ID950" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS949 ,Controls Non-secure access of the interrupt with ID949" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS948 ,Controls Non-secure access of the interrupt with ID948" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS947 ,Controls Non-secure access of the interrupt with ID947" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS946 ,Controls Non-secure access of the interrupt with ID946" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS945 ,Controls Non-secure access of the interrupt with ID945" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS944 ,Controls Non-secure access of the interrupt with ID944" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEEC++0x03
hide.long 0x00 "GICD_NSACR59,Non-secure Access Control Register 59"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF0)))
group.long 0xEF0++0x03
line.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
bitfld.long 0x00 30.--31. " NS_ACCESS975 ,Controls Non-secure access of the interrupt with ID975" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS974 ,Controls Non-secure access of the interrupt with ID974" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS973 ,Controls Non-secure access of the interrupt with ID973" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS972 ,Controls Non-secure access of the interrupt with ID972" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS971 ,Controls Non-secure access of the interrupt with ID971" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS970 ,Controls Non-secure access of the interrupt with ID970" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS969 ,Controls Non-secure access of the interrupt with ID969" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS968 ,Controls Non-secure access of the interrupt with ID968" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS967 ,Controls Non-secure access of the interrupt with ID967" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS966 ,Controls Non-secure access of the interrupt with ID966" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS965 ,Controls Non-secure access of the interrupt with ID965" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS964 ,Controls Non-secure access of the interrupt with ID964" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS963 ,Controls Non-secure access of the interrupt with ID963" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS962 ,Controls Non-secure access of the interrupt with ID962" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS961 ,Controls Non-secure access of the interrupt with ID961" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS960 ,Controls Non-secure access of the interrupt with ID960" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEF0++0x03
hide.long 0x00 "GICD_NSACR60,Non-secure Access Control Register 60"
endif
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.)+0xEF4)))
group.long 0xEF4++0x03
line.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
bitfld.long 0x00 30.--31. " NS_ACCESS991 ,Controls Non-secure access of the interrupt with ID991" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 28.--29. " NS_ACCESS990 ,Controls Non-secure access of the interrupt with ID990" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 26.--27. " NS_ACCESS989 ,Controls Non-secure access of the interrupt with ID989" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 24.--25. " NS_ACCESS988 ,Controls Non-secure access of the interrupt with ID988" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 22.--23. " NS_ACCESS987 ,Controls Non-secure access of the interrupt with ID987" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 20.--21. " NS_ACCESS986 ,Controls Non-secure access of the interrupt with ID986" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 18.--19. " NS_ACCESS985 ,Controls Non-secure access of the interrupt with ID985" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 16.--17. " NS_ACCESS984 ,Controls Non-secure access of the interrupt with ID984" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 14.--15. " NS_ACCESS983 ,Controls Non-secure access of the interrupt with ID983" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 12.--13. " NS_ACCESS982 ,Controls Non-secure access of the interrupt with ID982" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 10.--11. " NS_ACCESS981 ,Controls Non-secure access of the interrupt with ID981" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 8.--9. " NS_ACCESS980 ,Controls Non-secure access of the interrupt with ID980" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 6.--7. " NS_ACCESS979 ,Controls Non-secure access of the interrupt with ID979" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 4.--5. " NS_ACCESS978 ,Controls Non-secure access of the interrupt with ID978" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 2.--3. " NS_ACCESS977 ,Controls Non-secure access of the interrupt with ID977" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
textline "                       "
bitfld.long 0x00 0.--1. " NS_ACCESS976 ,Controls Non-secure access of the interrupt with ID976" "No access,SET_CLR_PENDR/SETSPI_NSR/SGIR,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER,SET_CLR_PENDR/SETSPI_NSR/SGIR/CLRSPI_NSR/SET_CLR_ACTIVER/ITARGETSR/IROUTER"
else
hgroup.long 0xEF4++0x03
hide.long 0x00 "GICD_NSACR61,Non-secure Access Control Register 61"
endif
tree.end
width 25.
tree "Software Generated Interrupt"
if (((per.l(COMP.BASE("GICD",-1.)))&0x10)==0x10)
hgroup.long 0x0F00++0x03
hide.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
hgroup.long 0xF10++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
hgroup.long 0xF14++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
hgroup.long 0xF18++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
hgroup.long 0xF1C++0x03
hide.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
hgroup.long 0xF20++0x03
hide.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
hgroup.long 0xF24++0x03
hide.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
hgroup.long 0xF28++0x03
hide.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
hgroup.long 0xF2C++0x03
hide.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
else
wgroup.long 0x0F00++0x03
line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register"
group.long 0xF10++0x03
line.long 0x00 "GICD_CLR_PENDSGIR0,SGI Clear Pending Register 0"
group.long 0xF14++0x03
line.long 0x00 "GICD_CLR_PENDSGIR1,SGI Clear Pending Register 1"
group.long 0xF18++0x03
line.long 0x00 "GICD_CLR_PENDSGIR2,SGI Clear Pending Register 2"
group.long 0xF1C++0x03
line.long 0x00 "GICD_CLR_PENDSGIR3,SGI Clear Pending Register 3"
group.long 0xF20++0x03
line.long 0x00 "GICD_SET_PENDSGIR0,SGI Set Pending Register 0"
group.long 0xF24++0x03
line.long 0x00 "GICD_SET_PENDSGIR1,SGI Set Pending Register 1"
group.long 0xF28++0x03
line.long 0x00 "GICD_SET_PENDSGIR2,SGI Set Pending Register 2"
group.long 0xF2C++0x03
line.long 0x00 "GICD_SET_PENDSGIR3,SGI Set Pending Register 3"
endif
tree.end
width 24.
tree "Interrupt Routing Registers"
group.quad 0x6100++0x07
line.quad 0x00 "GICD_IROUTER32 ,Interrupt Routing Register 32 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6108++0x07
line.quad 0x00 "GICD_IROUTER33 ,Interrupt Routing Register 33 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6110++0x07
line.quad 0x00 "GICD_IROUTER34 ,Interrupt Routing Register 34 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6118++0x07
line.quad 0x00 "GICD_IROUTER35 ,Interrupt Routing Register 35 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6120++0x07
line.quad 0x00 "GICD_IROUTER36 ,Interrupt Routing Register 36 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6128++0x07
line.quad 0x00 "GICD_IROUTER37 ,Interrupt Routing Register 37 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6130++0x07
line.quad 0x00 "GICD_IROUTER38 ,Interrupt Routing Register 38 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6138++0x07
line.quad 0x00 "GICD_IROUTER39 ,Interrupt Routing Register 39 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6140++0x07
line.quad 0x00 "GICD_IROUTER40 ,Interrupt Routing Register 40 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6148++0x07
line.quad 0x00 "GICD_IROUTER41 ,Interrupt Routing Register 41 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6150++0x07
line.quad 0x00 "GICD_IROUTER42 ,Interrupt Routing Register 42 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6158++0x07
line.quad 0x00 "GICD_IROUTER43 ,Interrupt Routing Register 43 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6160++0x07
line.quad 0x00 "GICD_IROUTER44 ,Interrupt Routing Register 44 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6168++0x07
line.quad 0x00 "GICD_IROUTER45 ,Interrupt Routing Register 45 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6170++0x07
line.quad 0x00 "GICD_IROUTER46 ,Interrupt Routing Register 46 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6178++0x07
line.quad 0x00 "GICD_IROUTER47 ,Interrupt Routing Register 47 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6180++0x07
line.quad 0x00 "GICD_IROUTER48 ,Interrupt Routing Register 48 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6188++0x07
line.quad 0x00 "GICD_IROUTER49 ,Interrupt Routing Register 49 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6190++0x07
line.quad 0x00 "GICD_IROUTER50 ,Interrupt Routing Register 50 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6198++0x07
line.quad 0x00 "GICD_IROUTER51 ,Interrupt Routing Register 51 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61A0++0x07
line.quad 0x00 "GICD_IROUTER52 ,Interrupt Routing Register 52 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61A8++0x07
line.quad 0x00 "GICD_IROUTER53 ,Interrupt Routing Register 53 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61B0++0x07
line.quad 0x00 "GICD_IROUTER54 ,Interrupt Routing Register 54 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61B8++0x07
line.quad 0x00 "GICD_IROUTER55 ,Interrupt Routing Register 55 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61C0++0x07
line.quad 0x00 "GICD_IROUTER56 ,Interrupt Routing Register 56 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61C8++0x07
line.quad 0x00 "GICD_IROUTER57 ,Interrupt Routing Register 57 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61D0++0x07
line.quad 0x00 "GICD_IROUTER58 ,Interrupt Routing Register 58 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61D8++0x07
line.quad 0x00 "GICD_IROUTER59 ,Interrupt Routing Register 59 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61E0++0x07
line.quad 0x00 "GICD_IROUTER60 ,Interrupt Routing Register 60 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61E8++0x07
line.quad 0x00 "GICD_IROUTER61 ,Interrupt Routing Register 61 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61F0++0x07
line.quad 0x00 "GICD_IROUTER62 ,Interrupt Routing Register 62 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x61F8++0x07
line.quad 0x00 "GICD_IROUTER63 ,Interrupt Routing Register 63 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6200++0x07
line.quad 0x00 "GICD_IROUTER64 ,Interrupt Routing Register 64 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6208++0x07
line.quad 0x00 "GICD_IROUTER65 ,Interrupt Routing Register 65 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6210++0x07
line.quad 0x00 "GICD_IROUTER66 ,Interrupt Routing Register 66 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6218++0x07
line.quad 0x00 "GICD_IROUTER67 ,Interrupt Routing Register 67 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6220++0x07
line.quad 0x00 "GICD_IROUTER68 ,Interrupt Routing Register 68 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6228++0x07
line.quad 0x00 "GICD_IROUTER69 ,Interrupt Routing Register 69 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6230++0x07
line.quad 0x00 "GICD_IROUTER70 ,Interrupt Routing Register 70 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6238++0x07
line.quad 0x00 "GICD_IROUTER71 ,Interrupt Routing Register 71 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6240++0x07
line.quad 0x00 "GICD_IROUTER72 ,Interrupt Routing Register 72 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6248++0x07
line.quad 0x00 "GICD_IROUTER73 ,Interrupt Routing Register 73 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6250++0x07
line.quad 0x00 "GICD_IROUTER74 ,Interrupt Routing Register 74 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6258++0x07
line.quad 0x00 "GICD_IROUTER75 ,Interrupt Routing Register 75 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6260++0x07
line.quad 0x00 "GICD_IROUTER76 ,Interrupt Routing Register 76 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6268++0x07
line.quad 0x00 "GICD_IROUTER77 ,Interrupt Routing Register 77 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6270++0x07
line.quad 0x00 "GICD_IROUTER78 ,Interrupt Routing Register 78 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6278++0x07
line.quad 0x00 "GICD_IROUTER79 ,Interrupt Routing Register 79 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6280++0x07
line.quad 0x00 "GICD_IROUTER80 ,Interrupt Routing Register 80 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6288++0x07
line.quad 0x00 "GICD_IROUTER81 ,Interrupt Routing Register 81 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6290++0x07
line.quad 0x00 "GICD_IROUTER82 ,Interrupt Routing Register 82 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6298++0x07
line.quad 0x00 "GICD_IROUTER83 ,Interrupt Routing Register 83 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62A0++0x07
line.quad 0x00 "GICD_IROUTER84 ,Interrupt Routing Register 84 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62A8++0x07
line.quad 0x00 "GICD_IROUTER85 ,Interrupt Routing Register 85 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62B0++0x07
line.quad 0x00 "GICD_IROUTER86 ,Interrupt Routing Register 86 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62B8++0x07
line.quad 0x00 "GICD_IROUTER87 ,Interrupt Routing Register 87 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62C0++0x07
line.quad 0x00 "GICD_IROUTER88 ,Interrupt Routing Register 88 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62C8++0x07
line.quad 0x00 "GICD_IROUTER89 ,Interrupt Routing Register 89 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62D0++0x07
line.quad 0x00 "GICD_IROUTER90 ,Interrupt Routing Register 90 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62D8++0x07
line.quad 0x00 "GICD_IROUTER91 ,Interrupt Routing Register 91 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62E0++0x07
line.quad 0x00 "GICD_IROUTER92 ,Interrupt Routing Register 92 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62E8++0x07
line.quad 0x00 "GICD_IROUTER93 ,Interrupt Routing Register 93 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62F0++0x07
line.quad 0x00 "GICD_IROUTER94 ,Interrupt Routing Register 94 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x62F8++0x07
line.quad 0x00 "GICD_IROUTER95 ,Interrupt Routing Register 95 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6300++0x07
line.quad 0x00 "GICD_IROUTER96 ,Interrupt Routing Register 96 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6308++0x07
line.quad 0x00 "GICD_IROUTER97 ,Interrupt Routing Register 97 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6310++0x07
line.quad 0x00 "GICD_IROUTER98 ,Interrupt Routing Register 98 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6318++0x07
line.quad 0x00 "GICD_IROUTER99 ,Interrupt Routing Register 99 "
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6320++0x07
line.quad 0x00 "GICD_IROUTER100,Interrupt Routing Register 100"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6328++0x07
line.quad 0x00 "GICD_IROUTER101,Interrupt Routing Register 101"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6330++0x07
line.quad 0x00 "GICD_IROUTER102,Interrupt Routing Register 102"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6338++0x07
line.quad 0x00 "GICD_IROUTER103,Interrupt Routing Register 103"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6340++0x07
line.quad 0x00 "GICD_IROUTER104,Interrupt Routing Register 104"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6348++0x07
line.quad 0x00 "GICD_IROUTER105,Interrupt Routing Register 105"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6350++0x07
line.quad 0x00 "GICD_IROUTER106,Interrupt Routing Register 106"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6358++0x07
line.quad 0x00 "GICD_IROUTER107,Interrupt Routing Register 107"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6360++0x07
line.quad 0x00 "GICD_IROUTER108,Interrupt Routing Register 108"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6368++0x07
line.quad 0x00 "GICD_IROUTER109,Interrupt Routing Register 109"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6370++0x07
line.quad 0x00 "GICD_IROUTER110,Interrupt Routing Register 110"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6378++0x07
line.quad 0x00 "GICD_IROUTER111,Interrupt Routing Register 111"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6380++0x07
line.quad 0x00 "GICD_IROUTER112,Interrupt Routing Register 112"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6388++0x07
line.quad 0x00 "GICD_IROUTER113,Interrupt Routing Register 113"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6390++0x07
line.quad 0x00 "GICD_IROUTER114,Interrupt Routing Register 114"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6398++0x07
line.quad 0x00 "GICD_IROUTER115,Interrupt Routing Register 115"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63A0++0x07
line.quad 0x00 "GICD_IROUTER116,Interrupt Routing Register 116"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63A8++0x07
line.quad 0x00 "GICD_IROUTER117,Interrupt Routing Register 117"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63B0++0x07
line.quad 0x00 "GICD_IROUTER118,Interrupt Routing Register 118"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63B8++0x07
line.quad 0x00 "GICD_IROUTER119,Interrupt Routing Register 119"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63C0++0x07
line.quad 0x00 "GICD_IROUTER120,Interrupt Routing Register 120"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63C8++0x07
line.quad 0x00 "GICD_IROUTER121,Interrupt Routing Register 121"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63D0++0x07
line.quad 0x00 "GICD_IROUTER122,Interrupt Routing Register 122"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63D8++0x07
line.quad 0x00 "GICD_IROUTER123,Interrupt Routing Register 123"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63E0++0x07
line.quad 0x00 "GICD_IROUTER124,Interrupt Routing Register 124"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63E8++0x07
line.quad 0x00 "GICD_IROUTER125,Interrupt Routing Register 125"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63F0++0x07
line.quad 0x00 "GICD_IROUTER126,Interrupt Routing Register 126"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x63F8++0x07
line.quad 0x00 "GICD_IROUTER127,Interrupt Routing Register 127"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6400++0x07
line.quad 0x00 "GICD_IROUTER128,Interrupt Routing Register 128"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6408++0x07
line.quad 0x00 "GICD_IROUTER129,Interrupt Routing Register 129"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6410++0x07
line.quad 0x00 "GICD_IROUTER130,Interrupt Routing Register 130"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6418++0x07
line.quad 0x00 "GICD_IROUTER131,Interrupt Routing Register 131"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6420++0x07
line.quad 0x00 "GICD_IROUTER132,Interrupt Routing Register 132"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6428++0x07
line.quad 0x00 "GICD_IROUTER133,Interrupt Routing Register 133"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6430++0x07
line.quad 0x00 "GICD_IROUTER134,Interrupt Routing Register 134"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6438++0x07
line.quad 0x00 "GICD_IROUTER135,Interrupt Routing Register 135"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6440++0x07
line.quad 0x00 "GICD_IROUTER136,Interrupt Routing Register 136"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6448++0x07
line.quad 0x00 "GICD_IROUTER137,Interrupt Routing Register 137"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6450++0x07
line.quad 0x00 "GICD_IROUTER138,Interrupt Routing Register 138"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6458++0x07
line.quad 0x00 "GICD_IROUTER139,Interrupt Routing Register 139"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6460++0x07
line.quad 0x00 "GICD_IROUTER140,Interrupt Routing Register 140"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6468++0x07
line.quad 0x00 "GICD_IROUTER141,Interrupt Routing Register 141"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6470++0x07
line.quad 0x00 "GICD_IROUTER142,Interrupt Routing Register 142"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6478++0x07
line.quad 0x00 "GICD_IROUTER143,Interrupt Routing Register 143"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6480++0x07
line.quad 0x00 "GICD_IROUTER144,Interrupt Routing Register 144"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6488++0x07
line.quad 0x00 "GICD_IROUTER145,Interrupt Routing Register 145"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6490++0x07
line.quad 0x00 "GICD_IROUTER146,Interrupt Routing Register 146"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6498++0x07
line.quad 0x00 "GICD_IROUTER147,Interrupt Routing Register 147"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64A0++0x07
line.quad 0x00 "GICD_IROUTER148,Interrupt Routing Register 148"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64A8++0x07
line.quad 0x00 "GICD_IROUTER149,Interrupt Routing Register 149"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64B0++0x07
line.quad 0x00 "GICD_IROUTER150,Interrupt Routing Register 150"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64B8++0x07
line.quad 0x00 "GICD_IROUTER151,Interrupt Routing Register 151"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64C0++0x07
line.quad 0x00 "GICD_IROUTER152,Interrupt Routing Register 152"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64C8++0x07
line.quad 0x00 "GICD_IROUTER153,Interrupt Routing Register 153"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64D0++0x07
line.quad 0x00 "GICD_IROUTER154,Interrupt Routing Register 154"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64D8++0x07
line.quad 0x00 "GICD_IROUTER155,Interrupt Routing Register 155"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64E0++0x07
line.quad 0x00 "GICD_IROUTER156,Interrupt Routing Register 156"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64E8++0x07
line.quad 0x00 "GICD_IROUTER157,Interrupt Routing Register 157"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64F0++0x07
line.quad 0x00 "GICD_IROUTER158,Interrupt Routing Register 158"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x64F8++0x07
line.quad 0x00 "GICD_IROUTER159,Interrupt Routing Register 159"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6500++0x07
line.quad 0x00 "GICD_IROUTER160,Interrupt Routing Register 160"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6508++0x07
line.quad 0x00 "GICD_IROUTER161,Interrupt Routing Register 161"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6510++0x07
line.quad 0x00 "GICD_IROUTER162,Interrupt Routing Register 162"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6518++0x07
line.quad 0x00 "GICD_IROUTER163,Interrupt Routing Register 163"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6520++0x07
line.quad 0x00 "GICD_IROUTER164,Interrupt Routing Register 164"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6528++0x07
line.quad 0x00 "GICD_IROUTER165,Interrupt Routing Register 165"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6530++0x07
line.quad 0x00 "GICD_IROUTER166,Interrupt Routing Register 166"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6538++0x07
line.quad 0x00 "GICD_IROUTER167,Interrupt Routing Register 167"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6540++0x07
line.quad 0x00 "GICD_IROUTER168,Interrupt Routing Register 168"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6548++0x07
line.quad 0x00 "GICD_IROUTER169,Interrupt Routing Register 169"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6550++0x07
line.quad 0x00 "GICD_IROUTER170,Interrupt Routing Register 170"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6558++0x07
line.quad 0x00 "GICD_IROUTER171,Interrupt Routing Register 171"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6560++0x07
line.quad 0x00 "GICD_IROUTER172,Interrupt Routing Register 172"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6568++0x07
line.quad 0x00 "GICD_IROUTER173,Interrupt Routing Register 173"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6570++0x07
line.quad 0x00 "GICD_IROUTER174,Interrupt Routing Register 174"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6578++0x07
line.quad 0x00 "GICD_IROUTER175,Interrupt Routing Register 175"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6580++0x07
line.quad 0x00 "GICD_IROUTER176,Interrupt Routing Register 176"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6588++0x07
line.quad 0x00 "GICD_IROUTER177,Interrupt Routing Register 177"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6590++0x07
line.quad 0x00 "GICD_IROUTER178,Interrupt Routing Register 178"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6598++0x07
line.quad 0x00 "GICD_IROUTER179,Interrupt Routing Register 179"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65A0++0x07
line.quad 0x00 "GICD_IROUTER180,Interrupt Routing Register 180"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65A8++0x07
line.quad 0x00 "GICD_IROUTER181,Interrupt Routing Register 181"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65B0++0x07
line.quad 0x00 "GICD_IROUTER182,Interrupt Routing Register 182"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65B8++0x07
line.quad 0x00 "GICD_IROUTER183,Interrupt Routing Register 183"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65C0++0x07
line.quad 0x00 "GICD_IROUTER184,Interrupt Routing Register 184"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65C8++0x07
line.quad 0x00 "GICD_IROUTER185,Interrupt Routing Register 185"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65D0++0x07
line.quad 0x00 "GICD_IROUTER186,Interrupt Routing Register 186"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65D8++0x07
line.quad 0x00 "GICD_IROUTER187,Interrupt Routing Register 187"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65E0++0x07
line.quad 0x00 "GICD_IROUTER188,Interrupt Routing Register 188"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65E8++0x07
line.quad 0x00 "GICD_IROUTER189,Interrupt Routing Register 189"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65F0++0x07
line.quad 0x00 "GICD_IROUTER190,Interrupt Routing Register 190"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x65F8++0x07
line.quad 0x00 "GICD_IROUTER191,Interrupt Routing Register 191"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6600++0x07
line.quad 0x00 "GICD_IROUTER192,Interrupt Routing Register 192"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6608++0x07
line.quad 0x00 "GICD_IROUTER193,Interrupt Routing Register 193"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6610++0x07
line.quad 0x00 "GICD_IROUTER194,Interrupt Routing Register 194"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6618++0x07
line.quad 0x00 "GICD_IROUTER195,Interrupt Routing Register 195"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6620++0x07
line.quad 0x00 "GICD_IROUTER196,Interrupt Routing Register 196"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6628++0x07
line.quad 0x00 "GICD_IROUTER197,Interrupt Routing Register 197"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6630++0x07
line.quad 0x00 "GICD_IROUTER198,Interrupt Routing Register 198"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6638++0x07
line.quad 0x00 "GICD_IROUTER199,Interrupt Routing Register 199"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6640++0x07
line.quad 0x00 "GICD_IROUTER200,Interrupt Routing Register 200"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6648++0x07
line.quad 0x00 "GICD_IROUTER201,Interrupt Routing Register 201"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6650++0x07
line.quad 0x00 "GICD_IROUTER202,Interrupt Routing Register 202"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6658++0x07
line.quad 0x00 "GICD_IROUTER203,Interrupt Routing Register 203"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6660++0x07
line.quad 0x00 "GICD_IROUTER204,Interrupt Routing Register 204"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6668++0x07
line.quad 0x00 "GICD_IROUTER205,Interrupt Routing Register 205"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6670++0x07
line.quad 0x00 "GICD_IROUTER206,Interrupt Routing Register 206"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6678++0x07
line.quad 0x00 "GICD_IROUTER207,Interrupt Routing Register 207"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6680++0x07
line.quad 0x00 "GICD_IROUTER208,Interrupt Routing Register 208"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6688++0x07
line.quad 0x00 "GICD_IROUTER209,Interrupt Routing Register 209"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6690++0x07
line.quad 0x00 "GICD_IROUTER210,Interrupt Routing Register 210"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6698++0x07
line.quad 0x00 "GICD_IROUTER211,Interrupt Routing Register 211"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66A0++0x07
line.quad 0x00 "GICD_IROUTER212,Interrupt Routing Register 212"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66A8++0x07
line.quad 0x00 "GICD_IROUTER213,Interrupt Routing Register 213"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66B0++0x07
line.quad 0x00 "GICD_IROUTER214,Interrupt Routing Register 214"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66B8++0x07
line.quad 0x00 "GICD_IROUTER215,Interrupt Routing Register 215"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66C0++0x07
line.quad 0x00 "GICD_IROUTER216,Interrupt Routing Register 216"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66C8++0x07
line.quad 0x00 "GICD_IROUTER217,Interrupt Routing Register 217"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66D0++0x07
line.quad 0x00 "GICD_IROUTER218,Interrupt Routing Register 218"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66D8++0x07
line.quad 0x00 "GICD_IROUTER219,Interrupt Routing Register 219"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66E0++0x07
line.quad 0x00 "GICD_IROUTER220,Interrupt Routing Register 220"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66E8++0x07
line.quad 0x00 "GICD_IROUTER221,Interrupt Routing Register 221"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66F0++0x07
line.quad 0x00 "GICD_IROUTER222,Interrupt Routing Register 222"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x66F8++0x07
line.quad 0x00 "GICD_IROUTER223,Interrupt Routing Register 223"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6700++0x07
line.quad 0x00 "GICD_IROUTER224,Interrupt Routing Register 224"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6708++0x07
line.quad 0x00 "GICD_IROUTER225,Interrupt Routing Register 225"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6710++0x07
line.quad 0x00 "GICD_IROUTER226,Interrupt Routing Register 226"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6718++0x07
line.quad 0x00 "GICD_IROUTER227,Interrupt Routing Register 227"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6720++0x07
line.quad 0x00 "GICD_IROUTER228,Interrupt Routing Register 228"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6728++0x07
line.quad 0x00 "GICD_IROUTER229,Interrupt Routing Register 229"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6730++0x07
line.quad 0x00 "GICD_IROUTER230,Interrupt Routing Register 230"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6738++0x07
line.quad 0x00 "GICD_IROUTER231,Interrupt Routing Register 231"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6740++0x07
line.quad 0x00 "GICD_IROUTER232,Interrupt Routing Register 232"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6748++0x07
line.quad 0x00 "GICD_IROUTER233,Interrupt Routing Register 233"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6750++0x07
line.quad 0x00 "GICD_IROUTER234,Interrupt Routing Register 234"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6758++0x07
line.quad 0x00 "GICD_IROUTER235,Interrupt Routing Register 235"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6760++0x07
line.quad 0x00 "GICD_IROUTER236,Interrupt Routing Register 236"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6768++0x07
line.quad 0x00 "GICD_IROUTER237,Interrupt Routing Register 237"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6770++0x07
line.quad 0x00 "GICD_IROUTER238,Interrupt Routing Register 238"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6778++0x07
line.quad 0x00 "GICD_IROUTER239,Interrupt Routing Register 239"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6780++0x07
line.quad 0x00 "GICD_IROUTER240,Interrupt Routing Register 240"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6788++0x07
line.quad 0x00 "GICD_IROUTER241,Interrupt Routing Register 241"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6790++0x07
line.quad 0x00 "GICD_IROUTER242,Interrupt Routing Register 242"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6798++0x07
line.quad 0x00 "GICD_IROUTER243,Interrupt Routing Register 243"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67A0++0x07
line.quad 0x00 "GICD_IROUTER244,Interrupt Routing Register 244"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67A8++0x07
line.quad 0x00 "GICD_IROUTER245,Interrupt Routing Register 245"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67B0++0x07
line.quad 0x00 "GICD_IROUTER246,Interrupt Routing Register 246"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67B8++0x07
line.quad 0x00 "GICD_IROUTER247,Interrupt Routing Register 247"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67C0++0x07
line.quad 0x00 "GICD_IROUTER248,Interrupt Routing Register 248"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67C8++0x07
line.quad 0x00 "GICD_IROUTER249,Interrupt Routing Register 249"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67D0++0x07
line.quad 0x00 "GICD_IROUTER250,Interrupt Routing Register 250"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67D8++0x07
line.quad 0x00 "GICD_IROUTER251,Interrupt Routing Register 251"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67E0++0x07
line.quad 0x00 "GICD_IROUTER252,Interrupt Routing Register 252"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67E8++0x07
line.quad 0x00 "GICD_IROUTER253,Interrupt Routing Register 253"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67F0++0x07
line.quad 0x00 "GICD_IROUTER254,Interrupt Routing Register 254"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x67F8++0x07
line.quad 0x00 "GICD_IROUTER255,Interrupt Routing Register 255"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6800++0x07
line.quad 0x00 "GICD_IROUTER256,Interrupt Routing Register 256"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6808++0x07
line.quad 0x00 "GICD_IROUTER257,Interrupt Routing Register 257"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6810++0x07
line.quad 0x00 "GICD_IROUTER258,Interrupt Routing Register 258"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6818++0x07
line.quad 0x00 "GICD_IROUTER259,Interrupt Routing Register 259"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6820++0x07
line.quad 0x00 "GICD_IROUTER260,Interrupt Routing Register 260"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6828++0x07
line.quad 0x00 "GICD_IROUTER261,Interrupt Routing Register 261"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6830++0x07
line.quad 0x00 "GICD_IROUTER262,Interrupt Routing Register 262"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6838++0x07
line.quad 0x00 "GICD_IROUTER263,Interrupt Routing Register 263"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6840++0x07
line.quad 0x00 "GICD_IROUTER264,Interrupt Routing Register 264"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6848++0x07
line.quad 0x00 "GICD_IROUTER265,Interrupt Routing Register 265"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6850++0x07
line.quad 0x00 "GICD_IROUTER266,Interrupt Routing Register 266"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6858++0x07
line.quad 0x00 "GICD_IROUTER267,Interrupt Routing Register 267"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6860++0x07
line.quad 0x00 "GICD_IROUTER268,Interrupt Routing Register 268"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6868++0x07
line.quad 0x00 "GICD_IROUTER269,Interrupt Routing Register 269"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6870++0x07
line.quad 0x00 "GICD_IROUTER270,Interrupt Routing Register 270"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6878++0x07
line.quad 0x00 "GICD_IROUTER271,Interrupt Routing Register 271"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6880++0x07
line.quad 0x00 "GICD_IROUTER272,Interrupt Routing Register 272"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6888++0x07
line.quad 0x00 "GICD_IROUTER273,Interrupt Routing Register 273"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6890++0x07
line.quad 0x00 "GICD_IROUTER274,Interrupt Routing Register 274"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6898++0x07
line.quad 0x00 "GICD_IROUTER275,Interrupt Routing Register 275"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68A0++0x07
line.quad 0x00 "GICD_IROUTER276,Interrupt Routing Register 276"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68A8++0x07
line.quad 0x00 "GICD_IROUTER277,Interrupt Routing Register 277"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68B0++0x07
line.quad 0x00 "GICD_IROUTER278,Interrupt Routing Register 278"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68B8++0x07
line.quad 0x00 "GICD_IROUTER279,Interrupt Routing Register 279"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68C0++0x07
line.quad 0x00 "GICD_IROUTER280,Interrupt Routing Register 280"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68C8++0x07
line.quad 0x00 "GICD_IROUTER281,Interrupt Routing Register 281"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68D0++0x07
line.quad 0x00 "GICD_IROUTER282,Interrupt Routing Register 282"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68D8++0x07
line.quad 0x00 "GICD_IROUTER283,Interrupt Routing Register 283"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68E0++0x07
line.quad 0x00 "GICD_IROUTER284,Interrupt Routing Register 284"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68E8++0x07
line.quad 0x00 "GICD_IROUTER285,Interrupt Routing Register 285"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68F0++0x07
line.quad 0x00 "GICD_IROUTER286,Interrupt Routing Register 286"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x68F8++0x07
line.quad 0x00 "GICD_IROUTER287,Interrupt Routing Register 287"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6900++0x07
line.quad 0x00 "GICD_IROUTER288,Interrupt Routing Register 288"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6908++0x07
line.quad 0x00 "GICD_IROUTER289,Interrupt Routing Register 289"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6910++0x07
line.quad 0x00 "GICD_IROUTER290,Interrupt Routing Register 290"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6918++0x07
line.quad 0x00 "GICD_IROUTER291,Interrupt Routing Register 291"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6920++0x07
line.quad 0x00 "GICD_IROUTER292,Interrupt Routing Register 292"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6928++0x07
line.quad 0x00 "GICD_IROUTER293,Interrupt Routing Register 293"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6930++0x07
line.quad 0x00 "GICD_IROUTER294,Interrupt Routing Register 294"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6938++0x07
line.quad 0x00 "GICD_IROUTER295,Interrupt Routing Register 295"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6940++0x07
line.quad 0x00 "GICD_IROUTER296,Interrupt Routing Register 296"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6948++0x07
line.quad 0x00 "GICD_IROUTER297,Interrupt Routing Register 297"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6950++0x07
line.quad 0x00 "GICD_IROUTER298,Interrupt Routing Register 298"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6958++0x07
line.quad 0x00 "GICD_IROUTER299,Interrupt Routing Register 299"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6960++0x07
line.quad 0x00 "GICD_IROUTER300,Interrupt Routing Register 300"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6968++0x07
line.quad 0x00 "GICD_IROUTER301,Interrupt Routing Register 301"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6970++0x07
line.quad 0x00 "GICD_IROUTER302,Interrupt Routing Register 302"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6978++0x07
line.quad 0x00 "GICD_IROUTER303,Interrupt Routing Register 303"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6980++0x07
line.quad 0x00 "GICD_IROUTER304,Interrupt Routing Register 304"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6988++0x07
line.quad 0x00 "GICD_IROUTER305,Interrupt Routing Register 305"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6990++0x07
line.quad 0x00 "GICD_IROUTER306,Interrupt Routing Register 306"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6998++0x07
line.quad 0x00 "GICD_IROUTER307,Interrupt Routing Register 307"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69A0++0x07
line.quad 0x00 "GICD_IROUTER308,Interrupt Routing Register 308"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69A8++0x07
line.quad 0x00 "GICD_IROUTER309,Interrupt Routing Register 309"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69B0++0x07
line.quad 0x00 "GICD_IROUTER310,Interrupt Routing Register 310"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69B8++0x07
line.quad 0x00 "GICD_IROUTER311,Interrupt Routing Register 311"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69C0++0x07
line.quad 0x00 "GICD_IROUTER312,Interrupt Routing Register 312"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69C8++0x07
line.quad 0x00 "GICD_IROUTER313,Interrupt Routing Register 313"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69D0++0x07
line.quad 0x00 "GICD_IROUTER314,Interrupt Routing Register 314"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69D8++0x07
line.quad 0x00 "GICD_IROUTER315,Interrupt Routing Register 315"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69E0++0x07
line.quad 0x00 "GICD_IROUTER316,Interrupt Routing Register 316"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69E8++0x07
line.quad 0x00 "GICD_IROUTER317,Interrupt Routing Register 317"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69F0++0x07
line.quad 0x00 "GICD_IROUTER318,Interrupt Routing Register 318"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x69F8++0x07
line.quad 0x00 "GICD_IROUTER319,Interrupt Routing Register 319"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A00++0x07
line.quad 0x00 "GICD_IROUTER320,Interrupt Routing Register 320"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A08++0x07
line.quad 0x00 "GICD_IROUTER321,Interrupt Routing Register 321"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A10++0x07
line.quad 0x00 "GICD_IROUTER322,Interrupt Routing Register 322"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A18++0x07
line.quad 0x00 "GICD_IROUTER323,Interrupt Routing Register 323"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A20++0x07
line.quad 0x00 "GICD_IROUTER324,Interrupt Routing Register 324"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A28++0x07
line.quad 0x00 "GICD_IROUTER325,Interrupt Routing Register 325"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A30++0x07
line.quad 0x00 "GICD_IROUTER326,Interrupt Routing Register 326"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A38++0x07
line.quad 0x00 "GICD_IROUTER327,Interrupt Routing Register 327"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A40++0x07
line.quad 0x00 "GICD_IROUTER328,Interrupt Routing Register 328"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A48++0x07
line.quad 0x00 "GICD_IROUTER329,Interrupt Routing Register 329"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A50++0x07
line.quad 0x00 "GICD_IROUTER330,Interrupt Routing Register 330"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A58++0x07
line.quad 0x00 "GICD_IROUTER331,Interrupt Routing Register 331"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A60++0x07
line.quad 0x00 "GICD_IROUTER332,Interrupt Routing Register 332"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A68++0x07
line.quad 0x00 "GICD_IROUTER333,Interrupt Routing Register 333"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A70++0x07
line.quad 0x00 "GICD_IROUTER334,Interrupt Routing Register 334"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A78++0x07
line.quad 0x00 "GICD_IROUTER335,Interrupt Routing Register 335"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A80++0x07
line.quad 0x00 "GICD_IROUTER336,Interrupt Routing Register 336"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A88++0x07
line.quad 0x00 "GICD_IROUTER337,Interrupt Routing Register 337"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A90++0x07
line.quad 0x00 "GICD_IROUTER338,Interrupt Routing Register 338"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6A98++0x07
line.quad 0x00 "GICD_IROUTER339,Interrupt Routing Register 339"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AA0++0x07
line.quad 0x00 "GICD_IROUTER340,Interrupt Routing Register 340"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AA8++0x07
line.quad 0x00 "GICD_IROUTER341,Interrupt Routing Register 341"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AB0++0x07
line.quad 0x00 "GICD_IROUTER342,Interrupt Routing Register 342"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AB8++0x07
line.quad 0x00 "GICD_IROUTER343,Interrupt Routing Register 343"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AC0++0x07
line.quad 0x00 "GICD_IROUTER344,Interrupt Routing Register 344"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AC8++0x07
line.quad 0x00 "GICD_IROUTER345,Interrupt Routing Register 345"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AD0++0x07
line.quad 0x00 "GICD_IROUTER346,Interrupt Routing Register 346"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AD8++0x07
line.quad 0x00 "GICD_IROUTER347,Interrupt Routing Register 347"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AE0++0x07
line.quad 0x00 "GICD_IROUTER348,Interrupt Routing Register 348"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AE8++0x07
line.quad 0x00 "GICD_IROUTER349,Interrupt Routing Register 349"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AF0++0x07
line.quad 0x00 "GICD_IROUTER350,Interrupt Routing Register 350"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6AF8++0x07
line.quad 0x00 "GICD_IROUTER351,Interrupt Routing Register 351"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B00++0x07
line.quad 0x00 "GICD_IROUTER352,Interrupt Routing Register 352"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B08++0x07
line.quad 0x00 "GICD_IROUTER353,Interrupt Routing Register 353"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B10++0x07
line.quad 0x00 "GICD_IROUTER354,Interrupt Routing Register 354"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B18++0x07
line.quad 0x00 "GICD_IROUTER355,Interrupt Routing Register 355"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B20++0x07
line.quad 0x00 "GICD_IROUTER356,Interrupt Routing Register 356"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B28++0x07
line.quad 0x00 "GICD_IROUTER357,Interrupt Routing Register 357"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B30++0x07
line.quad 0x00 "GICD_IROUTER358,Interrupt Routing Register 358"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B38++0x07
line.quad 0x00 "GICD_IROUTER359,Interrupt Routing Register 359"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B40++0x07
line.quad 0x00 "GICD_IROUTER360,Interrupt Routing Register 360"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B48++0x07
line.quad 0x00 "GICD_IROUTER361,Interrupt Routing Register 361"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B50++0x07
line.quad 0x00 "GICD_IROUTER362,Interrupt Routing Register 362"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B58++0x07
line.quad 0x00 "GICD_IROUTER363,Interrupt Routing Register 363"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B60++0x07
line.quad 0x00 "GICD_IROUTER364,Interrupt Routing Register 364"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B68++0x07
line.quad 0x00 "GICD_IROUTER365,Interrupt Routing Register 365"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B70++0x07
line.quad 0x00 "GICD_IROUTER366,Interrupt Routing Register 366"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B78++0x07
line.quad 0x00 "GICD_IROUTER367,Interrupt Routing Register 367"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B80++0x07
line.quad 0x00 "GICD_IROUTER368,Interrupt Routing Register 368"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B88++0x07
line.quad 0x00 "GICD_IROUTER369,Interrupt Routing Register 369"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B90++0x07
line.quad 0x00 "GICD_IROUTER370,Interrupt Routing Register 370"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6B98++0x07
line.quad 0x00 "GICD_IROUTER371,Interrupt Routing Register 371"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BA0++0x07
line.quad 0x00 "GICD_IROUTER372,Interrupt Routing Register 372"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BA8++0x07
line.quad 0x00 "GICD_IROUTER373,Interrupt Routing Register 373"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BB0++0x07
line.quad 0x00 "GICD_IROUTER374,Interrupt Routing Register 374"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BB8++0x07
line.quad 0x00 "GICD_IROUTER375,Interrupt Routing Register 375"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BC0++0x07
line.quad 0x00 "GICD_IROUTER376,Interrupt Routing Register 376"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BC8++0x07
line.quad 0x00 "GICD_IROUTER377,Interrupt Routing Register 377"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BD0++0x07
line.quad 0x00 "GICD_IROUTER378,Interrupt Routing Register 378"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BD8++0x07
line.quad 0x00 "GICD_IROUTER379,Interrupt Routing Register 379"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BE0++0x07
line.quad 0x00 "GICD_IROUTER380,Interrupt Routing Register 380"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BE8++0x07
line.quad 0x00 "GICD_IROUTER381,Interrupt Routing Register 381"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BF0++0x07
line.quad 0x00 "GICD_IROUTER382,Interrupt Routing Register 382"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6BF8++0x07
line.quad 0x00 "GICD_IROUTER383,Interrupt Routing Register 383"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C00++0x07
line.quad 0x00 "GICD_IROUTER384,Interrupt Routing Register 384"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C08++0x07
line.quad 0x00 "GICD_IROUTER385,Interrupt Routing Register 385"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C10++0x07
line.quad 0x00 "GICD_IROUTER386,Interrupt Routing Register 386"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C18++0x07
line.quad 0x00 "GICD_IROUTER387,Interrupt Routing Register 387"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C20++0x07
line.quad 0x00 "GICD_IROUTER388,Interrupt Routing Register 388"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C28++0x07
line.quad 0x00 "GICD_IROUTER389,Interrupt Routing Register 389"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C30++0x07
line.quad 0x00 "GICD_IROUTER390,Interrupt Routing Register 390"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C38++0x07
line.quad 0x00 "GICD_IROUTER391,Interrupt Routing Register 391"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C40++0x07
line.quad 0x00 "GICD_IROUTER392,Interrupt Routing Register 392"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C48++0x07
line.quad 0x00 "GICD_IROUTER393,Interrupt Routing Register 393"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C50++0x07
line.quad 0x00 "GICD_IROUTER394,Interrupt Routing Register 394"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C58++0x07
line.quad 0x00 "GICD_IROUTER395,Interrupt Routing Register 395"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C60++0x07
line.quad 0x00 "GICD_IROUTER396,Interrupt Routing Register 396"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C68++0x07
line.quad 0x00 "GICD_IROUTER397,Interrupt Routing Register 397"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C70++0x07
line.quad 0x00 "GICD_IROUTER398,Interrupt Routing Register 398"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C78++0x07
line.quad 0x00 "GICD_IROUTER399,Interrupt Routing Register 399"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C80++0x07
line.quad 0x00 "GICD_IROUTER400,Interrupt Routing Register 400"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C88++0x07
line.quad 0x00 "GICD_IROUTER401,Interrupt Routing Register 401"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C90++0x07
line.quad 0x00 "GICD_IROUTER402,Interrupt Routing Register 402"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6C98++0x07
line.quad 0x00 "GICD_IROUTER403,Interrupt Routing Register 403"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CA0++0x07
line.quad 0x00 "GICD_IROUTER404,Interrupt Routing Register 404"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CA8++0x07
line.quad 0x00 "GICD_IROUTER405,Interrupt Routing Register 405"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CB0++0x07
line.quad 0x00 "GICD_IROUTER406,Interrupt Routing Register 406"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CB8++0x07
line.quad 0x00 "GICD_IROUTER407,Interrupt Routing Register 407"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CC0++0x07
line.quad 0x00 "GICD_IROUTER408,Interrupt Routing Register 408"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CC8++0x07
line.quad 0x00 "GICD_IROUTER409,Interrupt Routing Register 409"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CD0++0x07
line.quad 0x00 "GICD_IROUTER410,Interrupt Routing Register 410"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CD8++0x07
line.quad 0x00 "GICD_IROUTER411,Interrupt Routing Register 411"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CE0++0x07
line.quad 0x00 "GICD_IROUTER412,Interrupt Routing Register 412"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CE8++0x07
line.quad 0x00 "GICD_IROUTER413,Interrupt Routing Register 413"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CF0++0x07
line.quad 0x00 "GICD_IROUTER414,Interrupt Routing Register 414"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6CF8++0x07
line.quad 0x00 "GICD_IROUTER415,Interrupt Routing Register 415"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D00++0x07
line.quad 0x00 "GICD_IROUTER416,Interrupt Routing Register 416"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D08++0x07
line.quad 0x00 "GICD_IROUTER417,Interrupt Routing Register 417"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D10++0x07
line.quad 0x00 "GICD_IROUTER418,Interrupt Routing Register 418"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D18++0x07
line.quad 0x00 "GICD_IROUTER419,Interrupt Routing Register 419"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D20++0x07
line.quad 0x00 "GICD_IROUTER420,Interrupt Routing Register 420"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D28++0x07
line.quad 0x00 "GICD_IROUTER421,Interrupt Routing Register 421"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D30++0x07
line.quad 0x00 "GICD_IROUTER422,Interrupt Routing Register 422"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D38++0x07
line.quad 0x00 "GICD_IROUTER423,Interrupt Routing Register 423"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D40++0x07
line.quad 0x00 "GICD_IROUTER424,Interrupt Routing Register 424"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D48++0x07
line.quad 0x00 "GICD_IROUTER425,Interrupt Routing Register 425"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D50++0x07
line.quad 0x00 "GICD_IROUTER426,Interrupt Routing Register 426"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D58++0x07
line.quad 0x00 "GICD_IROUTER427,Interrupt Routing Register 427"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D60++0x07
line.quad 0x00 "GICD_IROUTER428,Interrupt Routing Register 428"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D68++0x07
line.quad 0x00 "GICD_IROUTER429,Interrupt Routing Register 429"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D70++0x07
line.quad 0x00 "GICD_IROUTER430,Interrupt Routing Register 430"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D78++0x07
line.quad 0x00 "GICD_IROUTER431,Interrupt Routing Register 431"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D80++0x07
line.quad 0x00 "GICD_IROUTER432,Interrupt Routing Register 432"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D88++0x07
line.quad 0x00 "GICD_IROUTER433,Interrupt Routing Register 433"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D90++0x07
line.quad 0x00 "GICD_IROUTER434,Interrupt Routing Register 434"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6D98++0x07
line.quad 0x00 "GICD_IROUTER435,Interrupt Routing Register 435"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DA0++0x07
line.quad 0x00 "GICD_IROUTER436,Interrupt Routing Register 436"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DA8++0x07
line.quad 0x00 "GICD_IROUTER437,Interrupt Routing Register 437"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DB0++0x07
line.quad 0x00 "GICD_IROUTER438,Interrupt Routing Register 438"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DB8++0x07
line.quad 0x00 "GICD_IROUTER439,Interrupt Routing Register 439"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DC0++0x07
line.quad 0x00 "GICD_IROUTER440,Interrupt Routing Register 440"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DC8++0x07
line.quad 0x00 "GICD_IROUTER441,Interrupt Routing Register 441"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DD0++0x07
line.quad 0x00 "GICD_IROUTER442,Interrupt Routing Register 442"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DD8++0x07
line.quad 0x00 "GICD_IROUTER443,Interrupt Routing Register 443"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DE0++0x07
line.quad 0x00 "GICD_IROUTER444,Interrupt Routing Register 444"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DE8++0x07
line.quad 0x00 "GICD_IROUTER445,Interrupt Routing Register 445"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DF0++0x07
line.quad 0x00 "GICD_IROUTER446,Interrupt Routing Register 446"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6DF8++0x07
line.quad 0x00 "GICD_IROUTER447,Interrupt Routing Register 447"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E00++0x07
line.quad 0x00 "GICD_IROUTER448,Interrupt Routing Register 448"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E08++0x07
line.quad 0x00 "GICD_IROUTER449,Interrupt Routing Register 449"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E10++0x07
line.quad 0x00 "GICD_IROUTER450,Interrupt Routing Register 450"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E18++0x07
line.quad 0x00 "GICD_IROUTER451,Interrupt Routing Register 451"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E20++0x07
line.quad 0x00 "GICD_IROUTER452,Interrupt Routing Register 452"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E28++0x07
line.quad 0x00 "GICD_IROUTER453,Interrupt Routing Register 453"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E30++0x07
line.quad 0x00 "GICD_IROUTER454,Interrupt Routing Register 454"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E38++0x07
line.quad 0x00 "GICD_IROUTER455,Interrupt Routing Register 455"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E40++0x07
line.quad 0x00 "GICD_IROUTER456,Interrupt Routing Register 456"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E48++0x07
line.quad 0x00 "GICD_IROUTER457,Interrupt Routing Register 457"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E50++0x07
line.quad 0x00 "GICD_IROUTER458,Interrupt Routing Register 458"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E58++0x07
line.quad 0x00 "GICD_IROUTER459,Interrupt Routing Register 459"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E60++0x07
line.quad 0x00 "GICD_IROUTER460,Interrupt Routing Register 460"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E68++0x07
line.quad 0x00 "GICD_IROUTER461,Interrupt Routing Register 461"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E70++0x07
line.quad 0x00 "GICD_IROUTER462,Interrupt Routing Register 462"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E78++0x07
line.quad 0x00 "GICD_IROUTER463,Interrupt Routing Register 463"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E80++0x07
line.quad 0x00 "GICD_IROUTER464,Interrupt Routing Register 464"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E88++0x07
line.quad 0x00 "GICD_IROUTER465,Interrupt Routing Register 465"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E90++0x07
line.quad 0x00 "GICD_IROUTER466,Interrupt Routing Register 466"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6E98++0x07
line.quad 0x00 "GICD_IROUTER467,Interrupt Routing Register 467"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EA0++0x07
line.quad 0x00 "GICD_IROUTER468,Interrupt Routing Register 468"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EA8++0x07
line.quad 0x00 "GICD_IROUTER469,Interrupt Routing Register 469"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EB0++0x07
line.quad 0x00 "GICD_IROUTER470,Interrupt Routing Register 470"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EB8++0x07
line.quad 0x00 "GICD_IROUTER471,Interrupt Routing Register 471"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EC0++0x07
line.quad 0x00 "GICD_IROUTER472,Interrupt Routing Register 472"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EC8++0x07
line.quad 0x00 "GICD_IROUTER473,Interrupt Routing Register 473"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6ED0++0x07
line.quad 0x00 "GICD_IROUTER474,Interrupt Routing Register 474"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6ED8++0x07
line.quad 0x00 "GICD_IROUTER475,Interrupt Routing Register 475"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EE0++0x07
line.quad 0x00 "GICD_IROUTER476,Interrupt Routing Register 476"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EE8++0x07
line.quad 0x00 "GICD_IROUTER477,Interrupt Routing Register 477"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EF0++0x07
line.quad 0x00 "GICD_IROUTER478,Interrupt Routing Register 478"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6EF8++0x07
line.quad 0x00 "GICD_IROUTER479,Interrupt Routing Register 479"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F00++0x07
line.quad 0x00 "GICD_IROUTER480,Interrupt Routing Register 480"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F08++0x07
line.quad 0x00 "GICD_IROUTER481,Interrupt Routing Register 481"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F10++0x07
line.quad 0x00 "GICD_IROUTER482,Interrupt Routing Register 482"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F18++0x07
line.quad 0x00 "GICD_IROUTER483,Interrupt Routing Register 483"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F20++0x07
line.quad 0x00 "GICD_IROUTER484,Interrupt Routing Register 484"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F28++0x07
line.quad 0x00 "GICD_IROUTER485,Interrupt Routing Register 485"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F30++0x07
line.quad 0x00 "GICD_IROUTER486,Interrupt Routing Register 486"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F38++0x07
line.quad 0x00 "GICD_IROUTER487,Interrupt Routing Register 487"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F40++0x07
line.quad 0x00 "GICD_IROUTER488,Interrupt Routing Register 488"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F48++0x07
line.quad 0x00 "GICD_IROUTER489,Interrupt Routing Register 489"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F50++0x07
line.quad 0x00 "GICD_IROUTER490,Interrupt Routing Register 490"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F58++0x07
line.quad 0x00 "GICD_IROUTER491,Interrupt Routing Register 491"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F60++0x07
line.quad 0x00 "GICD_IROUTER492,Interrupt Routing Register 492"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F68++0x07
line.quad 0x00 "GICD_IROUTER493,Interrupt Routing Register 493"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F70++0x07
line.quad 0x00 "GICD_IROUTER494,Interrupt Routing Register 494"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F78++0x07
line.quad 0x00 "GICD_IROUTER495,Interrupt Routing Register 495"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F80++0x07
line.quad 0x00 "GICD_IROUTER496,Interrupt Routing Register 496"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F88++0x07
line.quad 0x00 "GICD_IROUTER497,Interrupt Routing Register 497"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F90++0x07
line.quad 0x00 "GICD_IROUTER498,Interrupt Routing Register 498"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6F98++0x07
line.quad 0x00 "GICD_IROUTER499,Interrupt Routing Register 499"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FA0++0x07
line.quad 0x00 "GICD_IROUTER500,Interrupt Routing Register 500"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FA8++0x07
line.quad 0x00 "GICD_IROUTER501,Interrupt Routing Register 501"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FB0++0x07
line.quad 0x00 "GICD_IROUTER502,Interrupt Routing Register 502"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FB8++0x07
line.quad 0x00 "GICD_IROUTER503,Interrupt Routing Register 503"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FC0++0x07
line.quad 0x00 "GICD_IROUTER504,Interrupt Routing Register 504"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FC8++0x07
line.quad 0x00 "GICD_IROUTER505,Interrupt Routing Register 505"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FD0++0x07
line.quad 0x00 "GICD_IROUTER506,Interrupt Routing Register 506"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FD8++0x07
line.quad 0x00 "GICD_IROUTER507,Interrupt Routing Register 507"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FE0++0x07
line.quad 0x00 "GICD_IROUTER508,Interrupt Routing Register 508"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FE8++0x07
line.quad 0x00 "GICD_IROUTER509,Interrupt Routing Register 509"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FF0++0x07
line.quad 0x00 "GICD_IROUTER510,Interrupt Routing Register 510"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x6FF8++0x07
line.quad 0x00 "GICD_IROUTER511,Interrupt Routing Register 511"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7000++0x07
line.quad 0x00 "GICD_IROUTER512,Interrupt Routing Register 512"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7008++0x07
line.quad 0x00 "GICD_IROUTER513,Interrupt Routing Register 513"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7010++0x07
line.quad 0x00 "GICD_IROUTER514,Interrupt Routing Register 514"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7018++0x07
line.quad 0x00 "GICD_IROUTER515,Interrupt Routing Register 515"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7020++0x07
line.quad 0x00 "GICD_IROUTER516,Interrupt Routing Register 516"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7028++0x07
line.quad 0x00 "GICD_IROUTER517,Interrupt Routing Register 517"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7030++0x07
line.quad 0x00 "GICD_IROUTER518,Interrupt Routing Register 518"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7038++0x07
line.quad 0x00 "GICD_IROUTER519,Interrupt Routing Register 519"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7040++0x07
line.quad 0x00 "GICD_IROUTER520,Interrupt Routing Register 520"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7048++0x07
line.quad 0x00 "GICD_IROUTER521,Interrupt Routing Register 521"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7050++0x07
line.quad 0x00 "GICD_IROUTER522,Interrupt Routing Register 522"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7058++0x07
line.quad 0x00 "GICD_IROUTER523,Interrupt Routing Register 523"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7060++0x07
line.quad 0x00 "GICD_IROUTER524,Interrupt Routing Register 524"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7068++0x07
line.quad 0x00 "GICD_IROUTER525,Interrupt Routing Register 525"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7070++0x07
line.quad 0x00 "GICD_IROUTER526,Interrupt Routing Register 526"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7078++0x07
line.quad 0x00 "GICD_IROUTER527,Interrupt Routing Register 527"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7080++0x07
line.quad 0x00 "GICD_IROUTER528,Interrupt Routing Register 528"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7088++0x07
line.quad 0x00 "GICD_IROUTER529,Interrupt Routing Register 529"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7090++0x07
line.quad 0x00 "GICD_IROUTER530,Interrupt Routing Register 530"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7098++0x07
line.quad 0x00 "GICD_IROUTER531,Interrupt Routing Register 531"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70A0++0x07
line.quad 0x00 "GICD_IROUTER532,Interrupt Routing Register 532"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70A8++0x07
line.quad 0x00 "GICD_IROUTER533,Interrupt Routing Register 533"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70B0++0x07
line.quad 0x00 "GICD_IROUTER534,Interrupt Routing Register 534"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70B8++0x07
line.quad 0x00 "GICD_IROUTER535,Interrupt Routing Register 535"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70C0++0x07
line.quad 0x00 "GICD_IROUTER536,Interrupt Routing Register 536"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70C8++0x07
line.quad 0x00 "GICD_IROUTER537,Interrupt Routing Register 537"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70D0++0x07
line.quad 0x00 "GICD_IROUTER538,Interrupt Routing Register 538"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70D8++0x07
line.quad 0x00 "GICD_IROUTER539,Interrupt Routing Register 539"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70E0++0x07
line.quad 0x00 "GICD_IROUTER540,Interrupt Routing Register 540"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70E8++0x07
line.quad 0x00 "GICD_IROUTER541,Interrupt Routing Register 541"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70F0++0x07
line.quad 0x00 "GICD_IROUTER542,Interrupt Routing Register 542"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x70F8++0x07
line.quad 0x00 "GICD_IROUTER543,Interrupt Routing Register 543"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7100++0x07
line.quad 0x00 "GICD_IROUTER544,Interrupt Routing Register 544"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7108++0x07
line.quad 0x00 "GICD_IROUTER545,Interrupt Routing Register 545"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7110++0x07
line.quad 0x00 "GICD_IROUTER546,Interrupt Routing Register 546"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7118++0x07
line.quad 0x00 "GICD_IROUTER547,Interrupt Routing Register 547"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7120++0x07
line.quad 0x00 "GICD_IROUTER548,Interrupt Routing Register 548"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7128++0x07
line.quad 0x00 "GICD_IROUTER549,Interrupt Routing Register 549"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7130++0x07
line.quad 0x00 "GICD_IROUTER550,Interrupt Routing Register 550"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7138++0x07
line.quad 0x00 "GICD_IROUTER551,Interrupt Routing Register 551"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7140++0x07
line.quad 0x00 "GICD_IROUTER552,Interrupt Routing Register 552"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7148++0x07
line.quad 0x00 "GICD_IROUTER553,Interrupt Routing Register 553"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7150++0x07
line.quad 0x00 "GICD_IROUTER554,Interrupt Routing Register 554"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7158++0x07
line.quad 0x00 "GICD_IROUTER555,Interrupt Routing Register 555"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7160++0x07
line.quad 0x00 "GICD_IROUTER556,Interrupt Routing Register 556"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7168++0x07
line.quad 0x00 "GICD_IROUTER557,Interrupt Routing Register 557"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7170++0x07
line.quad 0x00 "GICD_IROUTER558,Interrupt Routing Register 558"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7178++0x07
line.quad 0x00 "GICD_IROUTER559,Interrupt Routing Register 559"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7180++0x07
line.quad 0x00 "GICD_IROUTER560,Interrupt Routing Register 560"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7188++0x07
line.quad 0x00 "GICD_IROUTER561,Interrupt Routing Register 561"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7190++0x07
line.quad 0x00 "GICD_IROUTER562,Interrupt Routing Register 562"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7198++0x07
line.quad 0x00 "GICD_IROUTER563,Interrupt Routing Register 563"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71A0++0x07
line.quad 0x00 "GICD_IROUTER564,Interrupt Routing Register 564"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71A8++0x07
line.quad 0x00 "GICD_IROUTER565,Interrupt Routing Register 565"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71B0++0x07
line.quad 0x00 "GICD_IROUTER566,Interrupt Routing Register 566"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71B8++0x07
line.quad 0x00 "GICD_IROUTER567,Interrupt Routing Register 567"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71C0++0x07
line.quad 0x00 "GICD_IROUTER568,Interrupt Routing Register 568"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71C8++0x07
line.quad 0x00 "GICD_IROUTER569,Interrupt Routing Register 569"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71D0++0x07
line.quad 0x00 "GICD_IROUTER570,Interrupt Routing Register 570"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71D8++0x07
line.quad 0x00 "GICD_IROUTER571,Interrupt Routing Register 571"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71E0++0x07
line.quad 0x00 "GICD_IROUTER572,Interrupt Routing Register 572"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71E8++0x07
line.quad 0x00 "GICD_IROUTER573,Interrupt Routing Register 573"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71F0++0x07
line.quad 0x00 "GICD_IROUTER574,Interrupt Routing Register 574"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x71F8++0x07
line.quad 0x00 "GICD_IROUTER575,Interrupt Routing Register 575"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7200++0x07
line.quad 0x00 "GICD_IROUTER576,Interrupt Routing Register 576"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7208++0x07
line.quad 0x00 "GICD_IROUTER577,Interrupt Routing Register 577"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7210++0x07
line.quad 0x00 "GICD_IROUTER578,Interrupt Routing Register 578"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7218++0x07
line.quad 0x00 "GICD_IROUTER579,Interrupt Routing Register 579"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7220++0x07
line.quad 0x00 "GICD_IROUTER580,Interrupt Routing Register 580"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7228++0x07
line.quad 0x00 "GICD_IROUTER581,Interrupt Routing Register 581"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7230++0x07
line.quad 0x00 "GICD_IROUTER582,Interrupt Routing Register 582"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7238++0x07
line.quad 0x00 "GICD_IROUTER583,Interrupt Routing Register 583"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7240++0x07
line.quad 0x00 "GICD_IROUTER584,Interrupt Routing Register 584"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7248++0x07
line.quad 0x00 "GICD_IROUTER585,Interrupt Routing Register 585"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7250++0x07
line.quad 0x00 "GICD_IROUTER586,Interrupt Routing Register 586"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7258++0x07
line.quad 0x00 "GICD_IROUTER587,Interrupt Routing Register 587"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7260++0x07
line.quad 0x00 "GICD_IROUTER588,Interrupt Routing Register 588"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7268++0x07
line.quad 0x00 "GICD_IROUTER589,Interrupt Routing Register 589"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7270++0x07
line.quad 0x00 "GICD_IROUTER590,Interrupt Routing Register 590"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7278++0x07
line.quad 0x00 "GICD_IROUTER591,Interrupt Routing Register 591"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7280++0x07
line.quad 0x00 "GICD_IROUTER592,Interrupt Routing Register 592"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7288++0x07
line.quad 0x00 "GICD_IROUTER593,Interrupt Routing Register 593"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7290++0x07
line.quad 0x00 "GICD_IROUTER594,Interrupt Routing Register 594"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7298++0x07
line.quad 0x00 "GICD_IROUTER595,Interrupt Routing Register 595"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72A0++0x07
line.quad 0x00 "GICD_IROUTER596,Interrupt Routing Register 596"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72A8++0x07
line.quad 0x00 "GICD_IROUTER597,Interrupt Routing Register 597"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72B0++0x07
line.quad 0x00 "GICD_IROUTER598,Interrupt Routing Register 598"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72B8++0x07
line.quad 0x00 "GICD_IROUTER599,Interrupt Routing Register 599"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72C0++0x07
line.quad 0x00 "GICD_IROUTER600,Interrupt Routing Register 600"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72C8++0x07
line.quad 0x00 "GICD_IROUTER601,Interrupt Routing Register 601"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72D0++0x07
line.quad 0x00 "GICD_IROUTER602,Interrupt Routing Register 602"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72D8++0x07
line.quad 0x00 "GICD_IROUTER603,Interrupt Routing Register 603"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72E0++0x07
line.quad 0x00 "GICD_IROUTER604,Interrupt Routing Register 604"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72E8++0x07
line.quad 0x00 "GICD_IROUTER605,Interrupt Routing Register 605"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72F0++0x07
line.quad 0x00 "GICD_IROUTER606,Interrupt Routing Register 606"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x72F8++0x07
line.quad 0x00 "GICD_IROUTER607,Interrupt Routing Register 607"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7300++0x07
line.quad 0x00 "GICD_IROUTER608,Interrupt Routing Register 608"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7308++0x07
line.quad 0x00 "GICD_IROUTER609,Interrupt Routing Register 609"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7310++0x07
line.quad 0x00 "GICD_IROUTER610,Interrupt Routing Register 610"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7318++0x07
line.quad 0x00 "GICD_IROUTER611,Interrupt Routing Register 611"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7320++0x07
line.quad 0x00 "GICD_IROUTER612,Interrupt Routing Register 612"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7328++0x07
line.quad 0x00 "GICD_IROUTER613,Interrupt Routing Register 613"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7330++0x07
line.quad 0x00 "GICD_IROUTER614,Interrupt Routing Register 614"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7338++0x07
line.quad 0x00 "GICD_IROUTER615,Interrupt Routing Register 615"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7340++0x07
line.quad 0x00 "GICD_IROUTER616,Interrupt Routing Register 616"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7348++0x07
line.quad 0x00 "GICD_IROUTER617,Interrupt Routing Register 617"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7350++0x07
line.quad 0x00 "GICD_IROUTER618,Interrupt Routing Register 618"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7358++0x07
line.quad 0x00 "GICD_IROUTER619,Interrupt Routing Register 619"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7360++0x07
line.quad 0x00 "GICD_IROUTER620,Interrupt Routing Register 620"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7368++0x07
line.quad 0x00 "GICD_IROUTER621,Interrupt Routing Register 621"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7370++0x07
line.quad 0x00 "GICD_IROUTER622,Interrupt Routing Register 622"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7378++0x07
line.quad 0x00 "GICD_IROUTER623,Interrupt Routing Register 623"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7380++0x07
line.quad 0x00 "GICD_IROUTER624,Interrupt Routing Register 624"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7388++0x07
line.quad 0x00 "GICD_IROUTER625,Interrupt Routing Register 625"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7390++0x07
line.quad 0x00 "GICD_IROUTER626,Interrupt Routing Register 626"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7398++0x07
line.quad 0x00 "GICD_IROUTER627,Interrupt Routing Register 627"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73A0++0x07
line.quad 0x00 "GICD_IROUTER628,Interrupt Routing Register 628"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73A8++0x07
line.quad 0x00 "GICD_IROUTER629,Interrupt Routing Register 629"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73B0++0x07
line.quad 0x00 "GICD_IROUTER630,Interrupt Routing Register 630"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73B8++0x07
line.quad 0x00 "GICD_IROUTER631,Interrupt Routing Register 631"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73C0++0x07
line.quad 0x00 "GICD_IROUTER632,Interrupt Routing Register 632"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73C8++0x07
line.quad 0x00 "GICD_IROUTER633,Interrupt Routing Register 633"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73D0++0x07
line.quad 0x00 "GICD_IROUTER634,Interrupt Routing Register 634"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73D8++0x07
line.quad 0x00 "GICD_IROUTER635,Interrupt Routing Register 635"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73E0++0x07
line.quad 0x00 "GICD_IROUTER636,Interrupt Routing Register 636"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73E8++0x07
line.quad 0x00 "GICD_IROUTER637,Interrupt Routing Register 637"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73F0++0x07
line.quad 0x00 "GICD_IROUTER638,Interrupt Routing Register 638"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x73F8++0x07
line.quad 0x00 "GICD_IROUTER639,Interrupt Routing Register 639"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7400++0x07
line.quad 0x00 "GICD_IROUTER640,Interrupt Routing Register 640"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7408++0x07
line.quad 0x00 "GICD_IROUTER641,Interrupt Routing Register 641"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7410++0x07
line.quad 0x00 "GICD_IROUTER642,Interrupt Routing Register 642"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7418++0x07
line.quad 0x00 "GICD_IROUTER643,Interrupt Routing Register 643"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7420++0x07
line.quad 0x00 "GICD_IROUTER644,Interrupt Routing Register 644"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7428++0x07
line.quad 0x00 "GICD_IROUTER645,Interrupt Routing Register 645"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7430++0x07
line.quad 0x00 "GICD_IROUTER646,Interrupt Routing Register 646"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7438++0x07
line.quad 0x00 "GICD_IROUTER647,Interrupt Routing Register 647"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7440++0x07
line.quad 0x00 "GICD_IROUTER648,Interrupt Routing Register 648"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7448++0x07
line.quad 0x00 "GICD_IROUTER649,Interrupt Routing Register 649"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7450++0x07
line.quad 0x00 "GICD_IROUTER650,Interrupt Routing Register 650"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7458++0x07
line.quad 0x00 "GICD_IROUTER651,Interrupt Routing Register 651"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7460++0x07
line.quad 0x00 "GICD_IROUTER652,Interrupt Routing Register 652"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7468++0x07
line.quad 0x00 "GICD_IROUTER653,Interrupt Routing Register 653"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7470++0x07
line.quad 0x00 "GICD_IROUTER654,Interrupt Routing Register 654"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7478++0x07
line.quad 0x00 "GICD_IROUTER655,Interrupt Routing Register 655"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7480++0x07
line.quad 0x00 "GICD_IROUTER656,Interrupt Routing Register 656"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7488++0x07
line.quad 0x00 "GICD_IROUTER657,Interrupt Routing Register 657"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7490++0x07
line.quad 0x00 "GICD_IROUTER658,Interrupt Routing Register 658"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7498++0x07
line.quad 0x00 "GICD_IROUTER659,Interrupt Routing Register 659"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74A0++0x07
line.quad 0x00 "GICD_IROUTER660,Interrupt Routing Register 660"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74A8++0x07
line.quad 0x00 "GICD_IROUTER661,Interrupt Routing Register 661"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74B0++0x07
line.quad 0x00 "GICD_IROUTER662,Interrupt Routing Register 662"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74B8++0x07
line.quad 0x00 "GICD_IROUTER663,Interrupt Routing Register 663"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74C0++0x07
line.quad 0x00 "GICD_IROUTER664,Interrupt Routing Register 664"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74C8++0x07
line.quad 0x00 "GICD_IROUTER665,Interrupt Routing Register 665"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74D0++0x07
line.quad 0x00 "GICD_IROUTER666,Interrupt Routing Register 666"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74D8++0x07
line.quad 0x00 "GICD_IROUTER667,Interrupt Routing Register 667"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74E0++0x07
line.quad 0x00 "GICD_IROUTER668,Interrupt Routing Register 668"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74E8++0x07
line.quad 0x00 "GICD_IROUTER669,Interrupt Routing Register 669"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74F0++0x07
line.quad 0x00 "GICD_IROUTER670,Interrupt Routing Register 670"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x74F8++0x07
line.quad 0x00 "GICD_IROUTER671,Interrupt Routing Register 671"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7500++0x07
line.quad 0x00 "GICD_IROUTER672,Interrupt Routing Register 672"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7508++0x07
line.quad 0x00 "GICD_IROUTER673,Interrupt Routing Register 673"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7510++0x07
line.quad 0x00 "GICD_IROUTER674,Interrupt Routing Register 674"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7518++0x07
line.quad 0x00 "GICD_IROUTER675,Interrupt Routing Register 675"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7520++0x07
line.quad 0x00 "GICD_IROUTER676,Interrupt Routing Register 676"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7528++0x07
line.quad 0x00 "GICD_IROUTER677,Interrupt Routing Register 677"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7530++0x07
line.quad 0x00 "GICD_IROUTER678,Interrupt Routing Register 678"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7538++0x07
line.quad 0x00 "GICD_IROUTER679,Interrupt Routing Register 679"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7540++0x07
line.quad 0x00 "GICD_IROUTER680,Interrupt Routing Register 680"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7548++0x07
line.quad 0x00 "GICD_IROUTER681,Interrupt Routing Register 681"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7550++0x07
line.quad 0x00 "GICD_IROUTER682,Interrupt Routing Register 682"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7558++0x07
line.quad 0x00 "GICD_IROUTER683,Interrupt Routing Register 683"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7560++0x07
line.quad 0x00 "GICD_IROUTER684,Interrupt Routing Register 684"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7568++0x07
line.quad 0x00 "GICD_IROUTER685,Interrupt Routing Register 685"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7570++0x07
line.quad 0x00 "GICD_IROUTER686,Interrupt Routing Register 686"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7578++0x07
line.quad 0x00 "GICD_IROUTER687,Interrupt Routing Register 687"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7580++0x07
line.quad 0x00 "GICD_IROUTER688,Interrupt Routing Register 688"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7588++0x07
line.quad 0x00 "GICD_IROUTER689,Interrupt Routing Register 689"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7590++0x07
line.quad 0x00 "GICD_IROUTER690,Interrupt Routing Register 690"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7598++0x07
line.quad 0x00 "GICD_IROUTER691,Interrupt Routing Register 691"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75A0++0x07
line.quad 0x00 "GICD_IROUTER692,Interrupt Routing Register 692"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75A8++0x07
line.quad 0x00 "GICD_IROUTER693,Interrupt Routing Register 693"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75B0++0x07
line.quad 0x00 "GICD_IROUTER694,Interrupt Routing Register 694"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75B8++0x07
line.quad 0x00 "GICD_IROUTER695,Interrupt Routing Register 695"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75C0++0x07
line.quad 0x00 "GICD_IROUTER696,Interrupt Routing Register 696"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75C8++0x07
line.quad 0x00 "GICD_IROUTER697,Interrupt Routing Register 697"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75D0++0x07
line.quad 0x00 "GICD_IROUTER698,Interrupt Routing Register 698"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75D8++0x07
line.quad 0x00 "GICD_IROUTER699,Interrupt Routing Register 699"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75E0++0x07
line.quad 0x00 "GICD_IROUTER700,Interrupt Routing Register 700"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75E8++0x07
line.quad 0x00 "GICD_IROUTER701,Interrupt Routing Register 701"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75F0++0x07
line.quad 0x00 "GICD_IROUTER702,Interrupt Routing Register 702"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x75F8++0x07
line.quad 0x00 "GICD_IROUTER703,Interrupt Routing Register 703"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7600++0x07
line.quad 0x00 "GICD_IROUTER704,Interrupt Routing Register 704"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7608++0x07
line.quad 0x00 "GICD_IROUTER705,Interrupt Routing Register 705"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7610++0x07
line.quad 0x00 "GICD_IROUTER706,Interrupt Routing Register 706"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7618++0x07
line.quad 0x00 "GICD_IROUTER707,Interrupt Routing Register 707"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7620++0x07
line.quad 0x00 "GICD_IROUTER708,Interrupt Routing Register 708"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7628++0x07
line.quad 0x00 "GICD_IROUTER709,Interrupt Routing Register 709"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7630++0x07
line.quad 0x00 "GICD_IROUTER710,Interrupt Routing Register 710"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7638++0x07
line.quad 0x00 "GICD_IROUTER711,Interrupt Routing Register 711"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7640++0x07
line.quad 0x00 "GICD_IROUTER712,Interrupt Routing Register 712"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7648++0x07
line.quad 0x00 "GICD_IROUTER713,Interrupt Routing Register 713"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7650++0x07
line.quad 0x00 "GICD_IROUTER714,Interrupt Routing Register 714"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7658++0x07
line.quad 0x00 "GICD_IROUTER715,Interrupt Routing Register 715"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7660++0x07
line.quad 0x00 "GICD_IROUTER716,Interrupt Routing Register 716"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7668++0x07
line.quad 0x00 "GICD_IROUTER717,Interrupt Routing Register 717"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7670++0x07
line.quad 0x00 "GICD_IROUTER718,Interrupt Routing Register 718"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7678++0x07
line.quad 0x00 "GICD_IROUTER719,Interrupt Routing Register 719"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7680++0x07
line.quad 0x00 "GICD_IROUTER720,Interrupt Routing Register 720"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7688++0x07
line.quad 0x00 "GICD_IROUTER721,Interrupt Routing Register 721"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7690++0x07
line.quad 0x00 "GICD_IROUTER722,Interrupt Routing Register 722"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7698++0x07
line.quad 0x00 "GICD_IROUTER723,Interrupt Routing Register 723"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76A0++0x07
line.quad 0x00 "GICD_IROUTER724,Interrupt Routing Register 724"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76A8++0x07
line.quad 0x00 "GICD_IROUTER725,Interrupt Routing Register 725"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76B0++0x07
line.quad 0x00 "GICD_IROUTER726,Interrupt Routing Register 726"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76B8++0x07
line.quad 0x00 "GICD_IROUTER727,Interrupt Routing Register 727"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76C0++0x07
line.quad 0x00 "GICD_IROUTER728,Interrupt Routing Register 728"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76C8++0x07
line.quad 0x00 "GICD_IROUTER729,Interrupt Routing Register 729"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76D0++0x07
line.quad 0x00 "GICD_IROUTER730,Interrupt Routing Register 730"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76D8++0x07
line.quad 0x00 "GICD_IROUTER731,Interrupt Routing Register 731"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76E0++0x07
line.quad 0x00 "GICD_IROUTER732,Interrupt Routing Register 732"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76E8++0x07
line.quad 0x00 "GICD_IROUTER733,Interrupt Routing Register 733"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76F0++0x07
line.quad 0x00 "GICD_IROUTER734,Interrupt Routing Register 734"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x76F8++0x07
line.quad 0x00 "GICD_IROUTER735,Interrupt Routing Register 735"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7700++0x07
line.quad 0x00 "GICD_IROUTER736,Interrupt Routing Register 736"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7708++0x07
line.quad 0x00 "GICD_IROUTER737,Interrupt Routing Register 737"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7710++0x07
line.quad 0x00 "GICD_IROUTER738,Interrupt Routing Register 738"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7718++0x07
line.quad 0x00 "GICD_IROUTER739,Interrupt Routing Register 739"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7720++0x07
line.quad 0x00 "GICD_IROUTER740,Interrupt Routing Register 740"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7728++0x07
line.quad 0x00 "GICD_IROUTER741,Interrupt Routing Register 741"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7730++0x07
line.quad 0x00 "GICD_IROUTER742,Interrupt Routing Register 742"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7738++0x07
line.quad 0x00 "GICD_IROUTER743,Interrupt Routing Register 743"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7740++0x07
line.quad 0x00 "GICD_IROUTER744,Interrupt Routing Register 744"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7748++0x07
line.quad 0x00 "GICD_IROUTER745,Interrupt Routing Register 745"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7750++0x07
line.quad 0x00 "GICD_IROUTER746,Interrupt Routing Register 746"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7758++0x07
line.quad 0x00 "GICD_IROUTER747,Interrupt Routing Register 747"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7760++0x07
line.quad 0x00 "GICD_IROUTER748,Interrupt Routing Register 748"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7768++0x07
line.quad 0x00 "GICD_IROUTER749,Interrupt Routing Register 749"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7770++0x07
line.quad 0x00 "GICD_IROUTER750,Interrupt Routing Register 750"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7778++0x07
line.quad 0x00 "GICD_IROUTER751,Interrupt Routing Register 751"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7780++0x07
line.quad 0x00 "GICD_IROUTER752,Interrupt Routing Register 752"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7788++0x07
line.quad 0x00 "GICD_IROUTER753,Interrupt Routing Register 753"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7790++0x07
line.quad 0x00 "GICD_IROUTER754,Interrupt Routing Register 754"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7798++0x07
line.quad 0x00 "GICD_IROUTER755,Interrupt Routing Register 755"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77A0++0x07
line.quad 0x00 "GICD_IROUTER756,Interrupt Routing Register 756"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77A8++0x07
line.quad 0x00 "GICD_IROUTER757,Interrupt Routing Register 757"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77B0++0x07
line.quad 0x00 "GICD_IROUTER758,Interrupt Routing Register 758"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77B8++0x07
line.quad 0x00 "GICD_IROUTER759,Interrupt Routing Register 759"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77C0++0x07
line.quad 0x00 "GICD_IROUTER760,Interrupt Routing Register 760"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77C8++0x07
line.quad 0x00 "GICD_IROUTER761,Interrupt Routing Register 761"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77D0++0x07
line.quad 0x00 "GICD_IROUTER762,Interrupt Routing Register 762"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77D8++0x07
line.quad 0x00 "GICD_IROUTER763,Interrupt Routing Register 763"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77E0++0x07
line.quad 0x00 "GICD_IROUTER764,Interrupt Routing Register 764"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77E8++0x07
line.quad 0x00 "GICD_IROUTER765,Interrupt Routing Register 765"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77F0++0x07
line.quad 0x00 "GICD_IROUTER766,Interrupt Routing Register 766"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x77F8++0x07
line.quad 0x00 "GICD_IROUTER767,Interrupt Routing Register 767"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7800++0x07
line.quad 0x00 "GICD_IROUTER768,Interrupt Routing Register 768"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7808++0x07
line.quad 0x00 "GICD_IROUTER769,Interrupt Routing Register 769"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7810++0x07
line.quad 0x00 "GICD_IROUTER770,Interrupt Routing Register 770"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7818++0x07
line.quad 0x00 "GICD_IROUTER771,Interrupt Routing Register 771"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7820++0x07
line.quad 0x00 "GICD_IROUTER772,Interrupt Routing Register 772"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7828++0x07
line.quad 0x00 "GICD_IROUTER773,Interrupt Routing Register 773"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7830++0x07
line.quad 0x00 "GICD_IROUTER774,Interrupt Routing Register 774"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7838++0x07
line.quad 0x00 "GICD_IROUTER775,Interrupt Routing Register 775"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7840++0x07
line.quad 0x00 "GICD_IROUTER776,Interrupt Routing Register 776"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7848++0x07
line.quad 0x00 "GICD_IROUTER777,Interrupt Routing Register 777"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7850++0x07
line.quad 0x00 "GICD_IROUTER778,Interrupt Routing Register 778"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7858++0x07
line.quad 0x00 "GICD_IROUTER779,Interrupt Routing Register 779"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7860++0x07
line.quad 0x00 "GICD_IROUTER780,Interrupt Routing Register 780"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7868++0x07
line.quad 0x00 "GICD_IROUTER781,Interrupt Routing Register 781"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7870++0x07
line.quad 0x00 "GICD_IROUTER782,Interrupt Routing Register 782"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7878++0x07
line.quad 0x00 "GICD_IROUTER783,Interrupt Routing Register 783"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7880++0x07
line.quad 0x00 "GICD_IROUTER784,Interrupt Routing Register 784"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7888++0x07
line.quad 0x00 "GICD_IROUTER785,Interrupt Routing Register 785"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7890++0x07
line.quad 0x00 "GICD_IROUTER786,Interrupt Routing Register 786"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7898++0x07
line.quad 0x00 "GICD_IROUTER787,Interrupt Routing Register 787"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78A0++0x07
line.quad 0x00 "GICD_IROUTER788,Interrupt Routing Register 788"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78A8++0x07
line.quad 0x00 "GICD_IROUTER789,Interrupt Routing Register 789"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78B0++0x07
line.quad 0x00 "GICD_IROUTER790,Interrupt Routing Register 790"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78B8++0x07
line.quad 0x00 "GICD_IROUTER791,Interrupt Routing Register 791"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78C0++0x07
line.quad 0x00 "GICD_IROUTER792,Interrupt Routing Register 792"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78C8++0x07
line.quad 0x00 "GICD_IROUTER793,Interrupt Routing Register 793"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78D0++0x07
line.quad 0x00 "GICD_IROUTER794,Interrupt Routing Register 794"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78D8++0x07
line.quad 0x00 "GICD_IROUTER795,Interrupt Routing Register 795"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78E0++0x07
line.quad 0x00 "GICD_IROUTER796,Interrupt Routing Register 796"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78E8++0x07
line.quad 0x00 "GICD_IROUTER797,Interrupt Routing Register 797"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78F0++0x07
line.quad 0x00 "GICD_IROUTER798,Interrupt Routing Register 798"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x78F8++0x07
line.quad 0x00 "GICD_IROUTER799,Interrupt Routing Register 799"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7900++0x07
line.quad 0x00 "GICD_IROUTER800,Interrupt Routing Register 800"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7908++0x07
line.quad 0x00 "GICD_IROUTER801,Interrupt Routing Register 801"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7910++0x07
line.quad 0x00 "GICD_IROUTER802,Interrupt Routing Register 802"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7918++0x07
line.quad 0x00 "GICD_IROUTER803,Interrupt Routing Register 803"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7920++0x07
line.quad 0x00 "GICD_IROUTER804,Interrupt Routing Register 804"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7928++0x07
line.quad 0x00 "GICD_IROUTER805,Interrupt Routing Register 805"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7930++0x07
line.quad 0x00 "GICD_IROUTER806,Interrupt Routing Register 806"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7938++0x07
line.quad 0x00 "GICD_IROUTER807,Interrupt Routing Register 807"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7940++0x07
line.quad 0x00 "GICD_IROUTER808,Interrupt Routing Register 808"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7948++0x07
line.quad 0x00 "GICD_IROUTER809,Interrupt Routing Register 809"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7950++0x07
line.quad 0x00 "GICD_IROUTER810,Interrupt Routing Register 810"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7958++0x07
line.quad 0x00 "GICD_IROUTER811,Interrupt Routing Register 811"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7960++0x07
line.quad 0x00 "GICD_IROUTER812,Interrupt Routing Register 812"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7968++0x07
line.quad 0x00 "GICD_IROUTER813,Interrupt Routing Register 813"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7970++0x07
line.quad 0x00 "GICD_IROUTER814,Interrupt Routing Register 814"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7978++0x07
line.quad 0x00 "GICD_IROUTER815,Interrupt Routing Register 815"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7980++0x07
line.quad 0x00 "GICD_IROUTER816,Interrupt Routing Register 816"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7988++0x07
line.quad 0x00 "GICD_IROUTER817,Interrupt Routing Register 817"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7990++0x07
line.quad 0x00 "GICD_IROUTER818,Interrupt Routing Register 818"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7998++0x07
line.quad 0x00 "GICD_IROUTER819,Interrupt Routing Register 819"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79A0++0x07
line.quad 0x00 "GICD_IROUTER820,Interrupt Routing Register 820"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79A8++0x07
line.quad 0x00 "GICD_IROUTER821,Interrupt Routing Register 821"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79B0++0x07
line.quad 0x00 "GICD_IROUTER822,Interrupt Routing Register 822"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79B8++0x07
line.quad 0x00 "GICD_IROUTER823,Interrupt Routing Register 823"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79C0++0x07
line.quad 0x00 "GICD_IROUTER824,Interrupt Routing Register 824"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79C8++0x07
line.quad 0x00 "GICD_IROUTER825,Interrupt Routing Register 825"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79D0++0x07
line.quad 0x00 "GICD_IROUTER826,Interrupt Routing Register 826"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79D8++0x07
line.quad 0x00 "GICD_IROUTER827,Interrupt Routing Register 827"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79E0++0x07
line.quad 0x00 "GICD_IROUTER828,Interrupt Routing Register 828"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79E8++0x07
line.quad 0x00 "GICD_IROUTER829,Interrupt Routing Register 829"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79F0++0x07
line.quad 0x00 "GICD_IROUTER830,Interrupt Routing Register 830"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x79F8++0x07
line.quad 0x00 "GICD_IROUTER831,Interrupt Routing Register 831"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A00++0x07
line.quad 0x00 "GICD_IROUTER832,Interrupt Routing Register 832"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A08++0x07
line.quad 0x00 "GICD_IROUTER833,Interrupt Routing Register 833"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A10++0x07
line.quad 0x00 "GICD_IROUTER834,Interrupt Routing Register 834"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A18++0x07
line.quad 0x00 "GICD_IROUTER835,Interrupt Routing Register 835"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A20++0x07
line.quad 0x00 "GICD_IROUTER836,Interrupt Routing Register 836"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A28++0x07
line.quad 0x00 "GICD_IROUTER837,Interrupt Routing Register 837"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A30++0x07
line.quad 0x00 "GICD_IROUTER838,Interrupt Routing Register 838"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A38++0x07
line.quad 0x00 "GICD_IROUTER839,Interrupt Routing Register 839"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A40++0x07
line.quad 0x00 "GICD_IROUTER840,Interrupt Routing Register 840"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A48++0x07
line.quad 0x00 "GICD_IROUTER841,Interrupt Routing Register 841"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A50++0x07
line.quad 0x00 "GICD_IROUTER842,Interrupt Routing Register 842"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A58++0x07
line.quad 0x00 "GICD_IROUTER843,Interrupt Routing Register 843"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A60++0x07
line.quad 0x00 "GICD_IROUTER844,Interrupt Routing Register 844"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A68++0x07
line.quad 0x00 "GICD_IROUTER845,Interrupt Routing Register 845"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A70++0x07
line.quad 0x00 "GICD_IROUTER846,Interrupt Routing Register 846"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A78++0x07
line.quad 0x00 "GICD_IROUTER847,Interrupt Routing Register 847"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A80++0x07
line.quad 0x00 "GICD_IROUTER848,Interrupt Routing Register 848"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A88++0x07
line.quad 0x00 "GICD_IROUTER849,Interrupt Routing Register 849"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A90++0x07
line.quad 0x00 "GICD_IROUTER850,Interrupt Routing Register 850"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7A98++0x07
line.quad 0x00 "GICD_IROUTER851,Interrupt Routing Register 851"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AA0++0x07
line.quad 0x00 "GICD_IROUTER852,Interrupt Routing Register 852"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AA8++0x07
line.quad 0x00 "GICD_IROUTER853,Interrupt Routing Register 853"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AB0++0x07
line.quad 0x00 "GICD_IROUTER854,Interrupt Routing Register 854"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AB8++0x07
line.quad 0x00 "GICD_IROUTER855,Interrupt Routing Register 855"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AC0++0x07
line.quad 0x00 "GICD_IROUTER856,Interrupt Routing Register 856"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AC8++0x07
line.quad 0x00 "GICD_IROUTER857,Interrupt Routing Register 857"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AD0++0x07
line.quad 0x00 "GICD_IROUTER858,Interrupt Routing Register 858"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AD8++0x07
line.quad 0x00 "GICD_IROUTER859,Interrupt Routing Register 859"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AE0++0x07
line.quad 0x00 "GICD_IROUTER860,Interrupt Routing Register 860"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AE8++0x07
line.quad 0x00 "GICD_IROUTER861,Interrupt Routing Register 861"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AF0++0x07
line.quad 0x00 "GICD_IROUTER862,Interrupt Routing Register 862"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7AF8++0x07
line.quad 0x00 "GICD_IROUTER863,Interrupt Routing Register 863"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B00++0x07
line.quad 0x00 "GICD_IROUTER864,Interrupt Routing Register 864"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B08++0x07
line.quad 0x00 "GICD_IROUTER865,Interrupt Routing Register 865"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B10++0x07
line.quad 0x00 "GICD_IROUTER866,Interrupt Routing Register 866"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B18++0x07
line.quad 0x00 "GICD_IROUTER867,Interrupt Routing Register 867"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B20++0x07
line.quad 0x00 "GICD_IROUTER868,Interrupt Routing Register 868"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B28++0x07
line.quad 0x00 "GICD_IROUTER869,Interrupt Routing Register 869"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B30++0x07
line.quad 0x00 "GICD_IROUTER870,Interrupt Routing Register 870"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B38++0x07
line.quad 0x00 "GICD_IROUTER871,Interrupt Routing Register 871"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B40++0x07
line.quad 0x00 "GICD_IROUTER872,Interrupt Routing Register 872"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B48++0x07
line.quad 0x00 "GICD_IROUTER873,Interrupt Routing Register 873"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B50++0x07
line.quad 0x00 "GICD_IROUTER874,Interrupt Routing Register 874"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B58++0x07
line.quad 0x00 "GICD_IROUTER875,Interrupt Routing Register 875"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B60++0x07
line.quad 0x00 "GICD_IROUTER876,Interrupt Routing Register 876"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B68++0x07
line.quad 0x00 "GICD_IROUTER877,Interrupt Routing Register 877"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B70++0x07
line.quad 0x00 "GICD_IROUTER878,Interrupt Routing Register 878"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B78++0x07
line.quad 0x00 "GICD_IROUTER879,Interrupt Routing Register 879"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B80++0x07
line.quad 0x00 "GICD_IROUTER880,Interrupt Routing Register 880"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B88++0x07
line.quad 0x00 "GICD_IROUTER881,Interrupt Routing Register 881"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B90++0x07
line.quad 0x00 "GICD_IROUTER882,Interrupt Routing Register 882"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7B98++0x07
line.quad 0x00 "GICD_IROUTER883,Interrupt Routing Register 883"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BA0++0x07
line.quad 0x00 "GICD_IROUTER884,Interrupt Routing Register 884"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BA8++0x07
line.quad 0x00 "GICD_IROUTER885,Interrupt Routing Register 885"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BB0++0x07
line.quad 0x00 "GICD_IROUTER886,Interrupt Routing Register 886"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BB8++0x07
line.quad 0x00 "GICD_IROUTER887,Interrupt Routing Register 887"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BC0++0x07
line.quad 0x00 "GICD_IROUTER888,Interrupt Routing Register 888"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BC8++0x07
line.quad 0x00 "GICD_IROUTER889,Interrupt Routing Register 889"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BD0++0x07
line.quad 0x00 "GICD_IROUTER890,Interrupt Routing Register 890"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BD8++0x07
line.quad 0x00 "GICD_IROUTER891,Interrupt Routing Register 891"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BE0++0x07
line.quad 0x00 "GICD_IROUTER892,Interrupt Routing Register 892"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BE8++0x07
line.quad 0x00 "GICD_IROUTER893,Interrupt Routing Register 893"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BF0++0x07
line.quad 0x00 "GICD_IROUTER894,Interrupt Routing Register 894"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7BF8++0x07
line.quad 0x00 "GICD_IROUTER895,Interrupt Routing Register 895"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C00++0x07
line.quad 0x00 "GICD_IROUTER896,Interrupt Routing Register 896"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C08++0x07
line.quad 0x00 "GICD_IROUTER897,Interrupt Routing Register 897"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C10++0x07
line.quad 0x00 "GICD_IROUTER898,Interrupt Routing Register 898"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C18++0x07
line.quad 0x00 "GICD_IROUTER899,Interrupt Routing Register 899"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C20++0x07
line.quad 0x00 "GICD_IROUTER900,Interrupt Routing Register 900"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C28++0x07
line.quad 0x00 "GICD_IROUTER901,Interrupt Routing Register 901"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C30++0x07
line.quad 0x00 "GICD_IROUTER902,Interrupt Routing Register 902"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C38++0x07
line.quad 0x00 "GICD_IROUTER903,Interrupt Routing Register 903"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C40++0x07
line.quad 0x00 "GICD_IROUTER904,Interrupt Routing Register 904"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C48++0x07
line.quad 0x00 "GICD_IROUTER905,Interrupt Routing Register 905"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C50++0x07
line.quad 0x00 "GICD_IROUTER906,Interrupt Routing Register 906"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C58++0x07
line.quad 0x00 "GICD_IROUTER907,Interrupt Routing Register 907"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C60++0x07
line.quad 0x00 "GICD_IROUTER908,Interrupt Routing Register 908"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C68++0x07
line.quad 0x00 "GICD_IROUTER909,Interrupt Routing Register 909"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C70++0x07
line.quad 0x00 "GICD_IROUTER910,Interrupt Routing Register 910"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C78++0x07
line.quad 0x00 "GICD_IROUTER911,Interrupt Routing Register 911"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C80++0x07
line.quad 0x00 "GICD_IROUTER912,Interrupt Routing Register 912"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C88++0x07
line.quad 0x00 "GICD_IROUTER913,Interrupt Routing Register 913"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C90++0x07
line.quad 0x00 "GICD_IROUTER914,Interrupt Routing Register 914"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7C98++0x07
line.quad 0x00 "GICD_IROUTER915,Interrupt Routing Register 915"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CA0++0x07
line.quad 0x00 "GICD_IROUTER916,Interrupt Routing Register 916"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CA8++0x07
line.quad 0x00 "GICD_IROUTER917,Interrupt Routing Register 917"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CB0++0x07
line.quad 0x00 "GICD_IROUTER918,Interrupt Routing Register 918"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CB8++0x07
line.quad 0x00 "GICD_IROUTER919,Interrupt Routing Register 919"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CC0++0x07
line.quad 0x00 "GICD_IROUTER920,Interrupt Routing Register 920"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CC8++0x07
line.quad 0x00 "GICD_IROUTER921,Interrupt Routing Register 921"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CD0++0x07
line.quad 0x00 "GICD_IROUTER922,Interrupt Routing Register 922"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CD8++0x07
line.quad 0x00 "GICD_IROUTER923,Interrupt Routing Register 923"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CE0++0x07
line.quad 0x00 "GICD_IROUTER924,Interrupt Routing Register 924"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CE8++0x07
line.quad 0x00 "GICD_IROUTER925,Interrupt Routing Register 925"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CF0++0x07
line.quad 0x00 "GICD_IROUTER926,Interrupt Routing Register 926"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7CF8++0x07
line.quad 0x00 "GICD_IROUTER927,Interrupt Routing Register 927"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D00++0x07
line.quad 0x00 "GICD_IROUTER928,Interrupt Routing Register 928"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D08++0x07
line.quad 0x00 "GICD_IROUTER929,Interrupt Routing Register 929"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D10++0x07
line.quad 0x00 "GICD_IROUTER930,Interrupt Routing Register 930"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D18++0x07
line.quad 0x00 "GICD_IROUTER931,Interrupt Routing Register 931"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D20++0x07
line.quad 0x00 "GICD_IROUTER932,Interrupt Routing Register 932"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D28++0x07
line.quad 0x00 "GICD_IROUTER933,Interrupt Routing Register 933"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D30++0x07
line.quad 0x00 "GICD_IROUTER934,Interrupt Routing Register 934"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D38++0x07
line.quad 0x00 "GICD_IROUTER935,Interrupt Routing Register 935"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D40++0x07
line.quad 0x00 "GICD_IROUTER936,Interrupt Routing Register 936"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D48++0x07
line.quad 0x00 "GICD_IROUTER937,Interrupt Routing Register 937"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D50++0x07
line.quad 0x00 "GICD_IROUTER938,Interrupt Routing Register 938"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D58++0x07
line.quad 0x00 "GICD_IROUTER939,Interrupt Routing Register 939"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D60++0x07
line.quad 0x00 "GICD_IROUTER940,Interrupt Routing Register 940"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D68++0x07
line.quad 0x00 "GICD_IROUTER941,Interrupt Routing Register 941"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D70++0x07
line.quad 0x00 "GICD_IROUTER942,Interrupt Routing Register 942"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D78++0x07
line.quad 0x00 "GICD_IROUTER943,Interrupt Routing Register 943"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D80++0x07
line.quad 0x00 "GICD_IROUTER944,Interrupt Routing Register 944"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D88++0x07
line.quad 0x00 "GICD_IROUTER945,Interrupt Routing Register 945"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D90++0x07
line.quad 0x00 "GICD_IROUTER946,Interrupt Routing Register 946"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7D98++0x07
line.quad 0x00 "GICD_IROUTER947,Interrupt Routing Register 947"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DA0++0x07
line.quad 0x00 "GICD_IROUTER948,Interrupt Routing Register 948"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DA8++0x07
line.quad 0x00 "GICD_IROUTER949,Interrupt Routing Register 949"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DB0++0x07
line.quad 0x00 "GICD_IROUTER950,Interrupt Routing Register 950"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DB8++0x07
line.quad 0x00 "GICD_IROUTER951,Interrupt Routing Register 951"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DC0++0x07
line.quad 0x00 "GICD_IROUTER952,Interrupt Routing Register 952"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DC8++0x07
line.quad 0x00 "GICD_IROUTER953,Interrupt Routing Register 953"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DD0++0x07
line.quad 0x00 "GICD_IROUTER954,Interrupt Routing Register 954"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DD8++0x07
line.quad 0x00 "GICD_IROUTER955,Interrupt Routing Register 955"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DE0++0x07
line.quad 0x00 "GICD_IROUTER956,Interrupt Routing Register 956"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DE8++0x07
line.quad 0x00 "GICD_IROUTER957,Interrupt Routing Register 957"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DF0++0x07
line.quad 0x00 "GICD_IROUTER958,Interrupt Routing Register 958"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7DF8++0x07
line.quad 0x00 "GICD_IROUTER959,Interrupt Routing Register 959"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E00++0x07
line.quad 0x00 "GICD_IROUTER960,Interrupt Routing Register 960"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E08++0x07
line.quad 0x00 "GICD_IROUTER961,Interrupt Routing Register 961"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E10++0x07
line.quad 0x00 "GICD_IROUTER962,Interrupt Routing Register 962"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E18++0x07
line.quad 0x00 "GICD_IROUTER963,Interrupt Routing Register 963"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E20++0x07
line.quad 0x00 "GICD_IROUTER964,Interrupt Routing Register 964"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E28++0x07
line.quad 0x00 "GICD_IROUTER965,Interrupt Routing Register 965"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E30++0x07
line.quad 0x00 "GICD_IROUTER966,Interrupt Routing Register 966"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E38++0x07
line.quad 0x00 "GICD_IROUTER967,Interrupt Routing Register 967"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E40++0x07
line.quad 0x00 "GICD_IROUTER968,Interrupt Routing Register 968"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E48++0x07
line.quad 0x00 "GICD_IROUTER969,Interrupt Routing Register 969"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E50++0x07
line.quad 0x00 "GICD_IROUTER970,Interrupt Routing Register 970"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E58++0x07
line.quad 0x00 "GICD_IROUTER971,Interrupt Routing Register 971"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E60++0x07
line.quad 0x00 "GICD_IROUTER972,Interrupt Routing Register 972"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E68++0x07
line.quad 0x00 "GICD_IROUTER973,Interrupt Routing Register 973"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E70++0x07
line.quad 0x00 "GICD_IROUTER974,Interrupt Routing Register 974"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E78++0x07
line.quad 0x00 "GICD_IROUTER975,Interrupt Routing Register 975"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E80++0x07
line.quad 0x00 "GICD_IROUTER976,Interrupt Routing Register 976"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E88++0x07
line.quad 0x00 "GICD_IROUTER977,Interrupt Routing Register 977"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E90++0x07
line.quad 0x00 "GICD_IROUTER978,Interrupt Routing Register 978"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7E98++0x07
line.quad 0x00 "GICD_IROUTER979,Interrupt Routing Register 979"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EA0++0x07
line.quad 0x00 "GICD_IROUTER980,Interrupt Routing Register 980"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EA8++0x07
line.quad 0x00 "GICD_IROUTER981,Interrupt Routing Register 981"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EB0++0x07
line.quad 0x00 "GICD_IROUTER982,Interrupt Routing Register 982"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EB8++0x07
line.quad 0x00 "GICD_IROUTER983,Interrupt Routing Register 983"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EC0++0x07
line.quad 0x00 "GICD_IROUTER984,Interrupt Routing Register 984"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EC8++0x07
line.quad 0x00 "GICD_IROUTER985,Interrupt Routing Register 985"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7ED0++0x07
line.quad 0x00 "GICD_IROUTER986,Interrupt Routing Register 986"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7ED8++0x07
line.quad 0x00 "GICD_IROUTER987,Interrupt Routing Register 987"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EE0++0x07
line.quad 0x00 "GICD_IROUTER988,Interrupt Routing Register 988"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EE8++0x07
line.quad 0x00 "GICD_IROUTER989,Interrupt Routing Register 989"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EF0++0x07
line.quad 0x00 "GICD_IROUTER990,Interrupt Routing Register 990"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
group.quad 0x7EF8++0x07
line.quad 0x00 "GICD_IROUTER991,Interrupt Routing Register 991"
hexmask.quad.byte 0x00 32.--39. 1. " AFF3 ,Affinity level 3"
bitfld.quad 0x00 31. "  IRM  ,Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy" "PE specified by AFFn fields,Any PE defined as a participating node"
textline "                                         "
hexmask.quad.byte 0x00 16.--23. 1. " AFF2 ,Affinity level 2"
hexmask.quad.byte 0x00 8.--15. 1. "  AFF1 ,Affinity level 1"
textline "                                         "
hexmask.quad.byte 0x00 0.--7. 1. " AFF0 ,Affinity level 0"
tree.end
width 22.
tree "Interrupt Class Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=1.)
group.long (0xE000+0x8)++0x03
line.long 0x0 "GICD_ICLAR2,Interrupt Class Register 2"
bitfld.long 0x00 31. " SPI047_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI047_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI046_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI046_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI045_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI045_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI044_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI044_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI043_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI043_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI042_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI042_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI041_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI041_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI040_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI040_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI039_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI039_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI038_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI038_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI037_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI037_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI036_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI036_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI035_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI035_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI034_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI034_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI033_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI033_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI032_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI032_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x8)++0x03
hide.long 0x0 "GICD_ICLAR2,Interrupt Class Register 2"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=1.)
group.long (0xE000+0xc)++0x03
line.long 0x0 "GICD_ICLAR3,Interrupt Class Register 3"
bitfld.long 0x00 31. " SPI063_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI063_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI062_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI062_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI061_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI061_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI060_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI060_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI059_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI059_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI058_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI058_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI057_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI057_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI056_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI056_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI055_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI055_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI054_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI054_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI053_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI053_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI052_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI052_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI051_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI051_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI050_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI050_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI049_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI049_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI048_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI048_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xc)++0x03
hide.long 0x0 "GICD_ICLAR3,Interrupt Class Register 3"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=2.)
group.long (0xE000+0x10)++0x03
line.long 0x0 "GICD_ICLAR4,Interrupt Class Register 4"
bitfld.long 0x00 31. " SPI079_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI079_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI078_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI078_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI077_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI077_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI076_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI076_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI075_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI075_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI074_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI074_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI073_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI073_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI072_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI072_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI071_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI071_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI070_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI070_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI069_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI069_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI068_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI068_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI067_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI067_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI066_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI066_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI065_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI065_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI064_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI064_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x10)++0x03
hide.long 0x0 "GICD_ICLAR4,Interrupt Class Register 4"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=2.)
group.long (0xE000+0x14)++0x03
line.long 0x0 "GICD_ICLAR5,Interrupt Class Register 5"
bitfld.long 0x00 31. " SPI095_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI095_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI094_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI094_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI093_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI093_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI092_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI092_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI091_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI091_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI090_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI090_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI089_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI089_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI088_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI088_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI087_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI087_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI086_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI086_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI085_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI085_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI084_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI084_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI083_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI083_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI082_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI082_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI081_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI081_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI080_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI080_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x14)++0x03
hide.long 0x0 "GICD_ICLAR5,Interrupt Class Register 5"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=3.)
group.long (0xE000+0x18)++0x03
line.long 0x0 "GICD_ICLAR6,Interrupt Class Register 6"
bitfld.long 0x00 31. " SPI111_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI111_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI110_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI110_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI109_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI109_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI108_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI108_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI107_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI107_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI106_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI106_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI105_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI105_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI104_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI104_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI103_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI103_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI102_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI102_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI101_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI101_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI100_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI100_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI099_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI099_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI098_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI098_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI097_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI097_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI096_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI096_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x18)++0x03
hide.long 0x0 "GICD_ICLAR6,Interrupt Class Register 6"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=3.)
group.long (0xE000+0x1c)++0x03
line.long 0x0 "GICD_ICLAR7,Interrupt Class Register 7"
bitfld.long 0x00 31. " SPI127_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI127_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI126_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI126_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI125_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI125_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI124_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI124_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI123_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI123_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI122_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI122_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI121_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI121_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI120_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI120_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI119_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI119_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI118_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI118_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI117_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI117_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI116_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI116_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI115_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI115_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI114_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI114_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI113_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI113_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI112_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI112_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x1c)++0x03
hide.long 0x0 "GICD_ICLAR7,Interrupt Class Register 7"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=4.)
group.long (0xE000+0x20)++0x03
line.long 0x0 "GICD_ICLAR8,Interrupt Class Register 8"
bitfld.long 0x00 31. " SPI143_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI143_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI142_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI142_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI141_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI141_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI140_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI140_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI139_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI139_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI138_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI138_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI137_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI137_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI136_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI136_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI135_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI135_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI134_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI134_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI133_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI133_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI132_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI132_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI131_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI131_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI130_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI130_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI129_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI129_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI128_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI128_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x20)++0x03
hide.long 0x0 "GICD_ICLAR8,Interrupt Class Register 8"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=4.)
group.long (0xE000+0x24)++0x03
line.long 0x0 "GICD_ICLAR9,Interrupt Class Register 9"
bitfld.long 0x00 31. " SPI159_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI159_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI158_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI158_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI157_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI157_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI156_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI156_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI155_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI155_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI154_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI154_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI153_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI153_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI152_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI152_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI151_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI151_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI150_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI150_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI149_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI149_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI148_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI148_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI147_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI147_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI146_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI146_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI145_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI145_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI144_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI144_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x24)++0x03
hide.long 0x0 "GICD_ICLAR9,Interrupt Class Register 9"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=5.)
group.long (0xE000+0x28)++0x03
line.long 0x0 "GICD_ICLAR10,Interrupt Class Register 10"
bitfld.long 0x00 31. " SPI175_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI175_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI174_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI174_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI173_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI173_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI172_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI172_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI171_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI171_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI170_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI170_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI169_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI169_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI168_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI168_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI167_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI167_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI166_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI166_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI165_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI165_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI164_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI164_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI163_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI163_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI162_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI162_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI161_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI161_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI160_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI160_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x28)++0x03
hide.long 0x0 "GICD_ICLAR10,Interrupt Class Register 10"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=5.)
group.long (0xE000+0x2c)++0x03
line.long 0x0 "GICD_ICLAR11,Interrupt Class Register 11"
bitfld.long 0x00 31. " SPI191_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI191_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI190_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI190_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI189_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI189_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI188_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI188_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI187_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI187_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI186_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI186_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI185_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI185_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI184_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI184_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI183_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI183_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI182_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI182_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI181_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI181_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI180_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI180_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI179_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI179_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI178_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI178_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI177_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI177_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI176_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI176_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x2c)++0x03
hide.long 0x0 "GICD_ICLAR11,Interrupt Class Register 11"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=6.)
group.long (0xE000+0x30)++0x03
line.long 0x0 "GICD_ICLAR12,Interrupt Class Register 12"
bitfld.long 0x00 31. " SPI207_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI207_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI206_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI206_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI205_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI205_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI204_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI204_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI203_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI203_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI202_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI202_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI201_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI201_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI200_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI200_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI199_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI199_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI198_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI198_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI197_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI197_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI196_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI196_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI195_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI195_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI194_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI194_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI193_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI193_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI192_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI192_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x30)++0x03
hide.long 0x0 "GICD_ICLAR12,Interrupt Class Register 12"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=6.)
group.long (0xE000+0x34)++0x03
line.long 0x0 "GICD_ICLAR13,Interrupt Class Register 13"
bitfld.long 0x00 31. " SPI223_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI223_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI222_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI222_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI221_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI221_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI220_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI220_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI219_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI219_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI218_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI218_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI217_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI217_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI216_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI216_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI215_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI215_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI214_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI214_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI213_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI213_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI212_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI212_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI211_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI211_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI210_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI210_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI209_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI209_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI208_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI208_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x34)++0x03
hide.long 0x0 "GICD_ICLAR13,Interrupt Class Register 13"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=7.)
group.long (0xE000+0x38)++0x03
line.long 0x0 "GICD_ICLAR14,Interrupt Class Register 14"
bitfld.long 0x00 31. " SPI239_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI239_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI238_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI238_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI237_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI237_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI236_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI236_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI235_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI235_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI234_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI234_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI233_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI233_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI232_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI232_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI231_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI231_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI230_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI230_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI229_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI229_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI228_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI228_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI227_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI227_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI226_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI226_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI225_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI225_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI224_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI224_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x38)++0x03
hide.long 0x0 "GICD_ICLAR14,Interrupt Class Register 14"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=7.)
group.long (0xE000+0x3c)++0x03
line.long 0x0 "GICD_ICLAR15,Interrupt Class Register 15"
bitfld.long 0x00 31. " SPI255_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI255_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI254_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI254_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI253_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI253_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI252_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI252_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI251_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI251_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI250_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI250_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI249_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI249_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI248_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI248_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI247_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI247_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI246_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI246_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI245_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI245_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI244_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI244_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI243_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI243_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI242_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI242_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI241_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI241_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI240_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI240_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x3c)++0x03
hide.long 0x0 "GICD_ICLAR15,Interrupt Class Register 15"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=8.)
group.long (0xE000+0x40)++0x03
line.long 0x0 "GICD_ICLAR16,Interrupt Class Register 16"
bitfld.long 0x00 31. " SPI271_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI271_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI270_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI270_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI269_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI269_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI268_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI268_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI267_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI267_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI266_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI266_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI265_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI265_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI264_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI264_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI263_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI263_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI262_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI262_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI261_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI261_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI260_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI260_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI259_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI259_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI258_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI258_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI257_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI257_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI256_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI256_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x40)++0x03
hide.long 0x0 "GICD_ICLAR16,Interrupt Class Register 16"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=8.)
group.long (0xE000+0x44)++0x03
line.long 0x0 "GICD_ICLAR17,Interrupt Class Register 17"
bitfld.long 0x00 31. " SPI287_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI287_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI286_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI286_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI285_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI285_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI284_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI284_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI283_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI283_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI282_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI282_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI281_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI281_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI280_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI280_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI279_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI279_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI278_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI278_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI277_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI277_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI276_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI276_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI275_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI275_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI274_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI274_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI273_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI273_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI272_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI272_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x44)++0x03
hide.long 0x0 "GICD_ICLAR17,Interrupt Class Register 17"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=9.)
group.long (0xE000+0x48)++0x03
line.long 0x0 "GICD_ICLAR18,Interrupt Class Register 18"
bitfld.long 0x00 31. " SPI303_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI303_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI302_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI302_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI301_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI301_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI300_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI300_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI299_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI299_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI298_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI298_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI297_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI297_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI296_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI296_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI295_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI295_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI294_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI294_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI293_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI293_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI292_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI292_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI291_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI291_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI290_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI290_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI289_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI289_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI288_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI288_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x48)++0x03
hide.long 0x0 "GICD_ICLAR18,Interrupt Class Register 18"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=9.)
group.long (0xE000+0x4c)++0x03
line.long 0x0 "GICD_ICLAR19,Interrupt Class Register 19"
bitfld.long 0x00 31. " SPI319_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI319_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI318_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI318_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI317_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI317_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI316_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI316_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI315_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI315_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI314_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI314_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI313_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI313_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI312_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI312_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI311_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI311_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI310_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI310_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI309_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI309_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI308_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI308_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI307_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI307_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI306_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI306_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI305_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI305_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI304_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI304_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x4c)++0x03
hide.long 0x0 "GICD_ICLAR19,Interrupt Class Register 19"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=10.)
group.long (0xE000+0x50)++0x03
line.long 0x0 "GICD_ICLAR20,Interrupt Class Register 20"
bitfld.long 0x00 31. " SPI335_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI335_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI334_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI334_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI333_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI333_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI332_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI332_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI331_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI331_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI330_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI330_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI329_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI329_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI328_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI328_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI327_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI327_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI326_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI326_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI325_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI325_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI324_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI324_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI323_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI323_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI322_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI322_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI321_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI321_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI320_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI320_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x50)++0x03
hide.long 0x0 "GICD_ICLAR20,Interrupt Class Register 20"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=10.)
group.long (0xE000+0x54)++0x03
line.long 0x0 "GICD_ICLAR21,Interrupt Class Register 21"
bitfld.long 0x00 31. " SPI351_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI351_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI350_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI350_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI349_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI349_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI348_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI348_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI347_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI347_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI346_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI346_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI345_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI345_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI344_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI344_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI343_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI343_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI342_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI342_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI341_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI341_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI340_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI340_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI339_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI339_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI338_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI338_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI337_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI337_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI336_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI336_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x54)++0x03
hide.long 0x0 "GICD_ICLAR21,Interrupt Class Register 21"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=11.)
group.long (0xE000+0x58)++0x03
line.long 0x0 "GICD_ICLAR22,Interrupt Class Register 22"
bitfld.long 0x00 31. " SPI367_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI367_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI366_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI366_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI365_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI365_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI364_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI364_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI363_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI363_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI362_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI362_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI361_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI361_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI360_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI360_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI359_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI359_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI358_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI358_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI357_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI357_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI356_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI356_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI355_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI355_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI354_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI354_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI353_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI353_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI352_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI352_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x58)++0x03
hide.long 0x0 "GICD_ICLAR22,Interrupt Class Register 22"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=11.)
group.long (0xE000+0x5c)++0x03
line.long 0x0 "GICD_ICLAR23,Interrupt Class Register 23"
bitfld.long 0x00 31. " SPI383_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI383_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI382_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI382_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI381_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI381_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI380_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI380_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI379_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI379_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI378_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI378_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI377_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI377_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI376_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI376_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI375_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI375_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI374_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI374_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI373_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI373_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI372_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI372_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI371_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI371_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI370_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI370_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI369_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI369_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI368_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI368_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x5c)++0x03
hide.long 0x0 "GICD_ICLAR23,Interrupt Class Register 23"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=12.)
group.long (0xE000+0x60)++0x03
line.long 0x0 "GICD_ICLAR24,Interrupt Class Register 24"
bitfld.long 0x00 31. " SPI399_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI399_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI398_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI398_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI397_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI397_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI396_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI396_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI395_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI395_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI394_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI394_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI393_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI393_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI392_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI392_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI391_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI391_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI390_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI390_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI389_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI389_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI388_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI388_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI387_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI387_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI386_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI386_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI385_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI385_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI384_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI384_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x60)++0x03
hide.long 0x0 "GICD_ICLAR24,Interrupt Class Register 24"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=12.)
group.long (0xE000+0x64)++0x03
line.long 0x0 "GICD_ICLAR25,Interrupt Class Register 25"
bitfld.long 0x00 31. " SPI415_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI415_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI414_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI414_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI413_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI413_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI412_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI412_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI411_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI411_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI410_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI410_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI409_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI409_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI408_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI408_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI407_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI407_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI406_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI406_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI405_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI405_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI404_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI404_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI403_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI403_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI402_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI402_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI401_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI401_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI400_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI400_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x64)++0x03
hide.long 0x0 "GICD_ICLAR25,Interrupt Class Register 25"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=13.)
group.long (0xE000+0x68)++0x03
line.long 0x0 "GICD_ICLAR26,Interrupt Class Register 26"
bitfld.long 0x00 31. " SPI431_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI431_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI430_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI430_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI429_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI429_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI428_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI428_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI427_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI427_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI426_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI426_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI425_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI425_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI424_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI424_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI423_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI423_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI422_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI422_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI421_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI421_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI420_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI420_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI419_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI419_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI418_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI418_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI417_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI417_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI416_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI416_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x68)++0x03
hide.long 0x0 "GICD_ICLAR26,Interrupt Class Register 26"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=13.)
group.long (0xE000+0x6c)++0x03
line.long 0x0 "GICD_ICLAR27,Interrupt Class Register 27"
bitfld.long 0x00 31. " SPI447_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI447_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI446_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI446_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI445_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI445_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI444_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI444_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI443_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI443_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI442_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI442_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI441_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI441_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI440_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI440_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI439_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI439_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI438_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI438_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI437_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI437_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI436_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI436_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI435_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI435_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI434_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI434_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI433_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI433_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI432_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI432_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x6c)++0x03
hide.long 0x0 "GICD_ICLAR27,Interrupt Class Register 27"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=14.)
group.long (0xE000+0x70)++0x03
line.long 0x0 "GICD_ICLAR28,Interrupt Class Register 28"
bitfld.long 0x00 31. " SPI463_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI463_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI462_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI462_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI461_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI461_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI460_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI460_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI459_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI459_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI458_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI458_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI457_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI457_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI456_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI456_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI455_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI455_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI454_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI454_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI453_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI453_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI452_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI452_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI451_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI451_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI450_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI450_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI449_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI449_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI448_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI448_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x70)++0x03
hide.long 0x0 "GICD_ICLAR28,Interrupt Class Register 28"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=14.)
group.long (0xE000+0x74)++0x03
line.long 0x0 "GICD_ICLAR29,Interrupt Class Register 29"
bitfld.long 0x00 31. " SPI479_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI479_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI478_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI478_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI477_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI477_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI476_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI476_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI475_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI475_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI474_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI474_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI473_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI473_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI472_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI472_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI471_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI471_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI470_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI470_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI469_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI469_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI468_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI468_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI467_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI467_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI466_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI466_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI465_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI465_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI464_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI464_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x74)++0x03
hide.long 0x0 "GICD_ICLAR29,Interrupt Class Register 29"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=15.)
group.long (0xE000+0x78)++0x03
line.long 0x0 "GICD_ICLAR30,Interrupt Class Register 30"
bitfld.long 0x00 31. " SPI495_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI495_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI494_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI494_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI493_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI493_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI492_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI492_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI491_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI491_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI490_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI490_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI489_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI489_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI488_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI488_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI487_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI487_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI486_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI486_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI485_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI485_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI484_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI484_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI483_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI483_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI482_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI482_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI481_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI481_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI480_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI480_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x78)++0x03
hide.long 0x0 "GICD_ICLAR30,Interrupt Class Register 30"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=15.)
group.long (0xE000+0x7c)++0x03
line.long 0x0 "GICD_ICLAR31,Interrupt Class Register 31"
bitfld.long 0x00 31. " SPI511_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI511_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI510_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI510_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI509_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI509_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI508_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI508_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI507_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI507_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI506_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI506_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI505_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI505_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI504_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI504_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI503_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI503_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI502_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI502_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI501_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI501_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI500_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI500_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI499_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI499_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI498_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI498_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI497_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI497_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI496_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI496_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x7c)++0x03
hide.long 0x0 "GICD_ICLAR31,Interrupt Class Register 31"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=16.)
group.long (0xE000+0x80)++0x03
line.long 0x0 "GICD_ICLAR32,Interrupt Class Register 32"
bitfld.long 0x00 31. " SPI527_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI527_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI526_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI526_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI525_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI525_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI524_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI524_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI523_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI523_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI522_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI522_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI521_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI521_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI520_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI520_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI519_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI519_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI518_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI518_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI517_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI517_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI516_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI516_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI515_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI515_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI514_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI514_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI513_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI513_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI512_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI512_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x80)++0x03
hide.long 0x0 "GICD_ICLAR32,Interrupt Class Register 32"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=16.)
group.long (0xE000+0x84)++0x03
line.long 0x0 "GICD_ICLAR33,Interrupt Class Register 33"
bitfld.long 0x00 31. " SPI543_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI543_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI542_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI542_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI541_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI541_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI540_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI540_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI539_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI539_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI538_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI538_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI537_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI537_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI536_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI536_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI535_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI535_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI534_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI534_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI533_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI533_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI532_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI532_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI531_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI531_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI530_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI530_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI529_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI529_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI528_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI528_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x84)++0x03
hide.long 0x0 "GICD_ICLAR33,Interrupt Class Register 33"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=17.)
group.long (0xE000+0x88)++0x03
line.long 0x0 "GICD_ICLAR34,Interrupt Class Register 34"
bitfld.long 0x00 31. " SPI559_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI559_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI558_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI558_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI557_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI557_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI556_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI556_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI555_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI555_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI554_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI554_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI553_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI553_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI552_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI552_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI551_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI551_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI550_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI550_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI549_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI549_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI548_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI548_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI547_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI547_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI546_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI546_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI545_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI545_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI544_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI544_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x88)++0x03
hide.long 0x0 "GICD_ICLAR34,Interrupt Class Register 34"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=17.)
group.long (0xE000+0x8c)++0x03
line.long 0x0 "GICD_ICLAR35,Interrupt Class Register 35"
bitfld.long 0x00 31. " SPI575_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI575_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI574_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI574_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI573_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI573_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI572_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI572_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI571_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI571_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI570_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI570_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI569_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI569_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI568_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI568_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI567_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI567_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI566_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI566_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI565_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI565_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI564_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI564_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI563_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI563_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI562_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI562_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI561_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI561_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI560_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI560_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x8c)++0x03
hide.long 0x0 "GICD_ICLAR35,Interrupt Class Register 35"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=18.)
group.long (0xE000+0x90)++0x03
line.long 0x0 "GICD_ICLAR36,Interrupt Class Register 36"
bitfld.long 0x00 31. " SPI591_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI591_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI590_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI590_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI589_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI589_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI588_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI588_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI587_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI587_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI586_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI586_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI585_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI585_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI584_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI584_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI583_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI583_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI582_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI582_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI581_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI581_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI580_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI580_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI579_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI579_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI578_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI578_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI577_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI577_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI576_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI576_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x90)++0x03
hide.long 0x0 "GICD_ICLAR36,Interrupt Class Register 36"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=18.)
group.long (0xE000+0x94)++0x03
line.long 0x0 "GICD_ICLAR37,Interrupt Class Register 37"
bitfld.long 0x00 31. " SPI607_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI607_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI606_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI606_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI605_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI605_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI604_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI604_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI603_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI603_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI602_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI602_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI601_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI601_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI600_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI600_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI599_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI599_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI598_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI598_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI597_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI597_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI596_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI596_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI595_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI595_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI594_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI594_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI593_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI593_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI592_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI592_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x94)++0x03
hide.long 0x0 "GICD_ICLAR37,Interrupt Class Register 37"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=19.)
group.long (0xE000+0x98)++0x03
line.long 0x0 "GICD_ICLAR38,Interrupt Class Register 38"
bitfld.long 0x00 31. " SPI623_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI623_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI622_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI622_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI621_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI621_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI620_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI620_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI619_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI619_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI618_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI618_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI617_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI617_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI616_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI616_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI615_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI615_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI614_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI614_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI613_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI613_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI612_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI612_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI611_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI611_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI610_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI610_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI609_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI609_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI608_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI608_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x98)++0x03
hide.long 0x0 "GICD_ICLAR38,Interrupt Class Register 38"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=19.)
group.long (0xE000+0x9c)++0x03
line.long 0x0 "GICD_ICLAR39,Interrupt Class Register 39"
bitfld.long 0x00 31. " SPI639_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI639_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI638_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI638_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI637_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI637_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI636_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI636_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI635_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI635_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI634_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI634_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI633_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI633_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI632_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI632_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI631_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI631_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI630_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI630_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI629_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI629_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI628_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI628_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI627_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI627_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI626_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI626_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI625_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI625_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI624_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI624_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0x9c)++0x03
hide.long 0x0 "GICD_ICLAR39,Interrupt Class Register 39"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=20.)
group.long (0xE000+0xa0)++0x03
line.long 0x0 "GICD_ICLAR40,Interrupt Class Register 40"
bitfld.long 0x00 31. " SPI655_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI655_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI654_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI654_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI653_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI653_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI652_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI652_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI651_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI651_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI650_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI650_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI649_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI649_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI648_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI648_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI647_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI647_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI646_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI646_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI645_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI645_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI644_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI644_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI643_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI643_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI642_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI642_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI641_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI641_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI640_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI640_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xa0)++0x03
hide.long 0x0 "GICD_ICLAR40,Interrupt Class Register 40"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=20.)
group.long (0xE000+0xa4)++0x03
line.long 0x0 "GICD_ICLAR41,Interrupt Class Register 41"
bitfld.long 0x00 31. " SPI671_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI671_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI670_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI670_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI669_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI669_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI668_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI668_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI667_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI667_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI666_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI666_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI665_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI665_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI664_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI664_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI663_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI663_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI662_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI662_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI661_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI661_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI660_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI660_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI659_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI659_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI658_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI658_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI657_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI657_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI656_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI656_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xa4)++0x03
hide.long 0x0 "GICD_ICLAR41,Interrupt Class Register 41"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=21.)
group.long (0xE000+0xa8)++0x03
line.long 0x0 "GICD_ICLAR42,Interrupt Class Register 42"
bitfld.long 0x00 31. " SPI687_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI687_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI686_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI686_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI685_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI685_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI684_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI684_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI683_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI683_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI682_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI682_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI681_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI681_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI680_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI680_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI679_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI679_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI678_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI678_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI677_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI677_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI676_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI676_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI675_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI675_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI674_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI674_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI673_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI673_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI672_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI672_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xa8)++0x03
hide.long 0x0 "GICD_ICLAR42,Interrupt Class Register 42"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=21.)
group.long (0xE000+0xac)++0x03
line.long 0x0 "GICD_ICLAR43,Interrupt Class Register 43"
bitfld.long 0x00 31. " SPI703_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI703_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI702_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI702_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI701_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI701_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI700_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI700_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI699_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI699_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI698_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI698_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI697_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI697_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI696_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI696_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI695_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI695_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI694_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI694_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI693_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI693_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI692_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI692_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI691_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI691_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI690_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI690_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI689_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI689_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI688_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI688_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xac)++0x03
hide.long 0x0 "GICD_ICLAR43,Interrupt Class Register 43"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=22.)
group.long (0xE000+0xb0)++0x03
line.long 0x0 "GICD_ICLAR44,Interrupt Class Register 44"
bitfld.long 0x00 31. " SPI719_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI719_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI718_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI718_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI717_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI717_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI716_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI716_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI715_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI715_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI714_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI714_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI713_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI713_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI712_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI712_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI711_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI711_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI710_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI710_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI709_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI709_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI708_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI708_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI707_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI707_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI706_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI706_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI705_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI705_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI704_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI704_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xb0)++0x03
hide.long 0x0 "GICD_ICLAR44,Interrupt Class Register 44"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=22.)
group.long (0xE000+0xb4)++0x03
line.long 0x0 "GICD_ICLAR45,Interrupt Class Register 45"
bitfld.long 0x00 31. " SPI735_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI735_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI734_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI734_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI733_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI733_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI732_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI732_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI731_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI731_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI730_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI730_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI729_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI729_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI728_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI728_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI727_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI727_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI726_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI726_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI725_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI725_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI724_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI724_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI723_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI723_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI722_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI722_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI721_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI721_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI720_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI720_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xb4)++0x03
hide.long 0x0 "GICD_ICLAR45,Interrupt Class Register 45"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=23.)
group.long (0xE000+0xb8)++0x03
line.long 0x0 "GICD_ICLAR46,Interrupt Class Register 46"
bitfld.long 0x00 31. " SPI751_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI751_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI750_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI750_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI749_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI749_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI748_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI748_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI747_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI747_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI746_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI746_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI745_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI745_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI744_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI744_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI743_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI743_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI742_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI742_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI741_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI741_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI740_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI740_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI739_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI739_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI738_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI738_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI737_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI737_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI736_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI736_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xb8)++0x03
hide.long 0x0 "GICD_ICLAR46,Interrupt Class Register 46"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=23.)
group.long (0xE000+0xbc)++0x03
line.long 0x0 "GICD_ICLAR47,Interrupt Class Register 47"
bitfld.long 0x00 31. " SPI767_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI767_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI766_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI766_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI765_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI765_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI764_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI764_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI763_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI763_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI762_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI762_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI761_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI761_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI760_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI760_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI759_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI759_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI758_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI758_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI757_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI757_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI756_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI756_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI755_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI755_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI754_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI754_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI753_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI753_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI752_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI752_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xbc)++0x03
hide.long 0x0 "GICD_ICLAR47,Interrupt Class Register 47"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=24.)
group.long (0xE000+0xc0)++0x03
line.long 0x0 "GICD_ICLAR48,Interrupt Class Register 48"
bitfld.long 0x00 31. " SPI783_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI783_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI782_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI782_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI781_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI781_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI780_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI780_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI779_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI779_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI778_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI778_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI777_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI777_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI776_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI776_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI775_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI775_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI774_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI774_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI773_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI773_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI772_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI772_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI771_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI771_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI770_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI770_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI769_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI769_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI768_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI768_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xc0)++0x03
hide.long 0x0 "GICD_ICLAR48,Interrupt Class Register 48"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=24.)
group.long (0xE000+0xc4)++0x03
line.long 0x0 "GICD_ICLAR49,Interrupt Class Register 49"
bitfld.long 0x00 31. " SPI799_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI799_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI798_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI798_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI797_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI797_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI796_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI796_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI795_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI795_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI794_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI794_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI793_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI793_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI792_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI792_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI791_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI791_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI790_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI790_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI789_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI789_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI788_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI788_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI787_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI787_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI786_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI786_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI785_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI785_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI784_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI784_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xc4)++0x03
hide.long 0x0 "GICD_ICLAR49,Interrupt Class Register 49"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=25.)
group.long (0xE000+0xc8)++0x03
line.long 0x0 "GICD_ICLAR50,Interrupt Class Register 50"
bitfld.long 0x00 31. " SPI815_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI815_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI814_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI814_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI813_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI813_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI812_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI812_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI811_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI811_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI810_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI810_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI809_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI809_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI808_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI808_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI807_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI807_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI806_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI806_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI805_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI805_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI804_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI804_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI803_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI803_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI802_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI802_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI801_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI801_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI800_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI800_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xc8)++0x03
hide.long 0x0 "GICD_ICLAR50,Interrupt Class Register 50"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=25.)
group.long (0xE000+0xcc)++0x03
line.long 0x0 "GICD_ICLAR51,Interrupt Class Register 51"
bitfld.long 0x00 31. " SPI831_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI831_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI830_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI830_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI829_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI829_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI828_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI828_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI827_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI827_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI826_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI826_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI825_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI825_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI824_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI824_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI823_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI823_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI822_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI822_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI821_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI821_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI820_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI820_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI819_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI819_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI818_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI818_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI817_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI817_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI816_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI816_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xcc)++0x03
hide.long 0x0 "GICD_ICLAR51,Interrupt Class Register 51"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=26.)
group.long (0xE000+0xd0)++0x03
line.long 0x0 "GICD_ICLAR52,Interrupt Class Register 52"
bitfld.long 0x00 31. " SPI847_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI847_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI846_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI846_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI845_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI845_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI844_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI844_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI843_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI843_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI842_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI842_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI841_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI841_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI840_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI840_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI839_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI839_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI838_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI838_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI837_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI837_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI836_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI836_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI835_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI835_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI834_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI834_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI833_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI833_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI832_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI832_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xd0)++0x03
hide.long 0x0 "GICD_ICLAR52,Interrupt Class Register 52"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=26.)
group.long (0xE000+0xd4)++0x03
line.long 0x0 "GICD_ICLAR53,Interrupt Class Register 53"
bitfld.long 0x00 31. " SPI863_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI863_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI862_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI862_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI861_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI861_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI860_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI860_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI859_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI859_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI858_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI858_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI857_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI857_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI856_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI856_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI855_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI855_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI854_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI854_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI853_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI853_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI852_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI852_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI851_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI851_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI850_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI850_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI849_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI849_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI848_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI848_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xd4)++0x03
hide.long 0x0 "GICD_ICLAR53,Interrupt Class Register 53"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=27.)
group.long (0xE000+0xd8)++0x03
line.long 0x0 "GICD_ICLAR54,Interrupt Class Register 54"
bitfld.long 0x00 31. " SPI879_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI879_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI878_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI878_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI877_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI877_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI876_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI876_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI875_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI875_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI874_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI874_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI873_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI873_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI872_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI872_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI871_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI871_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI870_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI870_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI869_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI869_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI868_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI868_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI867_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI867_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI866_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI866_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI865_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI865_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI864_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI864_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xd8)++0x03
hide.long 0x0 "GICD_ICLAR54,Interrupt Class Register 54"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=27.)
group.long (0xE000+0xdc)++0x03
line.long 0x0 "GICD_ICLAR55,Interrupt Class Register 55"
bitfld.long 0x00 31. " SPI895_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI895_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI894_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI894_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI893_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI893_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI892_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI892_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI891_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI891_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI890_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI890_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI889_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI889_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI888_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI888_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI887_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI887_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI886_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI886_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI885_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI885_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI884_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI884_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI883_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI883_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI882_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI882_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI881_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI881_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI880_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI880_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xdc)++0x03
hide.long 0x0 "GICD_ICLAR55,Interrupt Class Register 55"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=28.)
group.long (0xE000+0xe0)++0x03
line.long 0x0 "GICD_ICLAR56,Interrupt Class Register 56"
bitfld.long 0x00 31. " SPI911_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI911_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI910_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI910_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI909_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI909_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI908_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI908_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI907_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI907_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI906_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI906_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI905_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI905_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI904_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI904_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI903_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI903_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI902_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI902_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI901_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI901_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI900_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI900_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI899_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI899_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI898_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI898_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI897_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI897_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI896_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI896_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xe0)++0x03
hide.long 0x0 "GICD_ICLAR56,Interrupt Class Register 56"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=28.)
group.long (0xE000+0xe4)++0x03
line.long 0x0 "GICD_ICLAR57,Interrupt Class Register 57"
bitfld.long 0x00 31. " SPI927_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI927_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI926_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI926_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI925_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI925_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI924_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI924_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI923_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI923_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI922_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI922_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI921_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI921_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI920_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI920_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI919_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI919_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI918_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI918_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI917_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI917_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI916_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI916_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI915_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI915_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI914_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI914_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI913_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI913_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI912_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI912_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xe4)++0x03
hide.long 0x0 "GICD_ICLAR57,Interrupt Class Register 57"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=29.)
group.long (0xE000+0xe8)++0x03
line.long 0x0 "GICD_ICLAR58,Interrupt Class Register 58"
bitfld.long 0x00 31. " SPI943_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI943_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI942_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI942_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI941_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI941_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI940_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI940_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI939_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI939_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI938_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI938_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI937_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI937_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI936_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI936_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI935_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI935_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI934_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI934_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI933_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI933_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI932_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI932_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI931_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI931_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI930_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI930_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI929_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI929_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI928_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI928_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xe8)++0x03
hide.long 0x0 "GICD_ICLAR58,Interrupt Class Register 58"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=29.)
group.long (0xE000+0xec)++0x03
line.long 0x0 "GICD_ICLAR59,Interrupt Class Register 59"
bitfld.long 0x00 31. " SPI959_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI959_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI958_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI958_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI957_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI957_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI956_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI956_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI955_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI955_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI954_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI954_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI953_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI953_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI952_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI952_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI951_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI951_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI950_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI950_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI949_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI949_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI948_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI948_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI947_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI947_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI946_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI946_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI945_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI945_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI944_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI944_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xec)++0x03
hide.long 0x0 "GICD_ICLAR59,Interrupt Class Register 59"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=30.)
group.long (0xE000+0xf0)++0x03
line.long 0x0 "GICD_ICLAR60,Interrupt Class Register 60"
bitfld.long 0x00 31. " SPI975_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI975_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI974_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI974_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI973_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI973_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI972_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI972_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI971_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI971_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI970_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI970_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI969_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI969_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI968_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI968_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI967_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI967_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI966_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI966_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI965_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI965_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI964_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI964_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI963_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI963_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI962_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI962_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI961_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI961_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI960_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI960_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xf0)++0x03
hide.long 0x0 "GICD_ICLAR60,Interrupt Class Register 60"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=30.)
group.long (0xE000+0xf4)++0x03
line.long 0x0 "GICD_ICLAR61,Interrupt Class Register 61"
bitfld.long 0x00 31. " SPI991_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 30. "    SPI991_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 29. "    SPI990_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 28. "    SPI990_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 27. " SPI989_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 26. "    SPI989_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 25. "    SPI988_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 24. "    SPI988_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 23. " SPI987_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 22. "    SPI987_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 21. "    SPI986_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 20. "    SPI986_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 19. " SPI985_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 18. "    SPI985_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 17. "    SPI984_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 16. "    SPI984_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 15. " SPI983_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 14. "    SPI983_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 13. "    SPI982_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 12. "    SPI982_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 11. " SPI981_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 10. "    SPI981_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 9. "    SPI980_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 8. "    SPI980_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 7. " SPI979_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 6. "    SPI979_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 5. "    SPI978_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 4. "    SPI978_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
textline "                               "
bitfld.long 0x00 3. " SPI977_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 2. "    SPI977_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
bitfld.long 0x00 1. "    SPI976_CLASS1  ,Controls whether the 1 of N SPI can target a core that is assigned to class 1" "0,1"
bitfld.long 0x00 0. "    SPI976_CLASS0  ,Controls whether the 1 of N SPI can target a core that is assigned to class 0" "0,1"
else
hgroup.long (0xE000+0xf4)++0x03
hide.long 0x0 "GICD_ICLAR61,Interrupt Class Register 61"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
tree.end
tree "Interrupt Error Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=1.)
group.long (0xE100+0x4)++0x03
line.long 0x0 "GICD_IERRR1,Interrupt Error Register 1"
bitfld.long 0x00 31. " SPI049_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI048_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI047_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI046_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI047_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI046_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI045_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI044_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI045_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI044_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI043_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI042_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI043_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI042_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI041_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI040_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI041_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI040_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI039_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI038_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI039_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI038_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI037_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI036_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI037_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI036_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI035_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI034_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI035_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI034_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI033_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI032_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x4)++0x03
hide.long 0x0 "GICD_IERRR1,Interrupt Error Register 1"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=2.)
group.long (0xE100+0x8)++0x03
line.long 0x0 "GICD_IERRR2,Interrupt Error Register 2"
bitfld.long 0x00 31. " SPI081_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI080_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI079_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI078_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI079_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI078_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI077_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI076_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI077_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI076_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI075_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI074_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI075_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI074_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI073_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI072_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI073_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI072_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI071_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI070_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI071_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI070_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI069_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI068_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI069_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI068_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI067_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI066_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI067_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI066_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI065_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI064_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x8)++0x03
hide.long 0x0 "GICD_IERRR2,Interrupt Error Register 2"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=3.)
group.long (0xE100+0xc)++0x03
line.long 0x0 "GICD_IERRR3,Interrupt Error Register 3"
bitfld.long 0x00 31. " SPI113_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI112_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI111_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI110_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI111_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI110_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI109_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI108_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI109_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI108_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI107_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI106_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI107_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI106_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI105_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI104_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI105_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI104_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI103_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI102_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI103_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI102_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI101_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI100_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI101_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI100_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI099_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI098_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI099_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI098_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI097_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI096_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0xc)++0x03
hide.long 0x0 "GICD_IERRR3,Interrupt Error Register 3"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=4.)
group.long (0xE100+0x10)++0x03
line.long 0x0 "GICD_IERRR4,Interrupt Error Register 4"
bitfld.long 0x00 31. " SPI145_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI144_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI143_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI142_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI143_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI142_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI141_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI140_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI141_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI140_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI139_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI138_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI139_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI138_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI137_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI136_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI137_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI136_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI135_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI134_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI135_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI134_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI133_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI132_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI133_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI132_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI131_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI130_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI131_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI130_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI129_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI128_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x10)++0x03
hide.long 0x0 "GICD_IERRR4,Interrupt Error Register 4"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=5.)
group.long (0xE100+0x14)++0x03
line.long 0x0 "GICD_IERRR5,Interrupt Error Register 5"
bitfld.long 0x00 31. " SPI177_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI176_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI175_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI174_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI175_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI174_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI173_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI172_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI173_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI172_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI171_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI170_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI171_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI170_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI169_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI168_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI169_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI168_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI167_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI166_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI167_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI166_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI165_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI164_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI165_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI164_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI163_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI162_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI163_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI162_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI161_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI160_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x14)++0x03
hide.long 0x0 "GICD_IERRR5,Interrupt Error Register 5"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=6.)
group.long (0xE100+0x18)++0x03
line.long 0x0 "GICD_IERRR6,Interrupt Error Register 6"
bitfld.long 0x00 31. " SPI209_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI208_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI207_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI206_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI207_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI206_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI205_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI204_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI205_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI204_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI203_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI202_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI203_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI202_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI201_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI200_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI201_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI200_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI199_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI198_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI199_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI198_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI197_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI196_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI197_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI196_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI195_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI194_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI195_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI194_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI193_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI192_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x18)++0x03
hide.long 0x0 "GICD_IERRR6,Interrupt Error Register 6"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=7.)
group.long (0xE100+0x1c)++0x03
line.long 0x0 "GICD_IERRR7,Interrupt Error Register 7"
bitfld.long 0x00 31. " SPI241_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI240_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI239_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI238_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI239_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI238_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI237_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI236_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI237_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI236_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI235_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI234_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI235_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI234_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI233_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI232_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI233_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI232_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI231_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI230_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI231_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI230_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI229_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI228_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI229_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI228_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI227_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI226_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI227_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI226_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI225_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI224_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x1c)++0x03
hide.long 0x0 "GICD_IERRR7,Interrupt Error Register 7"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=8.)
group.long (0xE100+0x20)++0x03
line.long 0x0 "GICD_IERRR8,Interrupt Error Register 8"
bitfld.long 0x00 31. " SPI273_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI272_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI271_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI270_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI271_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI270_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI269_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI268_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI269_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI268_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI267_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI266_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI267_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI266_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI265_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI264_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI265_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI264_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI263_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI262_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI263_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI262_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI261_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI260_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI261_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI260_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI259_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI258_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI259_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI258_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI257_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI256_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x20)++0x03
hide.long 0x0 "GICD_IERRR8,Interrupt Error Register 8"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=9.)
group.long (0xE100+0x24)++0x03
line.long 0x0 "GICD_IERRR9,Interrupt Error Register 9"
bitfld.long 0x00 31. " SPI305_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI304_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI303_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI302_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI303_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI302_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI301_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI300_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI301_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI300_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI299_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI298_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI299_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI298_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI297_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI296_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI297_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI296_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI295_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI294_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI295_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI294_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI293_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI292_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI293_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI292_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI291_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI290_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI291_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI290_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI289_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI288_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x24)++0x03
hide.long 0x0 "GICD_IERRR9,Interrupt Error Register 9"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=10.)
group.long (0xE100+0x28)++0x03
line.long 0x0 "GICD_IERRR10,Interrupt Error Register 10"
bitfld.long 0x00 31. " SPI337_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI336_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI335_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI334_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI335_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI334_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI333_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI332_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI333_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI332_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI331_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI330_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI331_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI330_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI329_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI328_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI329_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI328_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI327_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI326_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI327_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI326_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI325_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI324_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI325_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI324_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI323_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI322_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI323_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI322_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI321_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI320_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x28)++0x03
hide.long 0x0 "GICD_IERRR10,Interrupt Error Register 10"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=11.)
group.long (0xE100+0x2c)++0x03
line.long 0x0 "GICD_IERRR11,Interrupt Error Register 11"
bitfld.long 0x00 31. " SPI369_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI368_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI367_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI366_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI367_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI366_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI365_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI364_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI365_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI364_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI363_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI362_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI363_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI362_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI361_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI360_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI361_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI360_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI359_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI358_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI359_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI358_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI357_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI356_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI357_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI356_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI355_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI354_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI355_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI354_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI353_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI352_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x2c)++0x03
hide.long 0x0 "GICD_IERRR11,Interrupt Error Register 11"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=12.)
group.long (0xE100+0x30)++0x03
line.long 0x0 "GICD_IERRR12,Interrupt Error Register 12"
bitfld.long 0x00 31. " SPI401_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI400_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI399_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI398_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI399_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI398_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI397_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI396_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI397_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI396_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI395_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI394_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI395_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI394_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI393_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI392_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI393_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI392_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI391_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI390_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI391_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI390_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI389_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI388_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI389_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI388_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI387_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI386_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI387_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI386_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI385_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI384_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x30)++0x03
hide.long 0x0 "GICD_IERRR12,Interrupt Error Register 12"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=13.)
group.long (0xE100+0x34)++0x03
line.long 0x0 "GICD_IERRR13,Interrupt Error Register 13"
bitfld.long 0x00 31. " SPI433_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI432_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI431_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI430_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI431_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI430_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI429_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI428_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI429_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI428_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI427_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI426_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI427_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI426_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI425_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI424_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI425_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI424_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI423_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI422_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI423_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI422_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI421_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI420_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI421_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI420_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI419_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI418_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI419_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI418_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI417_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI416_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x34)++0x03
hide.long 0x0 "GICD_IERRR13,Interrupt Error Register 13"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=14.)
group.long (0xE100+0x38)++0x03
line.long 0x0 "GICD_IERRR14,Interrupt Error Register 14"
bitfld.long 0x00 31. " SPI465_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI464_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI463_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI462_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI463_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI462_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI461_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI460_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI461_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI460_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI459_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI458_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI459_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI458_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI457_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI456_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI457_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI456_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI455_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI454_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI455_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI454_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI453_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI452_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI453_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI452_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI451_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI450_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI451_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI450_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI449_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI448_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x38)++0x03
hide.long 0x0 "GICD_IERRR14,Interrupt Error Register 14"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=15.)
group.long (0xE100+0x3c)++0x03
line.long 0x0 "GICD_IERRR15,Interrupt Error Register 15"
bitfld.long 0x00 31. " SPI497_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI496_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI495_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI494_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI495_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI494_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI493_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI492_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI493_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI492_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI491_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI490_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI491_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI490_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI489_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI488_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI489_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI488_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI487_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI486_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI487_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI486_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI485_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI484_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI485_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI484_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI483_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI482_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI483_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI482_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI481_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI480_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x3c)++0x03
hide.long 0x0 "GICD_IERRR15,Interrupt Error Register 15"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=16.)
group.long (0xE100+0x40)++0x03
line.long 0x0 "GICD_IERRR16,Interrupt Error Register 16"
bitfld.long 0x00 31. " SPI529_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI528_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI527_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI526_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI527_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI526_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI525_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI524_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI525_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI524_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI523_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI522_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI523_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI522_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI521_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI520_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI521_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI520_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI519_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI518_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI519_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI518_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI517_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI516_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI517_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI516_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI515_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI514_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI515_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI514_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI513_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI512_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x40)++0x03
hide.long 0x0 "GICD_IERRR16,Interrupt Error Register 16"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=17.)
group.long (0xE100+0x44)++0x03
line.long 0x0 "GICD_IERRR17,Interrupt Error Register 17"
bitfld.long 0x00 31. " SPI561_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI560_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI559_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI558_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI559_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI558_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI557_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI556_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI557_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI556_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI555_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI554_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI555_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI554_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI553_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI552_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI553_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI552_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI551_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI550_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI551_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI550_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI549_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI548_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI549_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI548_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI547_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI546_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI547_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI546_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI545_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI544_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x44)++0x03
hide.long 0x0 "GICD_IERRR17,Interrupt Error Register 17"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=18.)
group.long (0xE100+0x48)++0x03
line.long 0x0 "GICD_IERRR18,Interrupt Error Register 18"
bitfld.long 0x00 31. " SPI593_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI592_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI591_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI590_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI591_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI590_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI589_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI588_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI589_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI588_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI587_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI586_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI587_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI586_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI585_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI584_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI585_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI584_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI583_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI582_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI583_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI582_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI581_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI580_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI581_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI580_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI579_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI578_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI579_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI578_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI577_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI576_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x48)++0x03
hide.long 0x0 "GICD_IERRR18,Interrupt Error Register 18"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=19.)
group.long (0xE100+0x4c)++0x03
line.long 0x0 "GICD_IERRR19,Interrupt Error Register 19"
bitfld.long 0x00 31. " SPI625_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI624_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI623_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI622_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI623_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI622_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI621_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI620_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI621_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI620_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI619_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI618_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI619_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI618_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI617_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI616_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI617_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI616_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI615_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI614_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI615_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI614_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI613_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI612_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI613_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI612_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI611_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI610_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI611_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI610_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI609_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI608_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x4c)++0x03
hide.long 0x0 "GICD_IERRR19,Interrupt Error Register 19"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=20.)
group.long (0xE100+0x50)++0x03
line.long 0x0 "GICD_IERRR20,Interrupt Error Register 20"
bitfld.long 0x00 31. " SPI657_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI656_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI655_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI654_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI655_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI654_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI653_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI652_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI653_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI652_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI651_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI650_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI651_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI650_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI649_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI648_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI649_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI648_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI647_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI646_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI647_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI646_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI645_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI644_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI645_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI644_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI643_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI642_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI643_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI642_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI641_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI640_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x50)++0x03
hide.long 0x0 "GICD_IERRR20,Interrupt Error Register 20"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=21.)
group.long (0xE100+0x54)++0x03
line.long 0x0 "GICD_IERRR21,Interrupt Error Register 21"
bitfld.long 0x00 31. " SPI689_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI688_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI687_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI686_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI687_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI686_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI685_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI684_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI685_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI684_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI683_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI682_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI683_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI682_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI681_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI680_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI681_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI680_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI679_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI678_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI679_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI678_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI677_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI676_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI677_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI676_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI675_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI674_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI675_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI674_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI673_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI672_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x54)++0x03
hide.long 0x0 "GICD_IERRR21,Interrupt Error Register 21"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=22.)
group.long (0xE100+0x58)++0x03
line.long 0x0 "GICD_IERRR22,Interrupt Error Register 22"
bitfld.long 0x00 31. " SPI721_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI720_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI719_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI718_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI719_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI718_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI717_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI716_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI717_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI716_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI715_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI714_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI715_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI714_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI713_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI712_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI713_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI712_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI711_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI710_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI711_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI710_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI709_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI708_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI709_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI708_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI707_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI706_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI707_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI706_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI705_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI704_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x58)++0x03
hide.long 0x0 "GICD_IERRR22,Interrupt Error Register 22"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=23.)
group.long (0xE100+0x5c)++0x03
line.long 0x0 "GICD_IERRR23,Interrupt Error Register 23"
bitfld.long 0x00 31. " SPI753_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI752_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI751_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI750_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI751_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI750_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI749_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI748_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI749_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI748_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI747_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI746_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI747_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI746_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI745_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI744_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI745_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI744_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI743_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI742_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI743_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI742_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI741_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI740_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI741_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI740_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI739_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI738_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI739_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI738_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI737_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI736_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x5c)++0x03
hide.long 0x0 "GICD_IERRR23,Interrupt Error Register 23"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=24.)
group.long (0xE100+0x60)++0x03
line.long 0x0 "GICD_IERRR24,Interrupt Error Register 24"
bitfld.long 0x00 31. " SPI785_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI784_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI783_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI782_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI783_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI782_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI781_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI780_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI781_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI780_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI779_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI778_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI779_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI778_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI777_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI776_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI777_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI776_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI775_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI774_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI775_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI774_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI773_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI772_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI773_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI772_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI771_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI770_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI771_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI770_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI769_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI768_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x60)++0x03
hide.long 0x0 "GICD_IERRR24,Interrupt Error Register 24"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=25.)
group.long (0xE100+0x64)++0x03
line.long 0x0 "GICD_IERRR25,Interrupt Error Register 25"
bitfld.long 0x00 31. " SPI817_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI816_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI815_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI814_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI815_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI814_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI813_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI812_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI813_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI812_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI811_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI810_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI811_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI810_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI809_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI808_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI809_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI808_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI807_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI806_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI807_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI806_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI805_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI804_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI805_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI804_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI803_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI802_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI803_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI802_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI801_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI800_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x64)++0x03
hide.long 0x0 "GICD_IERRR25,Interrupt Error Register 25"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=26.)
group.long (0xE100+0x68)++0x03
line.long 0x0 "GICD_IERRR26,Interrupt Error Register 26"
bitfld.long 0x00 31. " SPI849_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI848_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI847_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI846_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI847_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI846_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI845_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI844_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI845_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI844_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI843_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI842_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI843_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI842_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI841_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI840_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI841_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI840_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI839_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI838_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI839_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI838_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI837_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI836_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI837_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI836_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI835_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI834_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI835_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI834_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI833_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI832_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x68)++0x03
hide.long 0x0 "GICD_IERRR26,Interrupt Error Register 26"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=27.)
group.long (0xE100+0x6c)++0x03
line.long 0x0 "GICD_IERRR27,Interrupt Error Register 27"
bitfld.long 0x00 31. " SPI881_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI880_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI879_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI878_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI879_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI878_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI877_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI876_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI877_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI876_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI875_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI874_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI875_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI874_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI873_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI872_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI873_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI872_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI871_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI870_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI871_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI870_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI869_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI868_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI869_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI868_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI867_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI866_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI867_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI866_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI865_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI864_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x6c)++0x03
hide.long 0x0 "GICD_IERRR27,Interrupt Error Register 27"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=28.)
group.long (0xE100+0x70)++0x03
line.long 0x0 "GICD_IERRR28,Interrupt Error Register 28"
bitfld.long 0x00 31. " SPI913_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI912_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI911_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI910_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI911_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI910_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI909_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI908_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI909_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI908_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI907_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI906_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI907_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI906_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI905_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI904_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI905_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI904_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI903_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI902_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI903_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI902_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI901_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI900_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI901_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI900_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI899_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI898_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI899_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI898_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI897_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI896_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x70)++0x03
hide.long 0x0 "GICD_IERRR28,Interrupt Error Register 28"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=29.)
group.long (0xE100+0x74)++0x03
line.long 0x0 "GICD_IERRR29,Interrupt Error Register 29"
bitfld.long 0x00 31. " SPI945_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI944_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI943_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI942_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI943_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI942_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI941_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI940_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI941_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI940_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI939_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI938_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI939_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI938_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI937_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI936_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI937_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI936_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI935_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI934_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI935_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI934_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI933_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI932_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI933_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI932_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI931_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI930_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI931_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI930_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI929_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI928_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x74)++0x03
hide.long 0x0 "GICD_IERRR29,Interrupt Error Register 29"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x0000001F)>=30.)
group.long (0xE100+0x78)++0x03
line.long 0x0 "GICD_IERRR30,Interrupt Error Register 30"
bitfld.long 0x00 31. " SPI977_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 30. "    SPI976_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 29. "    SPI975_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 28. "    SPI974_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 27. " SPI975_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 26. "    SPI974_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 25. "    SPI973_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 24. "    SPI972_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 23. " SPI973_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 22. "    SPI972_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 21. "    SPI971_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 20. "    SPI970_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 19. " SPI971_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 18. "    SPI970_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 17. "    SPI969_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 16. "    SPI968_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 15. " SPI969_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 14. "    SPI968_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 13. "    SPI967_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 12. "    SPI966_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 11. " SPI967_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 10. "    SPI966_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 9. "    SPI965_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 8. "    SPI964_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 7. " SPI965_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 6. "    SPI964_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 5. "    SPI963_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 4. "    SPI962_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
textline "                               "
bitfld.long 0x00 3. " SPI963_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 2. "    SPI962_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 1. "    SPI961_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
bitfld.long 0x00 0. "    SPI960_STATUS  ,Indicates whether a SPI is in an error state. 0 = The SPI is not in an error state and programming is valid. 1 = The SPI is in an error state and programming is not valid." "OK,ERR"
else
hgroup.long (0xE100+0x78)++0x03
hide.long 0x0 "GICD_IERRR30,Interrupt Error Register 30"
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
textline "                               "
endif
tree.end
width 14.
tree "Peripheral/Component ID Registers"
rgroup.quad 0xF000++0x07
line.quad 0x00 "GICD_CFGID,Configuration ID Register"
bitfld.quad 0x00 44.--47. "   AFF3    ,Returns the Affinity3 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 40.--43. "               AFF2  ,Returns the Affinity2 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 36.--39. "             AFF1  ,Returns the Affinity1 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
bitfld.quad 0x00 32.--35. "   AFF0    ,Returns the Affinity0 bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 15.--20. "               SPIS  ,SPI Groups" "0,1,2,3,4,5,6,7,8,9,10,%d..."
bitfld.quad 0x00 14. "             AFSL  ,Chip affinity selection level" "0,1"
textline "                               "
bitfld.quad 0x00 13. "   DLPI    ,Direct LPI registers supported" "Not Supported,Supported"
bitfld.quad 0x00 12. "    LPIS  ,LPI supported" "Not Supported,Supported"
bitfld.quad 0x00 4.--7. "  SNUM  ,Chip number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                               "
bitfld.quad 0x00 0. "   SO      ,Chip offline" "OFFLINE,ONLINE"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICD_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "           PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICD_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. "           DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "               PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICD_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. "           ARCHREV ,Identifies the version of the GIC architecture with which the GIC-600 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "         JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Not Used,Used"
bitfld.long 0x00 0.--2. "      DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICD_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. "           REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "               CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICD_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. "           SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "               DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICD_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICD_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICD_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICD_CIDR0,Component ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "           FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICD_CIDR1,Component ID1 Register"
hexmask.long.byte 0x00 0.--7. 1. "           FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICD_CIDR2,Component ID2 Register"
hexmask.long.byte 0x00 0.--7. 1. "           FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICD_CIDR3,Component ID3 Register"
hexmask.long.byte 0x00 0.--7. 1. "           FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
width 0x0B
base (COMP.BASE("GICD",-1.)+0x20000)
AUTOINDENT.ON CENTER TREE
tree "Trace and Debug"
tree "Error Record 0: Software error in GICD programming"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((0.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR0FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (0.==0.)
group.quad ((0.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((0.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((0.&0x1)==0x0)
group.quad ((0.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((0.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((0.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((0.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+0.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((0.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((0.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register"
else
group.quad ((0.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((0.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR0MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((0.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR0FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((0.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((0.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((0.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register"
hgroup.quad ((0.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR0MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((0.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR0FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (0.==0.)
group.quad ((0.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((0.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((0.&0x1)==0x0)
group.quad ((0.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((0.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((0.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((0.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+0.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((0.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((0.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register"
else
group.quad ((0.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((0.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR0MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((0.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR0FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((0.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR0CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((0.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR0STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((0.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR0ADDR,Error Record Address Register"
hgroup.quad ((0.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR0MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 1: Correctable SPI RAM errors"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((1.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR1FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (1.==0.)
group.quad ((1.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((1.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((1.&0x1)==0x0)
group.quad ((1.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((1.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((1.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((1.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+1.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((1.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((1.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register"
else
group.quad ((1.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((1.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR1MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((1.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR1FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((1.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((1.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((1.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register"
hgroup.quad ((1.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR1MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((1.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR1FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (1.==0.)
group.quad ((1.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((1.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((1.&0x1)==0x0)
group.quad ((1.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((1.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((1.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((1.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+1.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((1.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((1.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register"
else
group.quad ((1.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((1.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR1MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((1.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR1FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((1.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR1CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((1.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR1STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((1.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR1ADDR,Error Record Address Register"
hgroup.quad ((1.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR1MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 2: Uncorrectable SPI RAM errors"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((2.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR2FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (2.==0.)
group.quad ((2.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((2.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((2.&0x1)==0x0)
group.quad ((2.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((2.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((2.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((2.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+2.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((2.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((2.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register"
else
group.quad ((2.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((2.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR2MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((2.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR2FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((2.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((2.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((2.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register"
hgroup.quad ((2.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR2MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((2.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR2FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (2.==0.)
group.quad ((2.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((2.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((2.&0x1)==0x0)
group.quad ((2.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((2.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((2.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((2.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+2.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((2.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((2.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register"
else
group.quad ((2.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((2.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR2MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((2.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR2FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((2.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR2CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((2.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR2STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((2.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR2ADDR,Error Record Address Register"
hgroup.quad ((2.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR2MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 3: Correctable SGI RAM errors"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((3.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR3FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (3.==0.)
group.quad ((3.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((3.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((3.&0x1)==0x0)
group.quad ((3.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((3.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((3.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((3.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+3.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((3.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((3.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register"
else
group.quad ((3.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((3.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR3MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((3.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR3FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((3.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((3.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((3.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register"
hgroup.quad ((3.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR3MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((3.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR3FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (3.==0.)
group.quad ((3.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((3.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((3.&0x1)==0x0)
group.quad ((3.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((3.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((3.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((3.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+3.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((3.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((3.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register"
else
group.quad ((3.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((3.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR3MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((3.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR3FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((3.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR3CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((3.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR3STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((3.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR3ADDR,Error Record Address Register"
hgroup.quad ((3.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR3MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 4: Uncorrectable SGI RAM errors"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((4.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR4FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (4.==0.)
group.quad ((4.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((4.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((4.&0x1)==0x0)
group.quad ((4.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((4.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((4.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((4.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+4.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((4.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((4.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register"
else
group.quad ((4.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((4.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR4MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((4.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR4FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((4.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((4.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((4.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register"
hgroup.quad ((4.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR4MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((4.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR4FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (4.==0.)
group.quad ((4.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((4.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((4.&0x1)==0x0)
group.quad ((4.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((4.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((4.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((4.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+4.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((4.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((4.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register"
else
group.quad ((4.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((4.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR4MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((4.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR4FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((4.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR4CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((4.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR4STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((4.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR4ADDR,Error Record Address Register"
hgroup.quad ((4.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR4MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 5: Correctable TGT cache errors"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((5.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR5FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (5.==0.)
group.quad ((5.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((5.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((5.&0x1)==0x0)
group.quad ((5.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((5.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((5.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((5.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+5.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((5.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((5.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register"
else
group.quad ((5.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((5.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR5MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((5.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR5FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((5.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((5.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((5.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register"
hgroup.quad ((5.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR5MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((5.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR5FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (5.==0.)
group.quad ((5.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((5.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((5.&0x1)==0x0)
group.quad ((5.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((5.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((5.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((5.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+5.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((5.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((5.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register"
else
group.quad ((5.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((5.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR5MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((5.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR5FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((5.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR5CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((5.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR5STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((5.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR5ADDR,Error Record Address Register"
hgroup.quad ((5.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR5MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 6: Uncorrectable TGT cache errors"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((6.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR6FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (6.==0.)
group.quad ((6.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((6.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((6.&0x1)==0x0)
group.quad ((6.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((6.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((6.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((6.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+6.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((6.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((6.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register"
else
group.quad ((6.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((6.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR6MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((6.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR6FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((6.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((6.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((6.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register"
hgroup.quad ((6.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR6MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((6.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR6FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (6.==0.)
group.quad ((6.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((6.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((6.&0x1)==0x0)
group.quad ((6.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((6.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((6.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((6.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+6.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((6.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((6.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register"
else
group.quad ((6.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((6.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR6MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((6.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR6FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((6.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR6CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((6.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR6STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((6.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR6ADDR,Error Record Address Register"
hgroup.quad ((6.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR6MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 7: Correctable PPI RAM errors"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((7.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR7FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (7.==0.)
group.quad ((7.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((7.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((7.&0x1)==0x0)
group.quad ((7.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((7.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((7.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((7.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+7.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((7.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((7.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register"
else
group.quad ((7.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((7.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR7MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((7.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR7FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((7.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((7.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((7.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register"
hgroup.quad ((7.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR7MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((7.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR7FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (7.==0.)
group.quad ((7.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((7.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((7.&0x1)==0x0)
group.quad ((7.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((7.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((7.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((7.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+7.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((7.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((7.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register"
else
group.quad ((7.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((7.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR7MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((7.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR7FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((7.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR7CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((7.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR7STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((7.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR7ADDR,Error Record Address Register"
hgroup.quad ((7.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR7MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 8: Uncorrectable PPI RAM errors"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((8.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR8FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (8.==0.)
group.quad ((8.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((8.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((8.&0x1)==0x0)
group.quad ((8.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((8.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((8.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((8.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+8.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((8.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((8.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register"
else
group.quad ((8.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((8.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR8MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((8.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR8FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((8.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((8.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((8.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register"
hgroup.quad ((8.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR8MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((8.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR8FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (8.==0.)
group.quad ((8.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((8.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((8.&0x1)==0x0)
group.quad ((8.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((8.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((8.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((8.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+8.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((8.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((8.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register"
else
group.quad ((8.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((8.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR8MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((8.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR8FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((8.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR8CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((8.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR8STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((8.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR8ADDR,Error Record Address Register"
hgroup.quad ((8.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR8MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 9: Correctable LPI RAM errors"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((9.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR9FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (9.==0.)
group.quad ((9.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((9.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((9.&0x1)==0x0)
group.quad ((9.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((9.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((9.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((9.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+9.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((9.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((9.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register"
else
group.quad ((9.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((9.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR9MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((9.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR9FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((9.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((9.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((9.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register"
hgroup.quad ((9.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR9MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((9.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR9FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (9.==0.)
group.quad ((9.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((9.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((9.&0x1)==0x0)
group.quad ((9.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((9.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((9.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((9.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+9.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((9.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((9.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register"
else
group.quad ((9.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((9.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR9MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((9.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR9FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((9.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR9CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((9.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR9STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((9.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR9ADDR,Error Record Address Register"
hgroup.quad ((9.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR9MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 10: Uncorrectable LPI RAM errors"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((10.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR10FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (10.==0.)
group.quad ((10.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((10.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((10.&0x1)==0x0)
group.quad ((10.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((10.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((10.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((10.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+10.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((10.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((10.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register"
else
group.quad ((10.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((10.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR10MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((10.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR10FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((10.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((10.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((10.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register"
hgroup.quad ((10.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR10MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((10.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR10FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (10.==0.)
group.quad ((10.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((10.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((10.&0x1)==0x0)
group.quad ((10.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((10.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((10.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((10.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+10.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((10.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((10.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register"
else
group.quad ((10.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((10.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR10MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((10.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR10FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((10.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR10CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((10.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR10STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((10.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR10ADDR,Error Record Address Register"
hgroup.quad ((10.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR10MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 11: Correctable error from ITS RAM"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((11.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR11FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (11.==0.)
group.quad ((11.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((11.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((11.&0x1)==0x0)
group.quad ((11.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((11.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((11.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((11.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+11.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((11.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((11.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register"
else
group.quad ((11.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((11.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR11MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((11.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR11FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((11.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((11.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((11.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register"
hgroup.quad ((11.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR11MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((11.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR11FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (11.==0.)
group.quad ((11.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((11.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((11.&0x1)==0x0)
group.quad ((11.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((11.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((11.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((11.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+11.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((11.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((11.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register"
else
group.quad ((11.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((11.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR11MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((11.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR11FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((11.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR11CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((11.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR11STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((11.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR11ADDR,Error Record Address Register"
hgroup.quad ((11.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR11MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 12: Uncorrectable error from ITS RAM"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((12.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR12FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (12.==0.)
group.quad ((12.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((12.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((12.&0x1)==0x0)
group.quad ((12.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((12.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((12.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((12.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+12.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((12.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((12.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register"
else
group.quad ((12.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((12.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR12MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((12.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR12FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((12.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((12.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((12.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register"
hgroup.quad ((12.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR12MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((12.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR12FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (12.==0.)
group.quad ((12.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((12.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((12.&0x1)==0x0)
group.quad ((12.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((12.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((12.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((12.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+12.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((12.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((12.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register"
else
group.quad ((12.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((12.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR12MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((12.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR12FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((12.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR12CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((12.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR12STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((12.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR12ADDR,Error Record Address Register"
hgroup.quad ((12.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR12MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Error Record 13: Software error in ITS"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
if 1==1
rgroup.quad ((13.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR13FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (13.==0.)
group.quad ((13.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((13.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((13.&0x1)==0x0)
group.quad ((13.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((13.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((13.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((13.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+13.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((13.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((13.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register"
else
group.quad ((13.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((13.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR13MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((13.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR13FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((13.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((13.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((13.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register"
hgroup.quad ((13.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR13MISC0,Error Record Miscellaneous Register 0"
endif
else
if 0==1
rgroup.quad ((13.*0x40)+0x000)++0x07
line.quad 0x00 "GICT_ERR13FR,Error Record Feature Register"
bitfld.quad 0x00 15. " RP   ,Repeat corrected error counter implemented." "0,1"
hexmask.quad.byte 0x00 12.--14. 1. "   CEC ,Corrected error count."
bitfld.quad 0x00 10.--11. "   CFI ,Corrected errors fault interrupt. Indicates if a fault handling interrupt for corrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  8.--9.  " UE ,Uncorrected error. Indicates if an in-band uncorrected error reporting feature is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  6.--7.  "  FI ,Fault handling interrupt for uncorrected errors. Indicates if a fault handling interrupt is implemented." "Not Implemented,?,Implemented,?"
bitfld.quad 0x00  4.--5.  "  UI ,Error recovery interrupt for uncorrected errors. Indicates if an error recovery interrupt for uncorrected errors is implemented." "Not Implemented,?,Implemented,?"
NEWLINE
bitfld.quad 0x00  2.--3.  " DE ,Error recovery interrupt for uncorrected errors. Indicates if deferring of errors support is supported." "Not Supported,?,?,?"
bitfld.quad 0x00  0.--1.  "  ED ,Uncorrected error reporting. Indicates if uncorrected error reporting is enabled." "Disabled,Enabled,?,?"
if (13.==0.)
group.quad ((13.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((13.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "           UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "   IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
elif ((13.&0x1)==0x0)
group.quad ((13.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
bitfld.quad 0x00  4. "   UE   ,Uncorrected error. Controls whether an external abort with transaction is send" "Not Send,Send"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Controls whether an fault handling interrupt generated on all uncorrectable errors or on none." "No Assert,Assert"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Controls whether an error recovery interrupt is generated on all uncorrectable errors or on none." "No Assert,Assert"
group.quad ((13.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 20.--21. "              UET   ," "?,UEO,?,UER"
hexmask.quad.byte 0x00  8.--15. 1. "  IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
else
group.quad ((13.*0x40)+0x008)++0x07
line.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register"
bitfld.quad 0x00 15. " RP   ,Controls whether an error response to a transition is reported." "Report,No Report"
bitfld.quad 0x00  8. "   CFI   ,Corrected errors fault interrupt.Controls whether a corrected error generates a fault handling interrupt." "No Assert,Assert"
NEWLINE
bitfld.quad 0x00  3. " FI   ,Fault handling interrupt. Should Be Zero (SBZ)." "0,1"
bitfld.quad 0x00  2. "   UI   ,Error recovery interrupt for uncorrected error. Should Be Zero (SBZ)." "0,1"
group.quad ((13.*0x40)+0x010)++0x07
line.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register"
bitfld.quad 0x00 31. " AV   ,Indicates if the GICT_ERR<n>ADDR address is valid, i.e. contains an address that is associated with the highest priority error that this record stores. Only present in record 0." "Not Valid,Valid"
bitfld.quad 0x00 30. "  V   ,Indicates if this  GICT_ERR<n>STATUS register is valid and one or more errors are recorded." "Not Valid,Valid"
bitfld.quad 0x00 29. "  UE   ,Uncorrectable error bit. Should Be Zero (SBZ) in Correctable Error (CE) records." "0,1"
NEWLINE
bitfld.quad 0x00 28. " ER   ,Indicates that at least one error has been reported over ACE-Lite." "0,1"
bitfld.quad 0x00 27. "  OF   ,Indicates that record has overflowed." "0,1"
bitfld.quad 0x00 26. "  MV   ,Indicates if the GICT miscellaneous GICT_ERR<n>MISC0 and GICT_ERR<n>MISC1 registers are valid." "Not Valid,Valid"
NEWLINE
bitfld.quad 0x00 24.--25. " CE   ,Indicates if an CE was recorded." "No Record,?,Record,?"
hexmask.quad.byte 0x00  8.--15. 1. "                    IERR ,Implementation defined error code. This field is RO if one value is specified. Returns the summary table information."
NEWLINE
hexmask.quad.byte 0x00  0.--7.  1. " SERR ,Architecturally-defined primary error code. This field is RO if one value is specified. Returns the summary table information."
endif
if ((per.q(((COMP.BASE("GICD",-1.)+0x20000)+13.*0x40)+0x010))&0x80000000)==0x80000000
rgroup.quad ((13.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
elif (((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0000)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0c00)||(((per.q(((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x010))&0xff00)==0x0d00)
hgroup.quad ((13.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register"
else
group.quad ((13.*0x40)+0x018)++0x07
line.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register"
bitfld.quad 0x00 63. " NS   ,Indicates if address is secure or non-secure." "Secure,Non-Secure"
hexmask.quad.quad 0x00 0.--47. 1. "  PADDR   ,The error address."
endif
group.quad ((13.*0x40)+0x020)++0x07
line.quad 0x00 "GICT_ERR13MISC0,Error Record Miscellaneous Register 0"
bitfld.quad 0x00 41. " RE   ,Rounding Error. The rounding error counter is under-reporting." "0,1"
bitfld.quad 0x00 40. "  OVERFLOW   ,Sticky overflow bit. If the corrected fault handling interrupt is enabled, then the GIC-600 generates a fault handling interrupt." "0,1"
hexmask.quad.word 0x00 32.--39. 1. "  COUNT   ,Corrected error count. Error counter is not 0 or is more than 134. Incremented for each corrected error that does not match the recorded syndrome."
NEWLINE
hexmask.quad.long 0x00  0.--31. 1. " DATA   ,Information associated with the error. See table in the TRM."
else
hgroup.quad ((13.*0x40)+0x000)++0x07
hide.quad 0x00 "GICT_ERR13FR,Error Record Feature Register"
NEWLINE
NEWLINE
hgroup.quad ((13.*0x40)+0x008)++0x07
hide.quad 0x00 "GICT_ERR13CTLR,Error Record Control Register"
NEWLINE
hgroup.quad ((13.*0x40)+0x010)++0x07
hide.quad 0x00 "GICT_ERR13STATUS,Error Record Primary Status Register"
NEWLINE
NEWLINE
NEWLINE
hgroup.quad ((13.*0x40)+0x018)++0x07
hide.quad 0x00 "GICT_ERR13ADDR,Error Record Address Register"
hgroup.quad ((13.*0x40)+0x020)++0x07
hide.quad 0x00 "GICT_ERR13MISC0,Error Record Miscellaneous Register 0"
endif
endif
tree.end
tree "Common Registers"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
group.quad ((10.*0x40)+0x028)++0x07
line.quad 0x00 "GICT_ERR10MISC1,Error Record Miscellaneous Register 1"
hexmask.quad.quad 0x00 0.--63. 1. " INFO ,Value represents either data that is written to the LPI RAM when an uncorrectable error is detected, or ITS software information for one of 13, or more, error records."
else
hgroup.quad (((COMP.BASE("GICD",-1.)+0x20000)*0x40)+0x028)++0x07
hide.quad 0x00 "GICT_ERR10MISC1,Error Record Miscellaneous Register 1"
endif
rgroup.quad 0xE000++0x07
line.quad 0x00 "GICT_ERRGSR,Group Status Register"
rgroup.long 0xFFBC++0x03
line.long 0x00 "GICT_ERRDEVARCH,Device Architecture register"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(((((per.l(COMP.BASE("GICD",-1.)+0xE08))&0x2)==0x0)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICD",-1.))))||(((per.l((COMP.BASE("GICD",-1.)+0xE08)))&0x2)==0x2)))
rgroup.long 0xFFC8++0x03
line.long 0x00 "GICT_ERRIDR,Error Record ID Register"
bitfld.long 0x00 0.--15. " NUM , Identifies the device configuration." "?,?,?,?,?,?,?,?,?,?,No LPI available,?,LPI available but no ITS,?,LPI available and 1*ITS,LPI available and 2*ITS,LPI available and 3*ITS,?..."
else
hgroup.long 0xFFC8++0x03
hide.long 0x00 "GICT_ERRIDR,Error Record ID Register"
endif
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICT_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICT_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICT_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-600 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICT_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICT_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICT_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICT_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICT_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICT_CIDR0,Component ID0 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICT_CIDR1,Component ID1 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICT_CIDR2,Component ID2 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICT_CIDR3,Component ID3 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
AUTOINDENT.OFF
base (COMP.BASE("GICD",-1.)+0x30000)
AUTOINDENT.ON CENTER TREE
tree "Performance Monitoring Unit"
group.long (0x000+0x0)++0x03
line.long 0x00 "GICP_EVCNTR0,Event Counter Register"
hexmask.long.long 0x00 0.--31. 1. " COUNT ,Counter value. If the counter is enabled, the counter value increments when an event matching GICP_EVTYPERn.EVENT occurs."
group.long (0x400+0x0)++0x03
line.long 0x00 "GICP_EVTYPER0,Event Type Configuration Register"
bitfld.long 0x00 31. " OVFCAP ,When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set." "0,1"
bitfld.long 0x00 16.--17. "  EVENTTYPE ,Event tracking type." "Count,Accumulate,Maximum,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "  EVENT ,Event identifier. All events reset to an UNKNOWN value. Registers corresponding to unimplemented counters are RES0. See table in TRM"
rgroup.long (0x600+0x0)++0x03
line.long 0x00 "GICP_SVR0,Shadow Value Registers"
hexmask.long.long 0x00 0.--31. 1. " COUNT,Captured counter value.This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn."
group.long (0xA00+0x0)++0x03
line.long 0x00 "GICP_FR0,Filter Registers"
bitfld.long 0x00 30.--31. " FILTERTYPE ,Filter Type." "Core,INTID,Chip/ITS,Reserved"
bitfld.long 0x00 29. "  FILTERENCODING ,Filter Encoding." "Range,Exact"
hexmask.long.byte 0x00 0.--15. 1. "  Filter ,If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this register is ignored."
NEWLINE
group.long (0x000+0x4)++0x03
line.long 0x00 "GICP_EVCNTR1,Event Counter Register"
hexmask.long.long 0x00 0.--31. 1. " COUNT ,Counter value. If the counter is enabled, the counter value increments when an event matching GICP_EVTYPERn.EVENT occurs."
group.long (0x400+0x4)++0x03
line.long 0x00 "GICP_EVTYPER1,Event Type Configuration Register"
bitfld.long 0x00 31. " OVFCAP ,When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set." "0,1"
bitfld.long 0x00 16.--17. "  EVENTTYPE ,Event tracking type." "Count,Accumulate,Maximum,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "  EVENT ,Event identifier. All events reset to an UNKNOWN value. Registers corresponding to unimplemented counters are RES0. See table in TRM"
rgroup.long (0x600+0x4)++0x03
line.long 0x00 "GICP_SVR1,Shadow Value Registers"
hexmask.long.long 0x00 0.--31. 1. " COUNT,Captured counter value.This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn."
group.long (0xA00+0x4)++0x03
line.long 0x00 "GICP_FR1,Filter Registers"
bitfld.long 0x00 30.--31. " FILTERTYPE ,Filter Type." "Core,INTID,Chip/ITS,Reserved"
bitfld.long 0x00 29. "  FILTERENCODING ,Filter Encoding." "Range,Exact"
hexmask.long.byte 0x00 0.--15. 1. "  Filter ,If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this register is ignored."
NEWLINE
group.long (0x000+0x8)++0x03
line.long 0x00 "GICP_EVCNTR2,Event Counter Register"
hexmask.long.long 0x00 0.--31. 1. " COUNT ,Counter value. If the counter is enabled, the counter value increments when an event matching GICP_EVTYPERn.EVENT occurs."
group.long (0x400+0x8)++0x03
line.long 0x00 "GICP_EVTYPER2,Event Type Configuration Register"
bitfld.long 0x00 31. " OVFCAP ,When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set." "0,1"
bitfld.long 0x00 16.--17. "  EVENTTYPE ,Event tracking type." "Count,Accumulate,Maximum,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "  EVENT ,Event identifier. All events reset to an UNKNOWN value. Registers corresponding to unimplemented counters are RES0. See table in TRM"
rgroup.long (0x600+0x8)++0x03
line.long 0x00 "GICP_SVR2,Shadow Value Registers"
hexmask.long.long 0x00 0.--31. 1. " COUNT,Captured counter value.This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn."
group.long (0xA00+0x8)++0x03
line.long 0x00 "GICP_FR2,Filter Registers"
bitfld.long 0x00 30.--31. " FILTERTYPE ,Filter Type." "Core,INTID,Chip/ITS,Reserved"
bitfld.long 0x00 29. "  FILTERENCODING ,Filter Encoding." "Range,Exact"
hexmask.long.byte 0x00 0.--15. 1. "  Filter ,If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this register is ignored."
NEWLINE
group.long (0x000+0xC)++0x03
line.long 0x00 "GICP_EVCNTR3,Event Counter Register"
hexmask.long.long 0x00 0.--31. 1. " COUNT ,Counter value. If the counter is enabled, the counter value increments when an event matching GICP_EVTYPERn.EVENT occurs."
group.long (0x400+0xC)++0x03
line.long 0x00 "GICP_EVTYPER3,Event Type Configuration Register"
bitfld.long 0x00 31. " OVFCAP ,When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set." "0,1"
bitfld.long 0x00 16.--17. "  EVENTTYPE ,Event tracking type." "Count,Accumulate,Maximum,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "  EVENT ,Event identifier. All events reset to an UNKNOWN value. Registers corresponding to unimplemented counters are RES0. See table in TRM"
rgroup.long (0x600+0xC)++0x03
line.long 0x00 "GICP_SVR3,Shadow Value Registers"
hexmask.long.long 0x00 0.--31. 1. " COUNT,Captured counter value.This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn."
group.long (0xA00+0xC)++0x03
line.long 0x00 "GICP_FR3,Filter Registers"
bitfld.long 0x00 30.--31. " FILTERTYPE ,Filter Type." "Core,INTID,Chip/ITS,Reserved"
bitfld.long 0x00 29. "  FILTERENCODING ,Filter Encoding." "Range,Exact"
hexmask.long.byte 0x00 0.--15. 1. "  Filter ,If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this register is ignored."
NEWLINE
group.long (0x000+0x10)++0x03
line.long 0x00 "GICP_EVCNTR4,Event Counter Register"
hexmask.long.long 0x00 0.--31. 1. " COUNT ,Counter value. If the counter is enabled, the counter value increments when an event matching GICP_EVTYPERn.EVENT occurs."
group.long (0x400+0x10)++0x03
line.long 0x00 "GICP_EVTYPER4,Event Type Configuration Register"
bitfld.long 0x00 31. " OVFCAP ,When set to 1, an overflow of counter n triggers a capture if GICP_CAPR.CAPTURE is set." "0,1"
bitfld.long 0x00 16.--17. "  EVENTTYPE ,Event tracking type." "Count,Accumulate,Maximum,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "  EVENT ,Event identifier. All events reset to an UNKNOWN value. Registers corresponding to unimplemented counters are RES0. See table in TRM"
rgroup.long (0x600+0x10)++0x03
line.long 0x00 "GICP_SVR4,Shadow Value Registers"
hexmask.long.long 0x00 0.--31. 1. " COUNT,Captured counter value.This field holds the captured counter values of the corresponding entry in GICP_EVCNTRn."
group.long (0xA00+0x10)++0x03
line.long 0x00 "GICP_FR4,Filter Registers"
bitfld.long 0x00 30.--31. " FILTERTYPE ,Filter Type." "Core,INTID,Chip/ITS,Reserved"
bitfld.long 0x00 29. "  FILTERENCODING ,Filter Encoding." "Range,Exact"
hexmask.long.byte 0x00 0.--15. 1. "  Filter ,If the corresponding GICP_EVTYPERn.EVENT indicates an event that cannot be filtered, then the value in this register is ignored."
NEWLINE
group.quad 0xC00++0x07
line.quad 0x00 "GICP_CNTENSET0,Counter Enable Set Register 0"
bitfld.quad 0x00 4. " CNTEN4  ,Counter disable. Writing 1 to a bit location sets the enable for the associated counter. Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register. Reads return the state of the counter enables." "0,1"
bitfld.quad 0x00 3. " CNTEN3  ,Counter disable. Writing 1 to a bit location sets the enable for the associated counter. Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register. Reads return the state of the counter enables." "0,1"
bitfld.quad 0x00 2. " CNTEN2  ,Counter disable. Writing 1 to a bit location sets the enable for the associated counter. Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register. Reads return the state of the counter enables." "0,1"
NEWLINE
bitfld.quad 0x00 1. " CNTEN1  ,Counter disable. Writing 1 to a bit location sets the enable for the associated counter. Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register. Reads return the state of the counter enables." "0,1"
bitfld.quad 0x00 0. " CNTEN0  ,Counter disable. Writing 1 to a bit location sets the enable for the associated counter. Writing 0 to a bit location has no effect. To disable a counter, use the GICP_CNTENCLR0 register. Reads return the state of the counter enables." "0,1"
group.quad 0xC20++0x07
line.quad 0x00 "GICP_INTENCLR0,Counter Enable Clear Register 0"
bitfld.quad 0x00 4. " CNTEN4  ,Counter disable. Writing 1 to a bit location clears the enable for the associated counter. Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register. Reads return the state of the counter enables." "0,1"
bitfld.quad 0x00 3. " CNTEN3  ,Counter disable. Writing 1 to a bit location clears the enable for the associated counter. Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register. Reads return the state of the counter enables." "0,1"
bitfld.quad 0x00 2. " CNTEN2  ,Counter disable. Writing 1 to a bit location clears the enable for the associated counter. Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register. Reads return the state of the counter enables." "0,1"
NEWLINE
bitfld.quad 0x00 1. " CNTEN1  ,Counter disable. Writing 1 to a bit location clears the enable for the associated counter. Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register. Reads return the state of the counter enables." "0,1"
bitfld.quad 0x00 0. " CNTEN0  ,Counter disable. Writing 1 to a bit location clears the enable for the associated counter. Writing 0 to a bit location has no effect. To enable a counter, use the GICP_CNTENSET0 register. Reads return the state of the counter enables." "0,1"
group.quad 0xC40++0x07
line.quad 0x00 "GICP_INTENSET0,Interrupt Contribution Enable Set Register 0"
bitfld.quad 0x00 4. " INTEN4  ,Interrupt enable. Writing 1 sets the interrupt enable for the associated counter. Writing 0 has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register. Reads return the state of the interrupt enables." "0,1"
bitfld.quad 0x00 3. "  INTEN3  ,Interrupt enable. Writing 1 sets the interrupt enable for the associated counter. Writing 0 has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register. Reads return the state of the interrupt enables." "0,1"
bitfld.quad 0x00 2. "  INTEN2  ,Interrupt enable. Writing 1 sets the interrupt enable for the associated counter. Writing 0 has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register. Reads return the state of the interrupt enables." "0,1"
NEWLINE
bitfld.quad 0x00 1. " INTEN1  ,Interrupt enable. Writing 1 sets the interrupt enable for the associated counter. Writing 0 has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register. Reads return the state of the interrupt enables." "0,1"
bitfld.quad 0x00 0. "  INTEN0  ,Interrupt enable. Writing 1 sets the interrupt enable for the associated counter. Writing 0 has no effect. To disable a counter interrupt enable, use the GICP_INTENCLR0 register. Reads return the state of the interrupt enables." "0,1"
group.quad 0xC60++0x07
line.quad 0x00 "GICP_INTENCLR0,Interrupt Contribution Enable Clear Register 0"
bitfld.quad 0x00 4. " INTEN4  ,Interrupt enable. Writing 1 clears the interrupt enable for the associated counter. Writing 0 has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register. Reads return the state of the interrupt enables." "0,1"
bitfld.quad 0x00 3. "  INTEN3  ,Interrupt enable. Writing 1 clears the interrupt enable for the associated counter. Writing 0 has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register. Reads return the state of the interrupt enables." "0,1"
bitfld.quad 0x00 2. "  INTEN2  ,Interrupt enable. Writing 1 clears the interrupt enable for the associated counter. Writing 0 has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register. Reads return the state of the interrupt enables." "0,1"
NEWLINE
bitfld.quad 0x00 1. " INTEN1  ,Interrupt enable. Writing 1 clears the interrupt enable for the associated counter. Writing 0 has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register. Reads return the state of the interrupt enables." "0,1"
bitfld.quad 0x00 0. "  INTEN0  ,Interrupt enable. Writing 1 clears the interrupt enable for the associated counter. Writing 0 has no effect. To enable a counter interrupt enable, use the GICP_INTENSET0 register. Reads return the state of the interrupt enables." "0,1"
group.quad 0xC80++0x07
line.quad 0x00 "GICP_OVSCLR0,Overflow Status Clear Register 0"
bitfld.quad 0x00 4. " OVS4  ,Overflow status. Writing 1 clears the overflow status for the associated counter. Writing 0 has no effect. To set the counter overflow status, use the GICP_OVSSET0 register. Reads return the state of the overflow status bits." "0,1"
bitfld.quad 0x00 3. "  OVS3  ,Overflow status. Writing 1 clears the overflow status for the associated counter. Writing 0 has no effect. To set the counter overflow status, use the GICP_OVSSET0 register. Reads return the state of the overflow status bits." "0,1"
bitfld.quad 0x00 2. "  OVS2  ,Overflow status. Writing 1 clears the overflow status for the associated counter. Writing 0 has no effect. To set the counter overflow status, use the GICP_OVSSET0 register. Reads return the state of the overflow status bits." "0,1"
NEWLINE
bitfld.quad 0x00 1. " OVS1  ,Overflow status. Writing 1 clears the overflow status for the associated counter. Writing 0 has no effect. To set the counter overflow status, use the GICP_OVSSET0 register. Reads return the state of the overflow status bits." "0,1"
bitfld.quad 0x00 0. "  OVS0  ,Overflow status. Writing 1 clears the overflow status for the associated counter. Writing 0 has no effect. To set the counter overflow status, use the GICP_OVSSET0 register. Reads return the state of the overflow status bits." "0,1"
group.quad 0xCC0++0x07
line.quad 0x00 "GICP_OVSSET0,Overflow Status Set Register 0"
bitfld.quad 0x00 4. " OVS4  ,Writing 1 sets the overflow status for the associated counter. Writing 0 has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register. Reads return the state of the overflow status bits." "0,1"
bitfld.quad 0x00 3. "  OVS3  ,Writing 1 sets the overflow status for the associated counter. Writing 0 has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register. Reads return the state of the overflow status bits." "0,1"
bitfld.quad 0x00 2. "  OVS2  ,Writing 1 sets the overflow status for the associated counter. Writing 0 has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register. Reads return the state of the overflow status bits." "0,1"
NEWLINE
bitfld.quad 0x00 1. " OVS1  ,Writing 1 sets the overflow status for the associated counter. Writing 0 has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register. Reads return the state of the overflow status bits." "0,1"
bitfld.quad 0x00 0. "  OVS0  ,Writing 1 sets the overflow status for the associated counter. Writing 0 has no effect. To clear a counter overflow status, use the GICP_OVSCLR0 register. Reads return the state of the overflow status bits." "0,1"
wgroup.long 0xD88++0x03
line.long 0x00 "GICP_CAPR,Counter Shadow Value Capture Register"
bitfld.long 0x00 0. " CAPTURE  ,When GICP_CFGR.CAPTURE == 1, a write of 1 to this bit triggers a capture of all values within the PMU into their respective shadow registers. When GICP_CFGR.CAPTURE == 0, this bit is zero." "-,1"
rgroup.long 0xE00++0x03
line.long 0x00 "GICP_CFGR,Configuration Information Register"
bitfld.long 0x00 22. " CAPTURE  ,Indicates if the GIC supports capture." "Not Supported,Supported"
hexmask.long.byte 0x00 8.--13. 1. " SIZE  ,Indicates the counter width+1."
hexmask.long.byte 0x00 0.--5.  1. " NCTR  ,Indicates the amount of available counters+1."
group.long 0xE04++0x03
line.long 0x00 "GICP_CR,Control Register"
bitfld.long 0x00 0. " E  ,Global counter enable. This bit takes precedence over the GICP_CNTENSET0.CNTEN bits." "Disabled,Enabled"
rgroup.long 0xFCC++0x03
line.long 0x00 "GICP_PMDEVTYPE,-"
NEWLINE
tree "Peripheral/Component ID Registers"
rgroup.long 0xFE0++0x03
line.long 0x00 "GICP_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFE4++0x03
line.long 0x00 "GICP_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFE8++0x03
line.long 0x00 "GICP_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-600 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFEC++0x03
line.long 0x00 "GICP_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFD0++0x03
line.long 0x00 "GICP_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFD4++0x03
hide.long 0x00 "GICP_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFD8++0x03
hide.long 0x00 "GICP_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFDC++0x03
hide.long 0x00 "GICP_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFF0++0x03
line.long 0x00 "GICP_CIDR0,Component ID0 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFF4++0x03
line.long 0x00 "GICP_CIDR1,Component ID1 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFF8++0x03
line.long 0x00 "GICP_CIDR2,Component ID2 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFC++0x03
line.long 0x00 "GICP_CIDR3,Component ID3 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
AUTOINDENT.OFF
base (COMP.BASE("GICD",-1.)+0x40000)
AUTOINDENT.ON CENTER TREE
tree "Interrupt Translation Service"
group.long 0x00++0x03
line.long 0x00 "GITS_CTLR,ITS Control Register"
rbitfld.long 0x00 31. "  QUIESCENT  ,Indicates completion of all ITS operations" "Not quiescent,Quiescent"
bitfld.long 0x00 0. "  ENABLED  ,Controls whether the ITS is enabled" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "GITS_IIDR,ITS Implementer Identification Register"
bitfld.long 0x00 24.--31. "  PRODID  ,Indicates the product ID" "GIC-500,?,GIC-600,?..."
bitfld.long 0x00 16.--19. "  VAR  ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
NEWLINE
bitfld.long 0x00 12.--15. "  REV  ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "  IMP  ,Implementer"
if (((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0008))&0x1000000000)==0x1000000000)&&(((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0008))&0xFF000000)!=0x00)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. "  VMOVP  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "  CIL  ,Collection ID Limit" "0,1"
NEWLINE
bitfld.quad 0x00 32.--35. "  CIDBITS  ,Number of Collection ID bits set by " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 24.--31. 1. "  HCC  ,Hardware Collection Count"
NEWLINE
bitfld.quad 0x00 19. "  PTA  ,Indicates the format of the target address" "Not suppported,Supported"
bitfld.quad 0x00 18. "  SEIS  ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
NEWLINE
bitfld.quad 0x00 13.--17. "  DEVBITS  ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--12. "  ID_BITS  ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
NEWLINE
rbitfld.quad 0x00 4.--7. "  ITT_ENTRY_SIZE  ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.quad 0x00 2. "  CCT  ,Cumulative Collection Tables" "0,1"
elif (((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0008))&0x1000000000)==0x1000000000)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. "  VMOVP  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "  CIL  ,Collection ID Limit" "0,1"
NEWLINE
bitfld.quad 0x00 32.--35. "  CIDBITS  ,Number of Collection ID bits minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.quad.byte 0x00 24.--31. 1. "  HCC  ,Hardware Collection Count"
NEWLINE
bitfld.quad 0x00 19. "  PTA  ,Indicates the format of the target address" "Not suppported,Supported"
bitfld.quad 0x00 18. "  SEIS  ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
NEWLINE
bitfld.quad 0x00 13.--17. "  DEVBITS  ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.quad 0x00 8.--12. "  ID_BITS  ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
NEWLINE
rbitfld.quad 0x00 4.--7. "  ITT_ENTRY_SIZE  ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
elif (((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0008))&0xFF000000)!=0x00)
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. "  VMOVP  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "  CIL  ,Collection ID Limit" "0,1"
NEWLINE
hexmask.quad.byte 0x00 24.--31. 1. "  HCC  ,Hardware Collection Count"
bitfld.quad 0x00 19. "  PTA  ,Indicates the format of the target address" "Not suppported,Supported"
NEWLINE
bitfld.quad 0x00 18. "  SEIS  ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
bitfld.quad 0x00 13.--17. "  DEVBITS  ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
NEWLINE
bitfld.quad 0x00 8.--12. "  ID_BITS  ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 4.--7. "  ITT_ENTRY_SIZE  ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
NEWLINE
bitfld.quad 0x00 2. "  CCT  ,Cumulative Collection Tables" "0,1"
else
rgroup.quad 0x08++0x07
line.quad 0x00 "GITS_TYPER,ITS Type Register"
bitfld.quad 0x00 37. "  VMOVP  ,Indicates the form of the VMOVP command" "All ITSs,One ITS"
bitfld.quad 0x00 36. "  CIL  ,Collection ID Limit" "0,1"
NEWLINE
hexmask.quad.byte 0x00 24.--31. 1. "  HCC  ,Hardware Collection Count"
bitfld.quad 0x00 19. "  PTA  ,Indicates the format of the target address" "Not suppported,Supported"
NEWLINE
bitfld.quad 0x00 18. "  SEIS  ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not suppported,Supported"
bitfld.quad 0x00 13.--17. "  DEVBITS  ,The number of DeviceID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
NEWLINE
bitfld.quad 0x00 8.--12. "  ID_BITS  ,The number of EventID bits implemented minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.quad 0x00 4.--7. "  ITT_ENTRY_SIZE  ,The number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x20++0x03
line.long 0x00 "GITS_FCTLR,Function Control Register"
bitfld.long 0x00 31. "  DCC  ,Disable Cache Conversion (DCC)." "Disabled,Enabled"
bitfld.long 0x00 30. "  PWE  ,Powerdown While Enabled. Request GITS_CTLR.Quiescent to indicate ITS is quiescent." "Disabled,Enabled"
NEWLINE
bitfld.long 0x00 18. "  IEC  ,Invalidate Event Cache." "Disabled,Enabled"
bitfld.long 0x00 17. "  IDC  ,Invalidate Device Cache." "Disabled,Enabled"
NEWLINE
bitfld.long 0x00 16. "  ICC  ,Invalidate Collection Cache." "Disabled,Enabled"
bitfld.long 0x00 9. "  QD  ,Q Deny. Indicates if Q-Channel requests are denied." "Not denied,Denied"
NEWLINE
bitfld.long 0x00 8. "  AEE  ,Access Error Enable. Indicates if reporting of slave access errors is enabled." "Disabled,Enabled"
hexmask.long.byte 0x00 4.--7. 1. "  CGO  ,One bit per clock gate. Indicates if full clock gating is active."
NEWLINE
bitfld.long 0x00 3. "  CEE  ,Command error enable." "Disabled,Enabled"
bitfld.long 0x00 2. "  UEE  ,Unmapped error enable. Indicates if unmapped interrupt errors are enabled" "Disabled,Enabled"
NEWLINE
bitfld.long 0x00 1. "  LTE  ,Latency tracking enable. Indicates if latency tracking of interrupts is enabled" "Disabled,Enabled"
bitfld.long 0x00 0. "  SIP  ,Scrub in progress. This bit is read and written by software. When a scrub is complete, the GIC clears the bit to 0." "Completed,In Progress"
group.quad 0x28++0x07
line.quad 0x00 "GITS_OPR,Operations Register"
bitfld.quad 0x00 60.--63. "  LOCKTYPE  ,Lock-Type. Supported lock types" "Track,Trial,ITS lock,ITS unlock,Track abort,?,LPI lock, LPI unlock, ITS unlock all,?,?,?,?,?,?,?"
hexmask.quad.long 0x00 32.--59. 1. "  DEVICEID  ,Device-ID. 0-maximum DeviceID supported."
NEWLINE
hexmask.quad.word 0x00 0.--15. 1. "  EVENTID  ,Event-ID. 8192-maximum EventID supported."
rgroup.quad 0x30++0x07
line.quad 0x00 "GITS_OPSR,Operation Status Register"
bitfld.quad 0x00 63. "  REQUESTCOMPLETE  ,Request to GITS_OPR completed." "In Progress,Completed"
bitfld.quad 0x00 62. "  REQUESTPASS  ,Request to GITS_OPR completed without error." "Not passed,Passed"
NEWLINE
bitfld.quad 0x00 61. "  REQUESTINPROGRESS  ,Translation in progress." "Completed,In Progress"
bitfld.quad 0x00 48. "  ENTRYLOCKED  ,Locked entry in cache corresponds to request." "Unlocked,Locked"
NEWLINE
hexmask.quad.word 0x00 32.--44. 1. "  TARGET  ,Target of interrupt requested."
hexmask.quad.word 0x00  0.--15. 1. "  PID  ,Physical ID of interrupt requested."
group.quad 0x80++0x07
line.quad 0x00 "GITS_CBASER,The command queue control register"
bitfld.quad 0x00 63. "  VALID  ,Indicates whether software has allocated memory for the command queue" "Not allocated,Allocated"
bitfld.quad 0x00 59.--61. "  INNERCACHE  ,Indicates the Inner Cacheability attributes of accesses to the command queue" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
NEWLINE
bitfld.quad 0x00 53.--55. "  OUTERCACHE  ,Indicates the Outer Cacheability attributes of accesses to the command queue" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
hexmask.quad 0x00 12.--51. 0x10 "  PHYSICAL_ADDRESS  ,Bits [51:12] of the base physical address of the command queue"
NEWLINE
bitfld.quad 0x00 10.--11. "  SHAREABILITY  ,Indicates the Shareability attributes of accesses to the command queue" "Non-shareable,Inner Shareable,Outer Shareable,?..."
hexmask.quad.byte 0x00 0.--7. 1. "  SIZE  ,The number of 4KB pages of physical memory allocated to the command queue minus one"
group.quad 0x88++0x7
line.quad 0x00 "GITS_CWRITER,The command queue write pointer"
hexmask.quad.word 0x00 5.--19. 0x20 "  OFFSET  ,Bits [19:5] of the offset from GITS_CBASER"
bitfld.quad 0x00 0. "  RETRY  ,Restarts the processing of commands by the ITS if it stalled because of a command error" "No effect,Restarted"
group.quad 0x90++0x07
line.quad 0x00 "GITS_CREADR,The command queue read pointer"
hexmask.quad.word 0x00 5.--19. 0x20 "  OFFSET  ,Bits [19:5] of the offset from GITS_CBASER"
bitfld.quad 0x00 0. "  STALLED  ,Reports whether the processing of commands is stalled because of a command error" "Not stalled,Stalled"
if (((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0100))&0x700000000000000)==0x00)
group.quad 0x100++0x07
line.quad 0x00 "GITS_BASER0,ITS table control register"
bitfld.quad 0x00 63. "  VALID  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "  INDIRECT  ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
NEWLINE
bitfld.quad 0x00 59.--61. "  INNERCACHE  ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "  TYPE  ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
NEWLINE
bitfld.quad 0x00 53.--55. "  OUTERCACHE  ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "  ENTRY_SIZE  ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
NEWLINE
hexmask.quad 0x00 12.--47. 1. "  PHYSICAL_ADDRESS  ,Physical Address"
bitfld.quad 0x00 10.--11. "  SHAREABILITY  ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
NEWLINE
bitfld.quad 0x00 8.--9. "  PAGE_SIZE  ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
else
group.quad 0x100++0x07
line.quad 0x00 "GITS_BASER0,ITS table control register"
bitfld.quad 0x00 63. "  VALID  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "  INDIRECT  ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
NEWLINE
bitfld.quad 0x00 59.--61. "  INNERCACHE  ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "  TYPE  ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
NEWLINE
bitfld.quad 0x00 53.--55. "  OUTERCACHE  ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "  ENTRY_SIZE  ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
NEWLINE
hexmask.quad 0x00 12.--47. 0x10 "  PHYSICAL_ADDRESS  ,Physical Address"
bitfld.quad 0x00 10.--11. "  SHAREABILITY  ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
NEWLINE
bitfld.quad 0x00 8.--9. "  PAGE_SIZE  ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
hexmask.quad.byte 0x00 0.--7. 1. "  SIZE  ,The number of pages of physical memory allocated to the table minus one"
endif
if (((per.q((COMP.BASE("GICD",-1.)+0x40000)+0x0108))&0x700000000000000)==0x00)
group.quad 0x108++0x07
line.quad 0x00 "GITS_BASER1,ITS table control register"
bitfld.quad 0x00 63. "  VALID  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "  INDIRECT  ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
NEWLINE
bitfld.quad 0x00 59.--61. "  INNERCACHE  ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "  TYPE  ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
NEWLINE
bitfld.quad 0x00 53.--55. "  OUTERCACHE  ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "  ENTRY_SIZE  ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
NEWLINE
hexmask.quad 0x00 12.--47. 1. "  PHYSICAL_ADDRESS  ,Physical Address"
bitfld.quad 0x00 10.--11. "  SHAREABILITY  ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
NEWLINE
bitfld.quad 0x00 8.--9. "  PAGE_SIZE  ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
else
group.quad 0x108++0x07
line.quad 0x00 "GITS_BASER1,ITS table control register"
bitfld.quad 0x00 63. "  VALID  ,Indicates whether software has allocated memory for the translation table" "Not allocated,Allocated"
bitfld.quad 0x00 62. "  INDIRECT  ,This field indicates whether an implemented register specifies a single flat table or a two-level table where the first level contains a list of descriptors" "Single Level,Two Level"
NEWLINE
bitfld.quad 0x00 59.--61. "  INNERCACHE  ,Indicates the Inner Cacheability attributes of accesses to the table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
rbitfld.quad 0x00 56.--58. "  TYPE  ,Specifies the type of entity that requires entries in the corresponding translation table" "Unimplemented,Devices,Reserved,Reserved,Interrupt collections,?..."
NEWLINE
bitfld.quad 0x00 53.--55. "  OUTERCACHE  ,Indicates the Outer Cacheability attributes of accesses to the table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
rbitfld.quad 0x00 48.--52. "  ENTRY_SIZE  ,Specifies the number of bytes per translation table entry minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
NEWLINE
hexmask.quad 0x00 12.--47. 0x10 "  PHYSICAL_ADDRESS  ,Physical Address"
bitfld.quad 0x00 10.--11. "  SHAREABILITY  ,Indicates the Shareability attributes of accesses to the table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
NEWLINE
bitfld.quad 0x00 8.--9. "  PAGE_SIZE  ,The size of page that the translation table uses" "4KB,16KB,64KB,?..."
hexmask.quad.byte 0x00 0.--7. 1. "  SIZE  ,The number of pages of physical memory allocated to the table minus one"
endif
NEWLINE
rgroup.long 0xFFE0++0x03
line.long 0x00 "GITS_CFGID,Configuration ID Register"
hexmask.long.byte 0x00 0.--3. 1. "  ITSNUMBER  ,Returns the ITS block ID. The its_id[7:0] tie-off signal controls the ID value. Each ITS block must have a unique ID."
rgroup.long 0xFFE0++0x03
line.long 0x00 "GITS_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "  PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GITS_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. "  DES_1  ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  PART_1  ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GITS_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. "  ARCHREV  ,Identifies the version of the GIC architecture with which the GIC-600 complies." "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used." "Low,High"
NEWLINE
bitfld.long 0x00 0.--2. "  DES_1  ,JEP106 identity code [6:4]. Bits[3:0] of the JEP106 identity code are assigned to GITS_PIDR1." "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GITS_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. "  REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  CMOD  ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GITS_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. "  SIZE  ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "  DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GITS_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GITS_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GITS_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GITS_CIDR0,Component ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. "  FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GITS_CIDR1,Component ID1 Register"
hexmask.long.byte 0x00 0.--7. 1. "  FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GITS_CIDR2,Component ID2 Register"
hexmask.long.byte 0x00 0.--7. 1. "  FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GITS_CIDR3,Component ID3 Register"
hexmask.long.byte 0x00 0.--7. 1. "  FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
NEWLINE
base (COMP.BASE("GICD",-1.)+0x40000)+0x10000
if (((per.l((COMP.BASE("GICD",-1.)+0x40000)))&0x01)==0x01)
wgroup.long 0x40++0x03
line.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
else
hgroup.long 0x40++0x03
hide.long 0x00 "GITS_TRANSLATER,ITS Translation Register"
endif
tree.end
AUTOINDENT.OFF
base COMP.BASE("GICR",-1.)
AUTOINDENT.ON CENTER TREE
tree "Redistributor Interface"
tree "Control Registers"
if (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x21)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 26. "       DPG1S          ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
NEWLINE
bitfld.long 0x00 25. "             DPG1NS           ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
bitfld.long 0x00 24. " DPG0      ,Disable Processor selection for Group 0 interrupts" "No,Yes"
NEWLINE
bitfld.long 0x00 3. "               RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
bitfld.long 0x00 0. "     ENABLE_LPIS      ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x20)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 26. "       DPG1S          ,Disable Processor selection for Group 1 Secure interrupts" "No,Yes"
NEWLINE
bitfld.long 0x00 25. "             DPG1NS           ,Disable Processor selection for Group 1 Non-secure interrupts" "No,Yes"
bitfld.long 0x00 24. " DPG0      ,Disable Processor selection for Group 0 interrupts" "No,Yes"
NEWLINE
bitfld.long 0x00 3. "               RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
elif (((per.q(COMP.BASE("GICR",-1.)+0x08))&0x21)==0x01)
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 3. "       RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
NEWLINE
bitfld.long 0x00 0. "     ENABLE_LPIS      ,Enables LPIs in implementations where affinity routing is enabled for Security state" "Disabled,Enabled"
else
group.long 0x0000++0x03
line.long 0x00 "GICR_CTLR,Redistributor Control Register"
rbitfld.long 0x00 31. "         UWP       ,Upstream Write Pending. Indicates whether all upstream writes have been communicated to the Distributor" "Not pending,Pending"
bitfld.long 0x00 3. "       RWP            ,Register Write Pending. Indicates whether a register write for the current Security state is in progress or not" "Not pending,Pending"
endif
rgroup.long 0x0004++0x03
line.long 0x00 "GICR_IIDR,Distributor Implementer Identification Register"
bitfld.long 0x00 24.--31. "         PRODID    ,Indicates the product ID" "GIC-500,?,GIC-600,?..."
bitfld.long 0x00 16.--19. "           VAR            ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
NEWLINE
bitfld.long 0x00 12.--15. " REV       ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "                IMP            ,Implementer"
rgroup.quad 0x0008++0x07
line.quad 0x00 "GICR_TYPER,Interrupt Controller Type Register"
hexmask.quad.byte 0x00 56.--63. 1. " AFF3      ,Affinity level 3 value for the Redistributor"
hexmask.quad.byte 0x00 48.--55. 1. "                AFF2           ,Affinity level 2 value for the Redistributor"
NEWLINE
hexmask.quad.byte 0x00 40.--47. 1. "              AFF1             ,Affinity level 1 value for the Redistributor"
hexmask.quad.byte 0x00 32.--39. 1. " AFF0      ,Affinity level 0 value for the Redistributor"
NEWLINE
bitfld.quad 0x00 24.--25. "                COMMONLPIAFF   ,The affinity level at which Redistributors share a LPI Configuration table" "Single Core CFG,Chip by AF3, Chip by AF2, Reserved"
hexmask.quad.word 0x00 8.--23. 1. "  PROCESSOR_NUMBER ,A unique identifier for the PE"
NEWLINE
bitfld.quad 0x00 5. " DPGS      ,Sets support for GICR_CTLR.DPG* bits" "Not supported,Supported"
bitfld.quad 0x00 4. "     LAST           ,Indicates whether this Redistributor is the highest-numbered Redistributor in a series of contiguous Redistributor pages" "Not highest,Highest"
NEWLINE
bitfld.quad 0x00 3. "     DIRECTLPI        ,Indicates whether this Redistributor supports direct injection of LPIs" "Not supported,Supported"
bitfld.quad 0x00 0. " PLPIS     ,Indicates whether the GIC implementation supports physical LPIs" "Not supported,Supported"
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x0014))))
group.long 0x0014++0x03
line.long 0x00 "GICR_WAKER,Power Management Control Register"
bitfld.long 0x00 31. "         QUIESCENT ,This bit shows that the GIC-600 is idle and can be powered down if required" "Not quiescent,Quiescent"
bitfld.long 0x00 2. "     CHILDRENASLEEP ,Indicates the bus between the CPU interface and this Redistributor is quiescent" "Not quiescent,Quiescent"
NEWLINE
bitfld.long 0x00 1. "   PROCESSORASLEEP  ,Indicates if this Redistributor must assert a WakeRequest if there is a pending interrupt targeted at the connected core" "No,Yes"
bitfld.long 0x00 0. " SLEEP     ,Indicates if GIC-600 ensures that all the caches are consistent with external memory and that it is safe to power off" "No,Yes"
NEWLINE
else
hgroup.long 0x0014++0x03
hide.long 0x00 "GICR_WAKER,Power Management Control Register"
endif
group.long 0x0020++0x03
line.long 0x00 "GICR_FCTLR,Function Control Register"
bitfld.long 0x00 31. " QD        ,Q Deny. Indicates if Q-Channel requests are denied." "Not denied,Denied"
hexmask.long.byte 0x00 4.--6. 1. "           CGO        ,One bit per clock gate. Indicates if full clock gating is active."
NEWLINE
bitfld.long 0x00 0. "             SIP        ,Scrub in progress. This bit is read and written by software. When a scrub is complete, the GIC clears the bit to 0." "Completed,In Progress"
group.long 0x0024++0x03
line.long 0x00 "GICR_PWRR,Power Register"
hexmask.long.byte 0x00 16.--23. 1. " RDG    ,RDGroup. This read-only field indicates the number of the current Redistributor. Must be packed from 0."
hexmask.long.byte 0x00  8.--15. 1. "    RDGO    ,RDGroupOffset.This read-only field indicates the offset of the current core that is connected to the current Redistributor. Must be packed from 0 but does not necessarily map to a single cluster because the AXI4-Stream bus can be subdivided."
NEWLINE
rbitfld.long 0x00 3. "       RDGPO      ,RDGroupPoweredOff. This read-only bit indicates if group is powered and accessable or if it can be powered down" "Powered,Not powered"
rbitfld.long 0x00 2. " RDGPD      ,RDGroupPowerDown. This read-only bit indicates the intentional power state of the Redistributor. The Redistributor has reached its intentional power state when RDGPD = RDGPO." "Powered,Not powered"
NEWLINE
eventfld.long  0x00 1. "    RDAG      ,RDApplyGroup. This write-only bit applies the RDPD value to all Redistributors in the group. If the RDPD value cannot be applied to all cores in the group, then the GIC ignores this request." "-,Apply"
bitfld.long  0x00 0. "    RDPD      ,RDPowerDown. Writes to 1 ignored if GICR_WAKER.ProcessorSleep != 1. Writes ignored if RDGPD != RDGPO and changing to not match RDGPD. If all other cores have RDPD == 1, then setting this bit to 1 also sets RDGPD = 1." "Powered,Not powered"
group.long 0x0028++0x03
line.long 0x00 "GICR_CLASS,Class Register"
bitfld.long 0x00 0. " CLASS    ,Interrupt class." "0,1"
group.quad 0x070++0x07
line.quad 0x00 "GICR_PROPBASER,Common LPI configuration table base register"
bitfld.quad 0x00 56.--58. " OUTERCACHE       ,Indicates the Outer Cacheability attributes of accesses to the LPI Configuration table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
hexmask.quad 0x00 12.--51. 0x10 "  PHYSICAL_ADDRESS ,Bits [51:12] of the physical address containing the LPI Configuration table"
NEWLINE
bitfld.quad 0x00 10.--11. " SHAREABILITY     ,Indicates the Shareability attributes of accesses to the LPI Configuration table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
bitfld.quad 0x00 7.--9. "                  INNERCACHE       ,Indicates the Inner Cacheability attributes of accesses to the LPI Configuration table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
NEWLINE
bitfld.quad 0x00 0.--4. " IDBITS           ,The number of bits of LPI INTID supported minus one by the LPI Configuration table starting at Physical_Address"
group.quad 0x78++0x07
line.long 0x00 "GICR_PENDBASER,LPI pending table base register"
bitfld.quad 0x00 62. "         PTZ              ,Pending Table Zero" "Not zero,Zero" 
bitfld.quad 0x00 56.--58. "                         OUTERCACHE       ,Indicates the Outer Cacheability attributes of accesses to the LPI Pending table" "Defined in INNERCACHE,Normal outer non-cacheable,Normal outer RA WT cacheable,Normal outer RA WB cacheable,Normal outer WA WT cacheable,Normal outer WA WB cacheable,Normal outer RA WA WT cacheable,Normal outer RA WA WB cacheable"
NEWLINE
hexmask.quad 0x00 16.--51. 0x10 " PHYSICAL_ADDRESS ,Bits [51:16] of the physical address containing the LPI Pending table"
bitfld.quad 0x00 10.--11. "                 SHAREABILITY     ,Indicates the Shareability attributes of accesses to the LPI Pending table" "Non-shareable,Inner Shareable,Outer Shareable,?..."
NEWLINE
bitfld.quad 0x00 7.--9. " INNERCACHE       ,Indicates the Inner Cacheability attributes of accesses to the LPI Pending table" "Device-nGnRnE,Normal inner non-cacheable,Normal inner RA WT cacheable,Normal inner RA WB cacheable,Normal inner WA WT cacheable,Normal inner WA WB cacheable,Normal inner RA WA WT cacheable,Normal inner RA WA WB cacheable"
NEWLINE
tree.end
tree "SGI and PPI Registers"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10080))
group.long 0x10080++0x03
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. "         GSB31 ,Group Status Bit 31" "Secure,Non-secure Group 1"
bitfld.long 0x00 30. "  GSB30 ,Group Status Bit 30" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 29. "  GSB29 ,Group Status Bit 29" "Secure,Non-secure Group 1"
bitfld.long 0x00 28. "         GSB28 ,Group Status Bit 28" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 27. "  GSB27 ,Group Status Bit 27" "Secure,Non-secure Group 1"
bitfld.long 0x00 26. "  GSB26 ,Group Status Bit 26" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 25. "         GSB25 ,Group Status Bit 25" "Secure,Non-secure Group 1"
bitfld.long 0x00 24. "  GSB24 ,Group Status Bit 24" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 23. "  GSB23 ,Group Status Bit 23" "Secure,Non-secure Group 1"
bitfld.long 0x00 22. "         GSB22 ,Group Status Bit 22" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 21. "  GSB21 ,Group Status Bit 21" "Secure,Non-secure Group 1"
bitfld.long 0x00 20. "  GSB20 ,Group Status Bit 20" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 19. "         GSB19 ,Group Status Bit 19" "Secure,Non-secure Group 1"
bitfld.long 0x00 18. "  GSB18 ,Group Status Bit 18" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 17. "  GSB17 ,Group Status Bit 17" "Secure,Non-secure Group 1"
bitfld.long 0x00 16. "         GSB16 ,Group Status Bit 16" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 15. "  GSB15 ,Group Status Bit 15" "Secure,Non-secure Group 1"
bitfld.long 0x00 14. "  GSB14 ,Group Status Bit 14" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 13. "         GSB13 ,Group Status Bit 13" "Secure,Non-secure Group 1"
bitfld.long 0x00 12. "  GSB12 ,Group Status Bit 12" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 11. "  GSB11 ,Group Status Bit 11" "Secure,Non-secure Group 1"
bitfld.long 0x00 10. "         GSB10 ,Group Status Bit 10" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 9. "  GSB9  ,Group Status Bit 9" "Secure,Non-secure Group 1"
bitfld.long 0x00 8. "  GSB8  ,Group Status Bit 8" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 7. "         GSB7  ,Group Status Bit 7" "Secure,Non-secure Group 1"
bitfld.long 0x00 6. "  GSB6  ,Group Status Bit 6" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 5. "  GSB5  ,Group Status Bit 5" "Secure,Non-secure Group 1"
bitfld.long 0x00 4. "         GSB4  ,Group Status Bit 4" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 3. "  GSB3  ,Group Status Bit 3" "Secure,Non-secure Group 1"
bitfld.long 0x00 2. "  GSB2  ,Group Status Bit 2" "Secure,Non-secure Group 1"
NEWLINE
bitfld.long 0x00 1. "         GSB1  ,Group Status Bit 1" "Secure,Non-secure Group 1"
bitfld.long 0x00 0. "  GSB0  ,Group Status Bit 0" "Secure,Non-secure Group 1"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x000)
group.long 0x10080++0x03
line.long 0x0 "GICR_IGROUPR0,Interrupt Group Register 0"
bitfld.long 0x00 31. "         GSB31 ,Group Status Bit 31" "Group 0,Group 1"
bitfld.long 0x00 30. "             GSB30 ,Group Status Bit 30" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 29. "             GSB29 ,Group Status Bit 29" "Group 0,Group 1"
bitfld.long 0x00 28. "         GSB28 ,Group Status Bit 28" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 27. "             GSB27 ,Group Status Bit 27" "Group 0,Group 1"
bitfld.long 0x00 26. "             GSB26 ,Group Status Bit 26" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 25. "         GSB25 ,Group Status Bit 25" "Group 0,Group 1"
bitfld.long 0x00 24. "             GSB24 ,Group Status Bit 24" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 23. "             GSB23 ,Group Status Bit 23" "Group 0,Group 1"
bitfld.long 0x00 22. "         GSB22 ,Group Status Bit 22" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 21. "             GSB21 ,Group Status Bit 21" "Group 0,Group 1"
bitfld.long 0x00 20. "             GSB20 ,Group Status Bit 20" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 19. "         GSB19 ,Group Status Bit 19" "Group 0,Group 1"
bitfld.long 0x00 18. "             GSB18 ,Group Status Bit 18" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 17. "             GSB17 ,Group Status Bit 17" "Group 0,Group 1"
bitfld.long 0x00 16. "         GSB16 ,Group Status Bit 16" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 15. "             GSB15 ,Group Status Bit 15" "Group 0,Group 1"
bitfld.long 0x00 14. "             GSB14 ,Group Status Bit 14" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 13. "         GSB13 ,Group Status Bit 13" "Group 0,Group 1"
bitfld.long 0x00 12. "             GSB12 ,Group Status Bit 12" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 11. "             GSB11 ,Group Status Bit 11" "Group 0,Group 1"
bitfld.long 0x00 10. "         GSB10 ,Group Status Bit 10" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 9. "             GSB9  ,Group Status Bit 9" "Group 0,Group 1"
bitfld.long 0x00 8. "             GSB8  ,Group Status Bit 8" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 7. "         GSB7  ,Group Status Bit 7" "Group 0,Group 1"
bitfld.long 0x00 6. "             GSB6  ,Group Status Bit 6" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 5. "             GSB5  ,Group Status Bit 5" "Group 0,Group 1"
bitfld.long 0x00 4. "         GSB4  ,Group Status Bit 4" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 3. "             GSB3  ,Group Status Bit 3" "Group 0,Group 1"
bitfld.long 0x00 2. "             GSB2  ,Group Status Bit 2" "Group 0,Group 1"
NEWLINE
bitfld.long 0x00 1. "         GSB1  ,Group Status Bit 1" "Group 0,Group 1"
bitfld.long 0x00 0. "             GSB0  ,Group Status Bit 0" "Group 0,Group 1"
else
hgroup.long 0x10080++0x03
hide.long 0x00 "GICR_IGROUPR0,Interrupt Group Register 0"
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
endif
NEWLINE
width 24.
group.long 0x10100++0x03
line.long 0x0 "GICR_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRENB31    ,Set/Clear Enable Bit 31" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRENB30    ,Set/Clear Enable Bit 30" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRENB29    ,Set/Clear Enable Bit 29" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRENB28    ,Set/Clear Enable Bit 28" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRENB27    ,Set/Clear Enable Bit 27" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRENB26    ,Set/Clear Enable Bit 26" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRENB25    ,Set/Clear Enable Bit 25" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRENB24    ,Set/Clear Enable Bit 24" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRENB23    ,Set/Clear Enable Bit 23" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRENB22    ,Set/Clear Enable Bit 22" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRENB21    ,Set/Clear Enable Bit 21" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRENB20    ,Set/Clear Enable Bit 20" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRENB19    ,Set/Clear Enable Bit 19" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRENB18    ,Set/Clear Enable Bit 18" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRENB17    ,Set/Clear Enable Bit 17" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRENB16    ,Set/Clear Enable Bit 16" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRENB15    ,Set/Clear Enable Bit 15" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRENB14    ,Set/Clear Enable Bit 14" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRENB13    ,Set/Clear Enable Bit 13" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRENB12    ,Set/Clear Enable Bit 12" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRENB11    ,Set/Clear Enable Bit 11" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRENB10    ,Set/Clear Enable Bit 10" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRENB9     ,Set/Clear Enable Bit 9" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRENB8     ,Set/Clear Enable Bit 8" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRENB7     ,Set/Clear Enable Bit 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRENB6     ,Set/Clear Enable Bit 6" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRENB5     ,Set/Clear Enable Bit 5" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRENB4     ,Set/Clear Enable Bit 4" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRENB3     ,Set/Clear Enable Bit 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRENB2     ,Set/Clear Enable Bit 2" "Disabled,Enabled"
NEWLINE
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRENB1     ,Set/Clear Enable Bit 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRENB0     ,Set/Clear Enable Bit 0" "Disabled,Enabled"
group.long 0x10200++0x03
line.long 0x0 "GICR_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRPEND31   ,Set/Clear Pending Bit 31" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "    SET/CLRPEND30   ,Set/Clear Pending Bit 30" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "    SET/CLRPEND29   ,Set/Clear Pending Bit 29" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRPEND28   ,Set/Clear Pending Bit 28" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "    SET/CLRPEND27   ,Set/Clear Pending Bit 27" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "    SET/CLRPEND26   ,Set/Clear Pending Bit 26" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRPEND25   ,Set/Clear Pending Bit 25" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "    SET/CLRPEND24   ,Set/Clear Pending Bit 24" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "    SET/CLRPEND23   ,Set/Clear Pending Bit 23" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRPEND22   ,Set/Clear Pending Bit 22" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "    SET/CLRPEND21   ,Set/Clear Pending Bit 21" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "    SET/CLRPEND20   ,Set/Clear Pending Bit 20" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRPEND19   ,Set/Clear Pending Bit 19" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "    SET/CLRPEND18   ,Set/Clear Pending Bit 18" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "    SET/CLRPEND17   ,Set/Clear Pending Bit 17" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRPEND16   ,Set/Clear Pending Bit 16" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "    SET/CLRPEND15   ,Set/Clear Pending Bit 15" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "    SET/CLRPEND14   ,Set/Clear Pending Bit 14" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRPEND13   ,Set/Clear Pending Bit 13" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "    SET/CLRPEND12   ,Set/Clear Pending Bit 12" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "    SET/CLRPEND11   ,Set/Clear Pending Bit 11" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRPEND10   ,Set/Clear Pending Bit 10" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "    SET/CLRPEND9    ,Set/Clear Pending Bit 9" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "    SET/CLRPEND8    ,Set/Clear Pending Bit 8" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRPEND7    ,Set/Clear Pending Bit 7" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "    SET/CLRPEND6    ,Set/Clear Pending Bit 6" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "    SET/CLRPEND5    ,Set/Clear Pending Bit 5" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRPEND4    ,Set/Clear Pending Bit 4" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "    SET/CLRPEND3    ,Set/Clear Pending Bit 3" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "    SET/CLRPEND2    ,Set/Clear Pending Bit 2" "Not pending,Pending"
NEWLINE
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRPEND1    ,Set/Clear Pending Bit 1" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "    SET/CLRPEND0    ,Set/Clear Pending Bit 0" "Not pending,Pending"
group.long 0x10300++0x03
line.long 0x0 "GICR_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. "  SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active"
NEWLINE
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active"
NEWLINE
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active"
NEWLINE
setclrfld.long 0x00 25. 0x00 25. 0x80 25. "  SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active"
NEWLINE
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active"
NEWLINE
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active"
NEWLINE
setclrfld.long 0x00 19. 0x00 19. 0x80 19. "  SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active"
NEWLINE
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active"
NEWLINE
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active"
NEWLINE
setclrfld.long 0x00 13. 0x00 13. 0x80 13. "  SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active"
NEWLINE
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active"
NEWLINE
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  SET/CLRACTIVE9  ,Set/Clear Active Bit 9" "Not active,Active"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  SET/CLRACTIVE8  ,Set/Clear Active Bit 8" "Not active,Active"
NEWLINE
setclrfld.long 0x00 7. 0x00 7. 0x80 7. "  SET/CLRACTIVE7  ,Set/Clear Active Bit 7" "Not active,Active"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  SET/CLRACTIVE6  ,Set/Clear Active Bit 6" "Not active,Active"
NEWLINE
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  SET/CLRACTIVE5  ,Set/Clear Active Bit 5" "Not active,Active"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  SET/CLRACTIVE4  ,Set/Clear Active Bit 4" "Not active,Active"
NEWLINE
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  SET/CLRACTIVE3  ,Set/Clear Active Bit 3" "Not active,Active"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  SET/CLRACTIVE2  ,Set/Clear Active Bit 2" "Not active,Active"
NEWLINE
setclrfld.long 0x00 1. 0x00 1. 0x80 1. "  SET/CLRACTIVE1  ,Set/Clear Active Bit 1" "Not active,Active"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  SET/CLRACTIVE0  ,Set/Clear Active Bit 0" "Not active,Active"
NEWLINE
width 18.
group.long 0x10400++0x03
line.long 0x00 "GICR_IPRIORITYR0,Interrupt Priority Register 0"
hexmask.long.byte 0x00 24.--31. 1. " INTID3    ,Interrupt ID3    Priority/Priority Byte Offset 3   "
hexmask.long.byte 0x00 16.--23. 1. "     INTID2    ,Interrupt ID2    Priority/Priority Byte Offset 2   "
NEWLINE
hexmask.long.byte 0x00 8.--15. 1. "     INTID1    ,Interrupt ID1    Priority/Priority Byte Offset 1   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID0    ,Interrupt ID0    Priority/Priority Byte Offset 0   "
group.long 0x10404++0x03
line.long 0x00 "GICR_IPRIORITYR1,Interrupt Priority Register 1"
hexmask.long.byte 0x00 24.--31. 1. " INTID7    ,Interrupt ID7    Priority/Priority Byte Offset 7   "
hexmask.long.byte 0x00 16.--23. 1. "     INTID6    ,Interrupt ID6    Priority/Priority Byte Offset 6   "
NEWLINE
hexmask.long.byte 0x00 8.--15. 1. "     INTID5    ,Interrupt ID5    Priority/Priority Byte Offset 5   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID4    ,Interrupt ID4    Priority/Priority Byte Offset 4   "
group.long 0x10408++0x03
line.long 0x00 "GICR_IPRIORITYR2,Interrupt Priority Register 2"
hexmask.long.byte 0x00 24.--31. 1. " INTID11   ,Interrupt ID11   Priority/Priority Byte Offset 11  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID10   ,Interrupt ID10   Priority/Priority Byte Offset 10  "
NEWLINE
hexmask.long.byte 0x00 8.--15. 1. "     INTID9    ,Interrupt ID9    Priority/Priority Byte Offset 9   "
hexmask.long.byte 0x00 0.--7. 1. "     INTID8    ,Interrupt ID8    Priority/Priority Byte Offset 8   "
group.long 0x1040C++0x03
line.long 0x00 "GICR_IPRIORITYR3,Interrupt Priority Register 3"
hexmask.long.byte 0x00 24.--31. 1. " INTID15   ,Interrupt ID15   Priority/Priority Byte Offset 15  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID14   ,Interrupt ID14   Priority/Priority Byte Offset 14  "
NEWLINE
hexmask.long.byte 0x00 8.--15. 1. "     INTID13   ,Interrupt ID13   Priority/Priority Byte Offset 13  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID12   ,Interrupt ID12   Priority/Priority Byte Offset 12  "
group.long 0x10410++0x03
line.long 0x00 "GICR_IPRIORITYR4,Interrupt Priority Register 4"
hexmask.long.byte 0x00 24.--31. 1. " INTID19   ,Interrupt ID19   Priority/Priority Byte Offset 19  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID18   ,Interrupt ID18   Priority/Priority Byte Offset 18  "
NEWLINE
hexmask.long.byte 0x00 8.--15. 1. "     INTID17   ,Interrupt ID17   Priority/Priority Byte Offset 17  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID16   ,Interrupt ID16   Priority/Priority Byte Offset 16  "
group.long 0x10414++0x03
line.long 0x00 "GICR_IPRIORITYR5,Interrupt Priority Register 5"
hexmask.long.byte 0x00 24.--31. 1. " INTID23   ,Interrupt ID23   Priority/Priority Byte Offset 23  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID22   ,Interrupt ID22   Priority/Priority Byte Offset 22  "
NEWLINE
hexmask.long.byte 0x00 8.--15. 1. "     INTID21   ,Interrupt ID21   Priority/Priority Byte Offset 21  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID20   ,Interrupt ID20   Priority/Priority Byte Offset 20  "
group.long 0x10418++0x03
line.long 0x00 "GICR_IPRIORITYR6,Interrupt Priority Register 6"
hexmask.long.byte 0x00 24.--31. 1. " INTID27   ,Interrupt ID27   Priority/Priority Byte Offset 27  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID26   ,Interrupt ID26   Priority/Priority Byte Offset 26  "
NEWLINE
hexmask.long.byte 0x00 8.--15. 1. "     INTID25   ,Interrupt ID25   Priority/Priority Byte Offset 25  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID24   ,Interrupt ID24   Priority/Priority Byte Offset 24  "
group.long 0x1041C++0x03
line.long 0x00 "GICR_IPRIORITYR7,Interrupt Priority Register 7"
hexmask.long.byte 0x00 24.--31. 1. " INTID31   ,Interrupt ID31   Priority/Priority Byte Offset 31  "
hexmask.long.byte 0x00 16.--23. 1. "     INTID30   ,Interrupt ID30   Priority/Priority Byte Offset 30  "
NEWLINE
hexmask.long.byte 0x00 8.--15. 1. "     INTID29   ,Interrupt ID29   Priority/Priority Byte Offset 29  "
hexmask.long.byte 0x00 0.--7. 1. "     INTID28   ,Interrupt ID28   Priority/Priority Byte Offset 28  "
NEWLINE
rgroup.long 0x10C00++0x03
line.long 0x00 "GICR_ICFGR0,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15   ,Interrupt Configuration 15 (SGI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14   ,Interrupt Configuration 14 (SGI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 27. "  ICF13   ,Interrupt Configuration 13 (SGI)" "Level,Edge"
bitfld.long 0x00 25. " ICF12   ,Interrupt Configuration 12 (SGI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 23. "  ICF11   ,Interrupt Configuration 11 (SGI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10   ,Interrupt Configuration 10 (SGI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 19. " ICF9    ,Interrupt Configuration 9 (SGI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8    ,Interrupt Configuration 8 (SGI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 15. "  ICF7    ,Interrupt Configuration 7 (SGI)" "Level,Edge"
bitfld.long 0x00 13. " ICF6    ,Interrupt Configuration 6 (SGI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 11. "  ICF5    ,Interrupt Configuration 5 (SGI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4    ,Interrupt Configuration 4 (SGI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 7. " ICF3    ,Interrupt Configuration 3 (SGI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2    ,Interrupt Configuration 2 (SGI)" "Level,Edge"
group.long 0x10C04++0x03
line.long 0x00 "GICR_ICFGR1,Interrupt Configuration Register"
bitfld.long 0x00 31. " ICF15   ,Interrupt Configuration 15 (PPI)" "Level,Edge"
bitfld.long 0x00 29. "  ICF14   ,Interrupt Configuration 14 (PPI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 27. "  ICF13   ,Interrupt Configuration 13 (PPI)" "Level,Edge"
bitfld.long 0x00 25. " ICF12   ,Interrupt Configuration 12 (PPI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 23. "  ICF11   ,Interrupt Configuration 11 (PPI)" "Level,Edge"
bitfld.long 0x00 21. "  ICF10   ,Interrupt Configuration 10 (PPI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 19. " ICF9    ,Interrupt Configuration 9 (PPI)" "Level,Edge"
bitfld.long 0x00 17. "  ICF8    ,Interrupt Configuration 8 (PPI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 15. "  ICF7    ,Interrupt Configuration 7 (PPI)" "Level,Edge"
bitfld.long 0x00 13. " ICF6    ,Interrupt Configuration 6 (PPI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 11. "  ICF5    ,Interrupt Configuration 5 (PPI)" "Level,Edge"
bitfld.long 0x00 9. "  ICF4    ,Interrupt Configuration 4 (PPI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 7. " ICF3    ,Interrupt Configuration 3 (PPI)" "Level,Edge"
bitfld.long 0x00 5. "  ICF2    ,Interrupt Configuration 2 (PPI)" "Level,Edge"
NEWLINE
bitfld.long 0x00 3. "  ICF1    ,Interrupt Configuration 1 (PPI)" "Level,Edge"
NEWLINE
width 18.
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10D00))
group.long 0x10D00++0x03
line.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
bitfld.long 0x00 31. " GMB31 ,Group Modifier Bit 31" "0,1"
bitfld.long 0x00 30. "  GMB30 ,Group Modifier Bit 30" "0,1"
NEWLINE
bitfld.long 0x00 29. "  GMB29 ,Group Modifier Bit 29" "0,1"
bitfld.long 0x00 28. " GMB28 ,Group Modifier Bit 28" "0,1"
NEWLINE
bitfld.long 0x00 27. "  GMB27 ,Group Modifier Bit 27" "0,1"
bitfld.long 0x00 26. "  GMB26 ,Group Modifier Bit 26" "0,1"
NEWLINE
bitfld.long 0x00 25. " GMB25 ,Group Modifier Bit 25" "0,1"
bitfld.long 0x00 24. "  GMB24 ,Group Modifier Bit 24" "0,1"
NEWLINE
bitfld.long 0x00 23. "  GMB23 ,Group Modifier Bit 23" "0,1"
bitfld.long 0x00 22. " GMB22 ,Group Modifier Bit 22" "0,1"
NEWLINE
bitfld.long 0x00 21. "  GMB21 ,Group Modifier Bit 21" "0,1"
bitfld.long 0x00 20. "  GMB20 ,Group Modifier Bit 20" "0,1"
NEWLINE
bitfld.long 0x00 19. " GMB19 ,Group Modifier Bit 19" "0,1"
bitfld.long 0x00 18. "  GMB18 ,Group Modifier Bit 18" "0,1"
NEWLINE
bitfld.long 0x00 17. "  GMB17 ,Group Modifier Bit 17" "0,1"
bitfld.long 0x00 16. " GMB16 ,Group Modifier Bit 16" "0,1"
NEWLINE
bitfld.long 0x00 15. "  GMB15 ,Group Modifier Bit 15" "0,1"
bitfld.long 0x00 14. "  GMB14 ,Group Modifier Bit 14" "0,1"
NEWLINE
bitfld.long 0x00 13. " GMB13 ,Group Modifier Bit 13" "0,1"
bitfld.long 0x00 12. "  GMB12 ,Group Modifier Bit 12" "0,1"
NEWLINE
bitfld.long 0x00 11. "  GMB11 ,Group Modifier Bit 11" "0,1"
bitfld.long 0x00 10. " GMB10 ,Group Modifier Bit 10" "0,1"
NEWLINE
bitfld.long 0x00 9. "  GMB9  ,Group Modifier Bit 9" "0,1"
bitfld.long 0x00 8. "  GMB8  ,Group Modifier Bit 8" "0,1"
NEWLINE
bitfld.long 0x00 7. " GMB7  ,Group Modifier Bit 7" "0,1"
bitfld.long 0x00 6. "  GMB6  ,Group Modifier Bit 6" "0,1"
NEWLINE
bitfld.long 0x00 5. "  GMB5  ,Group Modifier Bit 5" "0,1"
bitfld.long 0x00 4. " GMB4  ,Group Modifier Bit 4" "0,1"
NEWLINE
bitfld.long 0x00 3. "  GMB3  ,Group Modifier Bit 3" "0,1"
bitfld.long 0x00 2. "  GMB2  ,Group Modifier Bit 2" "0,1"
NEWLINE
bitfld.long 0x00 1. " GMB1  ,Group Modifier Bit 1" "0,1"
bitfld.long 0x00 0. "  GMB0  ,Group Modifier Bit 0" "0,1"
NEWLINE
else
hgroup.long 0x10D00++0x03
hide.long 0x0 "GICR_IGRPMODR0,Interrupt Group Modifier Register 0"
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
endif
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x10E00))
group.long 0x10E00++0x03
line.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
bitfld.long 0x00 30.--31. " NS_ACCESS15 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID15" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 28.--29. "  NS_ACCESS14 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID14" "No access,G0S,G0S/G1S,?..."
NEWLINE
bitfld.long 0x00 26.--27. "  NS_ACCESS13 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID13" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 24.--25. " NS_ACCESS12 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID12" "No access,G0S,G0S/G1S,?..."
NEWLINE
bitfld.long 0x00 22.--23. "  NS_ACCESS11 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID11" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 20.--21. "  NS_ACCESS10 ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID10" "No access,G0S,G0S/G1S,?..."
NEWLINE
bitfld.long 0x00 18.--19. " NS_ACCESS9  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID9" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 16.--17. "  NS_ACCESS8  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID8" "No access,G0S,G0S/G1S,?..."
NEWLINE
bitfld.long 0x00 14.--15. "  NS_ACCESS7  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID7" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 12.--13. " NS_ACCESS6  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID6" "No access,G0S,G0S/G1S,?..."
NEWLINE
bitfld.long 0x00 10.--11. "  NS_ACCESS5  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID5" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 8.--9. "  NS_ACCESS4  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID4" "No access,G0S,G0S/G1S,?..."
NEWLINE
bitfld.long 0x00 6.--7. " NS_ACCESS3  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID3" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 4.--5. "  NS_ACCESS2  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID2" "No access,G0S,G0S/G1S,?..."
NEWLINE
bitfld.long 0x00 2.--3. "  NS_ACCESS1  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID1" "No access,G0S,G0S/G1S,?..."
bitfld.long 0x00 0.--1. " NS_ACCESS0  ,Configures the level of Non-secure access permitted when the SGI is in Secure Group 0 or Secure Group 1 for interrupt ID0" "No access,G0S,G0S/G1S,?..."
NEWLINE
else
hgroup.long 0x10E00++0x03
hide.long 0x00 "GICR_NSACR,Non-secure Access Control Register"
NEWLINE
NEWLINE
NEWLINE
NEWLINE
NEWLINE
endif
rgroup.long 0x1C000++0x03
line.long 0x00 "GICR_MISCSTATUSR,Miscellaneous Status Register"
bitfld.long 0x00 31. " CPU_AS     ,CPU active state. This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read" "Low,High"
bitfld.long 0x00 30. " WAKEREQUEST     ,This bit indicates if a wake request is active" "Not active,Active"
NEWLINE
bitfld.long 0x00 3. "  ENABLEGRP1_S ,EnableGrp1 Secure" "0,1"
bitfld.long 0x00 2. " ENABLEGRP1_S ,EnableGrp1 Secure" "0,1"
NEWLINE
bitfld.long 0x00 1. "     ENABLEGRP1_NS ,EnableGrp1 Non-secure" "0,1"
bitfld.long 0x00 0. " ENABLEGRP0 ,EnableGrp0" "0,1"
NEWLINE
rgroup.long 0x1C008++0x03
line.long 0x00 "GICR_IERRV,Interrupt Error Valid Register"
bitfld.long 0x00 31. "     VALID31 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 30. "     VALID30 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 29. "     VALID29 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 28. "     VALID28 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 27. "     VALID27 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 26. "     VALID26 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 25. "     VALID25 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 24. "     VALID24 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 23. "     VALID23 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 22. "     VALID22 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 21. "     VALID21 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 20. "     VALID20 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 19. "     VALID19 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 18. "     VALID18 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 17. "     VALID17 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 16. "     VALID16 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 15. "     VALID15 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 14. "     VALID14 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 13. "     VALID13 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 12. "     VALID12 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 11. "     VALID11 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 10. "     VALID10 ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 9. "     VALID9  ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 8. "     VALID8  ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 7. "     VALID7  ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 6. "     VALID6  ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 5. "     VALID5  ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 4. "     VALID4  ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 3. "     VALID3  ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 2. "     VALID2  ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
bitfld.long 0x00 1. "     VALID1  ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
bitfld.long 0x00 0. "     VALID0  ,Indicates if there is an error on interrupt so the interrupt is not delivered." "0,1"
NEWLINE
NEWLINE
if ((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x00)||((((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICR",-1.)+0x1C010))))
//(GICD_TYPER.SECURITYEXTN == 1 [Implemented] && Accessed address is secure)
group.quad 0x1C010++0x07
line.quad 0x00 "GICR_SGIDR,SGI Default Register"
bitfld.quad 0x00 62. " GRPMOD16 ,As GRPMOD register." "0,1"
bitfld.quad 0x00 61. "     GRP16 ,As GRP register." "0,1"
bitfld.quad 0x00 60. "     NSACR16 ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 58. " GRPMOD15 ,As GRPMOD register." "0,1"
bitfld.quad 0x00 57. "     GRP15 ,As GRP register." "0,1"
bitfld.quad 0x00 56. "     NSACR15 ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 54. " GRPMOD14 ,As GRPMOD register." "0,1"
bitfld.quad 0x00 53. "     GRP14 ,As GRP register." "0,1"
bitfld.quad 0x00 52. "     NSACR14 ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 50. " GRPMOD13 ,As GRPMOD register." "0,1"
bitfld.quad 0x00 49. "     GRP13 ,As GRP register." "0,1"
bitfld.quad 0x00 48. "     NSACR13 ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 46. " GRPMOD12 ,As GRPMOD register." "0,1"
bitfld.quad 0x00 45. "     GRP12 ,As GRP register." "0,1"
bitfld.quad 0x00 44. "     NSACR12 ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 42. " GRPMOD11 ,As GRPMOD register." "0,1"
bitfld.quad 0x00 41. "     GRP11 ,As GRP register." "0,1"
bitfld.quad 0x00 40. "     NSACR11 ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 38. " GRPMOD10 ,As GRPMOD register." "0,1"
bitfld.quad 0x00 37. "     GRP10 ,As GRP register." "0,1"
bitfld.quad 0x00 36. "     NSACR10 ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 34. " GRPMOD9  ,As GRPMOD register." "0,1"
bitfld.quad 0x00 33. "     GRP9  ,As GRP register." "0,1"
bitfld.quad 0x00 32. "     NSACR9  ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 30. " GRPMOD8  ,As GRPMOD register." "0,1"
bitfld.quad 0x00 29. "     GRP8  ,As GRP register." "0,1"
bitfld.quad 0x00 28. "     NSACR8  ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 26. " GRPMOD7  ,As GRPMOD register." "0,1"
bitfld.quad 0x00 25. "     GRP7  ,As GRP register." "0,1"
bitfld.quad 0x00 24. "     NSACR7  ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 22. " GRPMOD6  ,As GRPMOD register." "0,1"
bitfld.quad 0x00 21. "     GRP6  ,As GRP register." "0,1"
bitfld.quad 0x00 20. "     NSACR6  ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 18. " GRPMOD5  ,As GRPMOD register." "0,1"
bitfld.quad 0x00 17. "     GRP5  ,As GRP register." "0,1"
bitfld.quad 0x00 16. "     NSACR5  ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 14. " GRPMOD4  ,As GRPMOD register." "0,1"
bitfld.quad 0x00 13. "     GRP4  ,As GRP register." "0,1"
bitfld.quad 0x00 12. "     NSACR4  ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 10. " GRPMOD3  ,As GRPMOD register." "0,1"
bitfld.quad 0x00 9. "     GRP3  ,As GRP register." "0,1"
bitfld.quad 0x00 8. "     NSACR3  ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 6. " GRPMOD2  ,As GRPMOD register." "0,1"
bitfld.quad 0x00 5. "     GRP2  ,As GRP register." "0,1"
bitfld.quad 0x00 4. "     NSACR2  ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
bitfld.quad 0x00 2. " GRPMOD1  ,As GRPMOD register." "0,1"
bitfld.quad 0x00 1. "     GRP1  ,As GRP register." "0,1"
bitfld.quad 0x00 0. "     NSACR1  ,Indicates if Non-secure access to interrupt is allowed." "0,1"
NEWLINE
else
hgroup.quad 0x1C010++0x07
hide.quad 0x00 "GICR_SGIDR,SGI Default Register"
endif
rgroup.long 0x1C080++0x03
line.long 0x00 "GICR_PPISR,Private Peripheral Interrupt Status Register"
bitfld.long 0x00 31. "         PPI31S     ,Actual status of the PPI31 input signal" "Low,High"
bitfld.long 0x00 30. "          PPI30S       ,Actual status of the PPI30 input signal" "Low,High"
NEWLINE
bitfld.long 0x00 29. "          PPI29S        ,Actual status of the PPI29 input signal" "Low,High"
bitfld.long 0x00 28. "         PPI28S     ,Actual status of the PPI28 input signal" "Low,High"
NEWLINE
bitfld.long 0x00 27. "          PPI27S       ,Actual status of the PPI27 input signal" "Low,High"
bitfld.long 0x00 26. "          PPI26S        ,Actual status of the PPI26 input signal" "Low,High"
NEWLINE
bitfld.long 0x00 25. "         PPI25S     ,Actual status of the PPI25 input signal" "Low,High"
bitfld.long 0x00 24. "          PPI24S       ,Actual status of the PPI24 input signal" "Low,High"
NEWLINE
bitfld.long 0x00 23. "          PPI23S        ,Actual status of the PPI23 input signal" "Low,High"
bitfld.long 0x00 22. "         PPI22S     ,Actual status of the PPI22 input signal" "Low,High"
NEWLINE
bitfld.long 0x00 21. "          PPI21S       ,Actual status of the PPI21 input signal" "Low,High"
bitfld.long 0x00 20. "          PPI20S        ,Actual status of the PPI20 input signal" "Low,High"
NEWLINE
bitfld.long 0x00 19. "         PPI19S     ,Actual status of the PPI19 input signal" "Low,High"
bitfld.long 0x00 18. "          PPI18S       ,Actual status of the PPI18 input signal" "Low,High"
NEWLINE
bitfld.long 0x00 17. "          PPI17S        ,Actual status of the PPI17 input signal" "Low,High"
bitfld.long 0x00 16. "         PPI16S     ,Actual status of the PPI16 input signal" "Low,High"
rgroup.long 0x1F000++0x03
line.long 0x00 "GICR_CFGID0,Configuration ID0 Register"
bitfld.long 0x00 28.--31. "         AF3WIDTH ,Affinity 3 width." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "          AF2WIDTH ,Affinity 2 width." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
NEWLINE
bitfld.long 0x00 20.--23. "          AF1WIDTH ,Affinity 1 width." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "         AF0WIDTH ,Affinity 0 width." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
NEWLINE
bitfld.long 0x00 12.--15. "          TGT0LISTWIDTH ,The Target0 list width - 1." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "          ECCSUPPORT ,This bit indicates if ECC is supported." "Not supported,Supported"
NEWLINE
hexmask.long.word 0x00 0.--8. 1. "         PPINUMBER  ,RedistributorID. The ppi_id[15:0] tie-off signal sets the value of the ID. Each Redistributor must have a unique ID."
rgroup.long 0x1F004++0x03
line.long 0x00 "GICR_CFGID1,Configuration ID1 Register"
bitfld.long 0x00 28.--31. "         VERSION       ,Identifies the major and minor revisions and product quality status of the GIC-600." "?,Ver0 (r0p0),?,Ver1 (r0p1),Ver2 (r0p2),?..."
hexmask.long.byte 0x00 24.--27. 1. "         USERVALUE       ,Modification value that you can set."
NEWLINE
hexmask.long.byte 0x00 16.--19. 1. "         PPIPERPROC       ,The number of Redistributors that each core supports - 1."
bitfld.long 0x00 12. "         DIRECTUPSTREAM, Indicates a direct upstream connection." "0,1"
NEWLINE
hexmask.long.word 0x00  4.--11. 1. "         NUMCPUS       ,The number of cores that are integrated in this Redistributor."
tree.end
width 12.
tree "Peripheral/Component ID Registers"
rgroup.long 0xFFE0++0x03
line.long 0x00 "GICR_PIDR0,Peripheral ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " PART_0  ,Part number[7:0]"
rgroup.long 0xFFE4++0x03
line.long 0x00 "GICR_PIDR1,Peripheral ID1 Register"
bitfld.long 0x00 4.--7. " DES_1   ,JEP106 identity code [3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        PART_1 ,         Part number[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFE8++0x03
line.long 0x00 "GICR_PIDR2,Peripheral ID2 Register"
bitfld.long 0x00 4.--7. " ARCHREV ,Identifies the version of the GIC architecture with which the GIC-600 complies" "Reserved,Reserved,Reserved,v3.0,?..."
bitfld.long 0x00 3. "  JEDEC  ,Indicates that a JEDEC-assigned JEP106 identity code is used" "Low,High"
bitfld.long 0x00 0.--2. "  DES_1 ,JEP106 identity code [6:4]" "0,1,2,3,4,5,6,7"
rgroup.long 0xFFEC++0x03
line.long 0x00 "GICR_PIDR3,Peripheral ID3 Register"
bitfld.long 0x00 4.--7. " REVAND  ,Manufacturer defined revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        CMOD   ,Indicates if the customer has modified the behavior of the component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xFFD0++0x03
line.long 0x00 "GICR_PIDR4,Peripheral ID4 Register"
bitfld.long 0x00 4.--7. " SIZE    ,64 KB software visible page" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "        DES_2  ,ARM implementation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0xFFD4++0x03
hide.long 0x00 "GICR_PIDR5,Peripheral ID5 Register"
hgroup.long 0xFFD8++0x03
hide.long 0x00 "GICR_PIDR6,Peripheral ID6 Register"
hgroup.long 0xFFDC++0x03
hide.long 0x00 "GICR_PIDR7,Peripheral ID7 Register"
rgroup.long 0xFFF0++0x03
line.long 0x00 "GICR_CIDR0,Component ID0 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF4++0x03
line.long 0x00 "GICR_CIDR1,Component ID1 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFF8++0x03
line.long 0x00 "GICR_CIDR2,Component ID2 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
rgroup.long 0xFFFC++0x03
line.long 0x00 "GICR_CIDR3,Component ID3 Register"
hexmask.long 0x00 0.--7. 1. " FIXVAL  ,ARM-defined fixed values for the preamble for component discovery"
tree.end
tree.end
AUTOINDENT.OFF
sif COMP.AVAILABLE("GICC")
base COMP.BASE("GICC",-1.)
width 14.
tree "CPU Interface"
if (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)&&(PER.ADDRESS.isSECUREEX(COMP.BASE("GICC",-1.)))
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 10. " EOIMODENS     ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 9. "  EOIMODES      ,Controls the behavior of Secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 7. " FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 6. "          IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 4. " CBPR          ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
bitfld.long 0x00 3. "               FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 1. "                   ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
textline "                       "
bitfld.long 0x00 0. " ENABLEGRP0    ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
elif (((per.l(COMP.BASE("GICD",-1.)+0x04))&0x400)==0x400)
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODENS     ,Controls the behavior of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 6. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 0. " ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
else
group.long 0x00++0x03
line.long 0x00 "GICC_CTLR,CPU Interface Control Register"
bitfld.long 0x00 9. " EOIMODE       ,Controls the behavior of accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 8. "  IRQBYPDISGRP1 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
bitfld.long 0x00 7. "          FIQBYPDISGRP1 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 1" "Signaled,Not signaled"
textline "                       "
bitfld.long 0x00 6. " IRQBYPDISGRP0 ,Controls whether the bypass IRQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 5. "          FIQBYPDISGRP0 ,Controls whether the bypass FIQ signal is signaled to the PE for Group 0" "Signaled,Not signaled"
bitfld.long 0x00 4. "          CBPR          ,Controls whether GICC_BPR provides common control of preemption to Group 0 and Group 1 interrupts" "Group 0,Both"
textline "                       "
bitfld.long 0x00 3. " FIQEN         ,Controls whether the CPU interface signals Group 0 interrupts to a target PE using the FIQ or IRQ signal" "IRQ,FIQ"
bitfld.long 0x00 1. "                   ENABLEGRP1    ,Enables the signaling of Group 1 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
bitfld.long 0x00 0. "              ENABLEGRP0    ,Enables the signaling of Group 0 interrupts by the CPU interface to a target PE" "Disabled,Enabled"
endif
textline "                       "
group.long 0x04++0x03
line.long 0x00 "GICC_PMR,Interrupt Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority mask level for CPU interface"
group.long 0x08++0x03
line.long 0x00 "GICC_BPR,Binary Point Register"
bitfld.long 0x00 0.--2. " BP       ,Binary point" "0,1,2,3,4,5,6,7"
hgroup.long 0x0C++0x03
hide.long 0x00 "GICC_IAR,Interrupt Acknowledge Register"
in
wgroup.long 0x10++0x03
line.long 0x00 "GICC_EOIR,End Of Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x14++0x03
line.long 0x00 "GICC_RPR,Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY ,Priority value of highest priority interrupt"
rgroup.long 0x18++0x03
line.long 0x00 "GICC_HPPIR,Highest Priority Pending Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
group.long 0x1C++0x03
line.long 0x00 "GICC_ABPR,Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BP       ,Binary point" "0,1,2,3,4,5,6,7"
hgroup.long 0x20++0x03
hide.long 0x00 "GICC_AIAR,Aliased Interrupt Acknowledge Register"
in
wgroup.long 0x24++0x03
line.long 0x00 "GICC_AEOIR,Aliased End of Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x28++0x03
line.long 0x00 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
rgroup.long 0x2C++0x03
line.long 0x00 "GICC_STATUSR,CPU Interface Status Register"
bitfld.long 0x00 4. " ASV      ,Attempted security violation" "Not detected,Detected"
bitfld.long 0x00 3. "  WROD    ,Write to an RO location" "Not detected,Detected"
bitfld.long 0x00 2. "  RWOD ,Read of a WO location" "Not detected,Detected"
textline "                       "
bitfld.long 0x00 1. " WRD      ,Write to a reserved location" "Not detected,Detected"
bitfld.long 0x00 0. "  RRD     ,Read of a reserved location" "Not detected,Detected"
group.long 0xD0++0x03
line.long 0x00 "GICC_APR0,Active Priorities Register 0"
group.long 0xD4++0x03
line.long 0x00 "GICC_APR1,Active Priorities Register 1"
group.long 0xD8++0x03
line.long 0x00 "GICC_APR2,Active Priorities Register 2"
group.long 0xDC++0x03
line.long 0x00 "GICC_APR3,Active Priorities Register 3"
group.long 0xE0++0x03
line.long 0x00 "GICC_NSAPR0,Non-Secure Active Priorities Register 0"
group.long 0xE4++0x03
line.long 0x00 "GICC_NSAPR1,Non-Secure Active Priorities Register 1"
group.long 0xE8++0x03
line.long 0x00 "GICC_NSAPR2,Non-Secure Active Priorities Register 2"
group.long 0xEC++0x03
line.long 0x00 "GICC_NSAPR3,Non-Secure Active Priorities Register 3"
rgroup.long 0xFC++0x03
line.long 0x00 "GICC_IIDR,CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID   ,Product ID"
bitfld.long 0x00 16.--19. "          ARCHVER ,The version of the GIC architecture that is implemented" ",,,GICv3,?..."
bitfld.long 0x00 12.--15. "         REV  ,Revision number for the CPU interface" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--11. 1. "            IMP ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICC_DIR,Deactivate Interrupt Register"
hexmask.long.tbyte 0x00 0.--23. 1. " INTID    ,Interrupt ID"
tree.end
width 0x0b
endif
sif COMP.AVAILABLE("GICH")
base COMP.BASE("GICH",-1.)
width 13.
tree "Virtual CPU Control Interface"
group.long 0x00++0x03
line.long 0x00 "GICH_HCR,Hypervisor Control Register"
bitfld.long 0x00 27.--31. " EOICOUNT ,Counts the number of EOIs received that do not have a corresponding entry in the List registers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 7. "             VGRP1DIE ,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 6. "      VGRP1EIE ,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 5. "             VGRP0DIE ,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 4. " VGRP0EIE ,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 3. "       NPIE     ,No Pending Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      LRENPIE  ,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled"
bitfld.long 0x00 1. "             UIE      ,Underflow Interrupt Enable" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " EN       ,Virtual CPU interface Enable" "Disabled,Enabled"
rgroup.long 0x04++0x03
line.long 0x00 "GICH_VTR,Virtual Type Register"
bitfld.long 0x00 29.--31. " PRIBITS  ,Number of priority bits" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 26.--28. "              PREBITS  ,Number of pre-emption bits" "1,2,3,4,5,6,7,8"
bitfld.long 0x00 23.--25. "             IDBITS   ,The number of virtual interrupt identifier bits supported" "16 bits,24 bits,?..."
textline "                      "
bitfld.long 0x00 22. " SEIS     ,Indicates whether the virtual CPU interface supports generation of SEIs" "Not supported,Supported"
bitfld.long 0x00 21. "  A3V      ,Affinity 3 valid" "Invalid,Valid"
bitfld.long 0x00 0.--4. "       LISTREGS ,List regs number" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0x08++0x03
line.long 0x00 "GICH_VMCR,Virtual Machine Control Register"
hexmask.long.byte 0x00 24.--31. 1. " VPMR     ,Virtual priority mask"
bitfld.long 0x00 21.--23. "             VBPR0    ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 0)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "             VBPR1    ,Defines the point at which the priority value fields split into two parts the group priority field and the subpriority field (group 1)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 9. "                    VEOIM    ,Virtual EOImode. DP - Drop the priority / ID - interrupt deactivate" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
textline "                      "
bitfld.long 0x00 4. " VCBPR    ,Virtual Common Binary Point Register" "ABPR,BPR"
bitfld.long 0x00 3. "           VFIQEN   ,Virtual FIQ enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      VACKCTL  ,Virtual AckCtl" "INTID=1022,INTID=corresponding"
bitfld.long 0x00 1. "  VENG1    ,Virtual interrupt enable for group 1" "Disabled,Enabled"
textline "                      "
bitfld.long 0x00 0. " VENG0    ,Virtual interrupt enable for group 0" "Disabled,Enabled"
rgroup.long 0x10++0x03
line.long 0x00 "GICH_MISR,Maintenance Interrupt Status Register"
bitfld.long 0x00 7. " VGRP1D   ,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 6. "   VGRP1E   ,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 5. "  VGRP0D   ,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 4. "         VGRP0E   ,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted"
textline "                      "
bitfld.long 0x00 3. " NP       ,No Pending maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 2. "   LRENP    ,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 1. "  U        ,Underflow maintenance interrupt assertion" "Not asserted,Asserted"
bitfld.long 0x00 0. "         EOI      ,End Of Interrupt maintenance interrupt assertion" "Not asserted,Asserted"
rgroup.long 0x20++0x03
line.long 0x00 "GICH_EISR0,End of Interrupt Status Register"
bitfld.long 0x00 15. " STATUS15 ,EOI maintenance interrupt status for List register 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "   STATUS14 ,EOI maintenance interrupt status for List register 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "  STATUS13 ,EOI maintenance interrupt status for List register 13" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 12. " STATUS12 ,EOI maintenance interrupt status for List register 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "   STATUS11 ,EOI maintenance interrupt status for List register 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  STATUS10 ,EOI maintenance interrupt status for List register 10" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 9. " STATUS9  ,EOI maintenance interrupt status for List register 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "   STATUS8  ,EOI maintenance interrupt status for List register 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. "  STATUS7  ,EOI maintenance interrupt status for List register 7" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 6. " STATUS6  ,EOI maintenance interrupt status for List register 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "   STATUS5  ,EOI maintenance interrupt status for List register 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  STATUS4  ,EOI maintenance interrupt status for List register 4" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 3. " STATUS3  ,EOI maintenance interrupt status for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "   STATUS2  ,EOI maintenance interrupt status for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1  ,EOI maintenance interrupt status for List register 1" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 0. " STATUS0  ,EOI maintenance interrupt status for List register 0" "No interrupt,Interrupt"
rgroup.long 0x30++0x03
line.long 0x00 "GICH_ELRSR0,Empty List register Status Register"
bitfld.long 0x00 15. " STATUS15 ,Status bit for List register 15" "No interrupt,Interrupt"
bitfld.long 0x00 14. "   STATUS14 ,Status bit for List register 14" "No interrupt,Interrupt"
bitfld.long 0x00 13. "  STATUS13 ,Status bit for List register 13" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 12. " STATUS12 ,Status bit for List register 12" "No interrupt,Interrupt"
bitfld.long 0x00 11. "   STATUS11 ,Status bit for List register 11" "No interrupt,Interrupt"
bitfld.long 0x00 10. "  STATUS10 ,Status bit for List register 10" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 9. " STATUS9  ,Status bit for List register 9" "No interrupt,Interrupt"
bitfld.long 0x00 8. "   STATUS8  ,Status bit for List register 8" "No interrupt,Interrupt"
bitfld.long 0x00 7. "  STATUS7  ,Status bit for List register 7" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 6. " STATUS6  ,Status bit for List register 6" "No interrupt,Interrupt"
bitfld.long 0x00 5. "   STATUS5  ,Status bit for List register 5" "No interrupt,Interrupt"
bitfld.long 0x00 4. "  STATUS4  ,Status bit for List register 4" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 3. " STATUS3  ,Status bit for List register 3" "No interrupt,Interrupt"
bitfld.long 0x00 2. "   STATUS2  ,Status bit for List register 2" "No interrupt,Interrupt"
bitfld.long 0x00 1. "  STATUS1  ,Status bit for List register 1" "No interrupt,Interrupt"
textline "                      "
bitfld.long 0x00 0. " STATUS0  ,Status bit for List register 0" "No interrupt,Interrupt"
textline "                      "
group.long 0xF0++0x03
line.long 0x00 "GICH_APR0,Active Priorities Register 0"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xF4++0x03
line.long 0x00 "GICH_APR1,Active Priorities Register 1"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xF8++0x03
line.long 0x00 "GICH_APR2,Active Priorities Register 2"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
group.long 0xFC++0x03
line.long 0x00 "GICH_APR3,Active Priorities Register 3"
bitfld.long 0x00 31. "  P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "  P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "  P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "  P28 ,Active Priority 28" "0,1"
textline "                       "
bitfld.long 0x00 27. " P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "  P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "  P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "  P24 ,Active Priority 24" "0,1"
textline "                       "
bitfld.long 0x00 23. " P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "  P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "  P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "  P20 ,Active Priority 20" "0,1"
textline "                       "
bitfld.long 0x00 19. " P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "  P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "  P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "  P16 ,Active Priority 16" "0,1"
textline "                       "
bitfld.long 0x00 15. " P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "  P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "  P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "  P12 ,Active Priority 12" "0,1"
textline "                       "
bitfld.long 0x00 11. " P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "  P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "  P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "  P8  ,Active Priority 8" "0,1"
textline "                       "
bitfld.long 0x00 7. " P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "  P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "  P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "  P4  ,Active Priority 4" "0,1"
textline "                       "
bitfld.long 0x00 3. " P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "  P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "  P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "  P0  ,Active Priority 0" "0,1"
textline "                       "
group.long 0x100++0x03
line.long 0x00 "GICH_LR0,List Register 0"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x104++0x03
line.long 0x00 "GICH_LR1,List Register 1"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x108++0x03
line.long 0x00 "GICH_LR2,List Register 2"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x10C++0x03
line.long 0x00 "GICH_LR3,List Register 3"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x110++0x03
line.long 0x00 "GICH_LR4,List Register 4"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x114++0x03
line.long 0x00 "GICH_LR5,List Register 5"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x118++0x03
line.long 0x00 "GICH_LR6,List Register 6"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x11C++0x03
line.long 0x00 "GICH_LR7,List Register 7"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x120++0x03
line.long 0x00 "GICH_LR8,List Register 8"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x124++0x03
line.long 0x00 "GICH_LR9,List Register 9"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x128++0x03
line.long 0x00 "GICH_LR10,List Register 10"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x12C++0x03
line.long 0x00 "GICH_LR11,List Register 11"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x130++0x03
line.long 0x00 "GICH_LR12,List Register 12"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x134++0x03
line.long 0x00 "GICH_LR13,List Register 13"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
group.long 0x138++0x03
line.long 0x00 "GICH_LR14,List Register 14"
bitfld.long 0x00 31. " HW ,Indicates whether this virtual interrupt is a hardware interrupt" "Software,Hardware"
bitfld.long 0x00 30. "  GROUP ,Indicates whether the interrupt is Group 0 or Group 1" "Group 0,Group 1"
bitfld.long 0x00 28.--29. "  STATE ,The state of the interrupt" "Inactive,Pending,Active,Active/Pending"
bitfld.long 0x00 23.--27. "  PRIORITY ,The priority of this interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.word 0x00 10.--19. 1. "  PINTID ,Physical interrupt ID"
hexmask.long.word 0x00 0.--9. 1. "  VINTID ,Virtual interrupt ID"
tree.end
width 0x0b
endif
sif COMP.AVAILABLE("GICV")
base COMP.BASE("GICV",-1.)
width 14.
tree "Virtual CPU Interface"
group.long 0x00++0x03
line.long 0x00 "GICV_CTLR,VM Control Register"
bitfld.long 0x00 9. " EOIMODE    ,Controls the behaviour of Non-secure accesses to GICC_EOIR/GICC_AEOIR/GICC_DIR. PD - Priority Drop / ID - Interrupt Deactivation" "EOIR+AEOIR=PD+ID,EOIR+AEOIR=PD/DIR=ID"
bitfld.long 0x00 4. "  CBPR       ,Controls whether GICV_BPR affects both Group 0 and Group 1 interrupts" "Group 0,Both"
bitfld.long 0x00 3. "       FIQEN ,FIQ Enable" "Disabled,Enabled"
bitfld.long 0x00 2. "      ACKCTL ,Acknowledge control. Return ID of the corresponding interrupt" "1022,Corresponding"
textline "                      "
bitfld.long 0x00 1. "  ENABLEGRP1 ,Enables the signalling of Group 1 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
bitfld.long 0x00 0. "              ENABLEGRP0 ,Enables the signalling of Group 0 interrupts by the CPU interface to the virtual machine" "Disabled,Enabled"
group.long 0x04++0x03
line.long 0x00 "GICV_PMR,VM Priority Mask Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY   ,Priority mask level for the virtual CPU interface"
group.long 0x08++0x03
line.long 0x00 "GICV_BPR,VM Binary Point Register"
bitfld.long 0x00 0.--2. " BP         ,Binary point" "0,1,2,3,4,5,6,7"
rgroup.long 0x0C++0x03
line.long 0x00 "GICV_IAR,VM Interrupt Acknowledge Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
wgroup.long 0x10++0x03
line.long 0x00 "GICV_EOIR,VM End Of Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
rgroup.long 0x14++0x03
line.long 0x00 "GICV_RPR,VM Running Priority Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITY   ,Priority value of highest priority interrupt"
rgroup.long 0x18++0x03
line.long 0x00 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
group.long 0x1C++0x03
line.long 0x00 "GICV_ABPR,VM Aliased Binary Point Register"
bitfld.long 0x00 0.--2. " BP         ,Binary point" "0,1,2,3,4,5,6,7"
rgroup.long 0x20++0x03
line.long 0x00 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
wgroup.long 0x24++0x03
line.long 0x00 "GICV_AEOIR,VM Aliased End of Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
rgroup.long 0x28++0x03
line.long 0x00 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
textline ""
group.long 0xD0++0x03
line.long 0x00 "GICV_APR0,VM Active Priority Register 0"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xD4++0x03
line.long 0x00 "GICV_APR1,VM Active Priority Register 1"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xD8++0x03
line.long 0x00 "GICV_APR2,VM Active Priority Register 2"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
group.long 0xDC++0x03
line.long 0x00 "GICV_APR3,VM Active Priority Register 3"
bitfld.long 0x00 31. " P31 ,Active Priority 31" "0,1"
bitfld.long 0x00 30. "   P30 ,Active Priority 30" "0,1"
bitfld.long 0x00 29. "   P29 ,Active Priority 29" "0,1"
bitfld.long 0x00 28. "   P28 ,Active Priority 28" "0,1"
textline "                      "
bitfld.long 0x00 27. "  P27 ,Active Priority 27" "0,1"
bitfld.long 0x00 26. "   P26 ,Active Priority 26" "0,1"
bitfld.long 0x00 25. "   P25 ,Active Priority 25" "0,1"
bitfld.long 0x00 24. "   P24 ,Active Priority 24" "0,1"
textline "                      "
bitfld.long 0x00 23. "  P23 ,Active Priority 23" "0,1"
bitfld.long 0x00 22. "   P22 ,Active Priority 22" "0,1"
bitfld.long 0x00 21. "   P21 ,Active Priority 21" "0,1"
bitfld.long 0x00 20. "   P20 ,Active Priority 20" "0,1"
textline "                      "
bitfld.long 0x00 19. "  P19 ,Active Priority 19" "0,1"
bitfld.long 0x00 18. "   P18 ,Active Priority 18" "0,1"
bitfld.long 0x00 17. "   P17 ,Active Priority 17" "0,1"
bitfld.long 0x00 16. "   P16 ,Active Priority 16" "0,1"
textline "                      "
bitfld.long 0x00 15. "  P15 ,Active Priority 15" "0,1"
bitfld.long 0x00 14. "   P14 ,Active Priority 14" "0,1"
bitfld.long 0x00 13. "   P13 ,Active Priority 13" "0,1"
bitfld.long 0x00 12. "   P12 ,Active Priority 12" "0,1"
textline "                      "
bitfld.long 0x00 11. "  P11 ,Active Priority 11" "0,1"
bitfld.long 0x00 10. "   P10 ,Active Priority 10" "0,1"
bitfld.long 0x00 9. "   P9  ,Active Priority 9" "0,1"
bitfld.long 0x00 8. "   P8  ,Active Priority 8" "0,1"
textline "                      "
bitfld.long 0x00 7. "  P7  ,Active Priority 7" "0,1"
bitfld.long 0x00 6. "   P6  ,Active Priority 6" "0,1"
bitfld.long 0x00 5. "   P5  ,Active Priority 5" "0,1"
bitfld.long 0x00 4. "   P4  ,Active Priority 4" "0,1"
textline "                      "
bitfld.long 0x00 3. "  P3  ,Active Priority 3" "0,1"
bitfld.long 0x00 2. "   P2  ,Active Priority 2" "0,1"
bitfld.long 0x00 1. "   P1  ,Active Priority 1" "0,1"
bitfld.long 0x00 0. "   P0  ,Active Priority 0" "0,1"
textline "                      "
rgroup.long 0xFC++0x03
line.long 0x00 "GICV_IIDR,Virtual Machine CPU Interface Identification Register"
hexmask.long.word 0x00 20.--31. 1. " PRODID     ,Product ID"
bitfld.long 0x00 16.--19. "    ARCHVER ,The version of the GIC architecture that is implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "  REV ,Revision number for the CPU interface" ",,,GICv3,?..."
hexmask.long.word 0x00 0.--11. 1. "  IMP ,Implementer"
wgroup.long 0x1000++0x03
line.long 0x00 "GICV_DIR,VM Deactivate Interrupt Register"
hexmask.long 0x00 0.--24. 1. " INTID      ,Interrupt ID"
tree.end
width 0x0b
endif
width 0x0B
AUTOINDENT.POP
tree.end
tree.end
endif
tree "CCU (Cache Coherency Unit)"
base ad:0x0
rgroup.long 0x1C000000++0x7
line.long 0x0 "CAIUIDR,AIU Identification Register"
bitfld.long 0x0 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the AIU is implemented." "0,1"
newline
hexmask.long.byte 0x0 24.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x0 12.--23. 1. "NUnitId,Ncore 3 Unit identifier."
newline
hexmask.long.byte 0x0 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this AIU resides"
newline
hexmask.long.byte 0x0 0.--7. 1. "RPN,AIU Register Page Number (within its NRR)"
line.long 0x4 "CAIUFUIDR,AIU Fabric Unit Identification Register"
hexmask.long.word 0x4 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x4 0.--15. 1. "FUnitId,Fabric Unit Identifier of the unit"
group.long 0x1C000040++0x3
line.long 0x0 "CAIUTCR,AIU Transaction Control Register"
hexmask.long.tbyte 0x0 10.--31. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x0 9. "SysCoAttach,Writing 1 to this bit when the status register bit SysCoAttached is 0 starts an attach sequence. Writing 0 to this bit when the status register bit SysCoAttached is 1 starts a detach sequence." "0,1"
newline
bitfld.long 0x0 8. "SysCoDisable,Setting this disables SysCo." "0,1"
newline
rbitfld.long 0x0 5.--7. "Rsvd2,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "EventDisable,Setting this disables Event handling." "0,1"
newline
rbitfld.long 0x0 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "RDisable,This controls whether new requests can be accepted inside the AIU." "0,1"
rgroup.long 0x1C000044++0x3
line.long 0x0 "CAIUTAR,AIU Transaction Activity Register"
hexmask.long 0x0 7.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 6. "SysCoError,1 indicates Error was detected during previous or current SysCo event. This bit clears itself when the SysCo process triggers next time." "0,1"
newline
bitfld.long 0x0 5. "SysCoAttached,1 indicates that SysCo is Attached; 0 indicates it is detached." "0,1"
newline
bitfld.long 0x0 4. "SysCoConnecting,1 indicates that SysCo is in the process of connecting." "0,1"
newline
bitfld.long 0x0 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when AIU is performing any activity related to native agent transactions." "0,1"
group.long 0x1C000100++0x17
line.long 0x0 "CAIUUEDR,Unit Uncorrectable Error Detect Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 4. "TimeoutErrDetEn,Timeout protection error detection enable: When set  timeout errors will be detected." "0,1"
newline
bitfld.long 0x0 3. "DecErrDetEn,Decode Error Enable. When set  this bit enables detection of address map uncorrectable error" "0,1"
newline
bitfld.long 0x0 2. "MemErrDetEn,Memory protection error detection enable: When set errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "CAIUUEIR,CAIU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 4. "TimeOutErrIntEn,Time Out Error Interrupt Enable. When set to 1  this bit enables the assertion of Time Out Error Interrupt signal." "0,1"
newline
bitfld.long 0x4 3. "DecErrIntEn,Decode Error Interrupt Enable. When set  this bit enables the assertion of address map Uncorrectable Error Interrupt signal." "0,1"
newline
bitfld.long 0x4 2. "MemErrIntEn,Memory protection error interrupt enable: When set  errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport error interrupt enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "CAIUUESR,AIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "CAIUUELR0,AIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "CAIUUELR1,AIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "CAIUUESAR,AIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C000180++0x3
line.long 0x0 "CAIUCRTR,AIU Correctable Resiliency Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "ResThreshold,Threshold for the correctable error indication to the functional safety controller."
group.long 0x1C000190++0x3
line.long 0x0 "CAIUTOCR,CAIU Timeout Control Register"
bitfld.long 0x0 31. "TimeOutRefEn,Set to use reference singal input instead of counting every 4K cycle" "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TimeOutThreshold,Time out threshold value; counts in increments of 4K cycles."
group.long 0x1C000200++0x7
line.long 0x0 "CAIUQOSCR,CAIU QoS Control Register"
hexmask.long.word 0x0 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "EventThreshold,Event threshold value counts every event (command issues) if value is 0 event count is disabled (event starvation disabled)."
line.long 0x4 "CAIUQOSSR,CAIU QoS Status Register"
hexmask.long.word 0x4 20.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.word 0x4 4.--19. 1. "EventStatusCount,Counts number of times event threshold was hit"
newline
rbitfld.long 0x4 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
eventfld.long 0x4 1. "EventStatusCountOverflow,Event count overflow bit  this bit is set once the counter overflows" "0,1"
newline
rbitfld.long 0x4 0. "EventStatus,0: Normal Mode" "0: Normal Mode,1: Starvation Mode"
group.long 0x1C000380++0xB
line.long 0x0 "NRSBAR,NRS Base Address Register"
hexmask.long 0x0 0.--31. 1. "NRSBA,NRSBA field indicates bits[51:20] of the Base address of the Ncore Register Space"
line.long 0x4 "NRSBHR,NRS Base Address Hold Register"
hexmask.long 0x4 0.--31. 1. "NRSBA,NRSBA field indicates bits[51:20] of the Base address of the Ncore Register Space"
line.long 0x8 "NRSBLR,NRS Base Address Load Register"
bitfld.long 0x8 31. "BALoaded,This field is set when NRSBHR is stored into and reset when this register is read" "0,1"
newline
hexmask.long.tbyte 0x8 14.--30. 1. "Rsvd2,Reserved"
newline
hexmask.long.word 0x8 4.--13. 1. "NRSDIIId,This field is set to NUId of the DII to which the Ncore is connected"
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "Secure,If this bit is set  only a secure access can update the NRSBHR register with a Write and only a secure access can load the NRSBAR. If the bit is not set  either a secure or non secure access can update NRSBHR and load the NRSBAR" "0,1"
group.long 0x1C000390++0xB
line.long 0x0 "CAIUBRAR,Boot Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: DMI  1:DII" "0: DMI,1: DII"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.word 0x0 0.--8. 1. "Rsvd1,Reserved"
line.long 0x4 "CAIUBRBLR,Boot Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUBRBHR,Boot Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0003C0++0x7
line.long 0x0 "CAIUAMIGR,Active Memory Interleave Group Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 1.--4. 1. "AMIGS,Active Memory Interleave Group Set in use currenlty when Valid is set"
newline
bitfld.long 0x0 0. "Valid,Memory Interleave Group Set valid  when set the MIGS specified in AMIGS field is being used for DMI interleaving else MIGS 0 is used by default" "0,1"
line.long 0x4 "CAIUMIFSR,Memory Interleave Function Select Register"
hexmask.long.byte 0x4 27.--31. 1. "Rsvd5,Reserved"
newline
bitfld.long 0x4 24.--26. "MIG16AIFId,Active function ID for 16 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 19.--23. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x4 16.--18. "MIG8AIFId,Active function ID for 8 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 11.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x4 8.--10. "MIG4AIFId,Active function ID for 4 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 7. "Rsvd2,Reserved" "0,1"
newline
bitfld.long 0x4 4.--6. "MIG3AIFId,Active function ID for 3 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x4 0.--2. "MIG2AIFId,Active function ID for 2 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
group.long 0x1C000400++0xB
line.long 0x0 "CAIUGPRAR0,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR0,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR0,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C000410++0xB
line.long 0x0 "CAIUGPRAR1,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR1,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR1,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C000420++0xB
line.long 0x0 "CAIUGPRAR2,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR2,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR2,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C000430++0xB
line.long 0x0 "CAIUGPRAR3,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR3,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR3,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C000440++0xB
line.long 0x0 "CAIUGPRAR4,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR4,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR4,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C000450++0xB
line.long 0x0 "CAIUGPRAR5,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR5,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR5,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C000460++0xB
line.long 0x0 "CAIUGPRAR6,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR6,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR6,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C000470++0xB
line.long 0x0 "CAIUGPRAR7,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR7,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR7,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C000480++0xB
line.long 0x0 "CAIUGPRAR8,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR8,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR8,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C000490++0xB
line.long 0x0 "CAIUGPRAR9,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR9,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR9,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0004A0++0xB
line.long 0x0 "CAIUGPRAR10,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR10,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR10,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0004B0++0xB
line.long 0x0 "CAIUGPRAR11,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "CAIUGPRBLR11,General Purpose Region Base Address Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "CAIUGPRBHR11,General Purpose Region Base Address High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C000900++0x1F
line.long 0x0 "CAIUCCTRLR,AIU Unit Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
line.long 0x4 "CAIUTCTRLR0,XAIU Trace Trigger Control Register"
hexmask.long.byte 0x4 28.--31. 1. "memattr,Specifies memory attribute. Memattr on CHI  AxCache on AXI/ACE/ACE-Lite/ACE-Lite-E"
newline
hexmask.long.byte 0x4 24.--27. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x4 19.--23. 1. "range,Address range size. This field indicates a binary number from 0 to 31 from which region's size is calculated as (Size of IG) * 2^(Size + 12) bytes"
newline
hexmask.long.byte 0x4 12.--18. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x4 7.--11. 1. "hui,Specifies the HUI NunItID for DII  and MIG number for DMI"
newline
bitfld.long 0x4 6. "hut,Specify target type. 0: DMI  1: DII" "0: DMI,1: DII"
newline
bitfld.long 0x4 5. "target_type_match_en,Enable Trace if there is a match on specified target type" "0,1"
newline
bitfld.long 0x4 4. "user_match_en,Enable Trace if there is a match on specified user bits" "0,1"
newline
bitfld.long 0x4 3. "memattr_match_en,Enable Trace on memory attribute match" "0,1"
newline
bitfld.long 0x4 2. "opcode_match_en,Enable Trace on opcode match" "0,1"
newline
bitfld.long 0x4 1. "addr_match_en,Enable Trace on address range match" "0,1"
newline
bitfld.long 0x4 0. "native_trace_en,0: Ignore native trace signaling. 1: Allow native trace signaling to set trigger" "0: Ignore native trace signaling,1: Allow native trace signaling to set trigger"
line.long 0x8 "CAIUTBALR0,AIU Trace Trigger Base Address Low Register"
hexmask.long 0x8 0.--31. 1. "base_addr_lo,Lower order bits 43:12 of the base address of the region"
line.long 0xC "CAIUTBAHR0,AIU Trace Trigger Base Address High Register"
hexmask.long.tbyte 0xC 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0xC 0.--7. 1. "base_addr_hi,Lower order bits 51:44 of the base address of the region"
line.long 0x10 "CAIUTOPCR00,AIU Trace Trigger Opcode Register"
bitfld.long 0x10 31. "valid2,Valid 2" "0,1"
newline
hexmask.long.word 0x10 22.--30. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x10 16.--21. 1. "opcode2,Opcode 2"
newline
bitfld.long 0x10 15. "valid1,Valid 1" "0,1"
newline
hexmask.long.word 0x10 6.--14. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x10 0.--5. 1. "opcode1,Opcode 1"
line.long 0x14 "CAIUTOPCR10,AIU Trace Trigger Opcode Register"
bitfld.long 0x14 31. "valid4,Valid 4" "0,1"
newline
hexmask.long.word 0x14 22.--30. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 16.--21. 1. "opcode4,Opcode 4"
newline
bitfld.long 0x14 15. "valid3,Valid 3" "0,1"
newline
hexmask.long.word 0x14 6.--14. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x14 0.--5. 1. "opcode3,Opcode 3"
line.long 0x18 "CAIUTUBR0,AIU Trace Trigger User Bits Register"
hexmask.long 0x18 4.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x18 0.--3. 1. "user,User bits. Width parameterized."
line.long 0x1C "CAIUTUBMR0,AIU Trace Trigger User Bits Mask Register"
hexmask.long 0x1C 4.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x1C 0.--3. 1. "user_mask,User bits. Width parameterized."
group.long 0x1C000B00++0xB
line.long 0x0 "CAIUCNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "CAIUCNTVR0,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "CAIUCNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C000B10++0xB
line.long 0x0 "CAIUCNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "CAIUCNTVR1,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "CAIUCNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C000B20++0xB
line.long 0x0 "CAIUCNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "CAIUCNTVR2,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "CAIUCNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C000B30++0xB
line.long 0x0 "CAIUCNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "CAIUCNTVR3,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "CAIUCNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C000FF0++0x3
line.long 0x0 "CAIUNRSAR,CAIU Ncore Register Space Attribute Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "NRSAR,Set high to enable CSR access via this AIU." "0,1"
rgroup.long 0x1C000FF4++0x3
line.long 0x0 "CAIUUEVIR,AIU Unit Engineering Version Id Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C000FFC++0xB
line.long 0x0 "CAIUINFOR,AIU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 19.--30. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 16.--18. "UST,Unit Type" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "XAIUIDR,XAIU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the unit is implemented." "0,1"
newline
hexmask.long.word 0x4 15.--30. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 12.--14. "NUnitId,Ncore 3 Unit identifier." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this unit resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,XAIU Register Page Number (within its NRR)"
line.long 0x8 "XAIUFUIDR,XAIU Fabric Unit Identification Register"
hexmask.long 0x8 4.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--3. 1. "FUnitId,Fabric Unit Identifier of the unit"
group.long 0x1C001040++0x3
line.long 0x0 "XAIUTCR,Transaction Control Register"
hexmask.long.word 0x0 20.--31. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x0 18.--19. "TransOrderModeWr,This setting controls transaction ordering based on AXI ID" "0: Reserved,1: Resreved,2: PCIe ordering rules,3: Strict request ordering mode"
newline
bitfld.long 0x0 16.--17. "TransOrderModeRd,This setting controls transaction ordering based on AXI ID" "0: Reserved,1: Reserved,2: PCIe ordering rules,3: Strict request ordering mode"
newline
hexmask.long.byte 0x0 10.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x0 9. "SysCoAttach,Writing 1 to this bit when the status register bit SysCoAttached is 0 starts an attach sequence. Writing 0 to this bit when the status register bit SysCoAttached is 1 starts a detach sequence." "0,1"
newline
bitfld.long 0x0 8. "SysCoDisable,Setting this disables SysCo." "0,1"
newline
rbitfld.long 0x0 5.--7. "Rsvd2,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "EventDisable,Setting this disables Event handling." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "Rsvd1,Reserved"
rgroup.long 0x1C001044++0x3
line.long 0x0 "XAIUTAR,Transaction Activity Register"
hexmask.long 0x0 7.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 6. "SysCoError,1 indicates Error was detected during previous or current SysCo event. This bit clears itself when the SysCo process triggers next time." "0,1"
newline
bitfld.long 0x0 5. "SysCoAttached,1 indicates that SysCo is Attached; 0 indicates it is detached." "0,1"
newline
bitfld.long 0x0 4. "SysCoConnecting,1 indicates that SysCo is in the process of connecting." "0,1"
newline
bitfld.long 0x0 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the Unit." "0,1"
group.long 0x1C001100++0x17
line.long 0x0 "XAIUUEDR,Unit Uncorrectable Error Detect Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 4. "TimeoutErrDetEn,Timeout protection error detection enable: When set  timeout errors will be detected." "0,1"
newline
bitfld.long 0x0 3. "DecErrDetEn,Decode Error Enable. When set  this bit enables detection of address map uncorrectable error" "0,1"
newline
bitfld.long 0x0 2. "MemErrDetEn,Memory protection error detection enable: When set errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "XAIUUEIR,Unit Uncorrectable Error Interrupt Register"
hexmask.long 0x4 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 4. "TimeoutErrIntEn,Timeout uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 3. "DecErrIntEn,Decode Error Interrupt Enable. When set  this bit enables the assertion of address map Uncorrectable Error Interrupt signal" "0,1"
newline
bitfld.long 0x4 2. "MemErrIntEn,RAM memory uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "XAIUUESR,XAIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "XAIUUELR0,XAIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "XAIUUELR1,XAIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "XAIUUESAR,XAIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C001140++0x13
line.long 0x0 "XAIUCECR,XAIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,This field determines the number of correctable errors that must be corrected before the Correctable Error Interrupt output signal is asserted."
newline
rbitfld.long 0x0 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,If this bit is set  the Correctable Error Interrupt output signal is asserted when the number of correctable errors corrected equals the value in ErrThreshold field; otherwise  the correctable error interrupt signal is never asserted." "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,If this bit is set  then correctable error detection and logging is enabled; otherwise  correctable error detection and logging is disabled." "0,1"
line.long 0x4 "XAIUCESR,XAIU Correctable Error Status Register"
hexmask.long.word 0x4 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Correctable Error Valid bit is set."
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,This field indicates the logged error type  if the Correctable Error Valid bit is set."
newline
rbitfld.long 0x4 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 2.--9. 1. "ErrCount,This field indicates the number of correctable errors detected by the unit. The field stops incrementing if the Correctable Error Count Overflow bit is set"
newline
rbitfld.long 0x4 1. "ErrCountOverflow,This bit indicates that the number of correctable errors detected by the unit overflowed the Correctable Error Count field" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Correctable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0x8 "XAIUCELR0,XAIU Correctable Error Location Registers 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0xC "XAIUCELR1,XAIU Correctable Error Location Registers 1"
hexmask.long.word 0xC 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x10 "XAIUCESAR,XAIU Correctable Error Status Alias Register"
hexmask.long.word 0x10 16.--31. 1. "ErrInfo,Alias bit for setting error info field of xCESR"
newline
hexmask.long.byte 0x10 12.--15. 1. "ErrType,Alias bit for setting error type field of xCESR"
newline
rbitfld.long 0x10 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x10 2.--9. 1. "ErrCount,Alias field for setting error Count field of xCESR"
newline
bitfld.long 0x10 1. "ErrCountOverflow,Alias bit for ssetting Error Count Overflow field of xCESR" "0,1"
newline
bitfld.long 0x10 0. "ErrVld,Alias bit for setting error valid field of xCESR" "0,1"
group.long 0x1C00117C++0x3
line.long 0x0 "XAIUCRTR,XAIU Correctable Resiliency Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "ResThreshold,Threshold for the correctable error indication to the functional safety controller."
group.long 0x1C001190++0x3
line.long 0x0 "XAIUTOCR,XAIU Timeout Control Register"
bitfld.long 0x0 31. "TimeOutRefEn,Set to use reference singal input instead of counting every 4K cycle" "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TimeOutThreshold,Time out threshold value; counts in increments of 4K cycles."
group.long 0x1C001200++0x7
line.long 0x0 "XAIUQOSCR,XAIU QoS Control Register"
hexmask.long.word 0x0 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "EventThreshold,Event threshold value counts every event (command issues) if value is 0 event count is disabled (event starvation disabled)."
line.long 0x4 "XAIUQOSSR,XAIU QoS Status Register"
hexmask.long.word 0x4 20.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.word 0x4 4.--19. 1. "EventStatusCount,Counts number of times event threshold was hit"
newline
rbitfld.long 0x4 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
eventfld.long 0x4 1. "EventStatusCountOverflow,Event count overflow bit  this bit is set once the counter overflows" "0,1"
newline
rbitfld.long 0x4 0. "EventStatus,0: Normal Mode" "0: Normal Mode,1: Starvation Mode"
rgroup.long 0x1C001380++0x3
line.long 0x0 "XAIUNRSBAR,NRS Base Address Register"
hexmask.long 0x0 0.--31. 1. "NRSBA,NRSBA"
group.long 0x1C001384++0x3
line.long 0x0 "XAIUNRSBHR,NRS Base Address Hold Register"
hexmask.long 0x0 0.--31. 1. "NRSBA,NRSBA field indicates bits[51:20] of the Base address of the Ncore Register Space"
rgroup.long 0x1C001388++0x3
line.long 0x0 "XAIUNRSBLR,NRS Base Address Load Register"
bitfld.long 0x0 31. "BALoaded,This field is set when NRSBHR is stored into and reset when this register is read" "0,1"
newline
hexmask.long.tbyte 0x0 14.--30. 1. "Rsvd2,Reserved"
newline
hexmask.long.word 0x0 4.--13. 1. "NRSDIIId,This field is set to NUId of the DII to which the Ncore is connected"
newline
hexmask.long.byte 0x0 0.--3. 1. "Rsvd1,Reserved"
group.long 0x1C0013A0++0xB
line.long 0x0 "XAIUBRAR,Boot Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: DMI  1:DII" "0: DMI,1: DII"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.word 0x0 0.--8. 1. "Rsvd1,Reserved"
line.long 0x4 "XAIUBRBLR,Boot Region Base Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUBRBHR,Boot Region Base High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0013C0++0x7
line.long 0x0 "XAIUAMIGR,Active Memory Interleave Group Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 1.--4. 1. "AMIGS,Active Memory Interleave Group Set in use currenlty when Valid is set"
newline
bitfld.long 0x0 0. "Valid,Memory Interleave Group Set valid  when set the MIGS specified in AMIGS field is being used for DMI interleaving else MIGS 0 is used by default" "0,1"
line.long 0x4 "XAIUMIFSR,Memory Interleave Function Select Register"
hexmask.long.byte 0x4 27.--31. 1. "Rsvd5,Reserved"
newline
bitfld.long 0x4 24.--26. "MIG16AIFId,Active function ID for 16 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 19.--23. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x4 16.--18. "MIG8AIFId,Active function ID for 8 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 11.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x4 8.--10. "MIG4AIFId,Active function ID for 4 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 7. "Rsvd2,Reserved" "0,1"
newline
bitfld.long 0x4 4.--6. "MIG3AIFId,Active function ID for 3 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x4 0.--2. "MIG2AIFId,Active function ID for 2 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
group.long 0x1C001400++0xB
line.long 0x0 "XAIUGPRAR0,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR0,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR0,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C001410++0xB
line.long 0x0 "XAIUGPRAR1,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR1,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR1,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C001420++0xB
line.long 0x0 "XAIUGPRAR2,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR2,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR2,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C001430++0xB
line.long 0x0 "XAIUGPRAR3,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR3,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR3,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C001440++0xB
line.long 0x0 "XAIUGPRAR4,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR4,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR4,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C001450++0xB
line.long 0x0 "XAIUGPRAR5,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR5,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR5,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C001460++0xB
line.long 0x0 "XAIUGPRAR6,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR6,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR6,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C001470++0xB
line.long 0x0 "XAIUGPRAR7,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR7,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR7,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C001480++0xB
line.long 0x0 "XAIUGPRAR8,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR8,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR8,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C001490++0xB
line.long 0x0 "XAIUGPRAR9,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR9,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR9,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0014A0++0xB
line.long 0x0 "XAIUGPRAR10,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR10,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR10,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0014B0++0xB
line.long 0x0 "XAIUGPRAR11,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR11,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR11,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C001808++0x17
line.long 0x0 "XAIUTBALR0,XAIU Trace Trigger Base Address Low Register"
hexmask.long 0x0 0.--31. 1. "base_addr_lo,Lower order bits 43:12 of the base address of the region"
line.long 0x4 "XAIUTBAHR0,XAIU Trace Trigger Base Address High Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x4 0.--7. 1. "base_addr_hi,Lower order bits 51:44 of the base address of the region"
line.long 0x8 "XAIUTOPCR00,XAIU Trace Trigger Opcode Register"
bitfld.long 0x8 31. "valid2,Valid 2" "0,1"
newline
hexmask.long.word 0x8 16.--30. 1. "opcode2,Opcode 2"
newline
bitfld.long 0x8 15. "valid1,Valid 1" "0,1"
newline
hexmask.long.word 0x8 0.--14. 1. "opcode1,Opcode 1"
line.long 0xC "XAIUTOPCR10,XAIU Trace Trigger Opcode Register"
bitfld.long 0xC 31. "valid4,Valid 4" "0,1"
newline
hexmask.long.word 0xC 16.--30. 1. "opcode4,Opcode 4"
newline
bitfld.long 0xC 15. "valid3,Valid 3" "0,1"
newline
hexmask.long.word 0xC 0.--14. 1. "opcode3,Opcode 3"
line.long 0x10 "XAIUTUBR0,XAIU Trace Trigger User Bits Register"
hexmask.long 0x10 0.--31. 1. "user,User bits. Width parameterized."
line.long 0x14 "XAIUTUBMR0,XAIU Trace Trigger User Bits Mask Register"
hexmask.long 0x14 0.--31. 1. "user_mask,User bits. Width parameterized."
group.long 0x1C001900++0x7
line.long 0x0 "XAIUCCTRLR,XAIU Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
line.long 0x4 "XAIUTCTRLR0,XAIU Trace Trigger Control Register"
hexmask.long.byte 0x4 28.--31. 1. "memattr,Specifies memory attribute. Memattr on CHI  AxCache on AXI/ACE/ACE-Lite/ACE-Lite-E"
newline
bitfld.long 0x4 27. "ar,Match memattr on AR channel" "0,1"
newline
bitfld.long 0x4 26. "aw,Match memattr on AW channel" "0,1"
newline
rbitfld.long 0x4 24.--25. "Rsvd2,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 19.--23. 1. "range,Address range size. This field indicates a binary number from 0 to 31 from which region's size is calculated as (Size of IG) * 2^(Size + 12) bytes"
newline
hexmask.long.byte 0x4 12.--18. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x4 7.--11. 1. "hui,Specifies the HUI NunItID for DII  and MIG number for DII"
newline
bitfld.long 0x4 6. "hut,Specify target type. 0: DMI  1: DII" "0: DMI,1: DII"
newline
bitfld.long 0x4 5. "target_type_match_en,Enable Trace if there is a match on specified target type" "0,1"
newline
bitfld.long 0x4 4. "user_match_en,Enable Trace if there is a match on specified user bits" "0,1"
newline
bitfld.long 0x4 3. "memattr_match_en,Enable Trace on memory attribute match" "0,1"
newline
bitfld.long 0x4 2. "opcode_match_en,Enable Trace on opcode match" "0,1"
newline
bitfld.long 0x4 1. "addr_match_en,Enable Trace on address range match" "0,1"
newline
bitfld.long 0x4 0. "native_trace_en,0: Ignore native trace signaling. 1: Allow native trace signaling to set trigger" "0: Ignore native trace signaling,1: Allow native trace signaling to set trigger"
group.long 0x1C001A00++0x1F
line.long 0x0 "XAIUEDR0,Credit on a per message type basis."
hexmask.long.byte 0x0 24.--31. 1. "MRW,DTW credit."
newline
hexmask.long.byte 0x0 16.--23. 1. "MRR,DTR credit."
newline
hexmask.long.byte 0x0 8.--15. 1. "MRU,Update credit."
newline
hexmask.long.byte 0x0 0.--7. 1. "MRC,Command credit."
line.long 0x4 "XAIUEDR1,Hardware control debug register."
hexmask.long 0x4 0.--31. 1. "cfg,Hardware control."
line.long 0x8 "XAIUEDR2,OTT pools."
hexmask.long.byte 0x8 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 16.--23. 1. "RD,OTT Read pool."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "WR,OTT Write pool."
line.long 0xC "XAIUEDR3,Limit OTT/STT sizes."
hexmask.long.byte 0xC 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0xC 16.--23. 1. "STT,STT Limit."
newline
hexmask.long.byte 0xC 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0xC 0.--7. 1. "OTT,OTT limit."
line.long 0x10 "XAIUEDR4,Limit Read/Write operations."
hexmask.long.byte 0x10 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x10 16.--23. 1. "RD,OTT Read Limit."
newline
hexmask.long.byte 0x10 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x10 0.--7. 1. "WR,OTT Write limit."
line.long 0x14 "XAIUEDR5,Limit evictions."
hexmask.long.tbyte 0x14 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x14 0.--7. 1. "EV,Limit evictions."
line.long 0x18 "XAIUEDR6,Credit adjustment per target type basis: 0x1: Max 1. 0x2: Max 2. 0x3: Max 3. 0x5: Minus 1. 0x6: Minus 2. 0x7: Minus 3. 0x9: 1 read others writes. 0xa: Reserve 1 write. 0xb: No limit. 0xd: reserve 1 extra write. 0xe: reserve 2 extra writes. 0xf:.."
hexmask.long.word 0x18 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x18 16.--19. 1. "QOS,QOS credit adjustment."
newline
hexmask.long.byte 0x18 12.--15. 1. "DVE,DVE credit adjustment."
newline
hexmask.long.byte 0x18 8.--11. 1. "DII,DII credit adjustment."
newline
hexmask.long.byte 0x18 4.--7. 1. "DMI,DMI credit adjustment."
newline
hexmask.long.byte 0x18 0.--3. 1. "DCE,DCE credit adjustment."
line.long 0x1C "XAIUEDR7,Specify period length for starvation detection"
hexmask.long.tbyte 0x1C 12.--31. 1. "TIME,Timer period in granularity of 2K."
newline
hexmask.long.word 0x1C 0.--11. 1. "EVENT,Event counter period in granularity of 16."
group.long 0x1C001B00++0xB
line.long 0x0 "XAIUCNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR0,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C001B10++0xB
line.long 0x0 "XAIUCNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR1,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C001B20++0xB
line.long 0x0 "XAIUCNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR2,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C001B30++0xB
line.long 0x0 "XAIUCNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR3,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C001FF0++0x3
line.long 0x0 "XAIUNRSAR,CAIU Ncore Register Space Attribute Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "NRSAR,Set high to enable CSR access via this AIU." "0,1"
rgroup.long 0x1C001FF4++0x3
line.long 0x0 "XAIUENGIDR,XAIU Engineering ID Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C001FFC++0xB
line.long 0x0 "XAIUINFOR,XAIU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 20.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 16.--19. 1. "UST,Unit Type"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "XAIUIDR,XAIU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the unit is implemented." "0,1"
newline
hexmask.long.word 0x4 15.--30. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 12.--14. "NUnitId,Ncore 3 Unit identifier." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this unit resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,XAIU Register Page Number (within its NRR)"
line.long 0x8 "XAIUFUIDR,XAIU Fabric Unit Identification Register"
hexmask.long 0x8 4.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--3. 1. "FUnitId,Fabric Unit Identifier of the unit"
group.long 0x1C002040++0x3
line.long 0x0 "XAIUTCR,Transaction Control Register"
hexmask.long.word 0x0 20.--31. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x0 18.--19. "TransOrderModeWr,This setting controls transaction ordering based on AXI ID" "0: Reserved,1: Resreved,2: PCIe ordering rules,3: Strict request ordering mode"
newline
bitfld.long 0x0 16.--17. "TransOrderModeRd,This setting controls transaction ordering based on AXI ID" "0: Reserved,1: Reserved,2: PCIe ordering rules,3: Strict request ordering mode"
newline
hexmask.long.byte 0x0 10.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x0 9. "SysCoAttach,Writing 1 to this bit when the status register bit SysCoAttached is 0 starts an attach sequence. Writing 0 to this bit when the status register bit SysCoAttached is 1 starts a detach sequence." "0,1"
newline
bitfld.long 0x0 8. "SysCoDisable,Setting this disables SysCo." "0,1"
newline
rbitfld.long 0x0 5.--7. "Rsvd2,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "EventDisable,Setting this disables Event handling." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "Rsvd1,Reserved"
rgroup.long 0x1C002044++0x3
line.long 0x0 "XAIUTAR,Transaction Activity Register"
hexmask.long 0x0 7.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 6. "SysCoError,1 indicates Error was detected during previous or current SysCo event. This bit clears itself when the SysCo process triggers next time." "0,1"
newline
bitfld.long 0x0 5. "SysCoAttached,1 indicates that SysCo is Attached; 0 indicates it is detached." "0,1"
newline
bitfld.long 0x0 4. "SysCoConnecting,1 indicates that SysCo is in the process of connecting." "0,1"
newline
bitfld.long 0x0 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the Unit." "0,1"
group.long 0x1C002100++0x17
line.long 0x0 "XAIUUEDR,Unit Uncorrectable Error Detect Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 4. "TimeoutErrDetEn,Timeout protection error detection enable: When set  timeout errors will be detected." "0,1"
newline
bitfld.long 0x0 3. "DecErrDetEn,Decode Error Enable. When set  this bit enables detection of address map uncorrectable error" "0,1"
newline
bitfld.long 0x0 2. "MemErrDetEn,Memory protection error detection enable: When set errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "XAIUUEIR,Unit Uncorrectable Error Interrupt Register"
hexmask.long 0x4 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 4. "TimeoutErrIntEn,Timeout uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 3. "DecErrIntEn,Decode Error Interrupt Enable. When set  this bit enables the assertion of address map Uncorrectable Error Interrupt signal" "0,1"
newline
bitfld.long 0x4 2. "MemErrIntEn,RAM memory uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "XAIUUESR,XAIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "XAIUUELR0,XAIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "XAIUUELR1,XAIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "XAIUUESAR,XAIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C002140++0x13
line.long 0x0 "XAIUCECR,XAIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,This field determines the number of correctable errors that must be corrected before the Correctable Error Interrupt output signal is asserted."
newline
rbitfld.long 0x0 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,If this bit is set  the Correctable Error Interrupt output signal is asserted when the number of correctable errors corrected equals the value in ErrThreshold field; otherwise  the correctable error interrupt signal is never asserted." "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,If this bit is set  then correctable error detection and logging is enabled; otherwise  correctable error detection and logging is disabled." "0,1"
line.long 0x4 "XAIUCESR,XAIU Correctable Error Status Register"
hexmask.long.word 0x4 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Correctable Error Valid bit is set."
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,This field indicates the logged error type  if the Correctable Error Valid bit is set."
newline
rbitfld.long 0x4 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 2.--9. 1. "ErrCount,This field indicates the number of correctable errors detected by the unit. The field stops incrementing if the Correctable Error Count Overflow bit is set"
newline
rbitfld.long 0x4 1. "ErrCountOverflow,This bit indicates that the number of correctable errors detected by the unit overflowed the Correctable Error Count field" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Correctable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0x8 "XAIUCELR0,XAIU Correctable Error Location Registers 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0xC "XAIUCELR1,XAIU Correctable Error Location Registers 1"
hexmask.long.word 0xC 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x10 "XAIUCESAR,XAIU Correctable Error Status Alias Register"
hexmask.long.word 0x10 16.--31. 1. "ErrInfo,Alias bit for setting error info field of xCESR"
newline
hexmask.long.byte 0x10 12.--15. 1. "ErrType,Alias bit for setting error type field of xCESR"
newline
rbitfld.long 0x10 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x10 2.--9. 1. "ErrCount,Alias field for setting error Count field of xCESR"
newline
bitfld.long 0x10 1. "ErrCountOverflow,Alias bit for ssetting Error Count Overflow field of xCESR" "0,1"
newline
bitfld.long 0x10 0. "ErrVld,Alias bit for setting error valid field of xCESR" "0,1"
group.long 0x1C00217C++0x3
line.long 0x0 "XAIUCRTR,XAIU Correctable Resiliency Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "ResThreshold,Threshold for the correctable error indication to the functional safety controller."
group.long 0x1C002190++0x3
line.long 0x0 "XAIUTOCR,XAIU Timeout Control Register"
bitfld.long 0x0 31. "TimeOutRefEn,Set to use reference singal input instead of counting every 4K cycle" "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TimeOutThreshold,Time out threshold value; counts in increments of 4K cycles."
group.long 0x1C002200++0x7
line.long 0x0 "XAIUQOSCR,XAIU QoS Control Register"
hexmask.long.word 0x0 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "EventThreshold,Event threshold value counts every event (command issues) if value is 0 event count is disabled (event starvation disabled)."
line.long 0x4 "XAIUQOSSR,XAIU QoS Status Register"
hexmask.long.word 0x4 20.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.word 0x4 4.--19. 1. "EventStatusCount,Counts number of times event threshold was hit"
newline
rbitfld.long 0x4 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
eventfld.long 0x4 1. "EventStatusCountOverflow,Event count overflow bit  this bit is set once the counter overflows" "0,1"
newline
rbitfld.long 0x4 0. "EventStatus,0: Normal Mode" "0: Normal Mode,1: Starvation Mode"
rgroup.long 0x1C002380++0x3
line.long 0x0 "XAIUNRSBAR,NRS Base Address Register"
hexmask.long 0x0 0.--31. 1. "NRSBA,NRSBA"
group.long 0x1C002384++0x3
line.long 0x0 "XAIUNRSBHR,NRS Base Address Hold Register"
hexmask.long 0x0 0.--31. 1. "NRSBA,NRSBA field indicates bits[51:20] of the Base address of the Ncore Register Space"
rgroup.long 0x1C002388++0x3
line.long 0x0 "XAIUNRSBLR,NRS Base Address Load Register"
bitfld.long 0x0 31. "BALoaded,This field is set when NRSBHR is stored into and reset when this register is read" "0,1"
newline
hexmask.long.tbyte 0x0 14.--30. 1. "Rsvd2,Reserved"
newline
hexmask.long.word 0x0 4.--13. 1. "NRSDIIId,This field is set to NUId of the DII to which the Ncore is connected"
newline
hexmask.long.byte 0x0 0.--3. 1. "Rsvd1,Reserved"
group.long 0x1C0023A0++0xB
line.long 0x0 "XAIUBRAR,Boot Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: DMI  1:DII" "0: DMI,1: DII"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.word 0x0 0.--8. 1. "Rsvd1,Reserved"
line.long 0x4 "XAIUBRBLR,Boot Region Base Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUBRBHR,Boot Region Base High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0023C0++0x7
line.long 0x0 "XAIUAMIGR,Active Memory Interleave Group Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 1.--4. 1. "AMIGS,Active Memory Interleave Group Set in use currenlty when Valid is set"
newline
bitfld.long 0x0 0. "Valid,Memory Interleave Group Set valid  when set the MIGS specified in AMIGS field is being used for DMI interleaving else MIGS 0 is used by default" "0,1"
line.long 0x4 "XAIUMIFSR,Memory Interleave Function Select Register"
hexmask.long.byte 0x4 27.--31. 1. "Rsvd5,Reserved"
newline
bitfld.long 0x4 24.--26. "MIG16AIFId,Active function ID for 16 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 19.--23. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x4 16.--18. "MIG8AIFId,Active function ID for 8 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 11.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x4 8.--10. "MIG4AIFId,Active function ID for 4 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 7. "Rsvd2,Reserved" "0,1"
newline
bitfld.long 0x4 4.--6. "MIG3AIFId,Active function ID for 3 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x4 0.--2. "MIG2AIFId,Active function ID for 2 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
group.long 0x1C002400++0xB
line.long 0x0 "XAIUGPRAR0,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR0,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR0,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C002410++0xB
line.long 0x0 "XAIUGPRAR1,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR1,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR1,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C002420++0xB
line.long 0x0 "XAIUGPRAR2,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR2,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR2,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C002430++0xB
line.long 0x0 "XAIUGPRAR3,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR3,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR3,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C002440++0xB
line.long 0x0 "XAIUGPRAR4,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR4,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR4,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C002450++0xB
line.long 0x0 "XAIUGPRAR5,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR5,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR5,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C002460++0xB
line.long 0x0 "XAIUGPRAR6,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR6,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR6,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C002470++0xB
line.long 0x0 "XAIUGPRAR7,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR7,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR7,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C002480++0xB
line.long 0x0 "XAIUGPRAR8,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR8,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR8,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C002490++0xB
line.long 0x0 "XAIUGPRAR9,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR9,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR9,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0024A0++0xB
line.long 0x0 "XAIUGPRAR10,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR10,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR10,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0024B0++0xB
line.long 0x0 "XAIUGPRAR11,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR11,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR11,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C002808++0x17
line.long 0x0 "XAIUTBALR0,XAIU Trace Trigger Base Address Low Register"
hexmask.long 0x0 0.--31. 1. "base_addr_lo,Lower order bits 43:12 of the base address of the region"
line.long 0x4 "XAIUTBAHR0,XAIU Trace Trigger Base Address High Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x4 0.--7. 1. "base_addr_hi,Lower order bits 51:44 of the base address of the region"
line.long 0x8 "XAIUTOPCR00,XAIU Trace Trigger Opcode Register"
bitfld.long 0x8 31. "valid2,Valid 2" "0,1"
newline
hexmask.long.word 0x8 16.--30. 1. "opcode2,Opcode 2"
newline
bitfld.long 0x8 15. "valid1,Valid 1" "0,1"
newline
hexmask.long.word 0x8 0.--14. 1. "opcode1,Opcode 1"
line.long 0xC "XAIUTOPCR10,XAIU Trace Trigger Opcode Register"
bitfld.long 0xC 31. "valid4,Valid 4" "0,1"
newline
hexmask.long.word 0xC 16.--30. 1. "opcode4,Opcode 4"
newline
bitfld.long 0xC 15. "valid3,Valid 3" "0,1"
newline
hexmask.long.word 0xC 0.--14. 1. "opcode3,Opcode 3"
line.long 0x10 "XAIUTUBR0,XAIU Trace Trigger User Bits Register"
hexmask.long 0x10 0.--31. 1. "user,User bits. Width parameterized."
line.long 0x14 "XAIUTUBMR0,XAIU Trace Trigger User Bits Mask Register"
hexmask.long 0x14 0.--31. 1. "user_mask,User bits. Width parameterized."
group.long 0x1C002900++0x7
line.long 0x0 "XAIUCCTRLR,XAIU Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
line.long 0x4 "XAIUTCTRLR0,XAIU Trace Trigger Control Register"
hexmask.long.byte 0x4 28.--31. 1. "memattr,Specifies memory attribute. Memattr on CHI  AxCache on AXI/ACE/ACE-Lite/ACE-Lite-E"
newline
bitfld.long 0x4 27. "ar,Match memattr on AR channel" "0,1"
newline
bitfld.long 0x4 26. "aw,Match memattr on AW channel" "0,1"
newline
rbitfld.long 0x4 24.--25. "Rsvd2,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 19.--23. 1. "range,Address range size. This field indicates a binary number from 0 to 31 from which region's size is calculated as (Size of IG) * 2^(Size + 12) bytes"
newline
hexmask.long.byte 0x4 12.--18. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x4 7.--11. 1. "hui,Specifies the HUI NunItID for DII  and MIG number for DII"
newline
bitfld.long 0x4 6. "hut,Specify target type. 0: DMI  1: DII" "0: DMI,1: DII"
newline
bitfld.long 0x4 5. "target_type_match_en,Enable Trace if there is a match on specified target type" "0,1"
newline
bitfld.long 0x4 4. "user_match_en,Enable Trace if there is a match on specified user bits" "0,1"
newline
bitfld.long 0x4 3. "memattr_match_en,Enable Trace on memory attribute match" "0,1"
newline
bitfld.long 0x4 2. "opcode_match_en,Enable Trace on opcode match" "0,1"
newline
bitfld.long 0x4 1. "addr_match_en,Enable Trace on address range match" "0,1"
newline
bitfld.long 0x4 0. "native_trace_en,0: Ignore native trace signaling. 1: Allow native trace signaling to set trigger" "0: Ignore native trace signaling,1: Allow native trace signaling to set trigger"
group.long 0x1C002A00++0x1F
line.long 0x0 "XAIUEDR0,Credit on a per message type basis."
hexmask.long.byte 0x0 24.--31. 1. "MRW,DTW credit."
newline
hexmask.long.byte 0x0 16.--23. 1. "MRR,DTR credit."
newline
hexmask.long.byte 0x0 8.--15. 1. "MRU,Update credit."
newline
hexmask.long.byte 0x0 0.--7. 1. "MRC,Command credit."
line.long 0x4 "XAIUEDR1,Hardware control debug register."
hexmask.long 0x4 0.--31. 1. "cfg,Hardware control."
line.long 0x8 "XAIUEDR2,OTT pools."
hexmask.long.byte 0x8 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 16.--23. 1. "RD,OTT Read pool."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "WR,OTT Write pool."
line.long 0xC "XAIUEDR3,Limit OTT/STT sizes."
hexmask.long.byte 0xC 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0xC 16.--23. 1. "STT,STT Limit."
newline
hexmask.long.byte 0xC 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0xC 0.--7. 1. "OTT,OTT limit."
line.long 0x10 "XAIUEDR4,Limit Read/Write operations."
hexmask.long.byte 0x10 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x10 16.--23. 1. "RD,OTT Read Limit."
newline
hexmask.long.byte 0x10 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x10 0.--7. 1. "WR,OTT Write limit."
line.long 0x14 "XAIUEDR5,Limit evictions."
hexmask.long.tbyte 0x14 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x14 0.--7. 1. "EV,Limit evictions."
line.long 0x18 "XAIUEDR6,Credit adjustment per target type basis: 0x1: Max 1. 0x2: Max 2. 0x3: Max 3. 0x5: Minus 1. 0x6: Minus 2. 0x7: Minus 3. 0x9: 1 read others writes. 0xa: Reserve 1 write. 0xb: No limit. 0xd: reserve 1 extra write. 0xe: reserve 2 extra writes. 0xf:.."
hexmask.long.word 0x18 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x18 16.--19. 1. "QOS,QOS credit adjustment."
newline
hexmask.long.byte 0x18 12.--15. 1. "DVE,DVE credit adjustment."
newline
hexmask.long.byte 0x18 8.--11. 1. "DII,DII credit adjustment."
newline
hexmask.long.byte 0x18 4.--7. 1. "DMI,DMI credit adjustment."
newline
hexmask.long.byte 0x18 0.--3. 1. "DCE,DCE credit adjustment."
line.long 0x1C "XAIUEDR7,Specify period length for starvation detection"
hexmask.long.tbyte 0x1C 12.--31. 1. "TIME,Timer period in granularity of 2K."
newline
hexmask.long.word 0x1C 0.--11. 1. "EVENT,Event counter period in granularity of 16."
group.long 0x1C002B00++0xB
line.long 0x0 "XAIUCNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR0,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C002B10++0xB
line.long 0x0 "XAIUCNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR1,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C002B20++0xB
line.long 0x0 "XAIUCNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR2,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C002B30++0xB
line.long 0x0 "XAIUCNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR3,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C002FF0++0x3
line.long 0x0 "XAIUNRSAR,CAIU Ncore Register Space Attribute Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "NRSAR,Set high to enable CSR access via this AIU." "0,1"
rgroup.long 0x1C002FF4++0x3
line.long 0x0 "XAIUENGIDR,XAIU Engineering ID Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C002FFC++0xB
line.long 0x0 "XAIUINFOR,XAIU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 20.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 16.--19. 1. "UST,Unit Type"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "XAIUIDR,XAIU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the unit is implemented." "0,1"
newline
hexmask.long.word 0x4 15.--30. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 12.--14. "NUnitId,Ncore 3 Unit identifier." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this unit resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,XAIU Register Page Number (within its NRR)"
line.long 0x8 "XAIUFUIDR,XAIU Fabric Unit Identification Register"
hexmask.long 0x8 4.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--3. 1. "FUnitId,Fabric Unit Identifier of the unit"
group.long 0x1C003040++0x3
line.long 0x0 "XAIUTCR,Transaction Control Register"
hexmask.long.word 0x0 20.--31. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x0 18.--19. "TransOrderModeWr,This setting controls transaction ordering based on AXI ID" "0: Reserved,1: Resreved,2: PCIe ordering rules,3: Strict request ordering mode"
newline
bitfld.long 0x0 16.--17. "TransOrderModeRd,This setting controls transaction ordering based on AXI ID" "0: Reserved,1: Reserved,2: PCIe ordering rules,3: Strict request ordering mode"
newline
hexmask.long.byte 0x0 10.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x0 9. "SysCoAttach,Writing 1 to this bit when the status register bit SysCoAttached is 0 starts an attach sequence. Writing 0 to this bit when the status register bit SysCoAttached is 1 starts a detach sequence." "0,1"
newline
bitfld.long 0x0 8. "SysCoDisable,Setting this disables SysCo." "0,1"
newline
rbitfld.long 0x0 5.--7. "Rsvd2,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "EventDisable,Setting this disables Event handling." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "Rsvd1,Reserved"
rgroup.long 0x1C003044++0x3
line.long 0x0 "XAIUTAR,Transaction Activity Register"
hexmask.long 0x0 7.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 6. "SysCoError,1 indicates Error was detected during previous or current SysCo event. This bit clears itself when the SysCo process triggers next time." "0,1"
newline
bitfld.long 0x0 5. "SysCoAttached,1 indicates that SysCo is Attached; 0 indicates it is detached." "0,1"
newline
bitfld.long 0x0 4. "SysCoConnecting,1 indicates that SysCo is in the process of connecting." "0,1"
newline
bitfld.long 0x0 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the Unit." "0,1"
group.long 0x1C003100++0x17
line.long 0x0 "XAIUUEDR,Unit Uncorrectable Error Detect Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 4. "TimeoutErrDetEn,Timeout protection error detection enable: When set  timeout errors will be detected." "0,1"
newline
bitfld.long 0x0 3. "DecErrDetEn,Decode Error Enable. When set  this bit enables detection of address map uncorrectable error" "0,1"
newline
bitfld.long 0x0 2. "MemErrDetEn,Memory protection error detection enable: When set errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "XAIUUEIR,Unit Uncorrectable Error Interrupt Register"
hexmask.long 0x4 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 4. "TimeoutErrIntEn,Timeout uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 3. "DecErrIntEn,Decode Error Interrupt Enable. When set  this bit enables the assertion of address map Uncorrectable Error Interrupt signal" "0,1"
newline
bitfld.long 0x4 2. "MemErrIntEn,RAM memory uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "XAIUUESR,XAIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "XAIUUELR0,XAIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "XAIUUELR1,XAIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "XAIUUESAR,XAIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C003140++0x13
line.long 0x0 "XAIUCECR,XAIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,This field determines the number of correctable errors that must be corrected before the Correctable Error Interrupt output signal is asserted."
newline
rbitfld.long 0x0 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,If this bit is set  the Correctable Error Interrupt output signal is asserted when the number of correctable errors corrected equals the value in ErrThreshold field; otherwise  the correctable error interrupt signal is never asserted." "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,If this bit is set  then correctable error detection and logging is enabled; otherwise  correctable error detection and logging is disabled." "0,1"
line.long 0x4 "XAIUCESR,XAIU Correctable Error Status Register"
hexmask.long.word 0x4 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Correctable Error Valid bit is set."
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,This field indicates the logged error type  if the Correctable Error Valid bit is set."
newline
rbitfld.long 0x4 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 2.--9. 1. "ErrCount,This field indicates the number of correctable errors detected by the unit. The field stops incrementing if the Correctable Error Count Overflow bit is set"
newline
rbitfld.long 0x4 1. "ErrCountOverflow,This bit indicates that the number of correctable errors detected by the unit overflowed the Correctable Error Count field" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Correctable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0x8 "XAIUCELR0,XAIU Correctable Error Location Registers 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0xC "XAIUCELR1,XAIU Correctable Error Location Registers 1"
hexmask.long.word 0xC 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x10 "XAIUCESAR,XAIU Correctable Error Status Alias Register"
hexmask.long.word 0x10 16.--31. 1. "ErrInfo,Alias bit for setting error info field of xCESR"
newline
hexmask.long.byte 0x10 12.--15. 1. "ErrType,Alias bit for setting error type field of xCESR"
newline
rbitfld.long 0x10 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x10 2.--9. 1. "ErrCount,Alias field for setting error Count field of xCESR"
newline
bitfld.long 0x10 1. "ErrCountOverflow,Alias bit for ssetting Error Count Overflow field of xCESR" "0,1"
newline
bitfld.long 0x10 0. "ErrVld,Alias bit for setting error valid field of xCESR" "0,1"
group.long 0x1C00317C++0x3
line.long 0x0 "XAIUCRTR,XAIU Correctable Resiliency Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "ResThreshold,Threshold for the correctable error indication to the functional safety controller."
group.long 0x1C003190++0x3
line.long 0x0 "XAIUTOCR,XAIU Timeout Control Register"
bitfld.long 0x0 31. "TimeOutRefEn,Set to use reference singal input instead of counting every 4K cycle" "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TimeOutThreshold,Time out threshold value; counts in increments of 4K cycles."
group.long 0x1C003200++0x7
line.long 0x0 "XAIUQOSCR,XAIU QoS Control Register"
hexmask.long.word 0x0 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "EventThreshold,Event threshold value counts every event (command issues) if value is 0 event count is disabled (event starvation disabled)."
line.long 0x4 "XAIUQOSSR,XAIU QoS Status Register"
hexmask.long.word 0x4 20.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.word 0x4 4.--19. 1. "EventStatusCount,Counts number of times event threshold was hit"
newline
rbitfld.long 0x4 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
eventfld.long 0x4 1. "EventStatusCountOverflow,Event count overflow bit  this bit is set once the counter overflows" "0,1"
newline
rbitfld.long 0x4 0. "EventStatus,0: Normal Mode" "0: Normal Mode,1: Starvation Mode"
rgroup.long 0x1C003380++0x3
line.long 0x0 "XAIUNRSBAR,NRS Base Address Register"
hexmask.long 0x0 0.--31. 1. "NRSBA,NRSBA"
group.long 0x1C003384++0x3
line.long 0x0 "XAIUNRSBHR,NRS Base Address Hold Register"
hexmask.long 0x0 0.--31. 1. "NRSBA,NRSBA field indicates bits[51:20] of the Base address of the Ncore Register Space"
rgroup.long 0x1C003388++0x3
line.long 0x0 "XAIUNRSBLR,NRS Base Address Load Register"
bitfld.long 0x0 31. "BALoaded,This field is set when NRSBHR is stored into and reset when this register is read" "0,1"
newline
hexmask.long.tbyte 0x0 14.--30. 1. "Rsvd2,Reserved"
newline
hexmask.long.word 0x0 4.--13. 1. "NRSDIIId,This field is set to NUId of the DII to which the Ncore is connected"
newline
hexmask.long.byte 0x0 0.--3. 1. "Rsvd1,Reserved"
group.long 0x1C0033A0++0xB
line.long 0x0 "XAIUBRAR,Boot Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: DMI  1:DII" "0: DMI,1: DII"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.word 0x0 0.--8. 1. "Rsvd1,Reserved"
line.long 0x4 "XAIUBRBLR,Boot Region Base Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUBRBHR,Boot Region Base High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0033C0++0x7
line.long 0x0 "XAIUAMIGR,Active Memory Interleave Group Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 1.--4. 1. "AMIGS,Active Memory Interleave Group Set in use currenlty when Valid is set"
newline
bitfld.long 0x0 0. "Valid,Memory Interleave Group Set valid  when set the MIGS specified in AMIGS field is being used for DMI interleaving else MIGS 0 is used by default" "0,1"
line.long 0x4 "XAIUMIFSR,Memory Interleave Function Select Register"
hexmask.long.byte 0x4 27.--31. 1. "Rsvd5,Reserved"
newline
bitfld.long 0x4 24.--26. "MIG16AIFId,Active function ID for 16 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 19.--23. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x4 16.--18. "MIG8AIFId,Active function ID for 8 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 11.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x4 8.--10. "MIG4AIFId,Active function ID for 4 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 7. "Rsvd2,Reserved" "0,1"
newline
bitfld.long 0x4 4.--6. "MIG3AIFId,Active function ID for 3 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x4 0.--2. "MIG2AIFId,Active function ID for 2 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
group.long 0x1C003400++0xB
line.long 0x0 "XAIUGPRAR0,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR0,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR0,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C003410++0xB
line.long 0x0 "XAIUGPRAR1,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR1,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR1,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C003420++0xB
line.long 0x0 "XAIUGPRAR2,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR2,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR2,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C003430++0xB
line.long 0x0 "XAIUGPRAR3,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR3,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR3,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C003440++0xB
line.long 0x0 "XAIUGPRAR4,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR4,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR4,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C003450++0xB
line.long 0x0 "XAIUGPRAR5,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR5,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR5,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C003460++0xB
line.long 0x0 "XAIUGPRAR6,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR6,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR6,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C003470++0xB
line.long 0x0 "XAIUGPRAR7,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR7,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR7,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C003480++0xB
line.long 0x0 "XAIUGPRAR8,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR8,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR8,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C003490++0xB
line.long 0x0 "XAIUGPRAR9,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR9,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR9,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0034A0++0xB
line.long 0x0 "XAIUGPRAR10,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR10,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR10,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0034B0++0xB
line.long 0x0 "XAIUGPRAR11,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR11,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR11,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C003808++0x17
line.long 0x0 "XAIUTBALR0,XAIU Trace Trigger Base Address Low Register"
hexmask.long 0x0 0.--31. 1. "base_addr_lo,Lower order bits 43:12 of the base address of the region"
line.long 0x4 "XAIUTBAHR0,XAIU Trace Trigger Base Address High Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x4 0.--7. 1. "base_addr_hi,Lower order bits 51:44 of the base address of the region"
line.long 0x8 "XAIUTOPCR00,XAIU Trace Trigger Opcode Register"
bitfld.long 0x8 31. "valid2,Valid 2" "0,1"
newline
hexmask.long.word 0x8 16.--30. 1. "opcode2,Opcode 2"
newline
bitfld.long 0x8 15. "valid1,Valid 1" "0,1"
newline
hexmask.long.word 0x8 0.--14. 1. "opcode1,Opcode 1"
line.long 0xC "XAIUTOPCR10,XAIU Trace Trigger Opcode Register"
bitfld.long 0xC 31. "valid4,Valid 4" "0,1"
newline
hexmask.long.word 0xC 16.--30. 1. "opcode4,Opcode 4"
newline
bitfld.long 0xC 15. "valid3,Valid 3" "0,1"
newline
hexmask.long.word 0xC 0.--14. 1. "opcode3,Opcode 3"
line.long 0x10 "XAIUTUBR0,XAIU Trace Trigger User Bits Register"
hexmask.long 0x10 0.--31. 1. "user,User bits. Width parameterized."
line.long 0x14 "XAIUTUBMR0,XAIU Trace Trigger User Bits Mask Register"
hexmask.long 0x14 0.--31. 1. "user_mask,User bits. Width parameterized."
group.long 0x1C003900++0x7
line.long 0x0 "XAIUCCTRLR,XAIU Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
line.long 0x4 "XAIUTCTRLR0,XAIU Trace Trigger Control Register"
hexmask.long.byte 0x4 28.--31. 1. "memattr,Specifies memory attribute. Memattr on CHI  AxCache on AXI/ACE/ACE-Lite/ACE-Lite-E"
newline
bitfld.long 0x4 27. "ar,Match memattr on AR channel" "0,1"
newline
bitfld.long 0x4 26. "aw,Match memattr on AW channel" "0,1"
newline
rbitfld.long 0x4 24.--25. "Rsvd2,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 19.--23. 1. "range,Address range size. This field indicates a binary number from 0 to 31 from which region's size is calculated as (Size of IG) * 2^(Size + 12) bytes"
newline
hexmask.long.byte 0x4 12.--18. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x4 7.--11. 1. "hui,Specifies the HUI NunItID for DII  and MIG number for DII"
newline
bitfld.long 0x4 6. "hut,Specify target type. 0: DMI  1: DII" "0: DMI,1: DII"
newline
bitfld.long 0x4 5. "target_type_match_en,Enable Trace if there is a match on specified target type" "0,1"
newline
bitfld.long 0x4 4. "user_match_en,Enable Trace if there is a match on specified user bits" "0,1"
newline
bitfld.long 0x4 3. "memattr_match_en,Enable Trace on memory attribute match" "0,1"
newline
bitfld.long 0x4 2. "opcode_match_en,Enable Trace on opcode match" "0,1"
newline
bitfld.long 0x4 1. "addr_match_en,Enable Trace on address range match" "0,1"
newline
bitfld.long 0x4 0. "native_trace_en,0: Ignore native trace signaling. 1: Allow native trace signaling to set trigger" "0: Ignore native trace signaling,1: Allow native trace signaling to set trigger"
group.long 0x1C003A00++0x1F
line.long 0x0 "XAIUEDR0,Credit on a per message type basis."
hexmask.long.byte 0x0 24.--31. 1. "MRW,DTW credit."
newline
hexmask.long.byte 0x0 16.--23. 1. "MRR,DTR credit."
newline
hexmask.long.byte 0x0 8.--15. 1. "MRU,Update credit."
newline
hexmask.long.byte 0x0 0.--7. 1. "MRC,Command credit."
line.long 0x4 "XAIUEDR1,Hardware control debug register."
hexmask.long 0x4 0.--31. 1. "cfg,Hardware control."
line.long 0x8 "XAIUEDR2,OTT pools."
hexmask.long.byte 0x8 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 16.--23. 1. "RD,OTT Read pool."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "WR,OTT Write pool."
line.long 0xC "XAIUEDR3,Limit OTT/STT sizes."
hexmask.long.byte 0xC 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0xC 16.--23. 1. "STT,STT Limit."
newline
hexmask.long.byte 0xC 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0xC 0.--7. 1. "OTT,OTT limit."
line.long 0x10 "XAIUEDR4,Limit Read/Write operations."
hexmask.long.byte 0x10 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x10 16.--23. 1. "RD,OTT Read Limit."
newline
hexmask.long.byte 0x10 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x10 0.--7. 1. "WR,OTT Write limit."
line.long 0x14 "XAIUEDR5,Limit evictions."
hexmask.long.tbyte 0x14 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x14 0.--7. 1. "EV,Limit evictions."
line.long 0x18 "XAIUEDR6,Credit adjustment per target type basis: 0x1: Max 1. 0x2: Max 2. 0x3: Max 3. 0x5: Minus 1. 0x6: Minus 2. 0x7: Minus 3. 0x9: 1 read others writes. 0xa: Reserve 1 write. 0xb: No limit. 0xd: reserve 1 extra write. 0xe: reserve 2 extra writes. 0xf:.."
hexmask.long.word 0x18 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x18 16.--19. 1. "QOS,QOS credit adjustment."
newline
hexmask.long.byte 0x18 12.--15. 1. "DVE,DVE credit adjustment."
newline
hexmask.long.byte 0x18 8.--11. 1. "DII,DII credit adjustment."
newline
hexmask.long.byte 0x18 4.--7. 1. "DMI,DMI credit adjustment."
newline
hexmask.long.byte 0x18 0.--3. 1. "DCE,DCE credit adjustment."
line.long 0x1C "XAIUEDR7,Specify period length for starvation detection"
hexmask.long.tbyte 0x1C 12.--31. 1. "TIME,Timer period in granularity of 2K."
newline
hexmask.long.word 0x1C 0.--11. 1. "EVENT,Event counter period in granularity of 16."
group.long 0x1C003B00++0xB
line.long 0x0 "XAIUCNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR0,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C003B10++0xB
line.long 0x0 "XAIUCNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR1,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C003B20++0xB
line.long 0x0 "XAIUCNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR2,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C003B30++0xB
line.long 0x0 "XAIUCNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR3,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C003FF0++0x3
line.long 0x0 "XAIUNRSAR,CAIU Ncore Register Space Attribute Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "NRSAR,Set high to enable CSR access via this AIU." "0,1"
rgroup.long 0x1C003FF4++0x3
line.long 0x0 "XAIUENGIDR,XAIU Engineering ID Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C003FFC++0xB
line.long 0x0 "XAIUINFOR,XAIU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 20.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 16.--19. 1. "UST,Unit Type"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "XAIUIDR,XAIU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the unit is implemented." "0,1"
newline
hexmask.long.word 0x4 15.--30. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 12.--14. "NUnitId,Ncore 3 Unit identifier." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this unit resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,XAIU Register Page Number (within its NRR)"
line.long 0x8 "XAIUFUIDR,XAIU Fabric Unit Identification Register"
hexmask.long 0x8 4.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--3. 1. "FUnitId,Fabric Unit Identifier of the unit"
group.long 0x1C004040++0x3
line.long 0x0 "XAIUTCR,Transaction Control Register"
hexmask.long.word 0x0 20.--31. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x0 18.--19. "TransOrderModeWr,This setting controls transaction ordering based on AXI ID" "0: Reserved,1: Resreved,2: PCIe ordering rules,3: Strict request ordering mode"
newline
bitfld.long 0x0 16.--17. "TransOrderModeRd,This setting controls transaction ordering based on AXI ID" "0: Reserved,1: Reserved,2: PCIe ordering rules,3: Strict request ordering mode"
newline
hexmask.long.byte 0x0 10.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x0 9. "SysCoAttach,Writing 1 to this bit when the status register bit SysCoAttached is 0 starts an attach sequence. Writing 0 to this bit when the status register bit SysCoAttached is 1 starts a detach sequence." "0,1"
newline
bitfld.long 0x0 8. "SysCoDisable,Setting this disables SysCo." "0,1"
newline
rbitfld.long 0x0 5.--7. "Rsvd2,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "EventDisable,Setting this disables Event handling." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "Rsvd1,Reserved"
rgroup.long 0x1C004044++0x3
line.long 0x0 "XAIUTAR,Transaction Activity Register"
hexmask.long 0x0 7.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 6. "SysCoError,1 indicates Error was detected during previous or current SysCo event. This bit clears itself when the SysCo process triggers next time." "0,1"
newline
bitfld.long 0x0 5. "SysCoAttached,1 indicates that SysCo is Attached; 0 indicates it is detached." "0,1"
newline
bitfld.long 0x0 4. "SysCoConnecting,1 indicates that SysCo is in the process of connecting." "0,1"
newline
bitfld.long 0x0 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the Unit." "0,1"
group.long 0x1C004100++0x17
line.long 0x0 "XAIUUEDR,Unit Uncorrectable Error Detect Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 4. "TimeoutErrDetEn,Timeout protection error detection enable: When set  timeout errors will be detected." "0,1"
newline
bitfld.long 0x0 3. "DecErrDetEn,Decode Error Enable. When set  this bit enables detection of address map uncorrectable error" "0,1"
newline
bitfld.long 0x0 2. "MemErrDetEn,Memory protection error detection enable: When set errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "XAIUUEIR,Unit Uncorrectable Error Interrupt Register"
hexmask.long 0x4 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 4. "TimeoutErrIntEn,Timeout uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 3. "DecErrIntEn,Decode Error Interrupt Enable. When set  this bit enables the assertion of address map Uncorrectable Error Interrupt signal" "0,1"
newline
bitfld.long 0x4 2. "MemErrIntEn,RAM memory uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "XAIUUESR,XAIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "XAIUUELR0,XAIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "XAIUUELR1,XAIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "XAIUUESAR,XAIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C004140++0x13
line.long 0x0 "XAIUCECR,XAIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,This field determines the number of correctable errors that must be corrected before the Correctable Error Interrupt output signal is asserted."
newline
rbitfld.long 0x0 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,If this bit is set  the Correctable Error Interrupt output signal is asserted when the number of correctable errors corrected equals the value in ErrThreshold field; otherwise  the correctable error interrupt signal is never asserted." "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,If this bit is set  then correctable error detection and logging is enabled; otherwise  correctable error detection and logging is disabled." "0,1"
line.long 0x4 "XAIUCESR,XAIU Correctable Error Status Register"
hexmask.long.word 0x4 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Correctable Error Valid bit is set."
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,This field indicates the logged error type  if the Correctable Error Valid bit is set."
newline
rbitfld.long 0x4 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 2.--9. 1. "ErrCount,This field indicates the number of correctable errors detected by the unit. The field stops incrementing if the Correctable Error Count Overflow bit is set"
newline
rbitfld.long 0x4 1. "ErrCountOverflow,This bit indicates that the number of correctable errors detected by the unit overflowed the Correctable Error Count field" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Correctable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0x8 "XAIUCELR0,XAIU Correctable Error Location Registers 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0xC "XAIUCELR1,XAIU Correctable Error Location Registers 1"
hexmask.long.word 0xC 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x10 "XAIUCESAR,XAIU Correctable Error Status Alias Register"
hexmask.long.word 0x10 16.--31. 1. "ErrInfo,Alias bit for setting error info field of xCESR"
newline
hexmask.long.byte 0x10 12.--15. 1. "ErrType,Alias bit for setting error type field of xCESR"
newline
rbitfld.long 0x10 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x10 2.--9. 1. "ErrCount,Alias field for setting error Count field of xCESR"
newline
bitfld.long 0x10 1. "ErrCountOverflow,Alias bit for ssetting Error Count Overflow field of xCESR" "0,1"
newline
bitfld.long 0x10 0. "ErrVld,Alias bit for setting error valid field of xCESR" "0,1"
group.long 0x1C00417C++0x3
line.long 0x0 "XAIUCRTR,XAIU Correctable Resiliency Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "ResThreshold,Threshold for the correctable error indication to the functional safety controller."
group.long 0x1C004190++0x3
line.long 0x0 "XAIUTOCR,XAIU Timeout Control Register"
bitfld.long 0x0 31. "TimeOutRefEn,Set to use reference singal input instead of counting every 4K cycle" "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TimeOutThreshold,Time out threshold value; counts in increments of 4K cycles."
group.long 0x1C004200++0x7
line.long 0x0 "XAIUQOSCR,XAIU QoS Control Register"
hexmask.long.word 0x0 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "EventThreshold,Event threshold value counts every event (command issues) if value is 0 event count is disabled (event starvation disabled)."
line.long 0x4 "XAIUQOSSR,XAIU QoS Status Register"
hexmask.long.word 0x4 20.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.word 0x4 4.--19. 1. "EventStatusCount,Counts number of times event threshold was hit"
newline
rbitfld.long 0x4 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
eventfld.long 0x4 1. "EventStatusCountOverflow,Event count overflow bit  this bit is set once the counter overflows" "0,1"
newline
rbitfld.long 0x4 0. "EventStatus,0: Normal Mode" "0: Normal Mode,1: Starvation Mode"
rgroup.long 0x1C004380++0x3
line.long 0x0 "XAIUNRSBAR,NRS Base Address Register"
hexmask.long 0x0 0.--31. 1. "NRSBA,NRSBA"
group.long 0x1C004384++0x3
line.long 0x0 "XAIUNRSBHR,NRS Base Address Hold Register"
hexmask.long 0x0 0.--31. 1. "NRSBA,NRSBA field indicates bits[51:20] of the Base address of the Ncore Register Space"
rgroup.long 0x1C004388++0x3
line.long 0x0 "XAIUNRSBLR,NRS Base Address Load Register"
bitfld.long 0x0 31. "BALoaded,This field is set when NRSBHR is stored into and reset when this register is read" "0,1"
newline
hexmask.long.tbyte 0x0 14.--30. 1. "Rsvd2,Reserved"
newline
hexmask.long.word 0x0 4.--13. 1. "NRSDIIId,This field is set to NUId of the DII to which the Ncore is connected"
newline
hexmask.long.byte 0x0 0.--3. 1. "Rsvd1,Reserved"
group.long 0x1C0043A0++0xB
line.long 0x0 "XAIUBRAR,Boot Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: DMI  1:DII" "0: DMI,1: DII"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.word 0x0 0.--8. 1. "Rsvd1,Reserved"
line.long 0x4 "XAIUBRBLR,Boot Region Base Low Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUBRBHR,Boot Region Base High Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0043C0++0x7
line.long 0x0 "XAIUAMIGR,Active Memory Interleave Group Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 1.--4. 1. "AMIGS,Active Memory Interleave Group Set in use currenlty when Valid is set"
newline
bitfld.long 0x0 0. "Valid,Memory Interleave Group Set valid  when set the MIGS specified in AMIGS field is being used for DMI interleaving else MIGS 0 is used by default" "0,1"
line.long 0x4 "XAIUMIFSR,Memory Interleave Function Select Register"
hexmask.long.byte 0x4 27.--31. 1. "Rsvd5,Reserved"
newline
bitfld.long 0x4 24.--26. "MIG16AIFId,Active function ID for 16 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 19.--23. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x4 16.--18. "MIG8AIFId,Active function ID for 8 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 11.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x4 8.--10. "MIG4AIFId,Active function ID for 4 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 7. "Rsvd2,Reserved" "0,1"
newline
bitfld.long 0x4 4.--6. "MIG3AIFId,Active function ID for 3 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x4 0.--2. "MIG2AIFId,Active function ID for 2 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
group.long 0x1C004400++0xB
line.long 0x0 "XAIUGPRAR0,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR0,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR0,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C004410++0xB
line.long 0x0 "XAIUGPRAR1,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR1,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR1,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C004420++0xB
line.long 0x0 "XAIUGPRAR2,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR2,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR2,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C004430++0xB
line.long 0x0 "XAIUGPRAR3,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR3,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR3,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C004440++0xB
line.long 0x0 "XAIUGPRAR4,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR4,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR4,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C004450++0xB
line.long 0x0 "XAIUGPRAR5,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR5,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR5,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C004460++0xB
line.long 0x0 "XAIUGPRAR6,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR6,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR6,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C004470++0xB
line.long 0x0 "XAIUGPRAR7,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR7,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR7,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C004480++0xB
line.long 0x0 "XAIUGPRAR8,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR8,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR8,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C004490++0xB
line.long 0x0 "XAIUGPRAR9,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR9,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR9,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0044A0++0xB
line.long 0x0 "XAIUGPRAR10,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR10,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR10,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0044B0++0xB
line.long 0x0 "XAIUGPRAR11,General Purpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "XAIUGPRBLR11,General Purpose Region Base Address Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "XAIUGPRBHR11,General Purpose Region Base Address Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C004808++0x17
line.long 0x0 "XAIUTBALR0,XAIU Trace Trigger Base Address Low Register"
hexmask.long 0x0 0.--31. 1. "base_addr_lo,Lower order bits 43:12 of the base address of the region"
line.long 0x4 "XAIUTBAHR0,XAIU Trace Trigger Base Address High Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x4 0.--7. 1. "base_addr_hi,Lower order bits 51:44 of the base address of the region"
line.long 0x8 "XAIUTOPCR00,XAIU Trace Trigger Opcode Register"
bitfld.long 0x8 31. "valid2,Valid 2" "0,1"
newline
hexmask.long.word 0x8 16.--30. 1. "opcode2,Opcode 2"
newline
bitfld.long 0x8 15. "valid1,Valid 1" "0,1"
newline
hexmask.long.word 0x8 0.--14. 1. "opcode1,Opcode 1"
line.long 0xC "XAIUTOPCR10,XAIU Trace Trigger Opcode Register"
bitfld.long 0xC 31. "valid4,Valid 4" "0,1"
newline
hexmask.long.word 0xC 16.--30. 1. "opcode4,Opcode 4"
newline
bitfld.long 0xC 15. "valid3,Valid 3" "0,1"
newline
hexmask.long.word 0xC 0.--14. 1. "opcode3,Opcode 3"
line.long 0x10 "XAIUTUBR0,XAIU Trace Trigger User Bits Register"
hexmask.long 0x10 0.--31. 1. "user,User bits. Width parameterized."
line.long 0x14 "XAIUTUBMR0,XAIU Trace Trigger User Bits Mask Register"
hexmask.long 0x14 0.--31. 1. "user_mask,User bits. Width parameterized."
group.long 0x1C004900++0x7
line.long 0x0 "XAIUCCTRLR,XAIU Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
line.long 0x4 "XAIUTCTRLR0,XAIU Trace Trigger Control Register"
hexmask.long.byte 0x4 28.--31. 1. "memattr,Specifies memory attribute. Memattr on CHI  AxCache on AXI/ACE/ACE-Lite/ACE-Lite-E"
newline
bitfld.long 0x4 27. "ar,Match memattr on AR channel" "0,1"
newline
bitfld.long 0x4 26. "aw,Match memattr on AW channel" "0,1"
newline
rbitfld.long 0x4 24.--25. "Rsvd2,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 19.--23. 1. "range,Address range size. This field indicates a binary number from 0 to 31 from which region's size is calculated as (Size of IG) * 2^(Size + 12) bytes"
newline
hexmask.long.byte 0x4 12.--18. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x4 7.--11. 1. "hui,Specifies the HUI NunItID for DII  and MIG number for DII"
newline
bitfld.long 0x4 6. "hut,Specify target type. 0: DMI  1: DII" "0: DMI,1: DII"
newline
bitfld.long 0x4 5. "target_type_match_en,Enable Trace if there is a match on specified target type" "0,1"
newline
bitfld.long 0x4 4. "user_match_en,Enable Trace if there is a match on specified user bits" "0,1"
newline
bitfld.long 0x4 3. "memattr_match_en,Enable Trace on memory attribute match" "0,1"
newline
bitfld.long 0x4 2. "opcode_match_en,Enable Trace on opcode match" "0,1"
newline
bitfld.long 0x4 1. "addr_match_en,Enable Trace on address range match" "0,1"
newline
bitfld.long 0x4 0. "native_trace_en,0: Ignore native trace signaling. 1: Allow native trace signaling to set trigger" "0: Ignore native trace signaling,1: Allow native trace signaling to set trigger"
group.long 0x1C004A00++0x1F
line.long 0x0 "XAIUEDR0,Credit on a per message type basis."
hexmask.long.byte 0x0 24.--31. 1. "MRW,DTW credit."
newline
hexmask.long.byte 0x0 16.--23. 1. "MRR,DTR credit."
newline
hexmask.long.byte 0x0 8.--15. 1. "MRU,Update credit."
newline
hexmask.long.byte 0x0 0.--7. 1. "MRC,Command credit."
line.long 0x4 "XAIUEDR1,Hardware control debug register."
hexmask.long 0x4 0.--31. 1. "cfg,Hardware control."
line.long 0x8 "XAIUEDR2,OTT pools."
hexmask.long.byte 0x8 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 16.--23. 1. "RD,OTT Read pool."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "WR,OTT Write pool."
line.long 0xC "XAIUEDR3,Limit OTT/STT sizes."
hexmask.long.byte 0xC 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0xC 16.--23. 1. "STT,STT Limit."
newline
hexmask.long.byte 0xC 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0xC 0.--7. 1. "OTT,OTT limit."
line.long 0x10 "XAIUEDR4,Limit Read/Write operations."
hexmask.long.byte 0x10 24.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x10 16.--23. 1. "RD,OTT Read Limit."
newline
hexmask.long.byte 0x10 8.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x10 0.--7. 1. "WR,OTT Write limit."
line.long 0x14 "XAIUEDR5,Limit evictions."
hexmask.long.tbyte 0x14 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x14 0.--7. 1. "EV,Limit evictions."
line.long 0x18 "XAIUEDR6,Credit adjustment per target type basis: 0x1: Max 1. 0x2: Max 2. 0x3: Max 3. 0x5: Minus 1. 0x6: Minus 2. 0x7: Minus 3. 0x9: 1 read others writes. 0xa: Reserve 1 write. 0xb: No limit. 0xd: reserve 1 extra write. 0xe: reserve 2 extra writes. 0xf:.."
hexmask.long.word 0x18 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x18 16.--19. 1. "QOS,QOS credit adjustment."
newline
hexmask.long.byte 0x18 12.--15. 1. "DVE,DVE credit adjustment."
newline
hexmask.long.byte 0x18 8.--11. 1. "DII,DII credit adjustment."
newline
hexmask.long.byte 0x18 4.--7. 1. "DMI,DMI credit adjustment."
newline
hexmask.long.byte 0x18 0.--3. 1. "DCE,DCE credit adjustment."
line.long 0x1C "XAIUEDR7,Specify period length for starvation detection"
hexmask.long.tbyte 0x1C 12.--31. 1. "TIME,Timer period in granularity of 2K."
newline
hexmask.long.word 0x1C 0.--11. 1. "EVENT,Event counter period in granularity of 16."
group.long 0x1C004B00++0xB
line.long 0x0 "XAIUCNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR0,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C004B10++0xB
line.long 0x0 "XAIUCNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR1,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C004B20++0xB
line.long 0x0 "XAIUCNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR2,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C004B30++0xB
line.long 0x0 "XAIUCNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "XAIUCNTVR3,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "XAIUCNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C004FF0++0x3
line.long 0x0 "XAIUNRSAR,CAIU Ncore Register Space Attribute Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "NRSAR,Set high to enable CSR access via this AIU." "0,1"
rgroup.long 0x1C004FF4++0x3
line.long 0x0 "XAIUENGIDR,XAIU Engineering ID Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C004FFC++0xB
line.long 0x0 "XAIUINFOR,XAIU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 20.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 16.--19. 1. "UST,Unit Type"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "DCEUIDR,DCEU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the DCEU is implemented." "0,1"
newline
hexmask.long.byte 0x4 24.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x4 12.--23. 1. "NUnitId,Ncore 3 Unit identifier."
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this DCEU resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,DCEU Register Page Number (within its NRR)"
line.long 0x8 "DCEUFUIDR,DCEU Fabric Unit Identification Register"
hexmask.long.word 0x8 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x8 0.--15. 1. "FUnitId,Fabric Unit Identifier of the unit"
group.long 0x1C005040++0x3
line.long 0x0 "DCEUTCR,DCEU Transaction Control Register"
hexmask.long 0x0 5.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 4. "EventDisable,Setting this disables Event handling." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "Rsvd1,Reserved"
rgroup.long 0x1C005044++0x3
line.long 0x0 "DCEUTAR,DCEU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the DCEU." "0,1"
group.long 0x1C005050++0x3
line.long 0x0 "DCEUSER0,DCEU Snoop Enable Register 0"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--4. 1. "SnpsEnb,Snoop Enable bits for Coherent agents 0..31. If a bit is set for an agent  Coherent-related snoop messages are enabled for that agent; otherwise  disabled."
group.long 0x1C005100++0x13
line.long 0x0 "DCEUCECR,DCEU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,This field determines the number of correctable errors that must be corrected before the Correctable Error Interrupt output signal is asserted."
newline
rbitfld.long 0x0 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,If this bit is set  the Correctable Error Interrupt output signal is asserted when the number of correctable errors corrected equals the value in ErrThreshold field; otherwise  the correctable error interrupt signal is never asserted." "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,If this bit is set  then correctable error detection and logging is enabled; otherwise  correctable error detection and logging is disabled." "0,1"
line.long 0x4 "DCEUCESR,DCEU Correctable Error Status Register"
hexmask.long.word 0x4 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Correctable Error Valid bit is set."
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,This field indicates the logged error type  if the Correctable Error Valid bit is set."
newline
rbitfld.long 0x4 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 2.--9. 1. "ErrCount,This field indicates the number of correctable errors detected by the unit. The field stops incrementing if the Correctable Error Count Overflow bit is set"
newline
rbitfld.long 0x4 1. "ErrCountOverflow,This bit indicates that the number of correctable errors detected by the unit overflowed the Correctable Error Count field" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Correctable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0x8 "DCEUCELR0,DCEU Correctable Error Location Registers 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0xC "DCEUCELR1,DCEU Correctable Error Location Registers 1"
hexmask.long.word 0xC 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x10 "DCEUCESAR,DCEU Correctable Error Status Alias Register"
hexmask.long.word 0x10 16.--31. 1. "ErrInfo,Alias bit for setting error info field of xCESR"
newline
hexmask.long.byte 0x10 12.--15. 1. "ErrType,Alias bit for setting error type field of xCESR"
newline
rbitfld.long 0x10 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x10 2.--9. 1. "ErrCount,Alias field for setting error Count field of xCESR"
newline
bitfld.long 0x10 1. "ErrCountOverflow,Alias bit for ssetting Error Count Overflow field of xCESR" "0,1"
newline
bitfld.long 0x10 0. "ErrVld,Alias bit for setting error valid field of xCESR" "0,1"
group.long 0x1C005140++0x17
line.long 0x0 "DCEUUEDR,DCEU Uncorrectable Error Detect Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 4. "TimeoutErrDetEn,Timeout protection error detection enable: When set  timeout errors will be detected." "0,1"
newline
bitfld.long 0x0 3. "DecErrDetEn,Decode Error Enable. When set  this bit enables detection of address map uncorrectable error" "0,1"
newline
bitfld.long 0x0 2. "MemErrDetEn,Memory protection error detection enable: When set errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "DCEUUEIR,DCEU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 4. "TimeoutErrIntEn,Timeout uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 3. "DecErrIntEn,Decode Error Interrupt Enable. When set  this bit enables the assertion of address map Uncorrectable Error Interrupt signal." "0,1"
newline
bitfld.long 0x4 2. "MemErrIntEn,RAM memory uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "DCEUUESR,DCEU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "DCEUUELR0,DCEU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "DCEUUELR1,DCEU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "DCEUUESAR,DCEU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C005190++0x3
line.long 0x0 "DCEUTOCR,Timeout Control Register"
bitfld.long 0x0 31. "TimeOutRefEn,Set to use reference singal input instead of counting every 4K cycle" "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TimeOutThreshold,Time out threshold value; counts in increments of 4K cycles."
group.long 0x1C005200++0x3
line.long 0x0 "DCEUQOSCR0,QoS Control Register"
hexmask.long.word 0x0 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "EventThreshold,Event threshold value counts every event (command issues) if value is 0 event count is disabled (event starvation disabled)."
group.long 0x1C005240++0x3
line.long 0x0 "DCEUSFMCR,DCEU Snoop Filter Maintenance Control Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "InitSnoopFilter,Toggle the bit to start snoop filter initialization." "0,1"
rgroup.long 0x1C005244++0x3
line.long 0x0 "DCEUSFMAR,DCEU Snoop Filter Maintenance Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "MntOpActv,This bit is set when any snoop filter maintenance is in progress and is clear otherwise" "0,1"
group.long 0x1C0053A0++0xB
line.long 0x0 "DCEUBRAR,Boot Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: DMI  1:DII" "0: DMI,1: DII"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.word 0x0 0.--8. 1. "Rsvd1,Reserved"
line.long 0x4 "DCEUBRBLR,Boot Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUBRBHR,Boot Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0053C0++0x7
line.long 0x0 "DCEUAMIGR,Active Memory Interleave Group Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 1.--4. 1. "AMIGS,Active Memory Interleave Group Set in use currenlty when Valid is set"
newline
bitfld.long 0x0 0. "Valid,Memory Interleave Group Set valid  when set the MIGS specified in AMIGS field is being used for DMI interleaving else MIGS 0 is used by default" "0,1"
line.long 0x4 "DCEUMIFSR,Memory Interleave Function Select Register"
hexmask.long.byte 0x4 27.--31. 1. "Rsvd5,Reserved"
newline
bitfld.long 0x4 24.--26. "MIG16AIFId,Active function ID for 16 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 19.--23. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x4 16.--18. "MIG8AIFId,Active function ID for 8 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 11.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x4 8.--10. "MIG4AIFId,Active function ID for 4 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 7. "Rsvd2,Reserved" "0,1"
newline
bitfld.long 0x4 4.--6. "MIG3AIFId,Active function ID for 3 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x4 0.--2. "MIG2AIFId,Active function ID for 2 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
group.long 0x1C005400++0xB
line.long 0x0 "DCEUGPRAR0,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR0,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR0,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C005410++0xB
line.long 0x0 "DCEUGPRAR1,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR1,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR1,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C005420++0xB
line.long 0x0 "DCEUGPRAR2,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR2,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR2,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C005430++0xB
line.long 0x0 "DCEUGPRAR3,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR3,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR3,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C005440++0xB
line.long 0x0 "DCEUGPRAR4,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR4,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR4,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C005450++0xB
line.long 0x0 "DCEUGPRAR5,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR5,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR5,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C005460++0xB
line.long 0x0 "DCEUGPRAR6,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR6,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR6,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C005470++0xB
line.long 0x0 "DCEUGPRAR7,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR7,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR7,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C005480++0xB
line.long 0x0 "DCEUGPRAR8,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR8,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR8,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C005490++0xB
line.long 0x0 "DCEUGPRAR9,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR9,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR9,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0054A0++0xB
line.long 0x0 "DCEUGPRAR10,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR10,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR10,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0054B0++0xB
line.long 0x0 "DCEUGPRAR11,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR11,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR11,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C005A00++0x3
line.long 0x0 "DCEUEDR0,Engineering Debug Register 0"
hexmask.long 0x0 0.--31. 1. "CfgCtrl"
group.long 0x1C005B00++0xB
line.long 0x0 "DCECNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DCECNTVR0,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DCECNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C005B10++0xB
line.long 0x0 "DCECNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DCECNTVR1,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DCECNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C005B20++0xB
line.long 0x0 "DCECNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DCECNTVR2,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DCECNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C005B30++0xB
line.long 0x0 "DCECNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DCECNTVR3,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DCECNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
rgroup.long 0x1C005FF4++0x3
line.long 0x0 "DCEUENGIDR,DCEU Engineering ID Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C005FFC++0xB
line.long 0x0 "DCEUINFOR,DCEU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 16.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "DCEUIDR,DCEU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the DCEU is implemented." "0,1"
newline
hexmask.long.byte 0x4 24.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x4 12.--23. 1. "NUnitId,Ncore 3 Unit identifier."
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this DCEU resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,DCEU Register Page Number (within its NRR)"
line.long 0x8 "DCEUFUIDR,DCEU Fabric Unit Identification Register"
hexmask.long.word 0x8 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x8 0.--15. 1. "FUnitId,Fabric Unit Identifier of the unit"
group.long 0x1C006040++0x3
line.long 0x0 "DCEUTCR,DCEU Transaction Control Register"
hexmask.long 0x0 5.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 4. "EventDisable,Setting this disables Event handling." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "Rsvd1,Reserved"
rgroup.long 0x1C006044++0x3
line.long 0x0 "DCEUTAR,DCEU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the DCEU." "0,1"
group.long 0x1C006050++0x3
line.long 0x0 "DCEUSER0,DCEU Snoop Enable Register 0"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--4. 1. "SnpsEnb,Snoop Enable bits for Coherent agents 0..31. If a bit is set for an agent  Coherent-related snoop messages are enabled for that agent; otherwise  disabled."
group.long 0x1C006100++0x13
line.long 0x0 "DCEUCECR,DCEU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,This field determines the number of correctable errors that must be corrected before the Correctable Error Interrupt output signal is asserted."
newline
rbitfld.long 0x0 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,If this bit is set  the Correctable Error Interrupt output signal is asserted when the number of correctable errors corrected equals the value in ErrThreshold field; otherwise  the correctable error interrupt signal is never asserted." "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,If this bit is set  then correctable error detection and logging is enabled; otherwise  correctable error detection and logging is disabled." "0,1"
line.long 0x4 "DCEUCESR,DCEU Correctable Error Status Register"
hexmask.long.word 0x4 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Correctable Error Valid bit is set."
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,This field indicates the logged error type  if the Correctable Error Valid bit is set."
newline
rbitfld.long 0x4 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 2.--9. 1. "ErrCount,This field indicates the number of correctable errors detected by the unit. The field stops incrementing if the Correctable Error Count Overflow bit is set"
newline
rbitfld.long 0x4 1. "ErrCountOverflow,This bit indicates that the number of correctable errors detected by the unit overflowed the Correctable Error Count field" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Correctable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0x8 "DCEUCELR0,DCEU Correctable Error Location Registers 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0xC "DCEUCELR1,DCEU Correctable Error Location Registers 1"
hexmask.long.word 0xC 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x10 "DCEUCESAR,DCEU Correctable Error Status Alias Register"
hexmask.long.word 0x10 16.--31. 1. "ErrInfo,Alias bit for setting error info field of xCESR"
newline
hexmask.long.byte 0x10 12.--15. 1. "ErrType,Alias bit for setting error type field of xCESR"
newline
rbitfld.long 0x10 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x10 2.--9. 1. "ErrCount,Alias field for setting error Count field of xCESR"
newline
bitfld.long 0x10 1. "ErrCountOverflow,Alias bit for ssetting Error Count Overflow field of xCESR" "0,1"
newline
bitfld.long 0x10 0. "ErrVld,Alias bit for setting error valid field of xCESR" "0,1"
group.long 0x1C006140++0x17
line.long 0x0 "DCEUUEDR,DCEU Uncorrectable Error Detect Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 4. "TimeoutErrDetEn,Timeout protection error detection enable: When set  timeout errors will be detected." "0,1"
newline
bitfld.long 0x0 3. "DecErrDetEn,Decode Error Enable. When set  this bit enables detection of address map uncorrectable error" "0,1"
newline
bitfld.long 0x0 2. "MemErrDetEn,Memory protection error detection enable: When set errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "DCEUUEIR,DCEU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 4. "TimeoutErrIntEn,Timeout uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 3. "DecErrIntEn,Decode Error Interrupt Enable. When set  this bit enables the assertion of address map Uncorrectable Error Interrupt signal." "0,1"
newline
bitfld.long 0x4 2. "MemErrIntEn,RAM memory uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "DCEUUESR,DCEU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "DCEUUELR0,DCEU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "DCEUUELR1,DCEU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "DCEUUESAR,DCEU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C006190++0x3
line.long 0x0 "DCEUTOCR,Timeout Control Register"
bitfld.long 0x0 31. "TimeOutRefEn,Set to use reference singal input instead of counting every 4K cycle" "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TimeOutThreshold,Time out threshold value; counts in increments of 4K cycles."
group.long 0x1C006200++0x3
line.long 0x0 "DCEUQOSCR0,QoS Control Register"
hexmask.long.word 0x0 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "EventThreshold,Event threshold value counts every event (command issues) if value is 0 event count is disabled (event starvation disabled)."
group.long 0x1C006240++0x3
line.long 0x0 "DCEUSFMCR,DCEU Snoop Filter Maintenance Control Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "InitSnoopFilter,Toggle the bit to start snoop filter initialization." "0,1"
rgroup.long 0x1C006244++0x3
line.long 0x0 "DCEUSFMAR,DCEU Snoop Filter Maintenance Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "MntOpActv,This bit is set when any snoop filter maintenance is in progress and is clear otherwise" "0,1"
group.long 0x1C0063A0++0xB
line.long 0x0 "DCEUBRAR,Boot Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: DMI  1:DII" "0: DMI,1: DII"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.word 0x0 0.--8. 1. "Rsvd1,Reserved"
line.long 0x4 "DCEUBRBLR,Boot Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUBRBHR,Boot Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0063C0++0x7
line.long 0x0 "DCEUAMIGR,Active Memory Interleave Group Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 1.--4. 1. "AMIGS,Active Memory Interleave Group Set in use currenlty when Valid is set"
newline
bitfld.long 0x0 0. "Valid,Memory Interleave Group Set valid  when set the MIGS specified in AMIGS field is being used for DMI interleaving else MIGS 0 is used by default" "0,1"
line.long 0x4 "DCEUMIFSR,Memory Interleave Function Select Register"
hexmask.long.byte 0x4 27.--31. 1. "Rsvd5,Reserved"
newline
bitfld.long 0x4 24.--26. "MIG16AIFId,Active function ID for 16 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 19.--23. 1. "Rsvd4,Reserved"
newline
bitfld.long 0x4 16.--18. "MIG8AIFId,Active function ID for 8 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 11.--15. 1. "Rsvd3,Reserved"
newline
bitfld.long 0x4 8.--10. "MIG4AIFId,Active function ID for 4 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 7. "Rsvd2,Reserved" "0,1"
newline
bitfld.long 0x4 4.--6. "MIG3AIFId,Active function ID for 3 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x4 0.--2. "MIG2AIFId,Active function ID for 2 way interleaving. Selects the address bits to be used for interleaving of DMI within the selected MIGS" "0,1,2,3,4,5,6,7"
group.long 0x1C006400++0xB
line.long 0x0 "DCEUGPRAR0,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR0,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR0,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C006410++0xB
line.long 0x0 "DCEUGPRAR1,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR1,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR1,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C006420++0xB
line.long 0x0 "DCEUGPRAR2,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR2,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR2,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C006430++0xB
line.long 0x0 "DCEUGPRAR3,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR3,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR3,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C006440++0xB
line.long 0x0 "DCEUGPRAR4,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR4,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR4,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C006450++0xB
line.long 0x0 "DCEUGPRAR5,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR5,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR5,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C006460++0xB
line.long 0x0 "DCEUGPRAR6,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR6,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR6,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C006470++0xB
line.long 0x0 "DCEUGPRAR7,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR7,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR7,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C006480++0xB
line.long 0x0 "DCEUGPRAR8,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR8,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR8,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C006490++0xB
line.long 0x0 "DCEUGPRAR9,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR9,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR9,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0064A0++0xB
line.long 0x0 "DCEUGPRAR10,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR10,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR10,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C0064B0++0xB
line.long 0x0 "DCEUGPRAR11,General Pusrpose Region Attribute Register"
bitfld.long 0x0 31. "Valid,This bit indicates if the region is valid - 0: Invalid mapping  1:Valid region mapping" "0: Invalid mapping,1: Valid region mapping"
newline
bitfld.long 0x0 30. "HUT,This bit indicates the Home Unit Type- 0: System Memory  1:Peripheral Storage" "0: System Memory,1: Peripheral Storage"
newline
hexmask.long.byte 0x0 25.--29. 1. "Rsvd3,Reserved"
newline
hexmask.long.byte 0x0 20.--24. 1. "Size,This field indicates a binary number from 0 to 31 from which the region's Size is calculated as (Size of IG) * 2 ^(Size +12) bytes"
newline
hexmask.long.byte 0x0 14.--19. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 9.--13. 1. "HUI,This bit indicates the Home unit identifier of the access"
newline
hexmask.long.byte 0x0 5.--8. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 3.--4. "Policy,Applicable only for NCAIU  ordering Policy:" "0: Reserved,?,?,?"
newline
bitfld.long 0x0 2. "WriteID,Applicable only for NCAIU  when set AWID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 1. "ReadID,Applicable only for NCAIU  when set ARID ordering in terms of execution is not garunteed within Ncore  responses are still issued in order" "0,1"
newline
bitfld.long 0x0 0. "Hazard,Ignore all address related hazards." "0,1"
line.long 0x4 "DCEUGPRBLR11,General Purpose Region Base Lower Register"
hexmask.long 0x4 0.--31. 1. "AddrLow,Lower order bits 43:12 of the base address of the region"
line.long 0x8 "DCEUGPRBHR11,General Purpose Region Base Higher Register"
hexmask.long.tbyte 0x8 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--7. 1. "AddrHigh,Higher order bits 51:44 of the base address of the region"
group.long 0x1C006A00++0x3
line.long 0x0 "DCEUEDR0,Engineering Debug Register 0"
hexmask.long 0x0 0.--31. 1. "CfgCtrl"
group.long 0x1C006B00++0xB
line.long 0x0 "DCECNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DCECNTVR0,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DCECNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C006B10++0xB
line.long 0x0 "DCECNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DCECNTVR1,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DCECNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C006B20++0xB
line.long 0x0 "DCECNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DCECNTVR2,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DCECNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C006B30++0xB
line.long 0x0 "DCECNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DCECNTVR3,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DCECNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
rgroup.long 0x1C006FF4++0x3
line.long 0x0 "DCEUENGIDR,DCEU Engineering ID Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C006FFC++0xB
line.long 0x0 "DCEUINFOR,DCEU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 16.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "DMIUIDR,DMIU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the DMIU is implemented" "0,1"
newline
hexmask.long.word 0x4 15.--30. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 12.--14. "NUnitId,Ncore 3 Unit identifier" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this DMIU resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,Distributed Memory Interface Unit Register Page Number (within its NRR)"
line.long 0x8 "DMIUFUIDR,DMIU Fabric Unit Identification Register"
hexmask.long 0x8 4.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x8 0.--3. 1. "FUnitId,Fabric Unit Identifier of the unit"
rgroup.long 0x1C007044++0x3
line.long 0x0 "DMIUTAR,DMIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the DMIU" "0,1"
group.long 0x1C007100++0x17
line.long 0x0 "DMIUUEDR,DMIU Uncorrectable Error Detect Register"
hexmask.long 0x0 5.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 4. "TimeoutErrDetEn,Timeout protection error detection enable: When set  timeout errors will be detected." "0,1"
newline
rbitfld.long 0x0 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x0 2. "MemErrDetEn,Memory protection error detection enable: When set errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "DMIUUEIR,DMIU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 5.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x4 4. "TimeoutErrIntEn,Timeout uncorrectable error interrupt enable." "0,1"
newline
rbitfld.long 0x4 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x4 2. "MemErrIntEn,SRAM memory uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "DMIUUESR,DMIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "DMIUUELR0,DMIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "DMIUUELR1,DMIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "DMIUUESAR,DMIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C007140++0x13
line.long 0x0 "DMIUCECR,DMIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,This field determines the number of correctable errors that must be corrected before the Correctable Error Interrupt output signal is asserted."
newline
rbitfld.long 0x0 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,If this bit is set  the Correctable Error Interrupt output signal is asserted when the number of correctable errors corrected equals the value in ErrThreshold field; otherwise  the correctable error interrupt signal is never asserted." "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,If this bit is set  then correctable error detection and logging is enabled; otherwise  correctable error detection and logging is disabled." "0,1"
line.long 0x4 "DMIUCESR,DMIU Correctable Error Status Register"
hexmask.long.word 0x4 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Correctable Error Valid bit is set."
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,This field indicates the logged error type  if the Correctable Error Valid bit is set."
newline
rbitfld.long 0x4 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 2.--9. 1. "ErrCount,This field indicates the number of correctable errors detected by the unit. The field stops incrementing if the Correctable Error Count Overflow bit is set"
newline
rbitfld.long 0x4 1. "ErrCountOverflow,This bit indicates that the number of correctable errors detected by the unit overflowed the Correctable Error Count field" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Correctable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0x8 "DMIUCELR0,DMIU Correctable Error Location Registers 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0xC "DMIUCELR1,DMIU Correctable Error Location Registers 1"
hexmask.long.word 0xC 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x10 "DMIUCESAR,DMIU Correctable Error Status Alias Register"
hexmask.long.word 0x10 16.--31. 1. "ErrInfo,Alias bit for setting error info field of xCESR"
newline
hexmask.long.byte 0x10 12.--15. 1. "ErrType,Alias bit for setting error type field of xCESR"
newline
rbitfld.long 0x10 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x10 2.--9. 1. "ErrCount,Alias field for setting error Count field of xCESR"
newline
bitfld.long 0x10 1. "ErrCountOverflow,Alias bit for ssetting Error Count Overflow field of xCESR" "0,1"
newline
bitfld.long 0x10 0. "ErrVld,Alias bit for setting error valid field of xCESR" "0,1"
group.long 0x1C007190++0x3
line.long 0x0 "DMIUTOCR,Timeout Control Register"
bitfld.long 0x0 31. "TimeOutRefEn,Set to use reference singal input instead of counting every 4K cycle" "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TimeOutThreshold,Time out threshold value; counts in increments of 4K cycles."
group.long 0x1C007200++0x3
line.long 0x0 "DMIUQOSCR0,QoS Control Register"
hexmask.long.word 0x0 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "EventThreshold,Event threshold value counts every event (command issues) if value is 0 event count is disabled (event starvation disabled)."
group.long 0x1C007300++0x3
line.long 0x0 "DMIUSMCTCR,DMIU System Memory Cache Transaction Control Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "AllocEn,This bit enables allocation into system memory cache." "0,1"
newline
bitfld.long 0x0 0. "LookupEn,This bit enables system memory cache." "0,1"
rgroup.long 0x1C007304++0x3
line.long 0x0 "DMIUSMCTAR,DMIU System Memory Cache Transaction Activity Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "AllocActive,This bit is set when the unit is performing any system memory cache allocation activity and is cleared otherwise." "0,1"
newline
bitfld.long 0x0 0. "EvictActive,This bit is set when the unit is performing any system memory cache eviction activity and is cleared otherwise" "0,1"
group.long 0x1C007308++0x3
line.long 0x0 "DMIUSMCAPR,DMIU System Memory Cache Allocation Policy Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 4. "WrAllocDisable,This bit disables cache allocation for writes" "0,1"
newline
bitfld.long 0x0 3. "RdAllocDisable,This bit disables cache allocation for reads" "0,1"
newline
bitfld.long 0x0 2. "DtyWrAllocDisable,This bit disables cache allocation for dirty writes" "0,1"
newline
bitfld.long 0x0 1. "ClnWrAllocDisable,This bit disables cache allocation for clean writes" "0,1"
newline
bitfld.long 0x0 0. "TOFAllocDisable,This bit disables cache allocation for writeUnique from CHI/ACE processors" "0,1"
rgroup.long 0x1C00730C++0x3
line.long 0x0 "DMIUSMCISR,DMIU System Memory Cache Initializtion Status Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "DataInitDone,This bit is set when SMC data initialization is done" "0,1"
newline
bitfld.long 0x0 0. "TagInitDone,This bit is set when SMC tag initialization is done" "0,1"
group.long 0x1C007340++0x3
line.long 0x0 "DMIUSMCMCR,DMIU System Memory Cache Maintenance Control Register"
hexmask.long.word 0x0 23.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 22. "SecAttr,This bit indicates the value of the security attribute of the address for the cache maintenance operation is to be performed." "0,1"
newline
hexmask.long.byte 0x0 16.--21. 1. "ArrayID,This field selects the array on which the cache maintenance operation is to be performed:"
newline
hexmask.long.word 0x0 4.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--3. 1. "MntOp,This field encodes the cache maintenance operation to be performed:"
rgroup.long 0x1C007344++0x3
line.long 0x0 "DMIUSMCMAR,DMIU System Memory Cache Maintenance Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "MntOpActv,This bit is set when any cache maintenance operation is in progress and is clear otherwise" "0,1"
group.long 0x1C007348++0xB
line.long 0x0 "DMIUSMCMLR0,DMIU System Memory Cache Maintenance Location Register 0"
hexmask.long.byte 0x0 26.--31. 1. "MntWord,This field indicates the data word on which the maintenance operation is to be performed."
newline
hexmask.long.byte 0x0 20.--25. 1. "MntWay,This field indicates the way on which the maintenance operation is to be performed."
newline
hexmask.long.tbyte 0x0 0.--19. 1. "MntSet,The field indicates the set on which the maintenance operation is to be performed"
line.long 0x4 "DMIUSMCMLR1,DMIU System Memory Cache Maintenance Location Register 1"
hexmask.long.word 0x4 16.--31. 1. "MntRange,This field indicates the range for flush operations in number of cache lines."
newline
hexmask.long.word 0x4 0.--15. 1. "MntAddr,This field contains the high-order address bits of the address on which the maintenance operation is to be performed"
line.long 0x8 "DMIUSMCMDR,DMIU System Memory Cache Maintenance Data Register"
hexmask.long 0x8 0.--31. 1. "MntData,This field contains the data resulting from a maintenance read operation or the data to be used for a maintenance write operation."
group.long 0x1C007800++0x3
line.long 0x0 "DMICCTRLR,AIU Unit Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
group.long 0x1C007B00++0xB
line.long 0x0 "DMICNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DMICNTVR0,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DMICNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C007B10++0xB
line.long 0x0 "DMICNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DMICNTVR1,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DMICNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C007B20++0xB
line.long 0x0 "DMICNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DMICNTVR2,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DMICNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C007B30++0xB
line.long 0x0 "DMICNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DMICNTVR3,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DMICNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
rgroup.long 0x1C007FF4++0x13
line.long 0x0 "DMIUEVIDR,DMIU Engineering Version Id Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
line.long 0x4 "DMIUSMCIFR,DMIU System Memory Cache Information Register"
hexmask.long.byte 0x4 28.--31. 1. "nWP,Number of way partitioning register pair minus one"
newline
bitfld.long 0x4 27. "WP,Way Partitioning support exist" "0,1"
newline
bitfld.long 0x4 26. "SP,This field indicates if scratch pad feature is eanbled when set" "0,1"
newline
hexmask.long.byte 0x4 20.--25. 1. "NumWay,This field indicates the number of ways(i.e. the associativity) minus one in the system memory cache"
newline
hexmask.long.tbyte 0x4 0.--19. 1. "NumSet,This field indicates the number of sets in the system memory cache minus one in this DMIU. To determine the total number of sets in the system memory cache  this value must be multiplied by the number of DMIUs that implement the system memory cache"
line.long 0x8 "DMIUINFOR,DMIU Information Register"
bitfld.long 0x8 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x8 22.--30. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x8 21. "AE,Atomic Engine Present" "0,1"
newline
bitfld.long 0x8 20. "SMC,System Memory Cache Present" "0,1"
newline
hexmask.long.byte 0x8 16.--19. 1. "UST,Unit sub Type: specifies the Ncore unit native interface type"
newline
hexmask.long.byte 0x8 12.--15. 1. "UT,Unit Type: specifies the Ncore unit type"
newline
hexmask.long.word 0x8 0.--11. 1. "ImplVer,Implementation Version"
line.long 0xC "DMIUIDR,DMIU Identification Register"
bitfld.long 0xC 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the DMIU is implemented" "0,1"
newline
hexmask.long.word 0xC 15.--30. 1. "Rsvd1,Reserved"
newline
bitfld.long 0xC 12.--14. "NUnitId,Ncore 3 Unit identifier" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xC 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this DMIU resides"
newline
hexmask.long.byte 0xC 0.--7. 1. "RPN,Distributed Memory Interface Unit Register Page Number (within its NRR)"
line.long 0x10 "DMIUFUIDR,DMIU Fabric Unit Identification Register"
hexmask.long 0x10 4.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x10 0.--3. 1. "FUnitId,Fabric Unit Identifier of the unit"
rgroup.long 0x1C008044++0x3
line.long 0x0 "DMIUTAR,DMIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the DMIU" "0,1"
group.long 0x1C008100++0x17
line.long 0x0 "DMIUUEDR,DMIU Uncorrectable Error Detect Register"
hexmask.long 0x0 5.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 4. "TimeoutErrDetEn,Timeout protection error detection enable: When set  timeout errors will be detected." "0,1"
newline
rbitfld.long 0x0 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x0 2. "MemErrDetEn,Memory protection error detection enable: When set errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "DMIUUEIR,DMIU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 5.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x4 4. "TimeoutErrIntEn,Timeout uncorrectable error interrupt enable." "0,1"
newline
rbitfld.long 0x4 3. "Rsvd1,Reserved" "0,1"
newline
bitfld.long 0x4 2. "MemErrIntEn,SRAM memory uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "DMIUUESR,DMIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "DMIUUELR0,DMIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "DMIUUELR1,DMIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "DMIUUESAR,DMIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C008140++0x13
line.long 0x0 "DMIUCECR,DMIU Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,This field determines the number of correctable errors that must be corrected before the Correctable Error Interrupt output signal is asserted."
newline
rbitfld.long 0x0 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,If this bit is set  the Correctable Error Interrupt output signal is asserted when the number of correctable errors corrected equals the value in ErrThreshold field; otherwise  the correctable error interrupt signal is never asserted." "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,If this bit is set  then correctable error detection and logging is enabled; otherwise  correctable error detection and logging is disabled." "0,1"
line.long 0x4 "DMIUCESR,DMIU Correctable Error Status Register"
hexmask.long.word 0x4 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Correctable Error Valid bit is set."
newline
hexmask.long.byte 0x4 12.--15. 1. "ErrType,This field indicates the logged error type  if the Correctable Error Valid bit is set."
newline
rbitfld.long 0x4 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x4 2.--9. 1. "ErrCount,This field indicates the number of correctable errors detected by the unit. The field stops incrementing if the Correctable Error Count Overflow bit is set"
newline
rbitfld.long 0x4 1. "ErrCountOverflow,This bit indicates that the number of correctable errors detected by the unit overflowed the Correctable Error Count field" "0,1"
newline
eventfld.long 0x4 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Correctable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0x8 "DMIUCELR0,DMIU Correctable Error Location Registers 0"
hexmask.long.byte 0x8 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0x8 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0xC "DMIUCELR1,DMIU Correctable Error Location Registers 1"
hexmask.long.word 0xC 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x10 "DMIUCESAR,DMIU Correctable Error Status Alias Register"
hexmask.long.word 0x10 16.--31. 1. "ErrInfo,Alias bit for setting error info field of xCESR"
newline
hexmask.long.byte 0x10 12.--15. 1. "ErrType,Alias bit for setting error type field of xCESR"
newline
rbitfld.long 0x10 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x10 2.--9. 1. "ErrCount,Alias field for setting error Count field of xCESR"
newline
bitfld.long 0x10 1. "ErrCountOverflow,Alias bit for ssetting Error Count Overflow field of xCESR" "0,1"
newline
bitfld.long 0x10 0. "ErrVld,Alias bit for setting error valid field of xCESR" "0,1"
group.long 0x1C008190++0x3
line.long 0x0 "DMIUTOCR,Timeout Control Register"
bitfld.long 0x0 31. "TimeOutRefEn,Set to use reference singal input instead of counting every 4K cycle" "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TimeOutThreshold,Time out threshold value; counts in increments of 4K cycles."
group.long 0x1C008200++0x3
line.long 0x0 "DMIUQOSCR0,QoS Control Register"
hexmask.long.word 0x0 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "EventThreshold,Event threshold value counts every event (command issues) if value is 0 event count is disabled (event starvation disabled)."
group.long 0x1C008300++0x3
line.long 0x0 "DMIUSMCTCR,DMIU System Memory Cache Transaction Control Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "AllocEn,This bit enables allocation into system memory cache." "0,1"
newline
bitfld.long 0x0 0. "LookupEn,This bit enables system memory cache." "0,1"
rgroup.long 0x1C008304++0x3
line.long 0x0 "DMIUSMCTAR,DMIU System Memory Cache Transaction Activity Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "AllocActive,This bit is set when the unit is performing any system memory cache allocation activity and is cleared otherwise." "0,1"
newline
bitfld.long 0x0 0. "EvictActive,This bit is set when the unit is performing any system memory cache eviction activity and is cleared otherwise" "0,1"
group.long 0x1C008308++0x3
line.long 0x0 "DMIUSMCAPR,DMIU System Memory Cache Allocation Policy Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 4. "WrAllocDisable,This bit disables cache allocation for writes" "0,1"
newline
bitfld.long 0x0 3. "RdAllocDisable,This bit disables cache allocation for reads" "0,1"
newline
bitfld.long 0x0 2. "DtyWrAllocDisable,This bit disables cache allocation for dirty writes" "0,1"
newline
bitfld.long 0x0 1. "ClnWrAllocDisable,This bit disables cache allocation for clean writes" "0,1"
newline
bitfld.long 0x0 0. "TOFAllocDisable,This bit disables cache allocation for writeUnique from CHI/ACE processors" "0,1"
rgroup.long 0x1C00830C++0x3
line.long 0x0 "DMIUSMCISR,DMIU System Memory Cache Initializtion Status Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "DataInitDone,This bit is set when SMC data initialization is done" "0,1"
newline
bitfld.long 0x0 0. "TagInitDone,This bit is set when SMC tag initialization is done" "0,1"
group.long 0x1C008340++0x3
line.long 0x0 "DMIUSMCMCR,DMIU System Memory Cache Maintenance Control Register"
hexmask.long.word 0x0 23.--31. 1. "Rsvd2,Reserved"
newline
bitfld.long 0x0 22. "SecAttr,This bit indicates the value of the security attribute of the address for the cache maintenance operation is to be performed." "0,1"
newline
hexmask.long.byte 0x0 16.--21. 1. "ArrayID,This field selects the array on which the cache maintenance operation is to be performed:"
newline
hexmask.long.word 0x0 4.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--3. 1. "MntOp,This field encodes the cache maintenance operation to be performed:"
rgroup.long 0x1C008344++0x3
line.long 0x0 "DMIUSMCMAR,DMIU System Memory Cache Maintenance Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "MntOpActv,This bit is set when any cache maintenance operation is in progress and is clear otherwise" "0,1"
group.long 0x1C008348++0xB
line.long 0x0 "DMIUSMCMLR0,DMIU System Memory Cache Maintenance Location Register 0"
hexmask.long.byte 0x0 26.--31. 1. "MntWord,This field indicates the data word on which the maintenance operation is to be performed."
newline
hexmask.long.byte 0x0 20.--25. 1. "MntWay,This field indicates the way on which the maintenance operation is to be performed."
newline
hexmask.long.tbyte 0x0 0.--19. 1. "MntSet,The field indicates the set on which the maintenance operation is to be performed"
line.long 0x4 "DMIUSMCMLR1,DMIU System Memory Cache Maintenance Location Register 1"
hexmask.long.word 0x4 16.--31. 1. "MntRange,This field indicates the range for flush operations in number of cache lines."
newline
hexmask.long.word 0x4 0.--15. 1. "MntAddr,This field contains the high-order address bits of the address on which the maintenance operation is to be performed"
line.long 0x8 "DMIUSMCMDR,DMIU System Memory Cache Maintenance Data Register"
hexmask.long 0x8 0.--31. 1. "MntData,This field contains the data resulting from a maintenance read operation or the data to be used for a maintenance write operation."
group.long 0x1C008800++0x3
line.long 0x0 "DMICCTRLR,AIU Unit Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
group.long 0x1C008B00++0xB
line.long 0x0 "DMICNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DMICNTVR0,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DMICNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C008B10++0xB
line.long 0x0 "DMICNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DMICNTVR1,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DMICNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C008B20++0xB
line.long 0x0 "DMICNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DMICNTVR2,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DMICNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C008B30++0xB
line.long 0x0 "DMICNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DMICNTVR3,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DMICNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
rgroup.long 0x1C008FF4++0x13
line.long 0x0 "DMIUEVIDR,DMIU Engineering Version Id Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
line.long 0x4 "DMIUSMCIFR,DMIU System Memory Cache Information Register"
hexmask.long.byte 0x4 28.--31. 1. "nWP,Number of way partitioning register pair minus one"
newline
bitfld.long 0x4 27. "WP,Way Partitioning support exist" "0,1"
newline
bitfld.long 0x4 26. "SP,This field indicates if scratch pad feature is eanbled when set" "0,1"
newline
hexmask.long.byte 0x4 20.--25. 1. "NumWay,This field indicates the number of ways(i.e. the associativity) minus one in the system memory cache"
newline
hexmask.long.tbyte 0x4 0.--19. 1. "NumSet,This field indicates the number of sets in the system memory cache minus one in this DMIU. To determine the total number of sets in the system memory cache  this value must be multiplied by the number of DMIUs that implement the system memory cache"
line.long 0x8 "DMIUINFOR,DMIU Information Register"
bitfld.long 0x8 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x8 22.--30. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x8 21. "AE,Atomic Engine Present" "0,1"
newline
bitfld.long 0x8 20. "SMC,System Memory Cache Present" "0,1"
newline
hexmask.long.byte 0x8 16.--19. 1. "UST,Unit sub Type: specifies the Ncore unit native interface type"
newline
hexmask.long.byte 0x8 12.--15. 1. "UT,Unit Type: specifies the Ncore unit type"
newline
hexmask.long.word 0x8 0.--11. 1. "ImplVer,Implementation Version"
line.long 0xC "DIIUIDR,DIIU Identification Register"
bitfld.long 0xC 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the DIIU is implemented." "0,1"
newline
hexmask.long.byte 0xC 24.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0xC 12.--23. 1. "NUnitId,Ncore 3 Unit identifier."
newline
hexmask.long.byte 0xC 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this DIIU resides"
newline
hexmask.long.byte 0xC 0.--7. 1. "RPN,DIIU Register Page Number (within its NRR)"
line.long 0x10 "DIIUFUIDR,DIIU Fabric Unit Identification Register"
hexmask.long.word 0x10 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x10 0.--15. 1. "FUnitId,Fabric Unit Identifier of the unit"
rgroup.long 0x1C009040++0x3
line.long 0x0 "DIIUTAR,DIIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the DIIU." "0,1"
group.long 0x1C009118++0x17
line.long 0x0 "DIIUUEDR,DIIU Uncorrectable Error Detect Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "DIIUUEIR,DIIU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "DIIUUESR,DIIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "DIIUUELR0,DIIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "DIIUUELR1,DIIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "DIIUUESAR,DIIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C009900++0x3
line.long 0x0 "DIICCTRLR,DIIU Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
group.long 0x1C009B00++0xB
line.long 0x0 "DIICNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR0,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C009B10++0xB
line.long 0x0 "DIICNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR1,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C009B20++0xB
line.long 0x0 "DIICNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR2,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C009B30++0xB
line.long 0x0 "DIICNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR3,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
rgroup.long 0x1C009FF4++0x3
line.long 0x0 "DIIUUEVIR,DIIU Unit Engineering Version Id Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C009FFC++0xB
line.long 0x0 "DIIUINFOR,DIIU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 20.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 16.--19. 1. "UST,Unit sub Type: specifies the Ncore unit native interface type"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type: specifies the Ncore unit type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "DIIUIDR,DIIU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the DIIU is implemented." "0,1"
newline
hexmask.long.byte 0x4 24.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x4 12.--23. 1. "NUnitId,Ncore 3 Unit identifier."
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this DIIU resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,DIIU Register Page Number (within its NRR)"
line.long 0x8 "DIIUFUIDR,DIIU Fabric Unit Identification Register"
hexmask.long.word 0x8 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x8 0.--15. 1. "FUnitId,Fabric Unit Identifier of the unit"
rgroup.long 0x1C00A040++0x3
line.long 0x0 "DIIUTAR,DIIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the DIIU." "0,1"
group.long 0x1C00A118++0x17
line.long 0x0 "DIIUUEDR,DIIU Uncorrectable Error Detect Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "DIIUUEIR,DIIU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "DIIUUESR,DIIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "DIIUUELR0,DIIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "DIIUUELR1,DIIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "DIIUUESAR,DIIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C00A900++0x3
line.long 0x0 "DIICCTRLR,DIIU Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
group.long 0x1C00AB00++0xB
line.long 0x0 "DIICNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR0,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00AB10++0xB
line.long 0x0 "DIICNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR1,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00AB20++0xB
line.long 0x0 "DIICNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR2,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00AB30++0xB
line.long 0x0 "DIICNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR3,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
rgroup.long 0x1C00AFF4++0x3
line.long 0x0 "DIIUUEVIR,DIIU Unit Engineering Version Id Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C00AFFC++0xB
line.long 0x0 "DIIUINFOR,DIIU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 20.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 16.--19. 1. "UST,Unit sub Type: specifies the Ncore unit native interface type"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type: specifies the Ncore unit type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "DIIUIDR,DIIU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the DIIU is implemented." "0,1"
newline
hexmask.long.byte 0x4 24.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x4 12.--23. 1. "NUnitId,Ncore 3 Unit identifier."
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this DIIU resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,DIIU Register Page Number (within its NRR)"
line.long 0x8 "DIIUFUIDR,DIIU Fabric Unit Identification Register"
hexmask.long.word 0x8 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x8 0.--15. 1. "FUnitId,Fabric Unit Identifier of the unit"
rgroup.long 0x1C00B040++0x3
line.long 0x0 "DIIUTAR,DIIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the DIIU." "0,1"
group.long 0x1C00B118++0x17
line.long 0x0 "DIIUUEDR,DIIU Uncorrectable Error Detect Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "DIIUUEIR,DIIU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "DIIUUESR,DIIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "DIIUUELR0,DIIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "DIIUUELR1,DIIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "DIIUUESAR,DIIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C00B900++0x3
line.long 0x0 "DIICCTRLR,DIIU Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
group.long 0x1C00BB00++0xB
line.long 0x0 "DIICNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR0,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00BB10++0xB
line.long 0x0 "DIICNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR1,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00BB20++0xB
line.long 0x0 "DIICNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR2,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00BB30++0xB
line.long 0x0 "DIICNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR3,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
rgroup.long 0x1C00BFF4++0x3
line.long 0x0 "DIIUUEVIR,DIIU Unit Engineering Version Id Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C00BFFC++0xB
line.long 0x0 "DIIUINFOR,DIIU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 20.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 16.--19. 1. "UST,Unit sub Type: specifies the Ncore unit native interface type"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type: specifies the Ncore unit type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "DIIUIDR,DIIU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the DIIU is implemented." "0,1"
newline
hexmask.long.byte 0x4 24.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x4 12.--23. 1. "NUnitId,Ncore 3 Unit identifier."
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this DIIU resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,DIIU Register Page Number (within its NRR)"
line.long 0x8 "DIIUFUIDR,DIIU Fabric Unit Identification Register"
hexmask.long.word 0x8 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x8 0.--15. 1. "FUnitId,Fabric Unit Identifier of the unit"
rgroup.long 0x1C00C040++0x3
line.long 0x0 "DIIUTAR,DIIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the DIIU." "0,1"
group.long 0x1C00C118++0x17
line.long 0x0 "DIIUUEDR,DIIU Uncorrectable Error Detect Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "DIIUUEIR,DIIU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "DIIUUESR,DIIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "DIIUUELR0,DIIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "DIIUUELR1,DIIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "DIIUUESAR,DIIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C00C900++0x3
line.long 0x0 "DIICCTRLR,DIIU Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
group.long 0x1C00CB00++0xB
line.long 0x0 "DIICNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR0,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00CB10++0xB
line.long 0x0 "DIICNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR1,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00CB20++0xB
line.long 0x0 "DIICNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR2,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00CB30++0xB
line.long 0x0 "DIICNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR3,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
rgroup.long 0x1C00CFF4++0x3
line.long 0x0 "DIIUUEVIR,DIIU Unit Engineering Version Id Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C00CFFC++0xB
line.long 0x0 "DIIUINFOR,DIIU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 20.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 16.--19. 1. "UST,Unit sub Type: specifies the Ncore unit native interface type"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type: specifies the Ncore unit type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "DIIUIDR,DIIU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the DIIU is implemented." "0,1"
newline
hexmask.long.byte 0x4 24.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x4 12.--23. 1. "NUnitId,Ncore 3 Unit identifier."
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this DIIU resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,DIIU Register Page Number (within its NRR)"
line.long 0x8 "DIIUFUIDR,DIIU Fabric Unit Identification Register"
hexmask.long.word 0x8 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x8 0.--15. 1. "FUnitId,Fabric Unit Identifier of the unit"
rgroup.long 0x1C00D040++0x3
line.long 0x0 "DIIUTAR,DIIU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the DIIU." "0,1"
group.long 0x1C00D118++0x17
line.long 0x0 "DIIUUEDR,DIIU Uncorrectable Error Detect Register"
hexmask.long 0x0 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "DIIUUEIR,DIIU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 2.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "DIIUUESR,DIIU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Uncorrectable Error Valid bit is set."
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "DIIUUELR0,DIIU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "DIIUUELR1,DIIU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "DIIUUESAR,DIIU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C00D900++0x3
line.long 0x0 "DIICCTRLR,DIIU Capture Control Register"
hexmask.long.word 0x0 20.--31. 1. "inc,Inc Value. Timestamp counter increment value: top 4 bits are integer and lower 8 bits are fractional. Ex: {4'b0001 8'b0000_0000}"
newline
hexmask.long.byte 0x0 16.--19. 1. "gain,Gain Value. 4 bit gain value for timestamp correction."
newline
hexmask.long.byte 0x0 8.--15. 1. "Rsvd,Reserved"
newline
bitfld.long 0x0 7. "dn0Rx,Dn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 6. "dn0Tx,Dn0 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 5. "ndn2Rx,Ndn2 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 4. "ndn2Tx,Ndn2 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 3. "ndn1Rx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 2. "ndn1Tx,Ndn1 SMI Tx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 1. "ndn0Rx,Ndn0 SMI Rx snoop and capture enable" "0,1"
newline
bitfld.long 0x0 0. "ndn0Tx,Ndn0 SMI Tx snoop and capture enable" "0,1"
group.long 0x1C00DB00++0xB
line.long 0x0 "DIICNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR0,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00DB10++0xB
line.long 0x0 "DIICNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR1,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00DB20++0xB
line.long 0x0 "DIICNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR2,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00DB30++0xB
line.long 0x0 "DIICNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DIICNTVR3,PMON Counter Value Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DIICNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
rgroup.long 0x1C00DFF4++0x3
line.long 0x0 "DIIUUEVIR,DIIU Unit Engineering Version Id Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C00DFFC++0xB
line.long 0x0 "DIIUINFOR,DIIU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 20.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 16.--19. 1. "UST,Unit sub Type: specifies the Ncore unit native interface type"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type: specifies the Ncore unit type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
line.long 0x4 "DVEUIDR,DVEU Identification Register"
bitfld.long 0x4 31. "Valid,Value of 1 validates this register. This bit is set to 1 if the DVEU is implemented." "0,1"
newline
hexmask.long.byte 0x4 24.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x4 12.--23. 1. "NUnitId,Ncore 3 Unit identifier."
newline
hexmask.long.byte 0x4 8.--11. 1. "NRRI,Identifier of the Ncore 3 Register Region in which this DVEU resides"
newline
hexmask.long.byte 0x4 0.--7. 1. "RPN,DVEU Register Page Number (within its NRR)"
line.long 0x8 "DVEUFUIDR,DVEU Fabric Unit Identification Register"
hexmask.long.word 0x8 16.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.word 0x8 0.--15. 1. "FUnitId,Fabric Unit Identifier of the unit"
rgroup.long 0x1C00E044++0x3
line.long 0x0 "DVEUTAR,DVEU Transaction Activity Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "TransActv,This bit is set when there is one or more active transactions inside the DVE." "0,1"
group.long 0x1C00E100++0x3
line.long 0x0 "DVECECR,DVE Correctable Error Control Register"
hexmask.long.tbyte 0x0 12.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 4.--11. 1. "ErrThreshold,This field determines the number of correctable errors that must be corrected before the Correctable Error Interrupt output signal is asserted."
newline
rbitfld.long 0x0 2.--3. "Rsvd1,Reserved" "0,1,2,3"
newline
bitfld.long 0x0 1. "ErrIntEn,If this bit is set  the Correctable Error Interrupt output signal is asserted when the number of correctable errors corrected equals the value in ErrThreshold field; otherwise  the correctable error interrupt signal is never asserted." "0,1"
newline
bitfld.long 0x0 0. "ErrDetEn,If this bit is set  then correctable error detection and logging is enabled; otherwise  correctable error detection and logging is disabled." "0,1"
group.long 0x1C00E108++0xF
line.long 0x0 "DVECESR,DVE Correctable Error Status Register"
hexmask.long.word 0x0 16.--31. 1. "ErrInfo,This field indicates additional information about logged error type  if the Correctable Error Valid bit is set."
newline
hexmask.long.byte 0x0 12.--15. 1. "ErrType,This field indicates the logged error type  if the Correctable Error Valid bit is set."
newline
rbitfld.long 0x0 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x0 2.--9. 1. "ErrCount,This field indicates the number of correctable errors detected by the unit. The field stops incrementing if the Correctable Error Count Overflow bit is set"
newline
rbitfld.long 0x0 1. "ErrCountOverflow,This bit indicates that the number of correctable errors detected by the unit overflowed the Correctable Error Count field" "0,1"
newline
eventfld.long 0x0 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Correctable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0x4 "DVECELR0,DVE Correctable Error Location Registers 0"
hexmask.long.byte 0x4 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0x4 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0x4 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x8 "DVECELR1,DVE Correctable Error Location Registers 1"
hexmask.long.word 0x8 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x8 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0xC "DVECESAR,DVE Correctable Error Status Alias Register"
hexmask.long.word 0xC 16.--31. 1. "ErrInfo,Alias bit for setting error info field of xCESR"
newline
hexmask.long.byte 0xC 12.--15. 1. "ErrType,Alias bit for setting error type field of xCESR"
newline
rbitfld.long 0xC 10.--11. "Rsvd1,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0xC 2.--9. 1. "ErrCount,Alias field for setting error Count field of xCESR"
newline
bitfld.long 0xC 1. "ErrCountOverflow,Alias bit for ssetting Error Count Overflow field of xCESR" "0,1"
newline
bitfld.long 0xC 0. "ErrVld,Alias bit for setting error valid field of xCESR" "0,1"
group.long 0x1C00E140++0x17
line.long 0x0 "DVEUUEDR,DVEU Uncorrectable Error Detect Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 4. "TimeoutErrDetEn,Timeout protection error detection enable: When set  timeout errors will be detected." "0,1"
newline
bitfld.long 0x0 3. "DecErrDetEn,Decode Error Enable. When set  this bit enables detection of address map uncorrectable error" "0,1"
newline
bitfld.long 0x0 2. "MemErrDetEn,Memory protection error detection enable: When set errors will be detected from any RAM memory arrays." "0,1"
newline
bitfld.long 0x0 1. "TransErrDetEn,Concerto Transport error detect enable: When set  errors will be detected from the Concerto Transport." "0,1"
newline
bitfld.long 0x0 0. "ProtErrDetEn,AXI downstream protocol error detect enable: When set  errors will be detected from the downstream AXI interface." "0,1"
line.long 0x4 "DVEUUEIR,DVEU Uncorrectable Error Interrupt Register"
hexmask.long 0x4 5.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x4 4. "TimeoutErrIntEn,Timeout uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 3. "DecErrIntEn,Decode Error Interrupt Enable. When set  this bit enables the assertion of address map Uncorrectable Error Interrupt signal." "0,1"
newline
bitfld.long 0x4 2. "MemErrIntEn,RAM memory uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 1. "TransErrIntEn,Concerto Transport uncorrectable error interrupt enable." "0,1"
newline
bitfld.long 0x4 0. "ProtErrIntEn,Downstream AXI uncorrectable error interrupt enable." "0,1"
line.long 0x8 "DVEUUESR,DVEU Uncorrectable Error Status Register"
hexmask.long.word 0x8 16.--31. 1. "ErrInfo,This field indicates additional information about logged error"
newline
hexmask.long.byte 0x8 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ErrType,This field indicates the logged error type  if the Uncorrectable Error Valid bit is set."
newline
rbitfld.long 0x8 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 0. "ErrVld,If this bit is set  Error information is logged in status and location registers. Writing a one to the Uncorrectable Error Valid bit clears the Correctable Error Valid bit." "0,1"
line.long 0xC "DVEUUELR0,DVEU Uncorrectable Error Location Registers 0"
hexmask.long.byte 0xC 26.--31. 1. "ErrWord,This field indicates the data word in which the logged error was detected"
newline
hexmask.long.byte 0xC 20.--25. 1. "ErrWay,This field indicates the way in which the logged error was detected"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "ErrEntry,This field indicates the entry or the set in which the logged error was detected"
line.long 0x10 "DVEUUELR1,DVEU Uncorrectable Error Location Registers 1"
hexmask.long.word 0x10 20.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "ErrAddr,This field contains the high-order address bits of the transaction that encountered the error"
line.long 0x14 "DVEUUESAR,DVEU Uncorrectable Error Status Alias Register"
hexmask.long.word 0x14 16.--31. 1. "ErrInfo,Alias bit for setting errro info field of xUESR"
newline
hexmask.long.byte 0x14 8.--15. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x14 4.--7. 1. "ErrType,Alias bit for setting error type field of xUESR"
newline
rbitfld.long 0x14 1.--3. "Rsvd1,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ErrVld,Alias bit for setting error valid filed of xUESR" "0,1"
group.long 0x1C00E180++0x3
line.long 0x0 "DVEUCRTR,DVEU Correctable Resiliency Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "ResThreshold,Threshold for the correctable error indication to the functional safety controller."
group.long 0x1C00E400++0x3
line.long 0x0 "DVEUSER0,DVEU Snoop Enable Register 0"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--4. 1. "SnpsEnb,Snoop Enable bits for DVM agents 0..31. If a bit is set for an agent  DVM-related snoop messages are enabled for that agent; otherwise  disabled."
group.long 0x1C00E900++0x3
line.long 0x0 "DVETASCR,Trace Accumulate and Control Register"
hexmask.long 0x0 5.--31. 1. "Rsvd1,Reserved"
newline
eventfld.long 0x0 4. "BufferRead,Write one to trigger a read" "0,1"
newline
eventfld.long 0x0 3. "BufferClear,Write 1 to clear the complete buffer" "0,1"
newline
bitfld.long 0x0 2. "BufferIsCircular,Enable circular buffer. 1: buffer drops older messages. 0: buffer drops newer messages." "0: buffer drops newer messages,1: buffer drops older messages"
newline
rbitfld.long 0x0 1. "BufferIsFull,Set when the buffer is full" "0,1"
newline
rbitfld.long 0x0 0. "BufferIsEmpty,Set when all entries in the buffer are read and the buffer is empty" "0,1"
rgroup.long 0x1C00E904++0x7
line.long 0x0 "DVETADHR,Trace Accumulate Data Header Register"
bitfld.long 0x0 31. "valid,Set when read data is valid  clears on read" "0,1"
newline
hexmask.long.tbyte 0x0 8.--30. 1. "Rsvd,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "fid,Funit ID of the trace capture Ncore unit"
line.long 0x4 "DVETADTSR,Trace Accumulate Data Time Stamp Register"
hexmask.long 0x4 0.--31. 1. "timestamp,Time stamp value from DVE free running counter"
rgroup.long 0x1C00E910++0x3F
line.long 0x0 "DVETAD0R,Trace Accumulate Data Register"
hexmask.long 0x0 0.--31. 1. "data,Capture data"
line.long 0x4 "DVETAD1R,Trace Accumulate Data Register"
hexmask.long 0x4 0.--31. 1. "data,Capture data"
line.long 0x8 "DVETAD2R,Trace Accumulate Data Register"
hexmask.long 0x8 0.--31. 1. "data,Capture data"
line.long 0xC "DVETAD3R,Trace Accumulate Data Register"
hexmask.long 0xC 0.--31. 1. "data,Capture data"
line.long 0x10 "DVETAD4R,Trace Accumulate Data Register"
hexmask.long 0x10 0.--31. 1. "data,Capture data"
line.long 0x14 "DVETAD5R,Trace Accumulate Data Register"
hexmask.long 0x14 0.--31. 1. "data,Capture data"
line.long 0x18 "DVETAD6R,Trace Accumulate Data Register"
hexmask.long 0x18 0.--31. 1. "data,Capture data"
line.long 0x1C "DVETAD7R,Trace Accumulate Data Register"
hexmask.long 0x1C 0.--31. 1. "data,Capture data"
line.long 0x20 "DVETAD8R,Trace Accumulate Data Register"
hexmask.long 0x20 0.--31. 1. "data,Capture data"
line.long 0x24 "DVETAD9R,Trace Accumulate Data Register"
hexmask.long 0x24 0.--31. 1. "data,Capture data"
line.long 0x28 "DVETAD10R,Trace Accumulate Data Register"
hexmask.long 0x28 0.--31. 1. "data,Capture data"
line.long 0x2C "DVETAD11R,Trace Accumulate Data Register"
hexmask.long 0x2C 0.--31. 1. "data,Capture data"
line.long 0x30 "DVETAD12R,Trace Accumulate Data Register"
hexmask.long 0x30 0.--31. 1. "data,Capture data"
line.long 0x34 "DVETAD13R,Trace Accumulate Data Register"
hexmask.long 0x34 0.--31. 1. "data,Capture data"
line.long 0x38 "DVETAD14R,Trace Accumulate Data Register"
hexmask.long 0x38 0.--31. 1. "data,Capture data"
line.long 0x3C "DVETAD15R,Trace Accumulate Data Register"
hexmask.long 0x3C 0.--31. 1. "data,Capture data"
group.long 0x1C00EB00++0xB
line.long 0x0 "DVECNTCR0,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DVECNTVR0,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DVECNTSR0,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00EB10++0xB
line.long 0x0 "DVECNTCR1,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DVECNTVR1,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DVECNTSR1,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00EB20++0xB
line.long 0x0 "DVECNTCR2,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DVECNTVR2,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DVECNTSR2,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00EB30++0xB
line.long 0x0 "DVECNTCR3,PMON Counter Control Register"
rbitfld.long 0x0 30.--31. "Rsvd1,Reserved bis 31:30" "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--29. 1. "CntEvtFirst,Select the first count event  0 not valid"
newline
rbitfld.long 0x0 22.--23. "Rsvd0,Reserved bis 23:22" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CntEvtSecond,Select the second count event  0 not valid"
newline
bitfld.long 0x0 13.--15. "MinStallPeriod,value is (2^ minstallperiod)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 10.--12. "FilterSel,LPF coefficients" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7.--9. "SSRCount,000: clear CNTSR  001: capture upper bits in CNTSR  010: use CNTSR as LPF  011: use CNTSR as max/saturation" "0: clear CNTSR,1: capture upper bits in CNTSR,?,?,?,?,?,?"
newline
bitfld.long 0x0 4.--6. "CounterCtl,Counter mode. 000: Normal  001: AND  010: XOR" "0: Normal,1: AND,?,?,?,?,?,?"
newline
rbitfld.long 0x0 3. "OverFlowStatus,Indicates overflow  sticky bit clears by clearing the counter" "0,1"
newline
bitfld.long 0x0 2. "InterruptEn,Enable rollover or overflow interrupt" "0,1"
newline
eventfld.long 0x0 1. "CountClr,Clear counter" "0,1"
newline
bitfld.long 0x0 0. "CountEn,Enable counting" "0,1"
line.long 0x4 "DVECNTVR3,PMON Counter Value Register Register"
hexmask.long 0x4 0.--31. 1. "CountVal,Counter value lower bits 31:0"
line.long 0x8 "DVECNTSR3,PMON Counter Saturation Register"
hexmask.long 0x8 0.--31. 1. "CountSatVal,Either upper counter value 63:32 or LPF bits"
group.long 0x1C00EFF0++0x3
line.long 0x0 "DVEUENGDBR,DVE Engineering Debug Register"
hexmask.long 0x0 1.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x0 0. "MaxOneSyncDVMOp,This bit when 0 restricts maximum outstanding Sync DVMOp to 3  when 1 restricts maximum outstanding Sync DVMOp to 1. Because 1 STT entry is always reserved for Non-Sync DVM Bypass  therefore this bit when 0 enables 3 + 1 = 4 STT entries .." "?,1: 2 STT entries"
rgroup.long 0x1C00EFF4++0x3
line.long 0x0 "DVEUENGIDR,DVEU Engineering ID Register"
hexmask.long 0x0 0.--31. 1. "EngVerId,Engineering Version Identifier"
rgroup.long 0x1C00EFFC++0x3
line.long 0x0 "DVEUINFOR,DVEU Information Register"
bitfld.long 0x0 31. "Valid,Implemented" "0,1"
newline
hexmask.long.word 0x0 16.--30. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 12.--15. 1. "UT,Unit Type"
newline
hexmask.long.word 0x0 0.--11. 1. "ImplVer,Implementation Version"
rgroup.long 0x1C0FFF00++0x3
line.long 0x0 "GRBUCSSFIDR0,GRBU Coherent Subsystem Snoop Filter Identification Register"
bitfld.long 0x0 29.--31. "Rsvd1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 26.--28. "filterType,Snoop Filter Type. This field indicates the type of snoop filter. The type of the snoop filter is given as follows (all other values are RESERVED): 0b000-Unimplemented filter  0b001-Null filter  0b010-Tag filter-presence vector  0b011-Tag.." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 20.--25. 1. "nWays,Number of Snoop Filter Ways. This field indicates the number of ways (i.e. the associativity) in the snoop filter minus one. For an unimplemented filter or a null filter  the value of this field is zero."
newline
hexmask.long.tbyte 0x0 0.--19. 1. "nSets,Number of Snoop Filter Sets. This field indicates the number of sets in the snoop filter minus one in each DIRU. To determine the total number of sets in the snoop filter  this value must be multiplied by the number of DIRUs. For an unimplemented.."
rgroup.long 0x1C0FFFF0++0xF
line.long 0x0 "GRBUNRRIR,GRBU NRR Identification Register"
hexmask.long.word 0x0 20.--31. 1. "Rsvd2,Reserved"
newline
hexmask.long.byte 0x0 16.--19. 1. "NRRUsed,Total number of NRRs used in this Ncore 3 instance is given by NRRUsed + 1 NRRs with indices 0 through NRRUsed are expected to be used in this instance."
newline
hexmask.long.word 0x0 4.--15. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0x0 0.--3. 1. "NRRI,Ncore Register Region Identifier of this Global Registers block."
line.long 0x4 "GRBUENGIDR,GRBU Engineering ID Register"
hexmask.long 0x4 0.--31. 1. "EngVerId,Engineering Version Identifier"
line.long 0x8 "GRBUNRRUCR,GRBU NRR Unit Census Register"
hexmask.long.byte 0x8 27.--31. 1. "Rsvd1,Reserved"
newline
bitfld.long 0x8 26. "nDVEs,Number of DVE units" "0,1"
newline
hexmask.long.byte 0x8 20.--25. 1. "nDPIs,Number of DII units"
newline
hexmask.long.byte 0x8 14.--19. 1. "nDMIs,Number of DMI units"
newline
hexmask.long.byte 0x8 8.--13. 1. "nDCEs,Number of DCE units"
newline
hexmask.long.byte 0x8 0.--7. 1. "nAIUs,Number of AIUs"
line.long 0xC "GRBUNSIDR,Ncore Subsystem Identification Register"
hexmask.long.byte 0xC 24.--31. 1. "Rsvd1,Reserved"
newline
hexmask.long.byte 0xC 16.--23. 1. "nSnoopFilters,Number of Snoop Filters. This field indicates the number of snoop filters in the coherent derived. The value of this field equals the number of snoop filters minus one."
newline
hexmask.long.byte 0xC 12.--15. 1. "CachelineOffset,Directory Cacheline Offset. This field indicates the width of the directory cache line offset. The number of bits in the directory cache line offset equals the value of this field + 5  e.g. for a 6-bit offset the value of this field.."
newline
hexmask.long.word 0xC 0.--11. 1. "RelVer,Release Version."
tree.end
tree "CLK_MGR (Clock Manager)"
base ad:0x10D10000
group.long 0x0++0x3
line.long 0x0 "ctrl,Contains fields that control the entire Clock Manager."
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 9. "swctrlbtclksel,This bit is only used if swctrlbtclken is set." "0,1"
newline
bitfld.long 0x0 8. "swctrlbtclken,If set  then Software will take control of the boot_clk mux select. If set  then swctrlbtclksel will determine the mux setting. If not set  the security features will determine the fuse settings." "0,1"
newline
hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "bootmode,When set the Clock Manager is in Boot Mode." "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "stat,Provides status for Clock Manager including PLL lock and HW Managed Clock State Machine busy."
hexmask.long.byte 0x0 26.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 25. "bootclksrc,If 1  the source of boot_clk is cb_intosc_hs_div2_clk. . If 0  the boot_clk source is the external oscillator (EOSC1)." "0,1"
newline
bitfld.long 0x0 24. "bootmode,If 1  the clocks are currently in Boot Mode. If 0  the clocks are not in Boot Mode." "0,1"
newline
hexmask.long.byte 0x0 18.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 17. "perf_trans,HP PLL disconnect state transition status. This status is delegated for power state transition between PD and Disconnect for Peripheral PLL." "0,1"
newline
bitfld.long 0x0 16. "perplllocked,PLL lock status which indicates if the HP PLL IP is locked to incoming reference clock within the PPM threshold programmed in the memory registers." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 9. "main_trans,HP PLL disconnect state transition status. This status is delegated for power state transition between PD and Disconnect for Main PLL." "0,1"
newline
bitfld.long 0x0 8. "mainplllocked,PLL lock status which indicates if the HP PLL IP is locked to incoming reference clock within the PPM threshold programmed in the memory registers." "0,1"
newline
hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "busy,This read only bit indicates that the Hardware Managed clock's state machine is active. If the state machine is active  then the clocks are in transition. Software should poll this bit after changing the source of internal clocks when changing.." "0,1"
group.long 0x8++0xB
line.long 0x0 "testioctrl,Contains fields setting the IO output select for Test Clock and Debug outputs."
hexmask.long.word 0x0 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 16. "debugclksel,Selects the source of PLL_lock for debug purpose." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8.--9. "periclksel,Selects between Channel 0  Channel 1  Channel2 and Channel 3 of the peripheral PLL." "0: periph PLL C0,1: periph PLL C1,2: periph PLL C2,3: periph PLL C3"
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--1. "mainclksel,Selects between Channel 0  Channel 1  Channel 2 and Channel 3 of the main PLL." "0: main PLL C0,1: main PLL C1,2: main PLL C2,3: main PLL C3"
line.long 0x4 "intrgen,Global Interrupt Enable"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "en" "0,1"
line.long 0x8 "intrmsk,Interrupt Mask"
hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 3. "perlocklost,To mask lock lost interrupt from periph PLL" "0,1"
newline
bitfld.long 0x8 2. "mainlocklost,To mask lock lost interrupt from main PLL" "0,1"
newline
bitfld.long 0x8 1. "perlockachieved,To mask lock achieved interrupt from periph PLL" "0,1"
newline
bitfld.long 0x8 0. "mainlockachieved,To mask lock achieved interrupt from main PLL" "0,1"
wgroup.long 0x14++0x3
line.long 0x0 "intrclr,Interrupt Clear."
hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 3. "perlocklost,This is used to clear sticky periph PLL lock lost signal." "0,1"
newline
eventfld.long 0x0 2. "mainlocklost,This is used to clear sticky main PLL lock lost signal." "0,1"
newline
eventfld.long 0x0 1. "perlockachieved,This is used to clear sticky periph PLL lock achieved signal." "0,1"
newline
eventfld.long 0x0 0. "mainlockachieved,This is used to clear sticky main PLL lock achieved signal." "0,1"
rgroup.long 0x18++0xB
line.long 0x0 "intrsts,Interrupt Pending Status after the interrupt masks."
hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 3. "perlocklost,Pending status for periph PLL lock lost interrupt after intr mask" "0,1"
newline
bitfld.long 0x0 2. "mainlocklost,Pending status for main PLL lock lost interrupt after intr mask" "0,1"
newline
bitfld.long 0x0 1. "perlockachieved,Pending status for periph PLL lock achieved interrupt after intr mask" "0,1"
newline
bitfld.long 0x0 0. "mainlockachieved,Pending status for main PLL lock achieved interrupt after intr mask" "0,1"
line.long 0x4 "intrstk,Interrupt Pending Status without considering the interrupt masks."
hexmask.long 0x4 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 3. "perlocklost,Pending status for periph PLL lock lost interrupt before intr mask" "0,1"
newline
bitfld.long 0x4 2. "mainlocklost,Pending status for main PLL lock lost interrupt before intr mask" "0,1"
newline
bitfld.long 0x4 1. "perlockachieved,Pending status for periph PLL lock achieved interrupt before intr mask" "0,1"
newline
bitfld.long 0x4 0. "mainlockachieved,Pending status for main PLL lock achieved interrupt before intr mask" "0,1"
line.long 0x8 "intrraw,Realtime Status of the bits which could have caused interrupt."
hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 3. "perlocklost,Raw signal (before masking) for periph PLL lock lost. It comed from clock manager" "0,1"
newline
bitfld.long 0x8 2. "mainlocklost,Raw signal (before masking) for main PLL lock lost. It comed from clock manager" "0,1"
newline
bitfld.long 0x8 1. "perlockachieved,Raw signal (before masking) for periph PLL lock achieved. It comed from clock manager" "0,1"
newline
bitfld.long 0x8 0. "mainlockachieved,Raw signal (before masking) for main PLL lock achieved. It comed from clock manager" "0,1"
group.long 0x24++0x17
line.long 0x0 "en,Contains fields that control clock enables for Main Clocks."
hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 11. "core3en,Enable for Core 3 Clock" "0,1"
newline
bitfld.long 0x0 10. "core2en,Enable for Core 2 Clock" "0,1"
newline
bitfld.long 0x0 9. "core1en,Enable for Core 1 Clock" "0,1"
newline
bitfld.long 0x0 8. "core0en,Enable for Core 0 Clock" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 6. "s2fuser0clken,Enables clock s2f_user0_clk output" "0,1"
newline
rbitfld.long 0x0 5. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 4. "csclken,Enables Debug Clock outputs (cs_at_clk  cs_pdbg_clk  and cs_trace_clk)" "0,1"
newline
bitfld.long 0x0 3. "l4spclken,Enables clock l4_sp_clk output" "0,1"
newline
bitfld.long 0x0 2. "l4mpclken,Enables clock l4_mp_clk output" "0,1"
newline
bitfld.long 0x0 1. "l4mainclken,Enables clock l4_main_clk output" "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
line.long 0x4 "ens,Write One to Set correspondng fields in the Enable Register."
hexmask.long.tbyte 0x4 12.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 11. "core3en,core 3 clock enable" "0,1"
newline
bitfld.long 0x4 10. "core2en,Core 2 Clock enable" "0,1"
newline
bitfld.long 0x4 9. "core1en,Core 1 clock enable" "0,1"
newline
bitfld.long 0x4 8. "core0en,Core 0 clock enable" "0,1"
newline
rbitfld.long 0x4 7. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x4 6. "s2fuser0clken,Enables clock s2f_user0_clk output" "0,1"
newline
rbitfld.long 0x4 5. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x4 4. "csclken,Enables Debug Clock outputs (cs_at_clk  cs_pdbg_clk and cs_trace_clk)" "0,1"
newline
bitfld.long 0x4 3. "l4spclken,Enables clock l4_sp_clk output" "0,1"
newline
bitfld.long 0x4 2. "l4mpclken,Enables clock l4_mp_clk output" "0,1"
newline
bitfld.long 0x4 1. "l4mainclken,Enables clock l4_main_clk output" "0,1"
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
line.long 0x8 "enr,Write One to Clear corresponding fields in Enable Register."
hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
newline
eventfld.long 0x8 11. "core3en,core 3 clock enable" "0,1"
newline
eventfld.long 0x8 10. "core2en,core 2 clock enable" "0,1"
newline
eventfld.long 0x8 9. "core1en,core 1 clock enable" "0,1"
newline
eventfld.long 0x8 8. "core0en,core 0 clock enable" "0,1"
newline
rbitfld.long 0x8 7. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x8 6. "s2fuser0clken,Enables clock s2f_user0_clk output" "0,1"
newline
rbitfld.long 0x8 5. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x8 4. "csclken,Enables Debug Clock outputs (cs_at_clk  cs_pdbg_clk and cs_trace_clk)" "0,1"
newline
eventfld.long 0x8 3. "l4spclken,Enables clock l4_sp_clk output" "0,1"
newline
eventfld.long 0x8 2. "l4mpclken,Enables clock l4_mp_clk output" "0,1"
newline
eventfld.long 0x8 1. "l4mainclken,Enables clock l4_main_clk output" "0,1"
newline
rbitfld.long 0x8 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
line.long 0xC "bypass,Contains fields that control bypass for clocks derived from the Main PLL."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 7. "core3,If set  the Core 3 clock will be bypassed to the boot_clk." "0,1"
newline
bitfld.long 0xC 6. "core2,If set  the core2 clock will be bypassed to the boot_clk." "0,1"
newline
bitfld.long 0xC 5. "core01,If set  the Core 01 clock group will be bypassed to the boot_clk." "0,1"
newline
bitfld.long 0xC 4. "dsu,If set  the DSU clock will be bypassed to the boot_clk." "0,1"
newline
rbitfld.long 0xC 3. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xC 2. "s2fuser0,If set  the s2f_user0_clk will be bypassed to the boot_clk." "0,1"
newline
bitfld.long 0xC 1. "noc,If set  the NOC clock group will be bypassed to boot_clk." "0,1"
newline
rbitfld.long 0xC 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
line.long 0x10 "bypasss,Write One to Set corresponding fields in Bypass Register."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 7. "core3,If set  the core3 clock will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
bitfld.long 0x10 6. "core2,If set  the core2 clock will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
bitfld.long 0x10 5. "core01,If set  the core01 clock will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
bitfld.long 0x10 4. "dsu,If set  the DSU clock will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
rbitfld.long 0x10 3. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x10 2. "s2fuser0,If set  the s2f_user0_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
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bitfld.long 0x10 1. "noc,If set  the NOC clock group will be bypassed to the input clock reference of the Main PLL." "0,1"
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rbitfld.long 0x10 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
line.long 0x14 "bypassr,Write One to Clear corresponding fields in Bypass Register."
hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
eventfld.long 0x14 7. "core3,If set  the core3 clock will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
eventfld.long 0x14 6. "core2,If set  the core2 clock will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
eventfld.long 0x14 5. "core01,If set  the core01 clock will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
eventfld.long 0x14 4. "dsu,If set  the DSU clock will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
rbitfld.long 0x14 3. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x14 2. "s2fuser0,If set  the s2f_user0_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
eventfld.long 0x14 1. "noc,If set  the NOC clock group will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
rbitfld.long 0x14 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
group.long 0x40++0x13
line.long 0x0 "nocclk,Contains settings that control noc_free_clk generated from the Peripheral PLL."
hexmask.long.word 0x0 19.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.word 0x0 0.--15. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x4 "nocdiv,Contains fields that control clock dividers for NoC Clocks."
rbitfld.long 0x4 30.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x4 28.--29. "cspdbgclk,The external cs_pdbg_clk divider is specified in this field." "0,1,2,3"
newline
bitfld.long 0x4 26.--27. "cstraceclk,The external cs_trace_clk divider is specified in this field. The cs_trace_clk is used by the actual trace interface to the debugger." "0,1,2,3"
newline
bitfld.long 0x4 24.--25. "csclk,The external cs_at_clk divider is specified in this field." "0,1,2,3"
newline
rbitfld.long 0x4 22.--23. "Reserved_6,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x4 20.--21. "mpuperiphdiv,The external OCRAM and GIC-600 divider is specified in this field." "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "ccudiv,The external ccu clk divider is specified in this field." "0,1,2,3"
newline
bitfld.long 0x4 16.--17. "softphydiv,The external soft PHY divider is specified in this field." "0,1,2,3"
newline
hexmask.long.byte 0x4 8.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 6.--7. "l4spclk,The external l4_sp_clk divider is specified in this field." "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "l4mpclk,The external l4_mp_clk divider is specified in this field." "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "l4sysfreeclk,The external l4sysfreeclk divider is specified in this field." "0,1,2,3"
newline
rbitfld.long 0x4 0.--1. "Reserved_0,Reserved bitfield added by Magillem" "0,1,2,3"
line.long 0x8 "pllglob,This refects register settings for all the channels of the main PLL"
rbitfld.long 0x8 30.--31. "Reserved_12,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x8 29. "clr_lostlock_bypass,if lostlock_bypass_en is set and the PLL loses lock  channel bypass signal is asserted by HW." "0: no effect on PLL lostlock bypass mode,1: Clear PLL's lostlock bypass mode"
newline
bitfld.long 0x8 28. "lostlock_bypass_en,When PLL loses lock  the PLL output clocks are muted. Clock manager will not have any clock to recover or even process lostlock interrupt. This bit when set will enable the main PLL to give keepalive clock at the output upon loosing lock" "0: Turns OFF bypass to keepalive clock feature upon..,1: Turns on bypass to keepalive clock feature upon.."
newline
hexmask.long.byte 0x8 24.--27. 1. "modclkdiv,Reference clock divider control; the decimal value of this register will be the divider settings. Setting 0 will"
newline
rbitfld.long 0x8 22.--23. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x8 21. "fastrefclk,HP PLL fast reference clock mode control." "0,1"
newline
bitfld.long 0x8 20. "disctrl,Disconnect clock disable control. It is used to glitchlessly disable all keepalive clock in disconnect state." "0,1"
newline
bitfld.long 0x8 19. "clksync,Clock slice output synchronization request control. Once asserted  the positive edge of all enabled clock slices will be aligned." "0,1"
newline
bitfld.long 0x8 18. "pwrgatectrl,HP PLL Internal Power-gated State Control" "0,1"
newline
bitfld.long 0x8 16.--17. "psrc,Controls the VCO input clock source." "0,1,2,3"
newline
rbitfld.long 0x8 14.--15. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x8 12.--13. "drefclkdiv,Reference clock divider control used by the DPLL. The effective divider value is 2^(ictl_pll_drefdiv_nt_[1:0])." "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--11. 1. "arefclkdiv,Reference clock divider control; the decimal value of this register will be the divider settings. Setting 0 will"
newline
hexmask.long.byte 0x8 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
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bitfld.long 0x8 1. "rst_n,Power-On Reset. Used to initialize memory and reset the Power Management Unit (PMU). The minimum POR assertion time required is 0.5 &micro;s." "0,1"
newline
bitfld.long 0x8 0. "pd_n,Keepalive clock power down control" "0,1"
line.long 0xC "fdbck,VCO freq register counters"
hexmask.long.byte 0xC 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.tbyte 0xC 0.--23. 1. "fdiv,Fractional synthesizer center frequency control word."
line.long 0x10 "mem,Registers dealing with PLL internal memory access."
hexmask.long.byte 0x10 27.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x10 26. "err,Memory Error Status Signal." "0,1"
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bitfld.long 0x10 25. "wr,Memory Read/Write Operation." "0,1"
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bitfld.long 0x10 24. "req,Memory Request Signal" "0,1"
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hexmask.long.byte 0x10 16.--23. 1. "wdat,Memory 'Write' Data bus."
newline
hexmask.long.word 0x10 0.--15. 1. "addr,PLL Memory Address"
rgroup.long 0x54++0x3
line.long 0x0 "memstat,Main PLL memstatus register. contains memory read data"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--7. 1. "rdata,Memory Read Data Bus"
group.long 0x58++0x4F
line.long 0x0 "vcocalib,VCO calibration control registers."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 27. "clr,HP PLL calibration clear control." "0,1"
newline
bitfld.long 0x0 25.--26. "banksel,Controls the calibration bank that will be used to store  restore or clear HP PLL calibration code." "0,1,2,3"
newline
rbitfld.long 0x0 24. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "mscnt,ictl_pll_calvcomeascount_nt_[7:0] = 100/(Fvco/Fref_ effective_digital)"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--9. 1. "hscnt,VCO calibration parameter:"
line.long 0x4 "pllc0,Channel C0 frequency settings for the main PLL"
rbitfld.long 0x4 30.--31. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
newline
rbitfld.long 0x4 29. "stat,HP PLL state transition status for clk_slice_0." "0,1"
newline
bitfld.long 0x4 28. "mute,Mutes PLL clock_slice_0 outputs without any glitch:" "0,1"
newline
bitfld.long 0x4 27. "en,PLL channel 0 output enable;" "0,1"
newline
bitfld.long 0x4 26. "bypas,PLL channel 0 output bypass. Before lock  it is muted  regardless of its value." "0,1"
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hexmask.long.word 0x4 11.--25. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--10. 1. "div,The ock_pll_clkslice_0 divider ratio in binary code."
line.long 0x8 "pllc1,Channel C1 frequency settings for the main PLL"
rbitfld.long 0x8 30.--31. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
newline
rbitfld.long 0x8 29. "stat,HP PLL state transition status for clk_slice_1." "0,1"
newline
bitfld.long 0x8 28. "mute,Mutes PLL clock_slice_1 outputs without any glitch:" "0,1"
newline
bitfld.long 0x8 27. "en,PLL channel 1 output enable;" "0,1"
newline
bitfld.long 0x8 26. "bypas,PLL channel 1 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x8 11.--25. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x8 0.--10. 1. "div,The ock_pll_clkslice_1 divider ratio in binary code."
line.long 0xC "pllc2,Channel C2 frequency settings for the main PLL"
rbitfld.long 0xC 30.--31. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
newline
rbitfld.long 0xC 29. "stat,HP PLL state transition status for clk_slice_2." "0,1"
newline
bitfld.long 0xC 28. "mute,Mutes PLL clock_slice_2 outputs without any glitch:" "0,1"
newline
bitfld.long 0xC 27. "en,PLL channel 2 output enable;" "0,1"
newline
bitfld.long 0xC 26. "bypas,PLL channel 2 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0xC 11.--25. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0xC 0.--10. 1. "div,The ock_pll_clkslice_2 divider ratio in binary code."
line.long 0x10 "pllc3,Channel C3 frequency settings for the main PLL"
rbitfld.long 0x10 30.--31. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
newline
rbitfld.long 0x10 29. "stat,HP PLL state transition status for clk_slice_3." "0,1"
newline
bitfld.long 0x10 28. "mute,Mutes PLL clock_slice_3 outputs without any glitch:" "0,1"
newline
bitfld.long 0x10 27. "en,PLL channel 3 output enable;" "0,1"
newline
bitfld.long 0x10 26. "bypas,PLL channel 3 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x10 11.--25. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x10 0.--10. 1. "div,The ock_pll_clkslice_3 divider ratio in binary code."
line.long 0x14 "pllm,Feedback Clock Divider Control (VCO Frequency Register Counters)"
hexmask.long.tbyte 0x14 10.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x14 0.--9. 1. "mdiv,Feedback clock divider. The HP PLL IP will initial operate at the frequency based on the Mdiv and Fdiv values set at PD state. It can be only set while the HP PLL IP is at Reset or PD state."
line.long 0x18 "fhop,Frequency Hopping (FHOP)/Dynamic Frequency Scaling(DFS) Control and status register."
hexmask.long.word 0x18 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x18 16. "ack,Asynchronous output. Acknowledge signal for the frequency ramp." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 8. "req,Request the HP PLL IP to perform the configured FHOP." "0,1"
newline
hexmask.long.byte 0x18 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0.--1. "dir,One-hot encoded." "0,1,2,3"
line.long 0x1C "ssc,Spread Spectrum Clocking (SSC) Control and Status Registers."
hexmask.long.tbyte 0x1C 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x1C 8. "stat,Indicates whether SSC is running." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 0. "en,Enables/Disables SSC." "0,1"
line.long 0x20 "lostlock,To enable the keep alive clock to appear on the clock slice outputs when PLL lock is lost. By default. the clock slices are muted (bit = 0)."
hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x20 0. "bypass_cleared,When all the bypass_en asserted due to loss of PLL lock from all the channels go low this bit gets set to 1." "0,1"
line.long 0x24 "en,Contains fields that control clock enables for clocks derived from the Peripheral PLL."
hexmask.long.byte 0x24 28.--31. 1. "Reserved_28,Reserved bitfield added by Magillem"
newline
bitfld.long 0x24 27. "i2c_emac2_clken,Enables i2c_emac2 peripheral clock. This enable goes outside of the Clock Manger to the i2c_emac2 directly." "0,1"
newline
bitfld.long 0x24 26. "softphyclken,Enables softphy peripheral clock. This enable goes outside of the Clock Manger to the softphy directly." "0,1"
newline
bitfld.long 0x24 25. "usb31clken,Enables usb31 peripheral clock. This enable goes outside of the Clock Manger to the usb31 directly." "0,1"
newline
bitfld.long 0x24 24. "sptimer_1_clken,Enables sptimer_1 peripheral clock. This enable goes outside of the Clock Manger to the sptimer_1 directly." "0,1"
newline
bitfld.long 0x24 23. "sptimer_0_clken,Enables sptimer_0 peripheral clock. This enable goes outside of the Clock Manger to the sptimer_0 directly." "0,1"
newline
bitfld.long 0x24 22. "i2c_emac1_clken,Enables i2c_emac1 peripheral clock. This enable goes outside of the Clock Manger to the i2c_emac1 directly." "0,1"
newline
bitfld.long 0x24 21. "uart_1_clken,Enables uart_1 peripheral clock. This enable goes outside of the Clock Manger to the uart_1 directly." "0,1"
newline
bitfld.long 0x24 20. "uart_0_clken,Enables uart_0 peripheral clock. This enable goes outside of the Clock Manger to the uart_0 directly." "0,1"
newline
bitfld.long 0x24 19. "i3c_1_clken,Enables i3c_1 peripheral clock. This enable goes outside of the Clock Manger to the i3c_1 directly." "0,1"
newline
bitfld.long 0x24 18. "i3c_0_clken,Enables i3c_0 peripheral clock. This enable goes outside of the Clock Manger to the i3c_0 directly." "0,1"
newline
bitfld.long 0x24 17. "i2c_emac0_clken,Enables i2c_emac0 peripheral clock. This enable goes outside of the Clock Manger to the i2c_emac0 directly." "0,1"
newline
bitfld.long 0x24 16. "i2c_1_clken,Enables i2c_1 peripheral clock. This enable goes outside of the Clock Manger to the i2c_1 directly." "0,1"
newline
bitfld.long 0x24 15. "i2c_0_clken,Enables i2c_0 peripheral clock. This enable goes outside of the Clock Manger to the I2C0 directly." "0,1"
newline
bitfld.long 0x24 14. "dmaclken,Enables DMA peripheral clock. This enable goes outside of the Clock Manger to the DMA directly." "0,1"
newline
bitfld.long 0x24 13. "spis_1_clken,Enables SPIS1 peripheral clock. This enable goes outside of the Clock Manger to the SPIS1 directly." "0,1"
newline
bitfld.long 0x24 12. "spis_0_clken,Enables SPIS0 peripheral clock. This enable goes outside of the Clock Manger to the SPIS0 directly." "0,1"
newline
bitfld.long 0x24 11. "spim_1_clken,Enables SPIM1peripheral clock. This enable goes outside of the Clock Manger to the SPIM1 directly." "0,1"
newline
bitfld.long 0x24 10. "nandclken,Enables NAND peripheral clock. This enable goes outside of the Clock Manger to the NAND directly." "0,1"
newline
bitfld.long 0x24 9. "spim_0_clken,Enables SPIM0 Master peripheral clock. This enable goes outside of the Clock Manger to the SPIM0 directly." "0,1"
newline
bitfld.long 0x24 8. "usb2clken,Enables USB2-OTG peripheral clock. This enable goes outside of the Clock Manger to the USB2-OTG directly." "0,1"
newline
bitfld.long 0x24 7. "psiclken,Enables psi_ref clock." "0,1"
newline
bitfld.long 0x24 6. "s2fuser1clken,Enables clock s2f_user1_clk output" "0,1"
newline
bitfld.long 0x24 5. "sdmmcclken,Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger to the SDMMC directly." "0,1"
newline
bitfld.long 0x24 4. "gpiodben,Enables clock gpio_db_clk output" "0,1"
newline
bitfld.long 0x24 3. "emacptpen,Enables clock emac_ptp_clk output" "0,1"
newline
bitfld.long 0x24 2. "emac2en,Enables clock emac2_clk output" "0,1"
newline
bitfld.long 0x24 1. "emac1en,Enables clock emac1_clk output" "0,1"
newline
bitfld.long 0x24 0. "emac0en,Enables clock emac0_clk output" "0,1"
line.long 0x28 "ens,Write One to Set corresponding fields in Enable Register."
hexmask.long.byte 0x28 28.--31. 1. "Reserved_28,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 27. "i2c_emac2_clken,Enables i2c_emac2 peripheral clock. This enable goes outside of the Clock Manger to the i2c_emac2 directly." "0,1"
newline
bitfld.long 0x28 26. "softphyclken,Enables softphy peripheral clock. This enable goes outside of the Clock Manger to the softphy directly." "0,1"
newline
bitfld.long 0x28 25. "usb31clken,Enables USB31 peripheral clock. This enable goes outside of the Clock Manger to the USB31 directly." "0,1"
newline
bitfld.long 0x28 24. "sptimer_1_clken,Enables SPTIMER-1 peripheral clock. This enable goes outside of the Clock Manger to the SPTIMER-1 directly." "0,1"
newline
bitfld.long 0x28 23. "sptimer_0_clken,Enables SPTIMER-0 peripheral clock. This enable goes outside of the Clock Manger to the SPTIMER-0 directly." "0,1"
newline
bitfld.long 0x28 22. "i2c_emac1_clken,Enables i2c_emac1 peripheral clock. This enable goes outside of the Clock Manger to the i2c_emac1 directly." "0,1"
newline
bitfld.long 0x28 21. "uart_1_clken,Enables uart_1 peripheral clock. This enable goes outside of the Clock Manger to the uart1 directly." "0,1"
newline
bitfld.long 0x28 20. "uart_0_clken,Enables uart0 peripheral clock. This enable goes outside of the Clock Manger to the uart0 directly." "0,1"
newline
bitfld.long 0x28 19. "i3c_1_clken,Enables i3c-1 peripheral clock. This enable goes outside of the Clock Manger to the i3c-1 directly." "0,1"
newline
bitfld.long 0x28 18. "i3c_0_clken,Enables i3c-0 peripheral clock. This enable goes outside of the Clock Manger to the i3c-0 directly." "0,1"
newline
bitfld.long 0x28 17. "i2c_emac0_clken,Enables I2C-EMAC0 peripheral clock. This enable goes outside of the Clock Manger to the I2C-EMAC0 directly." "0,1"
newline
bitfld.long 0x28 16. "i2c_1_clken,Enables I2C-1 peripheral clock. This enable goes outside of the Clock Manger to the I2C-1 directly." "0,1"
newline
bitfld.long 0x28 15. "i2c_0_clken,Enables I2C-0 peripheral clock. This enable goes outside of the Clock Manger to the I2C-0 directly." "0,1"
newline
bitfld.long 0x28 14. "dmaclken,Enables DMA peripheral clock. This enable goes outside of the Clock Manger to the DMA directly." "0,1"
newline
bitfld.long 0x28 13. "spis_1_clken,Enables SPIS1 peripheral clock. This enable goes outside of the Clock Manger to the SPIS1 directly." "0,1"
newline
bitfld.long 0x28 12. "spis_0_clken,Enables SPIS0 peripheral clock. This enable goes outside of the Clock Manger to the SPIS0 directly." "0,1"
newline
bitfld.long 0x28 11. "spim_1_clken,Enables SPIM peripheral clock. This enable goes outside of the Clock Manger to the SPIM 1 irectly." "0,1"
newline
bitfld.long 0x28 10. "nandclken,Enables NAND peripheral clock. This enable goes outside of the Clock Manger to the NAND directly." "0,1"
newline
bitfld.long 0x28 9. "spim_0_clken,Enables SPI Master 0 peripheral clock. This enable goes outside of the Clock Manger to the SPIM-0 directly." "0,1"
newline
bitfld.long 0x28 8. "usb2clken,Enables USB2-OTG peripheral clock. This enable goes outside of the Clock Manger to the USB2-OTG directly." "0,1"
newline
bitfld.long 0x28 7. "psiclken,Enables psi_ref clock." "0,1"
newline
bitfld.long 0x28 6. "s2fuser1clken,Enables clock s2f_user1_clk output" "0,1"
newline
bitfld.long 0x28 5. "sdmmcclken,Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger to the SDMMC directly." "0,1"
newline
bitfld.long 0x28 4. "gpiodben,Enables clock gpio_db_clk output" "0,1"
newline
bitfld.long 0x28 3. "emacptpen,Enables clock emac_ptp_clk output" "0,1"
newline
bitfld.long 0x28 2. "emac2en,Enables clock emac2_clk output" "0,1"
newline
bitfld.long 0x28 1. "emac1en,Enables clock emac1_clk output" "0,1"
newline
bitfld.long 0x28 0. "emac0en,Enables clock emac0_clk output" "0,1"
line.long 0x2C "enr,Write One to Clear corresponding fields in Enable Register."
hexmask.long.byte 0x2C 28.--31. 1. "Reserved_28,Reserved bitfield added by Magillem"
newline
eventfld.long 0x2C 27. "i2c_emac2_clken,Enables I2c_EMAC2 peripheral clock. This enable goes outside of the Clock Manger to the I2C_EMAC2 directly." "0,1"
newline
eventfld.long 0x2C 26. "softphyclken,Enables softphy peripheral clock. This enable goes outside of the Clock Manger to the sofyphy directly." "0,1"
newline
eventfld.long 0x2C 25. "usb31clken,Enables USB31 peripheral clock. This enable goes outside of the Clock Manger to the USB31 directly." "0,1"
newline
eventfld.long 0x2C 24. "sptimer_1_clken,Enables SPTIMER_1 peripheral clock. This enable goes outside of the Clock Manger to the SPTIMER_1 directly." "0,1"
newline
eventfld.long 0x2C 23. "sptimer_0_clken,Enables SPTIMER_0 peripheral clock. This enable goes outside of the Clock Manger to the SPTIMER_0 directly." "0,1"
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eventfld.long 0x2C 22. "i2c_emac1_clken,Enables I2c_EMAC1 peripheral clock. This enable goes outside of the Clock Manger to the I2C_EMAC1 directly." "0,1"
newline
eventfld.long 0x2C 21. "uart_1_clken,Enables UART_1 peripheral clock. This enable goes outside of the Clock Manger to the UART_1 directly." "0,1"
newline
eventfld.long 0x2C 20. "uart_0_clken,Enables UART_0 peripheral clock. This enable goes outside of the Clock Manger to the UART_0 directly." "0,1"
newline
eventfld.long 0x2C 19. "i3c_1_clken,Enables I3C_1 peripheral clock. This enable goes outside of the Clock Manger to the I3C_1 directly." "0,1"
newline
eventfld.long 0x2C 18. "i3c_0_clken,Enables i3C_0 peripheral clock. This enable goes outside of the Clock Manger to the I3C_0 directly." "0,1"
newline
eventfld.long 0x2C 17. "i2c_emac0_clken,Enables I2C_EMAC0 peripheral clock. This enable goes outside of the Clock Manger to the I2C_EMAC0 directly." "0,1"
newline
eventfld.long 0x2C 16. "i2c_1_clken,Enables I2C-1 peripheral clock. This enable goes outside of the Clock Manger to the I2C-1 directly." "0,1"
newline
eventfld.long 0x2C 15. "i2c_0_clken,Enables I2C-0 peripheral clock. This enable goes outside of the Clock Manger to the I2C-0 directly." "0,1"
newline
eventfld.long 0x2C 14. "dmaclken,Enables DMA peripheral clock. This enable goes outside of the Clock Manger to the DMA directly." "0,1"
newline
eventfld.long 0x2C 13. "spis_1_clken,Enables SPIS-1 peripheral clock. This enable goes outside of the Clock Manger to the SPIS-1 directly." "0,1"
newline
eventfld.long 0x2C 12. "spis_0_clken,Enables SPIS-0 peripheral clock. This enable goes outside of the Clock Manger to the SPIS-0 directly." "0,1"
newline
eventfld.long 0x2C 11. "spim_1_clken,Enables SPIM1 peripheral clock. This enable goes outside of the Clock Manger to the SPIM1 directly." "0,1"
newline
eventfld.long 0x2C 10. "nandclken,Enables NAND peripheral clock. This enable goes outside of the Clock Manger to the NAND directly." "0,1"
newline
eventfld.long 0x2C 9. "spim_0_clken,Enables SPI Master peripheral clock. This enable goes outside of the Clock Manger to the SPIM0 directly." "0,1"
newline
eventfld.long 0x2C 8. "usb2clken,Enables USB-2 peripheral clock. This enable goes outside of the Clock Manger to the USB-2 directly." "0,1"
newline
eventfld.long 0x2C 7. "psiclken,Enables psi_ref clock." "0,1"
newline
eventfld.long 0x2C 6. "s2fuser1clken,Enables clock s2f_user1_clk output" "0,1"
newline
eventfld.long 0x2C 5. "sdmmcclken,Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger to the SDMMC directly." "0,1"
newline
eventfld.long 0x2C 4. "gpiodben,Enables clock gpio_db_clk output" "0,1"
newline
eventfld.long 0x2C 3. "emacptpen,Enables clock emac_ptp_clk output" "0,1"
newline
eventfld.long 0x2C 2. "emac2en,Enables clock emac2_clk output" "0,1"
newline
eventfld.long 0x2C 1. "emac1en,Enables clock emac1_clk output" "0,1"
newline
eventfld.long 0x2C 0. "emac0en,Enables clock emac0_clk output" "0,1"
line.long 0x30 "bypass,Contains fields that control bypass for clocks derived from the Peripheral PLL."
hexmask.long.tbyte 0x30 8.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x30 7. "usb31,If set  the USB31 clock will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x30 6. "psiref,If set  the psi_ref_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x30 5. "s2fuser1,If set  the s2f_user1_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
rbitfld.long 0x30 4. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x30 3. "gpiodb,If set  the gpio_db_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x30 2. "emacptp,If set  the emac_ptp_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x30 1. "emacb,If set  the emacb_free_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
bitfld.long 0x30 0. "emaca,If set  the emaca_free_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
line.long 0x34 "bypasss,Write One to Set corresponding fields in Bypass Register."
hexmask.long.tbyte 0x34 8.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x34 7. "usb31,If set  the USB31 clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x34 6. "psiref,If set  the psi_ref_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x34 5. "s2fuser1,If set  the s2f_user1_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
rbitfld.long 0x34 4. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x34 3. "gpiodb,If set  the gpio_db_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x34 2. "emacptp,If set  the emac_ptp_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
bitfld.long 0x34 1. "emacb,If set  the emacb_free_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
bitfld.long 0x34 0. "emaca,If set  the emaca_free_clk will be bypassed to the input clock reference of the Periphal PLL." "0,1"
line.long 0x38 "bypassr,Write One to Clear corresponding fields in Bypass Register."
hexmask.long.tbyte 0x38 8.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
eventfld.long 0x38 7. "usb31,If set  the USB31 clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
eventfld.long 0x38 6. "psiref,If set  the psi_ref_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
eventfld.long 0x38 5. "s2fuser1,If set  the s2f_user1_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
rbitfld.long 0x38 4. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x38 3. "gpiodb,If set  the gpio_db_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
eventfld.long 0x38 2. "emacptp,If set  the emac_ptp_clk will be bypassed to the input clock reference of the Peripheral PLL." "0,1"
newline
eventfld.long 0x38 1. "emacb,If set  the emacb_free_clk will be bypassed to the input clock reference of the Main PLL." "0,1"
newline
eventfld.long 0x38 0. "emaca,If set  the emaca_free_clk will be bypassed to the input clock reference of the Periphal PLL." "0,1"
line.long 0x3C "emacctl,Selects the source for emac0/1/2_clk either from emaca_free_clk or from emacb_free_clk."
rbitfld.long 0x3C 29.--31. "Reserved_3,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 28. "emac2sel,Selects the source for emac2_clk as either emaca_free_clk or emacb_free_clk." "0,1"
newline
bitfld.long 0x3C 27. "emac1sel,Selects the source for emac1_clk as either emaca_free_clk or emacb_free_clk." "0,1"
newline
bitfld.long 0x3C 26. "emac0sel,Selects the source for emac0_clk as either emaca_free_clk or emacb_free_clk." "0,1"
newline
hexmask.long 0x3C 0.--25. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x40 "gpiodiv,Contains a field that controls the clock divider for the GPIO De-bounce clock."
hexmask.long.word 0x40 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x40 0.--15. 1. "gpiodbclk,The gpio_db_clk is divided down from the periph_base_clk by the value plus one specified in this field. The value 0 (divide by 1) is illegal. A value of 1 indicates divide by 2  2 divide by 3  etc."
line.long 0x44 "pllglob,This refects register settings for all clock channels of peripheral PLL."
rbitfld.long 0x44 30.--31. "Reserved_12,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x44 29. "clr_lostlock_bypass,if lostlock_bypass_en is set and the PLL loses lock  channel bypass signal is asserted by HW." "0: no effect on PLL lostlock bypass mode,1: Clear PLL's lostlock bypass mode"
newline
bitfld.long 0x44 28. "lostlock_bypass_en,When PLL loses lock  the PLL output clocks are muted." "0: Turns OFF bypass to keepalive clock feature upon..,1: Turns on bypass to keepalive clock feature upon.."
newline
hexmask.long.byte 0x44 24.--27. 1. "modclkdiv,Reference clock divider control; the decimal value of this register will be the divider settings. Setting 0 will"
newline
rbitfld.long 0x44 22.--23. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x44 21. "fastrefclk,HP PLL fast reference clock mode control." "0,1"
newline
bitfld.long 0x44 20. "disctrl,Disconnect clock disable control. It is used to glitchlessly disable all keepalive clock in disconnect state." "0,1"
newline
bitfld.long 0x44 19. "clksync,Clock slice output synchronization request control. Once asserted  the positive edge of all enabled clock slices will be aligned." "0,1"
newline
bitfld.long 0x44 18. "pwrgatectrl,HP PLL Internal Power-gated State Control" "0,1"
newline
bitfld.long 0x44 16.--17. "psrc,Controls the VCO input clock source." "0,1,2,3"
newline
rbitfld.long 0x44 14.--15. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x44 12.--13. "drefclkdiv,Reference clock divider control used by the DPLL. The effective divider value is 2^(ictl_pll_drefdiv_nt_[1:0])." "0,1,2,3"
newline
hexmask.long.byte 0x44 8.--11. 1. "arefclkdiv,Reference clock divider control; the decimal value of this register will be the divider settings. Setting 0 will gate the clock coming out from the divider."
newline
hexmask.long.byte 0x44 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x44 1. "rst_n,Power-On Reset. Used to initialize memory and reset the Power Management Unit (PMU). The minimum POR assertion time required is 0.5 &micro;s." "0,1"
newline
bitfld.long 0x44 0. "pd_n,Keepalive clock power down control" "0,1"
line.long 0x48 "fdbck,VCO freq register counters"
hexmask.long.byte 0x48 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.tbyte 0x48 0.--23. 1. "fdiv,Fractional synthesizer center frequency control word."
line.long 0x4C "mem,Registers dealing with PLL internal memory access."
hexmask.long.byte 0x4C 27.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x4C 26. "err,Memory Error Status Signal. It will be asserted if invalid address is accessed" "0,1"
newline
bitfld.long 0x4C 25. "wr,Memory Read/Write Operation." "0,1"
newline
bitfld.long 0x4C 24. "req,Memory Request Signal" "0,1"
newline
hexmask.long.byte 0x4C 16.--23. 1. "wdat,Memory 'Write' Data bus."
newline
hexmask.long.word 0x4C 0.--15. 1. "addr,PLL Memory Address"
rgroup.long 0xA8++0x3
line.long 0x0 "memstat,Periph PLL memstatus register. contains memory read data."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--7. 1. "rdata,Memory Read Data"
group.long 0xAC++0x37
line.long 0x0 "vcocalib,VCO calibration control registers."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 27. "clr,HP PLL calibration clear control." "0,1"
newline
bitfld.long 0x0 25.--26. "banksel,Controls the calibration bank that will be used to store  restore or clear HP PLL calibration code." "0,1,2,3"
newline
rbitfld.long 0x0 24. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
hexmask.long.byte 0x0 16.--23. 1. "mscnt,ictl_pll_calvcomeascount_nt_[7:0] = 100/(Fvco/Fref_ effective_digital)"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--9. 1. "hscnt,VCO calibration parameter:"
line.long 0x4 "pllc0,Channel C0 frequency settings for the peri PLL"
rbitfld.long 0x4 30.--31. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
newline
rbitfld.long 0x4 29. "stat,HP PLL state transition status for clk_slice_0." "0,1"
newline
bitfld.long 0x4 28. "mute,Mutes PLL clock_slice_0 outputs without any glitch:" "0,1"
newline
bitfld.long 0x4 27. "en,PLL channel 0 output enable;" "0,1"
newline
bitfld.long 0x4 26. "bypas,PLL channel 0 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x4 11.--25. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--10. 1. "div,The ock_pll_clkslice_0 divider ratio in binary code."
line.long 0x8 "pllc1,Channel C1 frequency settings for the peri PLL"
rbitfld.long 0x8 30.--31. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
newline
rbitfld.long 0x8 29. "stat,HP PLL state transition status for clk_slice_1." "0,1"
newline
bitfld.long 0x8 28. "mute,Mutes PLL clock_slice_1 outputs without any glitch:" "0,1"
newline
bitfld.long 0x8 27. "en,PLL channel 1 output enable;" "0,1"
newline
bitfld.long 0x8 26. "bypas,PLL channel 1 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x8 11.--25. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x8 0.--10. 1. "div,The ock_pll_clkslice_1 divider ratio in binary code."
line.long 0xC "pllc2,Channel C2 frequency settings for the peri PLL"
rbitfld.long 0xC 30.--31. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
newline
rbitfld.long 0xC 29. "stat,HP PLL state transition status for clk_slice_2." "0,1"
newline
bitfld.long 0xC 28. "mute,Mutes PLL clock_slice_2 outputs without any glitch:" "0,1"
newline
bitfld.long 0xC 27. "en,PLL channel 2 output enable." "0,1"
newline
bitfld.long 0xC 26. "bypas,PLL channel 2 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0xC 11.--25. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0xC 0.--10. 1. "div,The ock_pll_clkslice_2 divider ratio in binary code."
line.long 0x10 "pllc3,Channel C3 frequency settings for the peri PLL"
rbitfld.long 0x10 30.--31. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
newline
rbitfld.long 0x10 29. "stat,HP PLL state transition status for clk_slice_3." "0,1"
newline
bitfld.long 0x10 28. "mute,Mutes PLL clock_slice_3 outputs without any glitch:" "0,1"
newline
bitfld.long 0x10 27. "en,PLL channel 3 output enable;" "0,1"
newline
bitfld.long 0x10 26. "bypas,PLL channel 3 output bypass. Before lock  it is muted  regardless of its value." "0,1"
newline
hexmask.long.word 0x10 11.--25. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x10 0.--10. 1. "div,The ock_pll_clkslice_3 divider ratio in binary code."
line.long 0x14 "pllm,Feedback Clock Divider Control (VCO Frequency Register Counters)"
hexmask.long.tbyte 0x14 10.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x14 0.--9. 1. "mdiv,Feedback clock divider. The HP PLL IP will initial operate at the frequency based on the Mdiv and Fdiv values set at PD state. It can be only set while the HP PLL IP is at Reset or PD state."
line.long 0x18 "fhop,Frequency Hopping (FHOP)/Dynamic Frequency Scaling(DFS) Control and status register."
hexmask.long.word 0x18 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x18 16. "ack,Asynchronous output. Acknowledge signal for the frequency ramp." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 8. "req,Request the HP PLL IP to perform the configured FHOP." "0,1"
newline
hexmask.long.byte 0x18 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0.--1. "dir,One-hot encoded." "0,1,2,3"
line.long 0x1C "ssc,Spread Spectrum Clocking (SSC) Control and Status Registers."
hexmask.long.tbyte 0x1C 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x1C 8. "stat,Indicates whether SSC is running." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 0. "en,Enables/Disables SSC." "0,1"
line.long 0x20 "lostlock,To enable the keep alive clock to appear on the clock slice outputs when PLL lock is lost. By default. the clock slices are muted (bit = 0)."
hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x20 0. "bypass_cleared,When all the bypass_en asserted due to loss of PLL lock from all the channels go low this bit gets set to 1." "0,1"
line.long 0x24 "jtag,Jtag control registers for the PLLs - Testing Access"
hexmask.long.tbyte 0x24 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x24 8. "rst,Jtag rst signal." "0,1"
newline
hexmask.long.byte 0x24 0.--7. 1. "id,JTAG ID used to provide each HP PLL IP a unique ID."
line.long 0x28 "emacactr,Contains settings that control emaca_free_clk generated from the Main PLL."
hexmask.long.word 0x28 19.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.byte 0x28 11.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x28 0.--10. 1. "cnt,Divides the emaca_free_clk frequency by the value+1 in this field."
line.long 0x2C "emacbctr,Contains settings that control emacb_free_clk generated from Peripheral PLL."
hexmask.long.tbyte 0x2C 11.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x2C 0.--10. 1. "cnt,Divides the emacb_free_clk frequency by the value+1 in this field."
line.long 0x30 "emacptpctr,Contains settings that control emac_ptp_free_clk generated from Peripheral PLL."
hexmask.long.word 0x30 19.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x30 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.byte 0x30 11.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x30 0.--10. 1. "cnt,Divides the emac_ptp_free_clk frequency by the value+1 in this field."
line.long 0x34 "gpiodbctr,Contains settings that control gpio_db_free_clk generated from the Peripheral PLL."
hexmask.long.word 0x34 19.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x34 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.byte 0x34 11.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x34 0.--10. 1. "cnt,Divides the gpio_db_free_clk frequency by the value+1 in this field."
group.long 0xE8++0x2B
line.long 0x0 "s2fuser0ctr,Contains settings that control s2f_user0_free_clk generated from Main PLL."
hexmask.long.word 0x0 19.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 16.--18. "src,Selects the source for the active 5:1 clock for s2f clock slice when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock for s2f clock slice when the PLL is not..,?,?"
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "cnt,Division setting for ping pong counter in clock slice. Divides the s2f_user0_free_clk frequency by this value + 1."
line.long 0x4 "s2fuser1ctr,Contains settings that control s2f_user1_free_clk generated from Main PLL."
hexmask.long.word 0x4 19.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.byte 0x4 11.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--10. 1. "cnt,Division setting for ping pong counter in clock slice. Divides the s2f_user1_free_clk frequency by this value + 1."
line.long 0x8 "psirefctr,Contains settings that control psi_ref_free_clk generated from the Main PLL."
hexmask.long.word 0x8 19.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
newline
hexmask.long.byte 0x8 11.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x8 0.--10. 1. "cnt,Divides the psi_ref_free_clk frequency by the value+1 in this field."
line.long 0xC "extcntrst,Used to hold associated pingpong counter in reset while PLL and 5:1 mux configuration is changed."
hexmask.long.tbyte 0xC 14.--31. 1. "Reserved_12,Reserved bitfield added by Magillem"
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bitfld.long 0xC 13. "core3cntrst,This bit holds the associated core3 external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
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bitfld.long 0xC 12. "core2cntrst,This bit holds the associated core2 external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
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bitfld.long 0xC 11. "core01cntrst,This bit holds the associated core01 external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
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bitfld.long 0xC 10. "dsucntrst,This bit holds the associated DSU external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
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rbitfld.long 0xC 9. "Reserved_8,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xC 8. "usb31refcntrst,This bit holds the associated usb31 external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
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bitfld.long 0xC 7. "psirefcntrst,This bit holds the associated psi_ref external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
newline
bitfld.long 0xC 6. "s2fuser1cntrst,This bit holds the associated s2f_user1 external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
newline
bitfld.long 0xC 5. "s2fuser0cntrst,This bit holds the associated s2f_user0 external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
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rbitfld.long 0xC 4. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0xC 3. "gpiodbcntrst,This bit holds the associated gpio_db external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
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bitfld.long 0xC 2. "emacptpcntrst,This bit holds the associated emac_ptp external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
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bitfld.long 0xC 1. "emacbcntrst,This bit holds the associated emacb external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
newline
bitfld.long 0xC 0. "emacacntrst,This bit holds the associated emaca external pingpong counter in reset while PLL and 5:1 mux configuration is changed." "0: pingpong counter is not in reset,1: pingpong counter is in reset"
line.long 0x10 "usb31ctr,Contains settings that control usb31_clk generated from PLL."
hexmask.long.word 0x10 19.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
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bitfld.long 0x10 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
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hexmask.long.byte 0x10 11.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.word 0x10 0.--10. 1. "cnt,Division setting for ping pong counter in clock slice. Divides the usb31_clk frequency by this value + 1."
line.long 0x14 "dsuctr,Contains settings that control dsu_clk generated from PLL."
hexmask.long.word 0x14 19.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
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bitfld.long 0x14 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
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hexmask.long.byte 0x14 11.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.word 0x14 0.--10. 1. "cnt,Division setting for ping pong counter in DSU clock slice. Divides the dsu_clk frequency by this value + 1."
line.long 0x18 "core01ctr,Contains settings that control core01_clk generated from PLL."
hexmask.long.word 0x18 19.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
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bitfld.long 0x18 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
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hexmask.long.byte 0x18 11.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.word 0x18 0.--10. 1. "cnt,Division setting for ping pong counter in clock slice. Divides the core01_clk frequency by this value + 1."
line.long 0x1C "core23ctr,Contains settings that control core23_clk generated from PLL."
hexmask.long.word 0x1C 19.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
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bitfld.long 0x1C 16.--18. "src,Selects the source for the active 5:1 clock selection when the PLL is not bypassed." "?,?,?,?,?,5: 1 clock selection when the PLL is not bypassed,?,?"
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hexmask.long.word 0x1C 0.--15. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x20 "core2ctr,Contains settings that control core2_clk generated from PLL."
hexmask.long.tbyte 0x20 11.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.word 0x20 0.--10. 1. "cnt,Division setting for ping pong counter in clock slice. Divides the core2_clk frequency by this value + 1."
line.long 0x24 "core3ctr,Contains settings that control core3_clk generated from PLL."
hexmask.long.tbyte 0x24 11.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x24 0.--10. 1. "cnt,Division setting for ping pong counter in clock slice. Divides the core3_clk frequency by this value + 1."
line.long 0x28 "serial_con_pll_ctr"
hexmask.long 0x28 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0. "en,to control pll_jtag reset source selection" "0,1"
tree.end
tree "COMBO_PHY (Combo DLL PHY)"
base ad:0x10B92000
group.long 0x0++0x17
line.long 0x0 "phy_dq_timing_reg,This register controls the DQ related timing."
bitfld.long 0x0 31. "io_mask_always_on,Defines if the IO mask for DATA/CMD is always enabled." "0,1"
rbitfld.long 0x0 30. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 27.--29. "io_mask_end,Adjusts the ending point of the DQ/CMD pad input mask enable. Defines the delay after dfi_wrdata_en/dfi_wrcmd_en goes high when the mask is disabled (data/cmd are blocked and 1'b1 are passed to PHY)." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 24.--26. "io_mask_start,Adjusts the starting point of the DQ/CMD pad input mask enable. Defines the delay after dfi_wrdata_en/dfi_wrcmd_en goes low when the mask is enabled (data/cmd are passed to PHY)." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 16.--23. 1. "data_clkperiod_delay,Defines additional latency on the write datapath. It also adds a clock cycle delay for the data OE path which is equivalent of adding 2 to the data_select_oe_end and data_select_oe_start."
hexmask.long.byte 0x0 12.--15. 1. "data_select_tsel_start,Defines the DQ pad dynamic termination select enable time. Larger values add greater delay to when tsel turns on. Each bit changes the output enable time by a 1/2 cycle resolution."
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hexmask.long.byte 0x0 8.--11. 1. "data_select_tsel_end,Defines the DQ pad dynamic termination select disable time. Larger values increase the delay to when tsel turns off. Each bit changes the output enable time by a 1/2 cycle resolution."
rbitfld.long 0x0 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x0 4.--6. "data_select_oe_start,Adjusts the starting point of the DQ pad output enable window. Lower numbers pull the rising edge earlier in time and larger numbers cause the rising edge to be delayed. Each bit changes the output enable time by a 1/2 cycle.." "0,1,2,3,4,5,6,7"
rbitfld.long 0x0 3. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 0.--2. "data_select_oe_end,Adjusts the ending point of the DQ pad output enable window. Lower numbers pull the falling edge earlier in time and larger numbers" "0,1,2,3,4,5,6,7"
line.long 0x4 "phy_dqs_timing_reg,This register controls the DQS related timing."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_10,Reserved bitfield added by Magillem"
bitfld.long 0x4 23. "dqs_clkperiod_delay,Defines additional latency on the write DQS path. It also adds a clock cycle delay for the dqs OE path which is equivalent of adding 2 to the dqs_select_oe_end and dqs_select_oe_start." "0,1"
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bitfld.long 0x4 22. "use_ext_lpbk_dqs,Bit to choose lpbk_dqs to capture data for reads. It is valid when 'use_phony_dqs' and 'use_lpbk_dqs' fields are set high. [list] [*]0 - use internal lpbk_dqs (mem_rebar_ipad) for data capture.[*]1 - use external lpbk_dqs (lpbk_dqs.." "0,1"
bitfld.long 0x4 21. "use_lpbk_dqs,This bit is used in conjunction with bits 22 and 20 to control how read data is sampled by the PHY." "0,1"
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bitfld.long 0x4 20. "use_phony_dqs,Bit to choose lpbk_dqs or phony DQS (generated in the control slice logic) or DQS from the device to capture data for reads. [list] [*]0 - Use DQS from device for data capture.[*]1 - Use phony DQS or lpbk_dqs for data capture. Bit 21 of the.." "0,1"
bitfld.long 0x4 19. "use_phony_dqs_cmd,Bit to choose phony DQS (or lpbk_dqs) from the control slice logic or DQS from the device to capture command data for reads. [list] [*]0 - Use DQS from device for command data capture.[*]1 - Use phony DQS or lpbk_dqs for command data.." "0,1"
newline
rbitfld.long 0x4 17.--18. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
bitfld.long 0x4 16. "phony_dqs_sel,If this bit is cleared the phony_dqs is synchronous with rising edge of the clk_phy before sending to the entry flops. If this bit is set high the phony_dqs is synchronous with falling edge of clk_phy before sending to the entry flops." "0,1"
newline
hexmask.long.byte 0x4 12.--15. 1. "dqs_select_tsel_start,Defines the DQ pad dynamic termination select enable time. Larger values add greater delay to when tsel turns on. Each bit changes the output enable time by a 1/2 cycle resolution."
hexmask.long.byte 0x4 8.--11. 1. "dqs_select_tsel_end,Defines the DQ pad dynamic termination select disable time. Larger values increase the delay to when tsel turns off. Each bit changes the output enable time by a 1/2 cycle resolution."
newline
hexmask.long.byte 0x4 4.--7. 1. "dqs_select_oe_start,Adjusts the starting point of the DQS pad output enable window. Lower numbers pull the rising edge earlier in time and larger numbers cause the rising edge to be delayed. Each bit changes the output enable time by a 1/2 cycle.."
hexmask.long.byte 0x4 0.--3. 1. "dqs_select_oe_end,Adjusts the ending point of the DQS pad output enable window. Lower numbers pull the falling edge earlier in time and larger numbers cause the falling edge to be delayed. Each bit changes the output enable time by a 1/2 cycle.."
line.long 0x8 "phy_gate_lpbk_ctrl_reg,This register controls the gate and loopback control related timing."
bitfld.long 0x8 31. "sync_method,Defines the method of transfering the data from DQS domain flops to the clk_phy clock domain." "0,1"
bitfld.long 0x8 30. "sw_dqs_phase_bypass,[list]" "0,1"
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bitfld.long 0x8 29. "en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x8 28. "sw_half_cycle_shift,[list]" "0,1"
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bitfld.long 0x8 25.--27. "param_phase_detect_sel_oe,DLL Phase Detect Selector for DQS OE generation to handle the clock domain crossing between the clock and clk_wrdqs signal. Selects the number" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 19.--24. 1. "rd_del_sel,Defines the read data delay. Holds the number of cycles to delay the dfi_rddata_en signal prior to enabling the read FIFO. After this delay  the read pointers begin incrementing the read FIFO."
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bitfld.long 0x8 18. "underrun_suppress,This field turns off the generation of the underrun signal when 'sync_method' is set high." "0,1"
rbitfld.long 0x8 17. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x8 16. "rd_del_sel_empty,Defines the read data delay for the empty signal generated based on the incoming DQS strobes. For zero delay the data are passed from entry flops to the iodatain* flops one clock cycle after the !empty signals is asserted." "0,1"
bitfld.long 0x8 13.--15. "lpbk_err_check_timing,Sets the cycle delay between the LFSR and loopback error check logic to ensure that the LFSR sourced data and data being looped back arrive at the same clock cycle for comparison. This value is related to the rd_del_sel field  and.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 12. "lpbk_fail_muxsel,Selects data output type for phy_obs_reg_0[23:8]. [list][*]0 = Return the expected data. [*]1 = Return the actual data.[/list]" "0,1"
bitfld.long 0x8 10.--11. "loopback_control,Loopback control. [list][*]0 = Normal Operation Mode. [*]1 = lpbk_start; Enables loopback write mode. [*]2 = lpbk_stop; Stop loopback to check error register. [*]3 = clear; Clear loopback registers.[/list]" "0,1,2,3"
newline
bitfld.long 0x8 9. "lpbk_internal,Controls the loopback read multiplexer. [list][*]0 = External Loopback. [*]1 = Internal loopback.[/list]" "0,1"
bitfld.long 0x8 8. "lpbk_en,Controls internal write multiplexer. [list][*]0 = Normal Operation. [*]1 = Enable loopback.[/list]" "0,1"
newline
rbitfld.long 0x8 7. "Reserved_3,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x8 6. "gate_cfg_always_on,This parameter cause the gate to be always on." "0,1"
newline
bitfld.long 0x8 4.--5. "gate_cfg_close,Normally the gate is closing when all bits of dfi_cebar are high or when dfi_rd_pre_post_amble and rebar_dfi are high. This parameter allows to extend the closing of the DQS gate. Recommended value is zero." "0,1,2,3"
hexmask.long.byte 0x8 0.--3. 1. "gate_cfg,Coarse adjust of gate open time. This value is the number of cycles to delay the dfi_rddata_en signal prior to opening the gate in full cycle increments. Decreasing this value pulls the gate earlier in time. This field should be programmed such.."
line.long 0xC "phy_dll_master_ctrl_reg,This register holds the control for the Master DLL logic."
hexmask.long.byte 0xC 24.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0xC 23. "param_dll_bypass_mode,DLL bypass mode control. Controls the bypass mode of the master and slave DLLs. The param_dll_bypass_mode is intended to be used only for debug. [list][*]0 - Normal operational mode. DLL functioning in normal mode of operation where.." "0,1"
newline
bitfld.long 0xC 20.--22. "param_phase_detect_sel,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7"
rbitfld.long 0xC 19. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xC 16.--18. "param_dll_lock_num,Holds the number of consecutive increment or decrement indications that will trigger an unlock condition and increment the dll_unlock_cnt field (bits [7:3]) and either the lock_dec_dbg (bits [23:16]) or lock_inc_dbg (bits [31:24]).." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--7. 1. "param_dll_start_point,This value is the initial delay value for the DLL. This value is also used as the increment value if the initial value is less than a half-clock cycle. This field should be set such that it is not greater than 7/8ths of a clock.."
line.long 0x10 "phy_dll_slave_ctrl_reg,This register holds the control for the slave DLL logic."
hexmask.long.byte 0x10 24.--31. 1. "read_dqs_cmd_delay,Controls the read command DQS delay which adjusts the timing in 1/256th of the clock period when in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements."
hexmask.long.byte 0x10 16.--23. 1. "clk_wrdqs_delay,Controls the clk_wrdqs delay line which adjusts the write DQS timing in 1/256th steps of the clock period in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements."
newline
hexmask.long.byte 0x10 8.--15. 1. "clk_wr_delay,Controls the clk_wr delay line which adjusts the write DQ bit timing in 1/256th steps of the clock period in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements."
hexmask.long.byte 0x10 0.--7. 1. "read_dqs_delay,Controls the read DQS delay which adjusts the timing in 1/256th of the clock period when in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements."
line.long 0x14 "phy_ie_timing_reg,This register controls the DQS related timing."
hexmask.long.word 0x14 21.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x14 20. "ie_always_on,Forces the input enable(s) to be on always." "0,1"
newline
rbitfld.long 0x14 19. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x14 16.--18. "dq_ie_start,Define the start position for the DQ input enable." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x14 15. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x14 12.--14. "dq_ie_stop,Define the stop position for the DQ input enable." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x14 11. "Reserved_3,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x14 8.--10. "dqs_ie_start,Define the start position for the DQS input enable." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x14 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x14 4.--6. "dqs_ie_stop,Define the stop position for the DQS input enable." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x14 0.--3. 1. "rddata_en_ie_dly,Specifies the number of clocks of delay for the dfi_rddata_en signal to line it up with the true (normal) DFI read data position. The MC must deliver an early version of the read data enable to allow time for the input pads to turn on.."
rgroup.long 0x18++0xF
line.long 0x0 "phy_obs_reg_0,This register holds the following observable points in the PHY."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 27. "dqs_cmd_overflow,CMD Status signal to indicate that the logic gate was closed too late" "0,1"
newline
bitfld.long 0x0 26. "dqs_cmd_underrun,CMD Status signal to indicate that the logic gate had to" "0,1"
bitfld.long 0x0 25. "dqs_overflow,Status signal to indicate that the logic gate was closed too late" "0,1"
newline
bitfld.long 0x0 24. "dqs_underrun,Status signal to indicate that the logic gate had to" "0,1"
hexmask.long.word 0x0 8.--23. 1. "lpbk_dq_data,If errors are encountered in loopback test this field reports the actual data or the expected data  depending on the setting of the phy_gate_lpbk_ctrl_reg [12] parameter bit. This field is not clear by the clear state of the loopback. If.."
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0.--1. "lpbk_status,Loopback Status [list] [*] Bit0 - lpbk start; Defines the status of the loopback mode. 0 = Not in loopback mode; 1 = In loopback mode. [*] Bit1 - lpbk status; Defines the status of the loopback mode. 0 = Last Loopback test had no errors; 1 =.." "0: Last Loopback test had no errors,1: Last loopback test contained data errors,?,?"
line.long 0x4 "phy_dll_obs_reg_0,This register holds the following observable points in the PHY."
hexmask.long.byte 0x4 24.--31. 1. "lock_inc_dbg,Holds the state of the cumulative dll_lock_inc register when the dll_unlock_cnt field(bits [7:3]) of this parameter was triggered to increment or was last saturated at a value of 0x1f."
hexmask.long.byte 0x4 16.--23. 1. "lock_dec_dbg,Holds the state of the cumulative dll_lock_dec register when the dll_unlock_cnt field(bits [7:3]) of this parameter was triggered to decrement or was last saturated at a value of 0x1f."
newline
hexmask.long.byte 0x4 8.--15. 1. "dll_lock_value,Reports the number of delay elements that the DLL has determined for lock in either full clock or half clock mode. In full clock mode  this value equals the number of delay elements in one cycle. In half clock mode  this value equals the.."
hexmask.long.byte 0x4 3.--7. 1. "dll_unlock_cnt,Reports the number of times that the master DLL consecutive increment or decrement value programmed into the param_dll_lock_num field (bits [18:16]) of the phy_dll_master_ctrl_reg register has been triggered. The dll_unlock_cnt will.."
newline
bitfld.long 0x4 1.--2. "dll_locked_mode,Indicates status of DLL. Defines the mode in which the DLL has achieved the lock." "0,1,2,3"
bitfld.long 0x4 0. "dll_lock,Indicates status of DLL. It indicates the DLL locking when the DLL lock logic found (not inc AND not dec) OR (an inc then dec) OR (a dec then inc). When param_dll_start_point is set smaller than half clock period the first found (a dec then inc).." "0,1"
line.long 0x8 "phy_dll_obs_reg_1,This register holds the following observable points in the PHY."
hexmask.long.byte 0x8 24.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 16.--23. 1. "decoder_out_wr,Holds the encoded value for the clk_wr delay line for this slice."
newline
hexmask.long.byte 0x8 8.--15. 1. "decoder_out_rd_cmd,Holds the encoded value for the CMD read delay line for this slice."
hexmask.long.byte 0x8 0.--7. 1. "decoder_out_rd,Holds the encoded value for the read delay line for this slice."
line.long 0xC "phy_dll_obs_reg_2,This register holds the following observable points in the PHY."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0xC 0.--7. 1. "decoder_out_wrdqs,Holds the encoded value for the clk_wrdqs delay line for this slice."
group.long 0x28++0x17
line.long 0x0 "phy_static_togg_reg,This register controls the static aging feature of the PHY."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "read_dqs_togg_enable,Enables the toggling for the active part of the read_dqs delay line in idle state." "0,1"
newline
hexmask.long.byte 0x0 20.--23. 1. "static_togg_enable,Control to enable the toggle signal during static activity."
rbitfld.long 0x0 17.--19. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16. "static_togg_global_enable,Global control to enable the toggle signal during static activity." "0,1"
hexmask.long.word 0x0 0.--15. 1. "static_tog_clk_div,Clock divider to create toggle signal."
line.long 0x4 "phy_wr_deskew_reg,This register holds the values of delay of each DQ bit on the write path."
hexmask.long.byte 0x4 28.--31. 1. "wr_dq7_deskew_delay,Deskew delay for DQ bit 7."
hexmask.long.byte 0x4 24.--27. 1. "wr_dq6_deskew_delay,Deskew delay for DQ bit 6."
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hexmask.long.byte 0x4 20.--23. 1. "wr_dq5_deskew_delay,Deskew delay for DQ bit 5."
hexmask.long.byte 0x4 16.--19. 1. "wr_dq4_deskew_delay,Deskew delay for DQ bit 4."
newline
hexmask.long.byte 0x4 12.--15. 1. "wr_dq3_deskew_delay,Deskew delay for DQ bit 3."
hexmask.long.byte 0x4 8.--11. 1. "wr_dq2_deskew_delay,Deskew delay for DQ bit 2."
newline
hexmask.long.byte 0x4 4.--7. 1. "wr_dq1_deskew_delay,Deskew delay for DQ bit 1."
hexmask.long.byte 0x4 0.--3. 1. "wr_dq0_deskew_delay,Deskew delay for DQ bit 0."
line.long 0x8 "phy_wr_rd_deskew_cmd_reg,This register holds the values of delay of CMD bit on the write and read path as well as the values of phase detect block for CMD bit on the write path."
hexmask.long.byte 0x8 28.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 24.--27. 1. "rd_cmd_deskew_delay,Deskew delay for CMD signal."
newline
hexmask.long.byte 0x8 17.--23. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "cmd_clkperiod_delay,Defines additional latency on the CMD signal." "0,1"
newline
rbitfld.long 0x8 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x8 14. "cmd_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0x8 13. "cmd_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x8 12. "cmd_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0x8 11. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x8 8.--10. "cmd_phase_detect_sel,DLL Phase Detect Selector for CMD generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 4.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 0.--3. 1. "wr_cmd_deskew_delay,Deskew delay for CMD signal"
line.long 0xC "phy_wr_deskew_pd_ctrl_0_reg,This register holds the values of phase detect block for each DQ bit on the write path."
rbitfld.long 0xC 31. "Reserved_16,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 30. "dq3_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0xC 29. "dq3_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0xC 28. "dq3_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0xC 27. "Reserved_13,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 24.--26. "dq3_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0xC 23. "Reserved_12,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 22. "dq2_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0xC 21. "dq2_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0xC 20. "dq2_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0xC 19. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 16.--18. "dq2_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0xC 15. "Reserved_8,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 14. "dq1_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0xC 13. "dq1_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0xC 12. "dq1_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0xC 11. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 8.--10. "dq1_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0xC 7. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 6. "dq0_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0xC 5. "dq0_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0xC 4. "dq0_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0xC 3. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 0.--2. "dq0_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
line.long 0x10 "phy_wr_deskew_pd_ctrl_1_reg,This register holds the values of phase detect block for each DQ bit on the write path."
rbitfld.long 0x10 31. "Reserved_16,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 30. "dq7_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0x10 29. "dq7_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x10 28. "dq7_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0x10 27. "Reserved_13,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 24.--26. "dq7_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 23. "Reserved_12,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 22. "dq6_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0x10 21. "dq6_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x10 20. "dq6_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0x10 19. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 16.--18. "dq6_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 15. "Reserved_8,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 14. "dq5_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0x10 13. "dq5_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x10 12. "dq5_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0x10 11. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 8.--10. "dq5_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 7. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 6. "dq4_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0x10 5. "dq4_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x10 4. "dq4_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0x10 3. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 0.--2. "dq4_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
line.long 0x14 "phy_rd_deskew_reg,This register holds the values of delay of each DQ bit on the read path."
hexmask.long.byte 0x14 28.--31. 1. "rd_dq7_deskew_delay,Deskew delay for DQ bit 7."
hexmask.long.byte 0x14 24.--27. 1. "rd_dq6_deskew_delay,Deskew delay for DQ bit 6."
newline
hexmask.long.byte 0x14 20.--23. 1. "rd_dq5_deskew_delay,Deskew delay for DQ bit 5."
hexmask.long.byte 0x14 16.--19. 1. "rd_dq4_deskew_delay,Deskew delay for DQ bit 4."
newline
hexmask.long.byte 0x14 12.--15. 1. "rd_dq3_deskew_delay,Deskew delay for DQ bit 3."
hexmask.long.byte 0x14 8.--11. 1. "rd_dq2_deskew_delay,Deskew delay for DQ bit 2."
newline
hexmask.long.byte 0x14 4.--7. 1. "rd_dq1_deskew_delay,Deskew delay for DQ bit 1."
hexmask.long.byte 0x14 0.--3. 1. "rd_dq0_deskew_delay,Deskew delay for DQ bit 0."
rgroup.long 0x70++0x7
line.long 0x0 "phy_version_reg,This register contains release identification number."
hexmask.long.word 0x0 16.--31. 1. "combo_phy_magic_number,Magic number."
hexmask.long.byte 0x0 8.--15. 1. "phy_fix,Fixed number (minor revision number)."
newline
hexmask.long.byte 0x0 0.--7. 1. "phy_rev,PHY revision number."
line.long 0x4 "phy_features_reg,This register shows available hardware features."
hexmask.long.word 0x4 16.--31. 1. "Reserved_15,Reserved bitfield added by Magillem"
bitfld.long 0x4 15. "asf_sup,Support for Automotive Safety Feature." "0,1"
newline
bitfld.long 0x4 14. "pll_sup,Support for PLL." "0,1"
bitfld.long 0x4 13. "jtag_sup,Support for JTAG muxes." "0,1"
newline
bitfld.long 0x4 12. "ext_lpbk_dqs,Support for external LPBK_DQS io pad." "0,1"
bitfld.long 0x4 11. "reg_intf,SFR interface type. This is an encoded value. [list][*]0 - DFI. [*]1 - APB.[/list]" "0,1"
newline
bitfld.long 0x4 10. "per_bit_deskew,Support for per-bit deskew." "0,1"
bitfld.long 0x4 9. "dfi_clock_ratio,Support for clock ratio on DFI interface. This is an encoded value. [list][*]0 - 1:1 [*]1 - 1:2 [/list]" "?,1: 2 [/list]"
newline
bitfld.long 0x4 8. "aging,Support for aging in delay lines." "0,1"
bitfld.long 0x4 7. "dll_tap_num,Number of taps in delay line. This is an encoded value. [list][*]0 - 128. [*]1 - 256. [/list]" "0,1"
newline
bitfld.long 0x4 5.--6. "bank_num,Maximum number of banks supported by hardware. This is an encoded value. [list][*]0 - One bank. [*]1 - Two banks. [*]2 - Four banks. [*]3 - Eight banks.[/list]" "0,1,2,3"
bitfld.long 0x4 4. "sd_emmc,Support for SD/eMMC." "0,1"
newline
bitfld.long 0x4 3. "Reserved,Reserved." "0,1"
bitfld.long 0x4 2. "sdr_16bit,Support for 16bit in ONFI SDR work mode." "0,1"
newline
bitfld.long 0x4 1. "Reserved,Reserved." "0,1"
bitfld.long 0x4 0. "Reserved,Reserved." "0,1"
group.long 0x80++0xF
line.long 0x0 "phy_ctrl_reg,This register handles the global control settings for the PHY."
hexmask.long.word 0x0 22.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 21. "pu_pd_polarity,Defines the polarity of the ALE port that in SD works as pull-up/pull-down signal for bit 2 of the DATA." "0,1"
newline
bitfld.long 0x0 20. "low_freq_sel,If this field is set high the DFI interface is synchronous to the falling edge of the clock" "0,1"
hexmask.long.byte 0x0 15.--19. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 14. "sdr_dqs_value,The value that should be driven on the DQS pin while SDR operations are in progress. Please note that in the DDR modes of operations  the command and address cycles are still in SDR mode. This field informs the PHY of the value to be driven.." "0,1"
hexmask.long.byte 0x0 10.--13. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 4.--9. 1. "phony_dqs_timing,The timing of assertion of phony DQS to the data slices. If the extended_read_mode is disabled the value should be zero. If the extended_read_mode is enabled the value should match the width of the rebar pulse in terms of clock PHY clock.."
rbitfld.long 0x0 1.--3. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "ctrl_clkperiod_delay,Defines additional latency on the control signals ALE/CLE/WE/RE/CE/WP." "0,1"
line.long 0x4 "phy_tsel_reg,This register handles the global control settings for the termination selects for reads."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 20.--23. 1. "tsel_off_value_data,Termination select off value for the data."
newline
hexmask.long.byte 0x4 16.--19. 1. "tsel_rd_value_data,Termination select read value for the data."
hexmask.long.byte 0x4 12.--15. 1. "tsel_off_value_dqs,Termination select off value for the data strobe."
newline
hexmask.long.byte 0x4 8.--11. 1. "tsel_rd_value_dqs,Termination select read value for the data strobe."
hexmask.long.byte 0x4 0.--7. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x8 "phy_gpio_ctrl_0,Reserved."
hexmask.long 0x8 0.--31. 1. "Reserved,Reserved."
line.long 0xC "phy_gpio_ctrl_1,Reserved."
hexmask.long 0xC 0.--31. 1. "Reserved,Reserved."
rgroup.long 0x90++0x7
line.long 0x0 "phy_gpio_status_0,Reserved"
hexmask.long 0x0 0.--31. 1. "Reserved,Reserved."
line.long 0x4 "phy_gpio_status_1,Reserved."
hexmask.long 0x4 0.--31. 1. "Reserved,Reserved."
tree.end
tree "DMAC (DMA Controller)"
base ad:0x0
tree "DMAC_0"
base ad:0x10DB0000
rgroup.quad 0x0++0xF
line.quad 0x0 "DMAC_IDREG,DMAC ID Register contains a 32-bit value that is hardwired and read back by a read to the DW_axi_dmac ID Register."
hexmask.quad.long 0x0 32.--63. 1. "RSVD_DMAC_IDREG,DMAC_IDREG Reserved bits - Read Only"
newline
hexmask.quad.long 0x0 0.--31. 1. "DMAC_ID,DMAC ID Number."
line.quad 0x8 "DMAC_COMPVERREG,This register contains a 32-bit value that is hardwired and read back by a read to the DW_axi_dmac Component Version Register."
hexmask.quad.long 0x8 32.--63. 1. "RSVD_DMAC_COMPVERREG,DMAC_COMPVERREG Reserved bits - Read Only"
newline
hexmask.quad.long 0x8 0.--31. 1. "DMAC_COMPVER,DMAC Component Version Number."
group.quad 0x10++0xF
line.quad 0x0 "DMAC_CFGREG,This register is used to enable the DW_axi_dmac. which must be done before any channel"
hexmask.quad 0x0 2.--63. 1. "RSVD_DMAC_CFGREG,DMAC_CFGREG Reserved bits - Read Only"
newline
bitfld.quad 0x0 1. "INT_EN,This bit is used to globally enable the interrupt generation." "0: DW_axi_dmac Interrupts are disabled,1: DW_axi_dmac Interrupt logic is enabled"
newline
bitfld.quad 0x0 0. "DMAC_EN,This bit is used to enable the DW_axi_dmac." "0: DW_axi_dmac disabled,1: DW_axi_dmac enabled"
line.quad 0x8 "DMAC_CHENREG,This is DW_axi_dmac Channel Enable Register. If software wants to set up a new channel. it can read this register to find out which channels are currently inactive and then enable an inactive channel with the required priority."
hexmask.quad.word 0x8 48.--63. 1. "RSVD_DMAC_CHENREG,DMAC_CHENREG Reserved bits - Read Only"
newline
bitfld.quad 0x8 47. "CH8_ABORT_WE,This bit is used to write enable the Channel-8 Abort bit." "0,1"
newline
bitfld.quad 0x8 46. "CH7_ABORT_WE,This bit is used to write enable the Channel-7 Abort bit." "0,1"
newline
bitfld.quad 0x8 45. "CH6_ABORT_WE,This bit is used to write enable the Channel-6 Abort bit." "0,1"
newline
bitfld.quad 0x8 44. "CH5_ABORT_WE,This bit is used to write enable the Channel-5 Abort bit." "0,1"
newline
bitfld.quad 0x8 43. "CH4_ABORT_WE,This bit is used to write enable the Channel-4 Abort bit." "0,1"
newline
bitfld.quad 0x8 42. "CH3_ABORT_WE,This bit is used to write enable the Channel-3 Abort bit." "0,1"
newline
bitfld.quad 0x8 41. "CH2_ABORT_WE,This bit is used to write enable the Channel-2 Abort bit." "0,1"
newline
bitfld.quad 0x8 40. "CH1_ABORT_WE,This bit is used to write enable the Channel-1 Abort bit." "0,1"
newline
bitfld.quad 0x8 39. "CH8_ABORT,Channel-8 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 38. "CH7_ABORT,Channel-7 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 37. "CH6_ABORT,Channel-6 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 36. "CH5_ABORT,Channel-5 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 35. "CH4_ABORT,Channel-4 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 34. "CH3_ABORT,Channel-3 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 33. "CH2_ABORT,Channel-2 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 32. "CH1_ABORT,Channel-1 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 31. "CH8_SUSP_WE,This bit is used as a write enable to the Channel-8 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 30. "CH7_SUSP_WE,This bit is used as a write enable to the Channel-7 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 29. "CH6_SUSP_WE,This bit is used as a write enable to the Channel-6 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 28. "CH5_SUSP_WE,This bit is used as a write enable to the Channel-5 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 27. "CH4_SUSP_WE,This bit is used as a write enable to the Channel-4 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 26. "CH3_SUSP_WE,This bit is used as a write enable to the Channel-3 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 25. "CH2_SUSP_WE,This bit is used as a write enable to the Channel-2 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 24. "CH1_SUSP_WE,This bit is used as a write enable to the Channel-1 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 23. "CH8_SUSP,Channel-8 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 22. "CH7_SUSP,Channel-7 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 21. "CH6_SUSP,Channel-6 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 20. "CH5_SUSP,Channel-5 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 19. "CH4_SUSP,Channel-4 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 18. "CH3_SUSP,Channel-3 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 17. "CH2_SUSP,Channel-2 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 16. "CH1_SUSP,Channel-1 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 15. "CH8_EN_WE,DW_axi_dmac Channel-8 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 14. "CH7_EN_WE,DW_axi_dmac Channel-7 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 13. "CH6_EN_WE,DW_axi_dmac Channel-6 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 12. "CH5_EN_WE,DW_axi_dmac Channel-5 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 11. "CH4_EN_WE,DW_axi_dmac Channel-4 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 10. "CH3_EN_WE,DW_axi_dmac Channel-3 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 9. "CH2_EN_WE,DW_axi_dmac Channel-2 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 8. "CH1_EN_WE,DW_axi_dmac Channel-1 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 7. "CH8_EN,This bit is used to enable the DW_axi_dmac Channel-8." "0: DW_axi_dmac Channel-8 is disabled,1: DW_axi_dmac Channel-8 is enabled"
newline
bitfld.quad 0x8 6. "CH7_EN,This bit is used to enable the DW_axi_dmac Channel-7." "0: DW_axi_dmac Channel-7 is disabled,1: DW_axi_dmac Channel-7 is enabled"
newline
bitfld.quad 0x8 5. "CH6_EN,This bit is used to enable the DW_axi_dmac Channel-6." "0: DW_axi_dmac Channel-6 is disabled,1: DW_axi_dmac Channel-6 is enabled"
newline
bitfld.quad 0x8 4. "CH5_EN,This bit is used to enable the DW_axi_dmac Channel-5." "0: DW_axi_dmac Channel-5 is disabled,1: DW_axi_dmac Channel-5 is enabled"
newline
bitfld.quad 0x8 3. "CH4_EN,This bit is used to enable the DW_axi_dmac Channel-4." "0: DW_axi_dmac Channel-4 is disabled,1: DW_axi_dmac Channel-4 is enabled"
newline
bitfld.quad 0x8 2. "CH3_EN,This bit is used to enable the DW_axi_dmac Channel-3." "0: DW_axi_dmac Channel-3 is disabled,1: DW_axi_dmac Channel-3 is enabled"
newline
bitfld.quad 0x8 1. "CH2_EN,This bit is used to enable the DW_axi_dmac Channel-2." "0: DW_axi_dmac Channel-2 is disabled,1: DW_axi_dmac Channel-2 is enabled"
newline
bitfld.quad 0x8 0. "CH1_EN,This bit is used to enable the DW_axi_dmac Channel-1." "0: DW_axi_dmac Channel-1 is disabled,1: DW_axi_dmac Channel-1 is enabled"
rgroup.quad 0x30++0x7
line.quad 0x0 "DMAC_INTSTATUSREG,DMAC Interrupt Status Register captures the combined channel interrupt for each channel and Combined common register block interrupt. This register is present provided number of DMA channels are greater than 8."
hexmask.quad 0x0 17.--63. 1. "RSVD_DMAC_INTSTATUSREG_63to17,DMAC Interrupt Status Register (bits 63to17) Reserved bits - Read Only"
newline
bitfld.quad 0x0 16. "CommonReg_IntStat,Common Register Interrupt Status Bit." "0,1"
newline
hexmask.quad.byte 0x0 8.--15. 1. "RSVD_DMAC_INTSTATUSREG,DMAC Interrupt Status Register (bits 15to8) Reserved bits - Read Only"
newline
bitfld.quad 0x0 7. "CH8_IntStat,Channel 8 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 6. "CH7_IntStat,Channel 7 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 5. "CH6_IntStat,Channel 6 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 4. "CH5_IntStat,Channel 5 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 3. "CH4_IntStat,Channel 4 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 2. "CH3_IntStat,Channel 3 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 1. "CH2_IntStat,Channel 2 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 0. "CH1_IntStat,Channel 1 Interrupt Status Bit." "0,1"
wgroup.quad 0x38++0x7
line.quad 0x0 "DMAC_COMMONREG_INTCLEARREG,Writing 1 to specific field clears the corresponding field in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)."
hexmask.quad 0x0 21.--63. 1. "RSVD_DMAC_COMMONREG_INTCLEARREG_63to21,DMAC Common Register Interrupt Clear Register (bits 63to21) Reserved bits - Read Only"
newline
bitfld.quad 0x0 20. "Clear_MXIF2_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 19. "Clear_MXIF2_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 18. "Clear_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 17. "Clear_MXIF2_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 16. "Clear_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 15. "Clear_MXIF2_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 14. "Clear_MXIF1_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 13. "Clear_MXIF1_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 12. "Clear_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 11. "Clear_MXIF1_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 10. "Clear_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 9. "Clear_MXIF1_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 8. "Clear_SLVIF_UndefinedReg_DEC_ERR_IntStat,Slave Interface Undefined register Decode Error Interrupt clear Bit." "0,1"
newline
bitfld.quad 0x0 7. "Clear_SLVIF_CommonReg_WRPARITY_ERR_IntStat,Slave Interface Common Register Write Parity Error Interrupt clear Bit." "0,1"
newline
bitfld.quad 0x0 4.--6. "RSVD_DMAC_COMMONREG_INTCLEARREG_6to4,DMAC Common Register Interrupt Clear Register (bits 6to4) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 3. "Clear_SLVIF_CommonReg_WrOnHold_ERR_IntStat,Slave Interface Common Register Write On Hold Error Interrupt clear Bit." "0,1"
newline
bitfld.quad 0x0 2. "Clear_SLVIF_CommonReg_RD2WO_ERR_IntStat,Slave Interface Common Register Read to Write only Error Interrupt clear Bit." "0,1"
newline
bitfld.quad 0x0 1. "Clear_SLVIF_CommonReg_WR2RO_ERR_IntStat,Slave Interface Common Register Write to Read only Error Interrupt clear Bit." "0,1"
newline
bitfld.quad 0x0 0. "Clear_SLVIF_CommonReg_DEC_ERR_IntStat,Slave Interface Common Register Decode Error Interrupt clear Bit." "0,1"
group.quad 0x40++0xF
line.quad 0x0 "DMAC_COMMONREG_INTSTATUS_ENABLEREG,Writing 1 to specific field enables the corresponding interrupt status generation in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)."
hexmask.quad 0x0 21.--63. 1. "RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_63to21,DMAC Common Register Interrupt Status Enable Register (bits 63to21) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 20. "Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 19. "Enable_MXIF2_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 18. "Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 17. "Enable_MXIF2_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 16. "Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 15. "Enable_MXIF2_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 14. "Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 13. "Enable_MXIF1_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 12. "Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 11. "Enable_MXIF1_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 10. "Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 9. "Enable_MXIF1_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
bitfld.quad 0x0 8. "Enable_SLVIF_UndefinedReg_DEC_ERR_IntStat,Slave Interface Undefined register Decode Error Interrupt Status enable Bit." "0,1"
newline
rbitfld.quad 0x0 7. "Enable_SLVIF_CommonReg_WRPARITY_ERR_IntStat,Slave Interface Common Register Write Parity Error Interrupt Status Enable Bit." "0,1"
newline
rbitfld.quad 0x0 4.--6. "RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_6to4,DMAC Common Register Interrupt Status Enable Register (bits 6to4) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 3. "Enable_SLVIF_CommonReg_WrOnHold_ERR_IntStat,Slave Interface Common Register Write On Hold Error Interrupt Status Enable Bit." "0,1"
newline
bitfld.quad 0x0 2. "Enable_SLVIF_CommonReg_RD2WO_ERR_IntStat,Slave Interface Common Register Read to Write only Error Interrupt Status Enable Bit." "0,1"
newline
bitfld.quad 0x0 1. "Enable_SLVIF_CommonReg_WR2RO_ERR_IntStat,Slave Interface Common Register Write to Read only Error Interrupt Status Enable Bit." "0,1"
newline
bitfld.quad 0x0 0. "Enable_SLVIF_CommonReg_DEC_ERR_IntStat,Slave Interface Common Register Decode Error Interrupt Status Enable Bit." "0,1"
line.quad 0x8 "DMAC_COMMONREG_INTSIGNAL_ENABLEREG,Writing 1 to specific field will propagate the corresponding interrupt status in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg) to generate an port level interrupt."
hexmask.quad 0x8 21.--63. 1. "RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_63to21,DMAC Common Register Interrupt Signal Enable Register (bits 63to21) Reserved bits - Read Only"
newline
rbitfld.quad 0x8 20. "Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 2 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 19. "Enable_MXIF2_BCH_EccPROT_CorrERR_IntSignal,AXI Master Interface 2 Write Response Channel ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 18. "Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 17. "Enable_MXIF2_RCH1_EccPROT_CorrERR_IntSignal,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 16. "Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 2 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 15. "Enable_MXIF2_RCH0_EccPROT_CorrERR_IntSignal,AXI Master Interface 2 Read Channel (Data) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 14. "Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 1 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 13. "Enable_MXIF1_BCH_EccPROT_CorrERR_IntSignal,AXI Master Interface 1 Write Response Channel ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 12. "Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 11. "Enable_MXIF1_RCH1_EccPROT_CorrERR_IntSignal,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 10. "Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 1 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x8 9. "Enable_MXIF1_RCH0_EccPROT_CorrERR_IntSignal,AXI Master Interface 1 Read Channel (Data) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
bitfld.quad 0x8 8. "Enable_SLVIF_UndefinedReg_DEC_ERR_IntSignal,Slave Interface Undefined register Decode Error Interrupt Signal Enable Bit." "0,1"
newline
rbitfld.quad 0x8 7. "Enable_SLVIF_CommonReg_WRPARITY_ERR_IntSignal,Slave Interface Write Parity Error Interrupt Signal Enable Bit." "0,1"
newline
rbitfld.quad 0x8 4.--6. "RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_6to4,DMAC Common Register Interrupt Signal Enable Register (bits 6to4) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x8 3. "Enable_SLVIF_CommonReg_WrOnHold_ERR_IntSignal,Slave Interface Common Register Write On Hold Error Interrupt Signal Enable Bit." "0,1"
newline
bitfld.quad 0x8 2. "Enable_SLVIF_CommonReg_RD2WO_ERR_IntSignal,Slave Interface Common Register Read to Write only Error Interrupt Signal Enable Bit." "0,1"
newline
bitfld.quad 0x8 1. "Enable_SLVIF_CommonReg_WR2RO_ERR_IntSignal,Slave Interface Common Register Write to Read only Error Interrupt Signal Enable Bit." "0,1"
newline
bitfld.quad 0x8 0. "Enable_SLVIF_CommonReg_DEC_ERR_IntSignal,Slave Interface Common Register Decode Error Interrupt Signal Enable Bit." "0,1"
rgroup.quad 0x50++0x7
line.quad 0x0 "DMAC_COMMONREG_INTSTATUSREG,This Register captures Slave interface access errors."
hexmask.quad 0x0 21.--63. 1. "RSVD_DMAC_COMMONREG_INTSTATUSREG_63to21,DMAC Common Register Interrupt Signal Enable Register (bits 63to21) Reserved bits - Read Only"
newline
bitfld.quad 0x0 20. "MXIF2_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 2 Write Response Channel..,1: AXI Master 2 Write Response Channel.."
newline
bitfld.quad 0x0 19. "MXIF2_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 2 Write Response Channel..,1: AXI Master 2 Write Response Channel Correctable.."
newline
bitfld.quad 0x0 18. "MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 2 Read Channel Control signals..,1: AXI Master 2 Read Channel Control signals.."
newline
bitfld.quad 0x0 17. "MXIF2_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 2 Read Channel Control signlas..,1: AXI Master 2 Read Channel Control signals.."
newline
bitfld.quad 0x0 16. "MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 2 Read Channel Data related..,1: AXI Master 2 Read Channel Data related.."
newline
bitfld.quad 0x0 15. "MXIF2_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 2 Read Channel Data related..,1: AXI Master 2 Read Channel Data related.."
newline
bitfld.quad 0x0 14. "MXIF1_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 1 Write Response Channel..,1: AXI Master 1 Write Response Channel.."
newline
bitfld.quad 0x0 13. "MXIF1_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 1 Write Response Channel..,1: AXI Master 1 Write Response Channel Correctable.."
newline
bitfld.quad 0x0 12. "MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 1 Read Channel Control signals..,1: AXI Master 1 Read Channel Control signals.."
newline
bitfld.quad 0x0 11. "MXIF1_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 1 Read Channel Control signlas..,1: AXI Master 1 Read Channel Control signals.."
newline
bitfld.quad 0x0 10. "MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 1 Read Channel Data related..,1: AXI Master 1 Read Channel Data related.."
newline
bitfld.quad 0x0 9. "MXIF1_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 1 Read Channel Data related..,1: AXI Master 1 Read Channel Data related.."
newline
bitfld.quad 0x0 8. "SLVIF_UndefinedReg_DEC_ERR_IntStat,Slave Interface Undefined register Decode Error Interrupt Signal Enable Bit." "0: No Slave Interface Decode Errors,1: Slave Interface Decode Error detected"
newline
bitfld.quad 0x0 7. "SLVIF_CommonReg_WRPARITY_ERR_IntStat,Slave Interface Common Register Write Parity Error Interrupt Status Bit." "0: No Common Register Space Write Parity Error,1: Common Register Space Write Parity Error detected"
newline
bitfld.quad 0x0 4.--6. "RSVD_DMAC_COMMONREG_INTSTATUSREG_6to4,DMAC Common Register Interrupt Status Register (bits 6to4) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 3. "SLVIF_CommonReg_WrOnHold_ERR_IntStat,Slave Interface Common Register Write On Hold Error Interrupt Status Bit." "0: No Slave Interface Common Register Write On Hold..,1: Slave Interface Common Register Write On Hold.."
newline
bitfld.quad 0x0 2. "SLVIF_CommonReg_RD2WO_ERR_IntStat,Slave Interface Common Register Read to Write only Error Interrupt Status bit." "0: No Slave Interface Read to Write Only Errors,1: Slave Interface Read to Write Only Error detected"
newline
bitfld.quad 0x0 1. "SLVIF_CommonReg_WR2RO_ERR_IntStat,Slave Interface Common Register Write to Read Only Error Interrupt Status bit." "0: No Slave Interface Write to Read Only Errors,1: Slave Interface Write to Read Only Error detected"
newline
bitfld.quad 0x0 0. "SLVIF_CommonReg_DEC_ERR_IntStat,Slave Interface Common Register Decode Error Interrupt Status Bit." "0: No Slave Interface Decode Errors,1: Slave Interface Decode Error detected"
group.quad 0x58++0xF
line.quad 0x0 "DMAC_RESETREG,This register is used to initiate the Software Reset to DW_axi_dmac."
hexmask.quad 0x0 1.--63. 1. "RSVD_DMAC_ResetReg_1to63,DMAC_ResetReg (bits 1to63) Reserved bits - Read Only"
newline
bitfld.quad 0x0 0. "DMAC_RST,DMAC Reset Request bit" "0,1"
line.quad 0x8 "DMAC_LOWPOWER_CFGREG,This register contains the fields that configures the Context Sensitive Low Power feature. This register should be programmed prior to enabling the channel."
hexmask.quad.byte 0x8 56.--63. 1. "RSVD_DMAC_LOWPOWER_CFGREG_63to56,DMAC_LOWPOWER_CFGREG (bits 56to63) Reserved bits - Read Only"
newline
hexmask.quad.byte 0x8 48.--55. 1. "MXIF_LPDLY,Defines the load value to be programmed into the AXI Master Interface low power delay counter."
newline
hexmask.quad.byte 0x8 40.--47. 1. "SBIU_LPDLY,Defines the load value to be programmed into the SBIU low power delay counter."
newline
hexmask.quad.byte 0x8 32.--39. 1. "GLCH_LPDLY,Defines the load value to be programmed into the Global and DMA Channel low power delay counter."
newline
hexmask.quad.long 0x8 4.--31. 1. "RSVD_DMAC_LOWPOWER_CFGREG_31to4,DMAC_LOWPOWER_CFGREG (bits 4to31) Reserved bits - Read Only"
newline
bitfld.quad 0x8 3. "MXIF_CSLP_EN,AXI Master Interface Context Sensitive Low Power feature enable." "0,1"
newline
bitfld.quad 0x8 2. "SBIU_CSLP_EN,SBIU Context Sensitive Low Power feature enable." "0,1"
newline
bitfld.quad 0x8 1. "CHNL_CSLP_EN,DMA Channel Context Sensitive Low Power feature enable." "0,1"
newline
bitfld.quad 0x8 0. "GBL_CSLP_EN,Global Context Sensitive Low Power feature enable." "0,1"
group.quad 0x100++0x2F
line.quad 0x0 "CH1_SAR,The starting source address is programmed by software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While"
hexmask.quad 0x0 0.--63. 1. "SAR,Current Source Address of DMA transfer."
line.quad 0x8 "CH1_DAR,The starting destination address is programmed by the software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer."
hexmask.quad 0x8 0.--63. 1. "DAR,Current Destination Address of DMA transfer."
line.quad 0x10 "CH1_BLOCK_TS,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size."
hexmask.quad 0x10 22.--63. 1. "RSVD_DMAC_CHx_BLOCK_TSREG_63to22,DMAC Channelx Block Transfer Size Register (bits 63to22) Reserved bits - Read Only"
newline
hexmask.quad.tbyte 0x10 0.--21. 1. "BLOCK_TS,Block Transfer Size."
line.quad 0x18 "CH1_CTL,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.."
bitfld.quad 0x18 63. "SHADOWREG_OR_LLI_VALID,Shadow Register content/Linked List Item valid." "0: Shadow Register content/LLI is invalid,1: Last Shadow Register/LLI is valid"
newline
bitfld.quad 0x18 62. "SHADOWREG_OR_LLI_LAST,Last Shadow Register/Linked List Item." "0: Not last Shadow Register/LLI,1: Last Shadow Register/LLI"
newline
rbitfld.quad 0x18 59.--61. "RSVD_DMAC_CHx_CTL_59to61,DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 58. "IOC_BlkTfr,Interrupt On completion of Block Transfer" "0,1"
newline
rbitfld.quad 0x18 57. "DST_STAT_EN,Destination Status Enable" "0,1"
newline
rbitfld.quad 0x18 56. "SRC_STAT_EN,Source Status Enable" "0,1"
newline
hexmask.quad.byte 0x18 48.--55. 1. "AWLEN,Destination Burst Length"
newline
bitfld.quad 0x18 47. "AWLEN_EN,Destination Burst Length Enable" "0,1"
newline
hexmask.quad.byte 0x18 39.--46. 1. "ARLEN,Source Burst Length"
newline
bitfld.quad 0x18 38. "ARLEN_EN,Source Burst Length Enable" "0,1"
newline
bitfld.quad 0x18 35.--37. "AW_PROT,AXI 'aw_prot' signal" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 32.--34. "AR_PROT,AXI 'ar_prot' signal" "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x18 31. "RSVD_DMAC_CHx_CTL_31,DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 30. "NonPosted_LastWrite_En,Non Posted Last Write Enable" "0: Posted writes may be used throughout the block..,1: Posted writes may be used till the end of the.."
newline
hexmask.quad.byte 0x18 26.--29. 1. "AW_CACHE,AXI 'aw_cache' signal"
newline
hexmask.quad.byte 0x18 22.--25. 1. "AR_CACHE,AXI 'ar_cache' signal"
newline
hexmask.quad.byte 0x18 18.--21. 1. "DST_MSIZE,Destination Burst Transaction Length."
newline
hexmask.quad.byte 0x18 14.--17. 1. "SRC_MSIZE,Source Burst Transaction Length."
newline
bitfld.quad 0x18 11.--13. "DST_TR_WIDTH,Destination Transfer Width." "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 8.--10. "SRC_TR_WIDTH,Source Transfer Width." "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x18 7. "RSVD_DMAC_CHx_CTL_7,DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 6. "DINC,Destination Address Increment." "0: Increment,1: No Change"
newline
rbitfld.quad 0x18 5. "RSVD_DMAC_CHx_CTL_5,DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 4. "SINC,Source Address Increment." "0: Increment,1: No Change"
newline
rbitfld.quad 0x18 3. "RSVD_DMAC_CHx_CTL_3,DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only" "0,1"
newline
rbitfld.quad 0x18 2. "DMS,Destination Master Select." "0: AXI master 1,1: AXI Master 2"
newline
rbitfld.quad 0x18 1. "RSVD_DMAC_CHx_CTL_1,DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only" "0,1"
newline
rbitfld.quad 0x18 0. "SMS,Source Master Select." "0: AXI master 1,1: AXI Master 2"
line.quad 0x20 "CH1_CFG2,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel."
rbitfld.quad 0x20 63. "RSVD_DMAC_CHx_CFG_63,DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only" "0,1"
newline
hexmask.quad.byte 0x20 59.--62. 1. "DST_OSR_LMT,Destination Outstanding Request Limit"
newline
hexmask.quad.byte 0x20 55.--58. 1. "SRC_OSR_LMT,Source Outstanding Request Limit"
newline
bitfld.quad 0x20 53.--54. "LOCK_CH_L,Channel Lock Level" "0: Over complete DMA transfer,1: Over DMA block transfer,?,?"
newline
bitfld.quad 0x20 52. "LOCK_CH,Channel Lock bit" "0,1"
newline
hexmask.quad.byte 0x20 47.--51. 1. "CH_PRIOR,Channel Priority"
newline
hexmask.quad.byte 0x20 39.--46. 1. "RSVD_DMAC_CHx_CFG_39to46,DMAC Channelx Transfer Configuration Register (bits 39to46) Reserved bits - Read Only"
newline
rbitfld.quad 0x20 38. "DST_HWHS_POL,Destination Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
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rbitfld.quad 0x20 37. "SRC_HWHS_POL,Source Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
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bitfld.quad 0x20 36. "HS_SEL_DST,Destination Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
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bitfld.quad 0x20 35. "HS_SEL_SRC,Source Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
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bitfld.quad 0x20 32.--34. "TT_FC,Transfer Type and Flow Control." "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x20 29.--31. "RSVD_DMAC_CHx_CFG_29to31,DMAC Channelx Transfer Configuration Register (bits 29to31) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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hexmask.quad.byte 0x20 25.--28. 1. "WR_UID,Defines the number of AXI Unique ID's supported for the AXI Write Channel. The value programmed must be less than or equal to DMAX_CH(x)_WR_UID. Otherwise  it is limited by the value DMAX_CH(x)_WR_UID."
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rbitfld.quad 0x20 22.--24. "RSVD_DMAC_CHx_CFG_22to24,DMAC Channelx Transfer Configuration Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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hexmask.quad.byte 0x20 18.--21. 1. "RD_UID,Defines the number of AXI Unique ID's supported for the AXI Read Channel. The value programmed must be less than or equal to DMAX_CH(x)_RD_UID. Otherwise  it is limited by the value DMAX_CH(x)_RD_UID."
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rbitfld.quad 0x20 17. "RSVD_DMAC_CHx_CFG_17,DMAC Channelx Transfer Configuration Register (bit 17) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 11.--16. 1. "DST_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0;"
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rbitfld.quad 0x20 10. "RSVD_DMAC_CHx_CFG_10,DMAC Channelx Transfer Configuration Register (bit 10) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 4.--9. 1. "SRC_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise "
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rbitfld.quad 0x20 2.--3. "DST_MULTBLK_TYPE,Destination Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
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rbitfld.quad 0x20 0.--1. "SRC_MULTBLK_TYPE,Source Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
line.quad 0x28 "CH1_LLP,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the"
hexmask.quad 0x28 6.--63. 1. "LOC,Starting Address Memory of LLI block"
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hexmask.quad.byte 0x28 1.--5. 1. "RSVD_DMAC_CHx_LLP_1to5,DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only"
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rbitfld.quad 0x28 0. "LMS,LLI master Select" "0: AXI Master 1,1: AXI Master 2"
rgroup.quad 0x130++0x7
line.quad 0x0 "CH1_STATUSREG,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx."
hexmask.quad.tbyte 0x0 47.--63. 1. "RSVD_DMAC_CHx_STATUSREG_47to63,DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 32.--46. 1. "DATA_LEFT_IN_FIFO,Data Left in FIFO."
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hexmask.quad.word 0x0 22.--31. 1. "RSVD_DMAC_CHx_STATUSREG_22to31,DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x0 0.--21. 1. "CMPLTD_BLK_TFR_SIZE,Completed Block Transfer Size."
group.quad 0x138++0xF
line.quad 0x0 "CH1_SWHSSRCREG,Channelx Software handshake Source Register."
hexmask.quad 0x0 6.--63. 1. "RSVD_DMAC_CHx_SWHSSRCREG_6to63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x0 5. "SWHS_LST_SRC_WE,Write Enable bit for Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 4. "SWHS_LST_SRC,Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 3. "SWHS_SGLREQ_SRC_WE,Write Enable bit for Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 2. "SWHS_SGLREQ_SRC,Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 1. "SWHS_REQ_SRC_WE,Write Enable bit for Software Handshake Request for Channel Source." "0,1"
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bitfld.quad 0x0 0. "SWHS_REQ_SRC,Software Handshake Request for Channel Source." "0,1"
line.quad 0x8 "CH1_SWHSDSTREG,Channelx Software handshake Destination Register."
hexmask.quad 0x8 6.--63. 1. "RSVD_DMAC_CHx_SWHSDSTREG_6to63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x8 5. "SWHS_LST_DST_WE,Write Enable bit for Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 4. "SWHS_LST_DST,Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 3. "SWHS_SGLREQ_DST_WE,Write Enable bit for Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 2. "SWHS_SGLREQ_DST,Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 1. "SWHS_REQ_DST_WE,Write Enable bit for Software Handshake Request for Channel Destination." "0,1"
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bitfld.quad 0x8 0. "SWHS_REQ_DST,Software Handshake Request for Channel Destination." "0,1"
wgroup.quad 0x148++0x7
line.quad 0x0 "CH1_BLK_TFR_RESUMEREQREG,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer."
hexmask.quad 0x0 1.--63. 1. "RSVD_DMAC_CHx_BLK_TFR_RESUMEREQREG_1to63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only"
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bitfld.quad 0x0 0. "BLK_TFR_RESUMEREQ,Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer." "0,1"
group.quad 0x150++0xF
line.quad 0x0 "CH1_AXI_IDREG,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad.long 0x0 32.--63. 1. "RSVD_DMAC_CHx_AXI_IDREG_32to63,DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 20.--31. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm32to63,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 16.--19. 1. "AXI_WRITE_ID_SUFFIX,AXI Write ID Suffix."
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hexmask.quad.word 0x0 4.--15. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm1to31,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 0.--3. 1. "AXI_READ_ID_SUFFIX,AXI Read ID Suffix"
line.quad 0x8 "CH1_AXI_QOSREG,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad 0x8 8.--63. 1. "RSVD_DMAC_CHx_AXI_QOSREG_8to63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only"
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hexmask.quad.byte 0x8 4.--7. 1. "AXI_ARQOS,AXI ARQOS."
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hexmask.quad.byte 0x8 0.--3. 1. "AXI_AWQOS,AXI AWQOS."
group.quad 0x180++0x7
line.quad 0x0 "CH1_INTSTATUS_ENABLEREG,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH1_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63,DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only"
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rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation Channel x Channel Memory.."
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rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation of Channel x Channel.."
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bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntStat,Channel Aborted Status Enable." "0: Disable the generation of Channel Aborted..,1: Enable the generation of Channel Aborted.."
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bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntStat,Channel Disabled Status Enable." "0: Disable the generation of Channel Disabled..,1: Enable the generation of Channel Disabled.."
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bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntStat,Channel Suspended Status Enable." "0: Disable the generation of Channel Suspended..,1: Enable the generation of Channel Suspended.."
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bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Status Enable." "0: Disable the generation of Channel Source..,1: Enable the generation of Channel Source.."
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bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Status Enable." "0: Disable the generation of Channel LOCK CLEARED..,1: Enable the generation of Channel LOCK CLEARED.."
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rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26,DMAC Channelx Interrupt Status Register (bit 26) Reserved bit - Read Only" "0,1"
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rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24,DMAC Channelx Interrupt Status Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Status Enable." "0: Disable the generation of Shadow Register Write..,1: Enable the generation of Shadow register Write.."
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bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Status Enable." "0: Disable the generation of Slave Interface Read..,1: Enable the generation of Slave Interface Read to.."
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bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Status Enable." "0: Disable the generation of Slave Interface Decode..,1: Enable the generation of Slave Interface Decode.."
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rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Status Enable." "0: Disable the generation of Slave Interface Multi..,1: Enable the generation of Slave Interface Multi.."
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bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Status Enable." "0: Disable the generation of Shadow Register or LLI..,1: Enable the generation of Shadow Register or LLI.."
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bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Status Enable." "0: Disable the generation of LLI WRITE Slave Error..,1: Enable the generation of LLI WRITE Slave Error.."
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bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Status Enable." "0: Disable the generation of LLI Read Slave Error..,1: Enable the generation of LLI Read Slave Error.."
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bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Status Enable." "0: Disable the generation of LLI WRITE Decode Error..,1: Enable the generation of LLI WRITE Decode Error.."
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bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Status Enable." "0: Disable the generation of LLI Read Decode Error..,1: Enable the generation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntStat,Destination Slave Error Status Enable." "0: Disable the generation of Destination Slave..,1: Enable the generation of Destination Slave Error.."
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bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntStat,Source Slave Error Status Enable." "0: Disable the generation of Source Slave Error..,1: Enable the generation of Source Slave Error.."
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bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntStat,Destination Decode Error Status Enable." "0: Disable the generation of Destination Decode..,1: Enable the generation of Destination Decode.."
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bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntStat,Source Decode Error Status Enable." "0: Disable the generation of Source Decode Error..,1: Enable the generation of Source Decode Error.."
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bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntStat,Destination Transaction Completed Status Enable." "0: Disable the generation of Destination..,1: Enable the generation of Destination Transaction.."
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bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntStat,Source Transaction Completed Status Enable." "0: Disable the generation of Source Transaction..,1: Enable the generation of Source Transaction.."
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rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Status Enable." "0: Disable the generation of DMA Transfer Done..,1: Enable the generation of DMA Transfer Done.."
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bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Status Enable." "0: Disable the generation of Block Transfer Done..,1: Enable the generation of Block Transfer Done.."
rgroup.quad 0x188++0x7
line.quad 0x0 "CH1_INTSTATUS,Channelx Interrupt Status Register captures the Channelx specific interrupts"
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUSREG_36to63,DMAC Channelx Specific Interrupt Register (bits 36to63) Reserved bits - Read Only"
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bitfld.quad 0x0 35. "ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x UID Memory Interface Uncorrectable..,1: Channel x UID Memory Interface Uncorrectable.."
newline
bitfld.quad 0x0 34. "ECC_PROT_UIDMem_CorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x UID Memory Interface correctable..,1: Channel x UID Memory Interface correctable Error.."
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bitfld.quad 0x0 33. "ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface Uncorrectable..,1: Channel x FIFO Memory Interface Uncorrectable.."
newline
bitfld.quad 0x0 32. "ECC_PROT_CHMem_CorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface correctable..,1: Channel x FIFO Memory Interface correctable.."
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bitfld.quad 0x0 31. "CH_ABORTED_IntStat,Channel Aborted." "0: Channel is not aborted,1: Channel is aborted"
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bitfld.quad 0x0 30. "CH_DISABLED_IntStat,Channel Disabled." "0: Channel is not disabled,1: Channel is disabled"
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bitfld.quad 0x0 29. "CH_SUSPENDED_IntStat,Channel Suspended." "0: Channel is not suspended,1: Channel is suspended"
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bitfld.quad 0x0 28. "CH_SRC_SUSPENDED_IntStat,Channel Source Suspended." "0: Channel source is not suspended,1: Channel Source is suspended"
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bitfld.quad 0x0 27. "CH_LOCK_CLEARED_IntStat,Channel Lock Cleared." "0: Channel locking is not cleared,1: Channel locking is cleared"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUSREG_26,DMAC Channelx Specific Interrupt Register (bit 26) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 25. "SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error." "0: No Slave Interface Write Parity Errors,1: Slave Interface Write Parity Error detected"
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bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUSREG_22to24,DMAC Channelx Specific Interrupt Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error." "0: No Slave Interface Write On Hold Errors,1: Slave Interface Write On Hold Error detected"
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bitfld.quad 0x0 20. "SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error." "0: No Slave Interface Shadow Register Write On..,1: Slave Interface Shadow Register Write On Valid.."
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bitfld.quad 0x0 19. "SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error." "0: No Slave Interface Write On Channel Enabled Errors,1: Slave Interface Write On Channel Enabled Error.."
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bitfld.quad 0x0 18. "SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error." "0: No Slave Interface Read to Write Only Errors,1: Slave Interface Read to Write Only Error detected"
newline
bitfld.quad 0x0 17. "SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error." "0: No Slave Interface Write to Read Only Errors,1: Slave Interface Write to Read Only Error detected"
newline
bitfld.quad 0x0 16. "SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error." "0: No Slave Interface Decode errors,1: Slave Interface Decode Error detected"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUSREG_15,DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error." "0: No Multi-block transfer type Errors,1: Multi-block transfer type Error detected"
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bitfld.quad 0x0 13. "SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error." "0: No Shadow Register / LLI Invalid errors,1: Shadow Register / LLI Invalid error detected"
newline
bitfld.quad 0x0 12. "LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error." "0: No LLI write Slave Errors,1: LLI Write SLAVE Error detected"
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bitfld.quad 0x0 11. "LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error." "0: No LLI Read Slave Errors,1: LLI read Slave Error detected"
newline
bitfld.quad 0x0 10. "LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error." "0: NO LLI Write Decode Errors,1: LLI write Decode Error detected"
newline
bitfld.quad 0x0 9. "LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error." "0: NO LLI Read Decode Errors,1: LLI Read Decode Error detected"
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bitfld.quad 0x0 8. "DST_SLV_ERR_IntStat,Destination Slave Error." "0: No Destination Slave Errors,1: Destination Slave Errors Detected"
newline
bitfld.quad 0x0 7. "SRC_SLV_ERR_IntStat,Source Slave Error." "0: No Source Slave Errors,1: Source Slave Error Detected"
newline
bitfld.quad 0x0 6. "DST_DEC_ERR_IntStat,Destination Decode Error." "0: No destination Decode Errors,1: Destination Decode Error Detected"
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bitfld.quad 0x0 5. "SRC_DEC_ERR_IntStat,Source Decode Error." "0: No Source Decode Errors,1: Source Decode Error detected"
newline
bitfld.quad 0x0 4. "DST_TRANSCOMP_IntStat,Destination Transaction Completed." "0,1"
newline
bitfld.quad 0x0 3. "SRC_TRANSCOMP_IntStat,Source Transaction Completed." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUSREG_2,DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "DMA_TFR_DONE_IntStat,DMA Transfer Done." "0: DMA Transfer not completed,1: DMA Transfer Completed"
newline
bitfld.quad 0x0 0. "BLOCK_TFR_DONE_IntStat,Block Transfer Done." "0: Block Transfer not completed,1: Block Transfer completed"
group.quad 0x190++0x7
line.quad 0x0 "CH1_INTSIGNAL_ENABLEREG,This register contains fields that are used to enable the generation of port level interrupt at the channel level."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63,DMAC Channelx Interrupt Signal Enable Register (bits 36to63) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntSignal,Channel Aborted Signal Enable." "0: Disable the propagation of Channel Aborted..,1: Enable the propagation of Channel Aborted.."
newline
bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntSignal,Channel Disabled Signal Enable." "0: Disable the propagation of Channel Disabled..,1: Enable the propagation of Channel Disabled.."
newline
bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntSignal,Channel Suspended Signal Enable." "0: Disable the propagation of Channel Suspended..,1: Enable the propagation of Channel Suspended.."
newline
bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntSignal,Channel Source Suspended Signal Enable." "0: Disable the propagation of Channel Source..,1: Enable the propagation of Channel Source.."
newline
bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntSignal,Channel Lock Cleared Signal Enable." "0: Disable the propagation of Channel Lock Cleared..,1: Enable the propagation of Channel Lock Cleared.."
newline
rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26,DMAC Channelx Interrupt Signal Enable Register (bit 26) Reserved bit - Read Only" "0,1"
newline
rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntSignal,Slave Interface Write Parity Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24,DMAC Channelx Interrupt Signal Enable Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntSignal,Slave Interface Write On Hold Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
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bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal,Shadow Register Write On Valid Error Signal Enable." "0: Disable the propagation of Shadow Register Write..,1: Enable the propagation of Shadow register Write.."
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bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntSignal,Slave Interface Write On Channel Enabled Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
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bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntSignal,Slave Interface Read to write Only Error Signal Enable." "0: Disable the propagation of Slave Interface Read..,1: Enable the propagation of Slave Interface Read.."
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bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntSignal,Slave Interface Write to Read Only Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
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bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntSignal,Slave Interface Decode Error Signal Enable." "0: Disable the propagation of Slave Interface..,1: Enable the propagation of Slave Interface Decode.."
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rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,Slave Interface Multi Block type Error Signal Enable." "0: Disable the propagation of Slave Interface Multi..,1: Enable the propagation of Slave Interface Multi.."
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bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,Shadow register or LLI Invalid Error Signal Enable." "0: Disable the propagation of Shadow Register or..,1: Enable the propagation of Shadow Register or LLI.."
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bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntSignal,LLI WRITE Slave Error Signal Enable." "0: Disable the propagation of LLI WRITE Slave Error..,1: Enable the propagation of LLI WRITE Slave Error.."
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bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntSignal,LLI Read Slave Error Signal Enable." "0: Disable the propagation of LLI Read Slave Error..,1: Enable the propagation of LLI Read Slave Error.."
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bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntSignal,LLI WRITE Decode Error Signal Enable." "0: Disable the propagation of LLI WRITE Decode..,1: Enable the propagation of LLI WRITE Decode Error.."
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bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntSignal,LLI Read Decode Error Signal Enable." "0: Disable the propagation of LLI Read Decode Error..,1: Enable the propagation of LLI Read Decode Error.."
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bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntSignal,Destination Slave Error Signal Enable." "0: Disable the propagation of Destination Slave..,1: Enable the propagation of Destination Slave.."
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bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntSignal,Source Slave Error Signal Enable." "0: Disable the propagation of Source Slave Error..,1: Enable the propagation of Source Slave Error.."
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bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntSignal,Destination Decode Error Signal Enable." "0: Disable the propagation of Destination Decode..,1: Enable the propagation of Destination Decode.."
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bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntSignal,Source Decode Error Signal Enable." "0: Disable the propagation of Source Decode Error..,1: Enable the propagation of Source Decode Error.."
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bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntSignal,Destination Transaction Completed Signal Enable." "0: Disable the propagation of Destination..,1: Enable the propagation of Destination.."
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bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntSignal,Source Transaction Completed Signal Enable." "0: Disable the propagation of Source Transaction..,1: Enable the propagation of Source Transaction.."
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rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntSignal,DMA Transfer Done Interrupt Signal Enable." "0: Disable the propagation of DMA Transfer Done..,1: Enable the propagation of DMA Transfer Done.."
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bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntSignal,Block Transfer Done Interrupt Signal Enable." "0: Disable the propagation of Block Transfer Done..,1: Enable the propagation of Block Transfer Done.."
wgroup.quad 0x198++0x7
line.quad 0x0 "CH1_INTCLEARREG,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTCLEARREG_36to63,DMAC Channelx Interrupt Clear Register (bits 36to63) Reserved bit - Read Only"
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bitfld.quad 0x0 35. "Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat,ECC Protection Uncorrectable UID Memory Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 34. "Clear_ECC_PROT_UIDMem_CorrERR_IntStat,ECC Protection Correctable UID Memory Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 33. "Clear_ECC_PROT_CHMem_UnCorrERR_IntStat,ECC Protection Uncorrectable Channel Memory Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 32. "Clear_ECC_PROT_CHMem_CorrERR_IntStat,ECC Protection Correctable Channel Memory Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 31. "Clear_CH_ABORTED_IntStat,Channel Aborted Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 30. "Clear_CH_DISABLED_IntStat,Channel Disabled Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 29. "Clear_CH_SUSPENDED_IntStat,Channel Suspended Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 28. "Clear_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 27. "Clear_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTCLEARREG_26,DMAC Channelx Interrupt Clear Register (bit 26) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 25. "Clear_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTCLEARREG_22to24,DMAC Channelx Interrupt Clear Register (bits 22to24) Reserved bit - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "Clear_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 20. "Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 19. "Clear_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 18. "Clear_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 17. "Clear_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 16. "Clear_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTCLEARREG_15,DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 13. "Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 12. "Clear_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 11. "Clear_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 10. "Clear_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 9. "Clear_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 8. "Clear_DST_SLV_ERR_IntStat,Destination Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 7. "Clear_SRC_SLV_ERR_IntStat,Source Slave Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 6. "Clear_DST_DEC_ERR_IntStat,Destination Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 5. "Clear_SRC_DEC_ERR_IntStat,Source Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 4. "Clear_DST_TRANSCOMP_IntStat,Destination Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 3. "Clear_SRC_TRANSCOMP_IntStat,Source Transaction Completed Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTCLEARREG_2,DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 1. "Clear_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 0. "Clear_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Clear Bit." "0,1"
group.quad 0x200++0x2F
line.quad 0x0 "CH2_SAR,The starting source address is programmed by software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While"
hexmask.quad 0x0 0.--63. 1. "SAR,Current Source Address of DMA transfer."
line.quad 0x8 "CH2_DAR,The starting destination address is programmed by the software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer."
hexmask.quad 0x8 0.--63. 1. "DAR,Current Destination Address of DMA transfer."
line.quad 0x10 "CH2_BLOCK_TS,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size."
hexmask.quad 0x10 22.--63. 1. "RSVD_DMAC_CHx_BLOCK_TSREG_63to22,DMAC Channelx Block Transfer Size Register (bits 63to22) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x10 0.--21. 1. "BLOCK_TS,Block Transfer Size."
line.quad 0x18 "CH2_CTL,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.."
bitfld.quad 0x18 63. "SHADOWREG_OR_LLI_VALID,Shadow Register content/Linked List Item valid." "0: Shadow Register content/LLI is invalid,1: Last Shadow Register/LLI is valid"
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bitfld.quad 0x18 62. "SHADOWREG_OR_LLI_LAST,Last Shadow Register/Linked List Item." "0: Not last Shadow Register/LLI,1: Last Shadow Register/LLI"
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rbitfld.quad 0x18 59.--61. "RSVD_DMAC_CHx_CTL_59to61,DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 58. "IOC_BlkTfr,Interrupt On completion of Block Transfer" "0,1"
newline
rbitfld.quad 0x18 57. "DST_STAT_EN,Destination Status Enable" "0,1"
newline
rbitfld.quad 0x18 56. "SRC_STAT_EN,Source Status Enable" "0,1"
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hexmask.quad.byte 0x18 48.--55. 1. "AWLEN,Destination Burst Length"
newline
bitfld.quad 0x18 47. "AWLEN_EN,Destination Burst Length Enable" "0,1"
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hexmask.quad.byte 0x18 39.--46. 1. "ARLEN,Source Burst Length"
newline
bitfld.quad 0x18 38. "ARLEN_EN,Source Burst Length Enable" "0,1"
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bitfld.quad 0x18 35.--37. "AW_PROT,AXI 'aw_prot' signal" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 32.--34. "AR_PROT,AXI 'ar_prot' signal" "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x18 31. "RSVD_DMAC_CHx_CTL_31,DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 30. "NonPosted_LastWrite_En,Non Posted Last Write Enable" "0: Posted writes may be used throughout the block..,1: Posted writes may be used till the end of the.."
newline
hexmask.quad.byte 0x18 26.--29. 1. "AW_CACHE,AXI 'aw_cache' signal"
newline
hexmask.quad.byte 0x18 22.--25. 1. "AR_CACHE,AXI 'ar_cache' signal"
newline
hexmask.quad.byte 0x18 18.--21. 1. "DST_MSIZE,Destination Burst Transaction Length."
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hexmask.quad.byte 0x18 14.--17. 1. "SRC_MSIZE,Source Burst Transaction Length."
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bitfld.quad 0x18 11.--13. "DST_TR_WIDTH,Destination Transfer Width." "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 8.--10. "SRC_TR_WIDTH,Source Transfer Width." "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x18 7. "RSVD_DMAC_CHx_CTL_7,DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 6. "DINC,Destination Address Increment." "0: Increment,1: No Change"
newline
rbitfld.quad 0x18 5. "RSVD_DMAC_CHx_CTL_5,DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 4. "SINC,Source Address Increment." "0: Increment,1: No Change"
newline
rbitfld.quad 0x18 3. "RSVD_DMAC_CHx_CTL_3,DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only" "0,1"
newline
rbitfld.quad 0x18 2. "DMS,Destination Master Select." "0: AXI master 1,1: AXI Master 2"
newline
rbitfld.quad 0x18 1. "RSVD_DMAC_CHx_CTL_1,DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only" "0,1"
newline
rbitfld.quad 0x18 0. "SMS,Source Master Select." "0: AXI master 1,1: AXI Master 2"
line.quad 0x20 "CH2_CFG2,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel."
rbitfld.quad 0x20 63. "RSVD_DMAC_CHx_CFG_63,DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 59.--62. 1. "DST_OSR_LMT,Destination Outstanding Request Limit"
newline
hexmask.quad.byte 0x20 55.--58. 1. "SRC_OSR_LMT,Source Outstanding Request Limit"
newline
bitfld.quad 0x20 53.--54. "LOCK_CH_L,Channel Lock Level" "0: Over complete DMA transfer,1: Over DMA block transfer,?,?"
newline
bitfld.quad 0x20 52. "LOCK_CH,Channel Lock bit" "0,1"
newline
hexmask.quad.byte 0x20 47.--51. 1. "CH_PRIOR,Channel Priority"
newline
hexmask.quad.byte 0x20 39.--46. 1. "RSVD_DMAC_CHx_CFG_39to46,DMAC Channelx Transfer Configuration Register (bits 39to46) Reserved bits - Read Only"
newline
rbitfld.quad 0x20 38. "DST_HWHS_POL,Destination Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
newline
rbitfld.quad 0x20 37. "SRC_HWHS_POL,Source Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
newline
bitfld.quad 0x20 36. "HS_SEL_DST,Destination Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
newline
bitfld.quad 0x20 35. "HS_SEL_SRC,Source Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
newline
bitfld.quad 0x20 32.--34. "TT_FC,Transfer Type and Flow Control." "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x20 29.--31. "RSVD_DMAC_CHx_CFG_29to31,DMAC Channelx Transfer Configuration Register (bits 29to31) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x20 25.--28. 1. "WR_UID,Defines the number of AXI Unique ID's supported for the AXI Write Channel. The value programmed must be less than or equal to DMAX_CH(x)_WR_UID. Otherwise  it is limited by the value DMAX_CH(x)_WR_UID."
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rbitfld.quad 0x20 22.--24. "RSVD_DMAC_CHx_CFG_22to24,DMAC Channelx Transfer Configuration Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x20 18.--21. 1. "RD_UID,Defines the number of AXI Unique ID's supported for the AXI Read Channel. The value programmed must be less than or equal to DMAX_CH(x)_RD_UID. Otherwise  it is limited by the value DMAX_CH(x)_RD_UID."
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rbitfld.quad 0x20 17. "RSVD_DMAC_CHx_CFG_17,DMAC Channelx Transfer Configuration Register (bit 17) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 11.--16. 1. "DST_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0;"
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rbitfld.quad 0x20 10. "RSVD_DMAC_CHx_CFG_10,DMAC Channelx Transfer Configuration Register (bit 10) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 4.--9. 1. "SRC_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise "
newline
rbitfld.quad 0x20 2.--3. "DST_MULTBLK_TYPE,Destination Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
newline
rbitfld.quad 0x20 0.--1. "SRC_MULTBLK_TYPE,Source Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
line.quad 0x28 "CH2_LLP,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the"
hexmask.quad 0x28 6.--63. 1. "LOC,Starting Address Memory of LLI block"
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hexmask.quad.byte 0x28 1.--5. 1. "RSVD_DMAC_CHx_LLP_1to5,DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only"
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rbitfld.quad 0x28 0. "LMS,LLI master Select" "0: AXI Master 1,1: AXI Master 2"
rgroup.quad 0x230++0x7
line.quad 0x0 "CH2_STATUSREG,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx."
hexmask.quad.tbyte 0x0 47.--63. 1. "RSVD_DMAC_CHx_STATUSREG_47to63,DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 32.--46. 1. "DATA_LEFT_IN_FIFO,Data Left in FIFO."
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hexmask.quad.word 0x0 22.--31. 1. "RSVD_DMAC_CHx_STATUSREG_22to31,DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x0 0.--21. 1. "CMPLTD_BLK_TFR_SIZE,Completed Block Transfer Size."
group.quad 0x238++0xF
line.quad 0x0 "CH2_SWHSSRCREG,Channelx Software handshake Source Register."
hexmask.quad 0x0 6.--63. 1. "RSVD_DMAC_CHx_SWHSSRCREG_6to63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x0 5. "SWHS_LST_SRC_WE,Write Enable bit for Software Handshake Last Request for Channel Source." "0,1"
newline
bitfld.quad 0x0 4. "SWHS_LST_SRC,Software Handshake Last Request for Channel Source." "0,1"
newline
bitfld.quad 0x0 3. "SWHS_SGLREQ_SRC_WE,Write Enable bit for Software Handshake Single Request for Channel Source." "0,1"
newline
bitfld.quad 0x0 2. "SWHS_SGLREQ_SRC,Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 1. "SWHS_REQ_SRC_WE,Write Enable bit for Software Handshake Request for Channel Source." "0,1"
newline
bitfld.quad 0x0 0. "SWHS_REQ_SRC,Software Handshake Request for Channel Source." "0,1"
line.quad 0x8 "CH2_SWHSDSTREG,Channelx Software handshake Destination Register."
hexmask.quad 0x8 6.--63. 1. "RSVD_DMAC_CHx_SWHSDSTREG_6to63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only"
newline
bitfld.quad 0x8 5. "SWHS_LST_DST_WE,Write Enable bit for Software Handshake Last Request for Channel Destination." "0,1"
newline
bitfld.quad 0x8 4. "SWHS_LST_DST,Software Handshake Last Request for Channel Destination." "0,1"
newline
bitfld.quad 0x8 3. "SWHS_SGLREQ_DST_WE,Write Enable bit for Software Handshake Single Request for Channel Destination." "0,1"
newline
bitfld.quad 0x8 2. "SWHS_SGLREQ_DST,Software Handshake Single Request for Channel Destination." "0,1"
newline
bitfld.quad 0x8 1. "SWHS_REQ_DST_WE,Write Enable bit for Software Handshake Request for Channel Destination." "0,1"
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bitfld.quad 0x8 0. "SWHS_REQ_DST,Software Handshake Request for Channel Destination." "0,1"
wgroup.quad 0x248++0x7
line.quad 0x0 "CH2_BLK_TFR_RESUMEREQREG,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer."
hexmask.quad 0x0 1.--63. 1. "RSVD_DMAC_CHx_BLK_TFR_RESUMEREQREG_1to63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only"
newline
bitfld.quad 0x0 0. "BLK_TFR_RESUMEREQ,Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer." "0,1"
group.quad 0x250++0xF
line.quad 0x0 "CH2_AXI_IDREG,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad.long 0x0 32.--63. 1. "RSVD_DMAC_CHx_AXI_IDREG_32to63,DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 20.--31. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm32to63,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 16.--19. 1. "AXI_WRITE_ID_SUFFIX,AXI Write ID Suffix."
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hexmask.quad.word 0x0 4.--15. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm1to31,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 0.--3. 1. "AXI_READ_ID_SUFFIX,AXI Read ID Suffix"
line.quad 0x8 "CH2_AXI_QOSREG,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad 0x8 8.--63. 1. "RSVD_DMAC_CHx_AXI_QOSREG_8to63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only"
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hexmask.quad.byte 0x8 4.--7. 1. "AXI_ARQOS,AXI ARQOS."
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hexmask.quad.byte 0x8 0.--3. 1. "AXI_AWQOS,AXI AWQOS."
group.quad 0x280++0x7
line.quad 0x0 "CH2_INTSTATUS_ENABLEREG,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH2_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63,DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only"
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rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation Channel x Channel Memory.."
newline
rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntStat,Channel Aborted Status Enable." "0: Disable the generation of Channel Aborted..,1: Enable the generation of Channel Aborted.."
newline
bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntStat,Channel Disabled Status Enable." "0: Disable the generation of Channel Disabled..,1: Enable the generation of Channel Disabled.."
newline
bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntStat,Channel Suspended Status Enable." "0: Disable the generation of Channel Suspended..,1: Enable the generation of Channel Suspended.."
newline
bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Status Enable." "0: Disable the generation of Channel Source..,1: Enable the generation of Channel Source.."
newline
bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Status Enable." "0: Disable the generation of Channel LOCK CLEARED..,1: Enable the generation of Channel LOCK CLEARED.."
newline
rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26,DMAC Channelx Interrupt Status Register (bit 26) Reserved bit - Read Only" "0,1"
newline
rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24,DMAC Channelx Interrupt Status Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Status Enable." "0: Disable the generation of Shadow Register Write..,1: Enable the generation of Shadow register Write.."
newline
bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Status Enable." "0: Disable the generation of Slave Interface Read..,1: Enable the generation of Slave Interface Read to.."
newline
bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Status Enable." "0: Disable the generation of Slave Interface Decode..,1: Enable the generation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Status Enable." "0: Disable the generation of Slave Interface Multi..,1: Enable the generation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Status Enable." "0: Disable the generation of Shadow Register or LLI..,1: Enable the generation of Shadow Register or LLI.."
newline
bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Status Enable." "0: Disable the generation of LLI WRITE Slave Error..,1: Enable the generation of LLI WRITE Slave Error.."
newline
bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Status Enable." "0: Disable the generation of LLI Read Slave Error..,1: Enable the generation of LLI Read Slave Error.."
newline
bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Status Enable." "0: Disable the generation of LLI WRITE Decode Error..,1: Enable the generation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Status Enable." "0: Disable the generation of LLI Read Decode Error..,1: Enable the generation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntStat,Destination Slave Error Status Enable." "0: Disable the generation of Destination Slave..,1: Enable the generation of Destination Slave Error.."
newline
bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntStat,Source Slave Error Status Enable." "0: Disable the generation of Source Slave Error..,1: Enable the generation of Source Slave Error.."
newline
bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntStat,Destination Decode Error Status Enable." "0: Disable the generation of Destination Decode..,1: Enable the generation of Destination Decode.."
newline
bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntStat,Source Decode Error Status Enable." "0: Disable the generation of Source Decode Error..,1: Enable the generation of Source Decode Error.."
newline
bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntStat,Destination Transaction Completed Status Enable." "0: Disable the generation of Destination..,1: Enable the generation of Destination Transaction.."
newline
bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntStat,Source Transaction Completed Status Enable." "0: Disable the generation of Source Transaction..,1: Enable the generation of Source Transaction.."
newline
rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Status Enable." "0: Disable the generation of DMA Transfer Done..,1: Enable the generation of DMA Transfer Done.."
newline
bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Status Enable." "0: Disable the generation of Block Transfer Done..,1: Enable the generation of Block Transfer Done.."
rgroup.quad 0x288++0x7
line.quad 0x0 "CH2_INTSTATUS,Channelx Interrupt Status Register captures the Channelx specific interrupts"
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUSREG_36to63,DMAC Channelx Specific Interrupt Register (bits 36to63) Reserved bits - Read Only"
newline
bitfld.quad 0x0 35. "ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x UID Memory Interface Uncorrectable..,1: Channel x UID Memory Interface Uncorrectable.."
newline
bitfld.quad 0x0 34. "ECC_PROT_UIDMem_CorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x UID Memory Interface correctable..,1: Channel x UID Memory Interface correctable Error.."
newline
bitfld.quad 0x0 33. "ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface Uncorrectable..,1: Channel x FIFO Memory Interface Uncorrectable.."
newline
bitfld.quad 0x0 32. "ECC_PROT_CHMem_CorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface correctable..,1: Channel x FIFO Memory Interface correctable.."
newline
bitfld.quad 0x0 31. "CH_ABORTED_IntStat,Channel Aborted." "0: Channel is not aborted,1: Channel is aborted"
newline
bitfld.quad 0x0 30. "CH_DISABLED_IntStat,Channel Disabled." "0: Channel is not disabled,1: Channel is disabled"
newline
bitfld.quad 0x0 29. "CH_SUSPENDED_IntStat,Channel Suspended." "0: Channel is not suspended,1: Channel is suspended"
newline
bitfld.quad 0x0 28. "CH_SRC_SUSPENDED_IntStat,Channel Source Suspended." "0: Channel source is not suspended,1: Channel Source is suspended"
newline
bitfld.quad 0x0 27. "CH_LOCK_CLEARED_IntStat,Channel Lock Cleared." "0: Channel locking is not cleared,1: Channel locking is cleared"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUSREG_26,DMAC Channelx Specific Interrupt Register (bit 26) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 25. "SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error." "0: No Slave Interface Write Parity Errors,1: Slave Interface Write Parity Error detected"
newline
bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUSREG_22to24,DMAC Channelx Specific Interrupt Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error." "0: No Slave Interface Write On Hold Errors,1: Slave Interface Write On Hold Error detected"
newline
bitfld.quad 0x0 20. "SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error." "0: No Slave Interface Shadow Register Write On..,1: Slave Interface Shadow Register Write On Valid.."
newline
bitfld.quad 0x0 19. "SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error." "0: No Slave Interface Write On Channel Enabled Errors,1: Slave Interface Write On Channel Enabled Error.."
newline
bitfld.quad 0x0 18. "SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error." "0: No Slave Interface Read to Write Only Errors,1: Slave Interface Read to Write Only Error detected"
newline
bitfld.quad 0x0 17. "SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error." "0: No Slave Interface Write to Read Only Errors,1: Slave Interface Write to Read Only Error detected"
newline
bitfld.quad 0x0 16. "SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error." "0: No Slave Interface Decode errors,1: Slave Interface Decode Error detected"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUSREG_15,DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error." "0: No Multi-block transfer type Errors,1: Multi-block transfer type Error detected"
newline
bitfld.quad 0x0 13. "SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error." "0: No Shadow Register / LLI Invalid errors,1: Shadow Register / LLI Invalid error detected"
newline
bitfld.quad 0x0 12. "LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error." "0: No LLI write Slave Errors,1: LLI Write SLAVE Error detected"
newline
bitfld.quad 0x0 11. "LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error." "0: No LLI Read Slave Errors,1: LLI read Slave Error detected"
newline
bitfld.quad 0x0 10. "LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error." "0: NO LLI Write Decode Errors,1: LLI write Decode Error detected"
newline
bitfld.quad 0x0 9. "LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error." "0: NO LLI Read Decode Errors,1: LLI Read Decode Error detected"
newline
bitfld.quad 0x0 8. "DST_SLV_ERR_IntStat,Destination Slave Error." "0: No Destination Slave Errors,1: Destination Slave Errors Detected"
newline
bitfld.quad 0x0 7. "SRC_SLV_ERR_IntStat,Source Slave Error." "0: No Source Slave Errors,1: Source Slave Error Detected"
newline
bitfld.quad 0x0 6. "DST_DEC_ERR_IntStat,Destination Decode Error." "0: No destination Decode Errors,1: Destination Decode Error Detected"
newline
bitfld.quad 0x0 5. "SRC_DEC_ERR_IntStat,Source Decode Error." "0: No Source Decode Errors,1: Source Decode Error detected"
newline
bitfld.quad 0x0 4. "DST_TRANSCOMP_IntStat,Destination Transaction Completed." "0,1"
newline
bitfld.quad 0x0 3. "SRC_TRANSCOMP_IntStat,Source Transaction Completed." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUSREG_2,DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "DMA_TFR_DONE_IntStat,DMA Transfer Done." "0: DMA Transfer not completed,1: DMA Transfer Completed"
newline
bitfld.quad 0x0 0. "BLOCK_TFR_DONE_IntStat,Block Transfer Done." "0: Block Transfer not completed,1: Block Transfer completed"
group.quad 0x290++0x7
line.quad 0x0 "CH2_INTSIGNAL_ENABLEREG,This register contains fields that are used to enable the generation of port level interrupt at the channel level."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63,DMAC Channelx Interrupt Signal Enable Register (bits 36to63) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntSignal,Channel Aborted Signal Enable." "0: Disable the propagation of Channel Aborted..,1: Enable the propagation of Channel Aborted.."
newline
bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntSignal,Channel Disabled Signal Enable." "0: Disable the propagation of Channel Disabled..,1: Enable the propagation of Channel Disabled.."
newline
bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntSignal,Channel Suspended Signal Enable." "0: Disable the propagation of Channel Suspended..,1: Enable the propagation of Channel Suspended.."
newline
bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntSignal,Channel Source Suspended Signal Enable." "0: Disable the propagation of Channel Source..,1: Enable the propagation of Channel Source.."
newline
bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntSignal,Channel Lock Cleared Signal Enable." "0: Disable the propagation of Channel Lock Cleared..,1: Enable the propagation of Channel Lock Cleared.."
newline
rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26,DMAC Channelx Interrupt Signal Enable Register (bit 26) Reserved bit - Read Only" "0,1"
newline
rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntSignal,Slave Interface Write Parity Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24,DMAC Channelx Interrupt Signal Enable Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntSignal,Slave Interface Write On Hold Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal,Shadow Register Write On Valid Error Signal Enable." "0: Disable the propagation of Shadow Register Write..,1: Enable the propagation of Shadow register Write.."
newline
bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntSignal,Slave Interface Write On Channel Enabled Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntSignal,Slave Interface Read to write Only Error Signal Enable." "0: Disable the propagation of Slave Interface Read..,1: Enable the propagation of Slave Interface Read.."
newline
bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntSignal,Slave Interface Write to Read Only Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntSignal,Slave Interface Decode Error Signal Enable." "0: Disable the propagation of Slave Interface..,1: Enable the propagation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,Slave Interface Multi Block type Error Signal Enable." "0: Disable the propagation of Slave Interface Multi..,1: Enable the propagation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,Shadow register or LLI Invalid Error Signal Enable." "0: Disable the propagation of Shadow Register or..,1: Enable the propagation of Shadow Register or LLI.."
newline
bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntSignal,LLI WRITE Slave Error Signal Enable." "0: Disable the propagation of LLI WRITE Slave Error..,1: Enable the propagation of LLI WRITE Slave Error.."
newline
bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntSignal,LLI Read Slave Error Signal Enable." "0: Disable the propagation of LLI Read Slave Error..,1: Enable the propagation of LLI Read Slave Error.."
newline
bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntSignal,LLI WRITE Decode Error Signal Enable." "0: Disable the propagation of LLI WRITE Decode..,1: Enable the propagation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntSignal,LLI Read Decode Error Signal Enable." "0: Disable the propagation of LLI Read Decode Error..,1: Enable the propagation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntSignal,Destination Slave Error Signal Enable." "0: Disable the propagation of Destination Slave..,1: Enable the propagation of Destination Slave.."
newline
bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntSignal,Source Slave Error Signal Enable." "0: Disable the propagation of Source Slave Error..,1: Enable the propagation of Source Slave Error.."
newline
bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntSignal,Destination Decode Error Signal Enable." "0: Disable the propagation of Destination Decode..,1: Enable the propagation of Destination Decode.."
newline
bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntSignal,Source Decode Error Signal Enable." "0: Disable the propagation of Source Decode Error..,1: Enable the propagation of Source Decode Error.."
newline
bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntSignal,Destination Transaction Completed Signal Enable." "0: Disable the propagation of Destination..,1: Enable the propagation of Destination.."
newline
bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntSignal,Source Transaction Completed Signal Enable." "0: Disable the propagation of Source Transaction..,1: Enable the propagation of Source Transaction.."
newline
rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntSignal,DMA Transfer Done Interrupt Signal Enable." "0: Disable the propagation of DMA Transfer Done..,1: Enable the propagation of DMA Transfer Done.."
newline
bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntSignal,Block Transfer Done Interrupt Signal Enable." "0: Disable the propagation of Block Transfer Done..,1: Enable the propagation of Block Transfer Done.."
wgroup.quad 0x298++0x7
line.quad 0x0 "CH2_INTCLEARREG,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTCLEARREG_36to63,DMAC Channelx Interrupt Clear Register (bits 36to63) Reserved bit - Read Only"
newline
bitfld.quad 0x0 35. "Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat,ECC Protection Uncorrectable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 34. "Clear_ECC_PROT_UIDMem_CorrERR_IntStat,ECC Protection Correctable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 33. "Clear_ECC_PROT_CHMem_UnCorrERR_IntStat,ECC Protection Uncorrectable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 32. "Clear_ECC_PROT_CHMem_CorrERR_IntStat,ECC Protection Correctable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 31. "Clear_CH_ABORTED_IntStat,Channel Aborted Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 30. "Clear_CH_DISABLED_IntStat,Channel Disabled Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 29. "Clear_CH_SUSPENDED_IntStat,Channel Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 28. "Clear_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 27. "Clear_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTCLEARREG_26,DMAC Channelx Interrupt Clear Register (bit 26) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 25. "Clear_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTCLEARREG_22to24,DMAC Channelx Interrupt Clear Register (bits 22to24) Reserved bit - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Clear_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 20. "Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 19. "Clear_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 18. "Clear_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 17. "Clear_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 16. "Clear_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTCLEARREG_15,DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 13. "Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 12. "Clear_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 11. "Clear_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 10. "Clear_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 9. "Clear_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 8. "Clear_DST_SLV_ERR_IntStat,Destination Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 7. "Clear_SRC_SLV_ERR_IntStat,Source Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 6. "Clear_DST_DEC_ERR_IntStat,Destination Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 5. "Clear_SRC_DEC_ERR_IntStat,Source Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 4. "Clear_DST_TRANSCOMP_IntStat,Destination Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 3. "Clear_SRC_TRANSCOMP_IntStat,Source Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTCLEARREG_2,DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Clear_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 0. "Clear_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Clear Bit." "0,1"
group.quad 0x300++0x2F
line.quad 0x0 "CH3_SAR,The starting source address is programmed by software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While"
hexmask.quad 0x0 0.--63. 1. "SAR,Current Source Address of DMA transfer."
line.quad 0x8 "CH3_DAR,The starting destination address is programmed by the software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer."
hexmask.quad 0x8 0.--63. 1. "DAR,Current Destination Address of DMA transfer."
line.quad 0x10 "CH3_BLOCK_TS,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size."
hexmask.quad 0x10 22.--63. 1. "RSVD_DMAC_CHx_BLOCK_TSREG_63to22,DMAC Channelx Block Transfer Size Register (bits 63to22) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x10 0.--21. 1. "BLOCK_TS,Block Transfer Size."
line.quad 0x18 "CH3_CTL,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.."
bitfld.quad 0x18 63. "SHADOWREG_OR_LLI_VALID,Shadow Register content/Linked List Item valid." "0: Shadow Register content/LLI is invalid,1: Last Shadow Register/LLI is valid"
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bitfld.quad 0x18 62. "SHADOWREG_OR_LLI_LAST,Last Shadow Register/Linked List Item." "0: Not last Shadow Register/LLI,1: Last Shadow Register/LLI"
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rbitfld.quad 0x18 59.--61. "RSVD_DMAC_CHx_CTL_59to61,DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 58. "IOC_BlkTfr,Interrupt On completion of Block Transfer" "0,1"
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rbitfld.quad 0x18 57. "DST_STAT_EN,Destination Status Enable" "0,1"
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rbitfld.quad 0x18 56. "SRC_STAT_EN,Source Status Enable" "0,1"
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hexmask.quad.byte 0x18 48.--55. 1. "AWLEN,Destination Burst Length"
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bitfld.quad 0x18 47. "AWLEN_EN,Destination Burst Length Enable" "0,1"
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hexmask.quad.byte 0x18 39.--46. 1. "ARLEN,Source Burst Length"
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bitfld.quad 0x18 38. "ARLEN_EN,Source Burst Length Enable" "0,1"
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bitfld.quad 0x18 35.--37. "AW_PROT,AXI 'aw_prot' signal" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 32.--34. "AR_PROT,AXI 'ar_prot' signal" "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x18 31. "RSVD_DMAC_CHx_CTL_31,DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 30. "NonPosted_LastWrite_En,Non Posted Last Write Enable" "0: Posted writes may be used throughout the block..,1: Posted writes may be used till the end of the.."
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hexmask.quad.byte 0x18 26.--29. 1. "AW_CACHE,AXI 'aw_cache' signal"
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hexmask.quad.byte 0x18 22.--25. 1. "AR_CACHE,AXI 'ar_cache' signal"
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hexmask.quad.byte 0x18 18.--21. 1. "DST_MSIZE,Destination Burst Transaction Length."
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hexmask.quad.byte 0x18 14.--17. 1. "SRC_MSIZE,Source Burst Transaction Length."
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bitfld.quad 0x18 11.--13. "DST_TR_WIDTH,Destination Transfer Width." "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 8.--10. "SRC_TR_WIDTH,Source Transfer Width." "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x18 7. "RSVD_DMAC_CHx_CTL_7,DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 6. "DINC,Destination Address Increment." "0: Increment,1: No Change"
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rbitfld.quad 0x18 5. "RSVD_DMAC_CHx_CTL_5,DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 4. "SINC,Source Address Increment." "0: Increment,1: No Change"
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rbitfld.quad 0x18 3. "RSVD_DMAC_CHx_CTL_3,DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only" "0,1"
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rbitfld.quad 0x18 2. "DMS,Destination Master Select." "0: AXI master 1,1: AXI Master 2"
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rbitfld.quad 0x18 1. "RSVD_DMAC_CHx_CTL_1,DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only" "0,1"
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rbitfld.quad 0x18 0. "SMS,Source Master Select." "0: AXI master 1,1: AXI Master 2"
line.quad 0x20 "CH3_CFG2,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel."
rbitfld.quad 0x20 63. "RSVD_DMAC_CHx_CFG_63,DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 59.--62. 1. "DST_OSR_LMT,Destination Outstanding Request Limit"
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hexmask.quad.byte 0x20 55.--58. 1. "SRC_OSR_LMT,Source Outstanding Request Limit"
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bitfld.quad 0x20 53.--54. "LOCK_CH_L,Channel Lock Level" "0: Over complete DMA transfer,1: Over DMA block transfer,?,?"
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bitfld.quad 0x20 52. "LOCK_CH,Channel Lock bit" "0,1"
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hexmask.quad.byte 0x20 47.--51. 1. "CH_PRIOR,Channel Priority"
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hexmask.quad.byte 0x20 39.--46. 1. "RSVD_DMAC_CHx_CFG_39to46,DMAC Channelx Transfer Configuration Register (bits 39to46) Reserved bits - Read Only"
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rbitfld.quad 0x20 38. "DST_HWHS_POL,Destination Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
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rbitfld.quad 0x20 37. "SRC_HWHS_POL,Source Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
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bitfld.quad 0x20 36. "HS_SEL_DST,Destination Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
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bitfld.quad 0x20 35. "HS_SEL_SRC,Source Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
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bitfld.quad 0x20 32.--34. "TT_FC,Transfer Type and Flow Control." "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x20 29.--31. "RSVD_DMAC_CHx_CFG_29to31,DMAC Channelx Transfer Configuration Register (bits 29to31) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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hexmask.quad.byte 0x20 25.--28. 1. "WR_UID,Defines the number of AXI Unique ID's supported for the AXI Write Channel. The value programmed must be less than or equal to DMAX_CH(x)_WR_UID. Otherwise  it is limited by the value DMAX_CH(x)_WR_UID."
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rbitfld.quad 0x20 22.--24. "RSVD_DMAC_CHx_CFG_22to24,DMAC Channelx Transfer Configuration Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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hexmask.quad.byte 0x20 18.--21. 1. "RD_UID,Defines the number of AXI Unique ID's supported for the AXI Read Channel. The value programmed must be less than or equal to DMAX_CH(x)_RD_UID. Otherwise  it is limited by the value DMAX_CH(x)_RD_UID."
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rbitfld.quad 0x20 17. "RSVD_DMAC_CHx_CFG_17,DMAC Channelx Transfer Configuration Register (bit 17) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 11.--16. 1. "DST_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0;"
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rbitfld.quad 0x20 10. "RSVD_DMAC_CHx_CFG_10,DMAC Channelx Transfer Configuration Register (bit 10) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 4.--9. 1. "SRC_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise "
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rbitfld.quad 0x20 2.--3. "DST_MULTBLK_TYPE,Destination Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
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rbitfld.quad 0x20 0.--1. "SRC_MULTBLK_TYPE,Source Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
line.quad 0x28 "CH3_LLP,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the"
hexmask.quad 0x28 6.--63. 1. "LOC,Starting Address Memory of LLI block"
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hexmask.quad.byte 0x28 1.--5. 1. "RSVD_DMAC_CHx_LLP_1to5,DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only"
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rbitfld.quad 0x28 0. "LMS,LLI master Select" "0: AXI Master 1,1: AXI Master 2"
rgroup.quad 0x330++0x7
line.quad 0x0 "CH3_STATUSREG,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx."
hexmask.quad.tbyte 0x0 47.--63. 1. "RSVD_DMAC_CHx_STATUSREG_47to63,DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 32.--46. 1. "DATA_LEFT_IN_FIFO,Data Left in FIFO."
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hexmask.quad.word 0x0 22.--31. 1. "RSVD_DMAC_CHx_STATUSREG_22to31,DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x0 0.--21. 1. "CMPLTD_BLK_TFR_SIZE,Completed Block Transfer Size."
group.quad 0x338++0xF
line.quad 0x0 "CH3_SWHSSRCREG,Channelx Software handshake Source Register."
hexmask.quad 0x0 6.--63. 1. "RSVD_DMAC_CHx_SWHSSRCREG_6to63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x0 5. "SWHS_LST_SRC_WE,Write Enable bit for Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 4. "SWHS_LST_SRC,Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 3. "SWHS_SGLREQ_SRC_WE,Write Enable bit for Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 2. "SWHS_SGLREQ_SRC,Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 1. "SWHS_REQ_SRC_WE,Write Enable bit for Software Handshake Request for Channel Source." "0,1"
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bitfld.quad 0x0 0. "SWHS_REQ_SRC,Software Handshake Request for Channel Source." "0,1"
line.quad 0x8 "CH3_SWHSDSTREG,Channelx Software handshake Destination Register."
hexmask.quad 0x8 6.--63. 1. "RSVD_DMAC_CHx_SWHSDSTREG_6to63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x8 5. "SWHS_LST_DST_WE,Write Enable bit for Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 4. "SWHS_LST_DST,Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 3. "SWHS_SGLREQ_DST_WE,Write Enable bit for Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 2. "SWHS_SGLREQ_DST,Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 1. "SWHS_REQ_DST_WE,Write Enable bit for Software Handshake Request for Channel Destination." "0,1"
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bitfld.quad 0x8 0. "SWHS_REQ_DST,Software Handshake Request for Channel Destination." "0,1"
wgroup.quad 0x348++0x7
line.quad 0x0 "CH3_BLK_TFR_RESUMEREQREG,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer."
hexmask.quad 0x0 1.--63. 1. "RSVD_DMAC_CHx_BLK_TFR_RESUMEREQREG_1to63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only"
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bitfld.quad 0x0 0. "BLK_TFR_RESUMEREQ,Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer." "0,1"
group.quad 0x350++0xF
line.quad 0x0 "CH3_AXI_IDREG,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad.long 0x0 32.--63. 1. "RSVD_DMAC_CHx_AXI_IDREG_32to63,DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 20.--31. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm32to63,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 16.--19. 1. "AXI_WRITE_ID_SUFFIX,AXI Write ID Suffix."
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hexmask.quad.word 0x0 4.--15. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm1to31,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 0.--3. 1. "AXI_READ_ID_SUFFIX,AXI Read ID Suffix"
line.quad 0x8 "CH3_AXI_QOSREG,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad 0x8 8.--63. 1. "RSVD_DMAC_CHx_AXI_QOSREG_8to63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only"
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hexmask.quad.byte 0x8 4.--7. 1. "AXI_ARQOS,AXI ARQOS."
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hexmask.quad.byte 0x8 0.--3. 1. "AXI_AWQOS,AXI AWQOS."
group.quad 0x380++0x7
line.quad 0x0 "CH3_INTSTATUS_ENABLEREG,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH3_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63,DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only"
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rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation Channel x Channel Memory.."
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rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation of Channel x Channel.."
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bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntStat,Channel Aborted Status Enable." "0: Disable the generation of Channel Aborted..,1: Enable the generation of Channel Aborted.."
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bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntStat,Channel Disabled Status Enable." "0: Disable the generation of Channel Disabled..,1: Enable the generation of Channel Disabled.."
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bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntStat,Channel Suspended Status Enable." "0: Disable the generation of Channel Suspended..,1: Enable the generation of Channel Suspended.."
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bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Status Enable." "0: Disable the generation of Channel Source..,1: Enable the generation of Channel Source.."
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bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Status Enable." "0: Disable the generation of Channel LOCK CLEARED..,1: Enable the generation of Channel LOCK CLEARED.."
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rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26,DMAC Channelx Interrupt Status Register (bit 26) Reserved bit - Read Only" "0,1"
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rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24,DMAC Channelx Interrupt Status Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Status Enable." "0: Disable the generation of Shadow Register Write..,1: Enable the generation of Shadow register Write.."
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bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Status Enable." "0: Disable the generation of Slave Interface Read..,1: Enable the generation of Slave Interface Read to.."
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bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Status Enable." "0: Disable the generation of Slave Interface Decode..,1: Enable the generation of Slave Interface Decode.."
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rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Status Enable." "0: Disable the generation of Slave Interface Multi..,1: Enable the generation of Slave Interface Multi.."
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bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Status Enable." "0: Disable the generation of Shadow Register or LLI..,1: Enable the generation of Shadow Register or LLI.."
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bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Status Enable." "0: Disable the generation of LLI WRITE Slave Error..,1: Enable the generation of LLI WRITE Slave Error.."
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bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Status Enable." "0: Disable the generation of LLI Read Slave Error..,1: Enable the generation of LLI Read Slave Error.."
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bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Status Enable." "0: Disable the generation of LLI WRITE Decode Error..,1: Enable the generation of LLI WRITE Decode Error.."
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bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Status Enable." "0: Disable the generation of LLI Read Decode Error..,1: Enable the generation of LLI Read Decode Error.."
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bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntStat,Destination Slave Error Status Enable." "0: Disable the generation of Destination Slave..,1: Enable the generation of Destination Slave Error.."
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bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntStat,Source Slave Error Status Enable." "0: Disable the generation of Source Slave Error..,1: Enable the generation of Source Slave Error.."
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bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntStat,Destination Decode Error Status Enable." "0: Disable the generation of Destination Decode..,1: Enable the generation of Destination Decode.."
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bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntStat,Source Decode Error Status Enable." "0: Disable the generation of Source Decode Error..,1: Enable the generation of Source Decode Error.."
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bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntStat,Destination Transaction Completed Status Enable." "0: Disable the generation of Destination..,1: Enable the generation of Destination Transaction.."
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bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntStat,Source Transaction Completed Status Enable." "0: Disable the generation of Source Transaction..,1: Enable the generation of Source Transaction.."
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rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Status Enable." "0: Disable the generation of DMA Transfer Done..,1: Enable the generation of DMA Transfer Done.."
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bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Status Enable." "0: Disable the generation of Block Transfer Done..,1: Enable the generation of Block Transfer Done.."
rgroup.quad 0x388++0x7
line.quad 0x0 "CH3_INTSTATUS,Channelx Interrupt Status Register captures the Channelx specific interrupts"
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUSREG_36to63,DMAC Channelx Specific Interrupt Register (bits 36to63) Reserved bits - Read Only"
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bitfld.quad 0x0 35. "ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x UID Memory Interface Uncorrectable..,1: Channel x UID Memory Interface Uncorrectable.."
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bitfld.quad 0x0 34. "ECC_PROT_UIDMem_CorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x UID Memory Interface correctable..,1: Channel x UID Memory Interface correctable Error.."
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bitfld.quad 0x0 33. "ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface Uncorrectable..,1: Channel x FIFO Memory Interface Uncorrectable.."
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bitfld.quad 0x0 32. "ECC_PROT_CHMem_CorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface correctable..,1: Channel x FIFO Memory Interface correctable.."
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bitfld.quad 0x0 31. "CH_ABORTED_IntStat,Channel Aborted." "0: Channel is not aborted,1: Channel is aborted"
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bitfld.quad 0x0 30. "CH_DISABLED_IntStat,Channel Disabled." "0: Channel is not disabled,1: Channel is disabled"
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bitfld.quad 0x0 29. "CH_SUSPENDED_IntStat,Channel Suspended." "0: Channel is not suspended,1: Channel is suspended"
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bitfld.quad 0x0 28. "CH_SRC_SUSPENDED_IntStat,Channel Source Suspended." "0: Channel source is not suspended,1: Channel Source is suspended"
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bitfld.quad 0x0 27. "CH_LOCK_CLEARED_IntStat,Channel Lock Cleared." "0: Channel locking is not cleared,1: Channel locking is cleared"
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bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUSREG_26,DMAC Channelx Specific Interrupt Register (bit 26) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 25. "SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error." "0: No Slave Interface Write Parity Errors,1: Slave Interface Write Parity Error detected"
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bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUSREG_22to24,DMAC Channelx Specific Interrupt Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error." "0: No Slave Interface Write On Hold Errors,1: Slave Interface Write On Hold Error detected"
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bitfld.quad 0x0 20. "SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error." "0: No Slave Interface Shadow Register Write On..,1: Slave Interface Shadow Register Write On Valid.."
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bitfld.quad 0x0 19. "SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error." "0: No Slave Interface Write On Channel Enabled Errors,1: Slave Interface Write On Channel Enabled Error.."
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bitfld.quad 0x0 18. "SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error." "0: No Slave Interface Read to Write Only Errors,1: Slave Interface Read to Write Only Error detected"
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bitfld.quad 0x0 17. "SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error." "0: No Slave Interface Write to Read Only Errors,1: Slave Interface Write to Read Only Error detected"
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bitfld.quad 0x0 16. "SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error." "0: No Slave Interface Decode errors,1: Slave Interface Decode Error detected"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUSREG_15,DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error." "0: No Multi-block transfer type Errors,1: Multi-block transfer type Error detected"
newline
bitfld.quad 0x0 13. "SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error." "0: No Shadow Register / LLI Invalid errors,1: Shadow Register / LLI Invalid error detected"
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bitfld.quad 0x0 12. "LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error." "0: No LLI write Slave Errors,1: LLI Write SLAVE Error detected"
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bitfld.quad 0x0 11. "LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error." "0: No LLI Read Slave Errors,1: LLI read Slave Error detected"
newline
bitfld.quad 0x0 10. "LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error." "0: NO LLI Write Decode Errors,1: LLI write Decode Error detected"
newline
bitfld.quad 0x0 9. "LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error." "0: NO LLI Read Decode Errors,1: LLI Read Decode Error detected"
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bitfld.quad 0x0 8. "DST_SLV_ERR_IntStat,Destination Slave Error." "0: No Destination Slave Errors,1: Destination Slave Errors Detected"
newline
bitfld.quad 0x0 7. "SRC_SLV_ERR_IntStat,Source Slave Error." "0: No Source Slave Errors,1: Source Slave Error Detected"
newline
bitfld.quad 0x0 6. "DST_DEC_ERR_IntStat,Destination Decode Error." "0: No destination Decode Errors,1: Destination Decode Error Detected"
newline
bitfld.quad 0x0 5. "SRC_DEC_ERR_IntStat,Source Decode Error." "0: No Source Decode Errors,1: Source Decode Error detected"
newline
bitfld.quad 0x0 4. "DST_TRANSCOMP_IntStat,Destination Transaction Completed." "0,1"
newline
bitfld.quad 0x0 3. "SRC_TRANSCOMP_IntStat,Source Transaction Completed." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUSREG_2,DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "DMA_TFR_DONE_IntStat,DMA Transfer Done." "0: DMA Transfer not completed,1: DMA Transfer Completed"
newline
bitfld.quad 0x0 0. "BLOCK_TFR_DONE_IntStat,Block Transfer Done." "0: Block Transfer not completed,1: Block Transfer completed"
group.quad 0x390++0x7
line.quad 0x0 "CH3_INTSIGNAL_ENABLEREG,This register contains fields that are used to enable the generation of port level interrupt at the channel level."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63,DMAC Channelx Interrupt Signal Enable Register (bits 36to63) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
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rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntSignal,Channel Aborted Signal Enable." "0: Disable the propagation of Channel Aborted..,1: Enable the propagation of Channel Aborted.."
newline
bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntSignal,Channel Disabled Signal Enable." "0: Disable the propagation of Channel Disabled..,1: Enable the propagation of Channel Disabled.."
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bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntSignal,Channel Suspended Signal Enable." "0: Disable the propagation of Channel Suspended..,1: Enable the propagation of Channel Suspended.."
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bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntSignal,Channel Source Suspended Signal Enable." "0: Disable the propagation of Channel Source..,1: Enable the propagation of Channel Source.."
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bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntSignal,Channel Lock Cleared Signal Enable." "0: Disable the propagation of Channel Lock Cleared..,1: Enable the propagation of Channel Lock Cleared.."
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rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26,DMAC Channelx Interrupt Signal Enable Register (bit 26) Reserved bit - Read Only" "0,1"
newline
rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntSignal,Slave Interface Write Parity Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24,DMAC Channelx Interrupt Signal Enable Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntSignal,Slave Interface Write On Hold Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal,Shadow Register Write On Valid Error Signal Enable." "0: Disable the propagation of Shadow Register Write..,1: Enable the propagation of Shadow register Write.."
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bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntSignal,Slave Interface Write On Channel Enabled Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
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bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntSignal,Slave Interface Read to write Only Error Signal Enable." "0: Disable the propagation of Slave Interface Read..,1: Enable the propagation of Slave Interface Read.."
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bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntSignal,Slave Interface Write to Read Only Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntSignal,Slave Interface Decode Error Signal Enable." "0: Disable the propagation of Slave Interface..,1: Enable the propagation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,Slave Interface Multi Block type Error Signal Enable." "0: Disable the propagation of Slave Interface Multi..,1: Enable the propagation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,Shadow register or LLI Invalid Error Signal Enable." "0: Disable the propagation of Shadow Register or..,1: Enable the propagation of Shadow Register or LLI.."
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bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntSignal,LLI WRITE Slave Error Signal Enable." "0: Disable the propagation of LLI WRITE Slave Error..,1: Enable the propagation of LLI WRITE Slave Error.."
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bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntSignal,LLI Read Slave Error Signal Enable." "0: Disable the propagation of LLI Read Slave Error..,1: Enable the propagation of LLI Read Slave Error.."
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bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntSignal,LLI WRITE Decode Error Signal Enable." "0: Disable the propagation of LLI WRITE Decode..,1: Enable the propagation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntSignal,LLI Read Decode Error Signal Enable." "0: Disable the propagation of LLI Read Decode Error..,1: Enable the propagation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntSignal,Destination Slave Error Signal Enable." "0: Disable the propagation of Destination Slave..,1: Enable the propagation of Destination Slave.."
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bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntSignal,Source Slave Error Signal Enable." "0: Disable the propagation of Source Slave Error..,1: Enable the propagation of Source Slave Error.."
newline
bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntSignal,Destination Decode Error Signal Enable." "0: Disable the propagation of Destination Decode..,1: Enable the propagation of Destination Decode.."
newline
bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntSignal,Source Decode Error Signal Enable." "0: Disable the propagation of Source Decode Error..,1: Enable the propagation of Source Decode Error.."
newline
bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntSignal,Destination Transaction Completed Signal Enable." "0: Disable the propagation of Destination..,1: Enable the propagation of Destination.."
newline
bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntSignal,Source Transaction Completed Signal Enable." "0: Disable the propagation of Source Transaction..,1: Enable the propagation of Source Transaction.."
newline
rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntSignal,DMA Transfer Done Interrupt Signal Enable." "0: Disable the propagation of DMA Transfer Done..,1: Enable the propagation of DMA Transfer Done.."
newline
bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntSignal,Block Transfer Done Interrupt Signal Enable." "0: Disable the propagation of Block Transfer Done..,1: Enable the propagation of Block Transfer Done.."
wgroup.quad 0x398++0x7
line.quad 0x0 "CH3_INTCLEARREG,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTCLEARREG_36to63,DMAC Channelx Interrupt Clear Register (bits 36to63) Reserved bit - Read Only"
newline
bitfld.quad 0x0 35. "Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat,ECC Protection Uncorrectable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 34. "Clear_ECC_PROT_UIDMem_CorrERR_IntStat,ECC Protection Correctable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 33. "Clear_ECC_PROT_CHMem_UnCorrERR_IntStat,ECC Protection Uncorrectable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 32. "Clear_ECC_PROT_CHMem_CorrERR_IntStat,ECC Protection Correctable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 31. "Clear_CH_ABORTED_IntStat,Channel Aborted Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 30. "Clear_CH_DISABLED_IntStat,Channel Disabled Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 29. "Clear_CH_SUSPENDED_IntStat,Channel Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 28. "Clear_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 27. "Clear_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTCLEARREG_26,DMAC Channelx Interrupt Clear Register (bit 26) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 25. "Clear_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTCLEARREG_22to24,DMAC Channelx Interrupt Clear Register (bits 22to24) Reserved bit - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Clear_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 20. "Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 19. "Clear_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 18. "Clear_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 17. "Clear_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 16. "Clear_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTCLEARREG_15,DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 13. "Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 12. "Clear_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 11. "Clear_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 10. "Clear_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 9. "Clear_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 8. "Clear_DST_SLV_ERR_IntStat,Destination Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 7. "Clear_SRC_SLV_ERR_IntStat,Source Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 6. "Clear_DST_DEC_ERR_IntStat,Destination Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 5. "Clear_SRC_DEC_ERR_IntStat,Source Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 4. "Clear_DST_TRANSCOMP_IntStat,Destination Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 3. "Clear_SRC_TRANSCOMP_IntStat,Source Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTCLEARREG_2,DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Clear_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 0. "Clear_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Clear Bit." "0,1"
group.quad 0x400++0x2F
line.quad 0x0 "CH4_SAR,The starting source address is programmed by software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While"
hexmask.quad 0x0 0.--63. 1. "SAR,Current Source Address of DMA transfer."
line.quad 0x8 "CH4_DAR,The starting destination address is programmed by the software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer."
hexmask.quad 0x8 0.--63. 1. "DAR,Current Destination Address of DMA transfer."
line.quad 0x10 "CH4_BLOCK_TS,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size."
hexmask.quad 0x10 22.--63. 1. "RSVD_DMAC_CHx_BLOCK_TSREG_63to22,DMAC Channelx Block Transfer Size Register (bits 63to22) Reserved bits - Read Only"
newline
hexmask.quad.tbyte 0x10 0.--21. 1. "BLOCK_TS,Block Transfer Size."
line.quad 0x18 "CH4_CTL,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.."
bitfld.quad 0x18 63. "SHADOWREG_OR_LLI_VALID,Shadow Register content/Linked List Item valid." "0: Shadow Register content/LLI is invalid,1: Last Shadow Register/LLI is valid"
newline
bitfld.quad 0x18 62. "SHADOWREG_OR_LLI_LAST,Last Shadow Register/Linked List Item." "0: Not last Shadow Register/LLI,1: Last Shadow Register/LLI"
newline
rbitfld.quad 0x18 59.--61. "RSVD_DMAC_CHx_CTL_59to61,DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 58. "IOC_BlkTfr,Interrupt On completion of Block Transfer" "0,1"
newline
rbitfld.quad 0x18 57. "DST_STAT_EN,Destination Status Enable" "0,1"
newline
rbitfld.quad 0x18 56. "SRC_STAT_EN,Source Status Enable" "0,1"
newline
hexmask.quad.byte 0x18 48.--55. 1. "AWLEN,Destination Burst Length"
newline
bitfld.quad 0x18 47. "AWLEN_EN,Destination Burst Length Enable" "0,1"
newline
hexmask.quad.byte 0x18 39.--46. 1. "ARLEN,Source Burst Length"
newline
bitfld.quad 0x18 38. "ARLEN_EN,Source Burst Length Enable" "0,1"
newline
bitfld.quad 0x18 35.--37. "AW_PROT,AXI 'aw_prot' signal" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 32.--34. "AR_PROT,AXI 'ar_prot' signal" "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x18 31. "RSVD_DMAC_CHx_CTL_31,DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 30. "NonPosted_LastWrite_En,Non Posted Last Write Enable" "0: Posted writes may be used throughout the block..,1: Posted writes may be used till the end of the.."
newline
hexmask.quad.byte 0x18 26.--29. 1. "AW_CACHE,AXI 'aw_cache' signal"
newline
hexmask.quad.byte 0x18 22.--25. 1. "AR_CACHE,AXI 'ar_cache' signal"
newline
hexmask.quad.byte 0x18 18.--21. 1. "DST_MSIZE,Destination Burst Transaction Length."
newline
hexmask.quad.byte 0x18 14.--17. 1. "SRC_MSIZE,Source Burst Transaction Length."
newline
bitfld.quad 0x18 11.--13. "DST_TR_WIDTH,Destination Transfer Width." "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 8.--10. "SRC_TR_WIDTH,Source Transfer Width." "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x18 7. "RSVD_DMAC_CHx_CTL_7,DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 6. "DINC,Destination Address Increment." "0: Increment,1: No Change"
newline
rbitfld.quad 0x18 5. "RSVD_DMAC_CHx_CTL_5,DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 4. "SINC,Source Address Increment." "0: Increment,1: No Change"
newline
rbitfld.quad 0x18 3. "RSVD_DMAC_CHx_CTL_3,DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only" "0,1"
newline
rbitfld.quad 0x18 2. "DMS,Destination Master Select." "0: AXI master 1,1: AXI Master 2"
newline
rbitfld.quad 0x18 1. "RSVD_DMAC_CHx_CTL_1,DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only" "0,1"
newline
rbitfld.quad 0x18 0. "SMS,Source Master Select." "0: AXI master 1,1: AXI Master 2"
line.quad 0x20 "CH4_CFG2,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel."
rbitfld.quad 0x20 63. "RSVD_DMAC_CHx_CFG_63,DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only" "0,1"
newline
hexmask.quad.byte 0x20 59.--62. 1. "DST_OSR_LMT,Destination Outstanding Request Limit"
newline
hexmask.quad.byte 0x20 55.--58. 1. "SRC_OSR_LMT,Source Outstanding Request Limit"
newline
bitfld.quad 0x20 53.--54. "LOCK_CH_L,Channel Lock Level" "0: Over complete DMA transfer,1: Over DMA block transfer,?,?"
newline
bitfld.quad 0x20 52. "LOCK_CH,Channel Lock bit" "0,1"
newline
hexmask.quad.byte 0x20 47.--51. 1. "CH_PRIOR,Channel Priority"
newline
hexmask.quad.byte 0x20 39.--46. 1. "RSVD_DMAC_CHx_CFG_39to46,DMAC Channelx Transfer Configuration Register (bits 39to46) Reserved bits - Read Only"
newline
rbitfld.quad 0x20 38. "DST_HWHS_POL,Destination Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
newline
rbitfld.quad 0x20 37. "SRC_HWHS_POL,Source Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
newline
bitfld.quad 0x20 36. "HS_SEL_DST,Destination Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
newline
bitfld.quad 0x20 35. "HS_SEL_SRC,Source Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
newline
bitfld.quad 0x20 32.--34. "TT_FC,Transfer Type and Flow Control." "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x20 29.--31. "RSVD_DMAC_CHx_CFG_29to31,DMAC Channelx Transfer Configuration Register (bits 29to31) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x20 25.--28. 1. "WR_UID,Defines the number of AXI Unique ID's supported for the AXI Write Channel. The value programmed must be less than or equal to DMAX_CH(x)_WR_UID. Otherwise  it is limited by the value DMAX_CH(x)_WR_UID."
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rbitfld.quad 0x20 22.--24. "RSVD_DMAC_CHx_CFG_22to24,DMAC Channelx Transfer Configuration Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x20 18.--21. 1. "RD_UID,Defines the number of AXI Unique ID's supported for the AXI Read Channel. The value programmed must be less than or equal to DMAX_CH(x)_RD_UID. Otherwise  it is limited by the value DMAX_CH(x)_RD_UID."
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rbitfld.quad 0x20 17. "RSVD_DMAC_CHx_CFG_17,DMAC Channelx Transfer Configuration Register (bit 17) Reserved bit - Read Only" "0,1"
newline
hexmask.quad.byte 0x20 11.--16. 1. "DST_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0;"
newline
rbitfld.quad 0x20 10. "RSVD_DMAC_CHx_CFG_10,DMAC Channelx Transfer Configuration Register (bit 10) Reserved bit - Read Only" "0,1"
newline
hexmask.quad.byte 0x20 4.--9. 1. "SRC_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise "
newline
rbitfld.quad 0x20 2.--3. "DST_MULTBLK_TYPE,Destination Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
newline
rbitfld.quad 0x20 0.--1. "SRC_MULTBLK_TYPE,Source Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
line.quad 0x28 "CH4_LLP,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the"
hexmask.quad 0x28 6.--63. 1. "LOC,Starting Address Memory of LLI block"
newline
hexmask.quad.byte 0x28 1.--5. 1. "RSVD_DMAC_CHx_LLP_1to5,DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only"
newline
rbitfld.quad 0x28 0. "LMS,LLI master Select" "0: AXI Master 1,1: AXI Master 2"
rgroup.quad 0x430++0x7
line.quad 0x0 "CH4_STATUSREG,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx."
hexmask.quad.tbyte 0x0 47.--63. 1. "RSVD_DMAC_CHx_STATUSREG_47to63,DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only"
newline
hexmask.quad.word 0x0 32.--46. 1. "DATA_LEFT_IN_FIFO,Data Left in FIFO."
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hexmask.quad.word 0x0 22.--31. 1. "RSVD_DMAC_CHx_STATUSREG_22to31,DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only"
newline
hexmask.quad.tbyte 0x0 0.--21. 1. "CMPLTD_BLK_TFR_SIZE,Completed Block Transfer Size."
group.quad 0x438++0xF
line.quad 0x0 "CH4_SWHSSRCREG,Channelx Software handshake Source Register."
hexmask.quad 0x0 6.--63. 1. "RSVD_DMAC_CHx_SWHSSRCREG_6to63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x0 5. "SWHS_LST_SRC_WE,Write Enable bit for Software Handshake Last Request for Channel Source." "0,1"
newline
bitfld.quad 0x0 4. "SWHS_LST_SRC,Software Handshake Last Request for Channel Source." "0,1"
newline
bitfld.quad 0x0 3. "SWHS_SGLREQ_SRC_WE,Write Enable bit for Software Handshake Single Request for Channel Source." "0,1"
newline
bitfld.quad 0x0 2. "SWHS_SGLREQ_SRC,Software Handshake Single Request for Channel Source." "0,1"
newline
bitfld.quad 0x0 1. "SWHS_REQ_SRC_WE,Write Enable bit for Software Handshake Request for Channel Source." "0,1"
newline
bitfld.quad 0x0 0. "SWHS_REQ_SRC,Software Handshake Request for Channel Source." "0,1"
line.quad 0x8 "CH4_SWHSDSTREG,Channelx Software handshake Destination Register."
hexmask.quad 0x8 6.--63. 1. "RSVD_DMAC_CHx_SWHSDSTREG_6to63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only"
newline
bitfld.quad 0x8 5. "SWHS_LST_DST_WE,Write Enable bit for Software Handshake Last Request for Channel Destination." "0,1"
newline
bitfld.quad 0x8 4. "SWHS_LST_DST,Software Handshake Last Request for Channel Destination." "0,1"
newline
bitfld.quad 0x8 3. "SWHS_SGLREQ_DST_WE,Write Enable bit for Software Handshake Single Request for Channel Destination." "0,1"
newline
bitfld.quad 0x8 2. "SWHS_SGLREQ_DST,Software Handshake Single Request for Channel Destination." "0,1"
newline
bitfld.quad 0x8 1. "SWHS_REQ_DST_WE,Write Enable bit for Software Handshake Request for Channel Destination." "0,1"
newline
bitfld.quad 0x8 0. "SWHS_REQ_DST,Software Handshake Request for Channel Destination." "0,1"
wgroup.quad 0x448++0x7
line.quad 0x0 "CH4_BLK_TFR_RESUMEREQREG,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer."
hexmask.quad 0x0 1.--63. 1. "RSVD_DMAC_CHx_BLK_TFR_RESUMEREQREG_1to63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only"
newline
bitfld.quad 0x0 0. "BLK_TFR_RESUMEREQ,Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer." "0,1"
group.quad 0x450++0xF
line.quad 0x0 "CH4_AXI_IDREG,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad.long 0x0 32.--63. 1. "RSVD_DMAC_CHx_AXI_IDREG_32to63,DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only"
newline
hexmask.quad.word 0x0 20.--31. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm32to63,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only"
newline
hexmask.quad.byte 0x0 16.--19. 1. "AXI_WRITE_ID_SUFFIX,AXI Write ID Suffix."
newline
hexmask.quad.word 0x0 4.--15. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm1to31,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only"
newline
hexmask.quad.byte 0x0 0.--3. 1. "AXI_READ_ID_SUFFIX,AXI Read ID Suffix"
line.quad 0x8 "CH4_AXI_QOSREG,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad 0x8 8.--63. 1. "RSVD_DMAC_CHx_AXI_QOSREG_8to63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only"
newline
hexmask.quad.byte 0x8 4.--7. 1. "AXI_ARQOS,AXI ARQOS."
newline
hexmask.quad.byte 0x8 0.--3. 1. "AXI_AWQOS,AXI AWQOS."
group.quad 0x480++0x7
line.quad 0x0 "CH4_INTSTATUS_ENABLEREG,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH4_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63,DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
newline
rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
newline
rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation Channel x Channel Memory.."
newline
rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntStat,Channel Aborted Status Enable." "0: Disable the generation of Channel Aborted..,1: Enable the generation of Channel Aborted.."
newline
bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntStat,Channel Disabled Status Enable." "0: Disable the generation of Channel Disabled..,1: Enable the generation of Channel Disabled.."
newline
bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntStat,Channel Suspended Status Enable." "0: Disable the generation of Channel Suspended..,1: Enable the generation of Channel Suspended.."
newline
bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Status Enable." "0: Disable the generation of Channel Source..,1: Enable the generation of Channel Source.."
newline
bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Status Enable." "0: Disable the generation of Channel LOCK CLEARED..,1: Enable the generation of Channel LOCK CLEARED.."
newline
rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26,DMAC Channelx Interrupt Status Register (bit 26) Reserved bit - Read Only" "0,1"
newline
rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24,DMAC Channelx Interrupt Status Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Status Enable." "0: Disable the generation of Shadow Register Write..,1: Enable the generation of Shadow register Write.."
newline
bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Status Enable." "0: Disable the generation of Slave Interface Read..,1: Enable the generation of Slave Interface Read to.."
newline
bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Status Enable." "0: Disable the generation of Slave Interface Decode..,1: Enable the generation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Status Enable." "0: Disable the generation of Slave Interface Multi..,1: Enable the generation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Status Enable." "0: Disable the generation of Shadow Register or LLI..,1: Enable the generation of Shadow Register or LLI.."
newline
bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Status Enable." "0: Disable the generation of LLI WRITE Slave Error..,1: Enable the generation of LLI WRITE Slave Error.."
newline
bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Status Enable." "0: Disable the generation of LLI Read Slave Error..,1: Enable the generation of LLI Read Slave Error.."
newline
bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Status Enable." "0: Disable the generation of LLI WRITE Decode Error..,1: Enable the generation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Status Enable." "0: Disable the generation of LLI Read Decode Error..,1: Enable the generation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntStat,Destination Slave Error Status Enable." "0: Disable the generation of Destination Slave..,1: Enable the generation of Destination Slave Error.."
newline
bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntStat,Source Slave Error Status Enable." "0: Disable the generation of Source Slave Error..,1: Enable the generation of Source Slave Error.."
newline
bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntStat,Destination Decode Error Status Enable." "0: Disable the generation of Destination Decode..,1: Enable the generation of Destination Decode.."
newline
bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntStat,Source Decode Error Status Enable." "0: Disable the generation of Source Decode Error..,1: Enable the generation of Source Decode Error.."
newline
bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntStat,Destination Transaction Completed Status Enable." "0: Disable the generation of Destination..,1: Enable the generation of Destination Transaction.."
newline
bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntStat,Source Transaction Completed Status Enable." "0: Disable the generation of Source Transaction..,1: Enable the generation of Source Transaction.."
newline
rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Status Enable." "0: Disable the generation of DMA Transfer Done..,1: Enable the generation of DMA Transfer Done.."
newline
bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Status Enable." "0: Disable the generation of Block Transfer Done..,1: Enable the generation of Block Transfer Done.."
rgroup.quad 0x488++0x7
line.quad 0x0 "CH4_INTSTATUS,Channelx Interrupt Status Register captures the Channelx specific interrupts"
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUSREG_36to63,DMAC Channelx Specific Interrupt Register (bits 36to63) Reserved bits - Read Only"
newline
bitfld.quad 0x0 35. "ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x UID Memory Interface Uncorrectable..,1: Channel x UID Memory Interface Uncorrectable.."
newline
bitfld.quad 0x0 34. "ECC_PROT_UIDMem_CorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x UID Memory Interface correctable..,1: Channel x UID Memory Interface correctable Error.."
newline
bitfld.quad 0x0 33. "ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface Uncorrectable..,1: Channel x FIFO Memory Interface Uncorrectable.."
newline
bitfld.quad 0x0 32. "ECC_PROT_CHMem_CorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface correctable..,1: Channel x FIFO Memory Interface correctable.."
newline
bitfld.quad 0x0 31. "CH_ABORTED_IntStat,Channel Aborted." "0: Channel is not aborted,1: Channel is aborted"
newline
bitfld.quad 0x0 30. "CH_DISABLED_IntStat,Channel Disabled." "0: Channel is not disabled,1: Channel is disabled"
newline
bitfld.quad 0x0 29. "CH_SUSPENDED_IntStat,Channel Suspended." "0: Channel is not suspended,1: Channel is suspended"
newline
bitfld.quad 0x0 28. "CH_SRC_SUSPENDED_IntStat,Channel Source Suspended." "0: Channel source is not suspended,1: Channel Source is suspended"
newline
bitfld.quad 0x0 27. "CH_LOCK_CLEARED_IntStat,Channel Lock Cleared." "0: Channel locking is not cleared,1: Channel locking is cleared"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUSREG_26,DMAC Channelx Specific Interrupt Register (bit 26) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 25. "SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error." "0: No Slave Interface Write Parity Errors,1: Slave Interface Write Parity Error detected"
newline
bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUSREG_22to24,DMAC Channelx Specific Interrupt Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error." "0: No Slave Interface Write On Hold Errors,1: Slave Interface Write On Hold Error detected"
newline
bitfld.quad 0x0 20. "SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error." "0: No Slave Interface Shadow Register Write On..,1: Slave Interface Shadow Register Write On Valid.."
newline
bitfld.quad 0x0 19. "SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error." "0: No Slave Interface Write On Channel Enabled Errors,1: Slave Interface Write On Channel Enabled Error.."
newline
bitfld.quad 0x0 18. "SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error." "0: No Slave Interface Read to Write Only Errors,1: Slave Interface Read to Write Only Error detected"
newline
bitfld.quad 0x0 17. "SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error." "0: No Slave Interface Write to Read Only Errors,1: Slave Interface Write to Read Only Error detected"
newline
bitfld.quad 0x0 16. "SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error." "0: No Slave Interface Decode errors,1: Slave Interface Decode Error detected"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUSREG_15,DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error." "0: No Multi-block transfer type Errors,1: Multi-block transfer type Error detected"
newline
bitfld.quad 0x0 13. "SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error." "0: No Shadow Register / LLI Invalid errors,1: Shadow Register / LLI Invalid error detected"
newline
bitfld.quad 0x0 12. "LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error." "0: No LLI write Slave Errors,1: LLI Write SLAVE Error detected"
newline
bitfld.quad 0x0 11. "LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error." "0: No LLI Read Slave Errors,1: LLI read Slave Error detected"
newline
bitfld.quad 0x0 10. "LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error." "0: NO LLI Write Decode Errors,1: LLI write Decode Error detected"
newline
bitfld.quad 0x0 9. "LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error." "0: NO LLI Read Decode Errors,1: LLI Read Decode Error detected"
newline
bitfld.quad 0x0 8. "DST_SLV_ERR_IntStat,Destination Slave Error." "0: No Destination Slave Errors,1: Destination Slave Errors Detected"
newline
bitfld.quad 0x0 7. "SRC_SLV_ERR_IntStat,Source Slave Error." "0: No Source Slave Errors,1: Source Slave Error Detected"
newline
bitfld.quad 0x0 6. "DST_DEC_ERR_IntStat,Destination Decode Error." "0: No destination Decode Errors,1: Destination Decode Error Detected"
newline
bitfld.quad 0x0 5. "SRC_DEC_ERR_IntStat,Source Decode Error." "0: No Source Decode Errors,1: Source Decode Error detected"
newline
bitfld.quad 0x0 4. "DST_TRANSCOMP_IntStat,Destination Transaction Completed." "0,1"
newline
bitfld.quad 0x0 3. "SRC_TRANSCOMP_IntStat,Source Transaction Completed." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUSREG_2,DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "DMA_TFR_DONE_IntStat,DMA Transfer Done." "0: DMA Transfer not completed,1: DMA Transfer Completed"
newline
bitfld.quad 0x0 0. "BLOCK_TFR_DONE_IntStat,Block Transfer Done." "0: Block Transfer not completed,1: Block Transfer completed"
group.quad 0x490++0x7
line.quad 0x0 "CH4_INTSIGNAL_ENABLEREG,This register contains fields that are used to enable the generation of port level interrupt at the channel level."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63,DMAC Channelx Interrupt Signal Enable Register (bits 36to63) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntSignal,Channel Aborted Signal Enable." "0: Disable the propagation of Channel Aborted..,1: Enable the propagation of Channel Aborted.."
newline
bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntSignal,Channel Disabled Signal Enable." "0: Disable the propagation of Channel Disabled..,1: Enable the propagation of Channel Disabled.."
newline
bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntSignal,Channel Suspended Signal Enable." "0: Disable the propagation of Channel Suspended..,1: Enable the propagation of Channel Suspended.."
newline
bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntSignal,Channel Source Suspended Signal Enable." "0: Disable the propagation of Channel Source..,1: Enable the propagation of Channel Source.."
newline
bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntSignal,Channel Lock Cleared Signal Enable." "0: Disable the propagation of Channel Lock Cleared..,1: Enable the propagation of Channel Lock Cleared.."
newline
rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26,DMAC Channelx Interrupt Signal Enable Register (bit 26) Reserved bit - Read Only" "0,1"
newline
rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntSignal,Slave Interface Write Parity Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24,DMAC Channelx Interrupt Signal Enable Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntSignal,Slave Interface Write On Hold Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal,Shadow Register Write On Valid Error Signal Enable." "0: Disable the propagation of Shadow Register Write..,1: Enable the propagation of Shadow register Write.."
newline
bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntSignal,Slave Interface Write On Channel Enabled Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntSignal,Slave Interface Read to write Only Error Signal Enable." "0: Disable the propagation of Slave Interface Read..,1: Enable the propagation of Slave Interface Read.."
newline
bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntSignal,Slave Interface Write to Read Only Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntSignal,Slave Interface Decode Error Signal Enable." "0: Disable the propagation of Slave Interface..,1: Enable the propagation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,Slave Interface Multi Block type Error Signal Enable." "0: Disable the propagation of Slave Interface Multi..,1: Enable the propagation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,Shadow register or LLI Invalid Error Signal Enable." "0: Disable the propagation of Shadow Register or..,1: Enable the propagation of Shadow Register or LLI.."
newline
bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntSignal,LLI WRITE Slave Error Signal Enable." "0: Disable the propagation of LLI WRITE Slave Error..,1: Enable the propagation of LLI WRITE Slave Error.."
newline
bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntSignal,LLI Read Slave Error Signal Enable." "0: Disable the propagation of LLI Read Slave Error..,1: Enable the propagation of LLI Read Slave Error.."
newline
bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntSignal,LLI WRITE Decode Error Signal Enable." "0: Disable the propagation of LLI WRITE Decode..,1: Enable the propagation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntSignal,LLI Read Decode Error Signal Enable." "0: Disable the propagation of LLI Read Decode Error..,1: Enable the propagation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntSignal,Destination Slave Error Signal Enable." "0: Disable the propagation of Destination Slave..,1: Enable the propagation of Destination Slave.."
newline
bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntSignal,Source Slave Error Signal Enable." "0: Disable the propagation of Source Slave Error..,1: Enable the propagation of Source Slave Error.."
newline
bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntSignal,Destination Decode Error Signal Enable." "0: Disable the propagation of Destination Decode..,1: Enable the propagation of Destination Decode.."
newline
bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntSignal,Source Decode Error Signal Enable." "0: Disable the propagation of Source Decode Error..,1: Enable the propagation of Source Decode Error.."
newline
bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntSignal,Destination Transaction Completed Signal Enable." "0: Disable the propagation of Destination..,1: Enable the propagation of Destination.."
newline
bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntSignal,Source Transaction Completed Signal Enable." "0: Disable the propagation of Source Transaction..,1: Enable the propagation of Source Transaction.."
newline
rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntSignal,DMA Transfer Done Interrupt Signal Enable." "0: Disable the propagation of DMA Transfer Done..,1: Enable the propagation of DMA Transfer Done.."
newline
bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntSignal,Block Transfer Done Interrupt Signal Enable." "0: Disable the propagation of Block Transfer Done..,1: Enable the propagation of Block Transfer Done.."
wgroup.quad 0x498++0x7
line.quad 0x0 "CH4_INTCLEARREG,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTCLEARREG_36to63,DMAC Channelx Interrupt Clear Register (bits 36to63) Reserved bit - Read Only"
newline
bitfld.quad 0x0 35. "Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat,ECC Protection Uncorrectable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 34. "Clear_ECC_PROT_UIDMem_CorrERR_IntStat,ECC Protection Correctable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 33. "Clear_ECC_PROT_CHMem_UnCorrERR_IntStat,ECC Protection Uncorrectable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 32. "Clear_ECC_PROT_CHMem_CorrERR_IntStat,ECC Protection Correctable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 31. "Clear_CH_ABORTED_IntStat,Channel Aborted Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 30. "Clear_CH_DISABLED_IntStat,Channel Disabled Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 29. "Clear_CH_SUSPENDED_IntStat,Channel Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 28. "Clear_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 27. "Clear_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTCLEARREG_26,DMAC Channelx Interrupt Clear Register (bit 26) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 25. "Clear_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTCLEARREG_22to24,DMAC Channelx Interrupt Clear Register (bits 22to24) Reserved bit - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Clear_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 20. "Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 19. "Clear_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 18. "Clear_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 17. "Clear_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 16. "Clear_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTCLEARREG_15,DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 13. "Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 12. "Clear_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 11. "Clear_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 10. "Clear_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 9. "Clear_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 8. "Clear_DST_SLV_ERR_IntStat,Destination Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 7. "Clear_SRC_SLV_ERR_IntStat,Source Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 6. "Clear_DST_DEC_ERR_IntStat,Destination Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 5. "Clear_SRC_DEC_ERR_IntStat,Source Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 4. "Clear_DST_TRANSCOMP_IntStat,Destination Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 3. "Clear_SRC_TRANSCOMP_IntStat,Source Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTCLEARREG_2,DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Clear_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 0. "Clear_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Clear Bit." "0,1"
tree.end
tree "DMAC_1"
base ad:0x10DC0000
rgroup.quad 0x0++0xF
line.quad 0x0 "DMAC_IDREG,DMAC ID Register contains a 32-bit value that is hardwired and read back by a read to the DW_axi_dmac ID Register."
hexmask.quad.long 0x0 32.--63. 1. "RSVD_DMAC_IDREG,DMAC_IDREG Reserved bits - Read Only"
newline
hexmask.quad.long 0x0 0.--31. 1. "DMAC_ID,DMAC ID Number."
line.quad 0x8 "DMAC_COMPVERREG,This register contains a 32-bit value that is hardwired and read back by a read to the DW_axi_dmac Component Version Register."
hexmask.quad.long 0x8 32.--63. 1. "RSVD_DMAC_COMPVERREG,DMAC_COMPVERREG Reserved bits - Read Only"
newline
hexmask.quad.long 0x8 0.--31. 1. "DMAC_COMPVER,DMAC Component Version Number."
group.quad 0x10++0xF
line.quad 0x0 "DMAC_CFGREG,This register is used to enable the DW_axi_dmac. which must be done before any channel"
hexmask.quad 0x0 2.--63. 1. "RSVD_DMAC_CFGREG,DMAC_CFGREG Reserved bits - Read Only"
newline
bitfld.quad 0x0 1. "INT_EN,This bit is used to globally enable the interrupt generation." "0: DW_axi_dmac Interrupts are disabled,1: DW_axi_dmac Interrupt logic is enabled"
newline
bitfld.quad 0x0 0. "DMAC_EN,This bit is used to enable the DW_axi_dmac." "0: DW_axi_dmac disabled,1: DW_axi_dmac enabled"
line.quad 0x8 "DMAC_CHENREG,This is DW_axi_dmac Channel Enable Register. If software wants to set up a new channel. it can read this register to find out which channels are currently inactive and then enable an inactive channel with the required priority."
hexmask.quad.word 0x8 48.--63. 1. "RSVD_DMAC_CHENREG,DMAC_CHENREG Reserved bits - Read Only"
newline
bitfld.quad 0x8 47. "CH8_ABORT_WE,This bit is used to write enable the Channel-8 Abort bit." "0,1"
newline
bitfld.quad 0x8 46. "CH7_ABORT_WE,This bit is used to write enable the Channel-7 Abort bit." "0,1"
newline
bitfld.quad 0x8 45. "CH6_ABORT_WE,This bit is used to write enable the Channel-6 Abort bit." "0,1"
newline
bitfld.quad 0x8 44. "CH5_ABORT_WE,This bit is used to write enable the Channel-5 Abort bit." "0,1"
newline
bitfld.quad 0x8 43. "CH4_ABORT_WE,This bit is used to write enable the Channel-4 Abort bit." "0,1"
newline
bitfld.quad 0x8 42. "CH3_ABORT_WE,This bit is used to write enable the Channel-3 Abort bit." "0,1"
newline
bitfld.quad 0x8 41. "CH2_ABORT_WE,This bit is used to write enable the Channel-2 Abort bit." "0,1"
newline
bitfld.quad 0x8 40. "CH1_ABORT_WE,This bit is used to write enable the Channel-1 Abort bit." "0,1"
newline
bitfld.quad 0x8 39. "CH8_ABORT,Channel-8 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 38. "CH7_ABORT,Channel-7 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 37. "CH6_ABORT,Channel-6 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 36. "CH5_ABORT,Channel-5 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 35. "CH4_ABORT,Channel-4 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 34. "CH3_ABORT,Channel-3 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 33. "CH2_ABORT,Channel-2 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 32. "CH1_ABORT,Channel-1 Abort Request." "0: No Channel Abort Request,1: Request for Channel Abort"
newline
bitfld.quad 0x8 31. "CH8_SUSP_WE,This bit is used as a write enable to the Channel-8 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 30. "CH7_SUSP_WE,This bit is used as a write enable to the Channel-7 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 29. "CH6_SUSP_WE,This bit is used as a write enable to the Channel-6 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 28. "CH5_SUSP_WE,This bit is used as a write enable to the Channel-5 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 27. "CH4_SUSP_WE,This bit is used as a write enable to the Channel-4 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 26. "CH3_SUSP_WE,This bit is used as a write enable to the Channel-3 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 25. "CH2_SUSP_WE,This bit is used as a write enable to the Channel-2 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 24. "CH1_SUSP_WE,This bit is used as a write enable to the Channel-1 Suspend bit. The read back value of this register bit is always 0." "0,1"
newline
bitfld.quad 0x8 23. "CH8_SUSP,Channel-8 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 22. "CH7_SUSP,Channel-7 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 21. "CH6_SUSP,Channel-6 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 20. "CH5_SUSP,Channel-5 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 19. "CH4_SUSP,Channel-4 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 18. "CH3_SUSP,Channel-3 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 17. "CH2_SUSP,Channel-2 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 16. "CH1_SUSP,Channel-1 Suspend Request." "0: No Channel Suspend Request,1: Request for Channel Suspend"
newline
bitfld.quad 0x8 15. "CH8_EN_WE,DW_axi_dmac Channel-8 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 14. "CH7_EN_WE,DW_axi_dmac Channel-7 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 13. "CH6_EN_WE,DW_axi_dmac Channel-6 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 12. "CH5_EN_WE,DW_axi_dmac Channel-5 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 11. "CH4_EN_WE,DW_axi_dmac Channel-4 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 10. "CH3_EN_WE,DW_axi_dmac Channel-3 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 9. "CH2_EN_WE,DW_axi_dmac Channel-2 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 8. "CH1_EN_WE,DW_axi_dmac Channel-1 Enable Write Enable bit." "0,1"
newline
bitfld.quad 0x8 7. "CH8_EN,This bit is used to enable the DW_axi_dmac Channel-8." "0: DW_axi_dmac Channel-8 is disabled,1: DW_axi_dmac Channel-8 is enabled"
newline
bitfld.quad 0x8 6. "CH7_EN,This bit is used to enable the DW_axi_dmac Channel-7." "0: DW_axi_dmac Channel-7 is disabled,1: DW_axi_dmac Channel-7 is enabled"
newline
bitfld.quad 0x8 5. "CH6_EN,This bit is used to enable the DW_axi_dmac Channel-6." "0: DW_axi_dmac Channel-6 is disabled,1: DW_axi_dmac Channel-6 is enabled"
newline
bitfld.quad 0x8 4. "CH5_EN,This bit is used to enable the DW_axi_dmac Channel-5." "0: DW_axi_dmac Channel-5 is disabled,1: DW_axi_dmac Channel-5 is enabled"
newline
bitfld.quad 0x8 3. "CH4_EN,This bit is used to enable the DW_axi_dmac Channel-4." "0: DW_axi_dmac Channel-4 is disabled,1: DW_axi_dmac Channel-4 is enabled"
newline
bitfld.quad 0x8 2. "CH3_EN,This bit is used to enable the DW_axi_dmac Channel-3." "0: DW_axi_dmac Channel-3 is disabled,1: DW_axi_dmac Channel-3 is enabled"
newline
bitfld.quad 0x8 1. "CH2_EN,This bit is used to enable the DW_axi_dmac Channel-2." "0: DW_axi_dmac Channel-2 is disabled,1: DW_axi_dmac Channel-2 is enabled"
newline
bitfld.quad 0x8 0. "CH1_EN,This bit is used to enable the DW_axi_dmac Channel-1." "0: DW_axi_dmac Channel-1 is disabled,1: DW_axi_dmac Channel-1 is enabled"
rgroup.quad 0x30++0x7
line.quad 0x0 "DMAC_INTSTATUSREG,DMAC Interrupt Status Register captures the combined channel interrupt for each channel and Combined common register block interrupt. This register is present provided number of DMA channels are greater than 8."
hexmask.quad 0x0 17.--63. 1. "RSVD_DMAC_INTSTATUSREG_63to17,DMAC Interrupt Status Register (bits 63to17) Reserved bits - Read Only"
newline
bitfld.quad 0x0 16. "CommonReg_IntStat,Common Register Interrupt Status Bit." "0,1"
newline
hexmask.quad.byte 0x0 8.--15. 1. "RSVD_DMAC_INTSTATUSREG,DMAC Interrupt Status Register (bits 15to8) Reserved bits - Read Only"
newline
bitfld.quad 0x0 7. "CH8_IntStat,Channel 8 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 6. "CH7_IntStat,Channel 7 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 5. "CH6_IntStat,Channel 6 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 4. "CH5_IntStat,Channel 5 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 3. "CH4_IntStat,Channel 4 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 2. "CH3_IntStat,Channel 3 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 1. "CH2_IntStat,Channel 2 Interrupt Status Bit." "0,1"
newline
bitfld.quad 0x0 0. "CH1_IntStat,Channel 1 Interrupt Status Bit." "0,1"
wgroup.quad 0x38++0x7
line.quad 0x0 "DMAC_COMMONREG_INTCLEARREG,Writing 1 to specific field clears the corresponding field in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)."
hexmask.quad 0x0 21.--63. 1. "RSVD_DMAC_COMMONREG_INTCLEARREG_63to21,DMAC Common Register Interrupt Clear Register (bits 63to21) Reserved bits - Read Only"
newline
bitfld.quad 0x0 20. "Clear_MXIF2_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 19. "Clear_MXIF2_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 18. "Clear_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 17. "Clear_MXIF2_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 16. "Clear_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 15. "Clear_MXIF2_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 14. "Clear_MXIF1_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 13. "Clear_MXIF1_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 12. "Clear_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 11. "Clear_MXIF1_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 10. "Clear_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 9. "Clear_MXIF1_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection related Correctable Error Interrupt Clear bit." "0,1"
newline
bitfld.quad 0x0 8. "Clear_SLVIF_UndefinedReg_DEC_ERR_IntStat,Slave Interface Undefined register Decode Error Interrupt clear Bit." "0,1"
newline
bitfld.quad 0x0 7. "Clear_SLVIF_CommonReg_WRPARITY_ERR_IntStat,Slave Interface Common Register Write Parity Error Interrupt clear Bit." "0,1"
newline
bitfld.quad 0x0 4.--6. "RSVD_DMAC_COMMONREG_INTCLEARREG_6to4,DMAC Common Register Interrupt Clear Register (bits 6to4) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 3. "Clear_SLVIF_CommonReg_WrOnHold_ERR_IntStat,Slave Interface Common Register Write On Hold Error Interrupt clear Bit." "0,1"
newline
bitfld.quad 0x0 2. "Clear_SLVIF_CommonReg_RD2WO_ERR_IntStat,Slave Interface Common Register Read to Write only Error Interrupt clear Bit." "0,1"
newline
bitfld.quad 0x0 1. "Clear_SLVIF_CommonReg_WR2RO_ERR_IntStat,Slave Interface Common Register Write to Read only Error Interrupt clear Bit." "0,1"
newline
bitfld.quad 0x0 0. "Clear_SLVIF_CommonReg_DEC_ERR_IntStat,Slave Interface Common Register Decode Error Interrupt clear Bit." "0,1"
group.quad 0x40++0xF
line.quad 0x0 "DMAC_COMMONREG_INTSTATUS_ENABLEREG,Writing 1 to specific field enables the corresponding interrupt status generation in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)."
hexmask.quad 0x0 21.--63. 1. "RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_63to21,DMAC Common Register Interrupt Status Enable Register (bits 63to21) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 20. "Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 19. "Enable_MXIF2_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 18. "Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 17. "Enable_MXIF2_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 16. "Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 15. "Enable_MXIF2_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 14. "Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 13. "Enable_MXIF1_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 12. "Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 11. "Enable_MXIF1_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 10. "Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
newline
rbitfld.quad 0x0 9. "Enable_MXIF1_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
newline
bitfld.quad 0x0 8. "Enable_SLVIF_UndefinedReg_DEC_ERR_IntStat,Slave Interface Undefined register Decode Error Interrupt Status enable Bit." "0,1"
newline
rbitfld.quad 0x0 7. "Enable_SLVIF_CommonReg_WRPARITY_ERR_IntStat,Slave Interface Common Register Write Parity Error Interrupt Status Enable Bit." "0,1"
newline
rbitfld.quad 0x0 4.--6. "RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_6to4,DMAC Common Register Interrupt Status Enable Register (bits 6to4) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 3. "Enable_SLVIF_CommonReg_WrOnHold_ERR_IntStat,Slave Interface Common Register Write On Hold Error Interrupt Status Enable Bit." "0,1"
newline
bitfld.quad 0x0 2. "Enable_SLVIF_CommonReg_RD2WO_ERR_IntStat,Slave Interface Common Register Read to Write only Error Interrupt Status Enable Bit." "0,1"
newline
bitfld.quad 0x0 1. "Enable_SLVIF_CommonReg_WR2RO_ERR_IntStat,Slave Interface Common Register Write to Read only Error Interrupt Status Enable Bit." "0,1"
newline
bitfld.quad 0x0 0. "Enable_SLVIF_CommonReg_DEC_ERR_IntStat,Slave Interface Common Register Decode Error Interrupt Status Enable Bit." "0,1"
line.quad 0x8 "DMAC_COMMONREG_INTSIGNAL_ENABLEREG,Writing 1 to specific field will propagate the corresponding interrupt status in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg) to generate an port level interrupt."
hexmask.quad 0x8 21.--63. 1. "RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_63to21,DMAC Common Register Interrupt Signal Enable Register (bits 63to21) Reserved bits - Read Only"
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rbitfld.quad 0x8 20. "Enable_MXIF2_BCH_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 2 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 19. "Enable_MXIF2_BCH_EccPROT_CorrERR_IntSignal,AXI Master Interface 2 Write Response Channel ECC Protection related Correctable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 18. "Enable_MXIF2_RCH1_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 17. "Enable_MXIF2_RCH1_EccPROT_CorrERR_IntSignal,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 16. "Enable_MXIF2_RCH0_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 2 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 15. "Enable_MXIF2_RCH0_EccPROT_CorrERR_IntSignal,AXI Master Interface 2 Read Channel (Data) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 14. "Enable_MXIF1_BCH_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 1 Write Response Channel ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 13. "Enable_MXIF1_BCH_EccPROT_CorrERR_IntSignal,AXI Master Interface 1 Write Response Channel ECC Protection related Correctable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 12. "Enable_MXIF1_RCH1_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 11. "Enable_MXIF1_RCH1_EccPROT_CorrERR_IntSignal,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 10. "Enable_MXIF1_RCH0_EccPROT_UnCorrERR_IntSignal,AXI Master Interface 1 Read Channel (Data) ECC Protection related Uncorrectable Error Interrupt Status bit." "0,1"
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rbitfld.quad 0x8 9. "Enable_MXIF1_RCH0_EccPROT_CorrERR_IntSignal,AXI Master Interface 1 Read Channel (Data) ECC Protection related Correctable Error Interrupt Status bit." "0,1"
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bitfld.quad 0x8 8. "Enable_SLVIF_UndefinedReg_DEC_ERR_IntSignal,Slave Interface Undefined register Decode Error Interrupt Signal Enable Bit." "0,1"
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rbitfld.quad 0x8 7. "Enable_SLVIF_CommonReg_WRPARITY_ERR_IntSignal,Slave Interface Write Parity Error Interrupt Signal Enable Bit." "0,1"
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rbitfld.quad 0x8 4.--6. "RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_6to4,DMAC Common Register Interrupt Signal Enable Register (bits 6to4) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x8 3. "Enable_SLVIF_CommonReg_WrOnHold_ERR_IntSignal,Slave Interface Common Register Write On Hold Error Interrupt Signal Enable Bit." "0,1"
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bitfld.quad 0x8 2. "Enable_SLVIF_CommonReg_RD2WO_ERR_IntSignal,Slave Interface Common Register Read to Write only Error Interrupt Signal Enable Bit." "0,1"
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bitfld.quad 0x8 1. "Enable_SLVIF_CommonReg_WR2RO_ERR_IntSignal,Slave Interface Common Register Write to Read only Error Interrupt Signal Enable Bit." "0,1"
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bitfld.quad 0x8 0. "Enable_SLVIF_CommonReg_DEC_ERR_IntSignal,Slave Interface Common Register Decode Error Interrupt Signal Enable Bit." "0,1"
rgroup.quad 0x50++0x7
line.quad 0x0 "DMAC_COMMONREG_INTSTATUSREG,This Register captures Slave interface access errors."
hexmask.quad 0x0 21.--63. 1. "RSVD_DMAC_COMMONREG_INTSTATUSREG_63to21,DMAC Common Register Interrupt Signal Enable Register (bits 63to21) Reserved bits - Read Only"
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bitfld.quad 0x0 20. "MXIF2_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 2 Write Response Channel..,1: AXI Master 2 Write Response Channel.."
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bitfld.quad 0x0 19. "MXIF2_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Write Response Channel ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 2 Write Response Channel..,1: AXI Master 2 Write Response Channel Correctable.."
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bitfld.quad 0x0 18. "MXIF2_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 2 Read Channel Control signals..,1: AXI Master 2 Read Channel Control signals.."
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bitfld.quad 0x0 17. "MXIF2_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Other Control signals) ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 2 Read Channel Control signlas..,1: AXI Master 2 Read Channel Control signals.."
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bitfld.quad 0x0 16. "MXIF2_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 2 Read Channel Data related..,1: AXI Master 2 Read Channel Data related.."
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bitfld.quad 0x0 15. "MXIF2_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 2 Read Channel (Data) ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 2 Read Channel Data related..,1: AXI Master 2 Read Channel Data related.."
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bitfld.quad 0x0 14. "MXIF1_BCH_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 1 Write Response Channel..,1: AXI Master 1 Write Response Channel.."
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bitfld.quad 0x0 13. "MXIF1_BCH_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Write Response Channel ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 1 Write Response Channel..,1: AXI Master 1 Write Response Channel Correctable.."
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bitfld.quad 0x0 12. "MXIF1_RCH1_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 1 Read Channel Control signals..,1: AXI Master 1 Read Channel Control signals.."
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bitfld.quad 0x0 11. "MXIF1_RCH1_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Other Control signals) ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 1 Read Channel Control signlas..,1: AXI Master 1 Read Channel Control signals.."
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bitfld.quad 0x0 10. "MXIF1_RCH0_EccPROT_UnCorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection Uncorrectable Error Interrupt Status bit." "0: No AXI Master 1 Read Channel Data related..,1: AXI Master 1 Read Channel Data related.."
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bitfld.quad 0x0 9. "MXIF1_RCH0_EccPROT_CorrERR_IntStat,AXI Master Interface 1 Read Channel (Data) ECC Protection Correctable Error Interrupt Status bit." "0: No AXI Master 1 Read Channel Data related..,1: AXI Master 1 Read Channel Data related.."
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bitfld.quad 0x0 8. "SLVIF_UndefinedReg_DEC_ERR_IntStat,Slave Interface Undefined register Decode Error Interrupt Signal Enable Bit." "0: No Slave Interface Decode Errors,1: Slave Interface Decode Error detected"
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bitfld.quad 0x0 7. "SLVIF_CommonReg_WRPARITY_ERR_IntStat,Slave Interface Common Register Write Parity Error Interrupt Status Bit." "0: No Common Register Space Write Parity Error,1: Common Register Space Write Parity Error detected"
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bitfld.quad 0x0 4.--6. "RSVD_DMAC_COMMONREG_INTSTATUSREG_6to4,DMAC Common Register Interrupt Status Register (bits 6to4) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 3. "SLVIF_CommonReg_WrOnHold_ERR_IntStat,Slave Interface Common Register Write On Hold Error Interrupt Status Bit." "0: No Slave Interface Common Register Write On Hold..,1: Slave Interface Common Register Write On Hold.."
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bitfld.quad 0x0 2. "SLVIF_CommonReg_RD2WO_ERR_IntStat,Slave Interface Common Register Read to Write only Error Interrupt Status bit." "0: No Slave Interface Read to Write Only Errors,1: Slave Interface Read to Write Only Error detected"
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bitfld.quad 0x0 1. "SLVIF_CommonReg_WR2RO_ERR_IntStat,Slave Interface Common Register Write to Read Only Error Interrupt Status bit." "0: No Slave Interface Write to Read Only Errors,1: Slave Interface Write to Read Only Error detected"
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bitfld.quad 0x0 0. "SLVIF_CommonReg_DEC_ERR_IntStat,Slave Interface Common Register Decode Error Interrupt Status Bit." "0: No Slave Interface Decode Errors,1: Slave Interface Decode Error detected"
group.quad 0x58++0xF
line.quad 0x0 "DMAC_RESETREG,This register is used to initiate the Software Reset to DW_axi_dmac."
hexmask.quad 0x0 1.--63. 1. "RSVD_DMAC_ResetReg_1to63,DMAC_ResetReg (bits 1to63) Reserved bits - Read Only"
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bitfld.quad 0x0 0. "DMAC_RST,DMAC Reset Request bit" "0,1"
line.quad 0x8 "DMAC_LOWPOWER_CFGREG,This register contains the fields that configures the Context Sensitive Low Power feature. This register should be programmed prior to enabling the channel."
hexmask.quad.byte 0x8 56.--63. 1. "RSVD_DMAC_LOWPOWER_CFGREG_63to56,DMAC_LOWPOWER_CFGREG (bits 56to63) Reserved bits - Read Only"
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hexmask.quad.byte 0x8 48.--55. 1. "MXIF_LPDLY,Defines the load value to be programmed into the AXI Master Interface low power delay counter."
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hexmask.quad.byte 0x8 40.--47. 1. "SBIU_LPDLY,Defines the load value to be programmed into the SBIU low power delay counter."
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hexmask.quad.byte 0x8 32.--39. 1. "GLCH_LPDLY,Defines the load value to be programmed into the Global and DMA Channel low power delay counter."
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hexmask.quad.long 0x8 4.--31. 1. "RSVD_DMAC_LOWPOWER_CFGREG_31to4,DMAC_LOWPOWER_CFGREG (bits 4to31) Reserved bits - Read Only"
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bitfld.quad 0x8 3. "MXIF_CSLP_EN,AXI Master Interface Context Sensitive Low Power feature enable." "0,1"
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bitfld.quad 0x8 2. "SBIU_CSLP_EN,SBIU Context Sensitive Low Power feature enable." "0,1"
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bitfld.quad 0x8 1. "CHNL_CSLP_EN,DMA Channel Context Sensitive Low Power feature enable." "0,1"
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bitfld.quad 0x8 0. "GBL_CSLP_EN,Global Context Sensitive Low Power feature enable." "0,1"
group.quad 0x100++0x2F
line.quad 0x0 "CH1_SAR,The starting source address is programmed by software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While"
hexmask.quad 0x0 0.--63. 1. "SAR,Current Source Address of DMA transfer."
line.quad 0x8 "CH1_DAR,The starting destination address is programmed by the software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer."
hexmask.quad 0x8 0.--63. 1. "DAR,Current Destination Address of DMA transfer."
line.quad 0x10 "CH1_BLOCK_TS,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size."
hexmask.quad 0x10 22.--63. 1. "RSVD_DMAC_CHx_BLOCK_TSREG_63to22,DMAC Channelx Block Transfer Size Register (bits 63to22) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x10 0.--21. 1. "BLOCK_TS,Block Transfer Size."
line.quad 0x18 "CH1_CTL,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.."
bitfld.quad 0x18 63. "SHADOWREG_OR_LLI_VALID,Shadow Register content/Linked List Item valid." "0: Shadow Register content/LLI is invalid,1: Last Shadow Register/LLI is valid"
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bitfld.quad 0x18 62. "SHADOWREG_OR_LLI_LAST,Last Shadow Register/Linked List Item." "0: Not last Shadow Register/LLI,1: Last Shadow Register/LLI"
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rbitfld.quad 0x18 59.--61. "RSVD_DMAC_CHx_CTL_59to61,DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 58. "IOC_BlkTfr,Interrupt On completion of Block Transfer" "0,1"
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rbitfld.quad 0x18 57. "DST_STAT_EN,Destination Status Enable" "0,1"
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rbitfld.quad 0x18 56. "SRC_STAT_EN,Source Status Enable" "0,1"
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hexmask.quad.byte 0x18 48.--55. 1. "AWLEN,Destination Burst Length"
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bitfld.quad 0x18 47. "AWLEN_EN,Destination Burst Length Enable" "0,1"
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hexmask.quad.byte 0x18 39.--46. 1. "ARLEN,Source Burst Length"
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bitfld.quad 0x18 38. "ARLEN_EN,Source Burst Length Enable" "0,1"
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bitfld.quad 0x18 35.--37. "AW_PROT,AXI 'aw_prot' signal" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 32.--34. "AR_PROT,AXI 'ar_prot' signal" "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x18 31. "RSVD_DMAC_CHx_CTL_31,DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 30. "NonPosted_LastWrite_En,Non Posted Last Write Enable" "0: Posted writes may be used throughout the block..,1: Posted writes may be used till the end of the.."
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hexmask.quad.byte 0x18 26.--29. 1. "AW_CACHE,AXI 'aw_cache' signal"
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hexmask.quad.byte 0x18 22.--25. 1. "AR_CACHE,AXI 'ar_cache' signal"
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hexmask.quad.byte 0x18 18.--21. 1. "DST_MSIZE,Destination Burst Transaction Length."
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hexmask.quad.byte 0x18 14.--17. 1. "SRC_MSIZE,Source Burst Transaction Length."
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bitfld.quad 0x18 11.--13. "DST_TR_WIDTH,Destination Transfer Width." "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 8.--10. "SRC_TR_WIDTH,Source Transfer Width." "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x18 7. "RSVD_DMAC_CHx_CTL_7,DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 6. "DINC,Destination Address Increment." "0: Increment,1: No Change"
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rbitfld.quad 0x18 5. "RSVD_DMAC_CHx_CTL_5,DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 4. "SINC,Source Address Increment." "0: Increment,1: No Change"
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rbitfld.quad 0x18 3. "RSVD_DMAC_CHx_CTL_3,DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only" "0,1"
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rbitfld.quad 0x18 2. "DMS,Destination Master Select." "0: AXI master 1,1: AXI Master 2"
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rbitfld.quad 0x18 1. "RSVD_DMAC_CHx_CTL_1,DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only" "0,1"
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rbitfld.quad 0x18 0. "SMS,Source Master Select." "0: AXI master 1,1: AXI Master 2"
line.quad 0x20 "CH1_CFG2,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel."
rbitfld.quad 0x20 63. "RSVD_DMAC_CHx_CFG_63,DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 59.--62. 1. "DST_OSR_LMT,Destination Outstanding Request Limit"
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hexmask.quad.byte 0x20 55.--58. 1. "SRC_OSR_LMT,Source Outstanding Request Limit"
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bitfld.quad 0x20 53.--54. "LOCK_CH_L,Channel Lock Level" "0: Over complete DMA transfer,1: Over DMA block transfer,?,?"
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bitfld.quad 0x20 52. "LOCK_CH,Channel Lock bit" "0,1"
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hexmask.quad.byte 0x20 47.--51. 1. "CH_PRIOR,Channel Priority"
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hexmask.quad.byte 0x20 39.--46. 1. "RSVD_DMAC_CHx_CFG_39to46,DMAC Channelx Transfer Configuration Register (bits 39to46) Reserved bits - Read Only"
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rbitfld.quad 0x20 38. "DST_HWHS_POL,Destination Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
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rbitfld.quad 0x20 37. "SRC_HWHS_POL,Source Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
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bitfld.quad 0x20 36. "HS_SEL_DST,Destination Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
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bitfld.quad 0x20 35. "HS_SEL_SRC,Source Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
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bitfld.quad 0x20 32.--34. "TT_FC,Transfer Type and Flow Control." "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x20 29.--31. "RSVD_DMAC_CHx_CFG_29to31,DMAC Channelx Transfer Configuration Register (bits 29to31) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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hexmask.quad.byte 0x20 25.--28. 1. "WR_UID,Defines the number of AXI Unique ID's supported for the AXI Write Channel. The value programmed must be less than or equal to DMAX_CH(x)_WR_UID. Otherwise  it is limited by the value DMAX_CH(x)_WR_UID."
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rbitfld.quad 0x20 22.--24. "RSVD_DMAC_CHx_CFG_22to24,DMAC Channelx Transfer Configuration Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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hexmask.quad.byte 0x20 18.--21. 1. "RD_UID,Defines the number of AXI Unique ID's supported for the AXI Read Channel. The value programmed must be less than or equal to DMAX_CH(x)_RD_UID. Otherwise  it is limited by the value DMAX_CH(x)_RD_UID."
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rbitfld.quad 0x20 17. "RSVD_DMAC_CHx_CFG_17,DMAC Channelx Transfer Configuration Register (bit 17) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 11.--16. 1. "DST_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0;"
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rbitfld.quad 0x20 10. "RSVD_DMAC_CHx_CFG_10,DMAC Channelx Transfer Configuration Register (bit 10) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 4.--9. 1. "SRC_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise "
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rbitfld.quad 0x20 2.--3. "DST_MULTBLK_TYPE,Destination Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
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rbitfld.quad 0x20 0.--1. "SRC_MULTBLK_TYPE,Source Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
line.quad 0x28 "CH1_LLP,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the"
hexmask.quad 0x28 6.--63. 1. "LOC,Starting Address Memory of LLI block"
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hexmask.quad.byte 0x28 1.--5. 1. "RSVD_DMAC_CHx_LLP_1to5,DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only"
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rbitfld.quad 0x28 0. "LMS,LLI master Select" "0: AXI Master 1,1: AXI Master 2"
rgroup.quad 0x130++0x7
line.quad 0x0 "CH1_STATUSREG,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx."
hexmask.quad.tbyte 0x0 47.--63. 1. "RSVD_DMAC_CHx_STATUSREG_47to63,DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 32.--46. 1. "DATA_LEFT_IN_FIFO,Data Left in FIFO."
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hexmask.quad.word 0x0 22.--31. 1. "RSVD_DMAC_CHx_STATUSREG_22to31,DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x0 0.--21. 1. "CMPLTD_BLK_TFR_SIZE,Completed Block Transfer Size."
group.quad 0x138++0xF
line.quad 0x0 "CH1_SWHSSRCREG,Channelx Software handshake Source Register."
hexmask.quad 0x0 6.--63. 1. "RSVD_DMAC_CHx_SWHSSRCREG_6to63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x0 5. "SWHS_LST_SRC_WE,Write Enable bit for Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 4. "SWHS_LST_SRC,Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 3. "SWHS_SGLREQ_SRC_WE,Write Enable bit for Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 2. "SWHS_SGLREQ_SRC,Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 1. "SWHS_REQ_SRC_WE,Write Enable bit for Software Handshake Request for Channel Source." "0,1"
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bitfld.quad 0x0 0. "SWHS_REQ_SRC,Software Handshake Request for Channel Source." "0,1"
line.quad 0x8 "CH1_SWHSDSTREG,Channelx Software handshake Destination Register."
hexmask.quad 0x8 6.--63. 1. "RSVD_DMAC_CHx_SWHSDSTREG_6to63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x8 5. "SWHS_LST_DST_WE,Write Enable bit for Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 4. "SWHS_LST_DST,Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 3. "SWHS_SGLREQ_DST_WE,Write Enable bit for Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 2. "SWHS_SGLREQ_DST,Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 1. "SWHS_REQ_DST_WE,Write Enable bit for Software Handshake Request for Channel Destination." "0,1"
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bitfld.quad 0x8 0. "SWHS_REQ_DST,Software Handshake Request for Channel Destination." "0,1"
wgroup.quad 0x148++0x7
line.quad 0x0 "CH1_BLK_TFR_RESUMEREQREG,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer."
hexmask.quad 0x0 1.--63. 1. "RSVD_DMAC_CHx_BLK_TFR_RESUMEREQREG_1to63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only"
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bitfld.quad 0x0 0. "BLK_TFR_RESUMEREQ,Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer." "0,1"
group.quad 0x150++0xF
line.quad 0x0 "CH1_AXI_IDREG,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad.long 0x0 32.--63. 1. "RSVD_DMAC_CHx_AXI_IDREG_32to63,DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 20.--31. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm32to63,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 16.--19. 1. "AXI_WRITE_ID_SUFFIX,AXI Write ID Suffix."
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hexmask.quad.word 0x0 4.--15. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm1to31,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 0.--3. 1. "AXI_READ_ID_SUFFIX,AXI Read ID Suffix"
line.quad 0x8 "CH1_AXI_QOSREG,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad 0x8 8.--63. 1. "RSVD_DMAC_CHx_AXI_QOSREG_8to63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only"
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hexmask.quad.byte 0x8 4.--7. 1. "AXI_ARQOS,AXI ARQOS."
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hexmask.quad.byte 0x8 0.--3. 1. "AXI_AWQOS,AXI AWQOS."
group.quad 0x180++0x7
line.quad 0x0 "CH1_INTSTATUS_ENABLEREG,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH1_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63,DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
newline
rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
newline
rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation Channel x Channel Memory.."
newline
rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntStat,Channel Aborted Status Enable." "0: Disable the generation of Channel Aborted..,1: Enable the generation of Channel Aborted.."
newline
bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntStat,Channel Disabled Status Enable." "0: Disable the generation of Channel Disabled..,1: Enable the generation of Channel Disabled.."
newline
bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntStat,Channel Suspended Status Enable." "0: Disable the generation of Channel Suspended..,1: Enable the generation of Channel Suspended.."
newline
bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Status Enable." "0: Disable the generation of Channel Source..,1: Enable the generation of Channel Source.."
newline
bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Status Enable." "0: Disable the generation of Channel LOCK CLEARED..,1: Enable the generation of Channel LOCK CLEARED.."
newline
rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26,DMAC Channelx Interrupt Status Register (bit 26) Reserved bit - Read Only" "0,1"
newline
rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24,DMAC Channelx Interrupt Status Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Status Enable." "0: Disable the generation of Shadow Register Write..,1: Enable the generation of Shadow register Write.."
newline
bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Status Enable." "0: Disable the generation of Slave Interface Read..,1: Enable the generation of Slave Interface Read to.."
newline
bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Status Enable." "0: Disable the generation of Slave Interface Decode..,1: Enable the generation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Status Enable." "0: Disable the generation of Slave Interface Multi..,1: Enable the generation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Status Enable." "0: Disable the generation of Shadow Register or LLI..,1: Enable the generation of Shadow Register or LLI.."
newline
bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Status Enable." "0: Disable the generation of LLI WRITE Slave Error..,1: Enable the generation of LLI WRITE Slave Error.."
newline
bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Status Enable." "0: Disable the generation of LLI Read Slave Error..,1: Enable the generation of LLI Read Slave Error.."
newline
bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Status Enable." "0: Disable the generation of LLI WRITE Decode Error..,1: Enable the generation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Status Enable." "0: Disable the generation of LLI Read Decode Error..,1: Enable the generation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntStat,Destination Slave Error Status Enable." "0: Disable the generation of Destination Slave..,1: Enable the generation of Destination Slave Error.."
newline
bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntStat,Source Slave Error Status Enable." "0: Disable the generation of Source Slave Error..,1: Enable the generation of Source Slave Error.."
newline
bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntStat,Destination Decode Error Status Enable." "0: Disable the generation of Destination Decode..,1: Enable the generation of Destination Decode.."
newline
bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntStat,Source Decode Error Status Enable." "0: Disable the generation of Source Decode Error..,1: Enable the generation of Source Decode Error.."
newline
bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntStat,Destination Transaction Completed Status Enable." "0: Disable the generation of Destination..,1: Enable the generation of Destination Transaction.."
newline
bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntStat,Source Transaction Completed Status Enable." "0: Disable the generation of Source Transaction..,1: Enable the generation of Source Transaction.."
newline
rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Status Enable." "0: Disable the generation of DMA Transfer Done..,1: Enable the generation of DMA Transfer Done.."
newline
bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Status Enable." "0: Disable the generation of Block Transfer Done..,1: Enable the generation of Block Transfer Done.."
rgroup.quad 0x188++0x7
line.quad 0x0 "CH1_INTSTATUS,Channelx Interrupt Status Register captures the Channelx specific interrupts"
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUSREG_36to63,DMAC Channelx Specific Interrupt Register (bits 36to63) Reserved bits - Read Only"
newline
bitfld.quad 0x0 35. "ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x UID Memory Interface Uncorrectable..,1: Channel x UID Memory Interface Uncorrectable.."
newline
bitfld.quad 0x0 34. "ECC_PROT_UIDMem_CorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x UID Memory Interface correctable..,1: Channel x UID Memory Interface correctable Error.."
newline
bitfld.quad 0x0 33. "ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface Uncorrectable..,1: Channel x FIFO Memory Interface Uncorrectable.."
newline
bitfld.quad 0x0 32. "ECC_PROT_CHMem_CorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface correctable..,1: Channel x FIFO Memory Interface correctable.."
newline
bitfld.quad 0x0 31. "CH_ABORTED_IntStat,Channel Aborted." "0: Channel is not aborted,1: Channel is aborted"
newline
bitfld.quad 0x0 30. "CH_DISABLED_IntStat,Channel Disabled." "0: Channel is not disabled,1: Channel is disabled"
newline
bitfld.quad 0x0 29. "CH_SUSPENDED_IntStat,Channel Suspended." "0: Channel is not suspended,1: Channel is suspended"
newline
bitfld.quad 0x0 28. "CH_SRC_SUSPENDED_IntStat,Channel Source Suspended." "0: Channel source is not suspended,1: Channel Source is suspended"
newline
bitfld.quad 0x0 27. "CH_LOCK_CLEARED_IntStat,Channel Lock Cleared." "0: Channel locking is not cleared,1: Channel locking is cleared"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUSREG_26,DMAC Channelx Specific Interrupt Register (bit 26) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 25. "SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error." "0: No Slave Interface Write Parity Errors,1: Slave Interface Write Parity Error detected"
newline
bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUSREG_22to24,DMAC Channelx Specific Interrupt Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error." "0: No Slave Interface Write On Hold Errors,1: Slave Interface Write On Hold Error detected"
newline
bitfld.quad 0x0 20. "SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error." "0: No Slave Interface Shadow Register Write On..,1: Slave Interface Shadow Register Write On Valid.."
newline
bitfld.quad 0x0 19. "SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error." "0: No Slave Interface Write On Channel Enabled Errors,1: Slave Interface Write On Channel Enabled Error.."
newline
bitfld.quad 0x0 18. "SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error." "0: No Slave Interface Read to Write Only Errors,1: Slave Interface Read to Write Only Error detected"
newline
bitfld.quad 0x0 17. "SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error." "0: No Slave Interface Write to Read Only Errors,1: Slave Interface Write to Read Only Error detected"
newline
bitfld.quad 0x0 16. "SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error." "0: No Slave Interface Decode errors,1: Slave Interface Decode Error detected"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUSREG_15,DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error." "0: No Multi-block transfer type Errors,1: Multi-block transfer type Error detected"
newline
bitfld.quad 0x0 13. "SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error." "0: No Shadow Register / LLI Invalid errors,1: Shadow Register / LLI Invalid error detected"
newline
bitfld.quad 0x0 12. "LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error." "0: No LLI write Slave Errors,1: LLI Write SLAVE Error detected"
newline
bitfld.quad 0x0 11. "LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error." "0: No LLI Read Slave Errors,1: LLI read Slave Error detected"
newline
bitfld.quad 0x0 10. "LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error." "0: NO LLI Write Decode Errors,1: LLI write Decode Error detected"
newline
bitfld.quad 0x0 9. "LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error." "0: NO LLI Read Decode Errors,1: LLI Read Decode Error detected"
newline
bitfld.quad 0x0 8. "DST_SLV_ERR_IntStat,Destination Slave Error." "0: No Destination Slave Errors,1: Destination Slave Errors Detected"
newline
bitfld.quad 0x0 7. "SRC_SLV_ERR_IntStat,Source Slave Error." "0: No Source Slave Errors,1: Source Slave Error Detected"
newline
bitfld.quad 0x0 6. "DST_DEC_ERR_IntStat,Destination Decode Error." "0: No destination Decode Errors,1: Destination Decode Error Detected"
newline
bitfld.quad 0x0 5. "SRC_DEC_ERR_IntStat,Source Decode Error." "0: No Source Decode Errors,1: Source Decode Error detected"
newline
bitfld.quad 0x0 4. "DST_TRANSCOMP_IntStat,Destination Transaction Completed." "0,1"
newline
bitfld.quad 0x0 3. "SRC_TRANSCOMP_IntStat,Source Transaction Completed." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUSREG_2,DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "DMA_TFR_DONE_IntStat,DMA Transfer Done." "0: DMA Transfer not completed,1: DMA Transfer Completed"
newline
bitfld.quad 0x0 0. "BLOCK_TFR_DONE_IntStat,Block Transfer Done." "0: Block Transfer not completed,1: Block Transfer completed"
group.quad 0x190++0x7
line.quad 0x0 "CH1_INTSIGNAL_ENABLEREG,This register contains fields that are used to enable the generation of port level interrupt at the channel level."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63,DMAC Channelx Interrupt Signal Enable Register (bits 36to63) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntSignal,Channel Aborted Signal Enable." "0: Disable the propagation of Channel Aborted..,1: Enable the propagation of Channel Aborted.."
newline
bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntSignal,Channel Disabled Signal Enable." "0: Disable the propagation of Channel Disabled..,1: Enable the propagation of Channel Disabled.."
newline
bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntSignal,Channel Suspended Signal Enable." "0: Disable the propagation of Channel Suspended..,1: Enable the propagation of Channel Suspended.."
newline
bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntSignal,Channel Source Suspended Signal Enable." "0: Disable the propagation of Channel Source..,1: Enable the propagation of Channel Source.."
newline
bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntSignal,Channel Lock Cleared Signal Enable." "0: Disable the propagation of Channel Lock Cleared..,1: Enable the propagation of Channel Lock Cleared.."
newline
rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26,DMAC Channelx Interrupt Signal Enable Register (bit 26) Reserved bit - Read Only" "0,1"
newline
rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntSignal,Slave Interface Write Parity Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24,DMAC Channelx Interrupt Signal Enable Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntSignal,Slave Interface Write On Hold Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal,Shadow Register Write On Valid Error Signal Enable." "0: Disable the propagation of Shadow Register Write..,1: Enable the propagation of Shadow register Write.."
newline
bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntSignal,Slave Interface Write On Channel Enabled Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntSignal,Slave Interface Read to write Only Error Signal Enable." "0: Disable the propagation of Slave Interface Read..,1: Enable the propagation of Slave Interface Read.."
newline
bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntSignal,Slave Interface Write to Read Only Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntSignal,Slave Interface Decode Error Signal Enable." "0: Disable the propagation of Slave Interface..,1: Enable the propagation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,Slave Interface Multi Block type Error Signal Enable." "0: Disable the propagation of Slave Interface Multi..,1: Enable the propagation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,Shadow register or LLI Invalid Error Signal Enable." "0: Disable the propagation of Shadow Register or..,1: Enable the propagation of Shadow Register or LLI.."
newline
bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntSignal,LLI WRITE Slave Error Signal Enable." "0: Disable the propagation of LLI WRITE Slave Error..,1: Enable the propagation of LLI WRITE Slave Error.."
newline
bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntSignal,LLI Read Slave Error Signal Enable." "0: Disable the propagation of LLI Read Slave Error..,1: Enable the propagation of LLI Read Slave Error.."
newline
bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntSignal,LLI WRITE Decode Error Signal Enable." "0: Disable the propagation of LLI WRITE Decode..,1: Enable the propagation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntSignal,LLI Read Decode Error Signal Enable." "0: Disable the propagation of LLI Read Decode Error..,1: Enable the propagation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntSignal,Destination Slave Error Signal Enable." "0: Disable the propagation of Destination Slave..,1: Enable the propagation of Destination Slave.."
newline
bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntSignal,Source Slave Error Signal Enable." "0: Disable the propagation of Source Slave Error..,1: Enable the propagation of Source Slave Error.."
newline
bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntSignal,Destination Decode Error Signal Enable." "0: Disable the propagation of Destination Decode..,1: Enable the propagation of Destination Decode.."
newline
bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntSignal,Source Decode Error Signal Enable." "0: Disable the propagation of Source Decode Error..,1: Enable the propagation of Source Decode Error.."
newline
bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntSignal,Destination Transaction Completed Signal Enable." "0: Disable the propagation of Destination..,1: Enable the propagation of Destination.."
newline
bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntSignal,Source Transaction Completed Signal Enable." "0: Disable the propagation of Source Transaction..,1: Enable the propagation of Source Transaction.."
newline
rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntSignal,DMA Transfer Done Interrupt Signal Enable." "0: Disable the propagation of DMA Transfer Done..,1: Enable the propagation of DMA Transfer Done.."
newline
bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntSignal,Block Transfer Done Interrupt Signal Enable." "0: Disable the propagation of Block Transfer Done..,1: Enable the propagation of Block Transfer Done.."
wgroup.quad 0x198++0x7
line.quad 0x0 "CH1_INTCLEARREG,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTCLEARREG_36to63,DMAC Channelx Interrupt Clear Register (bits 36to63) Reserved bit - Read Only"
newline
bitfld.quad 0x0 35. "Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat,ECC Protection Uncorrectable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 34. "Clear_ECC_PROT_UIDMem_CorrERR_IntStat,ECC Protection Correctable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 33. "Clear_ECC_PROT_CHMem_UnCorrERR_IntStat,ECC Protection Uncorrectable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 32. "Clear_ECC_PROT_CHMem_CorrERR_IntStat,ECC Protection Correctable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 31. "Clear_CH_ABORTED_IntStat,Channel Aborted Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 30. "Clear_CH_DISABLED_IntStat,Channel Disabled Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 29. "Clear_CH_SUSPENDED_IntStat,Channel Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 28. "Clear_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 27. "Clear_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTCLEARREG_26,DMAC Channelx Interrupt Clear Register (bit 26) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 25. "Clear_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTCLEARREG_22to24,DMAC Channelx Interrupt Clear Register (bits 22to24) Reserved bit - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Clear_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 20. "Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 19. "Clear_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 18. "Clear_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 17. "Clear_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 16. "Clear_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTCLEARREG_15,DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 13. "Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 12. "Clear_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 11. "Clear_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 10. "Clear_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 9. "Clear_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 8. "Clear_DST_SLV_ERR_IntStat,Destination Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 7. "Clear_SRC_SLV_ERR_IntStat,Source Slave Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 6. "Clear_DST_DEC_ERR_IntStat,Destination Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 5. "Clear_SRC_DEC_ERR_IntStat,Source Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 4. "Clear_DST_TRANSCOMP_IntStat,Destination Transaction Completed Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 3. "Clear_SRC_TRANSCOMP_IntStat,Source Transaction Completed Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTCLEARREG_2,DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 1. "Clear_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 0. "Clear_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Clear Bit." "0,1"
group.quad 0x200++0x2F
line.quad 0x0 "CH2_SAR,The starting source address is programmed by software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While"
hexmask.quad 0x0 0.--63. 1. "SAR,Current Source Address of DMA transfer."
line.quad 0x8 "CH2_DAR,The starting destination address is programmed by the software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer."
hexmask.quad 0x8 0.--63. 1. "DAR,Current Destination Address of DMA transfer."
line.quad 0x10 "CH2_BLOCK_TS,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size."
hexmask.quad 0x10 22.--63. 1. "RSVD_DMAC_CHx_BLOCK_TSREG_63to22,DMAC Channelx Block Transfer Size Register (bits 63to22) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x10 0.--21. 1. "BLOCK_TS,Block Transfer Size."
line.quad 0x18 "CH2_CTL,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.."
bitfld.quad 0x18 63. "SHADOWREG_OR_LLI_VALID,Shadow Register content/Linked List Item valid." "0: Shadow Register content/LLI is invalid,1: Last Shadow Register/LLI is valid"
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bitfld.quad 0x18 62. "SHADOWREG_OR_LLI_LAST,Last Shadow Register/Linked List Item." "0: Not last Shadow Register/LLI,1: Last Shadow Register/LLI"
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rbitfld.quad 0x18 59.--61. "RSVD_DMAC_CHx_CTL_59to61,DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 58. "IOC_BlkTfr,Interrupt On completion of Block Transfer" "0,1"
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rbitfld.quad 0x18 57. "DST_STAT_EN,Destination Status Enable" "0,1"
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rbitfld.quad 0x18 56. "SRC_STAT_EN,Source Status Enable" "0,1"
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hexmask.quad.byte 0x18 48.--55. 1. "AWLEN,Destination Burst Length"
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bitfld.quad 0x18 47. "AWLEN_EN,Destination Burst Length Enable" "0,1"
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hexmask.quad.byte 0x18 39.--46. 1. "ARLEN,Source Burst Length"
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bitfld.quad 0x18 38. "ARLEN_EN,Source Burst Length Enable" "0,1"
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bitfld.quad 0x18 35.--37. "AW_PROT,AXI 'aw_prot' signal" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 32.--34. "AR_PROT,AXI 'ar_prot' signal" "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x18 31. "RSVD_DMAC_CHx_CTL_31,DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 30. "NonPosted_LastWrite_En,Non Posted Last Write Enable" "0: Posted writes may be used throughout the block..,1: Posted writes may be used till the end of the.."
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hexmask.quad.byte 0x18 26.--29. 1. "AW_CACHE,AXI 'aw_cache' signal"
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hexmask.quad.byte 0x18 22.--25. 1. "AR_CACHE,AXI 'ar_cache' signal"
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hexmask.quad.byte 0x18 18.--21. 1. "DST_MSIZE,Destination Burst Transaction Length."
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hexmask.quad.byte 0x18 14.--17. 1. "SRC_MSIZE,Source Burst Transaction Length."
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bitfld.quad 0x18 11.--13. "DST_TR_WIDTH,Destination Transfer Width." "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 8.--10. "SRC_TR_WIDTH,Source Transfer Width." "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x18 7. "RSVD_DMAC_CHx_CTL_7,DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 6. "DINC,Destination Address Increment." "0: Increment,1: No Change"
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rbitfld.quad 0x18 5. "RSVD_DMAC_CHx_CTL_5,DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 4. "SINC,Source Address Increment." "0: Increment,1: No Change"
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rbitfld.quad 0x18 3. "RSVD_DMAC_CHx_CTL_3,DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only" "0,1"
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rbitfld.quad 0x18 2. "DMS,Destination Master Select." "0: AXI master 1,1: AXI Master 2"
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rbitfld.quad 0x18 1. "RSVD_DMAC_CHx_CTL_1,DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only" "0,1"
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rbitfld.quad 0x18 0. "SMS,Source Master Select." "0: AXI master 1,1: AXI Master 2"
line.quad 0x20 "CH2_CFG2,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel."
rbitfld.quad 0x20 63. "RSVD_DMAC_CHx_CFG_63,DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 59.--62. 1. "DST_OSR_LMT,Destination Outstanding Request Limit"
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hexmask.quad.byte 0x20 55.--58. 1. "SRC_OSR_LMT,Source Outstanding Request Limit"
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bitfld.quad 0x20 53.--54. "LOCK_CH_L,Channel Lock Level" "0: Over complete DMA transfer,1: Over DMA block transfer,?,?"
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bitfld.quad 0x20 52. "LOCK_CH,Channel Lock bit" "0,1"
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hexmask.quad.byte 0x20 47.--51. 1. "CH_PRIOR,Channel Priority"
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hexmask.quad.byte 0x20 39.--46. 1. "RSVD_DMAC_CHx_CFG_39to46,DMAC Channelx Transfer Configuration Register (bits 39to46) Reserved bits - Read Only"
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rbitfld.quad 0x20 38. "DST_HWHS_POL,Destination Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
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rbitfld.quad 0x20 37. "SRC_HWHS_POL,Source Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
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bitfld.quad 0x20 36. "HS_SEL_DST,Destination Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
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bitfld.quad 0x20 35. "HS_SEL_SRC,Source Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
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bitfld.quad 0x20 32.--34. "TT_FC,Transfer Type and Flow Control." "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x20 29.--31. "RSVD_DMAC_CHx_CFG_29to31,DMAC Channelx Transfer Configuration Register (bits 29to31) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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hexmask.quad.byte 0x20 25.--28. 1. "WR_UID,Defines the number of AXI Unique ID's supported for the AXI Write Channel. The value programmed must be less than or equal to DMAX_CH(x)_WR_UID. Otherwise  it is limited by the value DMAX_CH(x)_WR_UID."
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rbitfld.quad 0x20 22.--24. "RSVD_DMAC_CHx_CFG_22to24,DMAC Channelx Transfer Configuration Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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hexmask.quad.byte 0x20 18.--21. 1. "RD_UID,Defines the number of AXI Unique ID's supported for the AXI Read Channel. The value programmed must be less than or equal to DMAX_CH(x)_RD_UID. Otherwise  it is limited by the value DMAX_CH(x)_RD_UID."
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rbitfld.quad 0x20 17. "RSVD_DMAC_CHx_CFG_17,DMAC Channelx Transfer Configuration Register (bit 17) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 11.--16. 1. "DST_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0;"
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rbitfld.quad 0x20 10. "RSVD_DMAC_CHx_CFG_10,DMAC Channelx Transfer Configuration Register (bit 10) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 4.--9. 1. "SRC_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise "
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rbitfld.quad 0x20 2.--3. "DST_MULTBLK_TYPE,Destination Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
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rbitfld.quad 0x20 0.--1. "SRC_MULTBLK_TYPE,Source Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
line.quad 0x28 "CH2_LLP,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the"
hexmask.quad 0x28 6.--63. 1. "LOC,Starting Address Memory of LLI block"
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hexmask.quad.byte 0x28 1.--5. 1. "RSVD_DMAC_CHx_LLP_1to5,DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only"
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rbitfld.quad 0x28 0. "LMS,LLI master Select" "0: AXI Master 1,1: AXI Master 2"
rgroup.quad 0x230++0x7
line.quad 0x0 "CH2_STATUSREG,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx."
hexmask.quad.tbyte 0x0 47.--63. 1. "RSVD_DMAC_CHx_STATUSREG_47to63,DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 32.--46. 1. "DATA_LEFT_IN_FIFO,Data Left in FIFO."
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hexmask.quad.word 0x0 22.--31. 1. "RSVD_DMAC_CHx_STATUSREG_22to31,DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x0 0.--21. 1. "CMPLTD_BLK_TFR_SIZE,Completed Block Transfer Size."
group.quad 0x238++0xF
line.quad 0x0 "CH2_SWHSSRCREG,Channelx Software handshake Source Register."
hexmask.quad 0x0 6.--63. 1. "RSVD_DMAC_CHx_SWHSSRCREG_6to63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x0 5. "SWHS_LST_SRC_WE,Write Enable bit for Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 4. "SWHS_LST_SRC,Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 3. "SWHS_SGLREQ_SRC_WE,Write Enable bit for Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 2. "SWHS_SGLREQ_SRC,Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 1. "SWHS_REQ_SRC_WE,Write Enable bit for Software Handshake Request for Channel Source." "0,1"
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bitfld.quad 0x0 0. "SWHS_REQ_SRC,Software Handshake Request for Channel Source." "0,1"
line.quad 0x8 "CH2_SWHSDSTREG,Channelx Software handshake Destination Register."
hexmask.quad 0x8 6.--63. 1. "RSVD_DMAC_CHx_SWHSDSTREG_6to63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x8 5. "SWHS_LST_DST_WE,Write Enable bit for Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 4. "SWHS_LST_DST,Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 3. "SWHS_SGLREQ_DST_WE,Write Enable bit for Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 2. "SWHS_SGLREQ_DST,Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 1. "SWHS_REQ_DST_WE,Write Enable bit for Software Handshake Request for Channel Destination." "0,1"
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bitfld.quad 0x8 0. "SWHS_REQ_DST,Software Handshake Request for Channel Destination." "0,1"
wgroup.quad 0x248++0x7
line.quad 0x0 "CH2_BLK_TFR_RESUMEREQREG,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer."
hexmask.quad 0x0 1.--63. 1. "RSVD_DMAC_CHx_BLK_TFR_RESUMEREQREG_1to63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only"
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bitfld.quad 0x0 0. "BLK_TFR_RESUMEREQ,Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer." "0,1"
group.quad 0x250++0xF
line.quad 0x0 "CH2_AXI_IDREG,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad.long 0x0 32.--63. 1. "RSVD_DMAC_CHx_AXI_IDREG_32to63,DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 20.--31. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm32to63,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 16.--19. 1. "AXI_WRITE_ID_SUFFIX,AXI Write ID Suffix."
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hexmask.quad.word 0x0 4.--15. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm1to31,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 0.--3. 1. "AXI_READ_ID_SUFFIX,AXI Read ID Suffix"
line.quad 0x8 "CH2_AXI_QOSREG,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad 0x8 8.--63. 1. "RSVD_DMAC_CHx_AXI_QOSREG_8to63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only"
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hexmask.quad.byte 0x8 4.--7. 1. "AXI_ARQOS,AXI ARQOS."
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hexmask.quad.byte 0x8 0.--3. 1. "AXI_AWQOS,AXI AWQOS."
group.quad 0x280++0x7
line.quad 0x0 "CH2_INTSTATUS_ENABLEREG,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH2_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63,DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only"
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rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation Channel x Channel Memory.."
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rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation of Channel x Channel.."
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bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntStat,Channel Aborted Status Enable." "0: Disable the generation of Channel Aborted..,1: Enable the generation of Channel Aborted.."
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bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntStat,Channel Disabled Status Enable." "0: Disable the generation of Channel Disabled..,1: Enable the generation of Channel Disabled.."
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bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntStat,Channel Suspended Status Enable." "0: Disable the generation of Channel Suspended..,1: Enable the generation of Channel Suspended.."
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bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Status Enable." "0: Disable the generation of Channel Source..,1: Enable the generation of Channel Source.."
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bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Status Enable." "0: Disable the generation of Channel LOCK CLEARED..,1: Enable the generation of Channel LOCK CLEARED.."
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rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26,DMAC Channelx Interrupt Status Register (bit 26) Reserved bit - Read Only" "0,1"
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rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24,DMAC Channelx Interrupt Status Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Status Enable." "0: Disable the generation of Shadow Register Write..,1: Enable the generation of Shadow register Write.."
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bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Status Enable." "0: Disable the generation of Slave Interface Read..,1: Enable the generation of Slave Interface Read to.."
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bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Status Enable." "0: Disable the generation of Slave Interface Decode..,1: Enable the generation of Slave Interface Decode.."
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rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Status Enable." "0: Disable the generation of Slave Interface Multi..,1: Enable the generation of Slave Interface Multi.."
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bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Status Enable." "0: Disable the generation of Shadow Register or LLI..,1: Enable the generation of Shadow Register or LLI.."
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bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Status Enable." "0: Disable the generation of LLI WRITE Slave Error..,1: Enable the generation of LLI WRITE Slave Error.."
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bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Status Enable." "0: Disable the generation of LLI Read Slave Error..,1: Enable the generation of LLI Read Slave Error.."
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bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Status Enable." "0: Disable the generation of LLI WRITE Decode Error..,1: Enable the generation of LLI WRITE Decode Error.."
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bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Status Enable." "0: Disable the generation of LLI Read Decode Error..,1: Enable the generation of LLI Read Decode Error.."
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bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntStat,Destination Slave Error Status Enable." "0: Disable the generation of Destination Slave..,1: Enable the generation of Destination Slave Error.."
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bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntStat,Source Slave Error Status Enable." "0: Disable the generation of Source Slave Error..,1: Enable the generation of Source Slave Error.."
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bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntStat,Destination Decode Error Status Enable." "0: Disable the generation of Destination Decode..,1: Enable the generation of Destination Decode.."
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bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntStat,Source Decode Error Status Enable." "0: Disable the generation of Source Decode Error..,1: Enable the generation of Source Decode Error.."
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bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntStat,Destination Transaction Completed Status Enable." "0: Disable the generation of Destination..,1: Enable the generation of Destination Transaction.."
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bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntStat,Source Transaction Completed Status Enable." "0: Disable the generation of Source Transaction..,1: Enable the generation of Source Transaction.."
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rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Status Enable." "0: Disable the generation of DMA Transfer Done..,1: Enable the generation of DMA Transfer Done.."
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bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Status Enable." "0: Disable the generation of Block Transfer Done..,1: Enable the generation of Block Transfer Done.."
rgroup.quad 0x288++0x7
line.quad 0x0 "CH2_INTSTATUS,Channelx Interrupt Status Register captures the Channelx specific interrupts"
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUSREG_36to63,DMAC Channelx Specific Interrupt Register (bits 36to63) Reserved bits - Read Only"
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bitfld.quad 0x0 35. "ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x UID Memory Interface Uncorrectable..,1: Channel x UID Memory Interface Uncorrectable.."
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bitfld.quad 0x0 34. "ECC_PROT_UIDMem_CorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x UID Memory Interface correctable..,1: Channel x UID Memory Interface correctable Error.."
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bitfld.quad 0x0 33. "ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface Uncorrectable..,1: Channel x FIFO Memory Interface Uncorrectable.."
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bitfld.quad 0x0 32. "ECC_PROT_CHMem_CorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface correctable..,1: Channel x FIFO Memory Interface correctable.."
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bitfld.quad 0x0 31. "CH_ABORTED_IntStat,Channel Aborted." "0: Channel is not aborted,1: Channel is aborted"
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bitfld.quad 0x0 30. "CH_DISABLED_IntStat,Channel Disabled." "0: Channel is not disabled,1: Channel is disabled"
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bitfld.quad 0x0 29. "CH_SUSPENDED_IntStat,Channel Suspended." "0: Channel is not suspended,1: Channel is suspended"
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bitfld.quad 0x0 28. "CH_SRC_SUSPENDED_IntStat,Channel Source Suspended." "0: Channel source is not suspended,1: Channel Source is suspended"
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bitfld.quad 0x0 27. "CH_LOCK_CLEARED_IntStat,Channel Lock Cleared." "0: Channel locking is not cleared,1: Channel locking is cleared"
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bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUSREG_26,DMAC Channelx Specific Interrupt Register (bit 26) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 25. "SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error." "0: No Slave Interface Write Parity Errors,1: Slave Interface Write Parity Error detected"
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bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUSREG_22to24,DMAC Channelx Specific Interrupt Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error." "0: No Slave Interface Write On Hold Errors,1: Slave Interface Write On Hold Error detected"
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bitfld.quad 0x0 20. "SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error." "0: No Slave Interface Shadow Register Write On..,1: Slave Interface Shadow Register Write On Valid.."
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bitfld.quad 0x0 19. "SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error." "0: No Slave Interface Write On Channel Enabled Errors,1: Slave Interface Write On Channel Enabled Error.."
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bitfld.quad 0x0 18. "SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error." "0: No Slave Interface Read to Write Only Errors,1: Slave Interface Read to Write Only Error detected"
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bitfld.quad 0x0 17. "SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error." "0: No Slave Interface Write to Read Only Errors,1: Slave Interface Write to Read Only Error detected"
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bitfld.quad 0x0 16. "SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error." "0: No Slave Interface Decode errors,1: Slave Interface Decode Error detected"
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bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUSREG_15,DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error." "0: No Multi-block transfer type Errors,1: Multi-block transfer type Error detected"
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bitfld.quad 0x0 13. "SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error." "0: No Shadow Register / LLI Invalid errors,1: Shadow Register / LLI Invalid error detected"
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bitfld.quad 0x0 12. "LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error." "0: No LLI write Slave Errors,1: LLI Write SLAVE Error detected"
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bitfld.quad 0x0 11. "LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error." "0: No LLI Read Slave Errors,1: LLI read Slave Error detected"
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bitfld.quad 0x0 10. "LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error." "0: NO LLI Write Decode Errors,1: LLI write Decode Error detected"
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bitfld.quad 0x0 9. "LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error." "0: NO LLI Read Decode Errors,1: LLI Read Decode Error detected"
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bitfld.quad 0x0 8. "DST_SLV_ERR_IntStat,Destination Slave Error." "0: No Destination Slave Errors,1: Destination Slave Errors Detected"
newline
bitfld.quad 0x0 7. "SRC_SLV_ERR_IntStat,Source Slave Error." "0: No Source Slave Errors,1: Source Slave Error Detected"
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bitfld.quad 0x0 6. "DST_DEC_ERR_IntStat,Destination Decode Error." "0: No destination Decode Errors,1: Destination Decode Error Detected"
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bitfld.quad 0x0 5. "SRC_DEC_ERR_IntStat,Source Decode Error." "0: No Source Decode Errors,1: Source Decode Error detected"
newline
bitfld.quad 0x0 4. "DST_TRANSCOMP_IntStat,Destination Transaction Completed." "0,1"
newline
bitfld.quad 0x0 3. "SRC_TRANSCOMP_IntStat,Source Transaction Completed." "0,1"
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bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUSREG_2,DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "DMA_TFR_DONE_IntStat,DMA Transfer Done." "0: DMA Transfer not completed,1: DMA Transfer Completed"
newline
bitfld.quad 0x0 0. "BLOCK_TFR_DONE_IntStat,Block Transfer Done." "0: Block Transfer not completed,1: Block Transfer completed"
group.quad 0x290++0x7
line.quad 0x0 "CH2_INTSIGNAL_ENABLEREG,This register contains fields that are used to enable the generation of port level interrupt at the channel level."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63,DMAC Channelx Interrupt Signal Enable Register (bits 36to63) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
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rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
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rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
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rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntSignal,Channel Aborted Signal Enable." "0: Disable the propagation of Channel Aborted..,1: Enable the propagation of Channel Aborted.."
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bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntSignal,Channel Disabled Signal Enable." "0: Disable the propagation of Channel Disabled..,1: Enable the propagation of Channel Disabled.."
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bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntSignal,Channel Suspended Signal Enable." "0: Disable the propagation of Channel Suspended..,1: Enable the propagation of Channel Suspended.."
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bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntSignal,Channel Source Suspended Signal Enable." "0: Disable the propagation of Channel Source..,1: Enable the propagation of Channel Source.."
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bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntSignal,Channel Lock Cleared Signal Enable." "0: Disable the propagation of Channel Lock Cleared..,1: Enable the propagation of Channel Lock Cleared.."
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rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26,DMAC Channelx Interrupt Signal Enable Register (bit 26) Reserved bit - Read Only" "0,1"
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rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntSignal,Slave Interface Write Parity Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
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rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24,DMAC Channelx Interrupt Signal Enable Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntSignal,Slave Interface Write On Hold Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal,Shadow Register Write On Valid Error Signal Enable." "0: Disable the propagation of Shadow Register Write..,1: Enable the propagation of Shadow register Write.."
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bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntSignal,Slave Interface Write On Channel Enabled Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
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bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntSignal,Slave Interface Read to write Only Error Signal Enable." "0: Disable the propagation of Slave Interface Read..,1: Enable the propagation of Slave Interface Read.."
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bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntSignal,Slave Interface Write to Read Only Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntSignal,Slave Interface Decode Error Signal Enable." "0: Disable the propagation of Slave Interface..,1: Enable the propagation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,Slave Interface Multi Block type Error Signal Enable." "0: Disable the propagation of Slave Interface Multi..,1: Enable the propagation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,Shadow register or LLI Invalid Error Signal Enable." "0: Disable the propagation of Shadow Register or..,1: Enable the propagation of Shadow Register or LLI.."
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bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntSignal,LLI WRITE Slave Error Signal Enable." "0: Disable the propagation of LLI WRITE Slave Error..,1: Enable the propagation of LLI WRITE Slave Error.."
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bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntSignal,LLI Read Slave Error Signal Enable." "0: Disable the propagation of LLI Read Slave Error..,1: Enable the propagation of LLI Read Slave Error.."
newline
bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntSignal,LLI WRITE Decode Error Signal Enable." "0: Disable the propagation of LLI WRITE Decode..,1: Enable the propagation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntSignal,LLI Read Decode Error Signal Enable." "0: Disable the propagation of LLI Read Decode Error..,1: Enable the propagation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntSignal,Destination Slave Error Signal Enable." "0: Disable the propagation of Destination Slave..,1: Enable the propagation of Destination Slave.."
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bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntSignal,Source Slave Error Signal Enable." "0: Disable the propagation of Source Slave Error..,1: Enable the propagation of Source Slave Error.."
newline
bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntSignal,Destination Decode Error Signal Enable." "0: Disable the propagation of Destination Decode..,1: Enable the propagation of Destination Decode.."
newline
bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntSignal,Source Decode Error Signal Enable." "0: Disable the propagation of Source Decode Error..,1: Enable the propagation of Source Decode Error.."
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bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntSignal,Destination Transaction Completed Signal Enable." "0: Disable the propagation of Destination..,1: Enable the propagation of Destination.."
newline
bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntSignal,Source Transaction Completed Signal Enable." "0: Disable the propagation of Source Transaction..,1: Enable the propagation of Source Transaction.."
newline
rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntSignal,DMA Transfer Done Interrupt Signal Enable." "0: Disable the propagation of DMA Transfer Done..,1: Enable the propagation of DMA Transfer Done.."
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bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntSignal,Block Transfer Done Interrupt Signal Enable." "0: Disable the propagation of Block Transfer Done..,1: Enable the propagation of Block Transfer Done.."
wgroup.quad 0x298++0x7
line.quad 0x0 "CH2_INTCLEARREG,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTCLEARREG_36to63,DMAC Channelx Interrupt Clear Register (bits 36to63) Reserved bit - Read Only"
newline
bitfld.quad 0x0 35. "Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat,ECC Protection Uncorrectable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 34. "Clear_ECC_PROT_UIDMem_CorrERR_IntStat,ECC Protection Correctable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 33. "Clear_ECC_PROT_CHMem_UnCorrERR_IntStat,ECC Protection Uncorrectable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 32. "Clear_ECC_PROT_CHMem_CorrERR_IntStat,ECC Protection Correctable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 31. "Clear_CH_ABORTED_IntStat,Channel Aborted Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 30. "Clear_CH_DISABLED_IntStat,Channel Disabled Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 29. "Clear_CH_SUSPENDED_IntStat,Channel Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 28. "Clear_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 27. "Clear_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTCLEARREG_26,DMAC Channelx Interrupt Clear Register (bit 26) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 25. "Clear_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTCLEARREG_22to24,DMAC Channelx Interrupt Clear Register (bits 22to24) Reserved bit - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Clear_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 20. "Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 19. "Clear_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 18. "Clear_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 17. "Clear_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 16. "Clear_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTCLEARREG_15,DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 13. "Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 12. "Clear_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 11. "Clear_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 10. "Clear_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 9. "Clear_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 8. "Clear_DST_SLV_ERR_IntStat,Destination Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 7. "Clear_SRC_SLV_ERR_IntStat,Source Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 6. "Clear_DST_DEC_ERR_IntStat,Destination Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 5. "Clear_SRC_DEC_ERR_IntStat,Source Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 4. "Clear_DST_TRANSCOMP_IntStat,Destination Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 3. "Clear_SRC_TRANSCOMP_IntStat,Source Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTCLEARREG_2,DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Clear_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 0. "Clear_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Clear Bit." "0,1"
group.quad 0x300++0x2F
line.quad 0x0 "CH3_SAR,The starting source address is programmed by software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While"
hexmask.quad 0x0 0.--63. 1. "SAR,Current Source Address of DMA transfer."
line.quad 0x8 "CH3_DAR,The starting destination address is programmed by the software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer."
hexmask.quad 0x8 0.--63. 1. "DAR,Current Destination Address of DMA transfer."
line.quad 0x10 "CH3_BLOCK_TS,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size."
hexmask.quad 0x10 22.--63. 1. "RSVD_DMAC_CHx_BLOCK_TSREG_63to22,DMAC Channelx Block Transfer Size Register (bits 63to22) Reserved bits - Read Only"
newline
hexmask.quad.tbyte 0x10 0.--21. 1. "BLOCK_TS,Block Transfer Size."
line.quad 0x18 "CH3_CTL,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.."
bitfld.quad 0x18 63. "SHADOWREG_OR_LLI_VALID,Shadow Register content/Linked List Item valid." "0: Shadow Register content/LLI is invalid,1: Last Shadow Register/LLI is valid"
newline
bitfld.quad 0x18 62. "SHADOWREG_OR_LLI_LAST,Last Shadow Register/Linked List Item." "0: Not last Shadow Register/LLI,1: Last Shadow Register/LLI"
newline
rbitfld.quad 0x18 59.--61. "RSVD_DMAC_CHx_CTL_59to61,DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 58. "IOC_BlkTfr,Interrupt On completion of Block Transfer" "0,1"
newline
rbitfld.quad 0x18 57. "DST_STAT_EN,Destination Status Enable" "0,1"
newline
rbitfld.quad 0x18 56. "SRC_STAT_EN,Source Status Enable" "0,1"
newline
hexmask.quad.byte 0x18 48.--55. 1. "AWLEN,Destination Burst Length"
newline
bitfld.quad 0x18 47. "AWLEN_EN,Destination Burst Length Enable" "0,1"
newline
hexmask.quad.byte 0x18 39.--46. 1. "ARLEN,Source Burst Length"
newline
bitfld.quad 0x18 38. "ARLEN_EN,Source Burst Length Enable" "0,1"
newline
bitfld.quad 0x18 35.--37. "AW_PROT,AXI 'aw_prot' signal" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 32.--34. "AR_PROT,AXI 'ar_prot' signal" "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x18 31. "RSVD_DMAC_CHx_CTL_31,DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 30. "NonPosted_LastWrite_En,Non Posted Last Write Enable" "0: Posted writes may be used throughout the block..,1: Posted writes may be used till the end of the.."
newline
hexmask.quad.byte 0x18 26.--29. 1. "AW_CACHE,AXI 'aw_cache' signal"
newline
hexmask.quad.byte 0x18 22.--25. 1. "AR_CACHE,AXI 'ar_cache' signal"
newline
hexmask.quad.byte 0x18 18.--21. 1. "DST_MSIZE,Destination Burst Transaction Length."
newline
hexmask.quad.byte 0x18 14.--17. 1. "SRC_MSIZE,Source Burst Transaction Length."
newline
bitfld.quad 0x18 11.--13. "DST_TR_WIDTH,Destination Transfer Width." "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x18 8.--10. "SRC_TR_WIDTH,Source Transfer Width." "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x18 7. "RSVD_DMAC_CHx_CTL_7,DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 6. "DINC,Destination Address Increment." "0: Increment,1: No Change"
newline
rbitfld.quad 0x18 5. "RSVD_DMAC_CHx_CTL_5,DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only" "0,1"
newline
bitfld.quad 0x18 4. "SINC,Source Address Increment." "0: Increment,1: No Change"
newline
rbitfld.quad 0x18 3. "RSVD_DMAC_CHx_CTL_3,DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only" "0,1"
newline
rbitfld.quad 0x18 2. "DMS,Destination Master Select." "0: AXI master 1,1: AXI Master 2"
newline
rbitfld.quad 0x18 1. "RSVD_DMAC_CHx_CTL_1,DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only" "0,1"
newline
rbitfld.quad 0x18 0. "SMS,Source Master Select." "0: AXI master 1,1: AXI Master 2"
line.quad 0x20 "CH3_CFG2,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel."
rbitfld.quad 0x20 63. "RSVD_DMAC_CHx_CFG_63,DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only" "0,1"
newline
hexmask.quad.byte 0x20 59.--62. 1. "DST_OSR_LMT,Destination Outstanding Request Limit"
newline
hexmask.quad.byte 0x20 55.--58. 1. "SRC_OSR_LMT,Source Outstanding Request Limit"
newline
bitfld.quad 0x20 53.--54. "LOCK_CH_L,Channel Lock Level" "0: Over complete DMA transfer,1: Over DMA block transfer,?,?"
newline
bitfld.quad 0x20 52. "LOCK_CH,Channel Lock bit" "0,1"
newline
hexmask.quad.byte 0x20 47.--51. 1. "CH_PRIOR,Channel Priority"
newline
hexmask.quad.byte 0x20 39.--46. 1. "RSVD_DMAC_CHx_CFG_39to46,DMAC Channelx Transfer Configuration Register (bits 39to46) Reserved bits - Read Only"
newline
rbitfld.quad 0x20 38. "DST_HWHS_POL,Destination Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
newline
rbitfld.quad 0x20 37. "SRC_HWHS_POL,Source Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
newline
bitfld.quad 0x20 36. "HS_SEL_DST,Destination Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
newline
bitfld.quad 0x20 35. "HS_SEL_SRC,Source Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
newline
bitfld.quad 0x20 32.--34. "TT_FC,Transfer Type and Flow Control." "0,1,2,3,4,5,6,7"
newline
rbitfld.quad 0x20 29.--31. "RSVD_DMAC_CHx_CFG_29to31,DMAC Channelx Transfer Configuration Register (bits 29to31) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x20 25.--28. 1. "WR_UID,Defines the number of AXI Unique ID's supported for the AXI Write Channel. The value programmed must be less than or equal to DMAX_CH(x)_WR_UID. Otherwise  it is limited by the value DMAX_CH(x)_WR_UID."
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rbitfld.quad 0x20 22.--24. "RSVD_DMAC_CHx_CFG_22to24,DMAC Channelx Transfer Configuration Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.byte 0x20 18.--21. 1. "RD_UID,Defines the number of AXI Unique ID's supported for the AXI Read Channel. The value programmed must be less than or equal to DMAX_CH(x)_RD_UID. Otherwise  it is limited by the value DMAX_CH(x)_RD_UID."
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rbitfld.quad 0x20 17. "RSVD_DMAC_CHx_CFG_17,DMAC Channelx Transfer Configuration Register (bit 17) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 11.--16. 1. "DST_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0;"
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rbitfld.quad 0x20 10. "RSVD_DMAC_CHx_CFG_10,DMAC Channelx Transfer Configuration Register (bit 10) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 4.--9. 1. "SRC_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise "
newline
rbitfld.quad 0x20 2.--3. "DST_MULTBLK_TYPE,Destination Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
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rbitfld.quad 0x20 0.--1. "SRC_MULTBLK_TYPE,Source Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
line.quad 0x28 "CH3_LLP,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the"
hexmask.quad 0x28 6.--63. 1. "LOC,Starting Address Memory of LLI block"
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hexmask.quad.byte 0x28 1.--5. 1. "RSVD_DMAC_CHx_LLP_1to5,DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only"
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rbitfld.quad 0x28 0. "LMS,LLI master Select" "0: AXI Master 1,1: AXI Master 2"
rgroup.quad 0x330++0x7
line.quad 0x0 "CH3_STATUSREG,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx."
hexmask.quad.tbyte 0x0 47.--63. 1. "RSVD_DMAC_CHx_STATUSREG_47to63,DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 32.--46. 1. "DATA_LEFT_IN_FIFO,Data Left in FIFO."
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hexmask.quad.word 0x0 22.--31. 1. "RSVD_DMAC_CHx_STATUSREG_22to31,DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x0 0.--21. 1. "CMPLTD_BLK_TFR_SIZE,Completed Block Transfer Size."
group.quad 0x338++0xF
line.quad 0x0 "CH3_SWHSSRCREG,Channelx Software handshake Source Register."
hexmask.quad 0x0 6.--63. 1. "RSVD_DMAC_CHx_SWHSSRCREG_6to63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x0 5. "SWHS_LST_SRC_WE,Write Enable bit for Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 4. "SWHS_LST_SRC,Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 3. "SWHS_SGLREQ_SRC_WE,Write Enable bit for Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 2. "SWHS_SGLREQ_SRC,Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 1. "SWHS_REQ_SRC_WE,Write Enable bit for Software Handshake Request for Channel Source." "0,1"
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bitfld.quad 0x0 0. "SWHS_REQ_SRC,Software Handshake Request for Channel Source." "0,1"
line.quad 0x8 "CH3_SWHSDSTREG,Channelx Software handshake Destination Register."
hexmask.quad 0x8 6.--63. 1. "RSVD_DMAC_CHx_SWHSDSTREG_6to63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x8 5. "SWHS_LST_DST_WE,Write Enable bit for Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 4. "SWHS_LST_DST,Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 3. "SWHS_SGLREQ_DST_WE,Write Enable bit for Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 2. "SWHS_SGLREQ_DST,Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 1. "SWHS_REQ_DST_WE,Write Enable bit for Software Handshake Request for Channel Destination." "0,1"
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bitfld.quad 0x8 0. "SWHS_REQ_DST,Software Handshake Request for Channel Destination." "0,1"
wgroup.quad 0x348++0x7
line.quad 0x0 "CH3_BLK_TFR_RESUMEREQREG,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer."
hexmask.quad 0x0 1.--63. 1. "RSVD_DMAC_CHx_BLK_TFR_RESUMEREQREG_1to63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only"
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bitfld.quad 0x0 0. "BLK_TFR_RESUMEREQ,Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer." "0,1"
group.quad 0x350++0xF
line.quad 0x0 "CH3_AXI_IDREG,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad.long 0x0 32.--63. 1. "RSVD_DMAC_CHx_AXI_IDREG_32to63,DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 20.--31. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm32to63,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 16.--19. 1. "AXI_WRITE_ID_SUFFIX,AXI Write ID Suffix."
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hexmask.quad.word 0x0 4.--15. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm1to31,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 0.--3. 1. "AXI_READ_ID_SUFFIX,AXI Read ID Suffix"
line.quad 0x8 "CH3_AXI_QOSREG,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad 0x8 8.--63. 1. "RSVD_DMAC_CHx_AXI_QOSREG_8to63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only"
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hexmask.quad.byte 0x8 4.--7. 1. "AXI_ARQOS,AXI ARQOS."
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hexmask.quad.byte 0x8 0.--3. 1. "AXI_AWQOS,AXI AWQOS."
group.quad 0x380++0x7
line.quad 0x0 "CH3_INTSTATUS_ENABLEREG,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH3_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63,DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only"
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rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation Channel x Channel Memory.."
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rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation of Channel x Channel.."
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bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntStat,Channel Aborted Status Enable." "0: Disable the generation of Channel Aborted..,1: Enable the generation of Channel Aborted.."
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bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntStat,Channel Disabled Status Enable." "0: Disable the generation of Channel Disabled..,1: Enable the generation of Channel Disabled.."
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bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntStat,Channel Suspended Status Enable." "0: Disable the generation of Channel Suspended..,1: Enable the generation of Channel Suspended.."
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bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Status Enable." "0: Disable the generation of Channel Source..,1: Enable the generation of Channel Source.."
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bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Status Enable." "0: Disable the generation of Channel LOCK CLEARED..,1: Enable the generation of Channel LOCK CLEARED.."
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rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26,DMAC Channelx Interrupt Status Register (bit 26) Reserved bit - Read Only" "0,1"
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rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24,DMAC Channelx Interrupt Status Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Status Enable." "0: Disable the generation of Shadow Register Write..,1: Enable the generation of Shadow register Write.."
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bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Status Enable." "0: Disable the generation of Slave Interface Read..,1: Enable the generation of Slave Interface Read to.."
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bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Status Enable." "0: Disable the generation of Slave Interface Decode..,1: Enable the generation of Slave Interface Decode.."
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rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Status Enable." "0: Disable the generation of Slave Interface Multi..,1: Enable the generation of Slave Interface Multi.."
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bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Status Enable." "0: Disable the generation of Shadow Register or LLI..,1: Enable the generation of Shadow Register or LLI.."
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bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Status Enable." "0: Disable the generation of LLI WRITE Slave Error..,1: Enable the generation of LLI WRITE Slave Error.."
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bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Status Enable." "0: Disable the generation of LLI Read Slave Error..,1: Enable the generation of LLI Read Slave Error.."
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bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Status Enable." "0: Disable the generation of LLI WRITE Decode Error..,1: Enable the generation of LLI WRITE Decode Error.."
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bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Status Enable." "0: Disable the generation of LLI Read Decode Error..,1: Enable the generation of LLI Read Decode Error.."
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bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntStat,Destination Slave Error Status Enable." "0: Disable the generation of Destination Slave..,1: Enable the generation of Destination Slave Error.."
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bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntStat,Source Slave Error Status Enable." "0: Disable the generation of Source Slave Error..,1: Enable the generation of Source Slave Error.."
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bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntStat,Destination Decode Error Status Enable." "0: Disable the generation of Destination Decode..,1: Enable the generation of Destination Decode.."
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bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntStat,Source Decode Error Status Enable." "0: Disable the generation of Source Decode Error..,1: Enable the generation of Source Decode Error.."
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bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntStat,Destination Transaction Completed Status Enable." "0: Disable the generation of Destination..,1: Enable the generation of Destination Transaction.."
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bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntStat,Source Transaction Completed Status Enable." "0: Disable the generation of Source Transaction..,1: Enable the generation of Source Transaction.."
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rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Status Enable." "0: Disable the generation of DMA Transfer Done..,1: Enable the generation of DMA Transfer Done.."
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bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Status Enable." "0: Disable the generation of Block Transfer Done..,1: Enable the generation of Block Transfer Done.."
rgroup.quad 0x388++0x7
line.quad 0x0 "CH3_INTSTATUS,Channelx Interrupt Status Register captures the Channelx specific interrupts"
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUSREG_36to63,DMAC Channelx Specific Interrupt Register (bits 36to63) Reserved bits - Read Only"
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bitfld.quad 0x0 35. "ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x UID Memory Interface Uncorrectable..,1: Channel x UID Memory Interface Uncorrectable.."
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bitfld.quad 0x0 34. "ECC_PROT_UIDMem_CorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x UID Memory Interface correctable..,1: Channel x UID Memory Interface correctable Error.."
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bitfld.quad 0x0 33. "ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface Uncorrectable..,1: Channel x FIFO Memory Interface Uncorrectable.."
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bitfld.quad 0x0 32. "ECC_PROT_CHMem_CorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface correctable..,1: Channel x FIFO Memory Interface correctable.."
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bitfld.quad 0x0 31. "CH_ABORTED_IntStat,Channel Aborted." "0: Channel is not aborted,1: Channel is aborted"
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bitfld.quad 0x0 30. "CH_DISABLED_IntStat,Channel Disabled." "0: Channel is not disabled,1: Channel is disabled"
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bitfld.quad 0x0 29. "CH_SUSPENDED_IntStat,Channel Suspended." "0: Channel is not suspended,1: Channel is suspended"
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bitfld.quad 0x0 28. "CH_SRC_SUSPENDED_IntStat,Channel Source Suspended." "0: Channel source is not suspended,1: Channel Source is suspended"
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bitfld.quad 0x0 27. "CH_LOCK_CLEARED_IntStat,Channel Lock Cleared." "0: Channel locking is not cleared,1: Channel locking is cleared"
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bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUSREG_26,DMAC Channelx Specific Interrupt Register (bit 26) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 25. "SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error." "0: No Slave Interface Write Parity Errors,1: Slave Interface Write Parity Error detected"
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bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUSREG_22to24,DMAC Channelx Specific Interrupt Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error." "0: No Slave Interface Write On Hold Errors,1: Slave Interface Write On Hold Error detected"
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bitfld.quad 0x0 20. "SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error." "0: No Slave Interface Shadow Register Write On..,1: Slave Interface Shadow Register Write On Valid.."
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bitfld.quad 0x0 19. "SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error." "0: No Slave Interface Write On Channel Enabled Errors,1: Slave Interface Write On Channel Enabled Error.."
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bitfld.quad 0x0 18. "SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error." "0: No Slave Interface Read to Write Only Errors,1: Slave Interface Read to Write Only Error detected"
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bitfld.quad 0x0 17. "SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error." "0: No Slave Interface Write to Read Only Errors,1: Slave Interface Write to Read Only Error detected"
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bitfld.quad 0x0 16. "SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error." "0: No Slave Interface Decode errors,1: Slave Interface Decode Error detected"
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bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUSREG_15,DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error." "0: No Multi-block transfer type Errors,1: Multi-block transfer type Error detected"
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bitfld.quad 0x0 13. "SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error." "0: No Shadow Register / LLI Invalid errors,1: Shadow Register / LLI Invalid error detected"
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bitfld.quad 0x0 12. "LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error." "0: No LLI write Slave Errors,1: LLI Write SLAVE Error detected"
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bitfld.quad 0x0 11. "LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error." "0: No LLI Read Slave Errors,1: LLI read Slave Error detected"
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bitfld.quad 0x0 10. "LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error." "0: NO LLI Write Decode Errors,1: LLI write Decode Error detected"
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bitfld.quad 0x0 9. "LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error." "0: NO LLI Read Decode Errors,1: LLI Read Decode Error detected"
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bitfld.quad 0x0 8. "DST_SLV_ERR_IntStat,Destination Slave Error." "0: No Destination Slave Errors,1: Destination Slave Errors Detected"
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bitfld.quad 0x0 7. "SRC_SLV_ERR_IntStat,Source Slave Error." "0: No Source Slave Errors,1: Source Slave Error Detected"
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bitfld.quad 0x0 6. "DST_DEC_ERR_IntStat,Destination Decode Error." "0: No destination Decode Errors,1: Destination Decode Error Detected"
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bitfld.quad 0x0 5. "SRC_DEC_ERR_IntStat,Source Decode Error." "0: No Source Decode Errors,1: Source Decode Error detected"
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bitfld.quad 0x0 4. "DST_TRANSCOMP_IntStat,Destination Transaction Completed." "0,1"
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bitfld.quad 0x0 3. "SRC_TRANSCOMP_IntStat,Source Transaction Completed." "0,1"
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bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUSREG_2,DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 1. "DMA_TFR_DONE_IntStat,DMA Transfer Done." "0: DMA Transfer not completed,1: DMA Transfer Completed"
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bitfld.quad 0x0 0. "BLOCK_TFR_DONE_IntStat,Block Transfer Done." "0: Block Transfer not completed,1: Block Transfer completed"
group.quad 0x390++0x7
line.quad 0x0 "CH3_INTSIGNAL_ENABLEREG,This register contains fields that are used to enable the generation of port level interrupt at the channel level."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63,DMAC Channelx Interrupt Signal Enable Register (bits 36to63) Reserved bits - Read Only"
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rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
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rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntSignal,Channel Aborted Signal Enable." "0: Disable the propagation of Channel Aborted..,1: Enable the propagation of Channel Aborted.."
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bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntSignal,Channel Disabled Signal Enable." "0: Disable the propagation of Channel Disabled..,1: Enable the propagation of Channel Disabled.."
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bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntSignal,Channel Suspended Signal Enable." "0: Disable the propagation of Channel Suspended..,1: Enable the propagation of Channel Suspended.."
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bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntSignal,Channel Source Suspended Signal Enable." "0: Disable the propagation of Channel Source..,1: Enable the propagation of Channel Source.."
newline
bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntSignal,Channel Lock Cleared Signal Enable." "0: Disable the propagation of Channel Lock Cleared..,1: Enable the propagation of Channel Lock Cleared.."
newline
rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26,DMAC Channelx Interrupt Signal Enable Register (bit 26) Reserved bit - Read Only" "0,1"
newline
rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntSignal,Slave Interface Write Parity Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24,DMAC Channelx Interrupt Signal Enable Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntSignal,Slave Interface Write On Hold Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal,Shadow Register Write On Valid Error Signal Enable." "0: Disable the propagation of Shadow Register Write..,1: Enable the propagation of Shadow register Write.."
newline
bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntSignal,Slave Interface Write On Channel Enabled Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntSignal,Slave Interface Read to write Only Error Signal Enable." "0: Disable the propagation of Slave Interface Read..,1: Enable the propagation of Slave Interface Read.."
newline
bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntSignal,Slave Interface Write to Read Only Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntSignal,Slave Interface Decode Error Signal Enable." "0: Disable the propagation of Slave Interface..,1: Enable the propagation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,Slave Interface Multi Block type Error Signal Enable." "0: Disable the propagation of Slave Interface Multi..,1: Enable the propagation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,Shadow register or LLI Invalid Error Signal Enable." "0: Disable the propagation of Shadow Register or..,1: Enable the propagation of Shadow Register or LLI.."
newline
bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntSignal,LLI WRITE Slave Error Signal Enable." "0: Disable the propagation of LLI WRITE Slave Error..,1: Enable the propagation of LLI WRITE Slave Error.."
newline
bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntSignal,LLI Read Slave Error Signal Enable." "0: Disable the propagation of LLI Read Slave Error..,1: Enable the propagation of LLI Read Slave Error.."
newline
bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntSignal,LLI WRITE Decode Error Signal Enable." "0: Disable the propagation of LLI WRITE Decode..,1: Enable the propagation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntSignal,LLI Read Decode Error Signal Enable." "0: Disable the propagation of LLI Read Decode Error..,1: Enable the propagation of LLI Read Decode Error.."
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bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntSignal,Destination Slave Error Signal Enable." "0: Disable the propagation of Destination Slave..,1: Enable the propagation of Destination Slave.."
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bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntSignal,Source Slave Error Signal Enable." "0: Disable the propagation of Source Slave Error..,1: Enable the propagation of Source Slave Error.."
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bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntSignal,Destination Decode Error Signal Enable." "0: Disable the propagation of Destination Decode..,1: Enable the propagation of Destination Decode.."
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bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntSignal,Source Decode Error Signal Enable." "0: Disable the propagation of Source Decode Error..,1: Enable the propagation of Source Decode Error.."
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bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntSignal,Destination Transaction Completed Signal Enable." "0: Disable the propagation of Destination..,1: Enable the propagation of Destination.."
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bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntSignal,Source Transaction Completed Signal Enable." "0: Disable the propagation of Source Transaction..,1: Enable the propagation of Source Transaction.."
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rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntSignal,DMA Transfer Done Interrupt Signal Enable." "0: Disable the propagation of DMA Transfer Done..,1: Enable the propagation of DMA Transfer Done.."
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bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntSignal,Block Transfer Done Interrupt Signal Enable." "0: Disable the propagation of Block Transfer Done..,1: Enable the propagation of Block Transfer Done.."
wgroup.quad 0x398++0x7
line.quad 0x0 "CH3_INTCLEARREG,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTCLEARREG_36to63,DMAC Channelx Interrupt Clear Register (bits 36to63) Reserved bit - Read Only"
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bitfld.quad 0x0 35. "Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat,ECC Protection Uncorrectable UID Memory Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 34. "Clear_ECC_PROT_UIDMem_CorrERR_IntStat,ECC Protection Correctable UID Memory Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 33. "Clear_ECC_PROT_CHMem_UnCorrERR_IntStat,ECC Protection Uncorrectable Channel Memory Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 32. "Clear_ECC_PROT_CHMem_CorrERR_IntStat,ECC Protection Correctable Channel Memory Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 31. "Clear_CH_ABORTED_IntStat,Channel Aborted Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 30. "Clear_CH_DISABLED_IntStat,Channel Disabled Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 29. "Clear_CH_SUSPENDED_IntStat,Channel Suspended Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 28. "Clear_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 27. "Clear_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTCLEARREG_26,DMAC Channelx Interrupt Clear Register (bit 26) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 25. "Clear_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTCLEARREG_22to24,DMAC Channelx Interrupt Clear Register (bits 22to24) Reserved bit - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "Clear_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 20. "Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 19. "Clear_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 18. "Clear_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 17. "Clear_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 16. "Clear_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTCLEARREG_15,DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 14. "Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 13. "Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 12. "Clear_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 11. "Clear_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 10. "Clear_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 9. "Clear_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 8. "Clear_DST_SLV_ERR_IntStat,Destination Slave Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 7. "Clear_SRC_SLV_ERR_IntStat,Source Slave Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 6. "Clear_DST_DEC_ERR_IntStat,Destination Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 5. "Clear_SRC_DEC_ERR_IntStat,Source Decode Error Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 4. "Clear_DST_TRANSCOMP_IntStat,Destination Transaction Completed Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 3. "Clear_SRC_TRANSCOMP_IntStat,Source Transaction Completed Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTCLEARREG_2,DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only" "0,1"
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bitfld.quad 0x0 1. "Clear_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Clear Bit." "0,1"
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bitfld.quad 0x0 0. "Clear_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Clear Bit." "0,1"
group.quad 0x400++0x2F
line.quad 0x0 "CH4_SAR,The starting source address is programmed by software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While"
hexmask.quad 0x0 0.--63. 1. "SAR,Current Source Address of DMA transfer."
line.quad 0x8 "CH4_DAR,The starting destination address is programmed by the software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer."
hexmask.quad 0x8 0.--63. 1. "DAR,Current Destination Address of DMA transfer."
line.quad 0x10 "CH4_BLOCK_TS,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size."
hexmask.quad 0x10 22.--63. 1. "RSVD_DMAC_CHx_BLOCK_TSREG_63to22,DMAC Channelx Block Transfer Size Register (bits 63to22) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x10 0.--21. 1. "BLOCK_TS,Block Transfer Size."
line.quad 0x18 "CH4_CTL,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.."
bitfld.quad 0x18 63. "SHADOWREG_OR_LLI_VALID,Shadow Register content/Linked List Item valid." "0: Shadow Register content/LLI is invalid,1: Last Shadow Register/LLI is valid"
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bitfld.quad 0x18 62. "SHADOWREG_OR_LLI_LAST,Last Shadow Register/Linked List Item." "0: Not last Shadow Register/LLI,1: Last Shadow Register/LLI"
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rbitfld.quad 0x18 59.--61. "RSVD_DMAC_CHx_CTL_59to61,DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 58. "IOC_BlkTfr,Interrupt On completion of Block Transfer" "0,1"
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rbitfld.quad 0x18 57. "DST_STAT_EN,Destination Status Enable" "0,1"
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rbitfld.quad 0x18 56. "SRC_STAT_EN,Source Status Enable" "0,1"
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hexmask.quad.byte 0x18 48.--55. 1. "AWLEN,Destination Burst Length"
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bitfld.quad 0x18 47. "AWLEN_EN,Destination Burst Length Enable" "0,1"
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hexmask.quad.byte 0x18 39.--46. 1. "ARLEN,Source Burst Length"
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bitfld.quad 0x18 38. "ARLEN_EN,Source Burst Length Enable" "0,1"
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bitfld.quad 0x18 35.--37. "AW_PROT,AXI 'aw_prot' signal" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 32.--34. "AR_PROT,AXI 'ar_prot' signal" "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x18 31. "RSVD_DMAC_CHx_CTL_31,DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 30. "NonPosted_LastWrite_En,Non Posted Last Write Enable" "0: Posted writes may be used throughout the block..,1: Posted writes may be used till the end of the.."
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hexmask.quad.byte 0x18 26.--29. 1. "AW_CACHE,AXI 'aw_cache' signal"
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hexmask.quad.byte 0x18 22.--25. 1. "AR_CACHE,AXI 'ar_cache' signal"
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hexmask.quad.byte 0x18 18.--21. 1. "DST_MSIZE,Destination Burst Transaction Length."
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hexmask.quad.byte 0x18 14.--17. 1. "SRC_MSIZE,Source Burst Transaction Length."
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bitfld.quad 0x18 11.--13. "DST_TR_WIDTH,Destination Transfer Width." "0,1,2,3,4,5,6,7"
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bitfld.quad 0x18 8.--10. "SRC_TR_WIDTH,Source Transfer Width." "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x18 7. "RSVD_DMAC_CHx_CTL_7,DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 6. "DINC,Destination Address Increment." "0: Increment,1: No Change"
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rbitfld.quad 0x18 5. "RSVD_DMAC_CHx_CTL_5,DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only" "0,1"
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bitfld.quad 0x18 4. "SINC,Source Address Increment." "0: Increment,1: No Change"
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rbitfld.quad 0x18 3. "RSVD_DMAC_CHx_CTL_3,DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only" "0,1"
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rbitfld.quad 0x18 2. "DMS,Destination Master Select." "0: AXI master 1,1: AXI Master 2"
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rbitfld.quad 0x18 1. "RSVD_DMAC_CHx_CTL_1,DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only" "0,1"
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rbitfld.quad 0x18 0. "SMS,Source Master Select." "0: AXI master 1,1: AXI Master 2"
line.quad 0x20 "CH4_CFG2,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel."
rbitfld.quad 0x20 63. "RSVD_DMAC_CHx_CFG_63,DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 59.--62. 1. "DST_OSR_LMT,Destination Outstanding Request Limit"
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hexmask.quad.byte 0x20 55.--58. 1. "SRC_OSR_LMT,Source Outstanding Request Limit"
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bitfld.quad 0x20 53.--54. "LOCK_CH_L,Channel Lock Level" "0: Over complete DMA transfer,1: Over DMA block transfer,?,?"
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bitfld.quad 0x20 52. "LOCK_CH,Channel Lock bit" "0,1"
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hexmask.quad.byte 0x20 47.--51. 1. "CH_PRIOR,Channel Priority"
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hexmask.quad.byte 0x20 39.--46. 1. "RSVD_DMAC_CHx_CFG_39to46,DMAC Channelx Transfer Configuration Register (bits 39to46) Reserved bits - Read Only"
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rbitfld.quad 0x20 38. "DST_HWHS_POL,Destination Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
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rbitfld.quad 0x20 37. "SRC_HWHS_POL,Source Hardware Handshaking Interface Polarity." "0: ACTIVE HIGH,1: ACTIVE LOW"
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bitfld.quad 0x20 36. "HS_SEL_DST,Destination Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
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bitfld.quad 0x20 35. "HS_SEL_SRC,Source Software or Hardware Handshaking Select." "0: Hardware handshaking interface,1: Software handshaking interface"
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bitfld.quad 0x20 32.--34. "TT_FC,Transfer Type and Flow Control." "0,1,2,3,4,5,6,7"
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rbitfld.quad 0x20 29.--31. "RSVD_DMAC_CHx_CFG_29to31,DMAC Channelx Transfer Configuration Register (bits 29to31) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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hexmask.quad.byte 0x20 25.--28. 1. "WR_UID,Defines the number of AXI Unique ID's supported for the AXI Write Channel. The value programmed must be less than or equal to DMAX_CH(x)_WR_UID. Otherwise  it is limited by the value DMAX_CH(x)_WR_UID."
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rbitfld.quad 0x20 22.--24. "RSVD_DMAC_CHx_CFG_22to24,DMAC Channelx Transfer Configuration Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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hexmask.quad.byte 0x20 18.--21. 1. "RD_UID,Defines the number of AXI Unique ID's supported for the AXI Read Channel. The value programmed must be less than or equal to DMAX_CH(x)_RD_UID. Otherwise  it is limited by the value DMAX_CH(x)_RD_UID."
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rbitfld.quad 0x20 17. "RSVD_DMAC_CHx_CFG_17,DMAC Channelx Transfer Configuration Register (bit 17) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 11.--16. 1. "DST_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0;"
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rbitfld.quad 0x20 10. "RSVD_DMAC_CHx_CFG_10,DMAC Channelx Transfer Configuration Register (bit 10) Reserved bit - Read Only" "0,1"
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hexmask.quad.byte 0x20 4.--9. 1. "SRC_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise "
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rbitfld.quad 0x20 2.--3. "DST_MULTBLK_TYPE,Destination Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
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rbitfld.quad 0x20 0.--1. "SRC_MULTBLK_TYPE,Source Multi Block Transfer Type." "0: Contiguous,1: Reload,?,?"
line.quad 0x28 "CH4_LLP,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the"
hexmask.quad 0x28 6.--63. 1. "LOC,Starting Address Memory of LLI block"
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hexmask.quad.byte 0x28 1.--5. 1. "RSVD_DMAC_CHx_LLP_1to5,DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only"
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rbitfld.quad 0x28 0. "LMS,LLI master Select" "0: AXI Master 1,1: AXI Master 2"
rgroup.quad 0x430++0x7
line.quad 0x0 "CH4_STATUSREG,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx."
hexmask.quad.tbyte 0x0 47.--63. 1. "RSVD_DMAC_CHx_STATUSREG_47to63,DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 32.--46. 1. "DATA_LEFT_IN_FIFO,Data Left in FIFO."
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hexmask.quad.word 0x0 22.--31. 1. "RSVD_DMAC_CHx_STATUSREG_22to31,DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only"
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hexmask.quad.tbyte 0x0 0.--21. 1. "CMPLTD_BLK_TFR_SIZE,Completed Block Transfer Size."
group.quad 0x438++0xF
line.quad 0x0 "CH4_SWHSSRCREG,Channelx Software handshake Source Register."
hexmask.quad 0x0 6.--63. 1. "RSVD_DMAC_CHx_SWHSSRCREG_6to63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x0 5. "SWHS_LST_SRC_WE,Write Enable bit for Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 4. "SWHS_LST_SRC,Software Handshake Last Request for Channel Source." "0,1"
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bitfld.quad 0x0 3. "SWHS_SGLREQ_SRC_WE,Write Enable bit for Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 2. "SWHS_SGLREQ_SRC,Software Handshake Single Request for Channel Source." "0,1"
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bitfld.quad 0x0 1. "SWHS_REQ_SRC_WE,Write Enable bit for Software Handshake Request for Channel Source." "0,1"
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bitfld.quad 0x0 0. "SWHS_REQ_SRC,Software Handshake Request for Channel Source." "0,1"
line.quad 0x8 "CH4_SWHSDSTREG,Channelx Software handshake Destination Register."
hexmask.quad 0x8 6.--63. 1. "RSVD_DMAC_CHx_SWHSDSTREG_6to63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only"
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bitfld.quad 0x8 5. "SWHS_LST_DST_WE,Write Enable bit for Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 4. "SWHS_LST_DST,Software Handshake Last Request for Channel Destination." "0,1"
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bitfld.quad 0x8 3. "SWHS_SGLREQ_DST_WE,Write Enable bit for Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 2. "SWHS_SGLREQ_DST,Software Handshake Single Request for Channel Destination." "0,1"
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bitfld.quad 0x8 1. "SWHS_REQ_DST_WE,Write Enable bit for Software Handshake Request for Channel Destination." "0,1"
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bitfld.quad 0x8 0. "SWHS_REQ_DST,Software Handshake Request for Channel Destination." "0,1"
wgroup.quad 0x448++0x7
line.quad 0x0 "CH4_BLK_TFR_RESUMEREQREG,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer."
hexmask.quad 0x0 1.--63. 1. "RSVD_DMAC_CHx_BLK_TFR_RESUMEREQREG_1to63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only"
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bitfld.quad 0x0 0. "BLK_TFR_RESUMEREQ,Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer." "0,1"
group.quad 0x450++0xF
line.quad 0x0 "CH4_AXI_IDREG,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad.long 0x0 32.--63. 1. "RSVD_DMAC_CHx_AXI_IDREG_32to63,DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only"
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hexmask.quad.word 0x0 20.--31. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm32to63,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 16.--19. 1. "AXI_WRITE_ID_SUFFIX,AXI Write ID Suffix."
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hexmask.quad.word 0x0 4.--15. 1. "RSVD_DMAC_CHx_AXI_IDREG_IDW_L2NCm1to31,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only"
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hexmask.quad.byte 0x0 0.--3. 1. "AXI_READ_ID_SUFFIX,AXI Read ID Suffix"
line.quad 0x8 "CH4_AXI_QOSREG,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire"
hexmask.quad 0x8 8.--63. 1. "RSVD_DMAC_CHx_AXI_QOSREG_8to63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only"
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hexmask.quad.byte 0x8 4.--7. 1. "AXI_ARQOS,AXI ARQOS."
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hexmask.quad.byte 0x8 0.--3. 1. "AXI_AWQOS,AXI AWQOS."
group.quad 0x480++0x7
line.quad 0x0 "CH4_INTSTATUS_ENABLEREG,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH4_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_32to63,DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only"
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rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntStat,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x UID Memory..,1: Enable the generation Channel x UID Memory.."
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rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation Channel x Channel Memory.."
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rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntStat,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt enable." "0: Disable the generation of Channel x Channel..,1: Enable the generation of Channel x Channel.."
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bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntStat,Channel Aborted Status Enable." "0: Disable the generation of Channel Aborted..,1: Enable the generation of Channel Aborted.."
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bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntStat,Channel Disabled Status Enable." "0: Disable the generation of Channel Disabled..,1: Enable the generation of Channel Disabled.."
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bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntStat,Channel Suspended Status Enable." "0: Disable the generation of Channel Suspended..,1: Enable the generation of Channel Suspended.."
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bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Status Enable." "0: Disable the generation of Channel Source..,1: Enable the generation of Channel Source.."
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bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Status Enable." "0: Disable the generation of Channel LOCK CLEARED..,1: Enable the generation of Channel LOCK CLEARED.."
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rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_26,DMAC Channelx Interrupt Status Register (bit 26) Reserved bit - Read Only" "0,1"
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rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_22to24,DMAC Channelx Interrupt Status Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Status Enable." "0: Disable the generation of Shadow Register Write..,1: Enable the generation of Shadow register Write.."
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bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
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bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Status Enable." "0: Disable the generation of Slave Interface Read..,1: Enable the generation of Slave Interface Read to.."
newline
bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Status Enable." "0: Disable the generation of Slave Interface Write..,1: Enable the generation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Status Enable." "0: Disable the generation of Slave Interface Decode..,1: Enable the generation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Status Enable." "0: Disable the generation of Slave Interface Multi..,1: Enable the generation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Status Enable." "0: Disable the generation of Shadow Register or LLI..,1: Enable the generation of Shadow Register or LLI.."
newline
bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Status Enable." "0: Disable the generation of LLI WRITE Slave Error..,1: Enable the generation of LLI WRITE Slave Error.."
newline
bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Status Enable." "0: Disable the generation of LLI Read Slave Error..,1: Enable the generation of LLI Read Slave Error.."
newline
bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Status Enable." "0: Disable the generation of LLI WRITE Decode Error..,1: Enable the generation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Status Enable." "0: Disable the generation of LLI Read Decode Error..,1: Enable the generation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntStat,Destination Slave Error Status Enable." "0: Disable the generation of Destination Slave..,1: Enable the generation of Destination Slave Error.."
newline
bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntStat,Source Slave Error Status Enable." "0: Disable the generation of Source Slave Error..,1: Enable the generation of Source Slave Error.."
newline
bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntStat,Destination Decode Error Status Enable." "0: Disable the generation of Destination Decode..,1: Enable the generation of Destination Decode.."
newline
bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntStat,Source Decode Error Status Enable." "0: Disable the generation of Source Decode Error..,1: Enable the generation of Source Decode Error.."
newline
bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntStat,Destination Transaction Completed Status Enable." "0: Disable the generation of Destination..,1: Enable the generation of Destination Transaction.."
newline
bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntStat,Source Transaction Completed Status Enable." "0: Disable the generation of Source Transaction..,1: Enable the generation of Source Transaction.."
newline
rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Status Enable." "0: Disable the generation of DMA Transfer Done..,1: Enable the generation of DMA Transfer Done.."
newline
bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Status Enable." "0: Disable the generation of Block Transfer Done..,1: Enable the generation of Block Transfer Done.."
rgroup.quad 0x488++0x7
line.quad 0x0 "CH4_INTSTATUS,Channelx Interrupt Status Register captures the Channelx specific interrupts"
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSTATUSREG_36to63,DMAC Channelx Specific Interrupt Register (bits 36to63) Reserved bits - Read Only"
newline
bitfld.quad 0x0 35. "ECC_PROT_UIDMem_UnCorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x UID Memory Interface Uncorrectable..,1: Channel x UID Memory Interface Uncorrectable.."
newline
bitfld.quad 0x0 34. "ECC_PROT_UIDMem_CorrERR_IntStat,Channel x UID Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x UID Memory Interface correctable..,1: Channel x UID Memory Interface correctable Error.."
newline
bitfld.quad 0x0 33. "ECC_PROT_CHMem_UnCorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Uncorrectable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface Uncorrectable..,1: Channel x FIFO Memory Interface Uncorrectable.."
newline
bitfld.quad 0x0 32. "ECC_PROT_CHMem_CorrERR_IntStat,Channel x FIFO Memory Interface ECC Protection related Correctable Error Interrupt Status bit." "0: No Channel x FIFO Memory Interface correctable..,1: Channel x FIFO Memory Interface correctable.."
newline
bitfld.quad 0x0 31. "CH_ABORTED_IntStat,Channel Aborted." "0: Channel is not aborted,1: Channel is aborted"
newline
bitfld.quad 0x0 30. "CH_DISABLED_IntStat,Channel Disabled." "0: Channel is not disabled,1: Channel is disabled"
newline
bitfld.quad 0x0 29. "CH_SUSPENDED_IntStat,Channel Suspended." "0: Channel is not suspended,1: Channel is suspended"
newline
bitfld.quad 0x0 28. "CH_SRC_SUSPENDED_IntStat,Channel Source Suspended." "0: Channel source is not suspended,1: Channel Source is suspended"
newline
bitfld.quad 0x0 27. "CH_LOCK_CLEARED_IntStat,Channel Lock Cleared." "0: Channel locking is not cleared,1: Channel locking is cleared"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSTATUSREG_26,DMAC Channelx Specific Interrupt Register (bit 26) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 25. "SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error." "0: No Slave Interface Write Parity Errors,1: Slave Interface Write Parity Error detected"
newline
bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSTATUSREG_22to24,DMAC Channelx Specific Interrupt Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error." "0: No Slave Interface Write On Hold Errors,1: Slave Interface Write On Hold Error detected"
newline
bitfld.quad 0x0 20. "SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error." "0: No Slave Interface Shadow Register Write On..,1: Slave Interface Shadow Register Write On Valid.."
newline
bitfld.quad 0x0 19. "SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error." "0: No Slave Interface Write On Channel Enabled Errors,1: Slave Interface Write On Channel Enabled Error.."
newline
bitfld.quad 0x0 18. "SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error." "0: No Slave Interface Read to Write Only Errors,1: Slave Interface Read to Write Only Error detected"
newline
bitfld.quad 0x0 17. "SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error." "0: No Slave Interface Write to Read Only Errors,1: Slave Interface Write to Read Only Error detected"
newline
bitfld.quad 0x0 16. "SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error." "0: No Slave Interface Decode errors,1: Slave Interface Decode Error detected"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUSREG_15,DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error." "0: No Multi-block transfer type Errors,1: Multi-block transfer type Error detected"
newline
bitfld.quad 0x0 13. "SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error." "0: No Shadow Register / LLI Invalid errors,1: Shadow Register / LLI Invalid error detected"
newline
bitfld.quad 0x0 12. "LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error." "0: No LLI write Slave Errors,1: LLI Write SLAVE Error detected"
newline
bitfld.quad 0x0 11. "LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error." "0: No LLI Read Slave Errors,1: LLI read Slave Error detected"
newline
bitfld.quad 0x0 10. "LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error." "0: NO LLI Write Decode Errors,1: LLI write Decode Error detected"
newline
bitfld.quad 0x0 9. "LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error." "0: NO LLI Read Decode Errors,1: LLI Read Decode Error detected"
newline
bitfld.quad 0x0 8. "DST_SLV_ERR_IntStat,Destination Slave Error." "0: No Destination Slave Errors,1: Destination Slave Errors Detected"
newline
bitfld.quad 0x0 7. "SRC_SLV_ERR_IntStat,Source Slave Error." "0: No Source Slave Errors,1: Source Slave Error Detected"
newline
bitfld.quad 0x0 6. "DST_DEC_ERR_IntStat,Destination Decode Error." "0: No destination Decode Errors,1: Destination Decode Error Detected"
newline
bitfld.quad 0x0 5. "SRC_DEC_ERR_IntStat,Source Decode Error." "0: No Source Decode Errors,1: Source Decode Error detected"
newline
bitfld.quad 0x0 4. "DST_TRANSCOMP_IntStat,Destination Transaction Completed." "0,1"
newline
bitfld.quad 0x0 3. "SRC_TRANSCOMP_IntStat,Source Transaction Completed." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUSREG_2,DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "DMA_TFR_DONE_IntStat,DMA Transfer Done." "0: DMA Transfer not completed,1: DMA Transfer Completed"
newline
bitfld.quad 0x0 0. "BLOCK_TFR_DONE_IntStat,Block Transfer Done." "0: Block Transfer not completed,1: Block Transfer completed"
group.quad 0x490++0x7
line.quad 0x0 "CH4_INTSIGNAL_ENABLEREG,This register contains fields that are used to enable the generation of port level interrupt at the channel level."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_36to63,DMAC Channelx Interrupt Signal Enable Register (bits 36to63) Reserved bits - Read Only"
newline
rbitfld.quad 0x0 35. "Enable_ECC_PROT_UIDMem_UnCorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 34. "Enable_ECC_PROT_UIDMem_CorrERR_IntSignal,Channel x Unique ID Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x UID Memory..,1: Enable the propagation of Channel x UID Memory.."
newline
rbitfld.quad 0x0 33. "Enable_ECC_PROT_CHMem_UnCorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Uncorrectable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
rbitfld.quad 0x0 32. "Enable_ECC_PROT_CHMem_CorrERR_IntSignal,Channel x Channel Memory Interface ECC Protection Correctable Error Interrupt Signal enable." "0: Disable the propagation of Channel x Channel..,1: Enable the propagation of Channel x Channel.."
newline
bitfld.quad 0x0 31. "Enable_CH_ABORTED_IntSignal,Channel Aborted Signal Enable." "0: Disable the propagation of Channel Aborted..,1: Enable the propagation of Channel Aborted.."
newline
bitfld.quad 0x0 30. "Enable_CH_DISABLED_IntSignal,Channel Disabled Signal Enable." "0: Disable the propagation of Channel Disabled..,1: Enable the propagation of Channel Disabled.."
newline
bitfld.quad 0x0 29. "Enable_CH_SUSPENDED_IntSignal,Channel Suspended Signal Enable." "0: Disable the propagation of Channel Suspended..,1: Enable the propagation of Channel Suspended.."
newline
bitfld.quad 0x0 28. "Enable_CH_SRC_SUSPENDED_IntSignal,Channel Source Suspended Signal Enable." "0: Disable the propagation of Channel Source..,1: Enable the propagation of Channel Source.."
newline
bitfld.quad 0x0 27. "Enable_CH_LOCK_CLEARED_IntSignal,Channel Lock Cleared Signal Enable." "0: Disable the propagation of Channel Lock Cleared..,1: Enable the propagation of Channel Lock Cleared.."
newline
rbitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_26,DMAC Channelx Interrupt Signal Enable Register (bit 26) Reserved bit - Read Only" "0,1"
newline
rbitfld.quad 0x0 25. "Enable_SLVIF_WRPARITY_ERR_IntSignal,Slave Interface Write Parity Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
rbitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTSIGNAL_ENABLEREG_22to24,DMAC Channelx Interrupt Signal Enable Register (bits 22to24) Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Enable_SLVIF_WRONHOLD_ERR_IntSignal,Slave Interface Write On Hold Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 20. "Enable_SLVIF_SHADOWREG_WRON_VALID_ERR_IntSignal,Shadow Register Write On Valid Error Signal Enable." "0: Disable the propagation of Shadow Register Write..,1: Enable the propagation of Shadow register Write.."
newline
bitfld.quad 0x0 19. "Enable_SLVIF_WRONCHEN_ERR_IntSignal,Slave Interface Write On Channel Enabled Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 18. "Enable_SLVIF_RD2RWO_ERR_IntSignal,Slave Interface Read to write Only Error Signal Enable." "0: Disable the propagation of Slave Interface Read..,1: Enable the propagation of Slave Interface Read.."
newline
bitfld.quad 0x0 17. "Enable_SLVIF_WR2RO_ERR_IntSignal,Slave Interface Write to Read Only Error Signal Enable." "0: Disable the propagation of Slave Interface Write..,1: Enable the propagation of Slave Interface Write.."
newline
bitfld.quad 0x0 16. "Enable_SLVIF_DEC_ERR_IntSignal,Slave Interface Decode Error Signal Enable." "0: Disable the propagation of Slave Interface..,1: Enable the propagation of Slave Interface Decode.."
newline
rbitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Enable_SLVIF_MULTIBLKTYPE_ERR_IntSignal,Slave Interface Multi Block type Error Signal Enable." "0: Disable the propagation of Slave Interface Multi..,1: Enable the propagation of Slave Interface Multi.."
newline
bitfld.quad 0x0 13. "Enable_SHADOWREG_OR_LLI_INVALID_ERR_IntSignal,Shadow register or LLI Invalid Error Signal Enable." "0: Disable the propagation of Shadow Register or..,1: Enable the propagation of Shadow Register or LLI.."
newline
bitfld.quad 0x0 12. "Enable_LLI_WR_SLV_ERR_IntSignal,LLI WRITE Slave Error Signal Enable." "0: Disable the propagation of LLI WRITE Slave Error..,1: Enable the propagation of LLI WRITE Slave Error.."
newline
bitfld.quad 0x0 11. "Enable_LLI_RD_SLV_ERR_IntSignal,LLI Read Slave Error Signal Enable." "0: Disable the propagation of LLI Read Slave Error..,1: Enable the propagation of LLI Read Slave Error.."
newline
bitfld.quad 0x0 10. "Enable_LLI_WR_DEC_ERR_IntSignal,LLI WRITE Decode Error Signal Enable." "0: Disable the propagation of LLI WRITE Decode..,1: Enable the propagation of LLI WRITE Decode Error.."
newline
bitfld.quad 0x0 9. "Enable_LLI_RD_DEC_ERR_IntSignal,LLI Read Decode Error Signal Enable." "0: Disable the propagation of LLI Read Decode Error..,1: Enable the propagation of LLI Read Decode Error.."
newline
bitfld.quad 0x0 8. "Enable_DST_SLV_ERR_IntSignal,Destination Slave Error Signal Enable." "0: Disable the propagation of Destination Slave..,1: Enable the propagation of Destination Slave.."
newline
bitfld.quad 0x0 7. "Enable_SRC_SLV_ERR_IntSignal,Source Slave Error Signal Enable." "0: Disable the propagation of Source Slave Error..,1: Enable the propagation of Source Slave Error.."
newline
bitfld.quad 0x0 6. "Enable_DST_DEC_ERR_IntSignal,Destination Decode Error Signal Enable." "0: Disable the propagation of Destination Decode..,1: Enable the propagation of Destination Decode.."
newline
bitfld.quad 0x0 5. "Enable_SRC_DEC_ERR_IntSignal,Source Decode Error Signal Enable." "0: Disable the propagation of Source Decode Error..,1: Enable the propagation of Source Decode Error.."
newline
bitfld.quad 0x0 4. "Enable_DST_TRANSCOMP_IntSignal,Destination Transaction Completed Signal Enable." "0: Disable the propagation of Destination..,1: Enable the propagation of Destination.."
newline
bitfld.quad 0x0 3. "Enable_SRC_TRANSCOMP_IntSignal,Source Transaction Completed Signal Enable." "0: Disable the propagation of Source Transaction..,1: Enable the propagation of Source Transaction.."
newline
rbitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Enable_DMA_TFR_DONE_IntSignal,DMA Transfer Done Interrupt Signal Enable." "0: Disable the propagation of DMA Transfer Done..,1: Enable the propagation of DMA Transfer Done.."
newline
bitfld.quad 0x0 0. "Enable_BLOCK_TFR_DONE_IntSignal,Block Transfer Done Interrupt Signal Enable." "0: Disable the propagation of Block Transfer Done..,1: Enable the propagation of Block Transfer Done.."
wgroup.quad 0x498++0x7
line.quad 0x0 "CH4_INTCLEARREG,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)."
hexmask.quad.long 0x0 36.--63. 1. "RSVD_DMAC_CHx_INTCLEARREG_36to63,DMAC Channelx Interrupt Clear Register (bits 36to63) Reserved bit - Read Only"
newline
bitfld.quad 0x0 35. "Clear_ECC_PROT_UIDMem_UnCorrERR_IntStat,ECC Protection Uncorrectable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 34. "Clear_ECC_PROT_UIDMem_CorrERR_IntStat,ECC Protection Correctable UID Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 33. "Clear_ECC_PROT_CHMem_UnCorrERR_IntStat,ECC Protection Uncorrectable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 32. "Clear_ECC_PROT_CHMem_CorrERR_IntStat,ECC Protection Correctable Channel Memory Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 31. "Clear_CH_ABORTED_IntStat,Channel Aborted Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 30. "Clear_CH_DISABLED_IntStat,Channel Disabled Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 29. "Clear_CH_SUSPENDED_IntStat,Channel Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 28. "Clear_CH_SRC_SUSPENDED_IntStat,Channel Source Suspended Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 27. "Clear_CH_LOCK_CLEARED_IntStat,Channel Lock Cleared Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 26. "RSVD_DMAC_CHx_INTCLEARREG_26,DMAC Channelx Interrupt Clear Register (bit 26) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 25. "Clear_SLVIF_WRPARITY_ERR_IntStat,Slave Interface Write Parity Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 22.--24. "RSVD_DMAC_CHx_INTCLEARREG_22to24,DMAC Channelx Interrupt Clear Register (bits 22to24) Reserved bit - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 21. "Clear_SLVIF_WRONHOLD_ERR_IntStat,Slave Interface Write On Hold Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 20. "Clear_SLVIF_SHADOWREG_WRON_VALID_ERR_IntStat,Shadow Register Write On Valid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 19. "Clear_SLVIF_WRONCHEN_ERR_IntStat,Slave Interface Write On Channel Enabled Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 18. "Clear_SLVIF_RD2RWO_ERR_IntStat,Slave Interface Read to write Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 17. "Clear_SLVIF_WR2RO_ERR_IntStat,Slave Interface Write to Read Only Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 16. "Clear_SLVIF_DEC_ERR_IntStat,Slave Interface Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 15. "RSVD_DMAC_CHx_INTCLEARREG_15,DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 14. "Clear_SLVIF_MULTIBLKTYPE_ERR_IntStat,Slave Interface Multi Block type Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 13. "Clear_SHADOWREG_OR_LLI_INVALID_ERR_IntStat,Shadow register or LLI Invalid Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 12. "Clear_LLI_WR_SLV_ERR_IntStat,LLI WRITE Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 11. "Clear_LLI_RD_SLV_ERR_IntStat,LLI Read Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 10. "Clear_LLI_WR_DEC_ERR_IntStat,LLI WRITE Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 9. "Clear_LLI_RD_DEC_ERR_IntStat,LLI Read Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 8. "Clear_DST_SLV_ERR_IntStat,Destination Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 7. "Clear_SRC_SLV_ERR_IntStat,Source Slave Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 6. "Clear_DST_DEC_ERR_IntStat,Destination Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 5. "Clear_SRC_DEC_ERR_IntStat,Source Decode Error Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 4. "Clear_DST_TRANSCOMP_IntStat,Destination Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 3. "Clear_SRC_TRANSCOMP_IntStat,Source Transaction Completed Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 2. "RSVD_DMAC_CHx_INTCLEARREG_2,DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only" "0,1"
newline
bitfld.quad 0x0 1. "Clear_DMA_TFR_DONE_IntStat,DMA Transfer Done Interrupt Clear Bit." "0,1"
newline
bitfld.quad 0x0 0. "Clear_BLOCK_TFR_DONE_IntStat,Block Transfer Done Interrupt Clear Bit." "0,1"
tree.end
tree.end
tree "ECC (Error Checking and Correction Controller)"
base ad:0x0
tree "ECC_EMAC0_RX"
base ad:0x108C0000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "ECC_EMAC0_TX"
base ad:0x108C0400
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
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eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "ECC_EMAC1_RX"
base ad:0x108C0800
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
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eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "ECC_EMAC1_TX"
base ad:0x108C0C00
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "ECC_EMAC2_RX"
base ad:0x108C1000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "ECC_EMAC2_TX"
base ad:0x108C1400
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "ECC_USB1_CACHE"
base ad:0x108C4C00
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "ECC_USB1_RX"
base ad:0x108C4400
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "ECC_USB1_TX"
base ad:0x108C4800
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "ECC_USBOTG0"
base ad:0x108C4000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree.end
tree "EMAC (Ethernet Media Access Controller)"
base ad:0x0
tree "EMAC_0"
base ad:0x10810000
group.long 0x0++0x17
line.long 0x0 "MAC_Tx_Configuration,The MAC Transmit Configuration register establishes the operating mode of the MAC transmitter."
bitfld.long 0x0 29.--31. "SS,Speed Selection." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 28. "Reserved_G9991EN,Reserved." "0,1"
newline
rbitfld.long 0x0 27. "Reserved_GT9WH,Reserved." "0,1"
newline
rbitfld.long 0x0 26. "Reserved_26,Reserved." "0,1"
newline
rbitfld.long 0x0 25. "Reserved_VNM,Reserved." "0,1"
newline
rbitfld.long 0x0 24. "Reserved_VNE,Reserved." "0,1"
newline
rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1"
newline
bitfld.long 0x0 20.--22. "SARC,Source Address Insertion or Replacement Control." "?,?,2: ,3: ,?,?,?,?"
newline
rbitfld.long 0x0 19. "Reserved_PEN,Reserved." "0,1"
newline
rbitfld.long 0x0 18. "Reserved_PCHM,Reserved." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "JD,Jabber Disable." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 13. "LUD,Link Up or Down." "0: Link down,1: Link up"
newline
bitfld.long 0x0 12. "TC,Transmit Configuration in RGMII." "0: Disable Transmit Configuration in RGMII,1: Enable Transmit Configuration in RGMII"
newline
bitfld.long 0x0 11. "IFP,IPG Control" "0,1"
newline
bitfld.long 0x0 8.--10. "IPG,Inter-Packet Gap" "0: 96 bit times,1: 88 bit times,2: 80 bit times,3: 72 bit times,4: 64 bit times,?,?,7: Reserved"
newline
hexmask.long.byte 0x0 4.--7. 1. "ISR,IFG Stretch Ratio."
newline
bitfld.long 0x0 3. "ISM,IFG Stretch Mode." "0,1"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 1. "DDIC,Disable DIC Algorithm." "0,1"
newline
bitfld.long 0x0 0. "TE,Transmitter Enable." "0,1"
line.long 0x4 "MAC_Rx_Configuration,The MAC Receive Configuration register establishes the operating mode of the MAC receiver."
bitfld.long 0x4 31. "ARPEN,ARP enable." "0,1"
newline
rbitfld.long 0x4 30. "Reserved_ELEN,Reserved." "0,1"
newline
hexmask.long.word 0x4 16.--29. 1. "GPSL,Giant Packet Size Limit."
newline
rbitfld.long 0x4 15. "Reserved_PRXM,Reserved." "0,1"
newline
bitfld.long 0x4 12.--14. "HDSMS,Maximum Size for Splitting the Header Data." "0: 64 bytes,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1023 bytes,?,?,?"
newline
bitfld.long 0x4 11. "S2KP,IEEE 802.3as Support for 2K Packets." "0,1"
newline
bitfld.long 0x4 10. "LM,Loopback Mode." "0,1"
newline
bitfld.long 0x4 9. "IPC,Checksum Offload." "0,1"
newline
bitfld.long 0x4 8. "JE,Jumbo Packet Enable." "0,1"
newline
bitfld.long 0x4 7. "WD,Watchdog Disable." "0,1"
newline
bitfld.long 0x4 6. "GPSLCE,Giant Packet Size Limit Control Enable." "0,1"
newline
bitfld.long 0x4 5. "USP,Unicast Slow Protocol Packet Detect." "0,1"
newline
bitfld.long 0x4 4. "SPEN,Slow Protocol Detection Enable." "0,1"
newline
bitfld.long 0x4 3. "DCRCC,Disable CRC Checking for Received Packets." "0,1"
newline
bitfld.long 0x4 2. "CST,CRC stripping for Type packets." "0,1"
newline
bitfld.long 0x4 1. "ACS,Automatic Pad or CRC Stripping." "0,1"
newline
bitfld.long 0x4 0. "RE,Receiver Enable." "0,1"
line.long 0x8 "MAC_Packet_Filter,The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of.."
bitfld.long 0x8 31. "RA,Receive All." "0,1"
newline
hexmask.long.byte 0x8 23.--30. 1. "Reserved_30_23,Reserved."
newline
rbitfld.long 0x8 22. "Reserved_VUCC,Reserved." "0,1"
newline
bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets." "0,1"
newline
bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable." "0,1"
newline
rbitfld.long 0x8 17.--19. "Reserved_19_17,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable." "0,1"
newline
rbitfld.long 0x8 13.--15. "Reserved_15_13,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 11.--12. "DHLFRS,DA Hash Index or L3/L4 Filter Number in Receive Status." "0: Use both backward compatible DA hash index and..,1: Use combined DA hash table index and L3/L4..,2: Use combined DA hash table index and L3/L4..,3: Reserved"
newline
bitfld.long 0x8 10. "HPF,Hash or Perfect Filter." "0,1"
newline
bitfld.long 0x8 9. "SAF,Source Address Filter Enable." "0,1"
newline
bitfld.long 0x8 8. "SAIF,SA Inverse Filtering." "0,1"
newline
bitfld.long 0x8 6.--7. "PCF,Pass Control Packets." "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,?,?"
newline
bitfld.long 0x8 5. "DBF,Disable Broadcast Packets." "0,1"
newline
bitfld.long 0x8 4. "PM,Pass All Multicast." "0,1"
newline
bitfld.long 0x8 3. "DAIF,DA Inverse Filtering." "0,1"
newline
bitfld.long 0x8 2. "HMC,Hash Multicast." "0,1"
newline
bitfld.long 0x8 1. "HUC,Hash Unicast." "0,1"
newline
bitfld.long 0x8 0. "PR,Promiscuous Mode." "0,1"
line.long 0xC "MAC_WD_JB_Timeout,The Watchdog and Jabber Timeout register controls the watchdog timeout limit for the received packets and jabber timeout limit for transmitted packets."
hexmask.long.byte 0xC 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0xC 24. "PJE,Programmable Jabber Enable." "0,1"
newline
hexmask.long.byte 0xC 20.--23. 1. "Reserved_23_20,Reserved."
newline
hexmask.long.byte 0xC 16.--19. 1. "JTO,Jabber Timeout."
newline
hexmask.long.byte 0xC 9.--15. 1. "Reserved_15_9,Reserved."
newline
bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable." "0,1"
newline
hexmask.long.byte 0xC 4.--7. 1. "Reserved_7_4,Reserved."
newline
hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout."
line.long 0x10 "MAC_Hash_Table_Reg0,The 64-bit hash table is used for group address filtering. For hash filtering. the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC are used to index the.."
hexmask.long 0x10 0.--31. 1. "HT31T0,Lower 32 bits of Hash Table."
line.long 0x14 "MAC_Hash_Table_Reg1,The 64-bit hash table is used for group address filtering. For hash filtering. the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC are used to index the.."
hexmask.long 0x14 0.--31. 1. "HT31T0,Upper 32 bits of Hash Table."
group.long 0x50++0x7
line.long 0x0 "MAC_VLAN_Tag_Ctrl,MAC_VLAN_Tag_Ctrl register is a re-defined version of MAC_VLAN_Tag register. This register holds the control and addressing fields required for indirect accessing of the MAC_VLAN_Tag_Filter registers. when Extended Internal Rx VLAN.."
bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status." "0,1"
newline
rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive." "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
newline
bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag for VLAN hash filtering." "0,1"
newline
bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing." "0,1"
newline
bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable." "0,1"
newline
bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status." "0,1"
newline
rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1"
newline
bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive." "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
newline
bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check for VLAN hash filtering." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match for VLAN hash filtering." "0,1"
newline
bitfld.long 0x0 18. "ESVL,Enable S-VLAN." "0,1"
newline
bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match/Result Enable." "0,1"
newline
bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison for VLAN hash filtering." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_ERIVTL,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 12.--13. "Reserved_EROVTL,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x0 7.--11. 1. "Reserved_11_7,Reserved."
newline
hexmask.long.byte 0x0 2.--6. 1. "OFS,Offset."
newline
bitfld.long 0x0 1. "CT,Command Type." "0,1"
newline
bitfld.long 0x0 0. "OB,Operation Busy." "0,1"
line.long 0x4 "MAC_VLAN_Tag_Data,This register holds the read/write data for Indirect Access of the Per MAC_VLAN_Tag_Filter registers. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field must.."
hexmask.long.byte 0x4 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x4 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x4 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x4 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x4 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag Identifier for Receive Packets."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter0,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter1,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter10,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter11,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter12,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter13,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter14,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter15,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter16,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter17,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter18,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter19,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter2,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter20,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter21,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter22,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter23,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter24,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter25,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter26,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter27,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter28,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter29,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter3,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter30,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter31,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter4,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter5,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter6,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter7,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter8,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x7
line.long 0x0 "MAC_VLAN_Tag_Filter9,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
line.long 0x4 "MAC_VLAN_Hash_Table,When the ERSVLM bit of MAC_VLAN_Tag register is set. the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the.."
hexmask.long.word 0x4 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "VLHT,VLAN Hash Table."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl,The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls."
rbitfld.long 0x0 31. "BUSY,BUSY." "0,1"
newline
bitfld.long 0x0 30. "RDWR,Read Write Control." "0,1"
newline
rbitfld.long 0x0 27.--29. "Reserved_29_y,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24.--26. "ADDR,Address." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 21. "CBTI,Channel Based Tag Insertion." "0,1"
newline
bitfld.long 0x0 20. "VLTI,VLAN Tag Input." "0,1"
newline
bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
bitfld.long 0x0 18. "VLP,VLAN Priority Control." "0,1"
newline
bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets." "0: No VLAN tag deletion,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl0,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl1,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl10,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl11,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl12,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl13,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl14,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl15,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl2,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl3,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl4,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl5,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl6,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl7,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl8,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x7
line.long 0x0 "MAC_VLAN_Incl9,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
line.long 0x4 "MAC_Inner_VLAN_Incl,The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls."
hexmask.long.word 0x4 21.--31. 1. "Reserved_31_21,Reserved."
newline
bitfld.long 0x4 20. "VLTI,VLAN Tag Input." "0,1"
newline
bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
bitfld.long 0x4 18. "VLP,VLAN Priority Control." "0,1"
newline
bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets." "0: No VLAN tag deletion,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
newline
hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x6C++0x2F
line.long 0x0 "MAC_Rx_Eth_Type_Match,The receive Ethernet type match register contains the ether type value that needs to be compared with the ether length/type field of the received packet. The result is indicated in the packet_type field of receive status word. This.."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0x0 0.--15. 1. "ET,Ethernet Type."
line.long 0x4 "MAC_Q0_Tx_Flow_Ctrl,The MAC_Q0_Tx_Flow_Ctrl register controls the generation of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a.."
hexmask.long.word 0x4 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x4 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x4 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,2: Pause Time minus 36 Slot Times,3: Pause Time minus 144 Slot Times,4: Pause Time minus 256 Slot Times,?,?,7: Reserved"
newline
rbitfld.long 0x4 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x4 0. "FCB,Flow Control Busy or Backpressure Activate." "0,1"
line.long 0x8 "MAC_Q1_Tx_Flow_Ctrl,The MAC_Q1_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x8 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x8 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x8 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x8 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x8 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x8 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x8 0. "FCB,Flow Control Busy." "0,1"
line.long 0xC "MAC_Q2_Tx_Flow_Ctrl,The MAC_Q2_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0xC 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0xC 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0xC 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0xC 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0xC 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0xC 0. "FCB,Flow Control Busy." "0,1"
line.long 0x10 "MAC_Q3_Tx_Flow_Ctrl,The MAC_Q3_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x10 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x10 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x10 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x10 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x10 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x10 0. "FCB,Flow Control Busy." "0,1"
line.long 0x14 "MAC_Q4_Tx_Flow_Ctrl,The MAC_Q4_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x14 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x14 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x14 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x14 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x14 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x14 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x14 0. "FCB,Flow Control Busy." "0,1"
line.long 0x18 "MAC_Q5_Tx_Flow_Ctrl,The MAC_Q5_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x18 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x18 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x18 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x18 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x18 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x18 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x18 0. "FCB,Flow Control Busy." "0,1"
line.long 0x1C "MAC_Q6_Tx_Flow_Ctrl,The MAC_Q6_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x1C 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x1C 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x1C 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x1C 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x1C 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x1C 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x1C 0. "FCB,Flow Control Busy." "0,1"
line.long 0x20 "MAC_Q7_Tx_Flow_Ctrl,The MAC_Q7_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x20 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x20 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x20 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x20 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x20 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x20 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x20 0. "FCB,Flow Control Busy." "0,1"
line.long 0x24 "MAC_Rx_Flow_Ctrl,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet."
hexmask.long.tbyte 0x24 9.--31. 1. "Reserved_31_9,Reserved."
newline
bitfld.long 0x24 8. "PFCE,Priority Based Flow Control Enable." "0: Enables generation and reception of IEEE 802,1: Enables generation and reception of.."
newline
hexmask.long.byte 0x24 2.--7. 1. "Reserved_7_2,Reserved."
newline
bitfld.long 0x24 1. "UP,Unicast Pause Packet Detect." "0,1"
newline
bitfld.long 0x24 0. "RFE,Receive Flow Control Enable." "0: When MAC operates in half-duplex mode,1: When MAC operates in full-duplex mode"
line.long 0x28 "MAC_RxQ_Ctrl4,The Receive Queue Control 4 register controls the routing of"
hexmask.long.byte 0x28 27.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x28 24.--26. "PMCBCQ,Preemption Multicast/Broadcast Queue." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 20.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x28 17.--19. "VFFQ,VLAN Tag Filter Fail Packets Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable." "0: VLAN tag Filter Fail Packets Queuing is disabled,1: VLAN tag Filter Fail Packets Queuing is enabled"
newline
hexmask.long.byte 0x28 12.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x28 9.--11. "MFFQ,Multicast Address Filter Fail Packets Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 8. "MFFQE,Multicast Filter Fail Packets Queuing Enable." "0: Multicast Address Filter Fail Packets Queuing is..,1: Multicast Address Filter Fail Packets Queuing is.."
newline
hexmask.long.byte 0x28 4.--7. 1. "Reserved_7_y,Reserved."
newline
bitfld.long 0x28 1.--3. "UFFQ,Unicast Address Filter Fail Packets Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 0. "UFFQE,Unicast Filter Fail Packets Queuing Enable." "0: Unicast Address Filter Fail Packets Queuing is..,1: Unicast Address Filter Fail Packets Queuing is.."
line.long 0x2C "MAC_RxQ_Ctrl5,The Receive Queue Control 5 register allows selection of start offset of the Receive queue from which received packets are routed based on VLAN Tag Priority field."
hexmask.long 0x2C 4.--31. 1. "Reserved_31_4,Reserved."
newline
hexmask.long.byte 0x2C 0.--3. 1. "PRQSO,Priority Receive Queue Start Offset."
group.long 0xA0++0xF
line.long 0x0 "MAC_RxQ_Ctrl0,The Receive Queue Control 0 register activates the queue management in the MAC Receiver. This register is present only when you select multiple queues in the Receive path."
rbitfld.long 0x0 30.--31. "Reserved_RXQ15EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 28.--29. "Reserved_RXQ14EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 26.--27. "Reserved_RXQ13EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 24.--25. "Reserved_RXQ12EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 22.--23. "Reserved_RXQ11EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 20.--21. "Reserved_RXQ10EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 18.--19. "Reserved_RXQ9EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 16.--17. "Reserved_RXQ8EN,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "RXQ7EN,Receive Queue 7 Enable." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RXQ6EN,Receive Queue 6 Enable." "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "RXQ5EN,Receive Queue 5 Enable." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RXQ4EN,Receive Queue 4 Enable." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "RXQ3EN,Receive Queue 3 Enable." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RXQ2EN,Receive Queue 2 Enable." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "RXQ1EN,Receive Queue 1 Enable." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RXQ0EN,Receive Queue 0 Enable." "0: Not enabled,1: Queue 0 enabled for Audio Video Bridging,2: Queue 0 enabled for Data Center Bridging/Generic,3: Reserved"
line.long 0x4 "MAC_RxQ_Ctrl1,This register allows the selection of the Receive queues to which the received untagged or special packets are routed or written. This register is present only when you select multiple queues in the Receive path."
hexmask.long.byte 0x4 28.--31. 1. "AVCPQ,AV Control Packets Queue."
newline
hexmask.long.byte 0x4 24.--27. 1. "PTPQ,PTP Packets Queue."
newline
bitfld.long 0x4 23. "TACPQE,Tagged AV Control Packets Queuing Enable." "0,1"
newline
bitfld.long 0x4 21.--22. "TPQC,Tagged PTP over Ethernet Packets Queuing Control." "0: VLAN Tagged PTP over Ethernet packets are routed..,1: VLAN Tagged PTP over Ethernet packets are routed..,2: VLAN Tagged PTP over Ethernet packets are routed..,3: Reserved"
newline
bitfld.long 0x4 20. "OMCBCQ,Programmable control for Over-riding MCBCQ Priority." "0,1"
newline
hexmask.long.byte 0x4 16.--19. 1. "DCBCPQ,DCB Control Packets Queue."
newline
bitfld.long 0x4 15. "MCBCQEN,Multicast or Broadcast Queue Enable." "0,1"
newline
rbitfld.long 0x4 12.--14. "Reserved_14_12,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 8.--11. 1. "MCBCQ,Multicast or Broadcast Queue."
newline
hexmask.long.byte 0x4 4.--7. 1. "RQ,Frame Preemption Residue Queue"
newline
hexmask.long.byte 0x4 0.--3. 1. "UPQ,Untagged Packet Queue."
line.long 0x8 "MAC_RxQ_Ctrl2,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the Rx Queues 0 to 3. This register is present when multiple Rx Queues are selected while configuring the controller."
hexmask.long.byte 0x8 24.--31. 1. "PSRQ3,Priorities Selected in the Receive Queue 3."
newline
hexmask.long.byte 0x8 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2."
newline
hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1."
newline
hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0."
line.long 0xC "MAC_RxQ_Ctrl3,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the Rx Queues 4 to 7. This register is present when the 'Enable Data Center Bridging' option is selected and with more.."
hexmask.long.byte 0xC 24.--31. 1. "PSRQ7,Priorities Selected in the Receive Queue 7."
newline
hexmask.long.byte 0xC 16.--23. 1. "PSRQ6,Priorities Selected in the Receive Queue 6."
newline
hexmask.long.byte 0xC 8.--15. 1. "PSRQ5,Priorities Selected in the Receive Queue 5."
newline
hexmask.long.byte 0xC 0.--7. 1. "PSRQ4,Priorities Selected in the Receive Queue 4."
rgroup.long 0xB0++0x3
line.long 0x0 "MAC_Interrupt_Status,The Interrupt Status register contains the status of interrupts."
hexmask.long.byte 0x0 26.--31. 1. "Reserved_31_26,Reserved."
newline
bitfld.long 0x0 24.--25. "LS,Link Status." "0: Half Duplex,1: Full Duplex,2: 1Gbps,3: Reserved"
newline
bitfld.long 0x0 23. "Reserved_PCIS,Reserved." "0,1"
newline
hexmask.long.byte 0x0 19.--22. 1. "Reserved_22_19,Reserved."
newline
bitfld.long 0x0 18. "MFRIS,MMC FPE Receive Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "MFTIS,MMC FPE Transmit Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "FPEIS,Frame Preemption Interrupt Status" "0,1"
newline
bitfld.long 0x0 15. "GPIIS,GPI Interrupt Status." "0,1"
newline
bitfld.long 0x0 14. "RXESIS,Receive Error Status Interrupt." "0,1"
newline
bitfld.long 0x0 13. "TXESIS,Transmit Error Status Interrupt." "0,1"
newline
bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status." "0,1"
newline
bitfld.long 0x0 11. "MMCRXIPIS,MMC Receive Checksum Offload Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status." "0,1"
newline
bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status." "0,1"
newline
bitfld.long 0x0 6.--8. "Reserved_8_6,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 5. "Reserved_LPIIS,Reserved." "0,1"
newline
bitfld.long 0x0 4. "Reserved_PMTIS,Reserved." "0,1"
newline
bitfld.long 0x0 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 1. "SMI,SMA Interrupt." "0,1"
newline
bitfld.long 0x0 0. "LSI,Link Status change Interrupt." "0,1"
group.long 0xB4++0x3
line.long 0x0 "MAC_Interrupt_Enable,The Interrupt Enable register contains the masks for generating the interrupts."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "FPEIE,Frame Preemption Interrupt Enable" "0,1"
newline
bitfld.long 0x0 14. "RXESIE,Receive Error Status Interrupt Enable." "0,1"
newline
bitfld.long 0x0 13. "TXESIE,Transmit Error Status Interrupt Enable." "0,1"
newline
bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable." "0,1"
newline
hexmask.long.byte 0x0 6.--11. 1. "Reserved_11_6,Reserved."
newline
rbitfld.long 0x0 5. "Reserved_LPIIE,Reserved." "0,1"
newline
rbitfld.long 0x0 4. "Reserved_PMTIE,Reserved." "0,1"
newline
rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "LSIE,Link Status Change Interrupt Enable." "0,1"
rgroup.long 0xB8++0x3
line.long 0x0 "MAC_Rx_Tx_Status,The Receive Transmit Status register contains the Receive and Transmit Error status."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
newline
bitfld.long 0x0 13. "PCE,Payload Checksum Error." "0,1"
newline
bitfld.long 0x0 12. "IHE,IP Header Error." "0,1"
newline
bitfld.long 0x0 9.--11. "Reserved_11_9,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout." "0,1"
newline
bitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 5. "EXCOL,Excessive Collisions" "0,1"
newline
bitfld.long 0x0 4. "LCOL,Late Collision" "0,1"
newline
bitfld.long 0x0 3. "EXDEF,Excessive Deferral" "0,1"
newline
bitfld.long 0x0 2. "LCARR,Loss of Carrier" "0,1"
newline
bitfld.long 0x0 1. "NCARR,No Carrier" "0,1"
newline
bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout." "0,1"
rgroup.long 0x110++0x7
line.long 0x0 "MAC_Version,The version register identifies the version of DWC_xgmac. This register contains two bytes: one that Synopsys uses to identify the controller release number. and the other that you set while configuring the controller."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
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hexmask.long.byte 0x0 16.--23. 1. "USERVER,User-defined Version (configured with coreConsultant)"
newline
hexmask.long.byte 0x0 8.--15. 1. "DEVID,Indicates the Device family"
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hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,Synopsys-defined Version (2.0)"
line.long 0x4 "MAC_Debug,The Debug register provides the debug status of various MAC blocks."
hexmask.long.word 0x4 19.--31. 1. "Reserved_31_19,Reserved."
newline
bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status." "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control packet,3: Transferring input packet for transmission"
newline
bitfld.long 0x4 16. "TPESTS,MAC GMII Transmit Protocol Engine Status." "0,1"
newline
hexmask.long.word 0x4 3.--15. 1. "Reserved_15_3,Reserved."
newline
bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status." "0,1,2,3"
newline
bitfld.long 0x4 0. "RPESTS,MAC  GMII  Receive Protocol Engine Status." "0,1"
rgroup.long 0x11C++0x13
line.long 0x0 "MAC_HW_Feature0,This register indicates the presence of the first set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
bitfld.long 0x0 31. "EDMA,Enhanced DMA." "0,1"
newline
bitfld.long 0x0 30. "EDIFFC,Different Descriptor Cache." "0,1"
newline
bitfld.long 0x0 29. "VXN,VxLAN/NVGRE Support." "0,1"
newline
bitfld.long 0x0 28. "Reserved_28,Reserved." "0,1"
newline
bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable." "0,1"
newline
bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source." "0: Reserved,1: Internal,?,?"
newline
bitfld.long 0x0 23.--24. "PHYSEL,RGMII Interface Select" "0,1,2,3"
newline
hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected."
newline
bitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled." "0,1"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled." "0,1"
newline
bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled." "0,1"
newline
bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled." "0,1"
newline
bitfld.long 0x0 11. "AVSEL,AV Feature Enabled." "0,1"
newline
bitfld.long 0x0 10. "RAVSEL,Rx Side Only AV Feature Enable." "0,1"
newline
bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled." "0,1"
newline
bitfld.long 0x0 8. "MMCSEL,RMON Module Enable." "0,1"
newline
bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable." "0,1"
newline
bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Enable." "0,1"
newline
bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface." "0,1"
newline
bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected." "0,1"
newline
bitfld.long 0x0 3. "HDSEL,Half-duplex Support" "0,1"
newline
bitfld.long 0x0 2. "RMIISEL,RMII Support." "0,1"
newline
bitfld.long 0x0 1. "GMIISEL,1000/100/10 Mbps Support." "0,1"
newline
bitfld.long 0x0 0. "RGMIISEL,RGMII Support." "0,1"
line.long 0x4 "MAC_HW_Feature1,This register indicates the presence of second set of the optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
bitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters."
newline
bitfld.long 0x4 24.--26. "HASHTBLSZ,Hash Table Size." "0: No hash table selected,1: 64,2: 128,3: 256,4: 512,5: 1024,6: 2048,7: 4096"
newline
bitfld.long 0x4 21.--23. "NUMTC,Number of Traffic Classes." "0: 1 Traffic Class,1: 2 Traffic Classes,2: 3 Traffic Classes,?,?,?,?,7: 8 Traffic"
newline
bitfld.long 0x4 20. "RSSEN,Internal Register based RSS Feature Enabled" "0,1"
newline
bitfld.long 0x4 19. "DBGMEMA,Debug Memory Interface Enabled." "0,1"
newline
bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable." "0,1"
newline
bitfld.long 0x4 17. "SPHEN,Header-Payload Split Feature Enable." "0,1"
newline
bitfld.long 0x4 16. "DCBEN,DCB Feature Enable." "0,1"
newline
bitfld.long 0x4 14.--15. "ADDR64,Address Width." "0: 32,1: 40,2: 48,3: Reserved"
newline
bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable." "0,1"
newline
bitfld.long 0x4 12. "PTOEN,PTP Offload Enable." "0,1"
newline
bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable." "0,1"
newline
hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size."
newline
bitfld.long 0x4 5. "PFCEN,PFC Enable" "0,1"
newline
hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size."
line.long 0x8 "MAC_HW_Feature2,This register indicates the presence of the third set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
bitfld.long 0x8 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs." "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary inputs,3: 3 auxiliary inputs,4: 4 auxiliary inputs,?,?,7: Reserved"
newline
bitfld.long 0x8 27. "Reserved_27,Reserved." "0,1"
newline
bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs." "0: No PPS output,1: 1 PPS output,2: 2 PPS outputs,3: 3 PPS outputs,4: 4 PPS outputs,?,?,7: Reserved"
newline
bitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels."
newline
bitfld.long 0x8 16.--17. "Reserved_17_16,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels."
newline
bitfld.long 0x8 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues."
newline
bitfld.long 0x8 4.--5. "Reserved_5_4,Reserved." "0,1,2,3"
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hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues."
line.long 0xC "MAC_HW_Feature3,This register indicates the presence of the fourth set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
hexmask.long.byte 0xC 28.--31. 1. "TBS_CH,The number of DMA channels enabled for TBS (starting from the highest Tx Channel  in descending order)"
newline
bitfld.long 0xC 27. "TBSSEL,Time Based Scheduling Enable" "0,1"
newline
bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable" "0,1"
newline
bitfld.long 0xC 25. "SGFSEL,Per-Stream Filtering Select" "0,1"
newline
bitfld.long 0xC 23.--24. "GCLWID,Width of the Time Interval field in the Gate Control List" "0,1,2,3"
newline
bitfld.long 0xC 20.--22. "GCLDEP,Depth of the Gate Control List" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 19. "ESTSEL,Enhancements to Scheduling Traffic Enable" "0,1"
newline
bitfld.long 0xC 16.--18. "TTSFD,Tx Timestamp FIFO Depth" "0: Reserved,1: 1,2: 2,3: 4,4: 8,5: 16,6: Reserved,7: Reserved"
newline
bitfld.long 0xC 14.--15. "ASP,Automotive Safety Package" "0: No Safety features selected,1: All the Automotive Safety features are selected..,2: All the Automotive Safety features are selected..,3: All the Automotive Safety features are selected.."
newline
bitfld.long 0xC 13. "DVLAN,Double VLAN Processing Enabled" "0,1"
newline
bitfld.long 0xC 11.--12. "FRPES,Supported Flexible Receive Parser Instructions" "0,1,2,3"
newline
bitfld.long 0xC 9.--10. "FRPPB,Supported Flexible Receive Parser Parsable Bytes" "0,1,2,3"
newline
bitfld.long 0xC 8. "POUOST,One Step for PTP over UDP/IP Feature Enable" "0,1"
newline
bitfld.long 0xC 5.--7. "FRPPIPE,Supported Parallel Instruction Processor Engines (PIPEs)" "0: 1 PIPE,1: 2 PIPEs,?,?,?,?,?,?"
newline
bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable" "0,1"
newline
bitfld.long 0xC 3. "FRPSEL,Supported Flexible Receive Parser." "0,1"
newline
bitfld.long 0xC 0.--2. "NRVF,Enabled number of Extended VLAN Tag Filters or External VLAN tag lookup size" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,6: Reserved,7: External Receive 12bit VLAN Tag Lookup is selected"
line.long 0x10 "MAC_HW_Feature4,This register indicates the presence of the fifth set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
hexmask.long 0x10 2.--31. 1. "Reserved_31_2,Reserved."
newline
bitfld.long 0x10 0.--1. "PCSEL,Policing Counters" "0,1,2,3"
group.long 0x140++0x7
line.long 0x0 "MAC_Extended_Configuration,The MAC Extended Configuration register establishes the operating mode of the MAC transmitter."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "HD,Duplex Mode" "0,1"
newline
bitfld.long 0x0 23. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode" "0,1"
newline
bitfld.long 0x0 22. "DO,Disable Receive Own" "0,1"
newline
bitfld.long 0x0 21. "DCRS,Disable Carrier Sense During Transmission" "0,1"
newline
bitfld.long 0x0 20. "DR,Disable Retry" "0,1"
newline
bitfld.long 0x0 18.--19. "BL,Back-Off Limit" "0,1,2,3"
newline
bitfld.long 0x0 17. "DC,Deferral Check" "0,1"
newline
rbitfld.long 0x0 16. "Reserved_SBDIOEN,Reserved." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_15_10,Reserved."
newline
bitfld.long 0x0 9. "TPRE,Reserved" "0,1"
newline
rbitfld.long 0x0 8. "Reserved_VPRE,Reserved." "0,1"
newline
bitfld.long 0x0 7. "DDS,DA Duplication Select." "0: DCS field in MAC_Address_High register is..,1: XDCS field in MAC_DChSel_IndReg register.."
newline
hexmask.long.byte 0x0 0.--6. 1. "EIPG,Extended Inter-Packet Gap."
line.long 0x4 "MAC_Ext_Cfg1,This register contains Split mode control field and offset field for Header-Payload Split feature."
hexmask.long.byte 0x4 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x4 24. "SAVE,Split AV Enable" "0,1"
newline
rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1"
newline
hexmask.long.byte 0x4 16.--22. 1. "SAVO,Split AV Offset"
newline
hexmask.long.byte 0x4 10.--15. 1. "Reserved_15_10,Reserved."
newline
bitfld.long 0x4 8.--9. "SPLM,Split Mode" "0,1,2,3"
newline
rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1"
newline
hexmask.long.byte 0x4 0.--6. 1. "SPLOFST,Split Offset"
group.long 0x200++0x13
line.long 0x0 "MDIO_Single_Command_Address,This register contains the addresses of the ports. devices. and registers accessed by the SMA during single read or write transfers."
hexmask.long.byte 0x0 26.--31. 1. "Reserved_31_26,Reserved."
newline
hexmask.long.byte 0x0 21.--25. 1. "DA,Device Address"
newline
hexmask.long.byte 0x0 16.--20. 1. "PA,Port Address"
newline
hexmask.long.word 0x0 0.--15. 1. "RA,Register Address"
line.long 0x4 "MDIO_Single_Command_Control_Data,This register controls single read/write operations. and contains the data bits read on a single-read operation and the data to be written during single-write operations."
bitfld.long 0x4 31. "CRS,Clock Range Select." "0,1"
newline
bitfld.long 0x4 30. "PSE,Preamble Suppression Enable." "0,1"
newline
hexmask.long.byte 0x4 23.--29. 1. "Reserved_29_23,Reserved."
newline
bitfld.long 0x4 22. "SBusy,Busy" "0,1"
newline
bitfld.long 0x4 19.--21. "CR,Application Clock Range" "0: MDC clock: clk_csr_i/4,1: MDC clock: clk_csr_i/6,2: MDC clock: clk_csr_i/8,3: MDC clock: clk_csr_i/10,4: MDC clock: clk_csr_i/12,5: MDC clock: clk_csr_i/14,6: MDC clock: clk_csr_i/16,7: MDC clock: clk_csr_i/18"
newline
bitfld.long 0x4 18. "SAADR,Skip Address Frame" "0,1"
newline
bitfld.long 0x4 16.--17. "CMD,Control Command" "0: Reserved,1: SINGLE_WRITE,2: POST INCREMENT READ OPERATION,3: SINGLE_READ"
newline
hexmask.long.word 0x4 0.--15. 1. "SDATA,Single Write Data"
line.long 0x8 "MDIO_Continuous_Write_Address,You can program this register to start continuous write operation."
hexmask.long.word 0x8 23.--31. 1. "Reserved_31_23,Reserved."
newline
bitfld.long 0x8 22. "CBUSY,Continuous Write Busy" "0,1"
newline
bitfld.long 0x8 21. "CPRT,Continuous Port or Device Address Select" "0,1"
newline
hexmask.long.byte 0x8 16.--20. 1. "CADDR,Continuous Port or Device Address"
newline
hexmask.long.word 0x8 0.--15. 1. "CREGADDR,Continuous Register Address"
line.long 0xC "MDIO_Continuous_Write_Data,This register contains the data to be written during continuous write operation. Do not change the register's contents until the Continuous Write Busy bit (CBUSY) is cleared."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "CDATA,Continuous Write Data"
line.long 0x10 "MDIO_Continuous_Scan_Port_Enable,This register controls the PHY ports and corresponding devices (enabled by the corresponding Device In Use register) to be accessed during the SMA's continuous scan operation. If you change any bit in this register during.."
bitfld.long 0x10 31. "PORT31SCE,Port 31 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 30. "PORT30SCE,Port 30 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 29. "PORT29SCE,Port 29 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 28. "PORT28SCE,Port 28 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 27. "PORT27SCE,Port 27 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 26. "PORT26SCE,Port 26 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 25. "PORT25SCE,Port 25 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 24. "PORT24SCE,Port 24 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 23. "PORT23SCE,Port 23 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 22. "PORT22SCE,Port 22 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 21. "PORT21SCE,Port 21 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 20. "PORT20SCE,Port 20 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 19. "PORT19SCE,Port 19 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 18. "PORT18SCE,Port 18 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 17. "PORT17SCE,Port 17 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 16. "PORT16SCE,Port 16 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 15. "PORT15SCE,Port 15 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 14. "PORT14SCE,Port 14 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 13. "PORT13SCE,Port 13 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 12. "PORT12SCE,Port 12 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 11. "PORT11SCE,Port 11 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 10. "PORT10SCE,Port 10 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 9. "PORT9SCE,Port 9 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 8. "PORT8SCE,Port 8 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 7. "PORT7SCE,Port 7 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 6. "PORT6SCE,Port 6 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 5. "PORT5SCE,Port 5 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 4. "PORT4SCE,Port 4 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 3. "PORT3SCE,Port 3 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 2. "PORT2SCE,Port 2 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 1. "PORT1SCE,Port 1 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 0. "PORT0SCE,Port 0 Continuous Scan Enable." "0,1"
rgroup.long 0x214++0x3
line.long 0x0 "MDIO_Interrupt_Status,This register gives the source of the interrupt raised by the SMA module on the sbd_intr_o output line. The status bits are cleared when the software reads the corresponding bytes."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
newline
bitfld.long 0x0 13. "CWCOMPINT,Continuous Write Completion Interrupt." "0,1"
newline
bitfld.long 0x0 12. "SNGLCOMPINT,Single Command Completion Interrupt." "0,1"
newline
bitfld.long 0x0 11. "PORTNx4P3ALINT,Device Present Status Change Interrupt (Port Nx4 Plus3)." "0,1"
newline
bitfld.long 0x0 10. "PORTNx4P2ALINT,Device Present Status Change Interrupt (Port Nx4 Plus2)." "0,1"
newline
bitfld.long 0x0 9. "PORTNx4P1ALINT,Device Present Status Change Interrupt (Port Nx4 Plus1)." "0,1"
newline
bitfld.long 0x0 8. "PORTNx4P0ALINT,Device Present Status Change Interrupt (Port Nx4 Plus0)." "0,1"
newline
bitfld.long 0x0 7. "PORTNx4P3LSINT,Link Status Change Interrupt (Port Nx4 Plus3)." "0,1"
newline
bitfld.long 0x0 6. "PORTNx4P2LSINT,Link Status Change Interrupt (Port Nx4 Plus2)." "0,1"
newline
bitfld.long 0x0 5. "PORTNx4P1LSINT,Link Status Change Interrupt (Port Nx4 Plus1)." "0,1"
newline
bitfld.long 0x0 4. "PORTNx4P0LSINT,Link Status Change Interrupt (Port Nx4 Plus0)." "0,1"
newline
bitfld.long 0x0 3. "PORTNx4P3CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus3)." "0,1"
newline
bitfld.long 0x0 2. "PORTNx4P2CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus2)." "0,1"
newline
bitfld.long 0x0 1. "PORTNx4P1CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus1)." "0,1"
newline
bitfld.long 0x0 0. "PORTNx4P0CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus0)." "0,1"
group.long 0x218++0x3
line.long 0x0 "MDIO_Interrupt_Enable,This register controls the enabling of interrupt sources in the MDIO Interrupt Status register."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
newline
bitfld.long 0x0 13. "CWCOMPIE,Continuous Write Completion Interrupt Enable." "0,1"
newline
bitfld.long 0x0 12. "SNGLCOMPIE,Single Command Completion Interrupt Enable." "0,1"
newline
bitfld.long 0x0 11. "PTRNx4P3ALIE,Device Present Status Change Interrupt (Port Nx4 Plus3) Enable." "0,1"
newline
bitfld.long 0x0 10. "PTRNx4P2ALIE,Device Present Status Change Interrupt (Port Nx4 Plus2) Enable." "0,1"
newline
bitfld.long 0x0 9. "PTRNx4P1ALIE,Device Present Status Change Interrupt (Port Nx4 Plus1) Enable." "0,1"
newline
bitfld.long 0x0 8. "PTRNx4P0ALIE,Device Present Status Change Interrupt (Port Nx4 Plus0) Enable." "0,1"
newline
bitfld.long 0x0 7. "PTRNx4P3LSIE,Link Status Change Interrupt (Port Nx4 Plus3) Enable." "0,1"
newline
bitfld.long 0x0 6. "PTRNx4P2LSIE,Link Status Change Interrupt (Port Nx4 Plus2) Enable." "0,1"
newline
bitfld.long 0x0 5. "PTRNx4P1LSIE,Link Status Change Interrupt (Port Nx4 Plus1) Enable." "0,1"
newline
bitfld.long 0x0 4. "PTRNx4P0LSIE,Link Status Change Interrupt (Port Nx4 Plus0) Enable." "0,1"
newline
bitfld.long 0x0 3. "PTRNx4P3CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus3) Enable." "0,1"
newline
bitfld.long 0x0 2. "PTRNx4P2CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus2) Enable." "0,1"
newline
bitfld.long 0x0 1. "PTRNx4P1CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus1) Enable." "0,1"
newline
bitfld.long 0x0 0. "PTRNx4P0CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus0) Enable." "0,1"
rgroup.long 0x21C++0x3
line.long 0x0 "MDIO_Port_Connect_Disconnect_Status,This register gives the hot plug-in status for Ports 0-31. This register is updated at the end of any read operation to any register of the corresponding PHY port. It is updated during single-read transfers or during.."
bitfld.long 0x0 31. "PORT31CON,Port 31 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 30. "PORT30CON,Port 30 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 29. "PORT29CON,Port 29 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 28. "PORT28CON,Port 28 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 27. "PORT27CON,Port 27 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 26. "PORT26CON,Port 26 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 25. "PORT25CON,Port 25 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 24. "PORT24CON,Port 24 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 23. "PORT23CON,Port 23 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 22. "PORT22CON,Port 22 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 21. "PORT21CON,Port 21 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 20. "PORT20CON,Port 20 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 19. "PORT19CON,Port 19 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 18. "PORT18CON,Port 18 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 17. "PORT17CON,Port 17 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 16. "PORT16CON,Port 16 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 15. "PORT15CON,Port 15 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 14. "PORT14CON,Port 14 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 13. "PORT13CON,Port 13 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 12. "PORT12CON,Port 12 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 11. "PORT11CON,Port 11 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 10. "PORT10CON,Port 10 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 9. "PORT9CON,Port 9 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 8. "PORT8CON,Port 8 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 7. "PORT7CON,Port 7 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 6. "PORT6CON,Port 6 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 5. "PORT5CON,Port 5 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 4. "PORT4CON,Port 4 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 3. "PORT3CON,Port 3 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 2. "PORT2CON,Port 2 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 1. "PORT1CON,Port 1 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 0. "PORT0CON,Port 0 Connect/Disconnect." "0,1"
group.long 0x220++0x7
line.long 0x0 "MDIO_Clause_22_Port,This register configures the SMA to access the PHY ports using either the Clause 22 or Clause 45 packet format. All SMA operations (single or continuous) depend on setting these bits correctly."
bitfld.long 0x0 31. "PTR31CL22,Port31CL22 Enable. Indicates that Port 31 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 30. "PTR30CL22,Port30CL22 Enable. Indicates that Port 30 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 29. "PTR29CL22,Port29CL22 Enable. Indicates that Port 29 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 28. "PTR28CL22,Port28CL22 Enable. Indicates that Port 28 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 27. "PTR27CL22,Port27CL22 Enable. Indicates that Port 27 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 26. "PTR26CL22,Port26CL22 Enable. Indicates that Port 26 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 25. "PTR25CL22,Port25CL22 Enable. Indicates that Port 25 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 24. "PTR24CL22,Port24CL22 Enable. Indicates that Port 24 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 23. "PTR23CL22,Port23CL22 Enable. Indicates that Port 23 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 22. "PTR22CL22,Port22CL22 Enable. Indicates that Port 22 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 21. "PTR21CL22,Port21CL22 Enable. Indicates that Port 21 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 20. "PTR20CL22,Port20CL22 Enable. Indicates that Port 20 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 19. "PTR19CL22,Port19CL22 Enable. Indicates that Port 19 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 18. "PTR18CL22,Port18CL22 Enable. Indicates that Port 18 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 17. "PTR17CL22,Port17CL22 Enable. Indicates that Port 17 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 16. "PTR16CL22,Port16CL22 Enable. Indicates that Port 16 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 15. "PTR15CL22,Port15CL22 Enable. Indicates that Port 15 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 14. "PTR14CL22,Port14CL22 Enable. Indicates that Port 14 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 13. "PTR13CL22,Port13CL22 Enable. Indicates that Port 13 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 12. "PTR12CL22,Port12CL22 Enable. Indicates that Port 12 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 11. "PTR11CL22,Port11CL22 Enable. Indicates that Port 11 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 10. "PTR10CL22,Port10CL22 Enable. Indicates that Port 10 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 9. "PTR9CL22,Port9CL22 Enable. Indicates that Port 9 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 8. "PTR8CL22,Port8CL22 Enable. Indicates that Port 8 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 7. "PTR7CL22,Port7CL22 Enable. Indicates that Port 7 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 6. "PTR6CL22,Port6CL22 Enable. Indicates that Port 6 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 5. "PTR5CL22,Port5CL22 Enable. Indicates that Port 5 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 4. "PTR4CL22,Port4CL22 Enable. Indicates that Port 4 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 3. "PTR3CL22,Port3CL22 Enable. Indicates that Port 3 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 2. "PTR2CL22,Port2CL22 Enable. Indicates that Port 2 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 1. "PTR1CL22,Port1CL22 Enable. Indicates that Port 1 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 0. "PTR0CL22,Port0CL22 Enable. Indicates that Port 0 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
line.long 0x4 "MDIO_Port_Nx4_Indirect_Control,This register contain fields that control the Port range select for accessing register sets."
hexmask.long 0x4 3.--31. 1. "Reserved_31_3,Reserved."
newline
bitfld.long 0x4 0.--2. "PRS,Port Range Select." "0: Selects the Port address range of 0 to 3,1: Selects the Port Address range of 4 to 7,2: Selects the Port Address range of 8 to 11,3: Selects the Port Address range of 12 to 15,4: Selects the Port Address range of 16 to 19,5: Selects the Port Address range of 20 to 23,6: Selects the Port Address range of 24 to 27,7: Selects the Port Address range of 28 to 31"
group.long 0x230++0x3
line.long 0x0 "MDIO_PortNx4P0_Device_In_Use,This register gives the status of each device on Port Nx4 Plus0 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P0VSD2,VSD2 Device is in Use" "0,1"
newline
bitfld.long 0x0 30. "Nx4P0VSD1,VSD1 Device is in Use" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P0TC,TC Device is in Use" "0,1"
newline
bitfld.long 0x0 5. "Nx4P0DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P0PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P0PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P0WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P0PMDPMA,PMA Device is in Use" "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x234++0x7
line.long 0x0 "MDIO_PortNx4P0_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus0 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported..."
bitfld.long 0x0 31. "Nx4P0VSD2LS,Link Status of VSD2 Device" "0,1"
newline
bitfld.long 0x0 30. "Nx4P0VSD1LS,Link Status of VCD1 Device" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P0TCLS,Link Status of TC Device" "0,1"
newline
bitfld.long 0x0 5. "Nx4P0DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P0PHYXSLS,Link Status of PHYXS Device" "0,1"
newline
bitfld.long 0x0 3. "Nx4P0PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P0WISLS,Link Status of WIS Device" "0,1"
newline
bitfld.long 0x0 1. "Nx4P0PMDPMALS,Link Status of PMA Device" "0,1"
newline
bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P0_Alive_Status,This register gives the device status in PHY Port Nx4Plus0 ((Here N is as per PRS field of 'MDIO Port Nx4 Indirect Control' register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified in.."
bitfld.long 0x4 31. "Nx4P0VSD2LS,Alive Status of VSD2 Device" "0,1"
newline
bitfld.long 0x4 30. "Nx4P0VSD1LS,Alive Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x4 6. "Nx4P0TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P0DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P0PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P0PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P0WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P0PMDPMALS,Alive Status of PMA Device" "0,1"
newline
bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x240++0x3
line.long 0x0 "MDIO_PortNx4P1_Device_In_Use,This register gives the status of each device on Port Nx4 Plus1 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P1VSD2,VSD2 Device is in Use" "0,1"
newline
bitfld.long 0x0 30. "Nx4P1VSD1,VSD1 Device is in Use" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P1TC,TC Device is in Use" "0,1"
newline
bitfld.long 0x0 5. "Nx4P1DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P1PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P1PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P1WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P1PMDPMA,PMA Device is in Use" "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x244++0x7
line.long 0x0 "MDIO_PortNx4P1_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus1 ((Here N is as per PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as.."
bitfld.long 0x0 31. "Nx4P1VSD2LS,Link Status of VSD2 Device" "0,1"
newline
bitfld.long 0x0 30. "Nx4P1VSD1LS,Link Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P1TCLS,Link Status of TC Device" "0,1"
newline
bitfld.long 0x0 5. "Nx4P1DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P1PHYXSLS,Link Status of PHYXS Device" "0,1"
newline
bitfld.long 0x0 3. "Nx4P1PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P1WISLS,Link Status of WIS Device" "0,1"
newline
bitfld.long 0x0 1. "Nx4P1PMDPMALS,Link Status of PMA Device" "0,1"
newline
bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P1_Alive_Status,This register gives the device status in PHY Port Nx4Plus1 ((Here N is as per PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified in.."
bitfld.long 0x4 31. "Nx4P1VSD2LS,Alive Status of VSD2 Device" "0,1"
newline
bitfld.long 0x4 30. "Nx4P1VSD1LS,Alive Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x4 6. "Nx4P1TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P1DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P1PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P1PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P1WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P1PMDPMALS,Alive Status of PMA Device" "0,1"
newline
bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x250++0x3
line.long 0x0 "MDIO_PortNx4P2_Device_In_Use,This register gives the status of each device on Port Nx4 Plus2 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P2VSD2,VSD2 Device is in Use" "0,1"
newline
bitfld.long 0x0 30. "Nx4P2VSD1,VSD1 Device is in Use" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P2TC,TC Device is in Use" "0,1"
newline
bitfld.long 0x0 5. "Nx4P2DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P2PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P2PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P2WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P2PMDPMA,PMA Device is in Use" "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x254++0x7
line.long 0x0 "MDIO_PortNx4P2_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus2 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported..."
bitfld.long 0x0 31. "Nx4P2VSD2LS,Link Status of VSD2 Device" "0,1"
newline
bitfld.long 0x0 30. "Nx4P2VSD1LS,Link Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P2TCLS,Link Status of TC Device" "0,1"
newline
bitfld.long 0x0 5. "Nx4P2DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P2PHYXSLS,Link Status of PHYXS Device" "0,1"
newline
bitfld.long 0x0 3. "Nx4P2PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P2WISLS,Link Status of WIS Device" "0,1"
newline
bitfld.long 0x0 1. "Nx4P2PMDPMALS,Link Status of PMA Device" "0,1"
newline
bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P2_Alive_Status,This register gives the device status in PHY Port Nx4Plus2 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified.."
bitfld.long 0x4 31. "Nx4P2VSD2LS,Alive Status of VSD2 Device" "0,1"
newline
bitfld.long 0x4 30. "Nx4P2VSD1LS,Alive Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x4 6. "Nx4P2TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P2DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P2PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P2PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P2WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P2PMDPMALS,Alive Status of PMA Device" "0,1"
newline
bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x260++0x3
line.long 0x0 "MDIO_PortNx4P3_Device_In_Use,This register gives the status of each device on Port Nx4 Plus3 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P3VSD2,VSD2 Device is in Use" "0,1"
newline
bitfld.long 0x0 30. "Nx4P3VSD1,VSD1 Device is in Use" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P3TC,TC Device is in Use" "0,1"
newline
bitfld.long 0x0 5. "Nx4P3DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P3PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P3PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P3WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P3PMDPMA,PMA Device is in Use" "0,1"
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rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x264++0x7
line.long 0x0 "MDIO_PortNx4P3_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus3 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported..."
bitfld.long 0x0 31. "Nx4P3VSD2LS,Link Status of VSD2 Device" "0,1"
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bitfld.long 0x0 30. "Nx4P3VSD1LS,Link Status of VSD1 Device" "0,1"
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hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
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bitfld.long 0x0 6. "Nx4P3TCLS,Link Status of TC Device" "0,1"
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bitfld.long 0x0 5. "Nx4P3DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P3PHYXSLS,Link Status of PHYXS Device" "0,1"
newline
bitfld.long 0x0 3. "Nx4P3PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P3WISLS,Link Status of WIS Device" "0,1"
newline
bitfld.long 0x0 1. "Nx4P3PMDPMALS,Link Status of PMA Device" "0,1"
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bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P3_Alive_Status,This register gives the device status in PHY Port Nx4Plus3 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified.."
bitfld.long 0x4 31. "Nx4P3VSD2LS,Alive Status of VSD2 Device" "0,1"
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bitfld.long 0x4 30. "Nx4P3VSD1LS,Alive Status of VSD1 Device" "0,1"
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hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
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bitfld.long 0x4 6. "Nx4P3TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P3DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P3PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P3PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P3WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P3PMDPMALS,Alive Status of PMA Device" "0,1"
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bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x278++0xB
line.long 0x0 "MAC_GPIO_Control,The GPIO Control register controls the GPIO."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x0 16.--23. 1. "GPIT,GPI Type."
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hexmask.long.word 0x0 4.--15. 1. "Reserved_15_4,Reserved."
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hexmask.long.byte 0x0 0.--3. 1. "GPIE,GPI Interrupt Enable."
line.long 0x4 "MAC_GPIO_Status,The General Purpose IO register provides the control to drive the following: up to 16 bits of output ports (GPO) and status of up to 16 input ports (GPIS)."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 16.--23. 1. "GPO,General Purpose Output."
newline
hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_y,Reserved."
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hexmask.long.byte 0x4 0.--7. 1. "GPIS,General Purpose Input Status."
line.long 0x8 "MAC_FPE_CTRL_STS,This register controls the operation of Frame Preemption."
hexmask.long.word 0x8 20.--31. 1. "Reserved_31_20,Reserved."
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rbitfld.long 0x8 19. "TRSP,Transmitted Respond Frame" "0,1"
newline
rbitfld.long 0x8 18. "TVER,Transmitted Verify Frame" "0,1"
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rbitfld.long 0x8 17. "RRSP,Received Respond Frame" "0,1"
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rbitfld.long 0x8 16. "RVER,Received Verify Frame" "0,1"
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hexmask.long.word 0x8 4.--15. 1. "Reserved_15_4,Reserved."
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bitfld.long 0x8 3. "ARV,Autogenerate Respond mPacket on receiving Verify mPacket" "0,1"
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bitfld.long 0x8 2. "SRSP,Send Respond mPacket" "0,1"
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bitfld.long 0x8 1. "SVER,Send Verify mPacket" "0,1"
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bitfld.long 0x8 0. "EFPE,Enable Tx Frame Preemption" "0,1"
group.long 0x290++0x3
line.long 0x0 "MAC_CSR_SW_Ctrl,This register contains software programmable controls for changing the CSR access response and status bits clearing."
hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved."
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bitfld.long 0x0 8. "SEEN,Slave Error Response Enable" "0,1"
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hexmask.long.byte 0x0 1.--7. 1. "Reserved_7_1,Reserved."
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bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1"
group.long 0x300++0xFF
line.long 0x0 "MAC_Address0_High,The MAC_Address0_High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address0_Low register."
rbitfld.long 0x0 31. "AE,Address Enable." "0,1"
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hexmask.long.word 0x0 19.--30. 1. "Reserved_30_y,Reserved."
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bitfld.long 0x0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32]."
line.long 0x4 "MAC_Address0_Low,The MAC_Address0_Low register holds the lower 32 bits of the 0th 6-byte MAC address of the station."
hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address0 [31:0]."
line.long 0x8 "MAC_Address1_High,The MAC_Address1_High register holds the upper 16 bits of the 1th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address1_Low register. For.."
bitfld.long 0x8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 1th MAC.."
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bitfld.long 0x8 30. "SA,Source Address." "0: The MAC Address1[47:0] is used to compare with..,1: The MAC Address1[47:0] is used to compare with.."
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hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x8 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32]."
line.long 0xC "MAC_Address1_Low,The MAC_Address1_Low register holds the lower 32 bits of the 1th 6-byte MAC address of the station."
hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address1 [31:0]."
line.long 0x10 "MAC_Address2_High,The MAC_Address2_High register holds the upper 16 bits of the 2th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address2_Low register. For.."
bitfld.long 0x10 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 2th MAC.."
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bitfld.long 0x10 30. "SA,Source Address." "0: The MAC Address2[47:0] is used to compare with..,1: The MAC Address2[47:0] is used to compare with.."
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hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x10 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x10 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address2 [47:32]."
line.long 0x14 "MAC_Address2_Low,The MAC_Address2_Low register holds the lower 32 bits of the 2th 6-byte MAC address of the station."
hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address2 [31:0]."
line.long 0x18 "MAC_Address3_High,The MAC_Address3_High register holds the upper 16 bits of the 3th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address3_Low register. For.."
bitfld.long 0x18 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 3th MAC.."
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bitfld.long 0x18 30. "SA,Source Address." "0: The MAC Address3[47:0] is used to compare with..,1: The MAC Address3[47:0] is used to compare with.."
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hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x18 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x18 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address3 [47:32]."
line.long 0x1C "MAC_Address3_Low,The MAC_Address3_Low register holds the lower 32 bits of the 3th 6-byte MAC address of the station."
hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address3 [31:0]."
line.long 0x20 "MAC_Address4_High,The MAC_Address4_High register holds the upper 16 bits of the 4th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address4_Low register. For.."
bitfld.long 0x20 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 4th MAC.."
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bitfld.long 0x20 30. "SA,Source Address." "0: The MAC Address4[47:0] is used to compare with..,1: The MAC Address4[47:0] is used to compare with.."
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hexmask.long.byte 0x20 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x20 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x20 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x20 0.--15. 1. "ADDRHI,MAC Address4 [47:32]."
line.long 0x24 "MAC_Address4_Low,The MAC_Address4_Low register holds the lower 32 bits of the 4th 6-byte MAC address of the station."
hexmask.long 0x24 0.--31. 1. "ADDRLO,MAC Address4 [31:0]."
line.long 0x28 "MAC_Address5_High,The MAC_Address5_High register holds the upper 16 bits of the 5th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address5_Low register. For.."
bitfld.long 0x28 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 5th MAC.."
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bitfld.long 0x28 30. "SA,Source Address." "0: The MAC Address5[47:0] is used to compare with..,1: The MAC Address5[47:0] is used to compare with.."
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hexmask.long.byte 0x28 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x28 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x28 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x28 0.--15. 1. "ADDRHI,MAC Address5 [47:32]."
line.long 0x2C "MAC_Address5_Low,The MAC_Address5_Low register holds the lower 32 bits of the 5th 6-byte MAC address of the station."
hexmask.long 0x2C 0.--31. 1. "ADDRLO,MAC Address5 [31:0]."
line.long 0x30 "MAC_Address6_High,The MAC_Address6_High register holds the upper 16 bits of the 6th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address6_Low register. For.."
bitfld.long 0x30 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 6th MAC.."
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bitfld.long 0x30 30. "SA,Source Address." "0: The MAC Address6[47:0] is used to compare with..,1: The MAC Address6[47:0] is used to compare with.."
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hexmask.long.byte 0x30 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x30 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x30 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x30 0.--15. 1. "ADDRHI,MAC Address6 [47:32]."
line.long 0x34 "MAC_Address6_Low,The MAC_Address6_Low register holds the lower 32 bits of the 6th 6-byte MAC address of the station."
hexmask.long 0x34 0.--31. 1. "ADDRLO,MAC Address6 [31:0]."
line.long 0x38 "MAC_Address7_High,The MAC_Address7_High register holds the upper 16 bits of the 7th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address7_Low register. For.."
bitfld.long 0x38 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 7th MAC.."
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bitfld.long 0x38 30. "SA,Source Address." "0: The MAC Address7[47:0] is used to compare with..,1: The MAC Address7[47:0] is used to compare with.."
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hexmask.long.byte 0x38 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x38 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x38 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x38 0.--15. 1. "ADDRHI,MAC Address7 [47:32]."
line.long 0x3C "MAC_Address7_Low,The MAC_Address7_Low register holds the lower 32 bits of the 7th 6-byte MAC address of the station."
hexmask.long 0x3C 0.--31. 1. "ADDRLO,MAC Address7 [31:0]."
line.long 0x40 "MAC_Address8_High,The MAC_Address8_High register holds the upper 16 bits of the 8th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address8_Low register. For.."
bitfld.long 0x40 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 8th MAC.."
newline
bitfld.long 0x40 30. "SA,Source Address." "0: The MAC Address8[47:0] is used to compare with..,1: The MAC Address8[47:0] is used to compare with.."
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hexmask.long.byte 0x40 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x40 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x40 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x40 0.--15. 1. "ADDRHI,MAC Address8 [47:32]."
line.long 0x44 "MAC_Address8_Low,The MAC_Address8_Low register holds the lower 32 bits of the 8th 6-byte MAC address of the station."
hexmask.long 0x44 0.--31. 1. "ADDRLO,MAC Address8 [31:0]."
line.long 0x48 "MAC_Address9_High,The MAC_Address9_High register holds the upper 16 bits of the 9th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address9_Low register. For.."
bitfld.long 0x48 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 9th MAC.."
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bitfld.long 0x48 30. "SA,Source Address." "0: The MAC Address9[47:0] is used to compare with..,1: The MAC Address9[47:0] is used to compare with.."
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hexmask.long.byte 0x48 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x48 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x48 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x48 0.--15. 1. "ADDRHI,MAC Address9 [47:32]."
line.long 0x4C "MAC_Address9_Low,The MAC_Address9_Low register holds the lower 32 bits of the 9th 6-byte MAC address of the station."
hexmask.long 0x4C 0.--31. 1. "ADDRLO,MAC Address9 [31:0]."
line.long 0x50 "MAC_Address10_High,The MAC_Address10_High register holds the upper 16 bits of the 10th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address10_Low register."
bitfld.long 0x50 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 10th MAC.."
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bitfld.long 0x50 30. "SA,Source Address." "0: The MAC Address10[47:0] is used to compare with..,1: The MAC Address10[47:0] is used to compare with.."
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hexmask.long.byte 0x50 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x50 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x50 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x50 0.--15. 1. "ADDRHI,MAC Address10 [47:32]."
line.long 0x54 "MAC_Address10_Low,The MAC_Address10_Low register holds the lower 32 bits of the 10th 6-byte MAC address of the station."
hexmask.long 0x54 0.--31. 1. "ADDRLO,MAC Address10 [31:0]."
line.long 0x58 "MAC_Address11_High,The MAC_Address11_High register holds the upper 16 bits of the 11th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address11_Low register."
bitfld.long 0x58 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 11th MAC.."
newline
bitfld.long 0x58 30. "SA,Source Address." "0: The MAC Address11[47:0] is used to compare with..,1: The MAC Address11[47:0] is used to compare with.."
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hexmask.long.byte 0x58 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x58 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x58 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x58 0.--15. 1. "ADDRHI,MAC Address11 [47:32]."
line.long 0x5C "MAC_Address11_Low,The MAC_Address11_Low register holds the lower 32 bits of the 11th 6-byte MAC address of the station."
hexmask.long 0x5C 0.--31. 1. "ADDRLO,MAC Address11 [31:0]."
line.long 0x60 "MAC_Address12_High,The MAC_Address12_High register holds the upper 16 bits of the 12th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address12_Low register."
bitfld.long 0x60 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 12th MAC.."
newline
bitfld.long 0x60 30. "SA,Source Address." "0: The MAC Address12[47:0] is used to compare with..,1: The MAC Address12[47:0] is used to compare with.."
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hexmask.long.byte 0x60 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x60 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x60 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x60 0.--15. 1. "ADDRHI,MAC Address12 [47:32]."
line.long 0x64 "MAC_Address12_Low,The MAC_Address12_Low register holds the lower 32 bits of the 12th 6-byte MAC address of the station."
hexmask.long 0x64 0.--31. 1. "ADDRLO,MAC Address12 [31:0]."
line.long 0x68 "MAC_Address13_High,The MAC_Address13_High register holds the upper 16 bits of the 13th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address13_Low register."
bitfld.long 0x68 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 13th MAC.."
newline
bitfld.long 0x68 30. "SA,Source Address." "0: The MAC Address13[47:0] is used to compare with..,1: The MAC Address13[47:0] is used to compare with.."
newline
hexmask.long.byte 0x68 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x68 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x68 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x68 0.--15. 1. "ADDRHI,MAC Address13 [47:32]."
line.long 0x6C "MAC_Address13_Low,The MAC_Address13_Low register holds the lower 32 bits of the 13th 6-byte MAC address of the station."
hexmask.long 0x6C 0.--31. 1. "ADDRLO,MAC Address13 [31:0]."
line.long 0x70 "MAC_Address14_High,The MAC_Address14_High register holds the upper 16 bits of the 14th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address14_Low register."
bitfld.long 0x70 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 14th MAC.."
newline
bitfld.long 0x70 30. "SA,Source Address." "0: The MAC Address14[47:0] is used to compare with..,1: The MAC Address14[47:0] is used to compare with.."
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hexmask.long.byte 0x70 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x70 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x70 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x70 0.--15. 1. "ADDRHI,MAC Address14 [47:32]."
line.long 0x74 "MAC_Address14_Low,The MAC_Address14_Low register holds the lower 32 bits of the 14th 6-byte MAC address of the station."
hexmask.long 0x74 0.--31. 1. "ADDRLO,MAC Address14 [31:0]."
line.long 0x78 "MAC_Address15_High,The MAC_Address15_High register holds the upper 16 bits of the 15th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address15_Low register."
bitfld.long 0x78 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 15th MAC.."
newline
bitfld.long 0x78 30. "SA,Source Address." "0: The MAC Address15[47:0] is used to compare with..,1: The MAC Address15[47:0] is used to compare with.."
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hexmask.long.byte 0x78 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x78 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x78 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x78 0.--15. 1. "ADDRHI,MAC Address15 [47:32]."
line.long 0x7C "MAC_Address15_Low,The MAC_Address15_Low register holds the lower 32 bits of the 15th 6-byte MAC address of the station."
hexmask.long 0x7C 0.--31. 1. "ADDRLO,MAC Address15 [31:0]."
line.long 0x80 "MAC_Address16_High,The MAC_Address16_High register holds the upper 16 bits of the 16th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address16_Low register."
bitfld.long 0x80 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 16th MAC.."
newline
bitfld.long 0x80 30. "SA,Source Address." "0: The MAC Address16[47:0] is used to compare with..,1: The MAC Address16[47:0] is used to compare with.."
newline
hexmask.long.byte 0x80 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x80 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x80 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x80 0.--15. 1. "ADDRHI,MAC Address16 [47:32]."
line.long 0x84 "MAC_Address16_Low,The MAC_Address16_Low register holds the lower 32 bits of the 16th 6-byte MAC address of the station."
hexmask.long 0x84 0.--31. 1. "ADDRLO,MAC Address16 [31:0]."
line.long 0x88 "MAC_Address17_High,The MAC_Address17_High register holds the upper 16 bits of the 17th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address17_Low register."
bitfld.long 0x88 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 17th MAC.."
newline
bitfld.long 0x88 30. "SA,Source Address." "0: The MAC Address17[47:0] is used to compare with..,1: The MAC Address17[47:0] is used to compare with.."
newline
hexmask.long.byte 0x88 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x88 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x88 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x88 0.--15. 1. "ADDRHI,MAC Address17 [47:32]."
line.long 0x8C "MAC_Address17_Low,The MAC_Address17_Low register holds the lower 32 bits of the 17th 6-byte MAC address of the station."
hexmask.long 0x8C 0.--31. 1. "ADDRLO,MAC Address17 [31:0]."
line.long 0x90 "MAC_Address18_High,The MAC_Address18_High register holds the upper 16 bits of the 18th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address18_Low register."
bitfld.long 0x90 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 18th MAC.."
newline
bitfld.long 0x90 30. "SA,Source Address." "0: The MAC Address18[47:0] is used to compare with..,1: The MAC Address18[47:0] is used to compare with.."
newline
hexmask.long.byte 0x90 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x90 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x90 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x90 0.--15. 1. "ADDRHI,MAC Address18 [47:32]."
line.long 0x94 "MAC_Address18_Low,The MAC_Address18_Low register holds the lower 32 bits of the 18th 6-byte MAC address of the station."
hexmask.long 0x94 0.--31. 1. "ADDRLO,MAC Address18 [31:0]."
line.long 0x98 "MAC_Address19_High,The MAC_Address19_High register holds the upper 16 bits of the 19th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address19_Low register."
bitfld.long 0x98 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 19th MAC.."
newline
bitfld.long 0x98 30. "SA,Source Address." "0: The MAC Address19[47:0] is used to compare with..,1: The MAC Address19[47:0] is used to compare with.."
newline
hexmask.long.byte 0x98 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x98 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x98 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x98 0.--15. 1. "ADDRHI,MAC Address19 [47:32]."
line.long 0x9C "MAC_Address19_Low,The MAC_Address19_Low register holds the lower 32 bits of the 19th 6-byte MAC address of the station."
hexmask.long 0x9C 0.--31. 1. "ADDRLO,MAC Address19 [31:0]."
line.long 0xA0 "MAC_Address20_High,The MAC_Address20_High register holds the upper 16 bits of the 20th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address20_Low register."
bitfld.long 0xA0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 20th MAC.."
newline
bitfld.long 0xA0 30. "SA,Source Address." "0: The MAC Address20[47:0] is used to compare with..,1: The MAC Address20[47:0] is used to compare with.."
newline
hexmask.long.byte 0xA0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xA0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xA0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xA0 0.--15. 1. "ADDRHI,MAC Address20 [47:32]."
line.long 0xA4 "MAC_Address20_Low,The MAC_Address20_Low register holds the lower 32 bits of the 20th 6-byte MAC address of the station."
hexmask.long 0xA4 0.--31. 1. "ADDRLO,MAC Address20 [31:0]."
line.long 0xA8 "MAC_Address21_High,The MAC_Address21_High register holds the upper 16 bits of the 21th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address21_Low register."
bitfld.long 0xA8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 21th MAC.."
newline
bitfld.long 0xA8 30. "SA,Source Address." "0: The MAC Address21[47:0] is used to compare with..,1: The MAC Address21[47:0] is used to compare with.."
newline
hexmask.long.byte 0xA8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xA8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xA8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xA8 0.--15. 1. "ADDRHI,MAC Address21 [47:32]."
line.long 0xAC "MAC_Address21_Low,The MAC_Address21_Low register holds the lower 32 bits of the 21th 6-byte MAC address of the station."
hexmask.long 0xAC 0.--31. 1. "ADDRLO,MAC Address21 [31:0]."
line.long 0xB0 "MAC_Address22_High,The MAC_Address22_High register holds the upper 16 bits of the 22th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address22_Low register."
bitfld.long 0xB0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 22th MAC.."
newline
bitfld.long 0xB0 30. "SA,Source Address." "0: The MAC Address22[47:0] is used to compare with..,1: The MAC Address22[47:0] is used to compare with.."
newline
hexmask.long.byte 0xB0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xB0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xB0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xB0 0.--15. 1. "ADDRHI,MAC Address22 [47:32]."
line.long 0xB4 "MAC_Address22_Low,The MAC_Address22_Low register holds the lower 32 bits of the 22th 6-byte MAC address of the station."
hexmask.long 0xB4 0.--31. 1. "ADDRLO,MAC Address22 [31:0]."
line.long 0xB8 "MAC_Address23_High,The MAC_Address23_High register holds the upper 16 bits of the 23th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address23_Low register."
bitfld.long 0xB8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 23th MAC.."
newline
bitfld.long 0xB8 30. "SA,Source Address." "0: The MAC Address23[47:0] is used to compare with..,1: The MAC Address23[47:0] is used to compare with.."
newline
hexmask.long.byte 0xB8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xB8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xB8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xB8 0.--15. 1. "ADDRHI,MAC Address23 [47:32]."
line.long 0xBC "MAC_Address23_Low,The MAC_Address23_Low register holds the lower 32 bits of the 23th 6-byte MAC address of the station."
hexmask.long 0xBC 0.--31. 1. "ADDRLO,MAC Address23 [31:0]."
line.long 0xC0 "MAC_Address24_High,The MAC_Address24_High register holds the upper 16 bits of the 24th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address24_Low register."
bitfld.long 0xC0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 24th MAC.."
newline
bitfld.long 0xC0 30. "SA,Source Address." "0: The MAC Address24[47:0] is used to compare with..,1: The MAC Address24[47:0] is used to compare with.."
newline
hexmask.long.byte 0xC0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xC0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xC0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xC0 0.--15. 1. "ADDRHI,MAC Address24 [47:32]."
line.long 0xC4 "MAC_Address24_Low,The MAC_Address24_Low register holds the lower 32 bits of the 24th 6-byte MAC address of the station."
hexmask.long 0xC4 0.--31. 1. "ADDRLO,MAC Address24 [31:0]."
line.long 0xC8 "MAC_Address25_High,The MAC_Address25_High register holds the upper 16 bits of the 25th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address25_Low register."
bitfld.long 0xC8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 25th MAC.."
newline
bitfld.long 0xC8 30. "SA,Source Address." "0: The MAC Address25[47:0] is used to compare with..,1: The MAC Address25[47:0] is used to compare with.."
newline
hexmask.long.byte 0xC8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xC8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xC8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xC8 0.--15. 1. "ADDRHI,MAC Address25 [47:32]."
line.long 0xCC "MAC_Address25_Low,The MAC_Address25_Low register holds the lower 32 bits of the 25th 6-byte MAC address of the station."
hexmask.long 0xCC 0.--31. 1. "ADDRLO,MAC Address25 [31:0]."
line.long 0xD0 "MAC_Address26_High,The MAC_Address26_High register holds the upper 16 bits of the 26th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address26_Low register."
bitfld.long 0xD0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 26th MAC.."
newline
bitfld.long 0xD0 30. "SA,Source Address." "0: The MAC Address26[47:0] is used to compare with..,1: The MAC Address26[47:0] is used to compare with.."
newline
hexmask.long.byte 0xD0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xD0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xD0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xD0 0.--15. 1. "ADDRHI,MAC Address26 [47:32]."
line.long 0xD4 "MAC_Address26_Low,The MAC_Address26_Low register holds the lower 32 bits of the 26th 6-byte MAC address of the station."
hexmask.long 0xD4 0.--31. 1. "ADDRLO,MAC Address26 [31:0]."
line.long 0xD8 "MAC_Address27_High,The MAC_Address27_High register holds the upper 16 bits of the 27th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address27_Low register."
bitfld.long 0xD8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 27th MAC.."
newline
bitfld.long 0xD8 30. "SA,Source Address." "0: The MAC Address27[47:0] is used to compare with..,1: The MAC Address27[47:0] is used to compare with.."
newline
hexmask.long.byte 0xD8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xD8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xD8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xD8 0.--15. 1. "ADDRHI,MAC Address27 [47:32]."
line.long 0xDC "MAC_Address27_Low,The MAC_Address27_Low register holds the lower 32 bits of the 27th 6-byte MAC address of the station."
hexmask.long 0xDC 0.--31. 1. "ADDRLO,MAC Address27 [31:0]."
line.long 0xE0 "MAC_Address28_High,The MAC_Address28_High register holds the upper 16 bits of the 28th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address28_Low register."
bitfld.long 0xE0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 28th MAC.."
newline
bitfld.long 0xE0 30. "SA,Source Address." "0: The MAC Address28[47:0] is used to compare with..,1: The MAC Address28[47:0] is used to compare with.."
newline
hexmask.long.byte 0xE0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xE0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xE0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xE0 0.--15. 1. "ADDRHI,MAC Address28 [47:32]."
line.long 0xE4 "MAC_Address28_Low,The MAC_Address28_Low register holds the lower 32 bits of the 28th 6-byte MAC address of the station."
hexmask.long 0xE4 0.--31. 1. "ADDRLO,MAC Address28 [31:0]."
line.long 0xE8 "MAC_Address29_High,The MAC_Address29_High register holds the upper 16 bits of the 29th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address29_Low register."
bitfld.long 0xE8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 29th MAC.."
newline
bitfld.long 0xE8 30. "SA,Source Address." "0: The MAC Address29[47:0] is used to compare with..,1: The MAC Address29[47:0] is used to compare with.."
newline
hexmask.long.byte 0xE8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xE8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xE8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xE8 0.--15. 1. "ADDRHI,MAC Address29 [47:32]."
line.long 0xEC "MAC_Address29_Low,The MAC_Address29_Low register holds the lower 32 bits of the 29th 6-byte MAC address of the station."
hexmask.long 0xEC 0.--31. 1. "ADDRLO,MAC Address29 [31:0]."
line.long 0xF0 "MAC_Address30_High,The MAC_Address30_High register holds the upper 16 bits of the 30th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address30_Low register."
bitfld.long 0xF0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 30th MAC.."
newline
bitfld.long 0xF0 30. "SA,Source Address." "0: The MAC Address30[47:0] is used to compare with..,1: The MAC Address30[47:0] is used to compare with.."
newline
hexmask.long.byte 0xF0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xF0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xF0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xF0 0.--15. 1. "ADDRHI,MAC Address30 [47:32]."
line.long 0xF4 "MAC_Address30_Low,The MAC_Address30_Low register holds the lower 32 bits of the 30th 6-byte MAC address of the station."
hexmask.long 0xF4 0.--31. 1. "ADDRLO,MAC Address30 [31:0]."
line.long 0xF8 "MAC_Address31_High,The MAC_Address31_High register holds the upper 16 bits of the 31th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address31_Low register."
bitfld.long 0xF8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 31th MAC.."
newline
bitfld.long 0xF8 30. "SA,Source Address." "0: The MAC Address31[47:0] is used to compare with..,1: The MAC Address31[47:0] is used to compare with.."
newline
hexmask.long.byte 0xF8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xF8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xF8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xF8 0.--15. 1. "ADDRHI,MAC Address31 [47:32]."
line.long 0xFC "MAC_Address31_Low,The MAC_Address31_Low register holds the lower 32 bits of the 31th 6-byte MAC address of the station."
hexmask.long 0xFC 0.--31. 1. "ADDRLO,MAC Address31 [31:0]."
group.long 0x700++0x7
line.long 0x0 "MAC_Indir_Access_Ctrl,This register provides the Indirect Access control and status for MAC_<MSEL>_IndReg(#AOFF) registers."
bitfld.long 0x0 31. "SNPS_R,Synopsys Reserved" "0,1"
newline
rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
hexmask.long.byte 0x0 26.--29. 1. "MSEL,Mode Select"
newline
rbitfld.long 0x0 24.--25. "Reserved_25_24,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--23. 1. "Reserved_23_x,Reserved"
newline
hexmask.long.byte 0x0 8.--15. 1. "AOFF,Address Offset"
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 5. "AUTO,Auto increment" "0,1"
newline
rbitfld.long 0x0 2.--4. "Reserved_4_2,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1. "COM,Command type" "0,1"
newline
bitfld.long 0x0 0. "OB,Operation Busy" "0,1"
line.long 0x4 "MAC_Indir_Access_Data,This register holds the read/write data for Indirect Access of MAC_<MSEL_IndReg(#AOFF) registers."
hexmask.long 0x4 0.--31. 1. "DATA,This field contains data to read/write for Indirect address access associated with MAC_Indir_Access_Ctrl register."
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg0,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg1,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg10,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg11,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg12,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg13,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg14,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg15,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg16,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg17,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg18,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg19,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg2,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg20,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg21,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg22,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg23,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg24,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg25,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg26,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg27,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg28,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg29,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg3,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg30,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg31,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg4,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg5,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg6,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg7,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg8,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg9,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x800++0x3
line.long 0x0 "MMC_Control,The MMC Control register establishes the operating mode of the management counters."
hexmask.long.word 0x0 19.--31. 1. "Reserved_31_19,Reserved."
newline
rbitfld.long 0x0 16.--18. "Reserved_PRMMCSEL,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "CNTPRST,Counters Preset" "0,1"
newline
rbitfld.long 0x0 6. "Reserved_6,Reserved." "0,1"
newline
bitfld.long 0x0 4.--5. "MCT,MMC Counter Threshold" "0: Reserved,1: One-quarter the maximum value,2: One-half of the maximum value,3: Three-quarters of the maximum value"
newline
bitfld.long 0x0 3. "MCF,MMC Counter Freeze" "0,1"
newline
bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1"
newline
bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1"
newline
bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1"
rgroup.long 0x804++0x7
line.long 0x0 "MMC_Rx_Interrupt,The MMC Receive Interrupt Status register maintains the interrupts generated when receive statistic counters reach the threshold programmed in the MMC control register. When the MMC counter that caused the interrupt is read. the.."
bitfld.long 0x0 31. "RXPRMMCIS,Rx Priority MMC Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
bitfld.long 0x0 29. "SGFPIS,SGF Fail Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 28. "SGPPIS,SGF Pass Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 27. "RXALEPIS,Rx Alignment Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 26. "RXLPITRCIS,Rx LPI Transition Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 25. "RXLPIUSCIS,Rx LPI microsecond Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 24. "RXDISOCGBIS,Rx Good Bad Discarded Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 23. "RXDISPCGBIS,Rx Good Bad Discarded Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 22. "RXWDOGPIS,Rx Watchdog Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 21. "RXVLANGBPIS,Rx Good Bad VLAN Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 20. "RXFOVPIS,Rx Queue Overflow Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 19. "RXPAUSPIS,Rx Pause Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "RXORANGEPIS,Rx Out-of-Range Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "RXLENERPIS,Rx Length Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "RXUCGPIS,Rx Good Unicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 15. "RX1024TMAXOCTGBPIS,Rx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 14. "RX512T1023OCTGBPIS,Rx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 13. "RX256T511OCTGBPIS,Rx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 12. "RX128T255OCTGBPIS,Rx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 11. "RX65T127OCTGBPIS,Rx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "RX64OCTGBPIS,Rx Good Bad 64 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "RXOSIZEGPIS,Rx Good Oversize Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "RXUSIZEGPIS,Rx Good Undersize Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 7. "RXJABERPIS,Rx Jabber Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "RXRUNTPIS,Rx Runt Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "RXCRCERPIS,Rx CRC Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "RXMCGPIS,Rx Good Multicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "RXBCGPIS,Rx Good Broadcast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "RXGOCTIS,Rx Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "RXGBOCTIS,Rx Good Bad Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "RXGBPKTIS,Rx Good Bad Packet Counter Interrupt Status" "0,1"
line.long 0x4 "MMC_Tx_Interrupt,The MMC Transmit Interrupt Status register maintains the interrupts generated when the transmit statistic counters reach the threshold value programmed in MMC control register (for example. the counter's MSB is set). This register is 32.."
bitfld.long 0x4 31. "TXPRMMCIS,Tx Priority MMC Counter Interrupt Status" "0,1"
newline
hexmask.long.byte 0x4 27.--30. 1. "Reserved_30_27,Reserved."
newline
bitfld.long 0x4 26. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 25. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 24. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 23. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 22. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 21. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 20. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 19. "TXLPITRCIS,Tx LPI Transition Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 18. "TXLPIUSCIS,Tx LPI microsecond Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 17. "TXVLANGPIS,Tx Good VLAN Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 16. "TXPAUSPIS,Tx Pause Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 15. "TXGPKTIS,Tx Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 14. "TXGOCTIS,Tx Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 13. "TXUFLOWERPIS,Tx Underflow Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 12. "TXBCGBPIS,Tx Good Bad Broadcast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 11. "TXMCGBPIS,Tx Good Bad Multicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 10. "TXUCGBPIS,Tx Good Bad Unicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 9. "TX1024TMAXOCTGBPIS,Tx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 8. "TX512T1023OCTGBPIS,Tx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 7. "TX256T511OCTGBPIS,Tx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 6. "TX128T255OCTGBPIS,Tx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 5. "TX65T127OCTGBPIS,Tx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 4. "TX64OCTGBPIS,Tx Good Bad 64 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 3. "TXMCGPIS,Tx Good Multicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 2. "TXBCGPIS,Tx Good Broadcast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 1. "TXGBPKTIS,Tx Good Bad Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 0. "TXGBOCTIS,Tx Good Bad Octet Counter Interrupt Status" "0,1"
group.long 0x80C++0x7
line.long 0x0 "MMC_Receive_Interrupt_Enable,The MMC Receive Interrupt Enable register maintains the enables for the interrupts generated when receive statistic counters reach the threshold value programmed in the MMC Control register. This register is 32 bits wide."
rbitfld.long 0x0 31. "Reserved_RXPRMMCIE,Reserved." "0,1"
newline
rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
rbitfld.long 0x0 29. "Reserved_SGFPIE,Reserved." "0,1"
newline
rbitfld.long 0x0 28. "Reserved_SGPPIE,Reserved." "0,1"
newline
bitfld.long 0x0 27. "RXALEPIE,Rx Alignment Error Packet Counter Interrupt Enable" "0,1"
newline
rbitfld.long 0x0 26. "Reserved_RXLPITRCIE,Reserved." "0,1"
newline
rbitfld.long 0x0 25. "Reserved_RXLPIUSCIE,Reserved." "0,1"
newline
bitfld.long 0x0 24. "RXDISOCGBIE,Rx Discard Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 23. "RXDISPCGBIE,Rx Discard Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 22. "RXWDOGPIE,Rx Watchdog Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 21. "RXVLANGBPIE,Rx Good Bad VLAN Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 20. "RXFOVPIE,Rx Queue Overflow Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 19. "RXPAUSPIE,Rx Pause Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 18. "RXORANGEPIE,Rx Out-of-Range Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 17. "RXLENERPIE,Rx Length Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 16. "RXUCGPIE,Rx Good Unicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 15. "RX1024TMAXOCTGBPIE,Rx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 14. "RX512T1023OCTGBPIE,Rx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 13. "RX256T511OCTGBPIE,Rx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 12. "RX128T255OCTGBPIE,Rx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 11. "RX65T127OCTGBPIE,Rx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 10. "RX64OCTGBPIE,Rx Good Bad 64 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 9. "RXOSIZEGPIE,Rx Good Oversize Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 8. "RXUSIZEGPIE,Rx Good Undersize Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 7. "RXJABERPIE,Rx Jabber Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 6. "RXRUNTPIE,Rx Runt Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 5. "RXCRCERPIE,Rx CRC Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 4. "RXMCGPIE,Rx Good Multicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 3. "RXBCGPIE,Rx Good Broadcast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "RXGOCTIE,Rx Good Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 1. "RXGBOCTIE,Rx Good Bad Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "RXGBPKTIE,Rx Good Bad Packet Counter Interrupt Enable" "0,1"
line.long 0x4 "MMC_Transmit_Interrupt_Enable,The MMC Transmit Interrupt Enable register maintains the enables for the interrupts generated when transmit statistic counters reach the threshold value programmed in the MMC Control register. This register is 32 bits wide."
rbitfld.long 0x4 31. "Reserved_TXPRMMCIE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 27.--30. 1. "Reserved_30_27,Reserved."
newline
bitfld.long 0x4 26. "TXEXDEFPIE,MMC Transmit Excessive Deferral Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 25. "TXCARERPIE,MMC Transmit Carrier Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 24. "TXEXCOLPIE,MMC Transmit Excessive Collision Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 23. "TXLATCOLPIE,MMC Transmit Late Collision Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 22. "TXDEFPIE,MMC Transmit Deferred Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 21. "TXMCOLGPIE,MMC Transmit Multiple Collision Good Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 20. "TXSCOLGPIE,MMC Transmit Single Collision Good Packet Counter Interrupt Enable" "0,1"
newline
rbitfld.long 0x4 19. "Reserved_TXLPITRCIE,Reserved." "0,1"
newline
rbitfld.long 0x4 18. "Reserved_TXLPIUSCIE,Reserved." "0,1"
newline
bitfld.long 0x4 17. "TXVLANGPIE,Tx Good VLAN Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 16. "TXPAUSPIE,Tx Pause Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 15. "TXGPKTIE,Tx Good Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 14. "TXGOCTIE,Tx Good Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 13. "TXUFLOWERPIE,Tx Underflow Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 12. "TXBCGBPIE,Tx Good Bad Broadcast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 11. "TXMCGBPIE,Tx Good Bad Multicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 10. "TXUCGBPIE,Tx Good Bad Unicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 9. "TX1024TMAXOCTGBPIE,Tx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 8. "TX512T1023OCTGBPIE,Tx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 7. "TX256T511OCTGBPIE,Tx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 6. "TX128T255OCTGBPIE,Tx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 5. "TX65T127OCTGBPIE,Tx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 4. "TX64OCTGBPIE,Tx Good Bad 64 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 3. "TXMCGPIE,Tx Good Multicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 2. "TXBCGPIE,Tx Good Broadcast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 1. "TXGBPKTIE,Tx Good Bad Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 0. "TXGBOCTIE,Tx Good Bad Octet Counter Interrupt Enable" "0,1"
rgroup.long 0x814++0xB
line.long 0x0 "Tx_Octet_Count_Good_Bad_Low,This register provides lower 32 bits of transmitted octet count. excluding preamble. in good and bad packets."
hexmask.long 0x0 0.--31. 1. "TXOCTGBLO,Tx Good Bad Octet Count Low"
line.long 0x4 "Tx_Octet_Count_Good_Bad_High,This register provides upper 32 bits of transmitted octet count. excluding preamble. in good and bad packets."
hexmask.long 0x4 0.--31. 1. "TXOCTGBHI,Tx Good Bad Octet Count High"
line.long 0x8 "Tx_Packet_Count_Good_Bad_Low,This register provides lower 32 bits of transmitted good and bad packet count."
hexmask.long 0x8 0.--31. 1. "TXPKTGBLO,Tx Good Bad Packet Count Low"
rgroup.long 0x824++0x3
line.long 0x0 "Tx_Broadcast_Packets_Good_Low,This register provides lower 32 bits of transmitted good broadcast packets count."
hexmask.long 0x0 0.--31. 1. "TXBCASTGLO,Tx Good Broadcast Packet Count Low."
rgroup.long 0x82C++0x3
line.long 0x0 "Tx_Multicast_Packets_Good_Low,This register provides lower 32 bits of transmitted good multicast packets count."
hexmask.long 0x0 0.--31. 1. "TXMCASTGLO,Tx Good Multicast Packet Count Low"
rgroup.long 0x834++0x3
line.long 0x0 "Tx_64Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 64 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX64OCTGBLO,Tx Good Bad 64 Octet Size Packet Count Low"
rgroup.long 0x83C++0x3
line.long 0x0 "Tx_65To127Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 65-to-127 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX65_127OCTGBLO,Tx Good Bad 65-to-127 Octet Size Packet Count Low"
rgroup.long 0x844++0x3
line.long 0x0 "Tx_128To255Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 128-to-255 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX128_255OCTGBLO,Tx Good Bad 128-to-255 Octet Size Packet Count Low"
rgroup.long 0x84C++0x3
line.long 0x0 "Tx_256To511Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 256-to-511 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX256_511OCTGBLO,Tx Good Bad 256-to-511 Octet Size Packet Count Low"
rgroup.long 0x854++0x3
line.long 0x0 "Tx_512To1023Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 512-to-1023 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX512_1023OCTGBLO,Tx Good Bad 512-to-1023 Octet Size Packet Count Low"
rgroup.long 0x85C++0x3
line.long 0x0 "Tx_1024ToMaxOctets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 1024-tomaxsize octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX1024_MAXOCTGBLO,Tx Good Bad 1024-tomaxsize Octet Size Packet Count Low"
rgroup.long 0x864++0x3
line.long 0x0 "Tx_Unicast_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted good bad unicast packets count."
hexmask.long 0x0 0.--31. 1. "TXUCASTGBLO,Tx Good Bad Unicast Packet Count Low"
rgroup.long 0x86C++0x3
line.long 0x0 "Tx_Multicast_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted good bad multicast packets count."
hexmask.long 0x0 0.--31. 1. "TXMCASTGBLO,Tx Good Bad Multicast Packet Count Low"
rgroup.long 0x874++0x3
line.long 0x0 "Tx_Broadcast_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted good bad broadcast packets count."
hexmask.long 0x0 0.--31. 1. "TXBCASTGBLO,Tx Good Bad Broadcast Packet Count Low"
rgroup.long 0x87C++0x3
line.long 0x0 "Tx_Underflow_Error_Packets_Low,This register provides lower 32 bits of transmitted packets aborted due to packet underflow error count."
hexmask.long 0x0 0.--31. 1. "TXUNDRFLWLO,Tx Underflow Error Packet Count Low"
rgroup.long 0x884++0xB
line.long 0x0 "Tx_Octet_Count_Good_Low,This register provides lower 32 bits of transmitted good octets count."
hexmask.long 0x0 0.--31. 1. "TXOCTGLO,Tx Good Octet Count Low"
line.long 0x4 "Tx_Octet_Count_Good_High,This register provides upper 32 bits of transmitted good octets count."
hexmask.long 0x4 0.--31. 1. "TXOCTGHI,Tx Good Octet Count High"
line.long 0x8 "Tx_Packet_Count_Good_Low,This register provides lower 32 bits of transmitted good packets count."
hexmask.long 0x8 0.--31. 1. "TXPKTGLO,Tx Good Packet Count Low"
rgroup.long 0x894++0x3
line.long 0x0 "Tx_Pause_Packets_Low,This register provides lower 32 bits of transmitted Pause packets count."
hexmask.long 0x0 0.--31. 1. "TXPAUSEGLO,Tx Pause Packet Count Low"
rgroup.long 0x89C++0x3
line.long 0x0 "Tx_VLAN_Packets_Good_Low,This register provides lower 32 bits of transmitted good VLAN packets count."
hexmask.long 0x0 0.--31. 1. "TXVLANGLO,Tx Good VLAN Packet Count Low"
rgroup.long 0x900++0x3
line.long 0x0 "Rx_Packet_Count_Good_Bad_Low,This register provides lower 32 bits of received good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RXPKTGBLO,Rx Good Bad Packet Count Low"
rgroup.long 0x908++0x13
line.long 0x0 "Rx_Octet_Count_Good_Bad_Low,This register provides lower 32 bits of received octet count. excluding preamble. in good and bad packets."
hexmask.long 0x0 0.--31. 1. "RXOCTGBLO,Rx Good Bad Octet Count Low"
line.long 0x4 "Rx_Octet_Count_Good_Bad_High,This register provides upper 32 bits of received octet count. excluding preamble. in good and bad packets."
hexmask.long 0x4 0.--31. 1. "RXOCTGBHI,Rx Good Bad Octet Count High"
line.long 0x8 "Rx_Octet_Count_Good_Low,This register provides lower 32 bits of received good octets count."
hexmask.long 0x8 0.--31. 1. "RXOCTGLO,Rx Good Octet Count Low"
line.long 0xC "Rx_Octet_Count_Good_High,This register provides upper 32 bits of received good octets count."
hexmask.long 0xC 0.--31. 1. "RXOCTGHI,Rx Good Octet Count High"
line.long 0x10 "Rx_Broadcast_Packets_Good_Low,This register provides lower 32 bits of received good broadcast packets count."
hexmask.long 0x10 0.--31. 1. "RXBCASTGLO,Rx Good Broadcast Packet Count Low"
rgroup.long 0x920++0x3
line.long 0x0 "Rx_Multicast_Packets_Good_Low,This register provides lower 32 bits of received good multicast packets count."
hexmask.long 0x0 0.--31. 1. "RXMCASTGLO,Rx Good Multicast Packet Count Low"
rgroup.long 0x928++0x3
line.long 0x0 "Rx_CRC_Error_Packets_Low,This register provides lower 32 bits of received packets with CRC error count."
hexmask.long 0x0 0.--31. 1. "RXCRCERLO,Rx CRC Error Packet Count Low"
rgroup.long 0x930++0x13
line.long 0x0 "Rx_Runt_Error_Packets,This register provides received packets with Runt error count."
hexmask.long 0x0 0.--31. 1. "RXRUNTER,Rx Runt Error Packet Count"
line.long 0x4 "Rx_Jabber_Error_Packets,This register provides received packets with Jabber error count."
hexmask.long 0x4 0.--31. 1. "RXJABERER,Rx Jabber Error Packet Count"
line.long 0x8 "Rx_Undersize_Packets_Good,This register provides count of received good undersize packets."
hexmask.long 0x8 0.--31. 1. "RXUSIZEG,Rx Good Undersize Packet Count"
line.long 0xC "Rx_Oversize_Packets_Good,This register provides count of received good oversize packets."
hexmask.long 0xC 0.--31. 1. "RXOSIZEG,Rx Good Oversize Packet Count"
line.long 0x10 "Rx_64Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 64 octet size good and bad packets count."
hexmask.long 0x10 0.--31. 1. "RX64OCTGBLO,Rx Good Bad 64 Octet Size Packet Count Low"
rgroup.long 0x948++0x3
line.long 0x0 "Rx_65To127Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 65-to-127 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX65_127OCTGBLO,Rx Good Bad 65-to-127 Octet Size Packet Count Low"
rgroup.long 0x950++0x3
line.long 0x0 "Rx_128To255Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 128-to-255 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX128_255OCTGBLO,Rx Good Bad 128-to-255 Octet Size Packet Count Low"
rgroup.long 0x958++0x3
line.long 0x0 "Rx_256To511Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 256-to-511 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX256_511OCTGBLO,Rx Good Bad 256-to-511 Octet Size Packet Count Low"
rgroup.long 0x960++0x3
line.long 0x0 "Rx_512To1023Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 512-to-1023 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX512_1023OCTGBLO,Rx Good Bad 512-to-1023 Octet Size Packet Count Low"
rgroup.long 0x968++0x3
line.long 0x0 "Rx_1024ToMaxOctets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 1024-tomaxsize octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX1024_MAXOCTGBLO,Rx Good Bad 1024-tomaxsize Octet Size Packet Count Low"
rgroup.long 0x970++0x3
line.long 0x0 "Rx_Unicast_Packets_Good_Low,This register provides lower 32 bits of received good unicast packets count."
hexmask.long 0x0 0.--31. 1. "RXUCASTGLO,Rx Good Unicast Packet Count Low"
rgroup.long 0x978++0x3
line.long 0x0 "Rx_Length_Error_Packets_Low,This register provides lower 32 bits of received packets with Length error count."
hexmask.long 0x0 0.--31. 1. "RXLENERRLO,Rx Length Error Packet Count Low"
rgroup.long 0x980++0x3
line.long 0x0 "Rx_OutofRange_Packets_Low,This register provides lower 32 bits of received packets with out of range length field count."
hexmask.long 0x0 0.--31. 1. "RXORANGELO,Rx Out of Range Packet Count Low"
rgroup.long 0x988++0x3
line.long 0x0 "Rx_Pause_Packets_Low,This register provides lower 32 bits of received Pause packets count."
hexmask.long 0x0 0.--31. 1. "RXPAUSELO,Rx Pause Packet Count Low"
rgroup.long 0x990++0x3
line.long 0x0 "Rx_FIFOOverflow_Packets_Low,This register provides lower 32 bits of received packets count that had Rx Queue overflow."
hexmask.long 0x0 0.--31. 1. "RXFOVFLO,Rx FIFO Overflow Packet Count Low"
rgroup.long 0x998++0x3
line.long 0x0 "Rx_VLAN_Packets_Good_Bad_Low,This register provides lower 32 bits of received good bad VLAN packets count."
hexmask.long 0x0 0.--31. 1. "RXVLANGBLO,Rx Good Bad VLAN Packet Count Low"
rgroup.long 0x9A0++0x3
line.long 0x0 "Rx_Watchdog_Error_Packets,This register has a count of packets that are received with watchdog error."
hexmask.long 0x0 0.--31. 1. "RXWDOGERR,Rx Watchdog Error Packet Count"
rgroup.long 0x9AC++0x3
line.long 0x0 "Rx_Discard_Packets_Good_Bad_Low,This register provides lower 32 bits of received good bad packets count that were discarded due to filter fail."
hexmask.long 0x0 0.--31. 1. "RXDPCNTGBLO,Rx Good Bad Discard Packet Count Low"
rgroup.long 0x9B4++0xB
line.long 0x0 "Rx_Discard_Octets_Good_Bad_Low,This register provides lower 32 bits of received good bad octets count that were discarded due to filter fail."
hexmask.long 0x0 0.--31. 1. "RXDOCNTGBLO,Rx Good Bad Discard Octet Count Low"
line.long 0x4 "Rx_Discard_Octets_Good_Bad_High,This register provides upper 32 bits of received good bad octets count that were discarded due to filter fail."
hexmask.long 0x4 0.--31. 1. "RXDOCNTGBHI,Rx Good Bad Discard Octet Count High"
line.long 0x8 "Rx_Alignment_Error_Packets,This register provides the number of packets received by DWC_xgmac with alignment (dribble) error. It is valid only in 10/100 mode."
hexmask.long 0x8 0.--31. 1. "RXALIGNERR,Rx Alignment Error Packet Count"
rgroup.long 0xA00++0x3
line.long 0x0 "MMC_FPE_Tx_Interrupt,This register maintains the interrupts generated from all FPE related Transmit statistics counters. The MMC FPE Transmit Interrupt register maintains the interrupts generated when the transmit statistic counters reach the threshold.."
hexmask.long 0x0 3.--31. 1. "Reserved_31_3,Reserved."
newline
bitfld.long 0x0 2. "GOCIS,MMC Tx Gate/Window Overrun Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status" "0,1"
group.long 0xA04++0x3
line.long 0x0 "MMC_FPE_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Transmit statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.."
hexmask.long 0x0 3.--31. 1. "Reserved_31_3,Reserved."
newline
bitfld.long 0x0 2. "GOCIM,MMC Transmit Gate/Window Overrun Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask" "0,1"
rgroup.long 0xA08++0xF
line.long 0x0 "MMC_Tx_FPE_Fragment_Cntr,This register provides the number of additional mPackets transmitted due to preemption."
hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter"
line.long 0x4 "MMC_Tx_Hold_Req_Cntr,This register provides the count of number of times a hold request is given to MAC"
hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter"
line.long 0x8 "MMC_Tx_Gate_Orun_Cntr_Low,This register provides the lower 32-bits of counter that counts the number of times packets overrun the transmission gate/window."
hexmask.long 0x8 0.--31. 1. "TXGOCL,Tx Gate/Window Overrun Counter Low"
line.long 0xC "MMC_Tx_Gate_Orun_Cntr_High,This register provides the upper 32-bits of counter that counts the number of times packets overrun the transmission gate/window."
hexmask.long 0xC 0.--31. 1. "TXGOCH,Tx Gate/Window Overrun Counter High"
rgroup.long 0xA20++0x3
line.long 0x0 "MMC_FPE_Rx_Interrupt,This register maintains the interrupts generated from all FPE related Receive statistics counters. The MMC FPE Receive Interrupt register maintains the interrupts generated when receive statistic counters reach the threshold value.."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status" "0,1"
group.long 0xA24++0x3
line.long 0x0 "MMC_FPE_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask" "0,1"
rgroup.long 0xA28++0xF
line.long 0x0 "MMC_Rx_Packet_Assembly_Err_Cntr,This register provides the number of MAC frames with reassembly errors on the Receiver. due to mismatch in the Fragment Count value."
hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter"
line.long 0x4 "MMC_Rx_Packet_SMD_Err_Cntr,This register provides the number of received MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame."
hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter"
line.long 0x8 "MMC_Rx_Packet_Assembly_OK_Cntr,This register provides the number of MAC frames that were successfully reassembled and delivered to MAC."
hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter"
line.long 0xC "MMC_Rx_FPE_Fragment_Cntr,This register provides the number of additional mPackets received due to preemption."
hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter"
rgroup.long 0xA40++0x1B
line.long 0x0 "Tx_Single_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_xgmac after a single collision in the half-duplex mode."
hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets"
line.long 0x4 "Tx_Multiple_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_xgmac after multiple collisions in the half-duplex mode."
hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets"
line.long 0x8 "Tx_Deferred_Packets,This register provides the number of successfully transmitted by DWC_xgmac after a deferral in the half-duplex mode."
hexmask.long 0x8 0.--31. 1. "TXDEFRD,Tx Deferred Packets"
line.long 0xC "Tx_Late_Collision_Packets,This register provides the number of packets aborted by DWC_xgmac because of late collision error."
hexmask.long 0xC 0.--31. 1. "TXLATECOL,Tx Late Collision Packets"
line.long 0x10 "Tx_Excessive_Collision_Packets,This register provides the number of packets aborted by DWC_xgmac because of excessive (16) collision errors."
hexmask.long 0x10 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets"
line.long 0x14 "Tx_Carrier_Error_Packets,This register provides the number of packets aborted by DWC_xgmac because of carrier sense error (no carrier or loss of carrier)."
hexmask.long 0x14 0.--31. 1. "TXCARR,Tx Carrier Error Packets"
line.long 0x18 "Tx_Excessive_Deferral_Error,This register provides the number of packets aborted by DWC_xgmac because of excessive deferral error (deferred for more than two max-size packet times)."
hexmask.long 0x18 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error"
group.long 0xA5C++0x3
line.long 0x0 "MMC_IPC_Rx_Interrupt_Mask,This register maintains the mask for the interrupt generated from the receive IPC statistic counters."
rbitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 29. "RXICMPEROIM,MMC Receive ICMP Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 28. "RXICMPGOIM,MMC Receive ICMP Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 27. "RXTCPEROIM,MMC Receive TCP Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 26. "RXTCPGOIM,MMC Receive TCP Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 25. "RXUDPEROIM,MMC Receive UDP Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 24. "RXUDPGOIM,MMC Receive IPv6 No Payload Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 23. "RXIPV6NOPAYOIM,MMC Receive IPv6 Header Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 22. "RXIPV6HEROIM,MMC Receive IPv6 Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 21. "RXIPV6GOIM,MMC Receive IPv6 Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 20. "RXIPV4UDSBLOIM,MMC Receive IPv4 UDP Checksum Disabled Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 19. "RXIPV4FRAGOIM,MMC Receive IPv4 Fragmented Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 18. "RXIPV4NOPAYOIM,MMC Receive IPv4 No Payload Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 17. "RXIPV4HEROIM,MMC Receive IPv4 Header Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 16. "RXIPV4GOIM,MMC Receive IPv4 Good Octet Counter Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 13. "RXICMPERPIM,MMC Receive ICMP Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 12. "RXICMPGPIM,MMC Receive ICMP Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 11. "RXTCPERPIM,MMC Receive TCP Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 10. "RXTCPGPIM,MMC Receive TCP Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 9. "RXUDPERPIM,MMC Receive UDP Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 8. "RXUDPGPIM,MMC Receive UDP Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 7. "RXIPV6NOPAYPIM,MMC Receive IPv6 No Payload Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 6. "RXIPV6HERPIM,MMC Receive IPv6 Header Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 5. "RXIPV6GPIM,MMC Receive IPv6 Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 4. "RXIPV4UDSBLPIM,MMC Receive IPv4 UDP Checksum Disabled Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXIPV4FRAGPIM,MMC Receive IPv4 Fragmented Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXIPV4NOPAYPIM,MMC Receive IPv4 No Payload Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "RXIPV4HERPIM,MMC Receive IPv4 Header Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "RXIPV4GPIM,MMC Receive IPv4 Good Packet Counter Interrupt Mask" "0,1"
rgroup.long 0xA60++0x7
line.long 0x0 "MMC_IPC_Rx_Interrupt,This register maintains the interrupt that the receive IPC statistic counters generate."
bitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 29. "RXICMPEROIS,MMC Receive ICMP Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 28. "RXICMPGOIS,MMC Receive ICMP Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 27. "RXTCPEROIS,MMC Receive TCP Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 26. "RXTCPGOIS,MMC Receive TCP Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 25. "RXUDPEROIS,MMC Receive UDP Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 24. "RXUDPGOIS,MMC Receive UDP Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 23. "RXIPV6NOPAYOIS,MMC Receive IPv6 No Payload Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 22. "RXIPV6HEROIS,MMC Receive IPv6 Header Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 21. "RXIPV6GOIS,MMC Receive IPv6 Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 20. "RXIPV4UDSBLOIS,MMC Receive IPv4 UDP Checksum Disabled Octet Counter Interrupt" "0,1"
newline
bitfld.long 0x0 19. "RXIPV4FRAGOIS,MMC Receive IPv4 Fragmented Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "RXIPV4NOPAYOIS,MMC Receive IPv4 No Payload Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "RXIPV4HEROIS,MMC Receive IPv4 Header Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "RXIPV4GOIS,MMC Receive IPv4 Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 13. "RXICMPERPIS,MMC Receive ICMP Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 12. "RXICMPGPIS,MMC Receive ICMP Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 11. "RXTCPERPIS,MMC Receive TCP Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "RXTCPGPIS,MMC Receive TCP Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "RXUDPERPIS,MMC Receive UDP Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "RXUDPGPIS,MC Receive UDP Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 7. "RXIPV6NOPAYPIS,MMC Receive IPv6 No Payload Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "RXIPV6HERPIS,MMC Receive IPv6 Header Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "RXIPV6GPIS,MMC Receive IPV6 Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "RXIPV4UDSBLPIS,MMC Receive IPv4 UDP Checksum Disabled Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "RXIPV4FRAGPIS,MMC Receive IPv4 Fragmented Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "RXIPV4NOPAYPIS,MMC Receive IPv4 No Payload Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "RXIPV4HERPIS,MMC Receive IPv4 Header Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "RXIPV4GPIS,MMC Receive IPv4 Good Packet Counter Interrupt Status" "0,1"
line.long 0x4 "RxIPv4_Good_Packets_Low,This register provides lower 32 bits of good IPv4 datagrams received by DWC_xgmac with the TCP. UDP. or ICMP payload."
hexmask.long 0x4 0.--31. 1. "RXIPV4GDPKTLO,RxIPv4 Good Packets"
rgroup.long 0xA6C++0x3
line.long 0x0 "RxIPv4_Header_Error_Packets_Low,RxIPv4 Header Error Packets"
hexmask.long 0x0 0.--31. 1. "RXIPV4HDRERRPKTLO,RxIPv4 Header Error Packets"
rgroup.long 0xA74++0x3
line.long 0x0 "RxIPv4_No_Payload_Packets_Low,This register provides lower 32 bits of IPv4 datagram packets received by DWC_xgmac that did not have a TCP. UDP. or ICMP payload."
hexmask.long 0x0 0.--31. 1. "RXIPV4NOPAYPKTLO,RxIPv4 Payload Packets"
rgroup.long 0xA7C++0x3
line.long 0x0 "RxIPv4_Fragmented_Packets_Low,This register provides lower 32 bits of good IPv4 datagrams received by DWC_xgmac with fragmentation."
hexmask.long 0x0 0.--31. 1. "RXIPV4FRAGPKTLO,RxIPv4 Fragmented Packets"
rgroup.long 0xA84++0x3
line.long 0x0 "RxIPv4_UDP_Checksum_Disabled_Packets_Low,This register provides lower 32 bits of good IPv4 datagrams received by DWC_xgmac that had a UDP payload with checksum disabled."
hexmask.long 0x0 0.--31. 1. "RXIPV4UDSBLPKTLO,RxIPv4 UDP Checksum Disabled Packets"
rgroup.long 0xA8C++0x3
line.long 0x0 "RxIPv6_Good_Packets_Low,This register provides lower 32 bits of good IPv6 datagrams received by DWC_xgmac with the TCP. UDP. or ICMP payload."
hexmask.long 0x0 0.--31. 1. "RXIPV6GDPKTLO,RxIPv6 Good Packets"
rgroup.long 0xA94++0x3
line.long 0x0 "RxIPv6_Header_Error_Packets_Low,This register provides lower 32 bits of IPv6 datagrams received by DWC_xgmac with header (length or version mismatch) errors."
hexmask.long 0x0 0.--31. 1. "RXIPV6HDRERRPKTLO,RxIPv6 Header Error Packets"
rgroup.long 0xA9C++0x3
line.long 0x0 "RxIPv6_No_Payload_Packets_Low,This register provides lower 32 bits of IPv6 datagram packets received by DWC_xgmac that did not have a TCP. UDP. or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers."
hexmask.long 0x0 0.--31. 1. "RXIPV6NOPAYPKTLO,RxIPv6 Payload Packets"
rgroup.long 0xAA4++0x3
line.long 0x0 "RxUDP_Good_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented."
hexmask.long 0x0 0.--31. 1. "RXUDPGDPKTLO,RxUDP Good Packets"
rgroup.long 0xAAC++0x3
line.long 0x0 "RxUDP_Error_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac whose UDP payload has a checksum error."
hexmask.long 0x0 0.--31. 1. "RXUDPERRPKTLO,RxUDP Error Packets"
rgroup.long 0xAB4++0x3
line.long 0x0 "RxTCP_Good_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac with a good TCP payload."
hexmask.long 0x0 0.--31. 1. "RXTCPGDPKTLO,RxTCP Good Packets"
rgroup.long 0xABC++0x3
line.long 0x0 "RxTCP_Error_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac whose TCP payload has a checksum error."
hexmask.long 0x0 0.--31. 1. "RXTCPERRPKTLO,RxTCP Error Packets"
rgroup.long 0xAC4++0x3
line.long 0x0 "RxICMP_Good_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac with a good ICMP payload."
hexmask.long 0x0 0.--31. 1. "RXICMPGDPKTLO,RxICMP Good Packets"
rgroup.long 0xACC++0x3
line.long 0x0 "RxICMP_Error_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac whose ICMP payload has a checksum error."
hexmask.long 0x0 0.--31. 1. "RXICMPERRPKTLO,RxICMP Error Packets"
rgroup.long 0xAD4++0x3
line.long 0x0 "RxIPv4_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in good IPv4 datagrams encapsulating TCP. UDP. or ICMP data. (Ethernet header. FCS. pad. or IP pad bytes are not included in this counter."
hexmask.long 0x0 0.--31. 1. "RXIPV4GDOCTLO,RxIPv4 Good Octets"
rgroup.long 0xADC++0x3
line.long 0x0 "RxIPv4_Header_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv4 datagrams with header errors (checksum. length. version mismatch). The value in the Length field of IPv4 header is used to update this counter."
hexmask.long 0x0 0.--31. 1. "RXIPV4HDRERROCTLO,RxIPv4 Header Error Octets"
rgroup.long 0xAE4++0x3
line.long 0x0 "RxIPv4_No_Payload_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv4 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. (Ethernet.."
hexmask.long 0x0 0.--31. 1. "RXIPV4NOPAYOCTLO,RxIPv4 Payload Octets"
rgroup.long 0xAEC++0x3
line.long 0x0 "RxIPv4_Fragmented_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header. FCS. pad. or IP pad bytes are.."
hexmask.long 0x0 0.--31. 1. "RXIPV4FRAGOCTLO,RxIPv4 Fragmented Octets"
rgroup.long 0xAF4++0x3
line.long 0x0 "RxIPv4_UDP_Checksum_Disable_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. (Ethernet header. FCS. pad. or IP pad bytes are.."
hexmask.long 0x0 0.--31. 1. "RXIPV4UDSBLOCTLO,RxIPv4 UDP Checksum Disable Octets"
rgroup.long 0xAFC++0x3
line.long 0x0 "RxIPv6_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in good IPv6 datagrams encapsulating TCP. UDP. or ICMP data. (Ethernet header. FCS. pad. or IP pad bytes are not included in this counter."
hexmask.long 0x0 0.--31. 1. "RXIPV6GDOCTLO,RxIPv6 Good Octets"
rgroup.long 0xB04++0x3
line.long 0x0 "RxIPv6_Header_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv6 datagrams with header errors (length. version mismatch). The value in the Length field of IPv6 header is used to update this counter. (Ethernet.."
hexmask.long 0x0 0.--31. 1. "RXIPV6HDRERROCTLO,RxIPv6 Header Error Octets"
rgroup.long 0xB0C++0x3
line.long 0x0 "RxIPv6_No_Payload_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv6 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. (Ethernet.."
hexmask.long 0x0 0.--31. 1. "RXIPV6NOPAYOCTLO,RxIPv6 Payload Octets"
rgroup.long 0xB14++0x3
line.long 0x0 "RxUDP_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a good UDP segment. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXUDPGDOCTLO,RxUDP Good Octets"
rgroup.long 0xB1C++0x3
line.long 0x0 "RxUDP_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a UDP segment that had checksum errors. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXUDPERROCTLO,RxUDP Error Octets"
rgroup.long 0xB24++0x3
line.long 0x0 "RxTCP_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a good TCP segment. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXTCPGDOCTLO,RxTCP Good Octets"
rgroup.long 0xB2C++0x3
line.long 0x0 "RxTCP_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a TCP segment that had checksum errors. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXTCPERROCTLO,RxTCP Error Octets"
rgroup.long 0xB34++0x3
line.long 0x0 "RxICMP_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a good ICMP segment. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXICMPGDOCTLO,RxICMP Good Octets"
rgroup.long 0xB3C++0x3
line.long 0x0 "RxICMP_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a ICMP segment that had checksum errors. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXICMPERROCTLO,RxICMP Error Octets"
group.long 0xC00++0x7
line.long 0x0 "MAC_L3_L4_Address_Control,This register has the indirect address and control for accessing the Layer 3 and Layer 4 Filter registers."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.byte 0x0 8.--15. 1. "IDDR,L3_L4 Filter Address."
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved."
newline
bitfld.long 0x0 1. "TT,Transfer Type." "0,1"
newline
bitfld.long 0x0 0. "XB,Transfer Busy." "0,1"
line.long 0x4 "MAC_L3_L4_Data,This register has the indirect data and control for accessing the Layer 3 and Layer 4 Filter registers."
hexmask.long 0x4 0.--31. 1. "IDATA,Indirect Data."
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control0,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE0,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control1,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE1,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control10,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE10,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM10,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM10,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM10,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM10,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN10,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM10,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM10,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM10,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM10,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM10,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM10,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN10,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control11,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE11,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM11,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM11,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM11,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM11,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN11,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM11,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM11,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM11,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM11,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM11,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM11,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN11,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control12,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE12,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM12,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM12,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM12,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM12,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN12,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM12,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM12,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM12,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM12,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM12,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM12,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN12,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control13,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE13,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM13,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM13,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM13,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM13,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN13,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM13,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM13,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM13,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM13,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM13,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM13,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN13,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control14,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE14,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM14,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM14,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM14,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM14,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN14,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM14,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM14,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM14,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM14,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM14,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM14,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN14,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control15,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE15,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM15,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM15,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM15,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM15,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN15,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM15,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM15,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM15,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM15,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM15,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM15,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN15,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control2,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE2,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM2,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM2,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM2,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM2,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN2,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM2,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM2,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM2,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM2,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM2,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM2,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN2,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control3,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE3,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM3,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM3,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM3,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM3,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN3,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM3,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM3,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM3,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM3,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM3,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM3,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN3,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control4,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE4,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM4,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM4,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM4,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM4,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN4,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM4,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM4,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM4,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM4,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM4,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM4,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN4,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control5,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE5,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM5,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM5,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM5,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM5,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN5,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM5,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM5,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM5,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM5,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM5,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM5,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN5,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control6,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE6,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM6,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM6,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM6,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM6,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN6,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM6,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM6,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM6,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM6,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM6,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM6,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN6,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control7,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE7,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM7,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM7,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM7,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM7,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN7,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM7,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM7,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM7,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM7,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM7,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM7,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN7,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control8,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE8,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM8,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM8,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM8,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM8,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN8,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM8,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM8,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM8,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM8,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM8,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM8,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN8,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control9,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE9,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM9,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM9,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM9,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM9,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN9,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM9,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM9,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM9,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM9,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM9,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM9,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN9,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg0,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg1,For IPv4 packets. the Layer 3 Address 0 Register 1 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg10,For IPv4 packets. the Layer 3 Address 0 Register 10 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A010,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg11,For IPv4 packets. the Layer 3 Address 0 Register 11 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A011,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg12,For IPv4 packets. the Layer 3 Address 0 Register 12 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A012,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg13,For IPv4 packets. the Layer 3 Address 0 Register 13 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A013,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg14,For IPv4 packets. the Layer 3 Address 0 Register 14 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A014,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg15,For IPv4 packets. the Layer 3 Address 0 Register 15 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A015,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg2,For IPv4 packets. the Layer 3 Address 0 Register 2 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A02,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg3,For IPv4 packets. the Layer 3 Address 0 Register 3 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A03,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg4,For IPv4 packets. the Layer 3 Address 0 Register 4 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A04,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg5,For IPv4 packets. the Layer 3 Address 0 Register 5 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A05,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg6,For IPv4 packets. the Layer 3 Address 0 Register 6 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A06,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg7,For IPv4 packets. the Layer 3 Address 0 Register 7 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A07,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg8,For IPv4 packets. the Layer 3 Address 0 Register 8 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A08,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg9,For IPv4 packets. the Layer 3 Address 0 Register 9 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A09,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg0,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A10,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg1,For IPv4 packets. the Layer 3 Address 1 Register 1 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A11,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg10,For IPv4 packets. the Layer 3 Address 1 Register 10 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A110,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg11,For IPv4 packets. the Layer 3 Address 1 Register 11 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A111,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg12,For IPv4 packets. the Layer 3 Address 1 Register 12 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A112,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg13,For IPv4 packets. the Layer 3 Address 1 Register 13 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A113,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg14,For IPv4 packets. the Layer 3 Address 1 Register 14 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A114,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg15,For IPv4 packets. the Layer 3 Address 1 Register 15 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A115,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg2,For IPv4 packets. the Layer 3 Address 1 Register 2 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A12,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg3,For IPv4 packets. the Layer 3 Address 1 Register 3 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A13,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg4,For IPv4 packets. the Layer 3 Address 1 Register 4 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A14,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg5,For IPv4 packets. the Layer 3 Address 1 Register 5 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A15,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg6,For IPv4 packets. the Layer 3 Address 1 Register 6 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A16,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg7,For IPv4 packets. the Layer 3 Address 1 Register 7 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A17,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg8,For IPv4 packets. the Layer 3 Address 1 Register 8 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A18,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg9,For IPv4 packets. the Layer 3 Address 1 Register 9 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A19,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg0,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A20,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg1,The Layer 3 Address 2 Register 1 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A21,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg10,The Layer 3 Address 2 Register 10 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A210,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg11,The Layer 3 Address 2 Register 11 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A211,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg12,The Layer 3 Address 2 Register 12 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A212,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg13,The Layer 3 Address 2 Register 13 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A213,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg14,The Layer 3 Address 2 Register 14 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A214,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg15,The Layer 3 Address 2 Register 15 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A215,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg2,The Layer 3 Address 2 Register 2 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A22,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg3,The Layer 3 Address 2 Register 3 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A23,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg4,The Layer 3 Address 2 Register 4 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A24,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg5,The Layer 3 Address 2 Register 5 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A25,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg6,The Layer 3 Address 2 Register 6 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A26,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg7,The Layer 3 Address 2 Register 7 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A27,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg8,The Layer 3 Address 2 Register 8 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A28,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg9,The Layer 3 Address 2 Register 9 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A29,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg0,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A30,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg1,The Layer 3 Address 3 Register 1 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A31,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg10,The Layer 3 Address 3 Register 10 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A310,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg11,The Layer 3 Address 3 Register 11 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A311,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg12,The Layer 3 Address 3 Register 12 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A312,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg13,The Layer 3 Address 3 Register 13 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A313,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg14,The Layer 3 Address 3 Register 14 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A314,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg15,The Layer 3 Address 3 Register 15 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A315,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg2,The Layer 3 Address 3 Register 2 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A32,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg3,The Layer 3 Address 3 Register 3 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A33,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg4,The Layer 3 Address 3 Register 4 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A34,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg5,The Layer 3 Address 3 Register 5 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A35,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg6,The Layer 3 Address 3 Register 6 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A36,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg7,The Layer 3 Address 3 Register 7 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A37,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg8,The Layer 3 Address 3 Register 8 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A38,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg9,The Layer 3 Address 3 Register 9 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A39,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address0,Layer 4 Address 0 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address1,Layer 4 Address 1 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address10,Layer 4 Address 10 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP10,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP10,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address11,Layer 4 Address 11 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP11,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP11,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address12,Layer 4 Address 12 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP12,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP12,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address13,Layer 4 Address 13 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP13,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP13,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address14,Layer 4 Address 14 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP14,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP14,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address15,Layer 4 Address 15 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP15,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP15,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address2,Layer 4 Address 2 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP2,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP2,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address3,Layer 4 Address 3 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP3,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP3,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address4,Layer 4 Address 4 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP4,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP4,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address5,Layer 4 Address 5 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP5,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP5,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address6,Layer 4 Address 6 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP6,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP6,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address7,Layer 4 Address 7 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP7,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP7,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address8,Layer 4 Address 8 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP8,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP8,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address9,Layer 4 Address 9 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP9,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP9,Layer 4 Source Port Number Field."
group.long 0xC10++0x3
line.long 0x0 "MAC_ARP_Address,The ARP Address register contains the IPv4 Destination Address of the MAC. This register is available only when the Enable IPv4 ARP Offload option is selected."
hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address."
group.long 0xD00++0x7
line.long 0x0 "MAC_Timestamp_Control,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver."
rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "AV8021ASMEN,AV IEEE 802.1AS Mode Enable." "0,1"
newline
rbitfld.long 0x0 25.--27. "Reserved_27_25,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 20. "Reserved_ESTI,Reserved." "0,1"
newline
bitfld.long 0x0 19. "CSC,Enable checksum correction during OST for PTP over UDP/IPv4 packets" "0,1"
newline
bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering." "0,1"
newline
bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots." "0,1,2,3"
newline
bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master." "0,1"
newline
bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages." "0,1"
newline
bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP." "0,1"
newline
bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP." "0,1"
newline
bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets." "0,1"
newline
bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format." "0,1"
newline
bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control." "0,1"
newline
bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets." "0,1"
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 5. "TSADDREG,Update Addend Register." "0,1"
newline
rbitfld.long 0x0 4. "Reserved_TSTRIG,Reserved." "0,1"
newline
bitfld.long 0x0 3. "TSUPDT,Update Timestamp." "0,1"
newline
bitfld.long 0x0 2. "TSINIT,Initialize Timestamp." "0,1"
newline
bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update." "0,1"
newline
bitfld.long 0x0 0. "TSENA,Enable Timestamp." "0,1"
line.long 0x4 "MAC_Sub_Second_Increment,The Sub-Second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in MAC_Timestamp_Control register]. the value in this register.."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value."
newline
hexmask.long.byte 0x4 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value."
newline
hexmask.long.byte 0x4 0.--7. 1. "Reserved_7_0,Reserved."
rgroup.long 0xD08++0x7
line.long 0x0 "MAC_System_Time_Seconds,The System Time-Seconds register. along with System Time-Nanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the actual.."
hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second."
line.long 0x4 "MAC_System_Time_Nanoseconds,The System Time-Nanoseconds register. along with System Time-Seconds register. indicates the current value of the system time maintained by the MAC."
bitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds."
group.long 0xD10++0xF
line.long 0x0 "MAC_System_Time_Seconds_Update,The System Time-Seconds Update register. along with the System Time-Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or.."
hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second."
line.long 0x4 "MAC_System_Time_Nanoseconds_Update,This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input."
bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time." "0,1"
newline
hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds."
line.long 0x8 "MAC_Timestamp_Addend,The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit.."
hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register."
line.long 0xC "MAC_System_Time_Higher_Word_Seconds,The System Time - Higher Word Seconds register is present only when the IEEE 1588 Timestamp feature is selected without an external timestamp input."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "TSHWR,Timestamp Higher Word Register."
rgroup.long 0xD20++0x3
line.long 0x0 "MAC_Timestamp_Status,The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected. All bits except Bits[29:25] gets cleared when the application reads this register."
bitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots."
newline
bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed." "0,1"
newline
hexmask.long.byte 0x0 20.--23. 1. "Reserved_23_20,Reserved."
newline
hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier."
newline
bitfld.long 0x0 15. "TXTSC,Tx Timestamp Captured." "0,1"
newline
hexmask.long.byte 0x0 10.--14. 1. "TTSNS,Number of Tx Timestamp Snapshots."
newline
bitfld.long 0x0 9. "TSTRGTERR3,Timestamp Target Time Error." "0,1"
newline
bitfld.long 0x0 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3." "0,1"
newline
bitfld.long 0x0 7. "TSTRGTERR2,Timestamp Target Time Error." "0,1"
newline
bitfld.long 0x0 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2." "0,1"
newline
bitfld.long 0x0 5. "TSTRGTERR1,Timestamp Target Time Error." "0,1"
newline
bitfld.long 0x0 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1." "0,1"
newline
bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error." "0,1"
newline
bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot." "0,1"
newline
bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached." "0,1"
newline
bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow." "0,1"
rgroup.long 0xD30++0xB
line.long 0x0 "MAC_Tx_Timestamp_Status_Nanoseconds,The MAC_TxTimestamp_Status_Nanoseconds register. along with MAC_TxTimestamp_Status_Seconds. gives the 64-bit timestamp captured for the PTP packet successfully transmitted by the MAC. This value is considered to be.."
bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed." "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low."
line.long 0x4 "MAC_Tx_Timestamp_Status_Seconds,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted."
hexmask.long 0x4 0.--31. 1. "TXTSSTSHI,Transmit Timestamp Status High."
line.long 0x8 "MAC_Tx_Timestamp_Status_PktID,This register contains the PTP packet ID corresponding to the Tx Timestamp Status in MAC_TxTimestamp_Status_Nanoseconds and MAC_TxTimestamp_Status_Seconds registers. This register is available when IEEE 1588 Tx Timestamp.."
hexmask.long.tbyte 0x8 10.--31. 1. "Reserved_31_10,Reserved."
newline
hexmask.long.word 0x8 0.--9. 1. "PKTID,Packet ID."
group.long 0xD40++0x3
line.long 0x0 "MAC_Auxiliary_Control,The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved."
newline
rbitfld.long 0x0 7. "Reserved_ATSEN3,Reserved." "0,1"
newline
rbitfld.long 0x0 6. "Reserved_ATSEN2,Reserved." "0,1"
newline
bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable." "0,1"
newline
bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable." "0,1"
newline
rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear." "0,1"
rgroup.long 0xD48++0x7
line.long 0x0 "MAC_Auxiliary_Timestamp_Nanoseconds,The Auxiliary Timestamp - Nanoseconds register. along with MAC_Auxiliary_Timestamp_Seconds. gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a.."
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp Low. Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp."
line.long 0x4 "MAC_Auxiliary_Timestamp_Seconds,The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register."
hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp High. Contains the lower 32 bits of the Seconds field of the auxiliary timestamp."
group.long 0xD50++0x17
line.long 0x0 "MAC_Timestamp_Ingress_Asym_Corr,The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in some PTP messages."
hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction."
line.long 0x4 "MAC_Timestamp_Egress_Asym_Corr,The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in for some PTP message types."
hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction."
line.long 0x8 "MAC_Timestamp_Ingress_Corr_Nanosecond,The MAC Timestamp Ingress Correction Nanosecond register contains the correction value to be used with the captured timestamp value in the ingress path. This is used to compensate the errors due to timestamp.."
hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction."
line.long 0xC "MAC_Timestamp_Ingress_Corr_Subnanosecond,The MAC Timestamp Ingress Correction Sub-Nanosecond register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for ingress directions."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.byte 0xC 8.--15. 1. "TSICSNS,Timestamp Ingress Correction  sub-nanoseconds."
newline
hexmask.long.byte 0xC 0.--7. 1. "Reserved_7_0,Reserved."
line.long 0x10 "MAC_Timestamp_Egress_Corr_Nanosecond,The MAC Egress Timestamp Correction Nanosecond register contains the correction value to be used with the captured timestamp value in the egress path. This is used to compensate the errors due to timestamp.."
hexmask.long 0x10 0.--31. 1. "TSEC,Timestamp Egress Correction."
line.long 0x14 "MAC_Timestamp_Egress_Corr_Subnanosecond,The MAC Timestamp Correction Egress Sub-nanosecond register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for egress directions."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.byte 0x14 8.--15. 1. "TSECSNS,Timestamp Egress Correction  sub-nanoseconds."
newline
hexmask.long.byte 0x14 0.--7. 1. "Reserved_7_0,Reserved."
group.long 0xD70++0x3
line.long 0x0 "MAC_PPS_Control,The PPS Control register is present only when the Timestamp feature is selected and External Timestamp is not enabled."
rbitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
rbitfld.long 0x0 29.--30. "Reserved_TRGTMODSEL3,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 27.--28. "Reserved_28_27,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 24.--26. "Reserved_PPSCMD3,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1"
newline
rbitfld.long 0x0 21.--22. "Reserved_TRGTMODSEL2,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 19.--20. "Reserved_20_19,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 16.--18. "Reserved_PPSCMD2,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output." "0,1,2,3"
newline
rbitfld.long 0x0 11.--12. "Reserved_12_11,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 8.--10. "PPSCMD1,Flexible PPS1 Output Control." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output." "0: Target Time registers are programmed only for..,1: Reserved,?,?"
newline
bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable." "0,1"
newline
hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL0_PPSCMD0,PPSCMD0: Flexible PPS Output (ptp_pps_o[0]) Control"
group.long 0xD80++0x1F
line.long 0x0 "MAC_PPS0_Target_Time_Seconds,The PPS0 Target Time Seconds register. along with PPS0 Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these.."
hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS0 Target Time Seconds Register."
line.long 0x4 "MAC_PPS0_Target_Time_Nanoseconds,The PPS0 Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected."
bitfld.long 0x4 31. "TRGTBUSY0,PPS0 Target Time Register Busy." "0,1"
newline
hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS0 Register."
line.long 0x8 "MAC_PPS0_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS0 Output Signal Interval."
line.long 0xC "MAC_PPS0_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS0 Output Signal Width."
line.long 0x10 "MAC_PPS1_Target_Time_Seconds,The PPS1 Target Time Seconds register. along with PPS1 Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these.."
hexmask.long 0x10 0.--31. 1. "TSTRH1,PPS1 Target Time Seconds."
line.long 0x14 "MAC_PPS1_Target_Time_Nanoseconds,This register is present only when more than one Flexible PPS output is selected while configuring the controller."
bitfld.long 0x14 31. "TRGTBUSY1,PPS1 Target Time Register Busy." "0,1"
newline
hexmask.long 0x14 0.--30. 1. "TTSL1,Target Time Low for PPS1 Register."
line.long 0x18 "MAC_PPS1_Interval,The PPS1 Interval register contains the number of units of sub-second increment value between the rising edges of PPS1 signal output (ptp_pps_o[1])."
hexmask.long 0x18 0.--31. 1. "PPSINT1,PPS1 Output Signal Interval."
line.long 0x1C "MAC_PPS1_Width,The PPS1 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS1 signal output (ptp_pps_o[1])."
hexmask.long 0x1C 0.--31. 1. "PPSWIDTH1,PPS1 Output Signal Width."
group.long 0xDC0++0x13
line.long 0x0 "MAC_PTO_Control,This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.byte 0x0 8.--15. 1. "DN,Domain Number."
newline
bitfld.long 0x0 7. "PDRDIS,Disable Peer Delay Response response generation" "0,1"
newline
bitfld.long 0x0 6. "DRRDIS,Disable PTO Delay Request/Response response generation." "0,1"
newline
bitfld.long 0x0 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger." "0,1"
newline
bitfld.long 0x0 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger." "0,1"
newline
rbitfld.long 0x0 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x0 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable." "0,1"
newline
bitfld.long 0x0 1. "ASYNCEN,Automatic PTP SYNC message Enable." "0,1"
newline
bitfld.long 0x0 0. "PTOEN,PTP Offload Enable." "0,1"
line.long 0x4 "MAC_Source_Port_Identity0,This register along with MAC_Source_Port_Identity1 and MAC_Source_Port_Identity2 contains the 80-bit Source Port Identity of the PTP node. These registers are available only when the Enable PTP Timestamp Offload feature is.."
hexmask.long 0x4 0.--31. 1. "SPI0,Source Port Identity 0."
line.long 0x8 "MAC_Source_Port_Identity1,This register along with MAC_Source_Port_Identity0 and MAC_Source_Port_Identity2 contains the 80-bit Source Port Identity of the PTP node. These registers are available only when the Enable PTP Timestamp Offload feature is.."
hexmask.long 0x8 0.--31. 1. "SPI1,Source Port Identity 1."
line.long 0xC "MAC_Source_Port_Identity2,This register along with MAC_Source_Port_Identity0 and MAC_Source_Port_Identity1 contains the 80-bit Source Port Identity of the PTP node. These registers are available only when the Enable PTP Timestamp Offload feature is.."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "SPI2,Source Port Identity 2."
line.long 0x10 "MAC_Log_Message_Interval,This register contains the periodic intervals for automatic PTP packet generation. This register is available only when the Enable PTP Timestamp Offload feature is selected."
hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval."
newline
hexmask.long.word 0x10 11.--23. 1. "Reserved_23_11,Reserved."
newline
bitfld.long 0x10 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 0.--7. 1. "LSI,Log Sync Interval."
group.long 0x1000++0x3
line.long 0x0 "MTL_Operation_Mode,The Operation Mode register establishes the Transmit and Receive operating modes and commands."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
bitfld.long 0x0 5.--6. "ETSALG,ETS Algorithm." "0: WRR algorithm,1: WFQ algorithm when Data Center Bridging feature..,2: DWRR algorithm when Data Center Bridging feature..,3: Reserved"
newline
rbitfld.long 0x0 3.--4. "Reserved_4_3,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm." "0: Strict Priority,1: Weighted Strict Priority"
newline
rbitfld.long 0x0 1. "Reserved_FTS,Reserved." "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
group.long 0x1008++0xB
line.long 0x0 "MTL_Debug_Control,The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access."
hexmask.long.word 0x0 19.--31. 1. "Reserved_31_19,Reserved."
newline
rbitfld.long 0x0 18. "Reserved_EIEC,Reserved." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_EIAEE,Reserved." "0,1"
newline
rbitfld.long 0x0 16. "Reserved_EIEE,Reserved." "0,1"
newline
rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 14. "PKTIE,Receive Packet Available Interrupt Status Enable." "0,1"
newline
bitfld.long 0x0 12.--13. "FIFOSEL,FIFO Selected for Access." "0: Tx FIFO,1: Descriptor cache,?,?"
newline
bitfld.long 0x0 11. "FIFOWREN,FIFO Write Enable." "0,1"
newline
bitfld.long 0x0 10. "FIFORDEN,FIFO Read Enable." "0,1"
newline
bitfld.long 0x0 9. "RSTSEL,Reset Pointers of Selected FIFO." "0,1"
newline
bitfld.long 0x0 8. "RSTALL,Reset All Pointers." "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 5.--6. "PKTSTATE,Write Control Type." "0: Packet Data,1: Normal Status,?,?"
newline
rbitfld.long 0x0 4. "Reserved_4,Reserved." "0,1"
newline
bitfld.long 0x0 2.--3. "BYTEEN,Write Data Byte Enable." "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,?,?"
newline
bitfld.long 0x0 1. "DBGMOD,Debug Mode Access to FIFO." "0,1"
newline
bitfld.long 0x0 0. "FDBGEN,FIFO Debug Access Enable." "0,1"
line.long 0x4 "MTL_Debug_Status,The FIFO Debug Status register contains the status of FIFO debug access."
hexmask.long.word 0x4 16.--31. 1. "LOCR,Remaining Locations in the FIFO."
newline
hexmask.long.byte 0x4 9.--15. 1. "Reserved_15_9,Reserved."
newline
bitfld.long 0x4 8. "PKTI,Receive Packet Available Interrupt Status." "0,1"
newline
rbitfld.long 0x4 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 3.--4. "BYTEEN,Read Data Byte Enable." "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,?,?"
newline
rbitfld.long 0x4 1.--2. "PKTSTATE,Read Control Type." "0: Packet Data,1: Normal Status,?,?"
newline
rbitfld.long 0x4 0. "FIFOBUSY,FIFO Busy." "0,1"
line.long 0x8 "MTL_FIFO_Debug_Data,The FIFO Debug Data register contains the data to be written to or read from the FIFOs."
hexmask.long 0x8 0.--31. 1. "FDBGDATA,FIFO Debug Data."
rgroup.long 0x1020++0x3
line.long 0x0 "MTL_Interrupt_Status,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
bitfld.long 0x0 23. "Reserved_MTLPIS,Reserved." "0,1"
newline
bitfld.long 0x0 21.--22. "Reserved_22_21,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 20. "Reserved_SGFIS,Reserved." "0,1"
newline
bitfld.long 0x0 19. "TINS,TBS Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "ESTIS,EST (TAS- IEEE 802.1Qbv) Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "DBGIS,Debug Interrupt Status." "0,1"
newline
bitfld.long 0x0 16. "MACIS,MAC Interrupt Status." "0,1"
newline
bitfld.long 0x0 15. "Q15IS,Queue 15 Interrupt Status." "0,1"
newline
bitfld.long 0x0 14. "Q14IS,Queue 14 Interrupt Status." "0,1"
newline
bitfld.long 0x0 13. "Q13IS,Queue 13 Interrupt Status." "0,1"
newline
bitfld.long 0x0 12. "Q12IS,Queue 12 Interrupt Status." "0,1"
newline
bitfld.long 0x0 11. "Q11IS,Queue 11 Interrupt Status." "0,1"
newline
bitfld.long 0x0 10. "Q10IS,Queue 10 Interrupt Status." "0,1"
newline
bitfld.long 0x0 9. "Q9IS,Queue 9 Interrupt Status." "0,1"
newline
bitfld.long 0x0 8. "Q8IS,Queue 8 Interrupt Status." "0,1"
newline
bitfld.long 0x0 7. "Q7IS,Traffic Class/Queue 7 Interrupt Status." "0,1"
newline
bitfld.long 0x0 6. "Q6IS,Traffic Class/Queue 6 Interrupt Status." "0,1"
newline
bitfld.long 0x0 5. "Q5IS,Traffic Class/Queue 5 Interrupt Status." "0,1"
newline
bitfld.long 0x0 4. "Q4IS,Traffic Class/Queue 4 Interrupt Status." "0,1"
newline
bitfld.long 0x0 3. "Q3IS,Traffic Class/Queue 3 Interrupt Status." "0,1"
newline
bitfld.long 0x0 2. "Q2IS,Traffic Class/Queue 2 Interrupt Status." "0,1"
newline
bitfld.long 0x0 1. "Q1IS,Traffic Class/Queue 1 Interrupt Status." "0,1"
newline
bitfld.long 0x0 0. "Q0IS,Traffic Class/Queue 0 Interrupt Status." "0,1"
group.long 0x1030++0x7
line.long 0x0 "MTL_RxQ_DMA_Map0,The Receive Queue and DMA Channel Mapping 0 register controls the static or dynamic mapping of Receive Queues 0-3 to Receive DMA Channels."
bitfld.long 0x0 31. "Q3DDMACH,Receive Queue 3 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_y,Reserved."
newline
bitfld.long 0x0 24.--26. "Q3MDMACH,Receive Queue 3 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3,4: DMA Channel 4,5: DMA Channel 5,6: DMA Channel 6,7: DMA Channel 7"
newline
bitfld.long 0x0 23. "Q2DDMACH,Receive Queue 2 Enabled for Dynamic MA Channel Selection" "0,1"
newline
hexmask.long.byte 0x0 19.--22. 1. "Reserved_22_y,Reserved."
newline
bitfld.long 0x0 16.--18. "Q2MDMACH,Receive Queue 2 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Q1DDMACH,Receive Queue 1 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q1MDMACH,Receive Queue 1 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7. "Q0DDMACH,Receive Queue 0 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x0 3.--6. 1. "Reserved_6_y,Reserved."
newline
bitfld.long 0x0 0.--2. "Q0MDMACH,Receive Queue 0 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ_DMA_Map1,The Receive Queue and DMA Channel Mapping 1 register controls the static or dynamic mapping of Receive Queues 4-7 to Receive DMA Channels."
bitfld.long 0x4 31. "Q7DDMACH,Receive Queue 7 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x4 27.--30. 1. "Reserved_30_y,Reserved."
newline
bitfld.long 0x4 24.--26. "Q7MDMACH,Receive Queue 7 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 23. "Q6DDMACH,Receive Queue 6 Enabled for Dynamic MA Channel Selection" "0,1"
newline
hexmask.long.byte 0x4 19.--22. 1. "Reserved_22_y,Reserved."
newline
bitfld.long 0x4 16.--18. "Q6MDMACH,Receive Queue 6 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 15. "Q5DDMACH,Receive Queue 5 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x4 11.--14. 1. "Reserved_14_y,Reserved."
newline
bitfld.long 0x4 8.--10. "Q5MDMACH,Receive Queue 5 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 7. "Q4DDMACH,Receive Queue 4 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x4 3.--6. 1. "Reserved_6_y,Reserved."
newline
bitfld.long 0x4 0.--2. "Q4MDMACH,Receive Queue 4 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
group.long 0x1040++0x1B
line.long 0x0 "MTL_TC_Prty_Map0,This register contains the priority values assigned to traffic classes 0 to 3."
hexmask.long.byte 0x0 24.--31. 1. "PSTC3,Priorities Mapped to Traffic Class 3."
newline
hexmask.long.byte 0x0 16.--23. 1. "PSTC2,Priorities Mapped to Traffic Class 2."
newline
hexmask.long.byte 0x0 8.--15. 1. "PSTC1,Priorities Mapped to Traffic Class 1."
newline
hexmask.long.byte 0x0 0.--7. 1. "PSTC0,Priorities Mapped to Traffic Class 0."
line.long 0x4 "MTL_TC_Prty_Map1,This register contains the priority values assigned to traffic classes 4 to 7."
hexmask.long.byte 0x4 24.--31. 1. "PSTC7,Priorities Mapped to Traffic Class 7."
newline
hexmask.long.byte 0x4 16.--23. 1. "PSTC6,Priorities Mapped to Traffic Class 6."
newline
hexmask.long.byte 0x4 8.--15. 1. "PSTC5,Priorities Mapped to Traffic Class 5."
newline
hexmask.long.byte 0x4 0.--7. 1. "PSTC4,Priorities Mapped to Traffic Class 4."
line.long 0x8 "MTL_TBS_CTRL,This register controls the operation of Time Based Scheduling."
hexmask.long.tbyte 0x8 8.--31. 1. "LEOS,Launch Expiry Offset"
newline
rbitfld.long 0x8 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x8 4.--6. "LEGOS,Launch Expiry GSN Offset" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x8 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x8 2. "TIEN,TBS Interrupt Enable" "0,1"
newline
bitfld.long 0x8 1. "LEOV,Launch Expiry Offset Valid" "0,1"
newline
bitfld.long 0x8 0. "ESTM,EST offset Mode" "0,1"
line.long 0xC "MTL_TBS_STATS,This register provides the One Hot encoded Queue numbers that have the frame drop related error"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "EDQN,Expiry drop Queue number"
line.long 0x10 "MTL_EST_Control,This register controls the operation of Enhancements to Scheduled Transmission (IEEE 802.1Qbv)."
hexmask.long.word 0x10 23.--31. 1. "PTOV,PTP Time Offset Value"
newline
hexmask.long.word 0x10 11.--22. 1. "CTOV,Current Time Offset Value"
newline
bitfld.long 0x10 8.--10. "TILS,Time Interval Left Shift Amount" "0: No left shift needed,1: Left shift TI by 1 bit,?,?,?,?,?,?"
newline
bitfld.long 0x10 6.--7. "LCSE,Loop Count to report Scheduling Error" "0,1,2,3"
newline
bitfld.long 0x10 5. "DFBS,Drop Frames causing Scheduling Error" "0,1"
newline
bitfld.long 0x10 4. "DDBF,Do not Drop frames during Frame Size Error" "0,1"
newline
bitfld.long 0x10 3. "QHLBF,Quick Assertion of HLBF Error" "0,1"
newline
rbitfld.long 0x10 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x10 1. "SSWL,Switch to software owned list" "0,1"
newline
bitfld.long 0x10 0. "EEST,Enable EST" "0,1"
line.long 0x14 "MTL_EST_Overhead,This register indicates the value of Overhead."
hexmask.long.word 0x14 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.byte 0x14 16.--20. 1. "Reserved_ABYT,Reserved."
newline
hexmask.long.byte 0x14 8.--15. 1. "Reserved_15_8,Reserved."
newline
hexmask.long.byte 0x14 0.--7. 1. "OVHD,Overhead Bytes Value"
line.long 0x18 "MTL_EST_Status,This register provides Status related to Enhancements to Scheduled Transmission (IEEE 802.1Qbv)."
hexmask.long.word 0x18 20.--31. 1. "Reserved_31_20,Reserved."
newline
hexmask.long.byte 0x18 16.--19. 1. "CGSN,Current GCL Slot Number."
newline
hexmask.long.byte 0x18 8.--15. 1. "BTRL,BTR Error Loop Count"
newline
rbitfld.long 0x18 7. "SWOL,Software Owned List" "0,1"
newline
rbitfld.long 0x18 5.--6. "Reserved_6_5,Reserved." "0,1,2,3"
newline
bitfld.long 0x18 4. "CGCE,Constant Gate Control Error" "0,1"
newline
rbitfld.long 0x18 3. "HLBS,Head-Of-Line Blocking due to Scheduling" "0,1"
newline
rbitfld.long 0x18 2. "HLBF,Head-Of-Line Blocking due to Frame Size" "0,1"
newline
bitfld.long 0x18 1. "BTRE,BTR Error" "0,1"
newline
bitfld.long 0x18 0. "SWLC,Switch to Software Owned List Complete" "0,1"
group.long 0x1060++0x7
line.long 0x0 "MTL_EST_Sch_Error,This register provides the One Hot encoded Queue numbers that have the scheduling related error (timeout)."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "SETN,Schedule Error TC Number"
line.long 0x4 "MTL_EST_Frm_Size_Error,This register provides the One Hot encoded Queue numbers that have the Frame Size related error."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "FETN,Frame Size Error TC Number"
rgroup.long 0x1068++0x3
line.long 0x0 "MTL_EST_Frm_Size_Capture,This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error. Upon clearing. this register captures the data of the next occurrence of a similar error."
hexmask.long.word 0x0 19.--31. 1. "Reserved_31_x,Reserved."
newline
bitfld.long 0x0 16.--18. "HBFQ,Queue Number of HLBF" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF"
group.long 0x1070++0x3
line.long 0x0 "MTL_EST_Intr_Enable,This register implements the Interrupt Enable bits for the various events that generate an interrupt. Bit positions have a 1- to-1 correspondence with the status bit positions in MTL_EST_Status register."
hexmask.long 0x0 5.--31. 1. "Reserved_31_5,Reserved."
newline
bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE" "0,1"
newline
bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS" "0,1"
newline
bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF" "0,1"
newline
bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error" "0,1"
newline
bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List" "0,1"
group.long 0x1080++0x7
line.long 0x0 "MTL_GCL_Control,This register provides the control information for reading/writing to the Gate Control lists."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
rbitfld.long 0x0 23. "GCLEIEC,ECC Inject Error Control for GCL Memory" "0,1"
newline
rbitfld.long 0x0 22. "GCLEIAEE,GCL ECC Inject Address Error Enable" "0,1"
newline
rbitfld.long 0x0 21. "GCLEIEE,GCL ECC Inject Error Enable" "0,1"
newline
hexmask.long.byte 0x0 16.--20. 1. "Reserved_20_y,Reserved."
newline
hexmask.long.byte 0x0 8.--15. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is 0)."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select" "0,1"
newline
bitfld.long 0x0 4. "DBGM,Debug Mode" "0,1"
newline
rbitfld.long 0x0 3. "Reserved_GCLS,Reserved." "0,1"
newline
bitfld.long 0x0 2. "GCRR,Gate Control Related Registers" "0,1"
newline
bitfld.long 0x0 1. "R1W0,Read 1  Write 0:" "0: Write Operation,1: Read Operation"
newline
bitfld.long 0x0 0. "SRWO,Start Read/Write Op" "0,1"
line.long 0x4 "MTL_GCL_Data,This register holds the read data or write data in case of reads and writes respectively."
hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data"
group.long 0x1090++0x7
line.long 0x0 "MTL_FPE_CTRL_STS,This register controls the operation of. and provides status for Frame Preemption (IEEE 802.1Qbu/802.3br)."
rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was last.."
newline
hexmask.long.word 0x0 17.--27. 1. "Reserved_27_17,Reserved."
newline
bitfld.long 0x0 16. "PHRSC,Preemption MAC Hold/Release Sideband Control Select" "0: Indicates that Set-Hold-and-Release-MAC..,1: Indicates that Set-Hold-and-Release-MAC.."
newline
hexmask.long.byte 0x0 8.--15. 1. "PEC,Preemption Classification"
newline
bitfld.long 0x0 7. "LBHT,Level Based Hold Transition" "0,1"
newline
hexmask.long.byte 0x0 2.--6. 1. "Reserved_6_2,Reserved."
newline
bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size" "0,1,2,3"
line.long 0x4 "MTL_FPE_Advance,This register holds the Hold and Release Advance time."
hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance"
newline
hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance"
group.long 0x1100++0x3
line.long 0x0 "MTL_TxQ0_Operation_Mode,The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1104++0x7
line.long 0x0 "MTL_TxQ0_Underflow,The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ0_Debug,The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 0 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1110++0x3
line.long 0x0 "MTL_TC0_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1114++0x3
line.long 0x0 "MTL_TC0_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1118++0x3
line.long 0x0 "MTL_TC0_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1140++0x3
line.long 0x0 "MTL_RxQ0_Operation_Mode,The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1144++0x7
line.long 0x0 "MTL_RxQ0_Missed_Pkt_Overflow_Cnt,The Queue 0 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ0_Debug,The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x114C++0x7
line.long 0x0 "MTL_RxQ0_Control,The Queue 0 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ0_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1170++0x7
line.long 0x0 "MTL_Q0_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 0."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q0_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 0."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1180++0x3
line.long 0x0 "MTL_TxQ1_Operation_Mode,The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1184++0x7
line.long 0x0 "MTL_TxQ1_Underflow,The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ1_Debug,The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 1 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1190++0x3
line.long 0x0 "MTL_TC1_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1194++0x3
line.long 0x0 "MTL_TC1_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1198++0x3
line.long 0x0 "MTL_TC1_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x11C0++0x3
line.long 0x0 "MTL_RxQ1_Operation_Mode,The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x11C4++0x7
line.long 0x0 "MTL_RxQ1_Missed_Pkt_Overflow_Cnt,The Queue 1 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ1_Debug,The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x11CC++0x7
line.long 0x0 "MTL_RxQ1_Control,The Queue 1 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ1_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x11F0++0x7
line.long 0x0 "MTL_Q1_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 1."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q1_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 1."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1200++0x3
line.long 0x0 "MTL_TxQ2_Operation_Mode,The Queue 2 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1204++0x7
line.long 0x0 "MTL_TxQ2_Underflow,The Queue 2 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ2_Debug,The Queue 2 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 2 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1210++0x3
line.long 0x0 "MTL_TC2_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1214++0x3
line.long 0x0 "MTL_TC2_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1218++0x3
line.long 0x0 "MTL_TC2_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1240++0x3
line.long 0x0 "MTL_RxQ2_Operation_Mode,The Queue 2 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1244++0x7
line.long 0x0 "MTL_RxQ2_Missed_Pkt_Overflow_Cnt,The Queue 2 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ2_Debug,The Queue 2 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x124C++0x7
line.long 0x0 "MTL_RxQ2_Control,The Queue 2 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ2_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1270++0x7
line.long 0x0 "MTL_Q2_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 2."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q2_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 2."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1280++0x3
line.long 0x0 "MTL_TxQ3_Operation_Mode,The Queue 3 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1284++0x7
line.long 0x0 "MTL_TxQ3_Underflow,The Queue 3 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ3_Debug,The Queue 3 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 3 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1290++0x3
line.long 0x0 "MTL_TC3_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1294++0x3
line.long 0x0 "MTL_TC3_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1298++0x3
line.long 0x0 "MTL_TC3_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x12C0++0x3
line.long 0x0 "MTL_RxQ3_Operation_Mode,The Queue 3 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x12C4++0x7
line.long 0x0 "MTL_RxQ3_Missed_Pkt_Overflow_Cnt,The Queue 3 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ3_Debug,The Queue 3 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x12CC++0x7
line.long 0x0 "MTL_RxQ3_Control,The Queue 3 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ3_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x12F0++0x7
line.long 0x0 "MTL_Q3_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 3."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q3_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 3."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1300++0x3
line.long 0x0 "MTL_TxQ4_Operation_Mode,The Queue 4 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1304++0x7
line.long 0x0 "MTL_TxQ4_Underflow,The Queue 4 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ4_Debug,The Queue 4 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 4 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1310++0x3
line.long 0x0 "MTL_TC4_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1314++0x3
line.long 0x0 "MTL_TC4_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1318++0x3
line.long 0x0 "MTL_TC4_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1340++0x3
line.long 0x0 "MTL_RxQ4_Operation_Mode,The Queue 4 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1344++0x7
line.long 0x0 "MTL_RxQ4_Missed_Pkt_Overflow_Cnt,The Queue 4 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ4_Debug,The Queue 4 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x134C++0x7
line.long 0x0 "MTL_RxQ4_Control,The Queue 4 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ4_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1370++0x7
line.long 0x0 "MTL_Q4_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 4."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q4_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 4."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1380++0x3
line.long 0x0 "MTL_TxQ5_Operation_Mode,The Queue 5 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1384++0x7
line.long 0x0 "MTL_TxQ5_Underflow,The Queue 5 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ5_Debug,The Queue 5 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 5 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1390++0x3
line.long 0x0 "MTL_TC5_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1394++0x3
line.long 0x0 "MTL_TC5_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1398++0x3
line.long 0x0 "MTL_TC5_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x13C0++0x3
line.long 0x0 "MTL_RxQ5_Operation_Mode,The Queue 5 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x13C4++0x7
line.long 0x0 "MTL_RxQ5_Missed_Pkt_Overflow_Cnt,The Queue 5 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ5_Debug,The Queue 5 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x13CC++0x7
line.long 0x0 "MTL_RxQ5_Control,The Queue 5 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ5_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x13F0++0x7
line.long 0x0 "MTL_Q5_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 5."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q5_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 5."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1400++0x3
line.long 0x0 "MTL_TxQ6_Operation_Mode,The Queue 6 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1404++0x7
line.long 0x0 "MTL_TxQ6_Underflow,The Queue 6 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ6_Debug,The Queue 6 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 6 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1410++0x3
line.long 0x0 "MTL_TC6_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1414++0x3
line.long 0x0 "MTL_TC6_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1418++0x3
line.long 0x0 "MTL_TC6_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1440++0x3
line.long 0x0 "MTL_RxQ6_Operation_Mode,The Queue 6 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1444++0x7
line.long 0x0 "MTL_RxQ6_Missed_Pkt_Overflow_Cnt,The Queue 6 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ6_Debug,The Queue 6 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x144C++0x7
line.long 0x0 "MTL_RxQ6_Control,The Queue 6 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ6_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1470++0x7
line.long 0x0 "MTL_Q6_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 6."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q6_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 6."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1480++0x3
line.long 0x0 "MTL_TxQ7_Operation_Mode,The Queue 7 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1484++0x7
line.long 0x0 "MTL_TxQ7_Underflow,The Queue 7 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ7_Debug,The Queue 7 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 7 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1490++0x3
line.long 0x0 "MTL_TC7_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
bitfld.long 0x0 4.--6. "SLC,Slot Count." "0: 1 Slot,1: 2 Slots,2: 4 Slots,3: 8 Slots,4: 16 Slots,?,?,?"
newline
bitfld.long 0x0 3. "CC,Credit Control." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1494++0x3
line.long 0x0 "MTL_TC7_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1498++0xF
line.long 0x0 "MTL_TC7_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
line.long 0x4 "MTL_TC7_SendSlopeCredit,MTL registers for traffic classes and queues 1 registers."
hexmask.long.word 0x4 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "SSC,sendSlopeCredit Value."
line.long 0x8 "MTL_TC7_HiCredit,This register contains the hiCredit value required for the credit-based shaper algorithm for TC1.."
rbitfld.long 0x8 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value."
line.long 0xC "MTL_TC7_LoCredit,This register contains the loCredit value required for the credit-based shaper algorithm for TC1."
rbitfld.long 0xC 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long 0xC 0.--28. 1. "LC,loCredit Value."
group.long 0x14C0++0x3
line.long 0x0 "MTL_RxQ7_Operation_Mode,The Queue 7 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x14C4++0x7
line.long 0x0 "MTL_RxQ7_Missed_Pkt_Overflow_Cnt,The Queue 7 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ7_Debug,The Queue 7 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x14CC++0x7
line.long 0x0 "MTL_RxQ7_Control,The Queue 7 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ7_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x14F0++0x7
line.long 0x0 "MTL_Q7_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 7."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q7_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 7."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x3000++0x7
line.long 0x0 "DMA_Mode,The Bus Mode register establishes the bus operating modes for the DMA."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
newline
bitfld.long 0x0 12.--13. "INTM,Interrupt Mode." "0: sbd_perch_* are pulse signals for each..,1: sbd_perch_* are level signals asserted on the..,?,?"
newline
rbitfld.long 0x0 9.--11. "Reserved_11_9,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "DSPW,Descriptor Posted Write." "0: By default,1: All Rx DMA data and descriptor writes are posted.."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 5. "Reserved_TMRP,Reserved." "0,1"
newline
bitfld.long 0x0 4. "TDRP,Tx Descriptor Read Priority." "0,1"
newline
rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "SWR,Software Reset." "0,1"
line.long 0x4 "DMA_SysBus_Mode,The System Bus mode register controls the behavior of the AXI master. It mainly controls burst splitting and number of outstanding requests."
rbitfld.long 0x4 29.--31. "Reserved_31_30,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 24.--28. 1. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit."
newline
rbitfld.long 0x4 21.--23. "Reserved_23_22,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 16.--20. 1. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit."
newline
bitfld.long 0x4 15. "EN_LPI,Enable Low Power Interface (LPI)." "0: Disables the LPI mode and always denies the LPI..,1: Enables the LPI mode supported by the AXI.."
newline
bitfld.long 0x4 14. "LPI_XIT_PKT,Unlock on Magic Packet or Remote Wake-Up Packet." "0: Enables the AXI master to come out of the LPI..,1: Enables the AXI master to come out of the LPI.."
newline
bitfld.long 0x4 13. "ONEKBBE,1 KB Boundary Crossing Enable for the AXI Master." "0: The burst transfers performed by the AXI master..,1: The burst transfers performed by the AXI master.."
newline
bitfld.long 0x4 12. "AAL,Address-Aligned Beats." "0,1"
newline
bitfld.long 0x4 11. "EAME,Enhanced Address Mode Enable." "?,1: DMA master enables the enhanced address mode"
newline
bitfld.long 0x4 10. "AALE,Automatic AXI LPI enable." "?,1: Enables the AXI master to enter into LPI state.."
newline
rbitfld.long 0x4 8.--9. "Reserved_9_8,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 7. "BLEN256,AXI Burst Length 256." "0,1"
newline
bitfld.long 0x4 6. "BLEN128,AXI Burst Length 128." "0,1"
newline
bitfld.long 0x4 5. "BLEN64,AXI Burst Length 64." "0,1"
newline
bitfld.long 0x4 4. "BLEN32,AXI Burst Length 32." "0,1"
newline
bitfld.long 0x4 3. "BLEN16,AXI Burst Length 16." "0,1"
newline
bitfld.long 0x4 2. "BLEN8,AXI Burst Length 8." "0,1"
newline
bitfld.long 0x4 1. "BLEN4,AXI Burst Length 4." "0,1"
newline
bitfld.long 0x4 0. "UBL,AXI Undefined Burst Length." "0: The AXI master performs one of the following..,1: The AXI master can perform burst transfers that.."
rgroup.long 0x3008++0x3
line.long 0x0 "DMA_Interrupt_Status,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels. MTL queues. and the MAC."
hexmask.long.word 0x0 18.--31. 1. "Reserved_31_18,Reserved."
newline
bitfld.long 0x0 17. "MACIS,MAC Interrupt Status." "0,1"
newline
bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status." "0,1"
newline
hexmask.long.byte 0x0 8.--15. 1. "DC15TC8IS,DMA Channel 15 Interrupt Status to DMA Channel 8 Interrupt Status."
newline
bitfld.long 0x0 7. "DC7IS,DMA Channel 7 Interrupt Status." "0,1"
newline
bitfld.long 0x0 6. "DC6IS,DMA Channel 6 Interrupt Status." "0,1"
newline
bitfld.long 0x0 5. "DC5IS,DMA Channel 5 Interrupt Status." "0,1"
newline
bitfld.long 0x0 4. "DC4IS,DMA Channel 4 Interrupt Status." "0,1"
newline
bitfld.long 0x0 3. "DC3IS,DMA Channel 3 Interrupt Status." "0,1"
newline
bitfld.long 0x0 2. "DC2IS,DMA Channel 2 Interrupt Status." "0,1"
newline
bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status." "0,1"
newline
bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status." "0,1"
group.long 0x3010++0x3
line.long 0x0 "AXI_Tx_AR_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for read transactions by all the Transmit DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding.."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 20.--21. "THD,Transmit DMA First Packet Buffer or TSO Header Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "THC,Transmit DMA First Packet Buffer or TSO Header Cache Control."
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "TED,Transmit DMA Extended Packet Buffer or TSO Payload Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 8.--11. 1. "TEC,Transmit DMA Extended Packet Buffer or TSO Payload Cache Control."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "TDRD,Transmit DMA Read Descriptor Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "TDRC,Transmit DMA Read Descriptor Cache Control."
group.long 0x3018++0x7
line.long 0x0 "AXI_Rx_AW_ACE_Control,This register is used to control the Cache Coherency Signals of the AXI4-ACE Lite on the Receive DMA. The programmable controllability is supported on the following signals of the AXI Write channel."
rbitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RDD,Receive DMA Buffer Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--27. 1. "RDC,Receive DMA Buffer Cache Control."
newline
rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RHD,Receive DMA Header Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "RHC,Receive DMA Header Cache Control."
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RPD,Receive DMA Payload Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 8.--11. 1. "RPC,Receive DMA Payload Cache Control."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RDWD,Receive DMA Write Descriptor Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "RDWC,Receive DMA Write Descriptor Cache Control."
line.long 0x4 "AXI_TxRx_AWAR_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for Descriptor write transactions by all the TxDMA channels and Descriptor read transactions by all the RxDMA channels. It also controls the values to be driven.."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_23,Reserved."
newline
bitfld.long 0x4 20.--22. "WRP,DMA Write Protection control." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 19. "Reserved_19,Reserved." "0,1"
newline
bitfld.long 0x4 16.--18. "RDP,DMA Read Protection control." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "RDRD,Receive DMA Read Descriptor Domain control." "0,1,2,3"
newline
hexmask.long.byte 0x4 8.--11. 1. "RDRC,Receive DMA Read Descriptor Cache control."
newline
rbitfld.long 0x4 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control." "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--3. 1. "TDWC,Transmit DMA Write Descriptor Cache control."
rgroup.long 0x3020++0x7
line.long 0x0 "DMA_Debug_Status0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0 - Channel 2 for debugging purpose."
hexmask.long.byte 0x0 28.--31. 1. "TPS2,DMA Channel 2 Transmit Process State."
newline
hexmask.long.byte 0x0 24.--27. 1. "RPS2,DMA Channel 2 Receive Process State."
newline
hexmask.long.byte 0x0 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State."
newline
hexmask.long.byte 0x0 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State."
newline
hexmask.long.byte 0x0 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State."
newline
hexmask.long.byte 0x0 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State."
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved."
newline
bitfld.long 0x0 1. "AXRHSTS,AXI Master Read Channel Status." "0,1"
newline
bitfld.long 0x0 0. "AXWHSTS,AXI Master Write Channel Status." "?,1: Indicates that the write channel of the AXI.."
line.long 0x4 "DMA_Debug_Status1,The Debug Status1 register gives the per Transmit DMA active status."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "TDAS,Transmit DMA Active Status."
rgroup.long 0x302C++0x3
line.long 0x0 "DMA_Debug_Status3,The Debug Status3 register gives the per Receive DMA active status."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "RDAS,Receive DMA Active Status."
group.long 0x3040++0x7
line.long 0x0 "DMA_Tx_EDMA_Control,The DMA_Tx_EDMA_Control register controls the sequence of all TxDMA operations with the DMA engine."
bitfld.long 0x0 30.--31. "TEDM,Tx DMA Mode." "0: Default mode of DMA,1: The value of TDPS field is ignored and only one..,2: The value of TDPS field is ignored and only one..,3: All operations are sequential"
newline
hexmask.long 0x0 2.--29. 1. "Reserved_29_y,Reserved."
newline
bitfld.long 0x0 0.--1. "TDPS,Tx Descriptor Pre-fetch threshold Size." "0: Threshold of 0 descriptors,1: Threshold is 4 descriptors,2: Threshold is 8 descriptors,3: Threshold is 12 descriptors"
line.long 0x4 "DMA_Rx_EDMA_Control,The DMA_Rx_EDMA_Control register controls the sequence of all RxDMA operations with the DMA engine."
bitfld.long 0x4 30.--31. "REDM,Rx DMA Mode." "0: Default mode of DMA as explained in section 2,1: The value of RDPS field is ignored and only 1..,2: The value of RDPS field is ignored and only 1..,3: All operations are sequential"
newline
hexmask.long 0x4 2.--29. 1. "Reserved_29_y,Reserved."
newline
bitfld.long 0x4 0.--1. "RDPS,Rx Descriptor Pre-Fetch Threshold Size." "0: Threshold of 0 descriptors,1: Threshold is 4 descriptors,2: Threshold is 8 descriptors,3: Threshold is 12 descriptors"
group.long 0x3050++0x13
line.long 0x0 "AXI_LPI_Entry_Interval,This register is used to control the AXI LPI entry interval."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
hexmask.long.byte 0x0 0.--3. 1. "LPIEI,LPI Entry Interval"
line.long 0x4 "DMA_TBS_CTRL0,This register is used to control the TBS0 attributes."
hexmask.long.tbyte 0x4 8.--31. 1. "FTOS,Fetch Time Offset 0"
newline
rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x4 4.--6. "FGOS,Fetch GSN Offset 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "FTOV,Fetch Time Offset 0 Valid" "0,1"
line.long 0x8 "DMA_TBS_CTRL1,This register is used to control the TBS1 attributes."
hexmask.long.tbyte 0x8 8.--31. 1. "FTOS,Fetch Time Offset 1"
newline
rbitfld.long 0x8 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x8 4.--6. "FGOS,Fetch GSN Offset 1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x8 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "FTOV,Fetch Time Offset 1 Valid" "0,1"
line.long 0xC "DMA_TBS_CTRL2,This register is used to control the TBS2 attributes."
hexmask.long.tbyte 0xC 8.--31. 1. "FTOS,Fetch Time Offset 2"
newline
rbitfld.long 0xC 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0xC 4.--6. "FGOS,Fetch GSN Offset 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0xC 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 0. "FTOV,Fetch Time Offset 2 Valid" "0,1"
line.long 0x10 "DMA_TBS_CTRL3,This register is used to control the TBS3 attributes."
hexmask.long.tbyte 0x10 8.--31. 1. "FTOS,Fetch Time Offset 3"
newline
rbitfld.long 0x10 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x10 4.--6. "FGOS,Fetch GSN Offset 3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "FTOV,Fetch Time Offset 3 Valid" "0,1"
group.long 0x3080++0x7
line.long 0x0 "DMA_CH_Ind_Ctrl,This register is used to program Indirect Access DMA configuration registers"
hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved."
newline
hexmask.long.byte 0x0 16.--19. 1. "MSEL,Mode Select"
newline
hexmask.long.byte 0x0 12.--15. 1. "Reserved_15_12,Reserved."
newline
hexmask.long.byte 0x0 8.--11. 1. "AOFF,Address Offset"
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "AUTO,Auto Increment" "0: No auto increment,1: Auto increment MSEL only,?,?"
newline
rbitfld.long 0x0 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 1. "CT,Command Type" "0: Indicates a write operation,1: Indicates a read operation"
newline
bitfld.long 0x0 0. "OB,Operation Busy" "0,1"
line.long 0x4 "DMA_CH_Ind_Data,This register holds the read/write data for Indirect Access of the registers indicated by DMA_<MSEL>_<AOFF>. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field.."
hexmask.long 0x4 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH0_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH1_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH2_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH3_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH4_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH5_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH6_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH7_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3100++0x1F
line.long 0x0 "DMA_CH0_Control,The DMA Channel0 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH0_Tx_Control,The DMA Channel0 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH0_Rx_Control,The DMA Channel0 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel0 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH0_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH0_TxDesc_List_HAddress,The Channel0 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH0_TxDesc_List_LAddress,The Channel0 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH0_RxDesc_List_HAddress,The Channel0 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH0_RxDesc_List_LAddress,The Channel0 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3124++0x3
line.long 0x0 "DMA_CH0_TxDesc_Tail_LPointer,The Channel0 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x312C++0x13
line.long 0x0 "DMA_CH0_RxDesc_Tail_LPointer,The Channel0 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH0_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH0_Rx_Control2,The Channel0 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH0_Interrupt_Enable,The Channel0 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH0_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3144++0x3
line.long 0x0 "DMA_CH0_Current_App_TxDesc_L,The Channel0 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x314C++0x13
line.long 0x0 "DMA_CH0_Current_App_RxDesc_L,The Channel0 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH0_Current_App_TxBuffer_H,The Channel0 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH0_Current_App_TxBuffer_L,The Channel0 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH0_Current_App_RxBuffer_H,The Channel0 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH0_Current_App_RxBuffer_L,The Channel0 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3160++0x3
line.long 0x0 "DMA_CH0_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3164++0x1B
line.long 0x0 "DMA_CH0_Debug_Status,DMA Channe0 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH0_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH0_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH0_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH0_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH0_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH0_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH0_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3180++0x1F
line.long 0x0 "DMA_CH1_Control,The DMA Channel1 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH1_Tx_Control,The DMA Channel1 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH1_Rx_Control,The DMA Channel1 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel1 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH1_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH1_TxDesc_List_HAddress,The Channel1 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH1_TxDesc_List_LAddress,The Channel1 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH1_RxDesc_List_HAddress,The Channel1 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH1_RxDesc_List_LAddress,The Channel1 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x31A4++0x3
line.long 0x0 "DMA_CH1_TxDesc_Tail_LPointer,The Channel1 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x31AC++0x13
line.long 0x0 "DMA_CH1_RxDesc_Tail_LPointer,The Channel1 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH1_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH1_Rx_Control2,The Channel1 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH1_Interrupt_Enable,The Channel1 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH1_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x31C4++0x3
line.long 0x0 "DMA_CH1_Current_App_TxDesc_L,The Channel1 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x31CC++0x13
line.long 0x0 "DMA_CH1_Current_App_RxDesc_L,The Channel1 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH1_Current_App_TxBuffer_H,The Channel1 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH1_Current_App_TxBuffer_L,The Channel1 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH1_Current_App_RxBuffer_H,The Channel1 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH1_Current_App_RxBuffer_L,The Channel1 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x31E0++0x3
line.long 0x0 "DMA_CH1_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x31E4++0x1B
line.long 0x0 "DMA_CH1_Debug_Status,DMA Channe1 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH1_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH1_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH1_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH1_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH1_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH1_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH1_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3200++0x1F
line.long 0x0 "DMA_CH2_Control,The DMA Channel2 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
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bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH2_Tx_Control,The DMA Channel2 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH2_Rx_Control,The DMA Channel2 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel2 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH2_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH2_TxDesc_List_HAddress,The Channel2 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH2_TxDesc_List_LAddress,The Channel2 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH2_RxDesc_List_HAddress,The Channel2 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH2_RxDesc_List_LAddress,The Channel2 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3224++0x3
line.long 0x0 "DMA_CH2_TxDesc_Tail_LPointer,The Channel2 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x322C++0x13
line.long 0x0 "DMA_CH2_RxDesc_Tail_LPointer,The Channel2 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH2_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH2_Rx_Control2,The Channel2 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH2_Interrupt_Enable,The Channel2 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH2_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3244++0x3
line.long 0x0 "DMA_CH2_Current_App_TxDesc_L,The Channel2 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x324C++0x13
line.long 0x0 "DMA_CH2_Current_App_RxDesc_L,The Channel2 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH2_Current_App_TxBuffer_H,The Channel2 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH2_Current_App_TxBuffer_L,The Channel2 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH2_Current_App_RxBuffer_H,The Channel2 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH2_Current_App_RxBuffer_L,The Channel2 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3260++0x3
line.long 0x0 "DMA_CH2_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3264++0x1B
line.long 0x0 "DMA_CH2_Debug_Status,DMA Channe2 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH2_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH2_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH2_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH2_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH2_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH2_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH2_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3280++0x1F
line.long 0x0 "DMA_CH3_Control,The DMA Channel3 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH3_Tx_Control,The DMA Channel3 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH3_Rx_Control,The DMA Channel3 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel3 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH3_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH3_TxDesc_List_HAddress,The Channel3 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH3_TxDesc_List_LAddress,The Channel3 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH3_RxDesc_List_HAddress,The Channel3 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH3_RxDesc_List_LAddress,The Channel3 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x32A4++0x3
line.long 0x0 "DMA_CH3_TxDesc_Tail_LPointer,The Channel3 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
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rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x32AC++0x13
line.long 0x0 "DMA_CH3_RxDesc_Tail_LPointer,The Channel3 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
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rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH3_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
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bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
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hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH3_Rx_Control2,The Channel3 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
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bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
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rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH3_Interrupt_Enable,The Channel3 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
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bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
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bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
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bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
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rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
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bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
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bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
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rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
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bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH3_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
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hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
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hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
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rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x32C4++0x3
line.long 0x0 "DMA_CH3_Current_App_TxDesc_L,The Channel3 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x32CC++0x13
line.long 0x0 "DMA_CH3_Current_App_RxDesc_L,The Channel3 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH3_Current_App_TxBuffer_H,The Channel3 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH3_Current_App_TxBuffer_L,The Channel3 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH3_Current_App_RxBuffer_H,The Channel3 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH3_Current_App_RxBuffer_L,The Channel3 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x32E0++0x3
line.long 0x0 "DMA_CH3_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
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bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
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bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
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bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
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bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
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bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
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bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
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rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
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bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
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bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
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bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
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rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
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bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
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bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x32E4++0x1B
line.long 0x0 "DMA_CH3_Debug_Status,DMA Channe3 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
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bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
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bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
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bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
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bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH3_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
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hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
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hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH3_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH3_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
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hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
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hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH3_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH3_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH3_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH3_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3300++0x1F
line.long 0x0 "DMA_CH4_Control,The DMA Channel4 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
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bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
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rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
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bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
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rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH4_Tx_Control,The DMA Channel4 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
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rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
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rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
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rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
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hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
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rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH4_Rx_Control,The DMA Channel4 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel4 Packet Flush." "0,1"
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rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
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rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
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hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
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rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH4_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
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hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
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bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
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bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH4_TxDesc_List_HAddress,The Channel4 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH4_TxDesc_List_LAddress,The Channel4 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
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rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH4_RxDesc_List_HAddress,The Channel4 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH4_RxDesc_List_LAddress,The Channel4 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3324++0x3
line.long 0x0 "DMA_CH4_TxDesc_Tail_LPointer,The Channel4 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x332C++0x13
line.long 0x0 "DMA_CH4_RxDesc_Tail_LPointer,The Channel4 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH4_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH4_Rx_Control2,The Channel4 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH4_Interrupt_Enable,The Channel4 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
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bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH4_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3344++0x3
line.long 0x0 "DMA_CH4_Current_App_TxDesc_L,The Channel4 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x334C++0x13
line.long 0x0 "DMA_CH4_Current_App_RxDesc_L,The Channel4 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH4_Current_App_TxBuffer_H,The Channel4 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH4_Current_App_TxBuffer_L,The Channel4 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH4_Current_App_RxBuffer_H,The Channel4 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH4_Current_App_RxBuffer_L,The Channel4 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3360++0x3
line.long 0x0 "DMA_CH4_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3364++0x1B
line.long 0x0 "DMA_CH4_Debug_Status,DMA Channe4 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH4_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH4_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH4_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH4_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH4_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH4_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH4_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3380++0x1F
line.long 0x0 "DMA_CH5_Control,The DMA Channel5 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH5_Tx_Control,The DMA Channel5 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH5_Rx_Control,The DMA Channel5 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel5 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH5_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH5_TxDesc_List_HAddress,The Channel5 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH5_TxDesc_List_LAddress,The Channel5 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH5_RxDesc_List_HAddress,The Channel5 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH5_RxDesc_List_LAddress,The Channel5 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x33A4++0x3
line.long 0x0 "DMA_CH5_TxDesc_Tail_LPointer,The Channel5 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x33AC++0x13
line.long 0x0 "DMA_CH5_RxDesc_Tail_LPointer,The Channel5 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH5_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH5_Rx_Control2,The Channel5 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH5_Interrupt_Enable,The Channel5 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH5_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x33C4++0x3
line.long 0x0 "DMA_CH5_Current_App_TxDesc_L,The Channel5 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x33CC++0x13
line.long 0x0 "DMA_CH5_Current_App_RxDesc_L,The Channel5 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH5_Current_App_TxBuffer_H,The Channel5 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH5_Current_App_TxBuffer_L,The Channel5 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH5_Current_App_RxBuffer_H,The Channel5 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH5_Current_App_RxBuffer_L,The Channel5 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x33E0++0x3
line.long 0x0 "DMA_CH5_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x33E4++0x1B
line.long 0x0 "DMA_CH5_Debug_Status,DMA Channe5 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH5_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH5_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH5_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH5_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH5_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH5_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH5_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3400++0x1F
line.long 0x0 "DMA_CH6_Control,The DMA Channel6 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH6_Tx_Control,The DMA Channel6 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH6_Rx_Control,The DMA Channel6 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel6 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH6_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH6_TxDesc_List_HAddress,The Channel6 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH6_TxDesc_List_LAddress,The Channel6 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH6_RxDesc_List_HAddress,The Channel6 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH6_RxDesc_List_LAddress,The Channel6 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3424++0x3
line.long 0x0 "DMA_CH6_TxDesc_Tail_LPointer,The Channel6 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x342C++0x13
line.long 0x0 "DMA_CH6_RxDesc_Tail_LPointer,The Channel6 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH6_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
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hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH6_Rx_Control2,The Channel6 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH6_Interrupt_Enable,The Channel6 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH6_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3444++0x3
line.long 0x0 "DMA_CH6_Current_App_TxDesc_L,The Channel6 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x344C++0x13
line.long 0x0 "DMA_CH6_Current_App_RxDesc_L,The Channel6 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH6_Current_App_TxBuffer_H,The Channel6 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH6_Current_App_TxBuffer_L,The Channel6 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH6_Current_App_RxBuffer_H,The Channel6 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH6_Current_App_RxBuffer_L,The Channel6 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3460++0x3
line.long 0x0 "DMA_CH6_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3464++0x1B
line.long 0x0 "DMA_CH6_Debug_Status,DMA Channe6 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH6_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH6_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH6_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH6_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH6_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH6_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH6_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3480++0x1F
line.long 0x0 "DMA_CH7_Control,The DMA Channel7 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH7_Tx_Control,The DMA Channel7 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH7_Rx_Control,The DMA Channel7 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel7 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH7_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH7_TxDesc_List_HAddress,The Channel7 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH7_TxDesc_List_LAddress,The Channel7 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH7_RxDesc_List_HAddress,The Channel7 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH7_RxDesc_List_LAddress,The Channel7 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x34A4++0x3
line.long 0x0 "DMA_CH7_TxDesc_Tail_LPointer,The Channel7 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x34AC++0x13
line.long 0x0 "DMA_CH7_RxDesc_Tail_LPointer,The Channel7 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH7_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH7_Rx_Control2,The Channel7 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH7_Interrupt_Enable,The Channel7 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH7_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x34C4++0x3
line.long 0x0 "DMA_CH7_Current_App_TxDesc_L,The Channel7 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x34CC++0x13
line.long 0x0 "DMA_CH7_Current_App_RxDesc_L,The Channel7 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH7_Current_App_TxBuffer_H,The Channel7 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH7_Current_App_TxBuffer_L,The Channel7 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH7_Current_App_RxBuffer_H,The Channel7 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH7_Current_App_RxBuffer_L,The Channel7 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x34E0++0x3
line.long 0x0 "DMA_CH7_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x34E4++0x1B
line.long 0x0 "DMA_CH7_Debug_Status,DMA Channe7 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH7_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH7_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH7_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH7_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH7_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH7_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH7_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
tree.end
tree "EMAC_1"
base ad:0x10820000
group.long 0x0++0x17
line.long 0x0 "MAC_Tx_Configuration,The MAC Transmit Configuration register establishes the operating mode of the MAC transmitter."
bitfld.long 0x0 29.--31. "SS,Speed Selection." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 28. "Reserved_G9991EN,Reserved." "0,1"
newline
rbitfld.long 0x0 27. "Reserved_GT9WH,Reserved." "0,1"
newline
rbitfld.long 0x0 26. "Reserved_26,Reserved." "0,1"
newline
rbitfld.long 0x0 25. "Reserved_VNM,Reserved." "0,1"
newline
rbitfld.long 0x0 24. "Reserved_VNE,Reserved." "0,1"
newline
rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1"
newline
bitfld.long 0x0 20.--22. "SARC,Source Address Insertion or Replacement Control." "?,?,2: ,3: ,?,?,?,?"
newline
rbitfld.long 0x0 19. "Reserved_PEN,Reserved." "0,1"
newline
rbitfld.long 0x0 18. "Reserved_PCHM,Reserved." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "JD,Jabber Disable." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 13. "LUD,Link Up or Down." "0: Link down,1: Link up"
newline
bitfld.long 0x0 12. "TC,Transmit Configuration in RGMII." "0: Disable Transmit Configuration in RGMII,1: Enable Transmit Configuration in RGMII"
newline
bitfld.long 0x0 11. "IFP,IPG Control" "0,1"
newline
bitfld.long 0x0 8.--10. "IPG,Inter-Packet Gap" "0: 96 bit times,1: 88 bit times,2: 80 bit times,3: 72 bit times,4: 64 bit times,?,?,7: Reserved"
newline
hexmask.long.byte 0x0 4.--7. 1. "ISR,IFG Stretch Ratio."
newline
bitfld.long 0x0 3. "ISM,IFG Stretch Mode." "0,1"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 1. "DDIC,Disable DIC Algorithm." "0,1"
newline
bitfld.long 0x0 0. "TE,Transmitter Enable." "0,1"
line.long 0x4 "MAC_Rx_Configuration,The MAC Receive Configuration register establishes the operating mode of the MAC receiver."
bitfld.long 0x4 31. "ARPEN,ARP enable." "0,1"
newline
rbitfld.long 0x4 30. "Reserved_ELEN,Reserved." "0,1"
newline
hexmask.long.word 0x4 16.--29. 1. "GPSL,Giant Packet Size Limit."
newline
rbitfld.long 0x4 15. "Reserved_PRXM,Reserved." "0,1"
newline
bitfld.long 0x4 12.--14. "HDSMS,Maximum Size for Splitting the Header Data." "0: 64 bytes,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1023 bytes,?,?,?"
newline
bitfld.long 0x4 11. "S2KP,IEEE 802.3as Support for 2K Packets." "0,1"
newline
bitfld.long 0x4 10. "LM,Loopback Mode." "0,1"
newline
bitfld.long 0x4 9. "IPC,Checksum Offload." "0,1"
newline
bitfld.long 0x4 8. "JE,Jumbo Packet Enable." "0,1"
newline
bitfld.long 0x4 7. "WD,Watchdog Disable." "0,1"
newline
bitfld.long 0x4 6. "GPSLCE,Giant Packet Size Limit Control Enable." "0,1"
newline
bitfld.long 0x4 5. "USP,Unicast Slow Protocol Packet Detect." "0,1"
newline
bitfld.long 0x4 4. "SPEN,Slow Protocol Detection Enable." "0,1"
newline
bitfld.long 0x4 3. "DCRCC,Disable CRC Checking for Received Packets." "0,1"
newline
bitfld.long 0x4 2. "CST,CRC stripping for Type packets." "0,1"
newline
bitfld.long 0x4 1. "ACS,Automatic Pad or CRC Stripping." "0,1"
newline
bitfld.long 0x4 0. "RE,Receiver Enable." "0,1"
line.long 0x8 "MAC_Packet_Filter,The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of.."
bitfld.long 0x8 31. "RA,Receive All." "0,1"
newline
hexmask.long.byte 0x8 23.--30. 1. "Reserved_30_23,Reserved."
newline
rbitfld.long 0x8 22. "Reserved_VUCC,Reserved." "0,1"
newline
bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets." "0,1"
newline
bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable." "0,1"
newline
rbitfld.long 0x8 17.--19. "Reserved_19_17,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable." "0,1"
newline
rbitfld.long 0x8 13.--15. "Reserved_15_13,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 11.--12. "DHLFRS,DA Hash Index or L3/L4 Filter Number in Receive Status." "0: Use both backward compatible DA hash index and..,1: Use combined DA hash table index and L3/L4..,2: Use combined DA hash table index and L3/L4..,3: Reserved"
newline
bitfld.long 0x8 10. "HPF,Hash or Perfect Filter." "0,1"
newline
bitfld.long 0x8 9. "SAF,Source Address Filter Enable." "0,1"
newline
bitfld.long 0x8 8. "SAIF,SA Inverse Filtering." "0,1"
newline
bitfld.long 0x8 6.--7. "PCF,Pass Control Packets." "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,?,?"
newline
bitfld.long 0x8 5. "DBF,Disable Broadcast Packets." "0,1"
newline
bitfld.long 0x8 4. "PM,Pass All Multicast." "0,1"
newline
bitfld.long 0x8 3. "DAIF,DA Inverse Filtering." "0,1"
newline
bitfld.long 0x8 2. "HMC,Hash Multicast." "0,1"
newline
bitfld.long 0x8 1. "HUC,Hash Unicast." "0,1"
newline
bitfld.long 0x8 0. "PR,Promiscuous Mode." "0,1"
line.long 0xC "MAC_WD_JB_Timeout,The Watchdog and Jabber Timeout register controls the watchdog timeout limit for the received packets and jabber timeout limit for transmitted packets."
hexmask.long.byte 0xC 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0xC 24. "PJE,Programmable Jabber Enable." "0,1"
newline
hexmask.long.byte 0xC 20.--23. 1. "Reserved_23_20,Reserved."
newline
hexmask.long.byte 0xC 16.--19. 1. "JTO,Jabber Timeout."
newline
hexmask.long.byte 0xC 9.--15. 1. "Reserved_15_9,Reserved."
newline
bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable." "0,1"
newline
hexmask.long.byte 0xC 4.--7. 1. "Reserved_7_4,Reserved."
newline
hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout."
line.long 0x10 "MAC_Hash_Table_Reg0,The 64-bit hash table is used for group address filtering. For hash filtering. the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC are used to index the.."
hexmask.long 0x10 0.--31. 1. "HT31T0,Lower 32 bits of Hash Table."
line.long 0x14 "MAC_Hash_Table_Reg1,The 64-bit hash table is used for group address filtering. For hash filtering. the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC are used to index the.."
hexmask.long 0x14 0.--31. 1. "HT31T0,Upper 32 bits of Hash Table."
group.long 0x50++0x7
line.long 0x0 "MAC_VLAN_Tag_Ctrl,MAC_VLAN_Tag_Ctrl register is a re-defined version of MAC_VLAN_Tag register. This register holds the control and addressing fields required for indirect accessing of the MAC_VLAN_Tag_Filter registers. when Extended Internal Rx VLAN.."
bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status." "0,1"
newline
rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive." "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
newline
bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag for VLAN hash filtering." "0,1"
newline
bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing." "0,1"
newline
bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable." "0,1"
newline
bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status." "0,1"
newline
rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1"
newline
bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive." "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
newline
bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check for VLAN hash filtering." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match for VLAN hash filtering." "0,1"
newline
bitfld.long 0x0 18. "ESVL,Enable S-VLAN." "0,1"
newline
bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match/Result Enable." "0,1"
newline
bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison for VLAN hash filtering." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_ERIVTL,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 12.--13. "Reserved_EROVTL,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x0 7.--11. 1. "Reserved_11_7,Reserved."
newline
hexmask.long.byte 0x0 2.--6. 1. "OFS,Offset."
newline
bitfld.long 0x0 1. "CT,Command Type." "0,1"
newline
bitfld.long 0x0 0. "OB,Operation Busy." "0,1"
line.long 0x4 "MAC_VLAN_Tag_Data,This register holds the read/write data for Indirect Access of the Per MAC_VLAN_Tag_Filter registers. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field must.."
hexmask.long.byte 0x4 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x4 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x4 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x4 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x4 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag Identifier for Receive Packets."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter0,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter1,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter10,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter11,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter12,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter13,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter14,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter15,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter16,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter17,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter18,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter19,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter2,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter20,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter21,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter22,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter23,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter24,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter25,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter26,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter27,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter28,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter29,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter3,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter30,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter31,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter4,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter5,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter6,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter7,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter8,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x7
line.long 0x0 "MAC_VLAN_Tag_Filter9,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
line.long 0x4 "MAC_VLAN_Hash_Table,When the ERSVLM bit of MAC_VLAN_Tag register is set. the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the.."
hexmask.long.word 0x4 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "VLHT,VLAN Hash Table."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl,The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls."
rbitfld.long 0x0 31. "BUSY,BUSY." "0,1"
newline
bitfld.long 0x0 30. "RDWR,Read Write Control." "0,1"
newline
rbitfld.long 0x0 27.--29. "Reserved_29_y,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24.--26. "ADDR,Address." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 21. "CBTI,Channel Based Tag Insertion." "0,1"
newline
bitfld.long 0x0 20. "VLTI,VLAN Tag Input." "0,1"
newline
bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
bitfld.long 0x0 18. "VLP,VLAN Priority Control." "0,1"
newline
bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets." "0: No VLAN tag deletion,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl0,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl1,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl10,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl11,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl12,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl13,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl14,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl15,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl2,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl3,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl4,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl5,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl6,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl7,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl8,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x7
line.long 0x0 "MAC_VLAN_Incl9,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
line.long 0x4 "MAC_Inner_VLAN_Incl,The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls."
hexmask.long.word 0x4 21.--31. 1. "Reserved_31_21,Reserved."
newline
bitfld.long 0x4 20. "VLTI,VLAN Tag Input." "0,1"
newline
bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
bitfld.long 0x4 18. "VLP,VLAN Priority Control." "0,1"
newline
bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets." "0: No VLAN tag deletion,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
newline
hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x6C++0x2F
line.long 0x0 "MAC_Rx_Eth_Type_Match,The receive Ethernet type match register contains the ether type value that needs to be compared with the ether length/type field of the received packet. The result is indicated in the packet_type field of receive status word. This.."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0x0 0.--15. 1. "ET,Ethernet Type."
line.long 0x4 "MAC_Q0_Tx_Flow_Ctrl,The MAC_Q0_Tx_Flow_Ctrl register controls the generation of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a.."
hexmask.long.word 0x4 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x4 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x4 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,2: Pause Time minus 36 Slot Times,3: Pause Time minus 144 Slot Times,4: Pause Time minus 256 Slot Times,?,?,7: Reserved"
newline
rbitfld.long 0x4 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x4 0. "FCB,Flow Control Busy or Backpressure Activate." "0,1"
line.long 0x8 "MAC_Q1_Tx_Flow_Ctrl,The MAC_Q1_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x8 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x8 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x8 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x8 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x8 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x8 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x8 0. "FCB,Flow Control Busy." "0,1"
line.long 0xC "MAC_Q2_Tx_Flow_Ctrl,The MAC_Q2_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0xC 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0xC 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0xC 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0xC 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0xC 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0xC 0. "FCB,Flow Control Busy." "0,1"
line.long 0x10 "MAC_Q3_Tx_Flow_Ctrl,The MAC_Q3_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x10 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x10 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x10 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x10 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x10 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x10 0. "FCB,Flow Control Busy." "0,1"
line.long 0x14 "MAC_Q4_Tx_Flow_Ctrl,The MAC_Q4_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x14 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x14 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x14 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x14 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x14 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
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bitfld.long 0x14 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x14 0. "FCB,Flow Control Busy." "0,1"
line.long 0x18 "MAC_Q5_Tx_Flow_Ctrl,The MAC_Q5_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x18 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x18 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x18 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x18 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x18 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x18 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x18 0. "FCB,Flow Control Busy." "0,1"
line.long 0x1C "MAC_Q6_Tx_Flow_Ctrl,The MAC_Q6_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x1C 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x1C 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x1C 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
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bitfld.long 0x1C 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
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rbitfld.long 0x1C 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x1C 1. "TFE,Transmit Flow Control Enable." "0,1"
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bitfld.long 0x1C 0. "FCB,Flow Control Busy." "0,1"
line.long 0x20 "MAC_Q7_Tx_Flow_Ctrl,The MAC_Q7_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x20 16.--31. 1. "PT,Pause Time."
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hexmask.long.byte 0x20 8.--15. 1. "Reserved_15_8,Reserved."
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bitfld.long 0x20 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x20 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x20 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x20 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x20 0. "FCB,Flow Control Busy." "0,1"
line.long 0x24 "MAC_Rx_Flow_Ctrl,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet."
hexmask.long.tbyte 0x24 9.--31. 1. "Reserved_31_9,Reserved."
newline
bitfld.long 0x24 8. "PFCE,Priority Based Flow Control Enable." "0: Enables generation and reception of IEEE 802,1: Enables generation and reception of.."
newline
hexmask.long.byte 0x24 2.--7. 1. "Reserved_7_2,Reserved."
newline
bitfld.long 0x24 1. "UP,Unicast Pause Packet Detect." "0,1"
newline
bitfld.long 0x24 0. "RFE,Receive Flow Control Enable." "0: When MAC operates in half-duplex mode,1: When MAC operates in full-duplex mode"
line.long 0x28 "MAC_RxQ_Ctrl4,The Receive Queue Control 4 register controls the routing of"
hexmask.long.byte 0x28 27.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x28 24.--26. "PMCBCQ,Preemption Multicast/Broadcast Queue." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 20.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x28 17.--19. "VFFQ,VLAN Tag Filter Fail Packets Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable." "0: VLAN tag Filter Fail Packets Queuing is disabled,1: VLAN tag Filter Fail Packets Queuing is enabled"
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hexmask.long.byte 0x28 12.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x28 9.--11. "MFFQ,Multicast Address Filter Fail Packets Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 8. "MFFQE,Multicast Filter Fail Packets Queuing Enable." "0: Multicast Address Filter Fail Packets Queuing is..,1: Multicast Address Filter Fail Packets Queuing is.."
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hexmask.long.byte 0x28 4.--7. 1. "Reserved_7_y,Reserved."
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bitfld.long 0x28 1.--3. "UFFQ,Unicast Address Filter Fail Packets Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 0. "UFFQE,Unicast Filter Fail Packets Queuing Enable." "0: Unicast Address Filter Fail Packets Queuing is..,1: Unicast Address Filter Fail Packets Queuing is.."
line.long 0x2C "MAC_RxQ_Ctrl5,The Receive Queue Control 5 register allows selection of start offset of the Receive queue from which received packets are routed based on VLAN Tag Priority field."
hexmask.long 0x2C 4.--31. 1. "Reserved_31_4,Reserved."
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hexmask.long.byte 0x2C 0.--3. 1. "PRQSO,Priority Receive Queue Start Offset."
group.long 0xA0++0xF
line.long 0x0 "MAC_RxQ_Ctrl0,The Receive Queue Control 0 register activates the queue management in the MAC Receiver. This register is present only when you select multiple queues in the Receive path."
rbitfld.long 0x0 30.--31. "Reserved_RXQ15EN,Reserved." "0,1,2,3"
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rbitfld.long 0x0 28.--29. "Reserved_RXQ14EN,Reserved." "0,1,2,3"
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rbitfld.long 0x0 26.--27. "Reserved_RXQ13EN,Reserved." "0,1,2,3"
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rbitfld.long 0x0 24.--25. "Reserved_RXQ12EN,Reserved." "0,1,2,3"
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rbitfld.long 0x0 22.--23. "Reserved_RXQ11EN,Reserved." "0,1,2,3"
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rbitfld.long 0x0 20.--21. "Reserved_RXQ10EN,Reserved." "0,1,2,3"
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rbitfld.long 0x0 18.--19. "Reserved_RXQ9EN,Reserved." "0,1,2,3"
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rbitfld.long 0x0 16.--17. "Reserved_RXQ8EN,Reserved." "0,1,2,3"
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bitfld.long 0x0 14.--15. "RXQ7EN,Receive Queue 7 Enable." "0,1,2,3"
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bitfld.long 0x0 12.--13. "RXQ6EN,Receive Queue 6 Enable." "0,1,2,3"
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bitfld.long 0x0 10.--11. "RXQ5EN,Receive Queue 5 Enable." "0,1,2,3"
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bitfld.long 0x0 8.--9. "RXQ4EN,Receive Queue 4 Enable." "0,1,2,3"
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bitfld.long 0x0 6.--7. "RXQ3EN,Receive Queue 3 Enable." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RXQ2EN,Receive Queue 2 Enable." "0,1,2,3"
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bitfld.long 0x0 2.--3. "RXQ1EN,Receive Queue 1 Enable." "0,1,2,3"
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bitfld.long 0x0 0.--1. "RXQ0EN,Receive Queue 0 Enable." "0: Not enabled,1: Queue 0 enabled for Audio Video Bridging,2: Queue 0 enabled for Data Center Bridging/Generic,3: Reserved"
line.long 0x4 "MAC_RxQ_Ctrl1,This register allows the selection of the Receive queues to which the received untagged or special packets are routed or written. This register is present only when you select multiple queues in the Receive path."
hexmask.long.byte 0x4 28.--31. 1. "AVCPQ,AV Control Packets Queue."
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hexmask.long.byte 0x4 24.--27. 1. "PTPQ,PTP Packets Queue."
newline
bitfld.long 0x4 23. "TACPQE,Tagged AV Control Packets Queuing Enable." "0,1"
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bitfld.long 0x4 21.--22. "TPQC,Tagged PTP over Ethernet Packets Queuing Control." "0: VLAN Tagged PTP over Ethernet packets are routed..,1: VLAN Tagged PTP over Ethernet packets are routed..,2: VLAN Tagged PTP over Ethernet packets are routed..,3: Reserved"
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bitfld.long 0x4 20. "OMCBCQ,Programmable control for Over-riding MCBCQ Priority." "0,1"
newline
hexmask.long.byte 0x4 16.--19. 1. "DCBCPQ,DCB Control Packets Queue."
newline
bitfld.long 0x4 15. "MCBCQEN,Multicast or Broadcast Queue Enable." "0,1"
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rbitfld.long 0x4 12.--14. "Reserved_14_12,Reserved." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x4 8.--11. 1. "MCBCQ,Multicast or Broadcast Queue."
newline
hexmask.long.byte 0x4 4.--7. 1. "RQ,Frame Preemption Residue Queue"
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hexmask.long.byte 0x4 0.--3. 1. "UPQ,Untagged Packet Queue."
line.long 0x8 "MAC_RxQ_Ctrl2,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the Rx Queues 0 to 3. This register is present when multiple Rx Queues are selected while configuring the controller."
hexmask.long.byte 0x8 24.--31. 1. "PSRQ3,Priorities Selected in the Receive Queue 3."
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hexmask.long.byte 0x8 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2."
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hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1."
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hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0."
line.long 0xC "MAC_RxQ_Ctrl3,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the Rx Queues 4 to 7. This register is present when the 'Enable Data Center Bridging' option is selected and with more.."
hexmask.long.byte 0xC 24.--31. 1. "PSRQ7,Priorities Selected in the Receive Queue 7."
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hexmask.long.byte 0xC 16.--23. 1. "PSRQ6,Priorities Selected in the Receive Queue 6."
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hexmask.long.byte 0xC 8.--15. 1. "PSRQ5,Priorities Selected in the Receive Queue 5."
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hexmask.long.byte 0xC 0.--7. 1. "PSRQ4,Priorities Selected in the Receive Queue 4."
rgroup.long 0xB0++0x3
line.long 0x0 "MAC_Interrupt_Status,The Interrupt Status register contains the status of interrupts."
hexmask.long.byte 0x0 26.--31. 1. "Reserved_31_26,Reserved."
newline
bitfld.long 0x0 24.--25. "LS,Link Status." "0: Half Duplex,1: Full Duplex,2: 1Gbps,3: Reserved"
newline
bitfld.long 0x0 23. "Reserved_PCIS,Reserved." "0,1"
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hexmask.long.byte 0x0 19.--22. 1. "Reserved_22_19,Reserved."
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bitfld.long 0x0 18. "MFRIS,MMC FPE Receive Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "MFTIS,MMC FPE Transmit Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "FPEIS,Frame Preemption Interrupt Status" "0,1"
newline
bitfld.long 0x0 15. "GPIIS,GPI Interrupt Status." "0,1"
newline
bitfld.long 0x0 14. "RXESIS,Receive Error Status Interrupt." "0,1"
newline
bitfld.long 0x0 13. "TXESIS,Transmit Error Status Interrupt." "0,1"
newline
bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status." "0,1"
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bitfld.long 0x0 11. "MMCRXIPIS,MMC Receive Checksum Offload Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status." "0,1"
newline
bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status." "0,1"
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bitfld.long 0x0 6.--8. "Reserved_8_6,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 5. "Reserved_LPIIS,Reserved." "0,1"
newline
bitfld.long 0x0 4. "Reserved_PMTIS,Reserved." "0,1"
newline
bitfld.long 0x0 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
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bitfld.long 0x0 1. "SMI,SMA Interrupt." "0,1"
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bitfld.long 0x0 0. "LSI,Link Status change Interrupt." "0,1"
group.long 0xB4++0x3
line.long 0x0 "MAC_Interrupt_Enable,The Interrupt Enable register contains the masks for generating the interrupts."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "FPEIE,Frame Preemption Interrupt Enable" "0,1"
newline
bitfld.long 0x0 14. "RXESIE,Receive Error Status Interrupt Enable." "0,1"
newline
bitfld.long 0x0 13. "TXESIE,Transmit Error Status Interrupt Enable." "0,1"
newline
bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable." "0,1"
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hexmask.long.byte 0x0 6.--11. 1. "Reserved_11_6,Reserved."
newline
rbitfld.long 0x0 5. "Reserved_LPIIE,Reserved." "0,1"
newline
rbitfld.long 0x0 4. "Reserved_PMTIE,Reserved." "0,1"
newline
rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. "LSIE,Link Status Change Interrupt Enable." "0,1"
rgroup.long 0xB8++0x3
line.long 0x0 "MAC_Rx_Tx_Status,The Receive Transmit Status register contains the Receive and Transmit Error status."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
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bitfld.long 0x0 13. "PCE,Payload Checksum Error." "0,1"
newline
bitfld.long 0x0 12. "IHE,IP Header Error." "0,1"
newline
bitfld.long 0x0 9.--11. "Reserved_11_9,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout." "0,1"
newline
bitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 5. "EXCOL,Excessive Collisions" "0,1"
newline
bitfld.long 0x0 4. "LCOL,Late Collision" "0,1"
newline
bitfld.long 0x0 3. "EXDEF,Excessive Deferral" "0,1"
newline
bitfld.long 0x0 2. "LCARR,Loss of Carrier" "0,1"
newline
bitfld.long 0x0 1. "NCARR,No Carrier" "0,1"
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bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout." "0,1"
rgroup.long 0x110++0x7
line.long 0x0 "MAC_Version,The version register identifies the version of DWC_xgmac. This register contains two bytes: one that Synopsys uses to identify the controller release number. and the other that you set while configuring the controller."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
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hexmask.long.byte 0x0 16.--23. 1. "USERVER,User-defined Version (configured with coreConsultant)"
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hexmask.long.byte 0x0 8.--15. 1. "DEVID,Indicates the Device family"
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hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,Synopsys-defined Version (2.0)"
line.long 0x4 "MAC_Debug,The Debug register provides the debug status of various MAC blocks."
hexmask.long.word 0x4 19.--31. 1. "Reserved_31_19,Reserved."
newline
bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status." "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control packet,3: Transferring input packet for transmission"
newline
bitfld.long 0x4 16. "TPESTS,MAC GMII Transmit Protocol Engine Status." "0,1"
newline
hexmask.long.word 0x4 3.--15. 1. "Reserved_15_3,Reserved."
newline
bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status." "0,1,2,3"
newline
bitfld.long 0x4 0. "RPESTS,MAC  GMII  Receive Protocol Engine Status." "0,1"
rgroup.long 0x11C++0x13
line.long 0x0 "MAC_HW_Feature0,This register indicates the presence of the first set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
bitfld.long 0x0 31. "EDMA,Enhanced DMA." "0,1"
newline
bitfld.long 0x0 30. "EDIFFC,Different Descriptor Cache." "0,1"
newline
bitfld.long 0x0 29. "VXN,VxLAN/NVGRE Support." "0,1"
newline
bitfld.long 0x0 28. "Reserved_28,Reserved." "0,1"
newline
bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable." "0,1"
newline
bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source." "0: Reserved,1: Internal,?,?"
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bitfld.long 0x0 23.--24. "PHYSEL,RGMII Interface Select" "0,1,2,3"
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hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected."
newline
bitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled." "0,1"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled." "0,1"
newline
bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled." "0,1"
newline
bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled." "0,1"
newline
bitfld.long 0x0 11. "AVSEL,AV Feature Enabled." "0,1"
newline
bitfld.long 0x0 10. "RAVSEL,Rx Side Only AV Feature Enable." "0,1"
newline
bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled." "0,1"
newline
bitfld.long 0x0 8. "MMCSEL,RMON Module Enable." "0,1"
newline
bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable." "0,1"
newline
bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Enable." "0,1"
newline
bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface." "0,1"
newline
bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected." "0,1"
newline
bitfld.long 0x0 3. "HDSEL,Half-duplex Support" "0,1"
newline
bitfld.long 0x0 2. "RMIISEL,RMII Support." "0,1"
newline
bitfld.long 0x0 1. "GMIISEL,1000/100/10 Mbps Support." "0,1"
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bitfld.long 0x0 0. "RGMIISEL,RGMII Support." "0,1"
line.long 0x4 "MAC_HW_Feature1,This register indicates the presence of second set of the optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
bitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters."
newline
bitfld.long 0x4 24.--26. "HASHTBLSZ,Hash Table Size." "0: No hash table selected,1: 64,2: 128,3: 256,4: 512,5: 1024,6: 2048,7: 4096"
newline
bitfld.long 0x4 21.--23. "NUMTC,Number of Traffic Classes." "0: 1 Traffic Class,1: 2 Traffic Classes,2: 3 Traffic Classes,?,?,?,?,7: 8 Traffic"
newline
bitfld.long 0x4 20. "RSSEN,Internal Register based RSS Feature Enabled" "0,1"
newline
bitfld.long 0x4 19. "DBGMEMA,Debug Memory Interface Enabled." "0,1"
newline
bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable." "0,1"
newline
bitfld.long 0x4 17. "SPHEN,Header-Payload Split Feature Enable." "0,1"
newline
bitfld.long 0x4 16. "DCBEN,DCB Feature Enable." "0,1"
newline
bitfld.long 0x4 14.--15. "ADDR64,Address Width." "0: 32,1: 40,2: 48,3: Reserved"
newline
bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable." "0,1"
newline
bitfld.long 0x4 12. "PTOEN,PTP Offload Enable." "0,1"
newline
bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable." "0,1"
newline
hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size."
newline
bitfld.long 0x4 5. "PFCEN,PFC Enable" "0,1"
newline
hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size."
line.long 0x8 "MAC_HW_Feature2,This register indicates the presence of the third set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
bitfld.long 0x8 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs." "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary inputs,3: 3 auxiliary inputs,4: 4 auxiliary inputs,?,?,7: Reserved"
newline
bitfld.long 0x8 27. "Reserved_27,Reserved." "0,1"
newline
bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs." "0: No PPS output,1: 1 PPS output,2: 2 PPS outputs,3: 3 PPS outputs,4: 4 PPS outputs,?,?,7: Reserved"
newline
bitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels."
newline
bitfld.long 0x8 16.--17. "Reserved_17_16,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels."
newline
bitfld.long 0x8 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues."
newline
bitfld.long 0x8 4.--5. "Reserved_5_4,Reserved." "0,1,2,3"
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hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues."
line.long 0xC "MAC_HW_Feature3,This register indicates the presence of the fourth set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
hexmask.long.byte 0xC 28.--31. 1. "TBS_CH,The number of DMA channels enabled for TBS (starting from the highest Tx Channel  in descending order)"
newline
bitfld.long 0xC 27. "TBSSEL,Time Based Scheduling Enable" "0,1"
newline
bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable" "0,1"
newline
bitfld.long 0xC 25. "SGFSEL,Per-Stream Filtering Select" "0,1"
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bitfld.long 0xC 23.--24. "GCLWID,Width of the Time Interval field in the Gate Control List" "0,1,2,3"
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bitfld.long 0xC 20.--22. "GCLDEP,Depth of the Gate Control List" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 19. "ESTSEL,Enhancements to Scheduling Traffic Enable" "0,1"
newline
bitfld.long 0xC 16.--18. "TTSFD,Tx Timestamp FIFO Depth" "0: Reserved,1: 1,2: 2,3: 4,4: 8,5: 16,6: Reserved,7: Reserved"
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bitfld.long 0xC 14.--15. "ASP,Automotive Safety Package" "0: No Safety features selected,1: All the Automotive Safety features are selected..,2: All the Automotive Safety features are selected..,3: All the Automotive Safety features are selected.."
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bitfld.long 0xC 13. "DVLAN,Double VLAN Processing Enabled" "0,1"
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bitfld.long 0xC 11.--12. "FRPES,Supported Flexible Receive Parser Instructions" "0,1,2,3"
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bitfld.long 0xC 9.--10. "FRPPB,Supported Flexible Receive Parser Parsable Bytes" "0,1,2,3"
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bitfld.long 0xC 8. "POUOST,One Step for PTP over UDP/IP Feature Enable" "0,1"
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bitfld.long 0xC 5.--7. "FRPPIPE,Supported Parallel Instruction Processor Engines (PIPEs)" "0: 1 PIPE,1: 2 PIPEs,?,?,?,?,?,?"
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bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable" "0,1"
newline
bitfld.long 0xC 3. "FRPSEL,Supported Flexible Receive Parser." "0,1"
newline
bitfld.long 0xC 0.--2. "NRVF,Enabled number of Extended VLAN Tag Filters or External VLAN tag lookup size" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,6: Reserved,7: External Receive 12bit VLAN Tag Lookup is selected"
line.long 0x10 "MAC_HW_Feature4,This register indicates the presence of the fifth set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
hexmask.long 0x10 2.--31. 1. "Reserved_31_2,Reserved."
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bitfld.long 0x10 0.--1. "PCSEL,Policing Counters" "0,1,2,3"
group.long 0x140++0x7
line.long 0x0 "MAC_Extended_Configuration,The MAC Extended Configuration register establishes the operating mode of the MAC transmitter."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "HD,Duplex Mode" "0,1"
newline
bitfld.long 0x0 23. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode" "0,1"
newline
bitfld.long 0x0 22. "DO,Disable Receive Own" "0,1"
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bitfld.long 0x0 21. "DCRS,Disable Carrier Sense During Transmission" "0,1"
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bitfld.long 0x0 20. "DR,Disable Retry" "0,1"
newline
bitfld.long 0x0 18.--19. "BL,Back-Off Limit" "0,1,2,3"
newline
bitfld.long 0x0 17. "DC,Deferral Check" "0,1"
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rbitfld.long 0x0 16. "Reserved_SBDIOEN,Reserved." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_15_10,Reserved."
newline
bitfld.long 0x0 9. "TPRE,Reserved" "0,1"
newline
rbitfld.long 0x0 8. "Reserved_VPRE,Reserved." "0,1"
newline
bitfld.long 0x0 7. "DDS,DA Duplication Select." "0: DCS field in MAC_Address_High register is..,1: XDCS field in MAC_DChSel_IndReg register.."
newline
hexmask.long.byte 0x0 0.--6. 1. "EIPG,Extended Inter-Packet Gap."
line.long 0x4 "MAC_Ext_Cfg1,This register contains Split mode control field and offset field for Header-Payload Split feature."
hexmask.long.byte 0x4 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x4 24. "SAVE,Split AV Enable" "0,1"
newline
rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1"
newline
hexmask.long.byte 0x4 16.--22. 1. "SAVO,Split AV Offset"
newline
hexmask.long.byte 0x4 10.--15. 1. "Reserved_15_10,Reserved."
newline
bitfld.long 0x4 8.--9. "SPLM,Split Mode" "0,1,2,3"
newline
rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1"
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hexmask.long.byte 0x4 0.--6. 1. "SPLOFST,Split Offset"
group.long 0x200++0x13
line.long 0x0 "MDIO_Single_Command_Address,This register contains the addresses of the ports. devices. and registers accessed by the SMA during single read or write transfers."
hexmask.long.byte 0x0 26.--31. 1. "Reserved_31_26,Reserved."
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hexmask.long.byte 0x0 21.--25. 1. "DA,Device Address"
newline
hexmask.long.byte 0x0 16.--20. 1. "PA,Port Address"
newline
hexmask.long.word 0x0 0.--15. 1. "RA,Register Address"
line.long 0x4 "MDIO_Single_Command_Control_Data,This register controls single read/write operations. and contains the data bits read on a single-read operation and the data to be written during single-write operations."
bitfld.long 0x4 31. "CRS,Clock Range Select." "0,1"
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bitfld.long 0x4 30. "PSE,Preamble Suppression Enable." "0,1"
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hexmask.long.byte 0x4 23.--29. 1. "Reserved_29_23,Reserved."
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bitfld.long 0x4 22. "SBusy,Busy" "0,1"
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bitfld.long 0x4 19.--21. "CR,Application Clock Range" "0: MDC clock: clk_csr_i/4,1: MDC clock: clk_csr_i/6,2: MDC clock: clk_csr_i/8,3: MDC clock: clk_csr_i/10,4: MDC clock: clk_csr_i/12,5: MDC clock: clk_csr_i/14,6: MDC clock: clk_csr_i/16,7: MDC clock: clk_csr_i/18"
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bitfld.long 0x4 18. "SAADR,Skip Address Frame" "0,1"
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bitfld.long 0x4 16.--17. "CMD,Control Command" "0: Reserved,1: SINGLE_WRITE,2: POST INCREMENT READ OPERATION,3: SINGLE_READ"
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hexmask.long.word 0x4 0.--15. 1. "SDATA,Single Write Data"
line.long 0x8 "MDIO_Continuous_Write_Address,You can program this register to start continuous write operation."
hexmask.long.word 0x8 23.--31. 1. "Reserved_31_23,Reserved."
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bitfld.long 0x8 22. "CBUSY,Continuous Write Busy" "0,1"
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bitfld.long 0x8 21. "CPRT,Continuous Port or Device Address Select" "0,1"
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hexmask.long.byte 0x8 16.--20. 1. "CADDR,Continuous Port or Device Address"
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hexmask.long.word 0x8 0.--15. 1. "CREGADDR,Continuous Register Address"
line.long 0xC "MDIO_Continuous_Write_Data,This register contains the data to be written during continuous write operation. Do not change the register's contents until the Continuous Write Busy bit (CBUSY) is cleared."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
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hexmask.long.word 0xC 0.--15. 1. "CDATA,Continuous Write Data"
line.long 0x10 "MDIO_Continuous_Scan_Port_Enable,This register controls the PHY ports and corresponding devices (enabled by the corresponding Device In Use register) to be accessed during the SMA's continuous scan operation. If you change any bit in this register during.."
bitfld.long 0x10 31. "PORT31SCE,Port 31 Continuous Scan Enable." "0,1"
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bitfld.long 0x10 30. "PORT30SCE,Port 30 Continuous Scan Enable." "0,1"
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bitfld.long 0x10 29. "PORT29SCE,Port 29 Continuous Scan Enable." "0,1"
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bitfld.long 0x10 28. "PORT28SCE,Port 28 Continuous Scan Enable." "0,1"
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bitfld.long 0x10 27. "PORT27SCE,Port 27 Continuous Scan Enable." "0,1"
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bitfld.long 0x10 26. "PORT26SCE,Port 26 Continuous Scan Enable." "0,1"
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bitfld.long 0x10 25. "PORT25SCE,Port 25 Continuous Scan Enable." "0,1"
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bitfld.long 0x10 24. "PORT24SCE,Port 24 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 23. "PORT23SCE,Port 23 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 22. "PORT22SCE,Port 22 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 21. "PORT21SCE,Port 21 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 20. "PORT20SCE,Port 20 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 19. "PORT19SCE,Port 19 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 18. "PORT18SCE,Port 18 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 17. "PORT17SCE,Port 17 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 16. "PORT16SCE,Port 16 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 15. "PORT15SCE,Port 15 Continuous Scan Enable." "0,1"
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bitfld.long 0x10 14. "PORT14SCE,Port 14 Continuous Scan Enable." "0,1"
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bitfld.long 0x10 13. "PORT13SCE,Port 13 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 12. "PORT12SCE,Port 12 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 11. "PORT11SCE,Port 11 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 10. "PORT10SCE,Port 10 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 9. "PORT9SCE,Port 9 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 8. "PORT8SCE,Port 8 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 7. "PORT7SCE,Port 7 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 6. "PORT6SCE,Port 6 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 5. "PORT5SCE,Port 5 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 4. "PORT4SCE,Port 4 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 3. "PORT3SCE,Port 3 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 2. "PORT2SCE,Port 2 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 1. "PORT1SCE,Port 1 Continuous Scan Enable." "0,1"
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bitfld.long 0x10 0. "PORT0SCE,Port 0 Continuous Scan Enable." "0,1"
rgroup.long 0x214++0x3
line.long 0x0 "MDIO_Interrupt_Status,This register gives the source of the interrupt raised by the SMA module on the sbd_intr_o output line. The status bits are cleared when the software reads the corresponding bytes."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
newline
bitfld.long 0x0 13. "CWCOMPINT,Continuous Write Completion Interrupt." "0,1"
newline
bitfld.long 0x0 12. "SNGLCOMPINT,Single Command Completion Interrupt." "0,1"
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bitfld.long 0x0 11. "PORTNx4P3ALINT,Device Present Status Change Interrupt (Port Nx4 Plus3)." "0,1"
newline
bitfld.long 0x0 10. "PORTNx4P2ALINT,Device Present Status Change Interrupt (Port Nx4 Plus2)." "0,1"
newline
bitfld.long 0x0 9. "PORTNx4P1ALINT,Device Present Status Change Interrupt (Port Nx4 Plus1)." "0,1"
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bitfld.long 0x0 8. "PORTNx4P0ALINT,Device Present Status Change Interrupt (Port Nx4 Plus0)." "0,1"
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bitfld.long 0x0 7. "PORTNx4P3LSINT,Link Status Change Interrupt (Port Nx4 Plus3)." "0,1"
newline
bitfld.long 0x0 6. "PORTNx4P2LSINT,Link Status Change Interrupt (Port Nx4 Plus2)." "0,1"
newline
bitfld.long 0x0 5. "PORTNx4P1LSINT,Link Status Change Interrupt (Port Nx4 Plus1)." "0,1"
newline
bitfld.long 0x0 4. "PORTNx4P0LSINT,Link Status Change Interrupt (Port Nx4 Plus0)." "0,1"
newline
bitfld.long 0x0 3. "PORTNx4P3CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus3)." "0,1"
newline
bitfld.long 0x0 2. "PORTNx4P2CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus2)." "0,1"
newline
bitfld.long 0x0 1. "PORTNx4P1CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus1)." "0,1"
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bitfld.long 0x0 0. "PORTNx4P0CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus0)." "0,1"
group.long 0x218++0x3
line.long 0x0 "MDIO_Interrupt_Enable,This register controls the enabling of interrupt sources in the MDIO Interrupt Status register."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
newline
bitfld.long 0x0 13. "CWCOMPIE,Continuous Write Completion Interrupt Enable." "0,1"
newline
bitfld.long 0x0 12. "SNGLCOMPIE,Single Command Completion Interrupt Enable." "0,1"
newline
bitfld.long 0x0 11. "PTRNx4P3ALIE,Device Present Status Change Interrupt (Port Nx4 Plus3) Enable." "0,1"
newline
bitfld.long 0x0 10. "PTRNx4P2ALIE,Device Present Status Change Interrupt (Port Nx4 Plus2) Enable." "0,1"
newline
bitfld.long 0x0 9. "PTRNx4P1ALIE,Device Present Status Change Interrupt (Port Nx4 Plus1) Enable." "0,1"
newline
bitfld.long 0x0 8. "PTRNx4P0ALIE,Device Present Status Change Interrupt (Port Nx4 Plus0) Enable." "0,1"
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bitfld.long 0x0 7. "PTRNx4P3LSIE,Link Status Change Interrupt (Port Nx4 Plus3) Enable." "0,1"
newline
bitfld.long 0x0 6. "PTRNx4P2LSIE,Link Status Change Interrupt (Port Nx4 Plus2) Enable." "0,1"
newline
bitfld.long 0x0 5. "PTRNx4P1LSIE,Link Status Change Interrupt (Port Nx4 Plus1) Enable." "0,1"
newline
bitfld.long 0x0 4. "PTRNx4P0LSIE,Link Status Change Interrupt (Port Nx4 Plus0) Enable." "0,1"
newline
bitfld.long 0x0 3. "PTRNx4P3CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus3) Enable." "0,1"
newline
bitfld.long 0x0 2. "PTRNx4P2CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus2) Enable." "0,1"
newline
bitfld.long 0x0 1. "PTRNx4P1CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus1) Enable." "0,1"
newline
bitfld.long 0x0 0. "PTRNx4P0CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus0) Enable." "0,1"
rgroup.long 0x21C++0x3
line.long 0x0 "MDIO_Port_Connect_Disconnect_Status,This register gives the hot plug-in status for Ports 0-31. This register is updated at the end of any read operation to any register of the corresponding PHY port. It is updated during single-read transfers or during.."
bitfld.long 0x0 31. "PORT31CON,Port 31 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 30. "PORT30CON,Port 30 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 29. "PORT29CON,Port 29 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 28. "PORT28CON,Port 28 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 27. "PORT27CON,Port 27 Connect/Disconnect." "0,1"
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bitfld.long 0x0 26. "PORT26CON,Port 26 Connect/Disconnect." "0,1"
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bitfld.long 0x0 25. "PORT25CON,Port 25 Connect/Disconnect." "0,1"
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bitfld.long 0x0 24. "PORT24CON,Port 24 Connect/Disconnect." "0,1"
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bitfld.long 0x0 23. "PORT23CON,Port 23 Connect/Disconnect." "0,1"
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bitfld.long 0x0 22. "PORT22CON,Port 22 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 21. "PORT21CON,Port 21 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 20. "PORT20CON,Port 20 Connect/Disconnect." "0,1"
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bitfld.long 0x0 19. "PORT19CON,Port 19 Connect/Disconnect." "0,1"
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bitfld.long 0x0 18. "PORT18CON,Port 18 Connect/Disconnect." "0,1"
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bitfld.long 0x0 17. "PORT17CON,Port 17 Connect/Disconnect." "0,1"
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bitfld.long 0x0 16. "PORT16CON,Port 16 Connect/Disconnect." "0,1"
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bitfld.long 0x0 15. "PORT15CON,Port 15 Connect/Disconnect." "0,1"
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bitfld.long 0x0 14. "PORT14CON,Port 14 Connect/Disconnect." "0,1"
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bitfld.long 0x0 13. "PORT13CON,Port 13 Connect/Disconnect." "0,1"
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bitfld.long 0x0 12. "PORT12CON,Port 12 Connect/Disconnect." "0,1"
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bitfld.long 0x0 11. "PORT11CON,Port 11 Connect/Disconnect." "0,1"
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bitfld.long 0x0 10. "PORT10CON,Port 10 Connect/Disconnect." "0,1"
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bitfld.long 0x0 9. "PORT9CON,Port 9 Connect/Disconnect." "0,1"
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bitfld.long 0x0 8. "PORT8CON,Port 8 Connect/Disconnect." "0,1"
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bitfld.long 0x0 7. "PORT7CON,Port 7 Connect/Disconnect." "0,1"
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bitfld.long 0x0 6. "PORT6CON,Port 6 Connect/Disconnect." "0,1"
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bitfld.long 0x0 5. "PORT5CON,Port 5 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 4. "PORT4CON,Port 4 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 3. "PORT3CON,Port 3 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 2. "PORT2CON,Port 2 Connect/Disconnect." "0,1"
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bitfld.long 0x0 1. "PORT1CON,Port 1 Connect/Disconnect." "0,1"
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bitfld.long 0x0 0. "PORT0CON,Port 0 Connect/Disconnect." "0,1"
group.long 0x220++0x7
line.long 0x0 "MDIO_Clause_22_Port,This register configures the SMA to access the PHY ports using either the Clause 22 or Clause 45 packet format. All SMA operations (single or continuous) depend on setting these bits correctly."
bitfld.long 0x0 31. "PTR31CL22,Port31CL22 Enable. Indicates that Port 31 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 30. "PTR30CL22,Port30CL22 Enable. Indicates that Port 30 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 29. "PTR29CL22,Port29CL22 Enable. Indicates that Port 29 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 28. "PTR28CL22,Port28CL22 Enable. Indicates that Port 28 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 27. "PTR27CL22,Port27CL22 Enable. Indicates that Port 27 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 26. "PTR26CL22,Port26CL22 Enable. Indicates that Port 26 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 25. "PTR25CL22,Port25CL22 Enable. Indicates that Port 25 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 24. "PTR24CL22,Port24CL22 Enable. Indicates that Port 24 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 23. "PTR23CL22,Port23CL22 Enable. Indicates that Port 23 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 22. "PTR22CL22,Port22CL22 Enable. Indicates that Port 22 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 21. "PTR21CL22,Port21CL22 Enable. Indicates that Port 21 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 20. "PTR20CL22,Port20CL22 Enable. Indicates that Port 20 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 19. "PTR19CL22,Port19CL22 Enable. Indicates that Port 19 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 18. "PTR18CL22,Port18CL22 Enable. Indicates that Port 18 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 17. "PTR17CL22,Port17CL22 Enable. Indicates that Port 17 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 16. "PTR16CL22,Port16CL22 Enable. Indicates that Port 16 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 15. "PTR15CL22,Port15CL22 Enable. Indicates that Port 15 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 14. "PTR14CL22,Port14CL22 Enable. Indicates that Port 14 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 13. "PTR13CL22,Port13CL22 Enable. Indicates that Port 13 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 12. "PTR12CL22,Port12CL22 Enable. Indicates that Port 12 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 11. "PTR11CL22,Port11CL22 Enable. Indicates that Port 11 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 10. "PTR10CL22,Port10CL22 Enable. Indicates that Port 10 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 9. "PTR9CL22,Port9CL22 Enable. Indicates that Port 9 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 8. "PTR8CL22,Port8CL22 Enable. Indicates that Port 8 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 7. "PTR7CL22,Port7CL22 Enable. Indicates that Port 7 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 6. "PTR6CL22,Port6CL22 Enable. Indicates that Port 6 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 5. "PTR5CL22,Port5CL22 Enable. Indicates that Port 5 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 4. "PTR4CL22,Port4CL22 Enable. Indicates that Port 4 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 3. "PTR3CL22,Port3CL22 Enable. Indicates that Port 3 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 2. "PTR2CL22,Port2CL22 Enable. Indicates that Port 2 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 1. "PTR1CL22,Port1CL22 Enable. Indicates that Port 1 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
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bitfld.long 0x0 0. "PTR0CL22,Port0CL22 Enable. Indicates that Port 0 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
line.long 0x4 "MDIO_Port_Nx4_Indirect_Control,This register contain fields that control the Port range select for accessing register sets."
hexmask.long 0x4 3.--31. 1. "Reserved_31_3,Reserved."
newline
bitfld.long 0x4 0.--2. "PRS,Port Range Select." "0: Selects the Port address range of 0 to 3,1: Selects the Port Address range of 4 to 7,2: Selects the Port Address range of 8 to 11,3: Selects the Port Address range of 12 to 15,4: Selects the Port Address range of 16 to 19,5: Selects the Port Address range of 20 to 23,6: Selects the Port Address range of 24 to 27,7: Selects the Port Address range of 28 to 31"
group.long 0x230++0x3
line.long 0x0 "MDIO_PortNx4P0_Device_In_Use,This register gives the status of each device on Port Nx4 Plus0 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P0VSD2,VSD2 Device is in Use" "0,1"
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bitfld.long 0x0 30. "Nx4P0VSD1,VSD1 Device is in Use" "0,1"
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hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
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bitfld.long 0x0 6. "Nx4P0TC,TC Device is in Use" "0,1"
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bitfld.long 0x0 5. "Nx4P0DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P0PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P0PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P0WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P0PMDPMA,PMA Device is in Use" "0,1"
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rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x234++0x7
line.long 0x0 "MDIO_PortNx4P0_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus0 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported..."
bitfld.long 0x0 31. "Nx4P0VSD2LS,Link Status of VSD2 Device" "0,1"
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bitfld.long 0x0 30. "Nx4P0VSD1LS,Link Status of VCD1 Device" "0,1"
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hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P0TCLS,Link Status of TC Device" "0,1"
newline
bitfld.long 0x0 5. "Nx4P0DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P0PHYXSLS,Link Status of PHYXS Device" "0,1"
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bitfld.long 0x0 3. "Nx4P0PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P0WISLS,Link Status of WIS Device" "0,1"
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bitfld.long 0x0 1. "Nx4P0PMDPMALS,Link Status of PMA Device" "0,1"
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bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P0_Alive_Status,This register gives the device status in PHY Port Nx4Plus0 ((Here N is as per PRS field of 'MDIO Port Nx4 Indirect Control' register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified in.."
bitfld.long 0x4 31. "Nx4P0VSD2LS,Alive Status of VSD2 Device" "0,1"
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bitfld.long 0x4 30. "Nx4P0VSD1LS,Alive Status of VSD1 Device" "0,1"
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hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x4 6. "Nx4P0TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P0DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P0PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P0PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P0WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P0PMDPMALS,Alive Status of PMA Device" "0,1"
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bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x240++0x3
line.long 0x0 "MDIO_PortNx4P1_Device_In_Use,This register gives the status of each device on Port Nx4 Plus1 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P1VSD2,VSD2 Device is in Use" "0,1"
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bitfld.long 0x0 30. "Nx4P1VSD1,VSD1 Device is in Use" "0,1"
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hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
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bitfld.long 0x0 6. "Nx4P1TC,TC Device is in Use" "0,1"
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bitfld.long 0x0 5. "Nx4P1DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P1PHYXS,PHYXS Device is in Use" "0,1"
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bitfld.long 0x0 3. "Nx4P1PCS,PCS Device is in Use" "0,1"
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bitfld.long 0x0 2. "Nx4P1WIS,WIS Device is in Use" "0,1"
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bitfld.long 0x0 1. "Nx4P1PMDPMA,PMA Device is in Use" "0,1"
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rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x244++0x7
line.long 0x0 "MDIO_PortNx4P1_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus1 ((Here N is as per PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as.."
bitfld.long 0x0 31. "Nx4P1VSD2LS,Link Status of VSD2 Device" "0,1"
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bitfld.long 0x0 30. "Nx4P1VSD1LS,Link Status of VSD1 Device" "0,1"
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hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
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bitfld.long 0x0 6. "Nx4P1TCLS,Link Status of TC Device" "0,1"
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bitfld.long 0x0 5. "Nx4P1DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P1PHYXSLS,Link Status of PHYXS Device" "0,1"
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bitfld.long 0x0 3. "Nx4P1PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P1WISLS,Link Status of WIS Device" "0,1"
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bitfld.long 0x0 1. "Nx4P1PMDPMALS,Link Status of PMA Device" "0,1"
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bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P1_Alive_Status,This register gives the device status in PHY Port Nx4Plus1 ((Here N is as per PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified in.."
bitfld.long 0x4 31. "Nx4P1VSD2LS,Alive Status of VSD2 Device" "0,1"
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bitfld.long 0x4 30. "Nx4P1VSD1LS,Alive Status of VSD1 Device" "0,1"
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hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
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bitfld.long 0x4 6. "Nx4P1TCLS,Alive Status of TC Device" "0,1"
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bitfld.long 0x4 5. "Nx4P1DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P1PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P1PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P1WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P1PMDPMALS,Alive Status of PMA Device" "0,1"
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bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x250++0x3
line.long 0x0 "MDIO_PortNx4P2_Device_In_Use,This register gives the status of each device on Port Nx4 Plus2 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P2VSD2,VSD2 Device is in Use" "0,1"
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bitfld.long 0x0 30. "Nx4P2VSD1,VSD1 Device is in Use" "0,1"
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hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
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bitfld.long 0x0 6. "Nx4P2TC,TC Device is in Use" "0,1"
newline
bitfld.long 0x0 5. "Nx4P2DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P2PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P2PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P2WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P2PMDPMA,PMA Device is in Use" "0,1"
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rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x254++0x7
line.long 0x0 "MDIO_PortNx4P2_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus2 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported..."
bitfld.long 0x0 31. "Nx4P2VSD2LS,Link Status of VSD2 Device" "0,1"
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bitfld.long 0x0 30. "Nx4P2VSD1LS,Link Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P2TCLS,Link Status of TC Device" "0,1"
newline
bitfld.long 0x0 5. "Nx4P2DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P2PHYXSLS,Link Status of PHYXS Device" "0,1"
newline
bitfld.long 0x0 3. "Nx4P2PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P2WISLS,Link Status of WIS Device" "0,1"
newline
bitfld.long 0x0 1. "Nx4P2PMDPMALS,Link Status of PMA Device" "0,1"
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bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P2_Alive_Status,This register gives the device status in PHY Port Nx4Plus2 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified.."
bitfld.long 0x4 31. "Nx4P2VSD2LS,Alive Status of VSD2 Device" "0,1"
newline
bitfld.long 0x4 30. "Nx4P2VSD1LS,Alive Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x4 6. "Nx4P2TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P2DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P2PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P2PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P2WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P2PMDPMALS,Alive Status of PMA Device" "0,1"
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bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x260++0x3
line.long 0x0 "MDIO_PortNx4P3_Device_In_Use,This register gives the status of each device on Port Nx4 Plus3 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P3VSD2,VSD2 Device is in Use" "0,1"
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bitfld.long 0x0 30. "Nx4P3VSD1,VSD1 Device is in Use" "0,1"
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hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
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bitfld.long 0x0 6. "Nx4P3TC,TC Device is in Use" "0,1"
newline
bitfld.long 0x0 5. "Nx4P3DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P3PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P3PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P3WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P3PMDPMA,PMA Device is in Use" "0,1"
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rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x264++0x7
line.long 0x0 "MDIO_PortNx4P3_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus3 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported..."
bitfld.long 0x0 31. "Nx4P3VSD2LS,Link Status of VSD2 Device" "0,1"
newline
bitfld.long 0x0 30. "Nx4P3VSD1LS,Link Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P3TCLS,Link Status of TC Device" "0,1"
newline
bitfld.long 0x0 5. "Nx4P3DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P3PHYXSLS,Link Status of PHYXS Device" "0,1"
newline
bitfld.long 0x0 3. "Nx4P3PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P3WISLS,Link Status of WIS Device" "0,1"
newline
bitfld.long 0x0 1. "Nx4P3PMDPMALS,Link Status of PMA Device" "0,1"
newline
bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P3_Alive_Status,This register gives the device status in PHY Port Nx4Plus3 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified.."
bitfld.long 0x4 31. "Nx4P3VSD2LS,Alive Status of VSD2 Device" "0,1"
newline
bitfld.long 0x4 30. "Nx4P3VSD1LS,Alive Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x4 6. "Nx4P3TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P3DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P3PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P3PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P3WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P3PMDPMALS,Alive Status of PMA Device" "0,1"
newline
bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x278++0xB
line.long 0x0 "MAC_GPIO_Control,The GPIO Control register controls the GPIO."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--23. 1. "GPIT,GPI Type."
newline
hexmask.long.word 0x0 4.--15. 1. "Reserved_15_4,Reserved."
newline
hexmask.long.byte 0x0 0.--3. 1. "GPIE,GPI Interrupt Enable."
line.long 0x4 "MAC_GPIO_Status,The General Purpose IO register provides the control to drive the following: up to 16 bits of output ports (GPO) and status of up to 16 input ports (GPIS)."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--23. 1. "GPO,General Purpose Output."
newline
hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_y,Reserved."
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hexmask.long.byte 0x4 0.--7. 1. "GPIS,General Purpose Input Status."
line.long 0x8 "MAC_FPE_CTRL_STS,This register controls the operation of Frame Preemption."
hexmask.long.word 0x8 20.--31. 1. "Reserved_31_20,Reserved."
newline
rbitfld.long 0x8 19. "TRSP,Transmitted Respond Frame" "0,1"
newline
rbitfld.long 0x8 18. "TVER,Transmitted Verify Frame" "0,1"
newline
rbitfld.long 0x8 17. "RRSP,Received Respond Frame" "0,1"
newline
rbitfld.long 0x8 16. "RVER,Received Verify Frame" "0,1"
newline
hexmask.long.word 0x8 4.--15. 1. "Reserved_15_4,Reserved."
newline
bitfld.long 0x8 3. "ARV,Autogenerate Respond mPacket on receiving Verify mPacket" "0,1"
newline
bitfld.long 0x8 2. "SRSP,Send Respond mPacket" "0,1"
newline
bitfld.long 0x8 1. "SVER,Send Verify mPacket" "0,1"
newline
bitfld.long 0x8 0. "EFPE,Enable Tx Frame Preemption" "0,1"
group.long 0x290++0x3
line.long 0x0 "MAC_CSR_SW_Ctrl,This register contains software programmable controls for changing the CSR access response and status bits clearing."
hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved."
newline
bitfld.long 0x0 8. "SEEN,Slave Error Response Enable" "0,1"
newline
hexmask.long.byte 0x0 1.--7. 1. "Reserved_7_1,Reserved."
newline
bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1"
group.long 0x300++0xFF
line.long 0x0 "MAC_Address0_High,The MAC_Address0_High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address0_Low register."
rbitfld.long 0x0 31. "AE,Address Enable." "0,1"
newline
hexmask.long.word 0x0 19.--30. 1. "Reserved_30_y,Reserved."
newline
bitfld.long 0x0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32]."
line.long 0x4 "MAC_Address0_Low,The MAC_Address0_Low register holds the lower 32 bits of the 0th 6-byte MAC address of the station."
hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address0 [31:0]."
line.long 0x8 "MAC_Address1_High,The MAC_Address1_High register holds the upper 16 bits of the 1th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address1_Low register. For.."
bitfld.long 0x8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 1th MAC.."
newline
bitfld.long 0x8 30. "SA,Source Address." "0: The MAC Address1[47:0] is used to compare with..,1: The MAC Address1[47:0] is used to compare with.."
newline
hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32]."
line.long 0xC "MAC_Address1_Low,The MAC_Address1_Low register holds the lower 32 bits of the 1th 6-byte MAC address of the station."
hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address1 [31:0]."
line.long 0x10 "MAC_Address2_High,The MAC_Address2_High register holds the upper 16 bits of the 2th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address2_Low register. For.."
bitfld.long 0x10 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 2th MAC.."
newline
bitfld.long 0x10 30. "SA,Source Address." "0: The MAC Address2[47:0] is used to compare with..,1: The MAC Address2[47:0] is used to compare with.."
newline
hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x10 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x10 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address2 [47:32]."
line.long 0x14 "MAC_Address2_Low,The MAC_Address2_Low register holds the lower 32 bits of the 2th 6-byte MAC address of the station."
hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address2 [31:0]."
line.long 0x18 "MAC_Address3_High,The MAC_Address3_High register holds the upper 16 bits of the 3th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address3_Low register. For.."
bitfld.long 0x18 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 3th MAC.."
newline
bitfld.long 0x18 30. "SA,Source Address." "0: The MAC Address3[47:0] is used to compare with..,1: The MAC Address3[47:0] is used to compare with.."
newline
hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x18 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x18 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address3 [47:32]."
line.long 0x1C "MAC_Address3_Low,The MAC_Address3_Low register holds the lower 32 bits of the 3th 6-byte MAC address of the station."
hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address3 [31:0]."
line.long 0x20 "MAC_Address4_High,The MAC_Address4_High register holds the upper 16 bits of the 4th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address4_Low register. For.."
bitfld.long 0x20 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 4th MAC.."
newline
bitfld.long 0x20 30. "SA,Source Address." "0: The MAC Address4[47:0] is used to compare with..,1: The MAC Address4[47:0] is used to compare with.."
newline
hexmask.long.byte 0x20 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x20 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x20 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 0.--15. 1. "ADDRHI,MAC Address4 [47:32]."
line.long 0x24 "MAC_Address4_Low,The MAC_Address4_Low register holds the lower 32 bits of the 4th 6-byte MAC address of the station."
hexmask.long 0x24 0.--31. 1. "ADDRLO,MAC Address4 [31:0]."
line.long 0x28 "MAC_Address5_High,The MAC_Address5_High register holds the upper 16 bits of the 5th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address5_Low register. For.."
bitfld.long 0x28 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 5th MAC.."
newline
bitfld.long 0x28 30. "SA,Source Address." "0: The MAC Address5[47:0] is used to compare with..,1: The MAC Address5[47:0] is used to compare with.."
newline
hexmask.long.byte 0x28 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x28 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x28 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 0.--15. 1. "ADDRHI,MAC Address5 [47:32]."
line.long 0x2C "MAC_Address5_Low,The MAC_Address5_Low register holds the lower 32 bits of the 5th 6-byte MAC address of the station."
hexmask.long 0x2C 0.--31. 1. "ADDRLO,MAC Address5 [31:0]."
line.long 0x30 "MAC_Address6_High,The MAC_Address6_High register holds the upper 16 bits of the 6th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address6_Low register. For.."
bitfld.long 0x30 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 6th MAC.."
newline
bitfld.long 0x30 30. "SA,Source Address." "0: The MAC Address6[47:0] is used to compare with..,1: The MAC Address6[47:0] is used to compare with.."
newline
hexmask.long.byte 0x30 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x30 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x30 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 0.--15. 1. "ADDRHI,MAC Address6 [47:32]."
line.long 0x34 "MAC_Address6_Low,The MAC_Address6_Low register holds the lower 32 bits of the 6th 6-byte MAC address of the station."
hexmask.long 0x34 0.--31. 1. "ADDRLO,MAC Address6 [31:0]."
line.long 0x38 "MAC_Address7_High,The MAC_Address7_High register holds the upper 16 bits of the 7th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address7_Low register. For.."
bitfld.long 0x38 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 7th MAC.."
newline
bitfld.long 0x38 30. "SA,Source Address." "0: The MAC Address7[47:0] is used to compare with..,1: The MAC Address7[47:0] is used to compare with.."
newline
hexmask.long.byte 0x38 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x38 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x38 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 0.--15. 1. "ADDRHI,MAC Address7 [47:32]."
line.long 0x3C "MAC_Address7_Low,The MAC_Address7_Low register holds the lower 32 bits of the 7th 6-byte MAC address of the station."
hexmask.long 0x3C 0.--31. 1. "ADDRLO,MAC Address7 [31:0]."
line.long 0x40 "MAC_Address8_High,The MAC_Address8_High register holds the upper 16 bits of the 8th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address8_Low register. For.."
bitfld.long 0x40 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 8th MAC.."
newline
bitfld.long 0x40 30. "SA,Source Address." "0: The MAC Address8[47:0] is used to compare with..,1: The MAC Address8[47:0] is used to compare with.."
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hexmask.long.byte 0x40 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x40 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x40 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x40 0.--15. 1. "ADDRHI,MAC Address8 [47:32]."
line.long 0x44 "MAC_Address8_Low,The MAC_Address8_Low register holds the lower 32 bits of the 8th 6-byte MAC address of the station."
hexmask.long 0x44 0.--31. 1. "ADDRLO,MAC Address8 [31:0]."
line.long 0x48 "MAC_Address9_High,The MAC_Address9_High register holds the upper 16 bits of the 9th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address9_Low register. For.."
bitfld.long 0x48 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 9th MAC.."
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bitfld.long 0x48 30. "SA,Source Address." "0: The MAC Address9[47:0] is used to compare with..,1: The MAC Address9[47:0] is used to compare with.."
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hexmask.long.byte 0x48 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x48 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x48 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x48 0.--15. 1. "ADDRHI,MAC Address9 [47:32]."
line.long 0x4C "MAC_Address9_Low,The MAC_Address9_Low register holds the lower 32 bits of the 9th 6-byte MAC address of the station."
hexmask.long 0x4C 0.--31. 1. "ADDRLO,MAC Address9 [31:0]."
line.long 0x50 "MAC_Address10_High,The MAC_Address10_High register holds the upper 16 bits of the 10th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address10_Low register."
bitfld.long 0x50 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 10th MAC.."
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bitfld.long 0x50 30. "SA,Source Address." "0: The MAC Address10[47:0] is used to compare with..,1: The MAC Address10[47:0] is used to compare with.."
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hexmask.long.byte 0x50 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x50 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x50 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x50 0.--15. 1. "ADDRHI,MAC Address10 [47:32]."
line.long 0x54 "MAC_Address10_Low,The MAC_Address10_Low register holds the lower 32 bits of the 10th 6-byte MAC address of the station."
hexmask.long 0x54 0.--31. 1. "ADDRLO,MAC Address10 [31:0]."
line.long 0x58 "MAC_Address11_High,The MAC_Address11_High register holds the upper 16 bits of the 11th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address11_Low register."
bitfld.long 0x58 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 11th MAC.."
newline
bitfld.long 0x58 30. "SA,Source Address." "0: The MAC Address11[47:0] is used to compare with..,1: The MAC Address11[47:0] is used to compare with.."
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hexmask.long.byte 0x58 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x58 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x58 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x58 0.--15. 1. "ADDRHI,MAC Address11 [47:32]."
line.long 0x5C "MAC_Address11_Low,The MAC_Address11_Low register holds the lower 32 bits of the 11th 6-byte MAC address of the station."
hexmask.long 0x5C 0.--31. 1. "ADDRLO,MAC Address11 [31:0]."
line.long 0x60 "MAC_Address12_High,The MAC_Address12_High register holds the upper 16 bits of the 12th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address12_Low register."
bitfld.long 0x60 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 12th MAC.."
newline
bitfld.long 0x60 30. "SA,Source Address." "0: The MAC Address12[47:0] is used to compare with..,1: The MAC Address12[47:0] is used to compare with.."
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hexmask.long.byte 0x60 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x60 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x60 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x60 0.--15. 1. "ADDRHI,MAC Address12 [47:32]."
line.long 0x64 "MAC_Address12_Low,The MAC_Address12_Low register holds the lower 32 bits of the 12th 6-byte MAC address of the station."
hexmask.long 0x64 0.--31. 1. "ADDRLO,MAC Address12 [31:0]."
line.long 0x68 "MAC_Address13_High,The MAC_Address13_High register holds the upper 16 bits of the 13th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address13_Low register."
bitfld.long 0x68 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 13th MAC.."
newline
bitfld.long 0x68 30. "SA,Source Address." "0: The MAC Address13[47:0] is used to compare with..,1: The MAC Address13[47:0] is used to compare with.."
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hexmask.long.byte 0x68 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x68 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x68 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x68 0.--15. 1. "ADDRHI,MAC Address13 [47:32]."
line.long 0x6C "MAC_Address13_Low,The MAC_Address13_Low register holds the lower 32 bits of the 13th 6-byte MAC address of the station."
hexmask.long 0x6C 0.--31. 1. "ADDRLO,MAC Address13 [31:0]."
line.long 0x70 "MAC_Address14_High,The MAC_Address14_High register holds the upper 16 bits of the 14th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address14_Low register."
bitfld.long 0x70 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 14th MAC.."
newline
bitfld.long 0x70 30. "SA,Source Address." "0: The MAC Address14[47:0] is used to compare with..,1: The MAC Address14[47:0] is used to compare with.."
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hexmask.long.byte 0x70 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x70 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x70 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x70 0.--15. 1. "ADDRHI,MAC Address14 [47:32]."
line.long 0x74 "MAC_Address14_Low,The MAC_Address14_Low register holds the lower 32 bits of the 14th 6-byte MAC address of the station."
hexmask.long 0x74 0.--31. 1. "ADDRLO,MAC Address14 [31:0]."
line.long 0x78 "MAC_Address15_High,The MAC_Address15_High register holds the upper 16 bits of the 15th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address15_Low register."
bitfld.long 0x78 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 15th MAC.."
newline
bitfld.long 0x78 30. "SA,Source Address." "0: The MAC Address15[47:0] is used to compare with..,1: The MAC Address15[47:0] is used to compare with.."
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hexmask.long.byte 0x78 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x78 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x78 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x78 0.--15. 1. "ADDRHI,MAC Address15 [47:32]."
line.long 0x7C "MAC_Address15_Low,The MAC_Address15_Low register holds the lower 32 bits of the 15th 6-byte MAC address of the station."
hexmask.long 0x7C 0.--31. 1. "ADDRLO,MAC Address15 [31:0]."
line.long 0x80 "MAC_Address16_High,The MAC_Address16_High register holds the upper 16 bits of the 16th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address16_Low register."
bitfld.long 0x80 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 16th MAC.."
newline
bitfld.long 0x80 30. "SA,Source Address." "0: The MAC Address16[47:0] is used to compare with..,1: The MAC Address16[47:0] is used to compare with.."
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hexmask.long.byte 0x80 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x80 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x80 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x80 0.--15. 1. "ADDRHI,MAC Address16 [47:32]."
line.long 0x84 "MAC_Address16_Low,The MAC_Address16_Low register holds the lower 32 bits of the 16th 6-byte MAC address of the station."
hexmask.long 0x84 0.--31. 1. "ADDRLO,MAC Address16 [31:0]."
line.long 0x88 "MAC_Address17_High,The MAC_Address17_High register holds the upper 16 bits of the 17th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address17_Low register."
bitfld.long 0x88 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 17th MAC.."
newline
bitfld.long 0x88 30. "SA,Source Address." "0: The MAC Address17[47:0] is used to compare with..,1: The MAC Address17[47:0] is used to compare with.."
newline
hexmask.long.byte 0x88 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x88 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x88 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x88 0.--15. 1. "ADDRHI,MAC Address17 [47:32]."
line.long 0x8C "MAC_Address17_Low,The MAC_Address17_Low register holds the lower 32 bits of the 17th 6-byte MAC address of the station."
hexmask.long 0x8C 0.--31. 1. "ADDRLO,MAC Address17 [31:0]."
line.long 0x90 "MAC_Address18_High,The MAC_Address18_High register holds the upper 16 bits of the 18th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address18_Low register."
bitfld.long 0x90 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 18th MAC.."
newline
bitfld.long 0x90 30. "SA,Source Address." "0: The MAC Address18[47:0] is used to compare with..,1: The MAC Address18[47:0] is used to compare with.."
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hexmask.long.byte 0x90 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x90 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x90 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x90 0.--15. 1. "ADDRHI,MAC Address18 [47:32]."
line.long 0x94 "MAC_Address18_Low,The MAC_Address18_Low register holds the lower 32 bits of the 18th 6-byte MAC address of the station."
hexmask.long 0x94 0.--31. 1. "ADDRLO,MAC Address18 [31:0]."
line.long 0x98 "MAC_Address19_High,The MAC_Address19_High register holds the upper 16 bits of the 19th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address19_Low register."
bitfld.long 0x98 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 19th MAC.."
newline
bitfld.long 0x98 30. "SA,Source Address." "0: The MAC Address19[47:0] is used to compare with..,1: The MAC Address19[47:0] is used to compare with.."
newline
hexmask.long.byte 0x98 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x98 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x98 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x98 0.--15. 1. "ADDRHI,MAC Address19 [47:32]."
line.long 0x9C "MAC_Address19_Low,The MAC_Address19_Low register holds the lower 32 bits of the 19th 6-byte MAC address of the station."
hexmask.long 0x9C 0.--31. 1. "ADDRLO,MAC Address19 [31:0]."
line.long 0xA0 "MAC_Address20_High,The MAC_Address20_High register holds the upper 16 bits of the 20th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address20_Low register."
bitfld.long 0xA0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 20th MAC.."
newline
bitfld.long 0xA0 30. "SA,Source Address." "0: The MAC Address20[47:0] is used to compare with..,1: The MAC Address20[47:0] is used to compare with.."
newline
hexmask.long.byte 0xA0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xA0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xA0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xA0 0.--15. 1. "ADDRHI,MAC Address20 [47:32]."
line.long 0xA4 "MAC_Address20_Low,The MAC_Address20_Low register holds the lower 32 bits of the 20th 6-byte MAC address of the station."
hexmask.long 0xA4 0.--31. 1. "ADDRLO,MAC Address20 [31:0]."
line.long 0xA8 "MAC_Address21_High,The MAC_Address21_High register holds the upper 16 bits of the 21th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address21_Low register."
bitfld.long 0xA8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 21th MAC.."
newline
bitfld.long 0xA8 30. "SA,Source Address." "0: The MAC Address21[47:0] is used to compare with..,1: The MAC Address21[47:0] is used to compare with.."
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hexmask.long.byte 0xA8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xA8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xA8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xA8 0.--15. 1. "ADDRHI,MAC Address21 [47:32]."
line.long 0xAC "MAC_Address21_Low,The MAC_Address21_Low register holds the lower 32 bits of the 21th 6-byte MAC address of the station."
hexmask.long 0xAC 0.--31. 1. "ADDRLO,MAC Address21 [31:0]."
line.long 0xB0 "MAC_Address22_High,The MAC_Address22_High register holds the upper 16 bits of the 22th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address22_Low register."
bitfld.long 0xB0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 22th MAC.."
newline
bitfld.long 0xB0 30. "SA,Source Address." "0: The MAC Address22[47:0] is used to compare with..,1: The MAC Address22[47:0] is used to compare with.."
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hexmask.long.byte 0xB0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xB0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xB0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xB0 0.--15. 1. "ADDRHI,MAC Address22 [47:32]."
line.long 0xB4 "MAC_Address22_Low,The MAC_Address22_Low register holds the lower 32 bits of the 22th 6-byte MAC address of the station."
hexmask.long 0xB4 0.--31. 1. "ADDRLO,MAC Address22 [31:0]."
line.long 0xB8 "MAC_Address23_High,The MAC_Address23_High register holds the upper 16 bits of the 23th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address23_Low register."
bitfld.long 0xB8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 23th MAC.."
newline
bitfld.long 0xB8 30. "SA,Source Address." "0: The MAC Address23[47:0] is used to compare with..,1: The MAC Address23[47:0] is used to compare with.."
newline
hexmask.long.byte 0xB8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xB8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xB8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xB8 0.--15. 1. "ADDRHI,MAC Address23 [47:32]."
line.long 0xBC "MAC_Address23_Low,The MAC_Address23_Low register holds the lower 32 bits of the 23th 6-byte MAC address of the station."
hexmask.long 0xBC 0.--31. 1. "ADDRLO,MAC Address23 [31:0]."
line.long 0xC0 "MAC_Address24_High,The MAC_Address24_High register holds the upper 16 bits of the 24th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address24_Low register."
bitfld.long 0xC0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 24th MAC.."
newline
bitfld.long 0xC0 30. "SA,Source Address." "0: The MAC Address24[47:0] is used to compare with..,1: The MAC Address24[47:0] is used to compare with.."
newline
hexmask.long.byte 0xC0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xC0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xC0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xC0 0.--15. 1. "ADDRHI,MAC Address24 [47:32]."
line.long 0xC4 "MAC_Address24_Low,The MAC_Address24_Low register holds the lower 32 bits of the 24th 6-byte MAC address of the station."
hexmask.long 0xC4 0.--31. 1. "ADDRLO,MAC Address24 [31:0]."
line.long 0xC8 "MAC_Address25_High,The MAC_Address25_High register holds the upper 16 bits of the 25th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address25_Low register."
bitfld.long 0xC8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 25th MAC.."
newline
bitfld.long 0xC8 30. "SA,Source Address." "0: The MAC Address25[47:0] is used to compare with..,1: The MAC Address25[47:0] is used to compare with.."
newline
hexmask.long.byte 0xC8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xC8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xC8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xC8 0.--15. 1. "ADDRHI,MAC Address25 [47:32]."
line.long 0xCC "MAC_Address25_Low,The MAC_Address25_Low register holds the lower 32 bits of the 25th 6-byte MAC address of the station."
hexmask.long 0xCC 0.--31. 1. "ADDRLO,MAC Address25 [31:0]."
line.long 0xD0 "MAC_Address26_High,The MAC_Address26_High register holds the upper 16 bits of the 26th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address26_Low register."
bitfld.long 0xD0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 26th MAC.."
newline
bitfld.long 0xD0 30. "SA,Source Address." "0: The MAC Address26[47:0] is used to compare with..,1: The MAC Address26[47:0] is used to compare with.."
newline
hexmask.long.byte 0xD0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xD0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xD0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xD0 0.--15. 1. "ADDRHI,MAC Address26 [47:32]."
line.long 0xD4 "MAC_Address26_Low,The MAC_Address26_Low register holds the lower 32 bits of the 26th 6-byte MAC address of the station."
hexmask.long 0xD4 0.--31. 1. "ADDRLO,MAC Address26 [31:0]."
line.long 0xD8 "MAC_Address27_High,The MAC_Address27_High register holds the upper 16 bits of the 27th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address27_Low register."
bitfld.long 0xD8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 27th MAC.."
newline
bitfld.long 0xD8 30. "SA,Source Address." "0: The MAC Address27[47:0] is used to compare with..,1: The MAC Address27[47:0] is used to compare with.."
newline
hexmask.long.byte 0xD8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xD8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xD8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xD8 0.--15. 1. "ADDRHI,MAC Address27 [47:32]."
line.long 0xDC "MAC_Address27_Low,The MAC_Address27_Low register holds the lower 32 bits of the 27th 6-byte MAC address of the station."
hexmask.long 0xDC 0.--31. 1. "ADDRLO,MAC Address27 [31:0]."
line.long 0xE0 "MAC_Address28_High,The MAC_Address28_High register holds the upper 16 bits of the 28th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address28_Low register."
bitfld.long 0xE0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 28th MAC.."
newline
bitfld.long 0xE0 30. "SA,Source Address." "0: The MAC Address28[47:0] is used to compare with..,1: The MAC Address28[47:0] is used to compare with.."
newline
hexmask.long.byte 0xE0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xE0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xE0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xE0 0.--15. 1. "ADDRHI,MAC Address28 [47:32]."
line.long 0xE4 "MAC_Address28_Low,The MAC_Address28_Low register holds the lower 32 bits of the 28th 6-byte MAC address of the station."
hexmask.long 0xE4 0.--31. 1. "ADDRLO,MAC Address28 [31:0]."
line.long 0xE8 "MAC_Address29_High,The MAC_Address29_High register holds the upper 16 bits of the 29th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address29_Low register."
bitfld.long 0xE8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 29th MAC.."
newline
bitfld.long 0xE8 30. "SA,Source Address." "0: The MAC Address29[47:0] is used to compare with..,1: The MAC Address29[47:0] is used to compare with.."
newline
hexmask.long.byte 0xE8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xE8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xE8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xE8 0.--15. 1. "ADDRHI,MAC Address29 [47:32]."
line.long 0xEC "MAC_Address29_Low,The MAC_Address29_Low register holds the lower 32 bits of the 29th 6-byte MAC address of the station."
hexmask.long 0xEC 0.--31. 1. "ADDRLO,MAC Address29 [31:0]."
line.long 0xF0 "MAC_Address30_High,The MAC_Address30_High register holds the upper 16 bits of the 30th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address30_Low register."
bitfld.long 0xF0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 30th MAC.."
newline
bitfld.long 0xF0 30. "SA,Source Address." "0: The MAC Address30[47:0] is used to compare with..,1: The MAC Address30[47:0] is used to compare with.."
newline
hexmask.long.byte 0xF0 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xF0 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xF0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xF0 0.--15. 1. "ADDRHI,MAC Address30 [47:32]."
line.long 0xF4 "MAC_Address30_Low,The MAC_Address30_Low register holds the lower 32 bits of the 30th 6-byte MAC address of the station."
hexmask.long 0xF4 0.--31. 1. "ADDRLO,MAC Address30 [31:0]."
line.long 0xF8 "MAC_Address31_High,The MAC_Address31_High register holds the upper 16 bits of the 31th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address31_Low register."
bitfld.long 0xF8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 31th MAC.."
newline
bitfld.long 0xF8 30. "SA,Source Address." "0: The MAC Address31[47:0] is used to compare with..,1: The MAC Address31[47:0] is used to compare with.."
newline
hexmask.long.byte 0xF8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0xF8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0xF8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xF8 0.--15. 1. "ADDRHI,MAC Address31 [47:32]."
line.long 0xFC "MAC_Address31_Low,The MAC_Address31_Low register holds the lower 32 bits of the 31th 6-byte MAC address of the station."
hexmask.long 0xFC 0.--31. 1. "ADDRLO,MAC Address31 [31:0]."
group.long 0x700++0x7
line.long 0x0 "MAC_Indir_Access_Ctrl,This register provides the Indirect Access control and status for MAC_<MSEL>_IndReg(#AOFF) registers."
bitfld.long 0x0 31. "SNPS_R,Synopsys Reserved" "0,1"
newline
rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
hexmask.long.byte 0x0 26.--29. 1. "MSEL,Mode Select"
newline
rbitfld.long 0x0 24.--25. "Reserved_25_24,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--23. 1. "Reserved_23_x,Reserved"
newline
hexmask.long.byte 0x0 8.--15. 1. "AOFF,Address Offset"
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 5. "AUTO,Auto increment" "0,1"
newline
rbitfld.long 0x0 2.--4. "Reserved_4_2,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1. "COM,Command type" "0,1"
newline
bitfld.long 0x0 0. "OB,Operation Busy" "0,1"
line.long 0x4 "MAC_Indir_Access_Data,This register holds the read/write data for Indirect Access of MAC_<MSEL_IndReg(#AOFF) registers."
hexmask.long 0x4 0.--31. 1. "DATA,This field contains data to read/write for Indirect address access associated with MAC_Indir_Access_Ctrl register."
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg0,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg1,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg10,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg11,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg12,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg13,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg14,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg15,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg16,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg17,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg18,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg19,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg2,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg20,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg21,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg22,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg23,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg24,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg25,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg26,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg27,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg28,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg29,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg3,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg30,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg31,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg4,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg5,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg6,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg7,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg8,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg9,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x800++0x3
line.long 0x0 "MMC_Control,The MMC Control register establishes the operating mode of the management counters."
hexmask.long.word 0x0 19.--31. 1. "Reserved_31_19,Reserved."
newline
rbitfld.long 0x0 16.--18. "Reserved_PRMMCSEL,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "CNTPRST,Counters Preset" "0,1"
newline
rbitfld.long 0x0 6. "Reserved_6,Reserved." "0,1"
newline
bitfld.long 0x0 4.--5. "MCT,MMC Counter Threshold" "0: Reserved,1: One-quarter the maximum value,2: One-half of the maximum value,3: Three-quarters of the maximum value"
newline
bitfld.long 0x0 3. "MCF,MMC Counter Freeze" "0,1"
newline
bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1"
newline
bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1"
newline
bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1"
rgroup.long 0x804++0x7
line.long 0x0 "MMC_Rx_Interrupt,The MMC Receive Interrupt Status register maintains the interrupts generated when receive statistic counters reach the threshold programmed in the MMC control register. When the MMC counter that caused the interrupt is read. the.."
bitfld.long 0x0 31. "RXPRMMCIS,Rx Priority MMC Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
bitfld.long 0x0 29. "SGFPIS,SGF Fail Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 28. "SGPPIS,SGF Pass Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 27. "RXALEPIS,Rx Alignment Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 26. "RXLPITRCIS,Rx LPI Transition Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 25. "RXLPIUSCIS,Rx LPI microsecond Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 24. "RXDISOCGBIS,Rx Good Bad Discarded Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 23. "RXDISPCGBIS,Rx Good Bad Discarded Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 22. "RXWDOGPIS,Rx Watchdog Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 21. "RXVLANGBPIS,Rx Good Bad VLAN Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 20. "RXFOVPIS,Rx Queue Overflow Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 19. "RXPAUSPIS,Rx Pause Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "RXORANGEPIS,Rx Out-of-Range Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "RXLENERPIS,Rx Length Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "RXUCGPIS,Rx Good Unicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 15. "RX1024TMAXOCTGBPIS,Rx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 14. "RX512T1023OCTGBPIS,Rx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 13. "RX256T511OCTGBPIS,Rx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 12. "RX128T255OCTGBPIS,Rx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 11. "RX65T127OCTGBPIS,Rx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "RX64OCTGBPIS,Rx Good Bad 64 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "RXOSIZEGPIS,Rx Good Oversize Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "RXUSIZEGPIS,Rx Good Undersize Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 7. "RXJABERPIS,Rx Jabber Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "RXRUNTPIS,Rx Runt Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "RXCRCERPIS,Rx CRC Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "RXMCGPIS,Rx Good Multicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "RXBCGPIS,Rx Good Broadcast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "RXGOCTIS,Rx Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "RXGBOCTIS,Rx Good Bad Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "RXGBPKTIS,Rx Good Bad Packet Counter Interrupt Status" "0,1"
line.long 0x4 "MMC_Tx_Interrupt,The MMC Transmit Interrupt Status register maintains the interrupts generated when the transmit statistic counters reach the threshold value programmed in MMC control register (for example. the counter's MSB is set). This register is 32.."
bitfld.long 0x4 31. "TXPRMMCIS,Tx Priority MMC Counter Interrupt Status" "0,1"
newline
hexmask.long.byte 0x4 27.--30. 1. "Reserved_30_27,Reserved."
newline
bitfld.long 0x4 26. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 25. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 24. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 23. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 22. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 21. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 20. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 19. "TXLPITRCIS,Tx LPI Transition Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 18. "TXLPIUSCIS,Tx LPI microsecond Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 17. "TXVLANGPIS,Tx Good VLAN Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 16. "TXPAUSPIS,Tx Pause Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 15. "TXGPKTIS,Tx Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 14. "TXGOCTIS,Tx Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 13. "TXUFLOWERPIS,Tx Underflow Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 12. "TXBCGBPIS,Tx Good Bad Broadcast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 11. "TXMCGBPIS,Tx Good Bad Multicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 10. "TXUCGBPIS,Tx Good Bad Unicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 9. "TX1024TMAXOCTGBPIS,Tx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 8. "TX512T1023OCTGBPIS,Tx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 7. "TX256T511OCTGBPIS,Tx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 6. "TX128T255OCTGBPIS,Tx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 5. "TX65T127OCTGBPIS,Tx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 4. "TX64OCTGBPIS,Tx Good Bad 64 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 3. "TXMCGPIS,Tx Good Multicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 2. "TXBCGPIS,Tx Good Broadcast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 1. "TXGBPKTIS,Tx Good Bad Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 0. "TXGBOCTIS,Tx Good Bad Octet Counter Interrupt Status" "0,1"
group.long 0x80C++0x7
line.long 0x0 "MMC_Receive_Interrupt_Enable,The MMC Receive Interrupt Enable register maintains the enables for the interrupts generated when receive statistic counters reach the threshold value programmed in the MMC Control register. This register is 32 bits wide."
rbitfld.long 0x0 31. "Reserved_RXPRMMCIE,Reserved." "0,1"
newline
rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
rbitfld.long 0x0 29. "Reserved_SGFPIE,Reserved." "0,1"
newline
rbitfld.long 0x0 28. "Reserved_SGPPIE,Reserved." "0,1"
newline
bitfld.long 0x0 27. "RXALEPIE,Rx Alignment Error Packet Counter Interrupt Enable" "0,1"
newline
rbitfld.long 0x0 26. "Reserved_RXLPITRCIE,Reserved." "0,1"
newline
rbitfld.long 0x0 25. "Reserved_RXLPIUSCIE,Reserved." "0,1"
newline
bitfld.long 0x0 24. "RXDISOCGBIE,Rx Discard Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 23. "RXDISPCGBIE,Rx Discard Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 22. "RXWDOGPIE,Rx Watchdog Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 21. "RXVLANGBPIE,Rx Good Bad VLAN Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 20. "RXFOVPIE,Rx Queue Overflow Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 19. "RXPAUSPIE,Rx Pause Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 18. "RXORANGEPIE,Rx Out-of-Range Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 17. "RXLENERPIE,Rx Length Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 16. "RXUCGPIE,Rx Good Unicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 15. "RX1024TMAXOCTGBPIE,Rx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 14. "RX512T1023OCTGBPIE,Rx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 13. "RX256T511OCTGBPIE,Rx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 12. "RX128T255OCTGBPIE,Rx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 11. "RX65T127OCTGBPIE,Rx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 10. "RX64OCTGBPIE,Rx Good Bad 64 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 9. "RXOSIZEGPIE,Rx Good Oversize Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 8. "RXUSIZEGPIE,Rx Good Undersize Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 7. "RXJABERPIE,Rx Jabber Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 6. "RXRUNTPIE,Rx Runt Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 5. "RXCRCERPIE,Rx CRC Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 4. "RXMCGPIE,Rx Good Multicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 3. "RXBCGPIE,Rx Good Broadcast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "RXGOCTIE,Rx Good Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 1. "RXGBOCTIE,Rx Good Bad Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "RXGBPKTIE,Rx Good Bad Packet Counter Interrupt Enable" "0,1"
line.long 0x4 "MMC_Transmit_Interrupt_Enable,The MMC Transmit Interrupt Enable register maintains the enables for the interrupts generated when transmit statistic counters reach the threshold value programmed in the MMC Control register. This register is 32 bits wide."
rbitfld.long 0x4 31. "Reserved_TXPRMMCIE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 27.--30. 1. "Reserved_30_27,Reserved."
newline
bitfld.long 0x4 26. "TXEXDEFPIE,MMC Transmit Excessive Deferral Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 25. "TXCARERPIE,MMC Transmit Carrier Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 24. "TXEXCOLPIE,MMC Transmit Excessive Collision Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 23. "TXLATCOLPIE,MMC Transmit Late Collision Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 22. "TXDEFPIE,MMC Transmit Deferred Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 21. "TXMCOLGPIE,MMC Transmit Multiple Collision Good Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 20. "TXSCOLGPIE,MMC Transmit Single Collision Good Packet Counter Interrupt Enable" "0,1"
newline
rbitfld.long 0x4 19. "Reserved_TXLPITRCIE,Reserved." "0,1"
newline
rbitfld.long 0x4 18. "Reserved_TXLPIUSCIE,Reserved." "0,1"
newline
bitfld.long 0x4 17. "TXVLANGPIE,Tx Good VLAN Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 16. "TXPAUSPIE,Tx Pause Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 15. "TXGPKTIE,Tx Good Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 14. "TXGOCTIE,Tx Good Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 13. "TXUFLOWERPIE,Tx Underflow Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 12. "TXBCGBPIE,Tx Good Bad Broadcast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 11. "TXMCGBPIE,Tx Good Bad Multicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 10. "TXUCGBPIE,Tx Good Bad Unicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 9. "TX1024TMAXOCTGBPIE,Tx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 8. "TX512T1023OCTGBPIE,Tx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 7. "TX256T511OCTGBPIE,Tx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 6. "TX128T255OCTGBPIE,Tx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 5. "TX65T127OCTGBPIE,Tx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 4. "TX64OCTGBPIE,Tx Good Bad 64 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 3. "TXMCGPIE,Tx Good Multicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 2. "TXBCGPIE,Tx Good Broadcast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 1. "TXGBPKTIE,Tx Good Bad Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 0. "TXGBOCTIE,Tx Good Bad Octet Counter Interrupt Enable" "0,1"
rgroup.long 0x814++0xB
line.long 0x0 "Tx_Octet_Count_Good_Bad_Low,This register provides lower 32 bits of transmitted octet count. excluding preamble. in good and bad packets."
hexmask.long 0x0 0.--31. 1. "TXOCTGBLO,Tx Good Bad Octet Count Low"
line.long 0x4 "Tx_Octet_Count_Good_Bad_High,This register provides upper 32 bits of transmitted octet count. excluding preamble. in good and bad packets."
hexmask.long 0x4 0.--31. 1. "TXOCTGBHI,Tx Good Bad Octet Count High"
line.long 0x8 "Tx_Packet_Count_Good_Bad_Low,This register provides lower 32 bits of transmitted good and bad packet count."
hexmask.long 0x8 0.--31. 1. "TXPKTGBLO,Tx Good Bad Packet Count Low"
rgroup.long 0x824++0x3
line.long 0x0 "Tx_Broadcast_Packets_Good_Low,This register provides lower 32 bits of transmitted good broadcast packets count."
hexmask.long 0x0 0.--31. 1. "TXBCASTGLO,Tx Good Broadcast Packet Count Low."
rgroup.long 0x82C++0x3
line.long 0x0 "Tx_Multicast_Packets_Good_Low,This register provides lower 32 bits of transmitted good multicast packets count."
hexmask.long 0x0 0.--31. 1. "TXMCASTGLO,Tx Good Multicast Packet Count Low"
rgroup.long 0x834++0x3
line.long 0x0 "Tx_64Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 64 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX64OCTGBLO,Tx Good Bad 64 Octet Size Packet Count Low"
rgroup.long 0x83C++0x3
line.long 0x0 "Tx_65To127Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 65-to-127 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX65_127OCTGBLO,Tx Good Bad 65-to-127 Octet Size Packet Count Low"
rgroup.long 0x844++0x3
line.long 0x0 "Tx_128To255Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 128-to-255 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX128_255OCTGBLO,Tx Good Bad 128-to-255 Octet Size Packet Count Low"
rgroup.long 0x84C++0x3
line.long 0x0 "Tx_256To511Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 256-to-511 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX256_511OCTGBLO,Tx Good Bad 256-to-511 Octet Size Packet Count Low"
rgroup.long 0x854++0x3
line.long 0x0 "Tx_512To1023Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 512-to-1023 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX512_1023OCTGBLO,Tx Good Bad 512-to-1023 Octet Size Packet Count Low"
rgroup.long 0x85C++0x3
line.long 0x0 "Tx_1024ToMaxOctets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 1024-tomaxsize octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX1024_MAXOCTGBLO,Tx Good Bad 1024-tomaxsize Octet Size Packet Count Low"
rgroup.long 0x864++0x3
line.long 0x0 "Tx_Unicast_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted good bad unicast packets count."
hexmask.long 0x0 0.--31. 1. "TXUCASTGBLO,Tx Good Bad Unicast Packet Count Low"
rgroup.long 0x86C++0x3
line.long 0x0 "Tx_Multicast_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted good bad multicast packets count."
hexmask.long 0x0 0.--31. 1. "TXMCASTGBLO,Tx Good Bad Multicast Packet Count Low"
rgroup.long 0x874++0x3
line.long 0x0 "Tx_Broadcast_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted good bad broadcast packets count."
hexmask.long 0x0 0.--31. 1. "TXBCASTGBLO,Tx Good Bad Broadcast Packet Count Low"
rgroup.long 0x87C++0x3
line.long 0x0 "Tx_Underflow_Error_Packets_Low,This register provides lower 32 bits of transmitted packets aborted due to packet underflow error count."
hexmask.long 0x0 0.--31. 1. "TXUNDRFLWLO,Tx Underflow Error Packet Count Low"
rgroup.long 0x884++0xB
line.long 0x0 "Tx_Octet_Count_Good_Low,This register provides lower 32 bits of transmitted good octets count."
hexmask.long 0x0 0.--31. 1. "TXOCTGLO,Tx Good Octet Count Low"
line.long 0x4 "Tx_Octet_Count_Good_High,This register provides upper 32 bits of transmitted good octets count."
hexmask.long 0x4 0.--31. 1. "TXOCTGHI,Tx Good Octet Count High"
line.long 0x8 "Tx_Packet_Count_Good_Low,This register provides lower 32 bits of transmitted good packets count."
hexmask.long 0x8 0.--31. 1. "TXPKTGLO,Tx Good Packet Count Low"
rgroup.long 0x894++0x3
line.long 0x0 "Tx_Pause_Packets_Low,This register provides lower 32 bits of transmitted Pause packets count."
hexmask.long 0x0 0.--31. 1. "TXPAUSEGLO,Tx Pause Packet Count Low"
rgroup.long 0x89C++0x3
line.long 0x0 "Tx_VLAN_Packets_Good_Low,This register provides lower 32 bits of transmitted good VLAN packets count."
hexmask.long 0x0 0.--31. 1. "TXVLANGLO,Tx Good VLAN Packet Count Low"
rgroup.long 0x900++0x3
line.long 0x0 "Rx_Packet_Count_Good_Bad_Low,This register provides lower 32 bits of received good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RXPKTGBLO,Rx Good Bad Packet Count Low"
rgroup.long 0x908++0x13
line.long 0x0 "Rx_Octet_Count_Good_Bad_Low,This register provides lower 32 bits of received octet count. excluding preamble. in good and bad packets."
hexmask.long 0x0 0.--31. 1. "RXOCTGBLO,Rx Good Bad Octet Count Low"
line.long 0x4 "Rx_Octet_Count_Good_Bad_High,This register provides upper 32 bits of received octet count. excluding preamble. in good and bad packets."
hexmask.long 0x4 0.--31. 1. "RXOCTGBHI,Rx Good Bad Octet Count High"
line.long 0x8 "Rx_Octet_Count_Good_Low,This register provides lower 32 bits of received good octets count."
hexmask.long 0x8 0.--31. 1. "RXOCTGLO,Rx Good Octet Count Low"
line.long 0xC "Rx_Octet_Count_Good_High,This register provides upper 32 bits of received good octets count."
hexmask.long 0xC 0.--31. 1. "RXOCTGHI,Rx Good Octet Count High"
line.long 0x10 "Rx_Broadcast_Packets_Good_Low,This register provides lower 32 bits of received good broadcast packets count."
hexmask.long 0x10 0.--31. 1. "RXBCASTGLO,Rx Good Broadcast Packet Count Low"
rgroup.long 0x920++0x3
line.long 0x0 "Rx_Multicast_Packets_Good_Low,This register provides lower 32 bits of received good multicast packets count."
hexmask.long 0x0 0.--31. 1. "RXMCASTGLO,Rx Good Multicast Packet Count Low"
rgroup.long 0x928++0x3
line.long 0x0 "Rx_CRC_Error_Packets_Low,This register provides lower 32 bits of received packets with CRC error count."
hexmask.long 0x0 0.--31. 1. "RXCRCERLO,Rx CRC Error Packet Count Low"
rgroup.long 0x930++0x13
line.long 0x0 "Rx_Runt_Error_Packets,This register provides received packets with Runt error count."
hexmask.long 0x0 0.--31. 1. "RXRUNTER,Rx Runt Error Packet Count"
line.long 0x4 "Rx_Jabber_Error_Packets,This register provides received packets with Jabber error count."
hexmask.long 0x4 0.--31. 1. "RXJABERER,Rx Jabber Error Packet Count"
line.long 0x8 "Rx_Undersize_Packets_Good,This register provides count of received good undersize packets."
hexmask.long 0x8 0.--31. 1. "RXUSIZEG,Rx Good Undersize Packet Count"
line.long 0xC "Rx_Oversize_Packets_Good,This register provides count of received good oversize packets."
hexmask.long 0xC 0.--31. 1. "RXOSIZEG,Rx Good Oversize Packet Count"
line.long 0x10 "Rx_64Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 64 octet size good and bad packets count."
hexmask.long 0x10 0.--31. 1. "RX64OCTGBLO,Rx Good Bad 64 Octet Size Packet Count Low"
rgroup.long 0x948++0x3
line.long 0x0 "Rx_65To127Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 65-to-127 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX65_127OCTGBLO,Rx Good Bad 65-to-127 Octet Size Packet Count Low"
rgroup.long 0x950++0x3
line.long 0x0 "Rx_128To255Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 128-to-255 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX128_255OCTGBLO,Rx Good Bad 128-to-255 Octet Size Packet Count Low"
rgroup.long 0x958++0x3
line.long 0x0 "Rx_256To511Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 256-to-511 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX256_511OCTGBLO,Rx Good Bad 256-to-511 Octet Size Packet Count Low"
rgroup.long 0x960++0x3
line.long 0x0 "Rx_512To1023Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 512-to-1023 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX512_1023OCTGBLO,Rx Good Bad 512-to-1023 Octet Size Packet Count Low"
rgroup.long 0x968++0x3
line.long 0x0 "Rx_1024ToMaxOctets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 1024-tomaxsize octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX1024_MAXOCTGBLO,Rx Good Bad 1024-tomaxsize Octet Size Packet Count Low"
rgroup.long 0x970++0x3
line.long 0x0 "Rx_Unicast_Packets_Good_Low,This register provides lower 32 bits of received good unicast packets count."
hexmask.long 0x0 0.--31. 1. "RXUCASTGLO,Rx Good Unicast Packet Count Low"
rgroup.long 0x978++0x3
line.long 0x0 "Rx_Length_Error_Packets_Low,This register provides lower 32 bits of received packets with Length error count."
hexmask.long 0x0 0.--31. 1. "RXLENERRLO,Rx Length Error Packet Count Low"
rgroup.long 0x980++0x3
line.long 0x0 "Rx_OutofRange_Packets_Low,This register provides lower 32 bits of received packets with out of range length field count."
hexmask.long 0x0 0.--31. 1. "RXORANGELO,Rx Out of Range Packet Count Low"
rgroup.long 0x988++0x3
line.long 0x0 "Rx_Pause_Packets_Low,This register provides lower 32 bits of received Pause packets count."
hexmask.long 0x0 0.--31. 1. "RXPAUSELO,Rx Pause Packet Count Low"
rgroup.long 0x990++0x3
line.long 0x0 "Rx_FIFOOverflow_Packets_Low,This register provides lower 32 bits of received packets count that had Rx Queue overflow."
hexmask.long 0x0 0.--31. 1. "RXFOVFLO,Rx FIFO Overflow Packet Count Low"
rgroup.long 0x998++0x3
line.long 0x0 "Rx_VLAN_Packets_Good_Bad_Low,This register provides lower 32 bits of received good bad VLAN packets count."
hexmask.long 0x0 0.--31. 1. "RXVLANGBLO,Rx Good Bad VLAN Packet Count Low"
rgroup.long 0x9A0++0x3
line.long 0x0 "Rx_Watchdog_Error_Packets,This register has a count of packets that are received with watchdog error."
hexmask.long 0x0 0.--31. 1. "RXWDOGERR,Rx Watchdog Error Packet Count"
rgroup.long 0x9AC++0x3
line.long 0x0 "Rx_Discard_Packets_Good_Bad_Low,This register provides lower 32 bits of received good bad packets count that were discarded due to filter fail."
hexmask.long 0x0 0.--31. 1. "RXDPCNTGBLO,Rx Good Bad Discard Packet Count Low"
rgroup.long 0x9B4++0xB
line.long 0x0 "Rx_Discard_Octets_Good_Bad_Low,This register provides lower 32 bits of received good bad octets count that were discarded due to filter fail."
hexmask.long 0x0 0.--31. 1. "RXDOCNTGBLO,Rx Good Bad Discard Octet Count Low"
line.long 0x4 "Rx_Discard_Octets_Good_Bad_High,This register provides upper 32 bits of received good bad octets count that were discarded due to filter fail."
hexmask.long 0x4 0.--31. 1. "RXDOCNTGBHI,Rx Good Bad Discard Octet Count High"
line.long 0x8 "Rx_Alignment_Error_Packets,This register provides the number of packets received by DWC_xgmac with alignment (dribble) error. It is valid only in 10/100 mode."
hexmask.long 0x8 0.--31. 1. "RXALIGNERR,Rx Alignment Error Packet Count"
rgroup.long 0xA00++0x3
line.long 0x0 "MMC_FPE_Tx_Interrupt,This register maintains the interrupts generated from all FPE related Transmit statistics counters. The MMC FPE Transmit Interrupt register maintains the interrupts generated when the transmit statistic counters reach the threshold.."
hexmask.long 0x0 3.--31. 1. "Reserved_31_3,Reserved."
newline
bitfld.long 0x0 2. "GOCIS,MMC Tx Gate/Window Overrun Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status" "0,1"
group.long 0xA04++0x3
line.long 0x0 "MMC_FPE_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Transmit statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.."
hexmask.long 0x0 3.--31. 1. "Reserved_31_3,Reserved."
newline
bitfld.long 0x0 2. "GOCIM,MMC Transmit Gate/Window Overrun Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask" "0,1"
rgroup.long 0xA08++0xF
line.long 0x0 "MMC_Tx_FPE_Fragment_Cntr,This register provides the number of additional mPackets transmitted due to preemption."
hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter"
line.long 0x4 "MMC_Tx_Hold_Req_Cntr,This register provides the count of number of times a hold request is given to MAC"
hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter"
line.long 0x8 "MMC_Tx_Gate_Orun_Cntr_Low,This register provides the lower 32-bits of counter that counts the number of times packets overrun the transmission gate/window."
hexmask.long 0x8 0.--31. 1. "TXGOCL,Tx Gate/Window Overrun Counter Low"
line.long 0xC "MMC_Tx_Gate_Orun_Cntr_High,This register provides the upper 32-bits of counter that counts the number of times packets overrun the transmission gate/window."
hexmask.long 0xC 0.--31. 1. "TXGOCH,Tx Gate/Window Overrun Counter High"
rgroup.long 0xA20++0x3
line.long 0x0 "MMC_FPE_Rx_Interrupt,This register maintains the interrupts generated from all FPE related Receive statistics counters. The MMC FPE Receive Interrupt register maintains the interrupts generated when receive statistic counters reach the threshold value.."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status" "0,1"
group.long 0xA24++0x3
line.long 0x0 "MMC_FPE_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask" "0,1"
rgroup.long 0xA28++0xF
line.long 0x0 "MMC_Rx_Packet_Assembly_Err_Cntr,This register provides the number of MAC frames with reassembly errors on the Receiver. due to mismatch in the Fragment Count value."
hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter"
line.long 0x4 "MMC_Rx_Packet_SMD_Err_Cntr,This register provides the number of received MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame."
hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter"
line.long 0x8 "MMC_Rx_Packet_Assembly_OK_Cntr,This register provides the number of MAC frames that were successfully reassembled and delivered to MAC."
hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter"
line.long 0xC "MMC_Rx_FPE_Fragment_Cntr,This register provides the number of additional mPackets received due to preemption."
hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter"
rgroup.long 0xA40++0x1B
line.long 0x0 "Tx_Single_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_xgmac after a single collision in the half-duplex mode."
hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets"
line.long 0x4 "Tx_Multiple_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_xgmac after multiple collisions in the half-duplex mode."
hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets"
line.long 0x8 "Tx_Deferred_Packets,This register provides the number of successfully transmitted by DWC_xgmac after a deferral in the half-duplex mode."
hexmask.long 0x8 0.--31. 1. "TXDEFRD,Tx Deferred Packets"
line.long 0xC "Tx_Late_Collision_Packets,This register provides the number of packets aborted by DWC_xgmac because of late collision error."
hexmask.long 0xC 0.--31. 1. "TXLATECOL,Tx Late Collision Packets"
line.long 0x10 "Tx_Excessive_Collision_Packets,This register provides the number of packets aborted by DWC_xgmac because of excessive (16) collision errors."
hexmask.long 0x10 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets"
line.long 0x14 "Tx_Carrier_Error_Packets,This register provides the number of packets aborted by DWC_xgmac because of carrier sense error (no carrier or loss of carrier)."
hexmask.long 0x14 0.--31. 1. "TXCARR,Tx Carrier Error Packets"
line.long 0x18 "Tx_Excessive_Deferral_Error,This register provides the number of packets aborted by DWC_xgmac because of excessive deferral error (deferred for more than two max-size packet times)."
hexmask.long 0x18 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error"
group.long 0xA5C++0x3
line.long 0x0 "MMC_IPC_Rx_Interrupt_Mask,This register maintains the mask for the interrupt generated from the receive IPC statistic counters."
rbitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 29. "RXICMPEROIM,MMC Receive ICMP Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 28. "RXICMPGOIM,MMC Receive ICMP Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 27. "RXTCPEROIM,MMC Receive TCP Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 26. "RXTCPGOIM,MMC Receive TCP Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 25. "RXUDPEROIM,MMC Receive UDP Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 24. "RXUDPGOIM,MMC Receive IPv6 No Payload Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 23. "RXIPV6NOPAYOIM,MMC Receive IPv6 Header Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 22. "RXIPV6HEROIM,MMC Receive IPv6 Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 21. "RXIPV6GOIM,MMC Receive IPv6 Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 20. "RXIPV4UDSBLOIM,MMC Receive IPv4 UDP Checksum Disabled Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 19. "RXIPV4FRAGOIM,MMC Receive IPv4 Fragmented Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 18. "RXIPV4NOPAYOIM,MMC Receive IPv4 No Payload Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 17. "RXIPV4HEROIM,MMC Receive IPv4 Header Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 16. "RXIPV4GOIM,MMC Receive IPv4 Good Octet Counter Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 13. "RXICMPERPIM,MMC Receive ICMP Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 12. "RXICMPGPIM,MMC Receive ICMP Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 11. "RXTCPERPIM,MMC Receive TCP Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 10. "RXTCPGPIM,MMC Receive TCP Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 9. "RXUDPERPIM,MMC Receive UDP Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 8. "RXUDPGPIM,MMC Receive UDP Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 7. "RXIPV6NOPAYPIM,MMC Receive IPv6 No Payload Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 6. "RXIPV6HERPIM,MMC Receive IPv6 Header Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 5. "RXIPV6GPIM,MMC Receive IPv6 Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 4. "RXIPV4UDSBLPIM,MMC Receive IPv4 UDP Checksum Disabled Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXIPV4FRAGPIM,MMC Receive IPv4 Fragmented Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXIPV4NOPAYPIM,MMC Receive IPv4 No Payload Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "RXIPV4HERPIM,MMC Receive IPv4 Header Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "RXIPV4GPIM,MMC Receive IPv4 Good Packet Counter Interrupt Mask" "0,1"
rgroup.long 0xA60++0x7
line.long 0x0 "MMC_IPC_Rx_Interrupt,This register maintains the interrupt that the receive IPC statistic counters generate."
bitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 29. "RXICMPEROIS,MMC Receive ICMP Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 28. "RXICMPGOIS,MMC Receive ICMP Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 27. "RXTCPEROIS,MMC Receive TCP Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 26. "RXTCPGOIS,MMC Receive TCP Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 25. "RXUDPEROIS,MMC Receive UDP Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 24. "RXUDPGOIS,MMC Receive UDP Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 23. "RXIPV6NOPAYOIS,MMC Receive IPv6 No Payload Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 22. "RXIPV6HEROIS,MMC Receive IPv6 Header Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 21. "RXIPV6GOIS,MMC Receive IPv6 Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 20. "RXIPV4UDSBLOIS,MMC Receive IPv4 UDP Checksum Disabled Octet Counter Interrupt" "0,1"
newline
bitfld.long 0x0 19. "RXIPV4FRAGOIS,MMC Receive IPv4 Fragmented Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "RXIPV4NOPAYOIS,MMC Receive IPv4 No Payload Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "RXIPV4HEROIS,MMC Receive IPv4 Header Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "RXIPV4GOIS,MMC Receive IPv4 Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 13. "RXICMPERPIS,MMC Receive ICMP Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 12. "RXICMPGPIS,MMC Receive ICMP Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 11. "RXTCPERPIS,MMC Receive TCP Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "RXTCPGPIS,MMC Receive TCP Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "RXUDPERPIS,MMC Receive UDP Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "RXUDPGPIS,MC Receive UDP Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 7. "RXIPV6NOPAYPIS,MMC Receive IPv6 No Payload Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "RXIPV6HERPIS,MMC Receive IPv6 Header Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "RXIPV6GPIS,MMC Receive IPV6 Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "RXIPV4UDSBLPIS,MMC Receive IPv4 UDP Checksum Disabled Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "RXIPV4FRAGPIS,MMC Receive IPv4 Fragmented Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "RXIPV4NOPAYPIS,MMC Receive IPv4 No Payload Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "RXIPV4HERPIS,MMC Receive IPv4 Header Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "RXIPV4GPIS,MMC Receive IPv4 Good Packet Counter Interrupt Status" "0,1"
line.long 0x4 "RxIPv4_Good_Packets_Low,This register provides lower 32 bits of good IPv4 datagrams received by DWC_xgmac with the TCP. UDP. or ICMP payload."
hexmask.long 0x4 0.--31. 1. "RXIPV4GDPKTLO,RxIPv4 Good Packets"
rgroup.long 0xA6C++0x3
line.long 0x0 "RxIPv4_Header_Error_Packets_Low,RxIPv4 Header Error Packets"
hexmask.long 0x0 0.--31. 1. "RXIPV4HDRERRPKTLO,RxIPv4 Header Error Packets"
rgroup.long 0xA74++0x3
line.long 0x0 "RxIPv4_No_Payload_Packets_Low,This register provides lower 32 bits of IPv4 datagram packets received by DWC_xgmac that did not have a TCP. UDP. or ICMP payload."
hexmask.long 0x0 0.--31. 1. "RXIPV4NOPAYPKTLO,RxIPv4 Payload Packets"
rgroup.long 0xA7C++0x3
line.long 0x0 "RxIPv4_Fragmented_Packets_Low,This register provides lower 32 bits of good IPv4 datagrams received by DWC_xgmac with fragmentation."
hexmask.long 0x0 0.--31. 1. "RXIPV4FRAGPKTLO,RxIPv4 Fragmented Packets"
rgroup.long 0xA84++0x3
line.long 0x0 "RxIPv4_UDP_Checksum_Disabled_Packets_Low,This register provides lower 32 bits of good IPv4 datagrams received by DWC_xgmac that had a UDP payload with checksum disabled."
hexmask.long 0x0 0.--31. 1. "RXIPV4UDSBLPKTLO,RxIPv4 UDP Checksum Disabled Packets"
rgroup.long 0xA8C++0x3
line.long 0x0 "RxIPv6_Good_Packets_Low,This register provides lower 32 bits of good IPv6 datagrams received by DWC_xgmac with the TCP. UDP. or ICMP payload."
hexmask.long 0x0 0.--31. 1. "RXIPV6GDPKTLO,RxIPv6 Good Packets"
rgroup.long 0xA94++0x3
line.long 0x0 "RxIPv6_Header_Error_Packets_Low,This register provides lower 32 bits of IPv6 datagrams received by DWC_xgmac with header (length or version mismatch) errors."
hexmask.long 0x0 0.--31. 1. "RXIPV6HDRERRPKTLO,RxIPv6 Header Error Packets"
rgroup.long 0xA9C++0x3
line.long 0x0 "RxIPv6_No_Payload_Packets_Low,This register provides lower 32 bits of IPv6 datagram packets received by DWC_xgmac that did not have a TCP. UDP. or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers."
hexmask.long 0x0 0.--31. 1. "RXIPV6NOPAYPKTLO,RxIPv6 Payload Packets"
rgroup.long 0xAA4++0x3
line.long 0x0 "RxUDP_Good_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented."
hexmask.long 0x0 0.--31. 1. "RXUDPGDPKTLO,RxUDP Good Packets"
rgroup.long 0xAAC++0x3
line.long 0x0 "RxUDP_Error_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac whose UDP payload has a checksum error."
hexmask.long 0x0 0.--31. 1. "RXUDPERRPKTLO,RxUDP Error Packets"
rgroup.long 0xAB4++0x3
line.long 0x0 "RxTCP_Good_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac with a good TCP payload."
hexmask.long 0x0 0.--31. 1. "RXTCPGDPKTLO,RxTCP Good Packets"
rgroup.long 0xABC++0x3
line.long 0x0 "RxTCP_Error_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac whose TCP payload has a checksum error."
hexmask.long 0x0 0.--31. 1. "RXTCPERRPKTLO,RxTCP Error Packets"
rgroup.long 0xAC4++0x3
line.long 0x0 "RxICMP_Good_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac with a good ICMP payload."
hexmask.long 0x0 0.--31. 1. "RXICMPGDPKTLO,RxICMP Good Packets"
rgroup.long 0xACC++0x3
line.long 0x0 "RxICMP_Error_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac whose ICMP payload has a checksum error."
hexmask.long 0x0 0.--31. 1. "RXICMPERRPKTLO,RxICMP Error Packets"
rgroup.long 0xAD4++0x3
line.long 0x0 "RxIPv4_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in good IPv4 datagrams encapsulating TCP. UDP. or ICMP data. (Ethernet header. FCS. pad. or IP pad bytes are not included in this counter."
hexmask.long 0x0 0.--31. 1. "RXIPV4GDOCTLO,RxIPv4 Good Octets"
rgroup.long 0xADC++0x3
line.long 0x0 "RxIPv4_Header_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv4 datagrams with header errors (checksum. length. version mismatch). The value in the Length field of IPv4 header is used to update this counter."
hexmask.long 0x0 0.--31. 1. "RXIPV4HDRERROCTLO,RxIPv4 Header Error Octets"
rgroup.long 0xAE4++0x3
line.long 0x0 "RxIPv4_No_Payload_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv4 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. (Ethernet.."
hexmask.long 0x0 0.--31. 1. "RXIPV4NOPAYOCTLO,RxIPv4 Payload Octets"
rgroup.long 0xAEC++0x3
line.long 0x0 "RxIPv4_Fragmented_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header. FCS. pad. or IP pad bytes are.."
hexmask.long 0x0 0.--31. 1. "RXIPV4FRAGOCTLO,RxIPv4 Fragmented Octets"
rgroup.long 0xAF4++0x3
line.long 0x0 "RxIPv4_UDP_Checksum_Disable_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. (Ethernet header. FCS. pad. or IP pad bytes are.."
hexmask.long 0x0 0.--31. 1. "RXIPV4UDSBLOCTLO,RxIPv4 UDP Checksum Disable Octets"
rgroup.long 0xAFC++0x3
line.long 0x0 "RxIPv6_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in good IPv6 datagrams encapsulating TCP. UDP. or ICMP data. (Ethernet header. FCS. pad. or IP pad bytes are not included in this counter."
hexmask.long 0x0 0.--31. 1. "RXIPV6GDOCTLO,RxIPv6 Good Octets"
rgroup.long 0xB04++0x3
line.long 0x0 "RxIPv6_Header_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv6 datagrams with header errors (length. version mismatch). The value in the Length field of IPv6 header is used to update this counter. (Ethernet.."
hexmask.long 0x0 0.--31. 1. "RXIPV6HDRERROCTLO,RxIPv6 Header Error Octets"
rgroup.long 0xB0C++0x3
line.long 0x0 "RxIPv6_No_Payload_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv6 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. (Ethernet.."
hexmask.long 0x0 0.--31. 1. "RXIPV6NOPAYOCTLO,RxIPv6 Payload Octets"
rgroup.long 0xB14++0x3
line.long 0x0 "RxUDP_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a good UDP segment. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXUDPGDOCTLO,RxUDP Good Octets"
rgroup.long 0xB1C++0x3
line.long 0x0 "RxUDP_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a UDP segment that had checksum errors. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXUDPERROCTLO,RxUDP Error Octets"
rgroup.long 0xB24++0x3
line.long 0x0 "RxTCP_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a good TCP segment. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXTCPGDOCTLO,RxTCP Good Octets"
rgroup.long 0xB2C++0x3
line.long 0x0 "RxTCP_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a TCP segment that had checksum errors. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXTCPERROCTLO,RxTCP Error Octets"
rgroup.long 0xB34++0x3
line.long 0x0 "RxICMP_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a good ICMP segment. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXICMPGDOCTLO,RxICMP Good Octets"
rgroup.long 0xB3C++0x3
line.long 0x0 "RxICMP_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a ICMP segment that had checksum errors. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXICMPERROCTLO,RxICMP Error Octets"
group.long 0xC00++0x7
line.long 0x0 "MAC_L3_L4_Address_Control,This register has the indirect address and control for accessing the Layer 3 and Layer 4 Filter registers."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.byte 0x0 8.--15. 1. "IDDR,L3_L4 Filter Address."
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved."
newline
bitfld.long 0x0 1. "TT,Transfer Type." "0,1"
newline
bitfld.long 0x0 0. "XB,Transfer Busy." "0,1"
line.long 0x4 "MAC_L3_L4_Data,This register has the indirect data and control for accessing the Layer 3 and Layer 4 Filter registers."
hexmask.long 0x4 0.--31. 1. "IDATA,Indirect Data."
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control0,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE0,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control1,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE1,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control10,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE10,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM10,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM10,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM10,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM10,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN10,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM10,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM10,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM10,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM10,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM10,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM10,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN10,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control11,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE11,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM11,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM11,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM11,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM11,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN11,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM11,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM11,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM11,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM11,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM11,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM11,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN11,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control12,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE12,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM12,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM12,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM12,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM12,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN12,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM12,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM12,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM12,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM12,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM12,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM12,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN12,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control13,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE13,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM13,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM13,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM13,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM13,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN13,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM13,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM13,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM13,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM13,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM13,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM13,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN13,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control14,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE14,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM14,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM14,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM14,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM14,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN14,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM14,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM14,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM14,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM14,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM14,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM14,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN14,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control15,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE15,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM15,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM15,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM15,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM15,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN15,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM15,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM15,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM15,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM15,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM15,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM15,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN15,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control2,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE2,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM2,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM2,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM2,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM2,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN2,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM2,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM2,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM2,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM2,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM2,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM2,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN2,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control3,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE3,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM3,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM3,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM3,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM3,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN3,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM3,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM3,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM3,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM3,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM3,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM3,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN3,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control4,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE4,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM4,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM4,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM4,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM4,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN4,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM4,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM4,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM4,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM4,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM4,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM4,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN4,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control5,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE5,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM5,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM5,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM5,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM5,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN5,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM5,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM5,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM5,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM5,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM5,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM5,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN5,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control6,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE6,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM6,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM6,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM6,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM6,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN6,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM6,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM6,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM6,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM6,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM6,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM6,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN6,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control7,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE7,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM7,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM7,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM7,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM7,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN7,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM7,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM7,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM7,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM7,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM7,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM7,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN7,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control8,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE8,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM8,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM8,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM8,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM8,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN8,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM8,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM8,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM8,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM8,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM8,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM8,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN8,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control9,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE9,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM9,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM9,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM9,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM9,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN9,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM9,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM9,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM9,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM9,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM9,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM9,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN9,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg0,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg1,For IPv4 packets. the Layer 3 Address 0 Register 1 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg10,For IPv4 packets. the Layer 3 Address 0 Register 10 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A010,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg11,For IPv4 packets. the Layer 3 Address 0 Register 11 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A011,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg12,For IPv4 packets. the Layer 3 Address 0 Register 12 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A012,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg13,For IPv4 packets. the Layer 3 Address 0 Register 13 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A013,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg14,For IPv4 packets. the Layer 3 Address 0 Register 14 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A014,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg15,For IPv4 packets. the Layer 3 Address 0 Register 15 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A015,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg2,For IPv4 packets. the Layer 3 Address 0 Register 2 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A02,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg3,For IPv4 packets. the Layer 3 Address 0 Register 3 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A03,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg4,For IPv4 packets. the Layer 3 Address 0 Register 4 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A04,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg5,For IPv4 packets. the Layer 3 Address 0 Register 5 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A05,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg6,For IPv4 packets. the Layer 3 Address 0 Register 6 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A06,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg7,For IPv4 packets. the Layer 3 Address 0 Register 7 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A07,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg8,For IPv4 packets. the Layer 3 Address 0 Register 8 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A08,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg9,For IPv4 packets. the Layer 3 Address 0 Register 9 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A09,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg0,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A10,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg1,For IPv4 packets. the Layer 3 Address 1 Register 1 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A11,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg10,For IPv4 packets. the Layer 3 Address 1 Register 10 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A110,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg11,For IPv4 packets. the Layer 3 Address 1 Register 11 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A111,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg12,For IPv4 packets. the Layer 3 Address 1 Register 12 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A112,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg13,For IPv4 packets. the Layer 3 Address 1 Register 13 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A113,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg14,For IPv4 packets. the Layer 3 Address 1 Register 14 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A114,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg15,For IPv4 packets. the Layer 3 Address 1 Register 15 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A115,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg2,For IPv4 packets. the Layer 3 Address 1 Register 2 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A12,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg3,For IPv4 packets. the Layer 3 Address 1 Register 3 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A13,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg4,For IPv4 packets. the Layer 3 Address 1 Register 4 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A14,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg5,For IPv4 packets. the Layer 3 Address 1 Register 5 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A15,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg6,For IPv4 packets. the Layer 3 Address 1 Register 6 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A16,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg7,For IPv4 packets. the Layer 3 Address 1 Register 7 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A17,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg8,For IPv4 packets. the Layer 3 Address 1 Register 8 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A18,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg9,For IPv4 packets. the Layer 3 Address 1 Register 9 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A19,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg0,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A20,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg1,The Layer 3 Address 2 Register 1 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A21,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg10,The Layer 3 Address 2 Register 10 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A210,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg11,The Layer 3 Address 2 Register 11 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A211,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg12,The Layer 3 Address 2 Register 12 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A212,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg13,The Layer 3 Address 2 Register 13 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A213,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg14,The Layer 3 Address 2 Register 14 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A214,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg15,The Layer 3 Address 2 Register 15 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A215,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg2,The Layer 3 Address 2 Register 2 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A22,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg3,The Layer 3 Address 2 Register 3 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A23,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg4,The Layer 3 Address 2 Register 4 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A24,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg5,The Layer 3 Address 2 Register 5 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A25,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg6,The Layer 3 Address 2 Register 6 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A26,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg7,The Layer 3 Address 2 Register 7 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A27,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg8,The Layer 3 Address 2 Register 8 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A28,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg9,The Layer 3 Address 2 Register 9 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A29,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg0,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A30,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg1,The Layer 3 Address 3 Register 1 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A31,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg10,The Layer 3 Address 3 Register 10 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A310,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg11,The Layer 3 Address 3 Register 11 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A311,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg12,The Layer 3 Address 3 Register 12 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A312,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg13,The Layer 3 Address 3 Register 13 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A313,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg14,The Layer 3 Address 3 Register 14 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A314,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg15,The Layer 3 Address 3 Register 15 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A315,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg2,The Layer 3 Address 3 Register 2 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A32,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg3,The Layer 3 Address 3 Register 3 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A33,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg4,The Layer 3 Address 3 Register 4 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A34,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg5,The Layer 3 Address 3 Register 5 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A35,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg6,The Layer 3 Address 3 Register 6 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A36,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg7,The Layer 3 Address 3 Register 7 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A37,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg8,The Layer 3 Address 3 Register 8 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A38,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg9,The Layer 3 Address 3 Register 9 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A39,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address0,Layer 4 Address 0 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address1,Layer 4 Address 1 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address10,Layer 4 Address 10 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP10,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP10,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address11,Layer 4 Address 11 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP11,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP11,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address12,Layer 4 Address 12 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP12,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP12,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address13,Layer 4 Address 13 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP13,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP13,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address14,Layer 4 Address 14 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP14,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP14,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address15,Layer 4 Address 15 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP15,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP15,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address2,Layer 4 Address 2 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP2,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP2,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address3,Layer 4 Address 3 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP3,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP3,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address4,Layer 4 Address 4 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP4,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP4,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address5,Layer 4 Address 5 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP5,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP5,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address6,Layer 4 Address 6 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP6,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP6,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address7,Layer 4 Address 7 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP7,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP7,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address8,Layer 4 Address 8 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP8,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP8,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address9,Layer 4 Address 9 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP9,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP9,Layer 4 Source Port Number Field."
group.long 0xC10++0x3
line.long 0x0 "MAC_ARP_Address,The ARP Address register contains the IPv4 Destination Address of the MAC. This register is available only when the Enable IPv4 ARP Offload option is selected."
hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address."
group.long 0xD00++0x7
line.long 0x0 "MAC_Timestamp_Control,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver."
rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 28. "AV8021ASMEN,AV IEEE 802.1AS Mode Enable." "0,1"
newline
rbitfld.long 0x0 25.--27. "Reserved_27_25,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 20. "Reserved_ESTI,Reserved." "0,1"
newline
bitfld.long 0x0 19. "CSC,Enable checksum correction during OST for PTP over UDP/IPv4 packets" "0,1"
newline
bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering." "0,1"
newline
bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots." "0,1,2,3"
newline
bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master." "0,1"
newline
bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages." "0,1"
newline
bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP." "0,1"
newline
bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP." "0,1"
newline
bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets." "0,1"
newline
bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format." "0,1"
newline
bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control." "0,1"
newline
bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets." "0,1"
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 5. "TSADDREG,Update Addend Register." "0,1"
newline
rbitfld.long 0x0 4. "Reserved_TSTRIG,Reserved." "0,1"
newline
bitfld.long 0x0 3. "TSUPDT,Update Timestamp." "0,1"
newline
bitfld.long 0x0 2. "TSINIT,Initialize Timestamp." "0,1"
newline
bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update." "0,1"
newline
bitfld.long 0x0 0. "TSENA,Enable Timestamp." "0,1"
line.long 0x4 "MAC_Sub_Second_Increment,The Sub-Second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in MAC_Timestamp_Control register]. the value in this register.."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value."
newline
hexmask.long.byte 0x4 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value."
newline
hexmask.long.byte 0x4 0.--7. 1. "Reserved_7_0,Reserved."
rgroup.long 0xD08++0x7
line.long 0x0 "MAC_System_Time_Seconds,The System Time-Seconds register. along with System Time-Nanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the actual.."
hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second."
line.long 0x4 "MAC_System_Time_Nanoseconds,The System Time-Nanoseconds register. along with System Time-Seconds register. indicates the current value of the system time maintained by the MAC."
bitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds."
group.long 0xD10++0xF
line.long 0x0 "MAC_System_Time_Seconds_Update,The System Time-Seconds Update register. along with the System Time-Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or.."
hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second."
line.long 0x4 "MAC_System_Time_Nanoseconds_Update,This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input."
bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time." "0,1"
newline
hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds."
line.long 0x8 "MAC_Timestamp_Addend,The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit.."
hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register."
line.long 0xC "MAC_System_Time_Higher_Word_Seconds,The System Time - Higher Word Seconds register is present only when the IEEE 1588 Timestamp feature is selected without an external timestamp input."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "TSHWR,Timestamp Higher Word Register."
rgroup.long 0xD20++0x3
line.long 0x0 "MAC_Timestamp_Status,The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected. All bits except Bits[29:25] gets cleared when the application reads this register."
bitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots."
newline
bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed." "0,1"
newline
hexmask.long.byte 0x0 20.--23. 1. "Reserved_23_20,Reserved."
newline
hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier."
newline
bitfld.long 0x0 15. "TXTSC,Tx Timestamp Captured." "0,1"
newline
hexmask.long.byte 0x0 10.--14. 1. "TTSNS,Number of Tx Timestamp Snapshots."
newline
bitfld.long 0x0 9. "TSTRGTERR3,Timestamp Target Time Error." "0,1"
newline
bitfld.long 0x0 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3." "0,1"
newline
bitfld.long 0x0 7. "TSTRGTERR2,Timestamp Target Time Error." "0,1"
newline
bitfld.long 0x0 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2." "0,1"
newline
bitfld.long 0x0 5. "TSTRGTERR1,Timestamp Target Time Error." "0,1"
newline
bitfld.long 0x0 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1." "0,1"
newline
bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error." "0,1"
newline
bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot." "0,1"
newline
bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached." "0,1"
newline
bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow." "0,1"
rgroup.long 0xD30++0xB
line.long 0x0 "MAC_Tx_Timestamp_Status_Nanoseconds,The MAC_TxTimestamp_Status_Nanoseconds register. along with MAC_TxTimestamp_Status_Seconds. gives the 64-bit timestamp captured for the PTP packet successfully transmitted by the MAC. This value is considered to be.."
bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed." "0,1"
newline
hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low."
line.long 0x4 "MAC_Tx_Timestamp_Status_Seconds,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted."
hexmask.long 0x4 0.--31. 1. "TXTSSTSHI,Transmit Timestamp Status High."
line.long 0x8 "MAC_Tx_Timestamp_Status_PktID,This register contains the PTP packet ID corresponding to the Tx Timestamp Status in MAC_TxTimestamp_Status_Nanoseconds and MAC_TxTimestamp_Status_Seconds registers. This register is available when IEEE 1588 Tx Timestamp.."
hexmask.long.tbyte 0x8 10.--31. 1. "Reserved_31_10,Reserved."
newline
hexmask.long.word 0x8 0.--9. 1. "PKTID,Packet ID."
group.long 0xD40++0x3
line.long 0x0 "MAC_Auxiliary_Control,The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved."
newline
rbitfld.long 0x0 7. "Reserved_ATSEN3,Reserved." "0,1"
newline
rbitfld.long 0x0 6. "Reserved_ATSEN2,Reserved." "0,1"
newline
bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable." "0,1"
newline
bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable." "0,1"
newline
rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear." "0,1"
rgroup.long 0xD48++0x7
line.long 0x0 "MAC_Auxiliary_Timestamp_Nanoseconds,The Auxiliary Timestamp - Nanoseconds register. along with MAC_Auxiliary_Timestamp_Seconds. gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a.."
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp Low. Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp."
line.long 0x4 "MAC_Auxiliary_Timestamp_Seconds,The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register."
hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp High. Contains the lower 32 bits of the Seconds field of the auxiliary timestamp."
group.long 0xD50++0x17
line.long 0x0 "MAC_Timestamp_Ingress_Asym_Corr,The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in some PTP messages."
hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction."
line.long 0x4 "MAC_Timestamp_Egress_Asym_Corr,The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in for some PTP message types."
hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction."
line.long 0x8 "MAC_Timestamp_Ingress_Corr_Nanosecond,The MAC Timestamp Ingress Correction Nanosecond register contains the correction value to be used with the captured timestamp value in the ingress path. This is used to compensate the errors due to timestamp.."
hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction."
line.long 0xC "MAC_Timestamp_Ingress_Corr_Subnanosecond,The MAC Timestamp Ingress Correction Sub-Nanosecond register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for ingress directions."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.byte 0xC 8.--15. 1. "TSICSNS,Timestamp Ingress Correction  sub-nanoseconds."
newline
hexmask.long.byte 0xC 0.--7. 1. "Reserved_7_0,Reserved."
line.long 0x10 "MAC_Timestamp_Egress_Corr_Nanosecond,The MAC Egress Timestamp Correction Nanosecond register contains the correction value to be used with the captured timestamp value in the egress path. This is used to compensate the errors due to timestamp.."
hexmask.long 0x10 0.--31. 1. "TSEC,Timestamp Egress Correction."
line.long 0x14 "MAC_Timestamp_Egress_Corr_Subnanosecond,The MAC Timestamp Correction Egress Sub-nanosecond register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for egress directions."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_16,Reserved."
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hexmask.long.byte 0x14 8.--15. 1. "TSECSNS,Timestamp Egress Correction  sub-nanoseconds."
newline
hexmask.long.byte 0x14 0.--7. 1. "Reserved_7_0,Reserved."
group.long 0xD70++0x3
line.long 0x0 "MAC_PPS_Control,The PPS Control register is present only when the Timestamp feature is selected and External Timestamp is not enabled."
rbitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
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rbitfld.long 0x0 29.--30. "Reserved_TRGTMODSEL3,Reserved." "0,1,2,3"
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rbitfld.long 0x0 27.--28. "Reserved_28_27,Reserved." "0,1,2,3"
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rbitfld.long 0x0 24.--26. "Reserved_PPSCMD3,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1"
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rbitfld.long 0x0 21.--22. "Reserved_TRGTMODSEL2,Reserved." "0,1,2,3"
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rbitfld.long 0x0 19.--20. "Reserved_20_19,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 16.--18. "Reserved_PPSCMD2,Reserved." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
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bitfld.long 0x0 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output." "0,1,2,3"
newline
rbitfld.long 0x0 11.--12. "Reserved_12_11,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 8.--10. "PPSCMD1,Flexible PPS1 Output Control." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
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bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output." "0: Target Time registers are programmed only for..,1: Reserved,?,?"
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bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL0_PPSCMD0,PPSCMD0: Flexible PPS Output (ptp_pps_o[0]) Control"
group.long 0xD80++0x1F
line.long 0x0 "MAC_PPS0_Target_Time_Seconds,The PPS0 Target Time Seconds register. along with PPS0 Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these.."
hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS0 Target Time Seconds Register."
line.long 0x4 "MAC_PPS0_Target_Time_Nanoseconds,The PPS0 Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected."
bitfld.long 0x4 31. "TRGTBUSY0,PPS0 Target Time Register Busy." "0,1"
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hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS0 Register."
line.long 0x8 "MAC_PPS0_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS0 Output Signal Interval."
line.long 0xC "MAC_PPS0_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS0 Output Signal Width."
line.long 0x10 "MAC_PPS1_Target_Time_Seconds,The PPS1 Target Time Seconds register. along with PPS1 Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these.."
hexmask.long 0x10 0.--31. 1. "TSTRH1,PPS1 Target Time Seconds."
line.long 0x14 "MAC_PPS1_Target_Time_Nanoseconds,This register is present only when more than one Flexible PPS output is selected while configuring the controller."
bitfld.long 0x14 31. "TRGTBUSY1,PPS1 Target Time Register Busy." "0,1"
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hexmask.long 0x14 0.--30. 1. "TTSL1,Target Time Low for PPS1 Register."
line.long 0x18 "MAC_PPS1_Interval,The PPS1 Interval register contains the number of units of sub-second increment value between the rising edges of PPS1 signal output (ptp_pps_o[1])."
hexmask.long 0x18 0.--31. 1. "PPSINT1,PPS1 Output Signal Interval."
line.long 0x1C "MAC_PPS1_Width,The PPS1 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS1 signal output (ptp_pps_o[1])."
hexmask.long 0x1C 0.--31. 1. "PPSWIDTH1,PPS1 Output Signal Width."
group.long 0xDC0++0x13
line.long 0x0 "MAC_PTO_Control,This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
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hexmask.long.byte 0x0 8.--15. 1. "DN,Domain Number."
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bitfld.long 0x0 7. "PDRDIS,Disable Peer Delay Response response generation" "0,1"
newline
bitfld.long 0x0 6. "DRRDIS,Disable PTO Delay Request/Response response generation." "0,1"
newline
bitfld.long 0x0 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger." "0,1"
newline
bitfld.long 0x0 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger." "0,1"
newline
rbitfld.long 0x0 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x0 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable." "0,1"
newline
bitfld.long 0x0 1. "ASYNCEN,Automatic PTP SYNC message Enable." "0,1"
newline
bitfld.long 0x0 0. "PTOEN,PTP Offload Enable." "0,1"
line.long 0x4 "MAC_Source_Port_Identity0,This register along with MAC_Source_Port_Identity1 and MAC_Source_Port_Identity2 contains the 80-bit Source Port Identity of the PTP node. These registers are available only when the Enable PTP Timestamp Offload feature is.."
hexmask.long 0x4 0.--31. 1. "SPI0,Source Port Identity 0."
line.long 0x8 "MAC_Source_Port_Identity1,This register along with MAC_Source_Port_Identity0 and MAC_Source_Port_Identity2 contains the 80-bit Source Port Identity of the PTP node. These registers are available only when the Enable PTP Timestamp Offload feature is.."
hexmask.long 0x8 0.--31. 1. "SPI1,Source Port Identity 1."
line.long 0xC "MAC_Source_Port_Identity2,This register along with MAC_Source_Port_Identity0 and MAC_Source_Port_Identity1 contains the 80-bit Source Port Identity of the PTP node. These registers are available only when the Enable PTP Timestamp Offload feature is.."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
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hexmask.long.word 0xC 0.--15. 1. "SPI2,Source Port Identity 2."
line.long 0x10 "MAC_Log_Message_Interval,This register contains the periodic intervals for automatic PTP packet generation. This register is available only when the Enable PTP Timestamp Offload feature is selected."
hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval."
newline
hexmask.long.word 0x10 11.--23. 1. "Reserved_23_11,Reserved."
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bitfld.long 0x10 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 0.--7. 1. "LSI,Log Sync Interval."
group.long 0x1000++0x3
line.long 0x0 "MTL_Operation_Mode,The Operation Mode register establishes the Transmit and Receive operating modes and commands."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
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bitfld.long 0x0 5.--6. "ETSALG,ETS Algorithm." "0: WRR algorithm,1: WFQ algorithm when Data Center Bridging feature..,2: DWRR algorithm when Data Center Bridging feature..,3: Reserved"
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rbitfld.long 0x0 3.--4. "Reserved_4_3,Reserved." "0,1,2,3"
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bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm." "0: Strict Priority,1: Weighted Strict Priority"
newline
rbitfld.long 0x0 1. "Reserved_FTS,Reserved." "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
group.long 0x1008++0xB
line.long 0x0 "MTL_Debug_Control,The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access."
hexmask.long.word 0x0 19.--31. 1. "Reserved_31_19,Reserved."
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rbitfld.long 0x0 18. "Reserved_EIEC,Reserved." "0,1"
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rbitfld.long 0x0 17. "Reserved_EIAEE,Reserved." "0,1"
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rbitfld.long 0x0 16. "Reserved_EIEE,Reserved." "0,1"
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rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
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bitfld.long 0x0 14. "PKTIE,Receive Packet Available Interrupt Status Enable." "0,1"
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bitfld.long 0x0 12.--13. "FIFOSEL,FIFO Selected for Access." "0: Tx FIFO,1: Descriptor cache,?,?"
newline
bitfld.long 0x0 11. "FIFOWREN,FIFO Write Enable." "0,1"
newline
bitfld.long 0x0 10. "FIFORDEN,FIFO Read Enable." "0,1"
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bitfld.long 0x0 9. "RSTSEL,Reset Pointers of Selected FIFO." "0,1"
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bitfld.long 0x0 8. "RSTALL,Reset All Pointers." "0,1"
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rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
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bitfld.long 0x0 5.--6. "PKTSTATE,Write Control Type." "0: Packet Data,1: Normal Status,?,?"
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rbitfld.long 0x0 4. "Reserved_4,Reserved." "0,1"
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bitfld.long 0x0 2.--3. "BYTEEN,Write Data Byte Enable." "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,?,?"
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bitfld.long 0x0 1. "DBGMOD,Debug Mode Access to FIFO." "0,1"
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bitfld.long 0x0 0. "FDBGEN,FIFO Debug Access Enable." "0,1"
line.long 0x4 "MTL_Debug_Status,The FIFO Debug Status register contains the status of FIFO debug access."
hexmask.long.word 0x4 16.--31. 1. "LOCR,Remaining Locations in the FIFO."
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hexmask.long.byte 0x4 9.--15. 1. "Reserved_15_9,Reserved."
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bitfld.long 0x4 8. "PKTI,Receive Packet Available Interrupt Status." "0,1"
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rbitfld.long 0x4 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x4 3.--4. "BYTEEN,Read Data Byte Enable." "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,?,?"
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rbitfld.long 0x4 1.--2. "PKTSTATE,Read Control Type." "0: Packet Data,1: Normal Status,?,?"
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rbitfld.long 0x4 0. "FIFOBUSY,FIFO Busy." "0,1"
line.long 0x8 "MTL_FIFO_Debug_Data,The FIFO Debug Data register contains the data to be written to or read from the FIFOs."
hexmask.long 0x8 0.--31. 1. "FDBGDATA,FIFO Debug Data."
rgroup.long 0x1020++0x3
line.long 0x0 "MTL_Interrupt_Status,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
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bitfld.long 0x0 23. "Reserved_MTLPIS,Reserved." "0,1"
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bitfld.long 0x0 21.--22. "Reserved_22_21,Reserved." "0,1,2,3"
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bitfld.long 0x0 20. "Reserved_SGFIS,Reserved." "0,1"
newline
bitfld.long 0x0 19. "TINS,TBS Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "ESTIS,EST (TAS- IEEE 802.1Qbv) Interrupt Status" "0,1"
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bitfld.long 0x0 17. "DBGIS,Debug Interrupt Status." "0,1"
newline
bitfld.long 0x0 16. "MACIS,MAC Interrupt Status." "0,1"
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bitfld.long 0x0 15. "Q15IS,Queue 15 Interrupt Status." "0,1"
newline
bitfld.long 0x0 14. "Q14IS,Queue 14 Interrupt Status." "0,1"
newline
bitfld.long 0x0 13. "Q13IS,Queue 13 Interrupt Status." "0,1"
newline
bitfld.long 0x0 12. "Q12IS,Queue 12 Interrupt Status." "0,1"
newline
bitfld.long 0x0 11. "Q11IS,Queue 11 Interrupt Status." "0,1"
newline
bitfld.long 0x0 10. "Q10IS,Queue 10 Interrupt Status." "0,1"
newline
bitfld.long 0x0 9. "Q9IS,Queue 9 Interrupt Status." "0,1"
newline
bitfld.long 0x0 8. "Q8IS,Queue 8 Interrupt Status." "0,1"
newline
bitfld.long 0x0 7. "Q7IS,Traffic Class/Queue 7 Interrupt Status." "0,1"
newline
bitfld.long 0x0 6. "Q6IS,Traffic Class/Queue 6 Interrupt Status." "0,1"
newline
bitfld.long 0x0 5. "Q5IS,Traffic Class/Queue 5 Interrupt Status." "0,1"
newline
bitfld.long 0x0 4. "Q4IS,Traffic Class/Queue 4 Interrupt Status." "0,1"
newline
bitfld.long 0x0 3. "Q3IS,Traffic Class/Queue 3 Interrupt Status." "0,1"
newline
bitfld.long 0x0 2. "Q2IS,Traffic Class/Queue 2 Interrupt Status." "0,1"
newline
bitfld.long 0x0 1. "Q1IS,Traffic Class/Queue 1 Interrupt Status." "0,1"
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bitfld.long 0x0 0. "Q0IS,Traffic Class/Queue 0 Interrupt Status." "0,1"
group.long 0x1030++0x7
line.long 0x0 "MTL_RxQ_DMA_Map0,The Receive Queue and DMA Channel Mapping 0 register controls the static or dynamic mapping of Receive Queues 0-3 to Receive DMA Channels."
bitfld.long 0x0 31. "Q3DDMACH,Receive Queue 3 Enabled for Dynamic DMA Channel Selection" "0,1"
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hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_y,Reserved."
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bitfld.long 0x0 24.--26. "Q3MDMACH,Receive Queue 3 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3,4: DMA Channel 4,5: DMA Channel 5,6: DMA Channel 6,7: DMA Channel 7"
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bitfld.long 0x0 23. "Q2DDMACH,Receive Queue 2 Enabled for Dynamic MA Channel Selection" "0,1"
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hexmask.long.byte 0x0 19.--22. 1. "Reserved_22_y,Reserved."
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bitfld.long 0x0 16.--18. "Q2MDMACH,Receive Queue 2 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Q1DDMACH,Receive Queue 1 Enabled for Dynamic DMA Channel Selection" "0,1"
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hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_y,Reserved."
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bitfld.long 0x0 8.--10. "Q1MDMACH,Receive Queue 1 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7. "Q0DDMACH,Receive Queue 0 Enabled for Dynamic DMA Channel Selection" "0,1"
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hexmask.long.byte 0x0 3.--6. 1. "Reserved_6_y,Reserved."
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bitfld.long 0x0 0.--2. "Q0MDMACH,Receive Queue 0 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ_DMA_Map1,The Receive Queue and DMA Channel Mapping 1 register controls the static or dynamic mapping of Receive Queues 4-7 to Receive DMA Channels."
bitfld.long 0x4 31. "Q7DDMACH,Receive Queue 7 Enabled for Dynamic DMA Channel Selection" "0,1"
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hexmask.long.byte 0x4 27.--30. 1. "Reserved_30_y,Reserved."
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bitfld.long 0x4 24.--26. "Q7MDMACH,Receive Queue 7 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 23. "Q6DDMACH,Receive Queue 6 Enabled for Dynamic MA Channel Selection" "0,1"
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hexmask.long.byte 0x4 19.--22. 1. "Reserved_22_y,Reserved."
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bitfld.long 0x4 16.--18. "Q6MDMACH,Receive Queue 6 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 15. "Q5DDMACH,Receive Queue 5 Enabled for Dynamic DMA Channel Selection" "0,1"
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hexmask.long.byte 0x4 11.--14. 1. "Reserved_14_y,Reserved."
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bitfld.long 0x4 8.--10. "Q5MDMACH,Receive Queue 5 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 7. "Q4DDMACH,Receive Queue 4 Enabled for Dynamic DMA Channel Selection" "0,1"
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hexmask.long.byte 0x4 3.--6. 1. "Reserved_6_y,Reserved."
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bitfld.long 0x4 0.--2. "Q4MDMACH,Receive Queue 4 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
group.long 0x1040++0x1B
line.long 0x0 "MTL_TC_Prty_Map0,This register contains the priority values assigned to traffic classes 0 to 3."
hexmask.long.byte 0x0 24.--31. 1. "PSTC3,Priorities Mapped to Traffic Class 3."
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hexmask.long.byte 0x0 16.--23. 1. "PSTC2,Priorities Mapped to Traffic Class 2."
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hexmask.long.byte 0x0 8.--15. 1. "PSTC1,Priorities Mapped to Traffic Class 1."
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hexmask.long.byte 0x0 0.--7. 1. "PSTC0,Priorities Mapped to Traffic Class 0."
line.long 0x4 "MTL_TC_Prty_Map1,This register contains the priority values assigned to traffic classes 4 to 7."
hexmask.long.byte 0x4 24.--31. 1. "PSTC7,Priorities Mapped to Traffic Class 7."
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hexmask.long.byte 0x4 16.--23. 1. "PSTC6,Priorities Mapped to Traffic Class 6."
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hexmask.long.byte 0x4 8.--15. 1. "PSTC5,Priorities Mapped to Traffic Class 5."
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hexmask.long.byte 0x4 0.--7. 1. "PSTC4,Priorities Mapped to Traffic Class 4."
line.long 0x8 "MTL_TBS_CTRL,This register controls the operation of Time Based Scheduling."
hexmask.long.tbyte 0x8 8.--31. 1. "LEOS,Launch Expiry Offset"
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rbitfld.long 0x8 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x8 4.--6. "LEGOS,Launch Expiry GSN Offset" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x8 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x8 2. "TIEN,TBS Interrupt Enable" "0,1"
newline
bitfld.long 0x8 1. "LEOV,Launch Expiry Offset Valid" "0,1"
newline
bitfld.long 0x8 0. "ESTM,EST offset Mode" "0,1"
line.long 0xC "MTL_TBS_STATS,This register provides the One Hot encoded Queue numbers that have the frame drop related error"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_x,Reserved."
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hexmask.long.byte 0xC 0.--7. 1. "EDQN,Expiry drop Queue number"
line.long 0x10 "MTL_EST_Control,This register controls the operation of Enhancements to Scheduled Transmission (IEEE 802.1Qbv)."
hexmask.long.word 0x10 23.--31. 1. "PTOV,PTP Time Offset Value"
newline
hexmask.long.word 0x10 11.--22. 1. "CTOV,Current Time Offset Value"
newline
bitfld.long 0x10 8.--10. "TILS,Time Interval Left Shift Amount" "0: No left shift needed,1: Left shift TI by 1 bit,?,?,?,?,?,?"
newline
bitfld.long 0x10 6.--7. "LCSE,Loop Count to report Scheduling Error" "0,1,2,3"
newline
bitfld.long 0x10 5. "DFBS,Drop Frames causing Scheduling Error" "0,1"
newline
bitfld.long 0x10 4. "DDBF,Do not Drop frames during Frame Size Error" "0,1"
newline
bitfld.long 0x10 3. "QHLBF,Quick Assertion of HLBF Error" "0,1"
newline
rbitfld.long 0x10 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x10 1. "SSWL,Switch to software owned list" "0,1"
newline
bitfld.long 0x10 0. "EEST,Enable EST" "0,1"
line.long 0x14 "MTL_EST_Overhead,This register indicates the value of Overhead."
hexmask.long.word 0x14 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.byte 0x14 16.--20. 1. "Reserved_ABYT,Reserved."
newline
hexmask.long.byte 0x14 8.--15. 1. "Reserved_15_8,Reserved."
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hexmask.long.byte 0x14 0.--7. 1. "OVHD,Overhead Bytes Value"
line.long 0x18 "MTL_EST_Status,This register provides Status related to Enhancements to Scheduled Transmission (IEEE 802.1Qbv)."
hexmask.long.word 0x18 20.--31. 1. "Reserved_31_20,Reserved."
newline
hexmask.long.byte 0x18 16.--19. 1. "CGSN,Current GCL Slot Number."
newline
hexmask.long.byte 0x18 8.--15. 1. "BTRL,BTR Error Loop Count"
newline
rbitfld.long 0x18 7. "SWOL,Software Owned List" "0,1"
newline
rbitfld.long 0x18 5.--6. "Reserved_6_5,Reserved." "0,1,2,3"
newline
bitfld.long 0x18 4. "CGCE,Constant Gate Control Error" "0,1"
newline
rbitfld.long 0x18 3. "HLBS,Head-Of-Line Blocking due to Scheduling" "0,1"
newline
rbitfld.long 0x18 2. "HLBF,Head-Of-Line Blocking due to Frame Size" "0,1"
newline
bitfld.long 0x18 1. "BTRE,BTR Error" "0,1"
newline
bitfld.long 0x18 0. "SWLC,Switch to Software Owned List Complete" "0,1"
group.long 0x1060++0x7
line.long 0x0 "MTL_EST_Sch_Error,This register provides the One Hot encoded Queue numbers that have the scheduling related error (timeout)."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "SETN,Schedule Error TC Number"
line.long 0x4 "MTL_EST_Frm_Size_Error,This register provides the One Hot encoded Queue numbers that have the Frame Size related error."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "FETN,Frame Size Error TC Number"
rgroup.long 0x1068++0x3
line.long 0x0 "MTL_EST_Frm_Size_Capture,This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error. Upon clearing. this register captures the data of the next occurrence of a similar error."
hexmask.long.word 0x0 19.--31. 1. "Reserved_31_x,Reserved."
newline
bitfld.long 0x0 16.--18. "HBFQ,Queue Number of HLBF" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF"
group.long 0x1070++0x3
line.long 0x0 "MTL_EST_Intr_Enable,This register implements the Interrupt Enable bits for the various events that generate an interrupt. Bit positions have a 1- to-1 correspondence with the status bit positions in MTL_EST_Status register."
hexmask.long 0x0 5.--31. 1. "Reserved_31_5,Reserved."
newline
bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE" "0,1"
newline
bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS" "0,1"
newline
bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF" "0,1"
newline
bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error" "0,1"
newline
bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List" "0,1"
group.long 0x1080++0x7
line.long 0x0 "MTL_GCL_Control,This register provides the control information for reading/writing to the Gate Control lists."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
rbitfld.long 0x0 23. "GCLEIEC,ECC Inject Error Control for GCL Memory" "0,1"
newline
rbitfld.long 0x0 22. "GCLEIAEE,GCL ECC Inject Address Error Enable" "0,1"
newline
rbitfld.long 0x0 21. "GCLEIEE,GCL ECC Inject Error Enable" "0,1"
newline
hexmask.long.byte 0x0 16.--20. 1. "Reserved_20_y,Reserved."
newline
hexmask.long.byte 0x0 8.--15. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is 0)."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select" "0,1"
newline
bitfld.long 0x0 4. "DBGM,Debug Mode" "0,1"
newline
rbitfld.long 0x0 3. "Reserved_GCLS,Reserved." "0,1"
newline
bitfld.long 0x0 2. "GCRR,Gate Control Related Registers" "0,1"
newline
bitfld.long 0x0 1. "R1W0,Read 1  Write 0:" "0: Write Operation,1: Read Operation"
newline
bitfld.long 0x0 0. "SRWO,Start Read/Write Op" "0,1"
line.long 0x4 "MTL_GCL_Data,This register holds the read data or write data in case of reads and writes respectively."
hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data"
group.long 0x1090++0x7
line.long 0x0 "MTL_FPE_CTRL_STS,This register controls the operation of. and provides status for Frame Preemption (IEEE 802.1Qbu/802.3br)."
rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was last.."
newline
hexmask.long.word 0x0 17.--27. 1. "Reserved_27_17,Reserved."
newline
bitfld.long 0x0 16. "PHRSC,Preemption MAC Hold/Release Sideband Control Select" "0: Indicates that Set-Hold-and-Release-MAC..,1: Indicates that Set-Hold-and-Release-MAC.."
newline
hexmask.long.byte 0x0 8.--15. 1. "PEC,Preemption Classification"
newline
bitfld.long 0x0 7. "LBHT,Level Based Hold Transition" "0,1"
newline
hexmask.long.byte 0x0 2.--6. 1. "Reserved_6_2,Reserved."
newline
bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size" "0,1,2,3"
line.long 0x4 "MTL_FPE_Advance,This register holds the Hold and Release Advance time."
hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance"
newline
hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance"
group.long 0x1100++0x3
line.long 0x0 "MTL_TxQ0_Operation_Mode,The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1104++0x7
line.long 0x0 "MTL_TxQ0_Underflow,The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ0_Debug,The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 0 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1110++0x3
line.long 0x0 "MTL_TC0_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1114++0x3
line.long 0x0 "MTL_TC0_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1118++0x3
line.long 0x0 "MTL_TC0_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1140++0x3
line.long 0x0 "MTL_RxQ0_Operation_Mode,The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1144++0x7
line.long 0x0 "MTL_RxQ0_Missed_Pkt_Overflow_Cnt,The Queue 0 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ0_Debug,The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x114C++0x7
line.long 0x0 "MTL_RxQ0_Control,The Queue 0 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ0_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1170++0x7
line.long 0x0 "MTL_Q0_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 0."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q0_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 0."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1180++0x3
line.long 0x0 "MTL_TxQ1_Operation_Mode,The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1184++0x7
line.long 0x0 "MTL_TxQ1_Underflow,The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ1_Debug,The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 1 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1190++0x3
line.long 0x0 "MTL_TC1_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1194++0x3
line.long 0x0 "MTL_TC1_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1198++0x3
line.long 0x0 "MTL_TC1_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x11C0++0x3
line.long 0x0 "MTL_RxQ1_Operation_Mode,The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x11C4++0x7
line.long 0x0 "MTL_RxQ1_Missed_Pkt_Overflow_Cnt,The Queue 1 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ1_Debug,The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x11CC++0x7
line.long 0x0 "MTL_RxQ1_Control,The Queue 1 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ1_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x11F0++0x7
line.long 0x0 "MTL_Q1_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 1."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q1_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 1."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1200++0x3
line.long 0x0 "MTL_TxQ2_Operation_Mode,The Queue 2 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1204++0x7
line.long 0x0 "MTL_TxQ2_Underflow,The Queue 2 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ2_Debug,The Queue 2 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 2 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1210++0x3
line.long 0x0 "MTL_TC2_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1214++0x3
line.long 0x0 "MTL_TC2_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1218++0x3
line.long 0x0 "MTL_TC2_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1240++0x3
line.long 0x0 "MTL_RxQ2_Operation_Mode,The Queue 2 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1244++0x7
line.long 0x0 "MTL_RxQ2_Missed_Pkt_Overflow_Cnt,The Queue 2 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ2_Debug,The Queue 2 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x124C++0x7
line.long 0x0 "MTL_RxQ2_Control,The Queue 2 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ2_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1270++0x7
line.long 0x0 "MTL_Q2_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 2."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q2_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 2."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1280++0x3
line.long 0x0 "MTL_TxQ3_Operation_Mode,The Queue 3 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1284++0x7
line.long 0x0 "MTL_TxQ3_Underflow,The Queue 3 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ3_Debug,The Queue 3 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 3 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1290++0x3
line.long 0x0 "MTL_TC3_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1294++0x3
line.long 0x0 "MTL_TC3_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1298++0x3
line.long 0x0 "MTL_TC3_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x12C0++0x3
line.long 0x0 "MTL_RxQ3_Operation_Mode,The Queue 3 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x12C4++0x7
line.long 0x0 "MTL_RxQ3_Missed_Pkt_Overflow_Cnt,The Queue 3 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ3_Debug,The Queue 3 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x12CC++0x7
line.long 0x0 "MTL_RxQ3_Control,The Queue 3 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ3_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x12F0++0x7
line.long 0x0 "MTL_Q3_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 3."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q3_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 3."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1300++0x3
line.long 0x0 "MTL_TxQ4_Operation_Mode,The Queue 4 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1304++0x7
line.long 0x0 "MTL_TxQ4_Underflow,The Queue 4 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ4_Debug,The Queue 4 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 4 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1310++0x3
line.long 0x0 "MTL_TC4_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1314++0x3
line.long 0x0 "MTL_TC4_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1318++0x3
line.long 0x0 "MTL_TC4_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1340++0x3
line.long 0x0 "MTL_RxQ4_Operation_Mode,The Queue 4 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1344++0x7
line.long 0x0 "MTL_RxQ4_Missed_Pkt_Overflow_Cnt,The Queue 4 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ4_Debug,The Queue 4 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x134C++0x7
line.long 0x0 "MTL_RxQ4_Control,The Queue 4 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ4_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1370++0x7
line.long 0x0 "MTL_Q4_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 4."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q4_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 4."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1380++0x3
line.long 0x0 "MTL_TxQ5_Operation_Mode,The Queue 5 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1384++0x7
line.long 0x0 "MTL_TxQ5_Underflow,The Queue 5 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ5_Debug,The Queue 5 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 5 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1390++0x3
line.long 0x0 "MTL_TC5_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1394++0x3
line.long 0x0 "MTL_TC5_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1398++0x3
line.long 0x0 "MTL_TC5_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x13C0++0x3
line.long 0x0 "MTL_RxQ5_Operation_Mode,The Queue 5 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x13C4++0x7
line.long 0x0 "MTL_RxQ5_Missed_Pkt_Overflow_Cnt,The Queue 5 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ5_Debug,The Queue 5 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x13CC++0x7
line.long 0x0 "MTL_RxQ5_Control,The Queue 5 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ5_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x13F0++0x7
line.long 0x0 "MTL_Q5_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 5."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q5_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 5."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1400++0x3
line.long 0x0 "MTL_TxQ6_Operation_Mode,The Queue 6 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1404++0x7
line.long 0x0 "MTL_TxQ6_Underflow,The Queue 6 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ6_Debug,The Queue 6 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 6 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1410++0x3
line.long 0x0 "MTL_TC6_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1414++0x3
line.long 0x0 "MTL_TC6_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1418++0x3
line.long 0x0 "MTL_TC6_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1440++0x3
line.long 0x0 "MTL_RxQ6_Operation_Mode,The Queue 6 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1444++0x7
line.long 0x0 "MTL_RxQ6_Missed_Pkt_Overflow_Cnt,The Queue 6 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ6_Debug,The Queue 6 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x144C++0x7
line.long 0x0 "MTL_RxQ6_Control,The Queue 6 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ6_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1470++0x7
line.long 0x0 "MTL_Q6_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 6."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q6_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 6."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1480++0x3
line.long 0x0 "MTL_TxQ7_Operation_Mode,The Queue 7 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1484++0x7
line.long 0x0 "MTL_TxQ7_Underflow,The Queue 7 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ7_Debug,The Queue 7 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 7 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1490++0x3
line.long 0x0 "MTL_TC7_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
bitfld.long 0x0 4.--6. "SLC,Slot Count." "0: 1 Slot,1: 2 Slots,2: 4 Slots,3: 8 Slots,4: 16 Slots,?,?,?"
newline
bitfld.long 0x0 3. "CC,Credit Control." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1494++0x3
line.long 0x0 "MTL_TC7_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1498++0xF
line.long 0x0 "MTL_TC7_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
line.long 0x4 "MTL_TC7_SendSlopeCredit,MTL registers for traffic classes and queues 1 registers."
hexmask.long.word 0x4 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "SSC,sendSlopeCredit Value."
line.long 0x8 "MTL_TC7_HiCredit,This register contains the hiCredit value required for the credit-based shaper algorithm for TC1.."
rbitfld.long 0x8 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value."
line.long 0xC "MTL_TC7_LoCredit,This register contains the loCredit value required for the credit-based shaper algorithm for TC1."
rbitfld.long 0xC 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long 0xC 0.--28. 1. "LC,loCredit Value."
group.long 0x14C0++0x3
line.long 0x0 "MTL_RxQ7_Operation_Mode,The Queue 7 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x14C4++0x7
line.long 0x0 "MTL_RxQ7_Missed_Pkt_Overflow_Cnt,The Queue 7 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ7_Debug,The Queue 7 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x14CC++0x7
line.long 0x0 "MTL_RxQ7_Control,The Queue 7 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ7_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x14F0++0x7
line.long 0x0 "MTL_Q7_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 7."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q7_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 7."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x3000++0x7
line.long 0x0 "DMA_Mode,The Bus Mode register establishes the bus operating modes for the DMA."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
newline
bitfld.long 0x0 12.--13. "INTM,Interrupt Mode." "0: sbd_perch_* are pulse signals for each..,1: sbd_perch_* are level signals asserted on the..,?,?"
newline
rbitfld.long 0x0 9.--11. "Reserved_11_9,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "DSPW,Descriptor Posted Write." "0: By default,1: All Rx DMA data and descriptor writes are posted.."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 5. "Reserved_TMRP,Reserved." "0,1"
newline
bitfld.long 0x0 4. "TDRP,Tx Descriptor Read Priority." "0,1"
newline
rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "SWR,Software Reset." "0,1"
line.long 0x4 "DMA_SysBus_Mode,The System Bus mode register controls the behavior of the AXI master. It mainly controls burst splitting and number of outstanding requests."
rbitfld.long 0x4 29.--31. "Reserved_31_30,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 24.--28. 1. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit."
newline
rbitfld.long 0x4 21.--23. "Reserved_23_22,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 16.--20. 1. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit."
newline
bitfld.long 0x4 15. "EN_LPI,Enable Low Power Interface (LPI)." "0: Disables the LPI mode and always denies the LPI..,1: Enables the LPI mode supported by the AXI.."
newline
bitfld.long 0x4 14. "LPI_XIT_PKT,Unlock on Magic Packet or Remote Wake-Up Packet." "0: Enables the AXI master to come out of the LPI..,1: Enables the AXI master to come out of the LPI.."
newline
bitfld.long 0x4 13. "ONEKBBE,1 KB Boundary Crossing Enable for the AXI Master." "0: The burst transfers performed by the AXI master..,1: The burst transfers performed by the AXI master.."
newline
bitfld.long 0x4 12. "AAL,Address-Aligned Beats." "0,1"
newline
bitfld.long 0x4 11. "EAME,Enhanced Address Mode Enable." "?,1: DMA master enables the enhanced address mode"
newline
bitfld.long 0x4 10. "AALE,Automatic AXI LPI enable." "?,1: Enables the AXI master to enter into LPI state.."
newline
rbitfld.long 0x4 8.--9. "Reserved_9_8,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 7. "BLEN256,AXI Burst Length 256." "0,1"
newline
bitfld.long 0x4 6. "BLEN128,AXI Burst Length 128." "0,1"
newline
bitfld.long 0x4 5. "BLEN64,AXI Burst Length 64." "0,1"
newline
bitfld.long 0x4 4. "BLEN32,AXI Burst Length 32." "0,1"
newline
bitfld.long 0x4 3. "BLEN16,AXI Burst Length 16." "0,1"
newline
bitfld.long 0x4 2. "BLEN8,AXI Burst Length 8." "0,1"
newline
bitfld.long 0x4 1. "BLEN4,AXI Burst Length 4." "0,1"
newline
bitfld.long 0x4 0. "UBL,AXI Undefined Burst Length." "0: The AXI master performs one of the following..,1: The AXI master can perform burst transfers that.."
rgroup.long 0x3008++0x3
line.long 0x0 "DMA_Interrupt_Status,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels. MTL queues. and the MAC."
hexmask.long.word 0x0 18.--31. 1. "Reserved_31_18,Reserved."
newline
bitfld.long 0x0 17. "MACIS,MAC Interrupt Status." "0,1"
newline
bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status." "0,1"
newline
hexmask.long.byte 0x0 8.--15. 1. "DC15TC8IS,DMA Channel 15 Interrupt Status to DMA Channel 8 Interrupt Status."
newline
bitfld.long 0x0 7. "DC7IS,DMA Channel 7 Interrupt Status." "0,1"
newline
bitfld.long 0x0 6. "DC6IS,DMA Channel 6 Interrupt Status." "0,1"
newline
bitfld.long 0x0 5. "DC5IS,DMA Channel 5 Interrupt Status." "0,1"
newline
bitfld.long 0x0 4. "DC4IS,DMA Channel 4 Interrupt Status." "0,1"
newline
bitfld.long 0x0 3. "DC3IS,DMA Channel 3 Interrupt Status." "0,1"
newline
bitfld.long 0x0 2. "DC2IS,DMA Channel 2 Interrupt Status." "0,1"
newline
bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status." "0,1"
newline
bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status." "0,1"
group.long 0x3010++0x3
line.long 0x0 "AXI_Tx_AR_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for read transactions by all the Transmit DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding.."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 20.--21. "THD,Transmit DMA First Packet Buffer or TSO Header Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "THC,Transmit DMA First Packet Buffer or TSO Header Cache Control."
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "TED,Transmit DMA Extended Packet Buffer or TSO Payload Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 8.--11. 1. "TEC,Transmit DMA Extended Packet Buffer or TSO Payload Cache Control."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "TDRD,Transmit DMA Read Descriptor Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "TDRC,Transmit DMA Read Descriptor Cache Control."
group.long 0x3018++0x7
line.long 0x0 "AXI_Rx_AW_ACE_Control,This register is used to control the Cache Coherency Signals of the AXI4-ACE Lite on the Receive DMA. The programmable controllability is supported on the following signals of the AXI Write channel."
rbitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RDD,Receive DMA Buffer Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--27. 1. "RDC,Receive DMA Buffer Cache Control."
newline
rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RHD,Receive DMA Header Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "RHC,Receive DMA Header Cache Control."
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RPD,Receive DMA Payload Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 8.--11. 1. "RPC,Receive DMA Payload Cache Control."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RDWD,Receive DMA Write Descriptor Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "RDWC,Receive DMA Write Descriptor Cache Control."
line.long 0x4 "AXI_TxRx_AWAR_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for Descriptor write transactions by all the TxDMA channels and Descriptor read transactions by all the RxDMA channels. It also controls the values to be driven.."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_23,Reserved."
newline
bitfld.long 0x4 20.--22. "WRP,DMA Write Protection control." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 19. "Reserved_19,Reserved." "0,1"
newline
bitfld.long 0x4 16.--18. "RDP,DMA Read Protection control." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "RDRD,Receive DMA Read Descriptor Domain control." "0,1,2,3"
newline
hexmask.long.byte 0x4 8.--11. 1. "RDRC,Receive DMA Read Descriptor Cache control."
newline
rbitfld.long 0x4 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control." "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--3. 1. "TDWC,Transmit DMA Write Descriptor Cache control."
rgroup.long 0x3020++0x7
line.long 0x0 "DMA_Debug_Status0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0 - Channel 2 for debugging purpose."
hexmask.long.byte 0x0 28.--31. 1. "TPS2,DMA Channel 2 Transmit Process State."
newline
hexmask.long.byte 0x0 24.--27. 1. "RPS2,DMA Channel 2 Receive Process State."
newline
hexmask.long.byte 0x0 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State."
newline
hexmask.long.byte 0x0 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State."
newline
hexmask.long.byte 0x0 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State."
newline
hexmask.long.byte 0x0 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State."
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved."
newline
bitfld.long 0x0 1. "AXRHSTS,AXI Master Read Channel Status." "0,1"
newline
bitfld.long 0x0 0. "AXWHSTS,AXI Master Write Channel Status." "?,1: Indicates that the write channel of the AXI.."
line.long 0x4 "DMA_Debug_Status1,The Debug Status1 register gives the per Transmit DMA active status."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "TDAS,Transmit DMA Active Status."
rgroup.long 0x302C++0x3
line.long 0x0 "DMA_Debug_Status3,The Debug Status3 register gives the per Receive DMA active status."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "RDAS,Receive DMA Active Status."
group.long 0x3040++0x7
line.long 0x0 "DMA_Tx_EDMA_Control,The DMA_Tx_EDMA_Control register controls the sequence of all TxDMA operations with the DMA engine."
bitfld.long 0x0 30.--31. "TEDM,Tx DMA Mode." "0: Default mode of DMA,1: The value of TDPS field is ignored and only one..,2: The value of TDPS field is ignored and only one..,3: All operations are sequential"
newline
hexmask.long 0x0 2.--29. 1. "Reserved_29_y,Reserved."
newline
bitfld.long 0x0 0.--1. "TDPS,Tx Descriptor Pre-fetch threshold Size." "0: Threshold of 0 descriptors,1: Threshold is 4 descriptors,2: Threshold is 8 descriptors,3: Threshold is 12 descriptors"
line.long 0x4 "DMA_Rx_EDMA_Control,The DMA_Rx_EDMA_Control register controls the sequence of all RxDMA operations with the DMA engine."
bitfld.long 0x4 30.--31. "REDM,Rx DMA Mode." "0: Default mode of DMA as explained in section 2,1: The value of RDPS field is ignored and only 1..,2: The value of RDPS field is ignored and only 1..,3: All operations are sequential"
newline
hexmask.long 0x4 2.--29. 1. "Reserved_29_y,Reserved."
newline
bitfld.long 0x4 0.--1. "RDPS,Rx Descriptor Pre-Fetch Threshold Size." "0: Threshold of 0 descriptors,1: Threshold is 4 descriptors,2: Threshold is 8 descriptors,3: Threshold is 12 descriptors"
group.long 0x3050++0x13
line.long 0x0 "AXI_LPI_Entry_Interval,This register is used to control the AXI LPI entry interval."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
hexmask.long.byte 0x0 0.--3. 1. "LPIEI,LPI Entry Interval"
line.long 0x4 "DMA_TBS_CTRL0,This register is used to control the TBS0 attributes."
hexmask.long.tbyte 0x4 8.--31. 1. "FTOS,Fetch Time Offset 0"
newline
rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x4 4.--6. "FGOS,Fetch GSN Offset 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "FTOV,Fetch Time Offset 0 Valid" "0,1"
line.long 0x8 "DMA_TBS_CTRL1,This register is used to control the TBS1 attributes."
hexmask.long.tbyte 0x8 8.--31. 1. "FTOS,Fetch Time Offset 1"
newline
rbitfld.long 0x8 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x8 4.--6. "FGOS,Fetch GSN Offset 1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x8 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "FTOV,Fetch Time Offset 1 Valid" "0,1"
line.long 0xC "DMA_TBS_CTRL2,This register is used to control the TBS2 attributes."
hexmask.long.tbyte 0xC 8.--31. 1. "FTOS,Fetch Time Offset 2"
newline
rbitfld.long 0xC 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0xC 4.--6. "FGOS,Fetch GSN Offset 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0xC 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 0. "FTOV,Fetch Time Offset 2 Valid" "0,1"
line.long 0x10 "DMA_TBS_CTRL3,This register is used to control the TBS3 attributes."
hexmask.long.tbyte 0x10 8.--31. 1. "FTOS,Fetch Time Offset 3"
newline
rbitfld.long 0x10 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x10 4.--6. "FGOS,Fetch GSN Offset 3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "FTOV,Fetch Time Offset 3 Valid" "0,1"
group.long 0x3080++0x7
line.long 0x0 "DMA_CH_Ind_Ctrl,This register is used to program Indirect Access DMA configuration registers"
hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved."
newline
hexmask.long.byte 0x0 16.--19. 1. "MSEL,Mode Select"
newline
hexmask.long.byte 0x0 12.--15. 1. "Reserved_15_12,Reserved."
newline
hexmask.long.byte 0x0 8.--11. 1. "AOFF,Address Offset"
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "AUTO,Auto Increment" "0: No auto increment,1: Auto increment MSEL only,?,?"
newline
rbitfld.long 0x0 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 1. "CT,Command Type" "0: Indicates a write operation,1: Indicates a read operation"
newline
bitfld.long 0x0 0. "OB,Operation Busy" "0,1"
line.long 0x4 "DMA_CH_Ind_Data,This register holds the read/write data for Indirect Access of the registers indicated by DMA_<MSEL>_<AOFF>. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field.."
hexmask.long 0x4 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH0_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH1_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH2_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH3_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH4_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH5_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH6_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH7_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3100++0x1F
line.long 0x0 "DMA_CH0_Control,The DMA Channel0 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH0_Tx_Control,The DMA Channel0 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH0_Rx_Control,The DMA Channel0 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel0 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH0_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH0_TxDesc_List_HAddress,The Channel0 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH0_TxDesc_List_LAddress,The Channel0 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH0_RxDesc_List_HAddress,The Channel0 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH0_RxDesc_List_LAddress,The Channel0 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3124++0x3
line.long 0x0 "DMA_CH0_TxDesc_Tail_LPointer,The Channel0 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x312C++0x13
line.long 0x0 "DMA_CH0_RxDesc_Tail_LPointer,The Channel0 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH0_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH0_Rx_Control2,The Channel0 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH0_Interrupt_Enable,The Channel0 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH0_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3144++0x3
line.long 0x0 "DMA_CH0_Current_App_TxDesc_L,The Channel0 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x314C++0x13
line.long 0x0 "DMA_CH0_Current_App_RxDesc_L,The Channel0 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH0_Current_App_TxBuffer_H,The Channel0 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH0_Current_App_TxBuffer_L,The Channel0 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH0_Current_App_RxBuffer_H,The Channel0 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH0_Current_App_RxBuffer_L,The Channel0 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3160++0x3
line.long 0x0 "DMA_CH0_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3164++0x1B
line.long 0x0 "DMA_CH0_Debug_Status,DMA Channe0 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH0_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH0_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH0_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH0_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH0_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH0_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH0_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3180++0x1F
line.long 0x0 "DMA_CH1_Control,The DMA Channel1 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH1_Tx_Control,The DMA Channel1 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH1_Rx_Control,The DMA Channel1 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel1 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
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rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
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rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
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hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
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rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH1_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
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hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
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hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
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bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
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bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH1_TxDesc_List_HAddress,The Channel1 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH1_TxDesc_List_LAddress,The Channel1 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
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rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH1_RxDesc_List_HAddress,The Channel1 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH1_RxDesc_List_LAddress,The Channel1 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
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rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x31A4++0x3
line.long 0x0 "DMA_CH1_TxDesc_Tail_LPointer,The Channel1 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
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rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x31AC++0x13
line.long 0x0 "DMA_CH1_RxDesc_Tail_LPointer,The Channel1 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
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rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH1_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
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bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
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hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH1_Rx_Control2,The Channel1 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
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bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
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rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH1_Interrupt_Enable,The Channel1 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
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bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
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bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
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bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
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rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
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bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
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bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
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rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
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bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH1_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
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hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
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hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
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rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
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hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x31C4++0x3
line.long 0x0 "DMA_CH1_Current_App_TxDesc_L,The Channel1 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x31CC++0x13
line.long 0x0 "DMA_CH1_Current_App_RxDesc_L,The Channel1 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH1_Current_App_TxBuffer_H,The Channel1 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH1_Current_App_TxBuffer_L,The Channel1 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH1_Current_App_RxBuffer_H,The Channel1 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH1_Current_App_RxBuffer_L,The Channel1 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x31E0++0x3
line.long 0x0 "DMA_CH1_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
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bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
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bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
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bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
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bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
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bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
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bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
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rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
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bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
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bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
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bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
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rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
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bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
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bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x31E4++0x1B
line.long 0x0 "DMA_CH1_Debug_Status,DMA Channe1 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
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bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
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bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
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bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
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bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH1_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
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hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
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hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH1_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH1_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
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hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
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hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH1_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH1_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH1_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH1_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3200++0x1F
line.long 0x0 "DMA_CH2_Control,The DMA Channel2 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
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bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
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rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
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bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
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rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH2_Tx_Control,The DMA Channel2 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
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rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
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rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
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rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
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rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
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bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
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hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
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rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
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rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH2_Rx_Control,The DMA Channel2 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel2 Packet Flush." "0,1"
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rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
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rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
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rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
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hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
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rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH2_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
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hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
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hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
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bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
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bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH2_TxDesc_List_HAddress,The Channel2 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH2_TxDesc_List_LAddress,The Channel2 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH2_RxDesc_List_HAddress,The Channel2 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH2_RxDesc_List_LAddress,The Channel2 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3224++0x3
line.long 0x0 "DMA_CH2_TxDesc_Tail_LPointer,The Channel2 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x322C++0x13
line.long 0x0 "DMA_CH2_RxDesc_Tail_LPointer,The Channel2 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH2_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH2_Rx_Control2,The Channel2 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH2_Interrupt_Enable,The Channel2 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
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bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
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rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
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rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
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bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH2_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
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hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
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hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
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rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3244++0x3
line.long 0x0 "DMA_CH2_Current_App_TxDesc_L,The Channel2 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x324C++0x13
line.long 0x0 "DMA_CH2_Current_App_RxDesc_L,The Channel2 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH2_Current_App_TxBuffer_H,The Channel2 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH2_Current_App_TxBuffer_L,The Channel2 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH2_Current_App_RxBuffer_H,The Channel2 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH2_Current_App_RxBuffer_L,The Channel2 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3260++0x3
line.long 0x0 "DMA_CH2_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
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bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
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bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
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bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
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bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
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bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
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bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
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rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
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bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
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bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
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bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
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rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
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bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
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bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3264++0x1B
line.long 0x0 "DMA_CH2_Debug_Status,DMA Channe2 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
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bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
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bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
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bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
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bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH2_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
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hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
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hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH2_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH2_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
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hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
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hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH2_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH2_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH2_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH2_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3280++0x1F
line.long 0x0 "DMA_CH3_Control,The DMA Channel3 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
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bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
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rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
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bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
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rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH3_Tx_Control,The DMA Channel3 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
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rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
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rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
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rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
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rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
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bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
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hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
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rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
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rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH3_Rx_Control,The DMA Channel3 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel3 Packet Flush." "0,1"
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rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
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rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
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rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
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hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
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rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH3_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
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hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
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hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
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bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
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bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH3_TxDesc_List_HAddress,The Channel3 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH3_TxDesc_List_LAddress,The Channel3 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
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rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH3_RxDesc_List_HAddress,The Channel3 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH3_RxDesc_List_LAddress,The Channel3 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
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rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x32A4++0x3
line.long 0x0 "DMA_CH3_TxDesc_Tail_LPointer,The Channel3 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x32AC++0x13
line.long 0x0 "DMA_CH3_RxDesc_Tail_LPointer,The Channel3 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH3_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
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hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH3_Rx_Control2,The Channel3 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
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rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH3_Interrupt_Enable,The Channel3 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
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bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
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bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
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bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
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bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
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rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
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bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH3_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x32C4++0x3
line.long 0x0 "DMA_CH3_Current_App_TxDesc_L,The Channel3 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x32CC++0x13
line.long 0x0 "DMA_CH3_Current_App_RxDesc_L,The Channel3 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH3_Current_App_TxBuffer_H,The Channel3 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH3_Current_App_TxBuffer_L,The Channel3 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH3_Current_App_RxBuffer_H,The Channel3 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH3_Current_App_RxBuffer_L,The Channel3 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x32E0++0x3
line.long 0x0 "DMA_CH3_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x32E4++0x1B
line.long 0x0 "DMA_CH3_Debug_Status,DMA Channe3 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH3_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH3_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH3_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
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hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH3_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH3_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH3_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH3_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3300++0x1F
line.long 0x0 "DMA_CH4_Control,The DMA Channel4 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
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bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
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rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
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bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH4_Tx_Control,The DMA Channel4 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
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rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH4_Rx_Control,The DMA Channel4 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel4 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH4_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
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hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
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bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
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bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH4_TxDesc_List_HAddress,The Channel4 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH4_TxDesc_List_LAddress,The Channel4 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
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rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH4_RxDesc_List_HAddress,The Channel4 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH4_RxDesc_List_LAddress,The Channel4 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3324++0x3
line.long 0x0 "DMA_CH4_TxDesc_Tail_LPointer,The Channel4 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x332C++0x13
line.long 0x0 "DMA_CH4_RxDesc_Tail_LPointer,The Channel4 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH4_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
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hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH4_Rx_Control2,The Channel4 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH4_Interrupt_Enable,The Channel4 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
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bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH4_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3344++0x3
line.long 0x0 "DMA_CH4_Current_App_TxDesc_L,The Channel4 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x334C++0x13
line.long 0x0 "DMA_CH4_Current_App_RxDesc_L,The Channel4 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH4_Current_App_TxBuffer_H,The Channel4 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH4_Current_App_TxBuffer_L,The Channel4 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH4_Current_App_RxBuffer_H,The Channel4 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH4_Current_App_RxBuffer_L,The Channel4 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3360++0x3
line.long 0x0 "DMA_CH4_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3364++0x1B
line.long 0x0 "DMA_CH4_Debug_Status,DMA Channe4 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH4_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
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hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH4_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH4_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH4_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH4_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH4_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH4_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3380++0x1F
line.long 0x0 "DMA_CH5_Control,The DMA Channel5 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH5_Tx_Control,The DMA Channel5 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH5_Rx_Control,The DMA Channel5 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel5 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH5_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH5_TxDesc_List_HAddress,The Channel5 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH5_TxDesc_List_LAddress,The Channel5 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
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rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH5_RxDesc_List_HAddress,The Channel5 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH5_RxDesc_List_LAddress,The Channel5 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
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rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x33A4++0x3
line.long 0x0 "DMA_CH5_TxDesc_Tail_LPointer,The Channel5 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
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rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x33AC++0x13
line.long 0x0 "DMA_CH5_RxDesc_Tail_LPointer,The Channel5 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
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rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH5_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
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bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
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hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH5_Rx_Control2,The Channel5 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
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bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
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rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH5_Interrupt_Enable,The Channel5 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
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bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
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bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
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bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
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rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
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rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
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bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH5_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
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hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
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hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
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rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x33C4++0x3
line.long 0x0 "DMA_CH5_Current_App_TxDesc_L,The Channel5 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x33CC++0x13
line.long 0x0 "DMA_CH5_Current_App_RxDesc_L,The Channel5 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH5_Current_App_TxBuffer_H,The Channel5 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH5_Current_App_TxBuffer_L,The Channel5 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH5_Current_App_RxBuffer_H,The Channel5 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH5_Current_App_RxBuffer_L,The Channel5 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x33E0++0x3
line.long 0x0 "DMA_CH5_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
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bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
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bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
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bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
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bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
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bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
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bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
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rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
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bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
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bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
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bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
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rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
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bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
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bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x33E4++0x1B
line.long 0x0 "DMA_CH5_Debug_Status,DMA Channe5 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
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bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
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bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
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bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
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bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH5_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
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hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
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hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH5_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH5_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
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hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
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hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH5_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH5_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH5_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH5_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3400++0x1F
line.long 0x0 "DMA_CH6_Control,The DMA Channel6 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
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rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
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bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
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rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH6_Tx_Control,The DMA Channel6 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
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bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
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rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
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rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
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rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
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hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
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rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
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rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH6_Rx_Control,The DMA Channel6 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel6 Packet Flush." "0,1"
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rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
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rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
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rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
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hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
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rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH6_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
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hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
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bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
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bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH6_TxDesc_List_HAddress,The Channel6 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH6_TxDesc_List_LAddress,The Channel6 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH6_RxDesc_List_HAddress,The Channel6 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH6_RxDesc_List_LAddress,The Channel6 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3424++0x3
line.long 0x0 "DMA_CH6_TxDesc_Tail_LPointer,The Channel6 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x342C++0x13
line.long 0x0 "DMA_CH6_RxDesc_Tail_LPointer,The Channel6 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH6_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH6_Rx_Control2,The Channel6 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH6_Interrupt_Enable,The Channel6 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH6_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3444++0x3
line.long 0x0 "DMA_CH6_Current_App_TxDesc_L,The Channel6 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x344C++0x13
line.long 0x0 "DMA_CH6_Current_App_RxDesc_L,The Channel6 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH6_Current_App_TxBuffer_H,The Channel6 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH6_Current_App_TxBuffer_L,The Channel6 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH6_Current_App_RxBuffer_H,The Channel6 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH6_Current_App_RxBuffer_L,The Channel6 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3460++0x3
line.long 0x0 "DMA_CH6_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3464++0x1B
line.long 0x0 "DMA_CH6_Debug_Status,DMA Channe6 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH6_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH6_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH6_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH6_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH6_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH6_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH6_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3480++0x1F
line.long 0x0 "DMA_CH7_Control,The DMA Channel7 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH7_Tx_Control,The DMA Channel7 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH7_Rx_Control,The DMA Channel7 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel7 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH7_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH7_TxDesc_List_HAddress,The Channel7 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH7_TxDesc_List_LAddress,The Channel7 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH7_RxDesc_List_HAddress,The Channel7 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH7_RxDesc_List_LAddress,The Channel7 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x34A4++0x3
line.long 0x0 "DMA_CH7_TxDesc_Tail_LPointer,The Channel7 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x34AC++0x13
line.long 0x0 "DMA_CH7_RxDesc_Tail_LPointer,The Channel7 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH7_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH7_Rx_Control2,The Channel7 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH7_Interrupt_Enable,The Channel7 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH7_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x34C4++0x3
line.long 0x0 "DMA_CH7_Current_App_TxDesc_L,The Channel7 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x34CC++0x13
line.long 0x0 "DMA_CH7_Current_App_RxDesc_L,The Channel7 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH7_Current_App_TxBuffer_H,The Channel7 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH7_Current_App_TxBuffer_L,The Channel7 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH7_Current_App_RxBuffer_H,The Channel7 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH7_Current_App_RxBuffer_L,The Channel7 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x34E0++0x3
line.long 0x0 "DMA_CH7_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x34E4++0x1B
line.long 0x0 "DMA_CH7_Debug_Status,DMA Channe7 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH7_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH7_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH7_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH7_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH7_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH7_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH7_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
tree.end
tree "EMAC_2"
base ad:0x10830000
group.long 0x0++0x17
line.long 0x0 "MAC_Tx_Configuration,The MAC Transmit Configuration register establishes the operating mode of the MAC transmitter."
bitfld.long 0x0 29.--31. "SS,Speed Selection." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 28. "Reserved_G9991EN,Reserved." "0,1"
newline
rbitfld.long 0x0 27. "Reserved_GT9WH,Reserved." "0,1"
newline
rbitfld.long 0x0 26. "Reserved_26,Reserved." "0,1"
newline
rbitfld.long 0x0 25. "Reserved_VNM,Reserved." "0,1"
newline
rbitfld.long 0x0 24. "Reserved_VNE,Reserved." "0,1"
newline
rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1"
newline
bitfld.long 0x0 20.--22. "SARC,Source Address Insertion or Replacement Control." "?,?,2: ,3: ,?,?,?,?"
newline
rbitfld.long 0x0 19. "Reserved_PEN,Reserved." "0,1"
newline
rbitfld.long 0x0 18. "Reserved_PCHM,Reserved." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "JD,Jabber Disable." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 13. "LUD,Link Up or Down." "0: Link down,1: Link up"
newline
bitfld.long 0x0 12. "TC,Transmit Configuration in RGMII." "0: Disable Transmit Configuration in RGMII,1: Enable Transmit Configuration in RGMII"
newline
bitfld.long 0x0 11. "IFP,IPG Control" "0,1"
newline
bitfld.long 0x0 8.--10. "IPG,Inter-Packet Gap" "0: 96 bit times,1: 88 bit times,2: 80 bit times,3: 72 bit times,4: 64 bit times,?,?,7: Reserved"
newline
hexmask.long.byte 0x0 4.--7. 1. "ISR,IFG Stretch Ratio."
newline
bitfld.long 0x0 3. "ISM,IFG Stretch Mode." "0,1"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 1. "DDIC,Disable DIC Algorithm." "0,1"
newline
bitfld.long 0x0 0. "TE,Transmitter Enable." "0,1"
line.long 0x4 "MAC_Rx_Configuration,The MAC Receive Configuration register establishes the operating mode of the MAC receiver."
bitfld.long 0x4 31. "ARPEN,ARP enable." "0,1"
newline
rbitfld.long 0x4 30. "Reserved_ELEN,Reserved." "0,1"
newline
hexmask.long.word 0x4 16.--29. 1. "GPSL,Giant Packet Size Limit."
newline
rbitfld.long 0x4 15. "Reserved_PRXM,Reserved." "0,1"
newline
bitfld.long 0x4 12.--14. "HDSMS,Maximum Size for Splitting the Header Data." "0: 64 bytes,1: 128 bytes,2: 256 bytes,3: 512 bytes,4: 1023 bytes,?,?,?"
newline
bitfld.long 0x4 11. "S2KP,IEEE 802.3as Support for 2K Packets." "0,1"
newline
bitfld.long 0x4 10. "LM,Loopback Mode." "0,1"
newline
bitfld.long 0x4 9. "IPC,Checksum Offload." "0,1"
newline
bitfld.long 0x4 8. "JE,Jumbo Packet Enable." "0,1"
newline
bitfld.long 0x4 7. "WD,Watchdog Disable." "0,1"
newline
bitfld.long 0x4 6. "GPSLCE,Giant Packet Size Limit Control Enable." "0,1"
newline
bitfld.long 0x4 5. "USP,Unicast Slow Protocol Packet Detect." "0,1"
newline
bitfld.long 0x4 4. "SPEN,Slow Protocol Detection Enable." "0,1"
newline
bitfld.long 0x4 3. "DCRCC,Disable CRC Checking for Received Packets." "0,1"
newline
bitfld.long 0x4 2. "CST,CRC stripping for Type packets." "0,1"
newline
bitfld.long 0x4 1. "ACS,Automatic Pad or CRC Stripping." "0,1"
newline
bitfld.long 0x4 0. "RE,Receiver Enable." "0,1"
line.long 0x8 "MAC_Packet_Filter,The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of.."
bitfld.long 0x8 31. "RA,Receive All." "0,1"
newline
hexmask.long.byte 0x8 23.--30. 1. "Reserved_30_23,Reserved."
newline
rbitfld.long 0x8 22. "Reserved_VUCC,Reserved." "0,1"
newline
bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets." "0,1"
newline
bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable." "0,1"
newline
rbitfld.long 0x8 17.--19. "Reserved_19_17,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable." "0,1"
newline
rbitfld.long 0x8 13.--15. "Reserved_15_13,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 11.--12. "DHLFRS,DA Hash Index or L3/L4 Filter Number in Receive Status." "0: Use both backward compatible DA hash index and..,1: Use combined DA hash table index and L3/L4..,2: Use combined DA hash table index and L3/L4..,3: Reserved"
newline
bitfld.long 0x8 10. "HPF,Hash or Perfect Filter." "0,1"
newline
bitfld.long 0x8 9. "SAF,Source Address Filter Enable." "0,1"
newline
bitfld.long 0x8 8. "SAIF,SA Inverse Filtering." "0,1"
newline
bitfld.long 0x8 6.--7. "PCF,Pass Control Packets." "0: The MAC filters all control packets from..,1: The MAC forwards all control packets except..,?,?"
newline
bitfld.long 0x8 5. "DBF,Disable Broadcast Packets." "0,1"
newline
bitfld.long 0x8 4. "PM,Pass All Multicast." "0,1"
newline
bitfld.long 0x8 3. "DAIF,DA Inverse Filtering." "0,1"
newline
bitfld.long 0x8 2. "HMC,Hash Multicast." "0,1"
newline
bitfld.long 0x8 1. "HUC,Hash Unicast." "0,1"
newline
bitfld.long 0x8 0. "PR,Promiscuous Mode." "0,1"
line.long 0xC "MAC_WD_JB_Timeout,The Watchdog and Jabber Timeout register controls the watchdog timeout limit for the received packets and jabber timeout limit for transmitted packets."
hexmask.long.byte 0xC 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0xC 24. "PJE,Programmable Jabber Enable." "0,1"
newline
hexmask.long.byte 0xC 20.--23. 1. "Reserved_23_20,Reserved."
newline
hexmask.long.byte 0xC 16.--19. 1. "JTO,Jabber Timeout."
newline
hexmask.long.byte 0xC 9.--15. 1. "Reserved_15_9,Reserved."
newline
bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable." "0,1"
newline
hexmask.long.byte 0xC 4.--7. 1. "Reserved_7_4,Reserved."
newline
hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout."
line.long 0x10 "MAC_Hash_Table_Reg0,The 64-bit hash table is used for group address filtering. For hash filtering. the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC are used to index the.."
hexmask.long 0x10 0.--31. 1. "HT31T0,Lower 32 bits of Hash Table."
line.long 0x14 "MAC_Hash_Table_Reg1,The 64-bit hash table is used for group address filtering. For hash filtering. the content of the destination address in the incoming packet is passed through the CRC logic and the upper six bits of the CRC are used to index the.."
hexmask.long 0x14 0.--31. 1. "HT31T0,Upper 32 bits of Hash Table."
group.long 0x50++0x7
line.long 0x0 "MAC_VLAN_Tag_Ctrl,MAC_VLAN_Tag_Ctrl register is a re-defined version of MAC_VLAN_Tag register. This register holds the control and addressing fields required for indirect accessing of the MAC_VLAN_Tag_Filter registers. when Extended Internal Rx VLAN.."
bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status." "0,1"
newline
rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive." "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
newline
bitfld.long 0x0 27. "ERIVLT,Enable Inner VLAN Tag for VLAN hash filtering." "0,1"
newline
bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing." "0,1"
newline
bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable." "0,1"
newline
bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status." "0,1"
newline
rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1"
newline
bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive." "0: Do not strip,1: Strip if VLAN filter passes,2: Strip if VLAN filter fails,3: Always strip"
newline
bitfld.long 0x0 20. "DOVLTC,Disable VLAN Type Check for VLAN hash filtering." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match for VLAN hash filtering." "0,1"
newline
bitfld.long 0x0 18. "ESVL,Enable S-VLAN." "0,1"
newline
bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match/Result Enable." "0,1"
newline
bitfld.long 0x0 16. "ETV,Enable 12-Bit VLAN Tag Comparison for VLAN hash filtering." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_ERIVTL,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 12.--13. "Reserved_EROVTL,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x0 7.--11. 1. "Reserved_11_7,Reserved."
newline
hexmask.long.byte 0x0 2.--6. 1. "OFS,Offset."
newline
bitfld.long 0x0 1. "CT,Command Type." "0,1"
newline
bitfld.long 0x0 0. "OB,Operation Busy." "0,1"
line.long 0x4 "MAC_VLAN_Tag_Data,This register holds the read/write data for Indirect Access of the Per MAC_VLAN_Tag_Filter registers. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field must.."
hexmask.long.byte 0x4 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x4 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x4 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x4 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x4 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag Identifier for Receive Packets."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter0,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter1,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter10,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter11,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter12,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter13,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter14,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter15,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter16,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter17,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter18,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter19,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter2,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter20,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter21,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter22,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter23,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter24,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter25,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter26,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter27,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter28,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter29,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter3,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter30,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter31,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter4,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter5,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter6,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter7,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x3
line.long 0x0 "MAC_VLAN_Tag_Filter8,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
group.long 0x54++0x7
line.long 0x0 "MAC_VLAN_Tag_Filter9,This register contains per VLAN Tag filter control information."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x0 25.--27. "DMACHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24. "DMACHEN,DMA Channel Number Enable." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 20. "ERIVLT,Enable Inner VLAN Tag." "0,1"
newline
bitfld.long 0x0 19. "ERSVLM,Enable Receive S-VLAN Match." "0,1"
newline
bitfld.long 0x0 18. "DOVLTC,Disable VLAN Type Check." "0,1"
newline
bitfld.long 0x0 17. "ETV,Enable 12-Bit VLAN Tag Comparison." "0,1"
newline
bitfld.long 0x0 16. "VEN,VLAN Tag Enable." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VID,VLAN Tag ID."
line.long 0x4 "MAC_VLAN_Hash_Table,When the ERSVLM bit of MAC_VLAN_Tag register is set. the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the.."
hexmask.long.word 0x4 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "VLHT,VLAN Hash Table."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl,The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls."
rbitfld.long 0x0 31. "BUSY,BUSY." "0,1"
newline
bitfld.long 0x0 30. "RDWR,Read Write Control." "0,1"
newline
rbitfld.long 0x0 27.--29. "Reserved_29_y,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 24.--26. "ADDR,Address." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 21. "CBTI,Channel Based Tag Insertion." "0,1"
newline
bitfld.long 0x0 20. "VLTI,VLAN Tag Input." "0,1"
newline
bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
bitfld.long 0x0 18. "VLP,VLAN Priority Control." "0,1"
newline
bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets." "0: No VLAN tag deletion,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl0,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl1,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl10,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl11,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl12,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl13,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl14,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl15,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl2,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl3,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl4,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl5,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl6,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl7,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x3
line.long 0x0 "MAC_VLAN_Incl8,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x60++0x7
line.long 0x0 "MAC_VLAN_Incl9,The per Tx Queue VLAN Tag Inclusion register contains the VLAN tag for insertion in the Transmit packets from respective Tx Queue. It also contains the VLAN tag insertion controls."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
line.long 0x4 "MAC_Inner_VLAN_Incl,The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls."
hexmask.long.word 0x4 21.--31. 1. "Reserved_31_21,Reserved."
newline
bitfld.long 0x4 20. "VLTI,VLAN Tag Input." "0,1"
newline
bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN." "0,1"
newline
bitfld.long 0x4 18. "VLP,VLAN Priority Control." "0,1"
newline
bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets." "0: No VLAN tag deletion,1: VLAN tag deletion,2: VLAN tag insertion,3: VLAN tag replacement"
newline
hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets."
group.long 0x6C++0x2F
line.long 0x0 "MAC_Rx_Eth_Type_Match,The receive Ethernet type match register contains the ether type value that needs to be compared with the ether length/type field of the received packet. The result is indicated in the packet_type field of receive status word. This.."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0x0 0.--15. 1. "ET,Ethernet Type."
line.long 0x4 "MAC_Q0_Tx_Flow_Ctrl,The MAC_Q0_Tx_Flow_Ctrl register controls the generation of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate a.."
hexmask.long.word 0x4 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x4 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x4 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,2: Pause Time minus 36 Slot Times,3: Pause Time minus 144 Slot Times,4: Pause Time minus 256 Slot Times,?,?,7: Reserved"
newline
rbitfld.long 0x4 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x4 0. "FCB,Flow Control Busy or Backpressure Activate." "0,1"
line.long 0x8 "MAC_Q1_Tx_Flow_Ctrl,The MAC_Q1_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x8 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x8 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x8 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x8 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x8 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x8 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x8 0. "FCB,Flow Control Busy." "0,1"
line.long 0xC "MAC_Q2_Tx_Flow_Ctrl,The MAC_Q2_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0xC 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0xC 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0xC 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0xC 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0xC 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0xC 0. "FCB,Flow Control Busy." "0,1"
line.long 0x10 "MAC_Q3_Tx_Flow_Ctrl,The MAC_Q3_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x10 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x10 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x10 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x10 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x10 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x10 0. "FCB,Flow Control Busy." "0,1"
line.long 0x14 "MAC_Q4_Tx_Flow_Ctrl,The MAC_Q4_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x14 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x14 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x14 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x14 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x14 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x14 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x14 0. "FCB,Flow Control Busy." "0,1"
line.long 0x18 "MAC_Q5_Tx_Flow_Ctrl,The MAC_Q5_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x18 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x18 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x18 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x18 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x18 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x18 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x18 0. "FCB,Flow Control Busy." "0,1"
line.long 0x1C "MAC_Q6_Tx_Flow_Ctrl,The MAC_Q6_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x1C 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x1C 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x1C 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x1C 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x1C 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x1C 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x1C 0. "FCB,Flow Control Busy." "0,1"
line.long 0x20 "MAC_Q7_Tx_Flow_Ctrl,The MAC_Q7_Tx_Flow_Ctrl register is per priority and controls the generation of the PFC (Priority Flow Control) packets by the Flow control module of the MAC. A write to a register with the Busy bit set to 1 triggers the Flow Control.."
hexmask.long.word 0x20 16.--31. 1. "PT,Pause Time."
newline
hexmask.long.byte 0x20 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x20 7. "DZPQ,Disable Zero-Quanta Pause." "0,1"
newline
bitfld.long 0x20 4.--6. "PLT,Pause Low Threshold." "0: Pause Time minus 4 Slot Times,1: Pause Time minus 28 Slot Times,?,?,?,?,?,?"
newline
rbitfld.long 0x20 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x20 1. "TFE,Transmit Flow Control Enable." "0,1"
newline
bitfld.long 0x20 0. "FCB,Flow Control Busy." "0,1"
line.long 0x24 "MAC_Rx_Flow_Ctrl,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet."
hexmask.long.tbyte 0x24 9.--31. 1. "Reserved_31_9,Reserved."
newline
bitfld.long 0x24 8. "PFCE,Priority Based Flow Control Enable." "0: Enables generation and reception of IEEE 802,1: Enables generation and reception of.."
newline
hexmask.long.byte 0x24 2.--7. 1. "Reserved_7_2,Reserved."
newline
bitfld.long 0x24 1. "UP,Unicast Pause Packet Detect." "0,1"
newline
bitfld.long 0x24 0. "RFE,Receive Flow Control Enable." "0: When MAC operates in half-duplex mode,1: When MAC operates in full-duplex mode"
line.long 0x28 "MAC_RxQ_Ctrl4,The Receive Queue Control 4 register controls the routing of"
hexmask.long.byte 0x28 27.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x28 24.--26. "PMCBCQ,Preemption Multicast/Broadcast Queue." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x28 20.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x28 17.--19. "VFFQ,VLAN Tag Filter Fail Packets Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable." "0: VLAN tag Filter Fail Packets Queuing is disabled,1: VLAN tag Filter Fail Packets Queuing is enabled"
newline
hexmask.long.byte 0x28 12.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x28 9.--11. "MFFQ,Multicast Address Filter Fail Packets Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 8. "MFFQE,Multicast Filter Fail Packets Queuing Enable." "0: Multicast Address Filter Fail Packets Queuing is..,1: Multicast Address Filter Fail Packets Queuing is.."
newline
hexmask.long.byte 0x28 4.--7. 1. "Reserved_7_y,Reserved."
newline
bitfld.long 0x28 1.--3. "UFFQ,Unicast Address Filter Fail Packets Queue." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 0. "UFFQE,Unicast Filter Fail Packets Queuing Enable." "0: Unicast Address Filter Fail Packets Queuing is..,1: Unicast Address Filter Fail Packets Queuing is.."
line.long 0x2C "MAC_RxQ_Ctrl5,The Receive Queue Control 5 register allows selection of start offset of the Receive queue from which received packets are routed based on VLAN Tag Priority field."
hexmask.long 0x2C 4.--31. 1. "Reserved_31_4,Reserved."
newline
hexmask.long.byte 0x2C 0.--3. 1. "PRQSO,Priority Receive Queue Start Offset."
group.long 0xA0++0xF
line.long 0x0 "MAC_RxQ_Ctrl0,The Receive Queue Control 0 register activates the queue management in the MAC Receiver. This register is present only when you select multiple queues in the Receive path."
rbitfld.long 0x0 30.--31. "Reserved_RXQ15EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 28.--29. "Reserved_RXQ14EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 26.--27. "Reserved_RXQ13EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 24.--25. "Reserved_RXQ12EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 22.--23. "Reserved_RXQ11EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 20.--21. "Reserved_RXQ10EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 18.--19. "Reserved_RXQ9EN,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 16.--17. "Reserved_RXQ8EN,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "RXQ7EN,Receive Queue 7 Enable." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RXQ6EN,Receive Queue 6 Enable." "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "RXQ5EN,Receive Queue 5 Enable." "0,1,2,3"
newline
bitfld.long 0x0 8.--9. "RXQ4EN,Receive Queue 4 Enable." "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "RXQ3EN,Receive Queue 3 Enable." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RXQ2EN,Receive Queue 2 Enable." "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "RXQ1EN,Receive Queue 1 Enable." "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "RXQ0EN,Receive Queue 0 Enable." "0: Not enabled,1: Queue 0 enabled for Audio Video Bridging,2: Queue 0 enabled for Data Center Bridging/Generic,3: Reserved"
line.long 0x4 "MAC_RxQ_Ctrl1,This register allows the selection of the Receive queues to which the received untagged or special packets are routed or written. This register is present only when you select multiple queues in the Receive path."
hexmask.long.byte 0x4 28.--31. 1. "AVCPQ,AV Control Packets Queue."
newline
hexmask.long.byte 0x4 24.--27. 1. "PTPQ,PTP Packets Queue."
newline
bitfld.long 0x4 23. "TACPQE,Tagged AV Control Packets Queuing Enable." "0,1"
newline
bitfld.long 0x4 21.--22. "TPQC,Tagged PTP over Ethernet Packets Queuing Control." "0: VLAN Tagged PTP over Ethernet packets are routed..,1: VLAN Tagged PTP over Ethernet packets are routed..,2: VLAN Tagged PTP over Ethernet packets are routed..,3: Reserved"
newline
bitfld.long 0x4 20. "OMCBCQ,Programmable control for Over-riding MCBCQ Priority." "0,1"
newline
hexmask.long.byte 0x4 16.--19. 1. "DCBCPQ,DCB Control Packets Queue."
newline
bitfld.long 0x4 15. "MCBCQEN,Multicast or Broadcast Queue Enable." "0,1"
newline
rbitfld.long 0x4 12.--14. "Reserved_14_12,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 8.--11. 1. "MCBCQ,Multicast or Broadcast Queue."
newline
hexmask.long.byte 0x4 4.--7. 1. "RQ,Frame Preemption Residue Queue"
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hexmask.long.byte 0x4 0.--3. 1. "UPQ,Untagged Packet Queue."
line.long 0x8 "MAC_RxQ_Ctrl2,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the Rx Queues 0 to 3. This register is present when multiple Rx Queues are selected while configuring the controller."
hexmask.long.byte 0x8 24.--31. 1. "PSRQ3,Priorities Selected in the Receive Queue 3."
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hexmask.long.byte 0x8 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2."
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hexmask.long.byte 0x8 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1."
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hexmask.long.byte 0x8 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0."
line.long 0xC "MAC_RxQ_Ctrl3,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the Rx Queues 4 to 7. This register is present when the 'Enable Data Center Bridging' option is selected and with more.."
hexmask.long.byte 0xC 24.--31. 1. "PSRQ7,Priorities Selected in the Receive Queue 7."
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hexmask.long.byte 0xC 16.--23. 1. "PSRQ6,Priorities Selected in the Receive Queue 6."
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hexmask.long.byte 0xC 8.--15. 1. "PSRQ5,Priorities Selected in the Receive Queue 5."
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hexmask.long.byte 0xC 0.--7. 1. "PSRQ4,Priorities Selected in the Receive Queue 4."
rgroup.long 0xB0++0x3
line.long 0x0 "MAC_Interrupt_Status,The Interrupt Status register contains the status of interrupts."
hexmask.long.byte 0x0 26.--31. 1. "Reserved_31_26,Reserved."
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bitfld.long 0x0 24.--25. "LS,Link Status." "0: Half Duplex,1: Full Duplex,2: 1Gbps,3: Reserved"
newline
bitfld.long 0x0 23. "Reserved_PCIS,Reserved." "0,1"
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hexmask.long.byte 0x0 19.--22. 1. "Reserved_22_19,Reserved."
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bitfld.long 0x0 18. "MFRIS,MMC FPE Receive Interrupt Status" "0,1"
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bitfld.long 0x0 17. "MFTIS,MMC FPE Transmit Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "FPEIS,Frame Preemption Interrupt Status" "0,1"
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bitfld.long 0x0 15. "GPIIS,GPI Interrupt Status." "0,1"
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bitfld.long 0x0 14. "RXESIS,Receive Error Status Interrupt." "0,1"
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bitfld.long 0x0 13. "TXESIS,Transmit Error Status Interrupt." "0,1"
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bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status." "0,1"
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bitfld.long 0x0 11. "MMCRXIPIS,MMC Receive Checksum Offload Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status." "0,1"
newline
bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status." "0,1"
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bitfld.long 0x0 6.--8. "Reserved_8_6,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 5. "Reserved_LPIIS,Reserved." "0,1"
newline
bitfld.long 0x0 4. "Reserved_PMTIS,Reserved." "0,1"
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bitfld.long 0x0 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
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bitfld.long 0x0 1. "SMI,SMA Interrupt." "0,1"
newline
bitfld.long 0x0 0. "LSI,Link Status change Interrupt." "0,1"
group.long 0xB4++0x3
line.long 0x0 "MAC_Interrupt_Enable,The Interrupt Enable register contains the masks for generating the interrupts."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "FPEIE,Frame Preemption Interrupt Enable" "0,1"
newline
bitfld.long 0x0 14. "RXESIE,Receive Error Status Interrupt Enable." "0,1"
newline
bitfld.long 0x0 13. "TXESIE,Transmit Error Status Interrupt Enable." "0,1"
newline
bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable." "0,1"
newline
hexmask.long.byte 0x0 6.--11. 1. "Reserved_11_6,Reserved."
newline
rbitfld.long 0x0 5. "Reserved_LPIIE,Reserved." "0,1"
newline
rbitfld.long 0x0 4. "Reserved_PMTIE,Reserved." "0,1"
newline
rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. "LSIE,Link Status Change Interrupt Enable." "0,1"
rgroup.long 0xB8++0x3
line.long 0x0 "MAC_Rx_Tx_Status,The Receive Transmit Status register contains the Receive and Transmit Error status."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
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bitfld.long 0x0 13. "PCE,Payload Checksum Error." "0,1"
newline
bitfld.long 0x0 12. "IHE,IP Header Error." "0,1"
newline
bitfld.long 0x0 9.--11. "Reserved_11_9,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout." "0,1"
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bitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
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bitfld.long 0x0 5. "EXCOL,Excessive Collisions" "0,1"
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bitfld.long 0x0 4. "LCOL,Late Collision" "0,1"
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bitfld.long 0x0 3. "EXDEF,Excessive Deferral" "0,1"
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bitfld.long 0x0 2. "LCARR,Loss of Carrier" "0,1"
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bitfld.long 0x0 1. "NCARR,No Carrier" "0,1"
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bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout." "0,1"
rgroup.long 0x110++0x7
line.long 0x0 "MAC_Version,The version register identifies the version of DWC_xgmac. This register contains two bytes: one that Synopsys uses to identify the controller release number. and the other that you set while configuring the controller."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
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hexmask.long.byte 0x0 16.--23. 1. "USERVER,User-defined Version (configured with coreConsultant)"
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hexmask.long.byte 0x0 8.--15. 1. "DEVID,Indicates the Device family"
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hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,Synopsys-defined Version (2.0)"
line.long 0x4 "MAC_Debug,The Debug register provides the debug status of various MAC blocks."
hexmask.long.word 0x4 19.--31. 1. "Reserved_31_19,Reserved."
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bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status." "0: Idle state,1: Waiting for one of the following:,2: Generating and transmitting a Pause control packet,3: Transferring input packet for transmission"
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bitfld.long 0x4 16. "TPESTS,MAC GMII Transmit Protocol Engine Status." "0,1"
newline
hexmask.long.word 0x4 3.--15. 1. "Reserved_15_3,Reserved."
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bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status." "0,1,2,3"
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bitfld.long 0x4 0. "RPESTS,MAC  GMII  Receive Protocol Engine Status." "0,1"
rgroup.long 0x11C++0x13
line.long 0x0 "MAC_HW_Feature0,This register indicates the presence of the first set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
bitfld.long 0x0 31. "EDMA,Enhanced DMA." "0,1"
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bitfld.long 0x0 30. "EDIFFC,Different Descriptor Cache." "0,1"
newline
bitfld.long 0x0 29. "VXN,VxLAN/NVGRE Support." "0,1"
newline
bitfld.long 0x0 28. "Reserved_28,Reserved." "0,1"
newline
bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable." "0,1"
newline
bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source." "0: Reserved,1: Internal,?,?"
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bitfld.long 0x0 23.--24. "PHYSEL,RGMII Interface Select" "0,1,2,3"
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hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected."
newline
bitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
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bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled." "0,1"
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bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled." "0,1"
newline
bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled." "0,1"
newline
bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled." "0,1"
newline
bitfld.long 0x0 11. "AVSEL,AV Feature Enabled." "0,1"
newline
bitfld.long 0x0 10. "RAVSEL,Rx Side Only AV Feature Enable." "0,1"
newline
bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled." "0,1"
newline
bitfld.long 0x0 8. "MMCSEL,RMON Module Enable." "0,1"
newline
bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable." "0,1"
newline
bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Enable." "0,1"
newline
bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface." "0,1"
newline
bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected." "0,1"
newline
bitfld.long 0x0 3. "HDSEL,Half-duplex Support" "0,1"
newline
bitfld.long 0x0 2. "RMIISEL,RMII Support." "0,1"
newline
bitfld.long 0x0 1. "GMIISEL,1000/100/10 Mbps Support." "0,1"
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bitfld.long 0x0 0. "RGMIISEL,RGMII Support." "0,1"
line.long 0x4 "MAC_HW_Feature1,This register indicates the presence of second set of the optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
bitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
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hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters."
newline
bitfld.long 0x4 24.--26. "HASHTBLSZ,Hash Table Size." "0: No hash table selected,1: 64,2: 128,3: 256,4: 512,5: 1024,6: 2048,7: 4096"
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bitfld.long 0x4 21.--23. "NUMTC,Number of Traffic Classes." "0: 1 Traffic Class,1: 2 Traffic Classes,2: 3 Traffic Classes,?,?,?,?,7: 8 Traffic"
newline
bitfld.long 0x4 20. "RSSEN,Internal Register based RSS Feature Enabled" "0,1"
newline
bitfld.long 0x4 19. "DBGMEMA,Debug Memory Interface Enabled." "0,1"
newline
bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable." "0,1"
newline
bitfld.long 0x4 17. "SPHEN,Header-Payload Split Feature Enable." "0,1"
newline
bitfld.long 0x4 16. "DCBEN,DCB Feature Enable." "0,1"
newline
bitfld.long 0x4 14.--15. "ADDR64,Address Width." "0: 32,1: 40,2: 48,3: Reserved"
newline
bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable." "0,1"
newline
bitfld.long 0x4 12. "PTOEN,PTP Offload Enable." "0,1"
newline
bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable." "0,1"
newline
hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size."
newline
bitfld.long 0x4 5. "PFCEN,PFC Enable" "0,1"
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hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size."
line.long 0x8 "MAC_HW_Feature2,This register indicates the presence of the third set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
bitfld.long 0x8 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs." "0: No auxiliary input,1: 1 auxiliary input,2: 2 auxiliary inputs,3: 3 auxiliary inputs,4: 4 auxiliary inputs,?,?,7: Reserved"
newline
bitfld.long 0x8 27. "Reserved_27,Reserved." "0,1"
newline
bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs." "0: No PPS output,1: 1 PPS output,2: 2 PPS outputs,3: 3 PPS outputs,4: 4 PPS outputs,?,?,7: Reserved"
newline
bitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels."
newline
bitfld.long 0x8 16.--17. "Reserved_17_16,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels."
newline
bitfld.long 0x8 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues."
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bitfld.long 0x8 4.--5. "Reserved_5_4,Reserved." "0,1,2,3"
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hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues."
line.long 0xC "MAC_HW_Feature3,This register indicates the presence of the fourth set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
hexmask.long.byte 0xC 28.--31. 1. "TBS_CH,The number of DMA channels enabled for TBS (starting from the highest Tx Channel  in descending order)"
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bitfld.long 0xC 27. "TBSSEL,Time Based Scheduling Enable" "0,1"
newline
bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable" "0,1"
newline
bitfld.long 0xC 25. "SGFSEL,Per-Stream Filtering Select" "0,1"
newline
bitfld.long 0xC 23.--24. "GCLWID,Width of the Time Interval field in the Gate Control List" "0,1,2,3"
newline
bitfld.long 0xC 20.--22. "GCLDEP,Depth of the Gate Control List" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 19. "ESTSEL,Enhancements to Scheduling Traffic Enable" "0,1"
newline
bitfld.long 0xC 16.--18. "TTSFD,Tx Timestamp FIFO Depth" "0: Reserved,1: 1,2: 2,3: 4,4: 8,5: 16,6: Reserved,7: Reserved"
newline
bitfld.long 0xC 14.--15. "ASP,Automotive Safety Package" "0: No Safety features selected,1: All the Automotive Safety features are selected..,2: All the Automotive Safety features are selected..,3: All the Automotive Safety features are selected.."
newline
bitfld.long 0xC 13. "DVLAN,Double VLAN Processing Enabled" "0,1"
newline
bitfld.long 0xC 11.--12. "FRPES,Supported Flexible Receive Parser Instructions" "0,1,2,3"
newline
bitfld.long 0xC 9.--10. "FRPPB,Supported Flexible Receive Parser Parsable Bytes" "0,1,2,3"
newline
bitfld.long 0xC 8. "POUOST,One Step for PTP over UDP/IP Feature Enable" "0,1"
newline
bitfld.long 0xC 5.--7. "FRPPIPE,Supported Parallel Instruction Processor Engines (PIPEs)" "0: 1 PIPE,1: 2 PIPEs,?,?,?,?,?,?"
newline
bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable" "0,1"
newline
bitfld.long 0xC 3. "FRPSEL,Supported Flexible Receive Parser." "0,1"
newline
bitfld.long 0xC 0.--2. "NRVF,Enabled number of Extended VLAN Tag Filters or External VLAN tag lookup size" "0: No Extended Rx VLAN Filters,1: 4 Extended Rx VLAN Filters,2: 8 Extended Rx VLAN Filters,3: 16 Extended Rx VLAN Filters,4: 24 Extended Rx VLAN Filters,5: 32 Extended Rx VLAN Filters,6: Reserved,7: External Receive 12bit VLAN Tag Lookup is selected"
line.long 0x10 "MAC_HW_Feature4,This register indicates the presence of the fifth set of optional features or functions of DWC_xgmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks."
hexmask.long 0x10 2.--31. 1. "Reserved_31_2,Reserved."
newline
bitfld.long 0x10 0.--1. "PCSEL,Policing Counters" "0,1,2,3"
group.long 0x140++0x7
line.long 0x0 "MAC_Extended_Configuration,The MAC Extended Configuration register establishes the operating mode of the MAC transmitter."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "HD,Duplex Mode" "0,1"
newline
bitfld.long 0x0 23. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode" "0,1"
newline
bitfld.long 0x0 22. "DO,Disable Receive Own" "0,1"
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bitfld.long 0x0 21. "DCRS,Disable Carrier Sense During Transmission" "0,1"
newline
bitfld.long 0x0 20. "DR,Disable Retry" "0,1"
newline
bitfld.long 0x0 18.--19. "BL,Back-Off Limit" "0,1,2,3"
newline
bitfld.long 0x0 17. "DC,Deferral Check" "0,1"
newline
rbitfld.long 0x0 16. "Reserved_SBDIOEN,Reserved." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_15_10,Reserved."
newline
bitfld.long 0x0 9. "TPRE,Reserved" "0,1"
newline
rbitfld.long 0x0 8. "Reserved_VPRE,Reserved." "0,1"
newline
bitfld.long 0x0 7. "DDS,DA Duplication Select." "0: DCS field in MAC_Address_High register is..,1: XDCS field in MAC_DChSel_IndReg register.."
newline
hexmask.long.byte 0x0 0.--6. 1. "EIPG,Extended Inter-Packet Gap."
line.long 0x4 "MAC_Ext_Cfg1,This register contains Split mode control field and offset field for Header-Payload Split feature."
hexmask.long.byte 0x4 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x4 24. "SAVE,Split AV Enable" "0,1"
newline
rbitfld.long 0x4 23. "Reserved_23,Reserved." "0,1"
newline
hexmask.long.byte 0x4 16.--22. 1. "SAVO,Split AV Offset"
newline
hexmask.long.byte 0x4 10.--15. 1. "Reserved_15_10,Reserved."
newline
bitfld.long 0x4 8.--9. "SPLM,Split Mode" "0,1,2,3"
newline
rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1"
newline
hexmask.long.byte 0x4 0.--6. 1. "SPLOFST,Split Offset"
group.long 0x200++0x13
line.long 0x0 "MDIO_Single_Command_Address,This register contains the addresses of the ports. devices. and registers accessed by the SMA during single read or write transfers."
hexmask.long.byte 0x0 26.--31. 1. "Reserved_31_26,Reserved."
newline
hexmask.long.byte 0x0 21.--25. 1. "DA,Device Address"
newline
hexmask.long.byte 0x0 16.--20. 1. "PA,Port Address"
newline
hexmask.long.word 0x0 0.--15. 1. "RA,Register Address"
line.long 0x4 "MDIO_Single_Command_Control_Data,This register controls single read/write operations. and contains the data bits read on a single-read operation and the data to be written during single-write operations."
bitfld.long 0x4 31. "CRS,Clock Range Select." "0,1"
newline
bitfld.long 0x4 30. "PSE,Preamble Suppression Enable." "0,1"
newline
hexmask.long.byte 0x4 23.--29. 1. "Reserved_29_23,Reserved."
newline
bitfld.long 0x4 22. "SBusy,Busy" "0,1"
newline
bitfld.long 0x4 19.--21. "CR,Application Clock Range" "0: MDC clock: clk_csr_i/4,1: MDC clock: clk_csr_i/6,2: MDC clock: clk_csr_i/8,3: MDC clock: clk_csr_i/10,4: MDC clock: clk_csr_i/12,5: MDC clock: clk_csr_i/14,6: MDC clock: clk_csr_i/16,7: MDC clock: clk_csr_i/18"
newline
bitfld.long 0x4 18. "SAADR,Skip Address Frame" "0,1"
newline
bitfld.long 0x4 16.--17. "CMD,Control Command" "0: Reserved,1: SINGLE_WRITE,2: POST INCREMENT READ OPERATION,3: SINGLE_READ"
newline
hexmask.long.word 0x4 0.--15. 1. "SDATA,Single Write Data"
line.long 0x8 "MDIO_Continuous_Write_Address,You can program this register to start continuous write operation."
hexmask.long.word 0x8 23.--31. 1. "Reserved_31_23,Reserved."
newline
bitfld.long 0x8 22. "CBUSY,Continuous Write Busy" "0,1"
newline
bitfld.long 0x8 21. "CPRT,Continuous Port or Device Address Select" "0,1"
newline
hexmask.long.byte 0x8 16.--20. 1. "CADDR,Continuous Port or Device Address"
newline
hexmask.long.word 0x8 0.--15. 1. "CREGADDR,Continuous Register Address"
line.long 0xC "MDIO_Continuous_Write_Data,This register contains the data to be written during continuous write operation. Do not change the register's contents until the Continuous Write Busy bit (CBUSY) is cleared."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "CDATA,Continuous Write Data"
line.long 0x10 "MDIO_Continuous_Scan_Port_Enable,This register controls the PHY ports and corresponding devices (enabled by the corresponding Device In Use register) to be accessed during the SMA's continuous scan operation. If you change any bit in this register during.."
bitfld.long 0x10 31. "PORT31SCE,Port 31 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 30. "PORT30SCE,Port 30 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 29. "PORT29SCE,Port 29 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 28. "PORT28SCE,Port 28 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 27. "PORT27SCE,Port 27 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 26. "PORT26SCE,Port 26 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 25. "PORT25SCE,Port 25 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 24. "PORT24SCE,Port 24 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 23. "PORT23SCE,Port 23 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 22. "PORT22SCE,Port 22 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 21. "PORT21SCE,Port 21 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 20. "PORT20SCE,Port 20 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 19. "PORT19SCE,Port 19 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 18. "PORT18SCE,Port 18 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 17. "PORT17SCE,Port 17 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 16. "PORT16SCE,Port 16 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 15. "PORT15SCE,Port 15 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 14. "PORT14SCE,Port 14 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 13. "PORT13SCE,Port 13 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 12. "PORT12SCE,Port 12 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 11. "PORT11SCE,Port 11 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 10. "PORT10SCE,Port 10 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 9. "PORT9SCE,Port 9 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 8. "PORT8SCE,Port 8 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 7. "PORT7SCE,Port 7 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 6. "PORT6SCE,Port 6 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 5. "PORT5SCE,Port 5 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 4. "PORT4SCE,Port 4 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 3. "PORT3SCE,Port 3 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 2. "PORT2SCE,Port 2 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 1. "PORT1SCE,Port 1 Continuous Scan Enable." "0,1"
newline
bitfld.long 0x10 0. "PORT0SCE,Port 0 Continuous Scan Enable." "0,1"
rgroup.long 0x214++0x3
line.long 0x0 "MDIO_Interrupt_Status,This register gives the source of the interrupt raised by the SMA module on the sbd_intr_o output line. The status bits are cleared when the software reads the corresponding bytes."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
newline
bitfld.long 0x0 13. "CWCOMPINT,Continuous Write Completion Interrupt." "0,1"
newline
bitfld.long 0x0 12. "SNGLCOMPINT,Single Command Completion Interrupt." "0,1"
newline
bitfld.long 0x0 11. "PORTNx4P3ALINT,Device Present Status Change Interrupt (Port Nx4 Plus3)." "0,1"
newline
bitfld.long 0x0 10. "PORTNx4P2ALINT,Device Present Status Change Interrupt (Port Nx4 Plus2)." "0,1"
newline
bitfld.long 0x0 9. "PORTNx4P1ALINT,Device Present Status Change Interrupt (Port Nx4 Plus1)." "0,1"
newline
bitfld.long 0x0 8. "PORTNx4P0ALINT,Device Present Status Change Interrupt (Port Nx4 Plus0)." "0,1"
newline
bitfld.long 0x0 7. "PORTNx4P3LSINT,Link Status Change Interrupt (Port Nx4 Plus3)." "0,1"
newline
bitfld.long 0x0 6. "PORTNx4P2LSINT,Link Status Change Interrupt (Port Nx4 Plus2)." "0,1"
newline
bitfld.long 0x0 5. "PORTNx4P1LSINT,Link Status Change Interrupt (Port Nx4 Plus1)." "0,1"
newline
bitfld.long 0x0 4. "PORTNx4P0LSINT,Link Status Change Interrupt (Port Nx4 Plus0)." "0,1"
newline
bitfld.long 0x0 3. "PORTNx4P3CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus3)." "0,1"
newline
bitfld.long 0x0 2. "PORTNx4P2CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus2)." "0,1"
newline
bitfld.long 0x0 1. "PORTNx4P1CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus1)." "0,1"
newline
bitfld.long 0x0 0. "PORTNx4P0CONINT,Connect/Disconnect Event Interrupt (Port Nx4 Plus0)." "0,1"
group.long 0x218++0x3
line.long 0x0 "MDIO_Interrupt_Enable,This register controls the enabling of interrupt sources in the MDIO Interrupt Status register."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
newline
bitfld.long 0x0 13. "CWCOMPIE,Continuous Write Completion Interrupt Enable." "0,1"
newline
bitfld.long 0x0 12. "SNGLCOMPIE,Single Command Completion Interrupt Enable." "0,1"
newline
bitfld.long 0x0 11. "PTRNx4P3ALIE,Device Present Status Change Interrupt (Port Nx4 Plus3) Enable." "0,1"
newline
bitfld.long 0x0 10. "PTRNx4P2ALIE,Device Present Status Change Interrupt (Port Nx4 Plus2) Enable." "0,1"
newline
bitfld.long 0x0 9. "PTRNx4P1ALIE,Device Present Status Change Interrupt (Port Nx4 Plus1) Enable." "0,1"
newline
bitfld.long 0x0 8. "PTRNx4P0ALIE,Device Present Status Change Interrupt (Port Nx4 Plus0) Enable." "0,1"
newline
bitfld.long 0x0 7. "PTRNx4P3LSIE,Link Status Change Interrupt (Port Nx4 Plus3) Enable." "0,1"
newline
bitfld.long 0x0 6. "PTRNx4P2LSIE,Link Status Change Interrupt (Port Nx4 Plus2) Enable." "0,1"
newline
bitfld.long 0x0 5. "PTRNx4P1LSIE,Link Status Change Interrupt (Port Nx4 Plus1) Enable." "0,1"
newline
bitfld.long 0x0 4. "PTRNx4P0LSIE,Link Status Change Interrupt (Port Nx4 Plus0) Enable." "0,1"
newline
bitfld.long 0x0 3. "PTRNx4P3CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus3) Enable." "0,1"
newline
bitfld.long 0x0 2. "PTRNx4P2CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus2) Enable." "0,1"
newline
bitfld.long 0x0 1. "PTRNx4P1CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus1) Enable." "0,1"
newline
bitfld.long 0x0 0. "PTRNx4P0CONIE,Connect/Disconnect Event Interrupt (Port Nx4 Plus0) Enable." "0,1"
rgroup.long 0x21C++0x3
line.long 0x0 "MDIO_Port_Connect_Disconnect_Status,This register gives the hot plug-in status for Ports 0-31. This register is updated at the end of any read operation to any register of the corresponding PHY port. It is updated during single-read transfers or during.."
bitfld.long 0x0 31. "PORT31CON,Port 31 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 30. "PORT30CON,Port 30 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 29. "PORT29CON,Port 29 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 28. "PORT28CON,Port 28 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 27. "PORT27CON,Port 27 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 26. "PORT26CON,Port 26 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 25. "PORT25CON,Port 25 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 24. "PORT24CON,Port 24 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 23. "PORT23CON,Port 23 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 22. "PORT22CON,Port 22 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 21. "PORT21CON,Port 21 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 20. "PORT20CON,Port 20 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 19. "PORT19CON,Port 19 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 18. "PORT18CON,Port 18 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 17. "PORT17CON,Port 17 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 16. "PORT16CON,Port 16 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 15. "PORT15CON,Port 15 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 14. "PORT14CON,Port 14 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 13. "PORT13CON,Port 13 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 12. "PORT12CON,Port 12 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 11. "PORT11CON,Port 11 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 10. "PORT10CON,Port 10 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 9. "PORT9CON,Port 9 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 8. "PORT8CON,Port 8 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 7. "PORT7CON,Port 7 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 6. "PORT6CON,Port 6 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 5. "PORT5CON,Port 5 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 4. "PORT4CON,Port 4 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 3. "PORT3CON,Port 3 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 2. "PORT2CON,Port 2 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 1. "PORT1CON,Port 1 Connect/Disconnect." "0,1"
newline
bitfld.long 0x0 0. "PORT0CON,Port 0 Connect/Disconnect." "0,1"
group.long 0x220++0x7
line.long 0x0 "MDIO_Clause_22_Port,This register configures the SMA to access the PHY ports using either the Clause 22 or Clause 45 packet format. All SMA operations (single or continuous) depend on setting these bits correctly."
bitfld.long 0x0 31. "PTR31CL22,Port31CL22 Enable. Indicates that Port 31 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 30. "PTR30CL22,Port30CL22 Enable. Indicates that Port 30 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 29. "PTR29CL22,Port29CL22 Enable. Indicates that Port 29 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 28. "PTR28CL22,Port28CL22 Enable. Indicates that Port 28 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 27. "PTR27CL22,Port27CL22 Enable. Indicates that Port 27 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 26. "PTR26CL22,Port26CL22 Enable. Indicates that Port 26 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 25. "PTR25CL22,Port25CL22 Enable. Indicates that Port 25 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 24. "PTR24CL22,Port24CL22 Enable. Indicates that Port 24 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 23. "PTR23CL22,Port23CL22 Enable. Indicates that Port 23 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 22. "PTR22CL22,Port22CL22 Enable. Indicates that Port 22 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 21. "PTR21CL22,Port21CL22 Enable. Indicates that Port 21 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 20. "PTR20CL22,Port20CL22 Enable. Indicates that Port 20 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 19. "PTR19CL22,Port19CL22 Enable. Indicates that Port 19 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 18. "PTR18CL22,Port18CL22 Enable. Indicates that Port 18 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 17. "PTR17CL22,Port17CL22 Enable. Indicates that Port 17 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 16. "PTR16CL22,Port16CL22 Enable. Indicates that Port 16 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 15. "PTR15CL22,Port15CL22 Enable. Indicates that Port 15 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 14. "PTR14CL22,Port14CL22 Enable. Indicates that Port 14 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 13. "PTR13CL22,Port13CL22 Enable. Indicates that Port 13 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 12. "PTR12CL22,Port12CL22 Enable. Indicates that Port 12 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 11. "PTR11CL22,Port11CL22 Enable. Indicates that Port 11 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 10. "PTR10CL22,Port10CL22 Enable. Indicates that Port 10 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 9. "PTR9CL22,Port9CL22 Enable. Indicates that Port 9 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 8. "PTR8CL22,Port8CL22 Enable. Indicates that Port 8 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 7. "PTR7CL22,Port7CL22 Enable. Indicates that Port 7 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 6. "PTR6CL22,Port6CL22 Enable. Indicates that Port 6 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 5. "PTR5CL22,Port5CL22 Enable. Indicates that Port 5 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 4. "PTR4CL22,Port4CL22 Enable. Indicates that Port 4 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 3. "PTR3CL22,Port3CL22 Enable. Indicates that Port 3 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 2. "PTR2CL22,Port2CL22 Enable. Indicates that Port 2 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 1. "PTR1CL22,Port1CL22 Enable. Indicates that Port 1 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
newline
bitfld.long 0x0 0. "PTR0CL22,Port0CL22 Enable. Indicates that Port 0 is connected to a PHY that only supports Clause 22. When this bit is reset  the PHY supports Clause 45." "0,1"
line.long 0x4 "MDIO_Port_Nx4_Indirect_Control,This register contain fields that control the Port range select for accessing register sets."
hexmask.long 0x4 3.--31. 1. "Reserved_31_3,Reserved."
newline
bitfld.long 0x4 0.--2. "PRS,Port Range Select." "0: Selects the Port address range of 0 to 3,1: Selects the Port Address range of 4 to 7,2: Selects the Port Address range of 8 to 11,3: Selects the Port Address range of 12 to 15,4: Selects the Port Address range of 16 to 19,5: Selects the Port Address range of 20 to 23,6: Selects the Port Address range of 24 to 27,7: Selects the Port Address range of 28 to 31"
group.long 0x230++0x3
line.long 0x0 "MDIO_PortNx4P0_Device_In_Use,This register gives the status of each device on Port Nx4 Plus0 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P0VSD2,VSD2 Device is in Use" "0,1"
newline
bitfld.long 0x0 30. "Nx4P0VSD1,VSD1 Device is in Use" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P0TC,TC Device is in Use" "0,1"
newline
bitfld.long 0x0 5. "Nx4P0DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P0PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P0PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P0WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P0PMDPMA,PMA Device is in Use" "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x234++0x7
line.long 0x0 "MDIO_PortNx4P0_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus0 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported..."
bitfld.long 0x0 31. "Nx4P0VSD2LS,Link Status of VSD2 Device" "0,1"
newline
bitfld.long 0x0 30. "Nx4P0VSD1LS,Link Status of VCD1 Device" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P0TCLS,Link Status of TC Device" "0,1"
newline
bitfld.long 0x0 5. "Nx4P0DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P0PHYXSLS,Link Status of PHYXS Device" "0,1"
newline
bitfld.long 0x0 3. "Nx4P0PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P0WISLS,Link Status of WIS Device" "0,1"
newline
bitfld.long 0x0 1. "Nx4P0PMDPMALS,Link Status of PMA Device" "0,1"
newline
bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P0_Alive_Status,This register gives the device status in PHY Port Nx4Plus0 ((Here N is as per PRS field of 'MDIO Port Nx4 Indirect Control' register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified in.."
bitfld.long 0x4 31. "Nx4P0VSD2LS,Alive Status of VSD2 Device" "0,1"
newline
bitfld.long 0x4 30. "Nx4P0VSD1LS,Alive Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x4 6. "Nx4P0TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P0DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P0PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P0PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P0WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P0PMDPMALS,Alive Status of PMA Device" "0,1"
newline
bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x240++0x3
line.long 0x0 "MDIO_PortNx4P1_Device_In_Use,This register gives the status of each device on Port Nx4 Plus1 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P1VSD2,VSD2 Device is in Use" "0,1"
newline
bitfld.long 0x0 30. "Nx4P1VSD1,VSD1 Device is in Use" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P1TC,TC Device is in Use" "0,1"
newline
bitfld.long 0x0 5. "Nx4P1DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P1PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P1PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P1WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P1PMDPMA,PMA Device is in Use" "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x244++0x7
line.long 0x0 "MDIO_PortNx4P1_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus1 ((Here N is as per PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as.."
bitfld.long 0x0 31. "Nx4P1VSD2LS,Link Status of VSD2 Device" "0,1"
newline
bitfld.long 0x0 30. "Nx4P1VSD1LS,Link Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P1TCLS,Link Status of TC Device" "0,1"
newline
bitfld.long 0x0 5. "Nx4P1DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P1PHYXSLS,Link Status of PHYXS Device" "0,1"
newline
bitfld.long 0x0 3. "Nx4P1PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P1WISLS,Link Status of WIS Device" "0,1"
newline
bitfld.long 0x0 1. "Nx4P1PMDPMALS,Link Status of PMA Device" "0,1"
newline
bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P1_Alive_Status,This register gives the device status in PHY Port Nx4Plus1 ((Here N is as per PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified in.."
bitfld.long 0x4 31. "Nx4P1VSD2LS,Alive Status of VSD2 Device" "0,1"
newline
bitfld.long 0x4 30. "Nx4P1VSD1LS,Alive Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x4 6. "Nx4P1TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P1DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P1PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P1PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P1WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P1PMDPMALS,Alive Status of PMA Device" "0,1"
newline
bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x250++0x3
line.long 0x0 "MDIO_PortNx4P2_Device_In_Use,This register gives the status of each device on Port Nx4 Plus2 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P2VSD2,VSD2 Device is in Use" "0,1"
newline
bitfld.long 0x0 30. "Nx4P2VSD1,VSD1 Device is in Use" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P2TC,TC Device is in Use" "0,1"
newline
bitfld.long 0x0 5. "Nx4P2DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P2PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P2PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P2WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P2PMDPMA,PMA Device is in Use" "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x254++0x7
line.long 0x0 "MDIO_PortNx4P2_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus2 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported..."
bitfld.long 0x0 31. "Nx4P2VSD2LS,Link Status of VSD2 Device" "0,1"
newline
bitfld.long 0x0 30. "Nx4P2VSD1LS,Link Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P2TCLS,Link Status of TC Device" "0,1"
newline
bitfld.long 0x0 5. "Nx4P2DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P2PHYXSLS,Link Status of PHYXS Device" "0,1"
newline
bitfld.long 0x0 3. "Nx4P2PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P2WISLS,Link Status of WIS Device" "0,1"
newline
bitfld.long 0x0 1. "Nx4P2PMDPMALS,Link Status of PMA Device" "0,1"
newline
bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P2_Alive_Status,This register gives the device status in PHY Port Nx4Plus2 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified.."
bitfld.long 0x4 31. "Nx4P2VSD2LS,Alive Status of VSD2 Device" "0,1"
newline
bitfld.long 0x4 30. "Nx4P2VSD1LS,Alive Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x4 6. "Nx4P2TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P2DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P2PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P2PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P2WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P2PMDPMALS,Alive Status of PMA Device" "0,1"
newline
bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x260++0x3
line.long 0x0 "MDIO_PortNx4P3_Device_In_Use,This register gives the status of each device on Port Nx4 Plus3 (Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register). Set these bits to indicate that a device is present and that the SMA must access it.."
bitfld.long 0x0 31. "Nx4P3VSD2,VSD2 Device is in Use" "0,1"
newline
bitfld.long 0x0 30. "Nx4P3VSD1,VSD1 Device is in Use" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P3TC,TC Device is in Use" "0,1"
newline
bitfld.long 0x0 5. "Nx4P3DTEXS,DTEXS Device is in Use" "0,1"
newline
bitfld.long 0x0 4. "Nx4P3PHYXS,PHYXS Device is in Use" "0,1"
newline
bitfld.long 0x0 3. "Nx4P3PCS,PCS Device is in Use" "0,1"
newline
bitfld.long 0x0 2. "Nx4P3WIS,WIS Device is in Use" "0,1"
newline
bitfld.long 0x0 1. "Nx4P3PMDPMA,PMA Device is in Use" "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
rgroup.long 0x264++0x7
line.long 0x0 "MDIO_PortNx4P3_Link_Status,This register gives the link status of the devices in PHY Port Nx4Plus3 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported..."
bitfld.long 0x0 31. "Nx4P3VSD2LS,Link Status of VSD2 Device" "0,1"
newline
bitfld.long 0x0 30. "Nx4P3VSD1LS,Link Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x0 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x0 6. "Nx4P3TCLS,Link Status of TC Device" "0,1"
newline
bitfld.long 0x0 5. "Nx4P3DTEXSLS,Link Status of DTEXS Device" "0,1"
newline
bitfld.long 0x0 4. "Nx4P3PHYXSLS,Link Status of PHYXS Device" "0,1"
newline
bitfld.long 0x0 3. "Nx4P3PCSLS,Link Status of PCS Device" "0,1"
newline
bitfld.long 0x0 2. "Nx4P3WISLS,Link Status of WIS Device" "0,1"
newline
bitfld.long 0x0 1. "Nx4P3PMDPMALS,Link Status of PMA Device" "0,1"
newline
bitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
line.long 0x4 "MDIO_PortNx4P3_Alive_Status,This register gives the device status in PHY Port Nx4Plus3 ((Here N is as per the PRS field of MDIO Port Nx4 Indirect Control register) at the end of each continuous scan cycle. Up to eight devices are supported. as specified.."
bitfld.long 0x4 31. "Nx4P3VSD2LS,Alive Status of VSD2 Device" "0,1"
newline
bitfld.long 0x4 30. "Nx4P3VSD1LS,Alive Status of VSD1 Device" "0,1"
newline
hexmask.long.tbyte 0x4 7.--29. 1. "Reserved_29_7,Reserved."
newline
bitfld.long 0x4 6. "Nx4P3TCLS,Alive Status of TC Device" "0,1"
newline
bitfld.long 0x4 5. "Nx4P3DTEXSLS,Alive Status of DTEXS Device" "0,1"
newline
bitfld.long 0x4 4. "Nx4P3PHYXSLS,Alive Status of PHYXS Device" "0,1"
newline
bitfld.long 0x4 3. "Nx4P3PCSLS,Alive Status of PCS Device" "0,1"
newline
bitfld.long 0x4 2. "Nx4P3WISLS,Alive Status of WIS Device" "0,1"
newline
bitfld.long 0x4 1. "Nx4P3PMDPMALS,Alive Status of PMA Device" "0,1"
newline
bitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x278++0xB
line.long 0x0 "MAC_GPIO_Control,The GPIO Control register controls the GPIO."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--23. 1. "GPIT,GPI Type."
newline
hexmask.long.word 0x0 4.--15. 1. "Reserved_15_4,Reserved."
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hexmask.long.byte 0x0 0.--3. 1. "GPIE,GPI Interrupt Enable."
line.long 0x4 "MAC_GPIO_Status,The General Purpose IO register provides the control to drive the following: up to 16 bits of output ports (GPO) and status of up to 16 input ports (GPIS)."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--23. 1. "GPO,General Purpose Output."
newline
hexmask.long.byte 0x4 8.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "GPIS,General Purpose Input Status."
line.long 0x8 "MAC_FPE_CTRL_STS,This register controls the operation of Frame Preemption."
hexmask.long.word 0x8 20.--31. 1. "Reserved_31_20,Reserved."
newline
rbitfld.long 0x8 19. "TRSP,Transmitted Respond Frame" "0,1"
newline
rbitfld.long 0x8 18. "TVER,Transmitted Verify Frame" "0,1"
newline
rbitfld.long 0x8 17. "RRSP,Received Respond Frame" "0,1"
newline
rbitfld.long 0x8 16. "RVER,Received Verify Frame" "0,1"
newline
hexmask.long.word 0x8 4.--15. 1. "Reserved_15_4,Reserved."
newline
bitfld.long 0x8 3. "ARV,Autogenerate Respond mPacket on receiving Verify mPacket" "0,1"
newline
bitfld.long 0x8 2. "SRSP,Send Respond mPacket" "0,1"
newline
bitfld.long 0x8 1. "SVER,Send Verify mPacket" "0,1"
newline
bitfld.long 0x8 0. "EFPE,Enable Tx Frame Preemption" "0,1"
group.long 0x290++0x3
line.long 0x0 "MAC_CSR_SW_Ctrl,This register contains software programmable controls for changing the CSR access response and status bits clearing."
hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved."
newline
bitfld.long 0x0 8. "SEEN,Slave Error Response Enable" "0,1"
newline
hexmask.long.byte 0x0 1.--7. 1. "Reserved_7_1,Reserved."
newline
bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable" "0,1"
group.long 0x300++0xFF
line.long 0x0 "MAC_Address0_High,The MAC_Address0_High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address0_Low register."
rbitfld.long 0x0 31. "AE,Address Enable." "0,1"
newline
hexmask.long.word 0x0 19.--30. 1. "Reserved_30_y,Reserved."
newline
bitfld.long 0x0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32]."
line.long 0x4 "MAC_Address0_Low,The MAC_Address0_Low register holds the lower 32 bits of the 0th 6-byte MAC address of the station."
hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address0 [31:0]."
line.long 0x8 "MAC_Address1_High,The MAC_Address1_High register holds the upper 16 bits of the 1th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address1_Low register. For.."
bitfld.long 0x8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 1th MAC.."
newline
bitfld.long 0x8 30. "SA,Source Address." "0: The MAC Address1[47:0] is used to compare with..,1: The MAC Address1[47:0] is used to compare with.."
newline
hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x8 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32]."
line.long 0xC "MAC_Address1_Low,The MAC_Address1_Low register holds the lower 32 bits of the 1th 6-byte MAC address of the station."
hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address1 [31:0]."
line.long 0x10 "MAC_Address2_High,The MAC_Address2_High register holds the upper 16 bits of the 2th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address2_Low register. For.."
bitfld.long 0x10 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 2th MAC.."
newline
bitfld.long 0x10 30. "SA,Source Address." "0: The MAC Address2[47:0] is used to compare with..,1: The MAC Address2[47:0] is used to compare with.."
newline
hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x10 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x10 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address2 [47:32]."
line.long 0x14 "MAC_Address2_Low,The MAC_Address2_Low register holds the lower 32 bits of the 2th 6-byte MAC address of the station."
hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address2 [31:0]."
line.long 0x18 "MAC_Address3_High,The MAC_Address3_High register holds the upper 16 bits of the 3th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address3_Low register. For.."
bitfld.long 0x18 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 3th MAC.."
newline
bitfld.long 0x18 30. "SA,Source Address." "0: The MAC Address3[47:0] is used to compare with..,1: The MAC Address3[47:0] is used to compare with.."
newline
hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x18 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x18 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address3 [47:32]."
line.long 0x1C "MAC_Address3_Low,The MAC_Address3_Low register holds the lower 32 bits of the 3th 6-byte MAC address of the station."
hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address3 [31:0]."
line.long 0x20 "MAC_Address4_High,The MAC_Address4_High register holds the upper 16 bits of the 4th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address4_Low register. For.."
bitfld.long 0x20 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 4th MAC.."
newline
bitfld.long 0x20 30. "SA,Source Address." "0: The MAC Address4[47:0] is used to compare with..,1: The MAC Address4[47:0] is used to compare with.."
newline
hexmask.long.byte 0x20 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x20 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x20 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 0.--15. 1. "ADDRHI,MAC Address4 [47:32]."
line.long 0x24 "MAC_Address4_Low,The MAC_Address4_Low register holds the lower 32 bits of the 4th 6-byte MAC address of the station."
hexmask.long 0x24 0.--31. 1. "ADDRLO,MAC Address4 [31:0]."
line.long 0x28 "MAC_Address5_High,The MAC_Address5_High register holds the upper 16 bits of the 5th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address5_Low register. For.."
bitfld.long 0x28 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 5th MAC.."
newline
bitfld.long 0x28 30. "SA,Source Address." "0: The MAC Address5[47:0] is used to compare with..,1: The MAC Address5[47:0] is used to compare with.."
newline
hexmask.long.byte 0x28 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x28 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x28 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 0.--15. 1. "ADDRHI,MAC Address5 [47:32]."
line.long 0x2C "MAC_Address5_Low,The MAC_Address5_Low register holds the lower 32 bits of the 5th 6-byte MAC address of the station."
hexmask.long 0x2C 0.--31. 1. "ADDRLO,MAC Address5 [31:0]."
line.long 0x30 "MAC_Address6_High,The MAC_Address6_High register holds the upper 16 bits of the 6th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address6_Low register. For.."
bitfld.long 0x30 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 6th MAC.."
newline
bitfld.long 0x30 30. "SA,Source Address." "0: The MAC Address6[47:0] is used to compare with..,1: The MAC Address6[47:0] is used to compare with.."
newline
hexmask.long.byte 0x30 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x30 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x30 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 0.--15. 1. "ADDRHI,MAC Address6 [47:32]."
line.long 0x34 "MAC_Address6_Low,The MAC_Address6_Low register holds the lower 32 bits of the 6th 6-byte MAC address of the station."
hexmask.long 0x34 0.--31. 1. "ADDRLO,MAC Address6 [31:0]."
line.long 0x38 "MAC_Address7_High,The MAC_Address7_High register holds the upper 16 bits of the 7th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address7_Low register. For.."
bitfld.long 0x38 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 7th MAC.."
newline
bitfld.long 0x38 30. "SA,Source Address." "0: The MAC Address7[47:0] is used to compare with..,1: The MAC Address7[47:0] is used to compare with.."
newline
hexmask.long.byte 0x38 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x38 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x38 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 0.--15. 1. "ADDRHI,MAC Address7 [47:32]."
line.long 0x3C "MAC_Address7_Low,The MAC_Address7_Low register holds the lower 32 bits of the 7th 6-byte MAC address of the station."
hexmask.long 0x3C 0.--31. 1. "ADDRLO,MAC Address7 [31:0]."
line.long 0x40 "MAC_Address8_High,The MAC_Address8_High register holds the upper 16 bits of the 8th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address8_Low register. For.."
bitfld.long 0x40 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 8th MAC.."
newline
bitfld.long 0x40 30. "SA,Source Address." "0: The MAC Address8[47:0] is used to compare with..,1: The MAC Address8[47:0] is used to compare with.."
newline
hexmask.long.byte 0x40 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x40 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x40 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x40 0.--15. 1. "ADDRHI,MAC Address8 [47:32]."
line.long 0x44 "MAC_Address8_Low,The MAC_Address8_Low register holds the lower 32 bits of the 8th 6-byte MAC address of the station."
hexmask.long 0x44 0.--31. 1. "ADDRLO,MAC Address8 [31:0]."
line.long 0x48 "MAC_Address9_High,The MAC_Address9_High register holds the upper 16 bits of the 9th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address9_Low register. For.."
bitfld.long 0x48 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 9th MAC.."
newline
bitfld.long 0x48 30. "SA,Source Address." "0: The MAC Address9[47:0] is used to compare with..,1: The MAC Address9[47:0] is used to compare with.."
newline
hexmask.long.byte 0x48 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x48 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x48 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x48 0.--15. 1. "ADDRHI,MAC Address9 [47:32]."
line.long 0x4C "MAC_Address9_Low,The MAC_Address9_Low register holds the lower 32 bits of the 9th 6-byte MAC address of the station."
hexmask.long 0x4C 0.--31. 1. "ADDRLO,MAC Address9 [31:0]."
line.long 0x50 "MAC_Address10_High,The MAC_Address10_High register holds the upper 16 bits of the 10th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address10_Low register."
bitfld.long 0x50 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 10th MAC.."
newline
bitfld.long 0x50 30. "SA,Source Address." "0: The MAC Address10[47:0] is used to compare with..,1: The MAC Address10[47:0] is used to compare with.."
newline
hexmask.long.byte 0x50 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x50 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x50 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x50 0.--15. 1. "ADDRHI,MAC Address10 [47:32]."
line.long 0x54 "MAC_Address10_Low,The MAC_Address10_Low register holds the lower 32 bits of the 10th 6-byte MAC address of the station."
hexmask.long 0x54 0.--31. 1. "ADDRLO,MAC Address10 [31:0]."
line.long 0x58 "MAC_Address11_High,The MAC_Address11_High register holds the upper 16 bits of the 11th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address11_Low register."
bitfld.long 0x58 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 11th MAC.."
newline
bitfld.long 0x58 30. "SA,Source Address." "0: The MAC Address11[47:0] is used to compare with..,1: The MAC Address11[47:0] is used to compare with.."
newline
hexmask.long.byte 0x58 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x58 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x58 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x58 0.--15. 1. "ADDRHI,MAC Address11 [47:32]."
line.long 0x5C "MAC_Address11_Low,The MAC_Address11_Low register holds the lower 32 bits of the 11th 6-byte MAC address of the station."
hexmask.long 0x5C 0.--31. 1. "ADDRLO,MAC Address11 [31:0]."
line.long 0x60 "MAC_Address12_High,The MAC_Address12_High register holds the upper 16 bits of the 12th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address12_Low register."
bitfld.long 0x60 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 12th MAC.."
newline
bitfld.long 0x60 30. "SA,Source Address." "0: The MAC Address12[47:0] is used to compare with..,1: The MAC Address12[47:0] is used to compare with.."
newline
hexmask.long.byte 0x60 24.--29. 1. "MBC,Mask Byte Control."
newline
hexmask.long.byte 0x60 19.--23. 1. "Reserved_23_y,Reserved."
newline
bitfld.long 0x60 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x60 0.--15. 1. "ADDRHI,MAC Address12 [47:32]."
line.long 0x64 "MAC_Address12_Low,The MAC_Address12_Low register holds the lower 32 bits of the 12th 6-byte MAC address of the station."
hexmask.long 0x64 0.--31. 1. "ADDRLO,MAC Address12 [31:0]."
line.long 0x68 "MAC_Address13_High,The MAC_Address13_High register holds the upper 16 bits of the 13th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address13_Low register."
bitfld.long 0x68 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 13th MAC.."
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bitfld.long 0x68 30. "SA,Source Address." "0: The MAC Address13[47:0] is used to compare with..,1: The MAC Address13[47:0] is used to compare with.."
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hexmask.long.byte 0x68 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x68 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x68 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x68 0.--15. 1. "ADDRHI,MAC Address13 [47:32]."
line.long 0x6C "MAC_Address13_Low,The MAC_Address13_Low register holds the lower 32 bits of the 13th 6-byte MAC address of the station."
hexmask.long 0x6C 0.--31. 1. "ADDRLO,MAC Address13 [31:0]."
line.long 0x70 "MAC_Address14_High,The MAC_Address14_High register holds the upper 16 bits of the 14th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address14_Low register."
bitfld.long 0x70 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 14th MAC.."
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bitfld.long 0x70 30. "SA,Source Address." "0: The MAC Address14[47:0] is used to compare with..,1: The MAC Address14[47:0] is used to compare with.."
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hexmask.long.byte 0x70 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x70 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x70 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x70 0.--15. 1. "ADDRHI,MAC Address14 [47:32]."
line.long 0x74 "MAC_Address14_Low,The MAC_Address14_Low register holds the lower 32 bits of the 14th 6-byte MAC address of the station."
hexmask.long 0x74 0.--31. 1. "ADDRLO,MAC Address14 [31:0]."
line.long 0x78 "MAC_Address15_High,The MAC_Address15_High register holds the upper 16 bits of the 15th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address15_Low register."
bitfld.long 0x78 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 15th MAC.."
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bitfld.long 0x78 30. "SA,Source Address." "0: The MAC Address15[47:0] is used to compare with..,1: The MAC Address15[47:0] is used to compare with.."
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hexmask.long.byte 0x78 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x78 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x78 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x78 0.--15. 1. "ADDRHI,MAC Address15 [47:32]."
line.long 0x7C "MAC_Address15_Low,The MAC_Address15_Low register holds the lower 32 bits of the 15th 6-byte MAC address of the station."
hexmask.long 0x7C 0.--31. 1. "ADDRLO,MAC Address15 [31:0]."
line.long 0x80 "MAC_Address16_High,The MAC_Address16_High register holds the upper 16 bits of the 16th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address16_Low register."
bitfld.long 0x80 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 16th MAC.."
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bitfld.long 0x80 30. "SA,Source Address." "0: The MAC Address16[47:0] is used to compare with..,1: The MAC Address16[47:0] is used to compare with.."
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hexmask.long.byte 0x80 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x80 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x80 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x80 0.--15. 1. "ADDRHI,MAC Address16 [47:32]."
line.long 0x84 "MAC_Address16_Low,The MAC_Address16_Low register holds the lower 32 bits of the 16th 6-byte MAC address of the station."
hexmask.long 0x84 0.--31. 1. "ADDRLO,MAC Address16 [31:0]."
line.long 0x88 "MAC_Address17_High,The MAC_Address17_High register holds the upper 16 bits of the 17th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address17_Low register."
bitfld.long 0x88 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 17th MAC.."
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bitfld.long 0x88 30. "SA,Source Address." "0: The MAC Address17[47:0] is used to compare with..,1: The MAC Address17[47:0] is used to compare with.."
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hexmask.long.byte 0x88 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x88 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x88 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x88 0.--15. 1. "ADDRHI,MAC Address17 [47:32]."
line.long 0x8C "MAC_Address17_Low,The MAC_Address17_Low register holds the lower 32 bits of the 17th 6-byte MAC address of the station."
hexmask.long 0x8C 0.--31. 1. "ADDRLO,MAC Address17 [31:0]."
line.long 0x90 "MAC_Address18_High,The MAC_Address18_High register holds the upper 16 bits of the 18th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address18_Low register."
bitfld.long 0x90 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 18th MAC.."
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bitfld.long 0x90 30. "SA,Source Address." "0: The MAC Address18[47:0] is used to compare with..,1: The MAC Address18[47:0] is used to compare with.."
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hexmask.long.byte 0x90 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x90 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x90 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x90 0.--15. 1. "ADDRHI,MAC Address18 [47:32]."
line.long 0x94 "MAC_Address18_Low,The MAC_Address18_Low register holds the lower 32 bits of the 18th 6-byte MAC address of the station."
hexmask.long 0x94 0.--31. 1. "ADDRLO,MAC Address18 [31:0]."
line.long 0x98 "MAC_Address19_High,The MAC_Address19_High register holds the upper 16 bits of the 19th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address19_Low register."
bitfld.long 0x98 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 19th MAC.."
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bitfld.long 0x98 30. "SA,Source Address." "0: The MAC Address19[47:0] is used to compare with..,1: The MAC Address19[47:0] is used to compare with.."
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hexmask.long.byte 0x98 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0x98 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0x98 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x98 0.--15. 1. "ADDRHI,MAC Address19 [47:32]."
line.long 0x9C "MAC_Address19_Low,The MAC_Address19_Low register holds the lower 32 bits of the 19th 6-byte MAC address of the station."
hexmask.long 0x9C 0.--31. 1. "ADDRLO,MAC Address19 [31:0]."
line.long 0xA0 "MAC_Address20_High,The MAC_Address20_High register holds the upper 16 bits of the 20th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address20_Low register."
bitfld.long 0xA0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 20th MAC.."
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bitfld.long 0xA0 30. "SA,Source Address." "0: The MAC Address20[47:0] is used to compare with..,1: The MAC Address20[47:0] is used to compare with.."
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hexmask.long.byte 0xA0 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xA0 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xA0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xA0 0.--15. 1. "ADDRHI,MAC Address20 [47:32]."
line.long 0xA4 "MAC_Address20_Low,The MAC_Address20_Low register holds the lower 32 bits of the 20th 6-byte MAC address of the station."
hexmask.long 0xA4 0.--31. 1. "ADDRLO,MAC Address20 [31:0]."
line.long 0xA8 "MAC_Address21_High,The MAC_Address21_High register holds the upper 16 bits of the 21th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address21_Low register."
bitfld.long 0xA8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 21th MAC.."
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bitfld.long 0xA8 30. "SA,Source Address." "0: The MAC Address21[47:0] is used to compare with..,1: The MAC Address21[47:0] is used to compare with.."
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hexmask.long.byte 0xA8 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xA8 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xA8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xA8 0.--15. 1. "ADDRHI,MAC Address21 [47:32]."
line.long 0xAC "MAC_Address21_Low,The MAC_Address21_Low register holds the lower 32 bits of the 21th 6-byte MAC address of the station."
hexmask.long 0xAC 0.--31. 1. "ADDRLO,MAC Address21 [31:0]."
line.long 0xB0 "MAC_Address22_High,The MAC_Address22_High register holds the upper 16 bits of the 22th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address22_Low register."
bitfld.long 0xB0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 22th MAC.."
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bitfld.long 0xB0 30. "SA,Source Address." "0: The MAC Address22[47:0] is used to compare with..,1: The MAC Address22[47:0] is used to compare with.."
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hexmask.long.byte 0xB0 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xB0 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xB0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xB0 0.--15. 1. "ADDRHI,MAC Address22 [47:32]."
line.long 0xB4 "MAC_Address22_Low,The MAC_Address22_Low register holds the lower 32 bits of the 22th 6-byte MAC address of the station."
hexmask.long 0xB4 0.--31. 1. "ADDRLO,MAC Address22 [31:0]."
line.long 0xB8 "MAC_Address23_High,The MAC_Address23_High register holds the upper 16 bits of the 23th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address23_Low register."
bitfld.long 0xB8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 23th MAC.."
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bitfld.long 0xB8 30. "SA,Source Address." "0: The MAC Address23[47:0] is used to compare with..,1: The MAC Address23[47:0] is used to compare with.."
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hexmask.long.byte 0xB8 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xB8 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xB8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xB8 0.--15. 1. "ADDRHI,MAC Address23 [47:32]."
line.long 0xBC "MAC_Address23_Low,The MAC_Address23_Low register holds the lower 32 bits of the 23th 6-byte MAC address of the station."
hexmask.long 0xBC 0.--31. 1. "ADDRLO,MAC Address23 [31:0]."
line.long 0xC0 "MAC_Address24_High,The MAC_Address24_High register holds the upper 16 bits of the 24th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address24_Low register."
bitfld.long 0xC0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 24th MAC.."
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bitfld.long 0xC0 30. "SA,Source Address." "0: The MAC Address24[47:0] is used to compare with..,1: The MAC Address24[47:0] is used to compare with.."
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hexmask.long.byte 0xC0 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xC0 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xC0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xC0 0.--15. 1. "ADDRHI,MAC Address24 [47:32]."
line.long 0xC4 "MAC_Address24_Low,The MAC_Address24_Low register holds the lower 32 bits of the 24th 6-byte MAC address of the station."
hexmask.long 0xC4 0.--31. 1. "ADDRLO,MAC Address24 [31:0]."
line.long 0xC8 "MAC_Address25_High,The MAC_Address25_High register holds the upper 16 bits of the 25th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address25_Low register."
bitfld.long 0xC8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 25th MAC.."
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bitfld.long 0xC8 30. "SA,Source Address." "0: The MAC Address25[47:0] is used to compare with..,1: The MAC Address25[47:0] is used to compare with.."
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hexmask.long.byte 0xC8 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xC8 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xC8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xC8 0.--15. 1. "ADDRHI,MAC Address25 [47:32]."
line.long 0xCC "MAC_Address25_Low,The MAC_Address25_Low register holds the lower 32 bits of the 25th 6-byte MAC address of the station."
hexmask.long 0xCC 0.--31. 1. "ADDRLO,MAC Address25 [31:0]."
line.long 0xD0 "MAC_Address26_High,The MAC_Address26_High register holds the upper 16 bits of the 26th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address26_Low register."
bitfld.long 0xD0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 26th MAC.."
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bitfld.long 0xD0 30. "SA,Source Address." "0: The MAC Address26[47:0] is used to compare with..,1: The MAC Address26[47:0] is used to compare with.."
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hexmask.long.byte 0xD0 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xD0 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xD0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xD0 0.--15. 1. "ADDRHI,MAC Address26 [47:32]."
line.long 0xD4 "MAC_Address26_Low,The MAC_Address26_Low register holds the lower 32 bits of the 26th 6-byte MAC address of the station."
hexmask.long 0xD4 0.--31. 1. "ADDRLO,MAC Address26 [31:0]."
line.long 0xD8 "MAC_Address27_High,The MAC_Address27_High register holds the upper 16 bits of the 27th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address27_Low register."
bitfld.long 0xD8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 27th MAC.."
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bitfld.long 0xD8 30. "SA,Source Address." "0: The MAC Address27[47:0] is used to compare with..,1: The MAC Address27[47:0] is used to compare with.."
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hexmask.long.byte 0xD8 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xD8 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xD8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xD8 0.--15. 1. "ADDRHI,MAC Address27 [47:32]."
line.long 0xDC "MAC_Address27_Low,The MAC_Address27_Low register holds the lower 32 bits of the 27th 6-byte MAC address of the station."
hexmask.long 0xDC 0.--31. 1. "ADDRLO,MAC Address27 [31:0]."
line.long 0xE0 "MAC_Address28_High,The MAC_Address28_High register holds the upper 16 bits of the 28th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address28_Low register."
bitfld.long 0xE0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 28th MAC.."
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bitfld.long 0xE0 30. "SA,Source Address." "0: The MAC Address28[47:0] is used to compare with..,1: The MAC Address28[47:0] is used to compare with.."
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hexmask.long.byte 0xE0 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xE0 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xE0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xE0 0.--15. 1. "ADDRHI,MAC Address28 [47:32]."
line.long 0xE4 "MAC_Address28_Low,The MAC_Address28_Low register holds the lower 32 bits of the 28th 6-byte MAC address of the station."
hexmask.long 0xE4 0.--31. 1. "ADDRLO,MAC Address28 [31:0]."
line.long 0xE8 "MAC_Address29_High,The MAC_Address29_High register holds the upper 16 bits of the 29th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address29_Low register."
bitfld.long 0xE8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 29th MAC.."
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bitfld.long 0xE8 30. "SA,Source Address." "0: The MAC Address29[47:0] is used to compare with..,1: The MAC Address29[47:0] is used to compare with.."
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hexmask.long.byte 0xE8 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xE8 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xE8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xE8 0.--15. 1. "ADDRHI,MAC Address29 [47:32]."
line.long 0xEC "MAC_Address29_Low,The MAC_Address29_Low register holds the lower 32 bits of the 29th 6-byte MAC address of the station."
hexmask.long 0xEC 0.--31. 1. "ADDRLO,MAC Address29 [31:0]."
line.long 0xF0 "MAC_Address30_High,The MAC_Address30_High register holds the upper 16 bits of the 30th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address30_Low register."
bitfld.long 0xF0 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 30th MAC.."
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bitfld.long 0xF0 30. "SA,Source Address." "0: The MAC Address30[47:0] is used to compare with..,1: The MAC Address30[47:0] is used to compare with.."
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hexmask.long.byte 0xF0 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xF0 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xF0 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xF0 0.--15. 1. "ADDRHI,MAC Address30 [47:32]."
line.long 0xF4 "MAC_Address30_Low,The MAC_Address30_Low register holds the lower 32 bits of the 30th 6-byte MAC address of the station."
hexmask.long 0xF4 0.--31. 1. "ADDRLO,MAC Address30 [31:0]."
line.long 0xF8 "MAC_Address31_High,The MAC_Address31_High register holds the upper 16 bits of the 31th 6-byte MAC address of the station. The first DA byte that is received on the GMII interface corresponds to the LS byte (Bits [7:0]) of the MAC_Address31_Low register."
bitfld.long 0xF8 31. "AE,Address Enable." "0: The address filter module ignores the address..,1: The address filter module uses the 31th MAC.."
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bitfld.long 0xF8 30. "SA,Source Address." "0: The MAC Address31[47:0] is used to compare with..,1: The MAC Address31[47:0] is used to compare with.."
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hexmask.long.byte 0xF8 24.--29. 1. "MBC,Mask Byte Control."
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hexmask.long.byte 0xF8 19.--23. 1. "Reserved_23_y,Reserved."
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bitfld.long 0xF8 16.--18. "DCS,DMA Channel Select." "0,1,2,3,4,5,6,7"
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hexmask.long.word 0xF8 0.--15. 1. "ADDRHI,MAC Address31 [47:32]."
line.long 0xFC "MAC_Address31_Low,The MAC_Address31_Low register holds the lower 32 bits of the 31th 6-byte MAC address of the station."
hexmask.long 0xFC 0.--31. 1. "ADDRLO,MAC Address31 [31:0]."
group.long 0x700++0x7
line.long 0x0 "MAC_Indir_Access_Ctrl,This register provides the Indirect Access control and status for MAC_<MSEL>_IndReg(#AOFF) registers."
bitfld.long 0x0 31. "SNPS_R,Synopsys Reserved" "0,1"
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rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
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hexmask.long.byte 0x0 26.--29. 1. "MSEL,Mode Select"
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rbitfld.long 0x0 24.--25. "Reserved_25_24,Reserved." "0,1,2,3"
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hexmask.long.byte 0x0 16.--23. 1. "Reserved_23_x,Reserved"
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hexmask.long.byte 0x0 8.--15. 1. "AOFF,Address Offset"
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rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
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bitfld.long 0x0 5. "AUTO,Auto increment" "0,1"
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rbitfld.long 0x0 2.--4. "Reserved_4_2,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 1. "COM,Command type" "0,1"
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bitfld.long 0x0 0. "OB,Operation Busy" "0,1"
line.long 0x4 "MAC_Indir_Access_Data,This register holds the read/write data for Indirect Access of MAC_<MSEL_IndReg(#AOFF) registers."
hexmask.long 0x4 0.--31. 1. "DATA,This field contains data to read/write for Indirect address access associated with MAC_Indir_Access_Ctrl register."
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg0,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg1,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg10,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg11,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg12,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg13,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg14,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg15,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg16,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg17,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg18,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg19,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg2,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg20,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg21,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg22,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg23,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg24,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg25,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg26,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg27,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg28,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg29,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg3,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg30,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg31,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg4,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg5,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg6,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg7,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg8,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x704++0x3
line.long 0x0 "MAC_DChSel_IndReg9,This register contains DCS (XDCS) one hot encoded value of receive channel selection for multicast/broadcast."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "XDCS,DMA Channel Select"
group.long 0x800++0x3
line.long 0x0 "MMC_Control,The MMC Control register establishes the operating mode of the management counters."
hexmask.long.word 0x0 19.--31. 1. "Reserved_31_19,Reserved."
newline
rbitfld.long 0x0 16.--18. "Reserved_PRMMCSEL,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "CNTPRST,Counters Preset" "0,1"
newline
rbitfld.long 0x0 6. "Reserved_6,Reserved." "0,1"
newline
bitfld.long 0x0 4.--5. "MCT,MMC Counter Threshold" "0: Reserved,1: One-quarter the maximum value,2: One-half of the maximum value,3: Three-quarters of the maximum value"
newline
bitfld.long 0x0 3. "MCF,MMC Counter Freeze" "0,1"
newline
bitfld.long 0x0 2. "RSTONRD,Reset on Read" "0,1"
newline
bitfld.long 0x0 1. "CNTSTOPRO,Counter Stop Rollover" "0,1"
newline
bitfld.long 0x0 0. "CNTRST,Counters Reset" "0,1"
rgroup.long 0x804++0x7
line.long 0x0 "MMC_Rx_Interrupt,The MMC Receive Interrupt Status register maintains the interrupts generated when receive statistic counters reach the threshold programmed in the MMC control register. When the MMC counter that caused the interrupt is read. the.."
bitfld.long 0x0 31. "RXPRMMCIS,Rx Priority MMC Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
bitfld.long 0x0 29. "SGFPIS,SGF Fail Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 28. "SGPPIS,SGF Pass Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 27. "RXALEPIS,Rx Alignment Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 26. "RXLPITRCIS,Rx LPI Transition Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 25. "RXLPIUSCIS,Rx LPI microsecond Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 24. "RXDISOCGBIS,Rx Good Bad Discarded Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 23. "RXDISPCGBIS,Rx Good Bad Discarded Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 22. "RXWDOGPIS,Rx Watchdog Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 21. "RXVLANGBPIS,Rx Good Bad VLAN Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 20. "RXFOVPIS,Rx Queue Overflow Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 19. "RXPAUSPIS,Rx Pause Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "RXORANGEPIS,Rx Out-of-Range Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "RXLENERPIS,Rx Length Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "RXUCGPIS,Rx Good Unicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 15. "RX1024TMAXOCTGBPIS,Rx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 14. "RX512T1023OCTGBPIS,Rx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 13. "RX256T511OCTGBPIS,Rx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 12. "RX128T255OCTGBPIS,Rx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 11. "RX65T127OCTGBPIS,Rx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "RX64OCTGBPIS,Rx Good Bad 64 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "RXOSIZEGPIS,Rx Good Oversize Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "RXUSIZEGPIS,Rx Good Undersize Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 7. "RXJABERPIS,Rx Jabber Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "RXRUNTPIS,Rx Runt Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "RXCRCERPIS,Rx CRC Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "RXMCGPIS,Rx Good Multicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "RXBCGPIS,Rx Good Broadcast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "RXGOCTIS,Rx Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "RXGBOCTIS,Rx Good Bad Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "RXGBPKTIS,Rx Good Bad Packet Counter Interrupt Status" "0,1"
line.long 0x4 "MMC_Tx_Interrupt,The MMC Transmit Interrupt Status register maintains the interrupts generated when the transmit statistic counters reach the threshold value programmed in MMC control register (for example. the counter's MSB is set). This register is 32.."
bitfld.long 0x4 31. "TXPRMMCIS,Tx Priority MMC Counter Interrupt Status" "0,1"
newline
hexmask.long.byte 0x4 27.--30. 1. "Reserved_30_27,Reserved."
newline
bitfld.long 0x4 26. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 25. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 24. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 23. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 22. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 21. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 20. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 19. "TXLPITRCIS,Tx LPI Transition Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 18. "TXLPIUSCIS,Tx LPI microsecond Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 17. "TXVLANGPIS,Tx Good VLAN Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 16. "TXPAUSPIS,Tx Pause Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 15. "TXGPKTIS,Tx Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 14. "TXGOCTIS,Tx Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 13. "TXUFLOWERPIS,Tx Underflow Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 12. "TXBCGBPIS,Tx Good Bad Broadcast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 11. "TXMCGBPIS,Tx Good Bad Multicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 10. "TXUCGBPIS,Tx Good Bad Unicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 9. "TX1024TMAXOCTGBPIS,Tx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 8. "TX512T1023OCTGBPIS,Tx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 7. "TX256T511OCTGBPIS,Tx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 6. "TX128T255OCTGBPIS,Tx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 5. "TX65T127OCTGBPIS,Tx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 4. "TX64OCTGBPIS,Tx Good Bad 64 Octet Size Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 3. "TXMCGPIS,Tx Good Multicast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 2. "TXBCGPIS,Tx Good Broadcast Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 1. "TXGBPKTIS,Tx Good Bad Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x4 0. "TXGBOCTIS,Tx Good Bad Octet Counter Interrupt Status" "0,1"
group.long 0x80C++0x7
line.long 0x0 "MMC_Receive_Interrupt_Enable,The MMC Receive Interrupt Enable register maintains the enables for the interrupts generated when receive statistic counters reach the threshold value programmed in the MMC Control register. This register is 32 bits wide."
rbitfld.long 0x0 31. "Reserved_RXPRMMCIE,Reserved." "0,1"
newline
rbitfld.long 0x0 30. "Reserved_30,Reserved." "0,1"
newline
rbitfld.long 0x0 29. "Reserved_SGFPIE,Reserved." "0,1"
newline
rbitfld.long 0x0 28. "Reserved_SGPPIE,Reserved." "0,1"
newline
bitfld.long 0x0 27. "RXALEPIE,Rx Alignment Error Packet Counter Interrupt Enable" "0,1"
newline
rbitfld.long 0x0 26. "Reserved_RXLPITRCIE,Reserved." "0,1"
newline
rbitfld.long 0x0 25. "Reserved_RXLPIUSCIE,Reserved." "0,1"
newline
bitfld.long 0x0 24. "RXDISOCGBIE,Rx Discard Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 23. "RXDISPCGBIE,Rx Discard Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 22. "RXWDOGPIE,Rx Watchdog Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 21. "RXVLANGBPIE,Rx Good Bad VLAN Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 20. "RXFOVPIE,Rx Queue Overflow Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 19. "RXPAUSPIE,Rx Pause Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 18. "RXORANGEPIE,Rx Out-of-Range Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 17. "RXLENERPIE,Rx Length Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 16. "RXUCGPIE,Rx Good Unicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 15. "RX1024TMAXOCTGBPIE,Rx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 14. "RX512T1023OCTGBPIE,Rx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 13. "RX256T511OCTGBPIE,Rx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 12. "RX128T255OCTGBPIE,Rx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 11. "RX65T127OCTGBPIE,Rx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 10. "RX64OCTGBPIE,Rx Good Bad 64 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 9. "RXOSIZEGPIE,Rx Good Oversize Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 8. "RXUSIZEGPIE,Rx Good Undersize Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 7. "RXJABERPIE,Rx Jabber Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 6. "RXRUNTPIE,Rx Runt Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 5. "RXCRCERPIE,Rx CRC Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 4. "RXMCGPIE,Rx Good Multicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 3. "RXBCGPIE,Rx Good Broadcast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 2. "RXGOCTIE,Rx Good Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 1. "RXGBOCTIE,Rx Good Bad Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x0 0. "RXGBPKTIE,Rx Good Bad Packet Counter Interrupt Enable" "0,1"
line.long 0x4 "MMC_Transmit_Interrupt_Enable,The MMC Transmit Interrupt Enable register maintains the enables for the interrupts generated when transmit statistic counters reach the threshold value programmed in the MMC Control register. This register is 32 bits wide."
rbitfld.long 0x4 31. "Reserved_TXPRMMCIE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 27.--30. 1. "Reserved_30_27,Reserved."
newline
bitfld.long 0x4 26. "TXEXDEFPIE,MMC Transmit Excessive Deferral Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 25. "TXCARERPIE,MMC Transmit Carrier Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 24. "TXEXCOLPIE,MMC Transmit Excessive Collision Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 23. "TXLATCOLPIE,MMC Transmit Late Collision Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 22. "TXDEFPIE,MMC Transmit Deferred Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 21. "TXMCOLGPIE,MMC Transmit Multiple Collision Good Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 20. "TXSCOLGPIE,MMC Transmit Single Collision Good Packet Counter Interrupt Enable" "0,1"
newline
rbitfld.long 0x4 19. "Reserved_TXLPITRCIE,Reserved." "0,1"
newline
rbitfld.long 0x4 18. "Reserved_TXLPIUSCIE,Reserved." "0,1"
newline
bitfld.long 0x4 17. "TXVLANGPIE,Tx Good VLAN Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 16. "TXPAUSPIE,Tx Pause Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 15. "TXGPKTIE,Tx Good Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 14. "TXGOCTIE,Tx Good Octet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 13. "TXUFLOWERPIE,Tx Underflow Error Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 12. "TXBCGBPIE,Tx Good Bad Broadcast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 11. "TXMCGBPIE,Tx Good Bad Multicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 10. "TXUCGBPIE,Tx Good Bad Unicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 9. "TX1024TMAXOCTGBPIE,Tx Good Bad 1024-to-Max Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 8. "TX512T1023OCTGBPIE,Tx Good Bad 512-to-1023 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 7. "TX256T511OCTGBPIE,Tx Good Bad 256-to-511 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 6. "TX128T255OCTGBPIE,Tx Good Bad 128-to-255 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 5. "TX65T127OCTGBPIE,Tx Good Bad 65-to-127 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 4. "TX64OCTGBPIE,Tx Good Bad 64 Octet Size Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 3. "TXMCGPIE,Tx Good Multicast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 2. "TXBCGPIE,Tx Good Broadcast Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 1. "TXGBPKTIE,Tx Good Bad Packet Counter Interrupt Enable" "0,1"
newline
bitfld.long 0x4 0. "TXGBOCTIE,Tx Good Bad Octet Counter Interrupt Enable" "0,1"
rgroup.long 0x814++0xB
line.long 0x0 "Tx_Octet_Count_Good_Bad_Low,This register provides lower 32 bits of transmitted octet count. excluding preamble. in good and bad packets."
hexmask.long 0x0 0.--31. 1. "TXOCTGBLO,Tx Good Bad Octet Count Low"
line.long 0x4 "Tx_Octet_Count_Good_Bad_High,This register provides upper 32 bits of transmitted octet count. excluding preamble. in good and bad packets."
hexmask.long 0x4 0.--31. 1. "TXOCTGBHI,Tx Good Bad Octet Count High"
line.long 0x8 "Tx_Packet_Count_Good_Bad_Low,This register provides lower 32 bits of transmitted good and bad packet count."
hexmask.long 0x8 0.--31. 1. "TXPKTGBLO,Tx Good Bad Packet Count Low"
rgroup.long 0x824++0x3
line.long 0x0 "Tx_Broadcast_Packets_Good_Low,This register provides lower 32 bits of transmitted good broadcast packets count."
hexmask.long 0x0 0.--31. 1. "TXBCASTGLO,Tx Good Broadcast Packet Count Low."
rgroup.long 0x82C++0x3
line.long 0x0 "Tx_Multicast_Packets_Good_Low,This register provides lower 32 bits of transmitted good multicast packets count."
hexmask.long 0x0 0.--31. 1. "TXMCASTGLO,Tx Good Multicast Packet Count Low"
rgroup.long 0x834++0x3
line.long 0x0 "Tx_64Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 64 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX64OCTGBLO,Tx Good Bad 64 Octet Size Packet Count Low"
rgroup.long 0x83C++0x3
line.long 0x0 "Tx_65To127Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 65-to-127 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX65_127OCTGBLO,Tx Good Bad 65-to-127 Octet Size Packet Count Low"
rgroup.long 0x844++0x3
line.long 0x0 "Tx_128To255Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 128-to-255 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX128_255OCTGBLO,Tx Good Bad 128-to-255 Octet Size Packet Count Low"
rgroup.long 0x84C++0x3
line.long 0x0 "Tx_256To511Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 256-to-511 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX256_511OCTGBLO,Tx Good Bad 256-to-511 Octet Size Packet Count Low"
rgroup.long 0x854++0x3
line.long 0x0 "Tx_512To1023Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 512-to-1023 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX512_1023OCTGBLO,Tx Good Bad 512-to-1023 Octet Size Packet Count Low"
rgroup.long 0x85C++0x3
line.long 0x0 "Tx_1024ToMaxOctets_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted 1024-tomaxsize octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "TX1024_MAXOCTGBLO,Tx Good Bad 1024-tomaxsize Octet Size Packet Count Low"
rgroup.long 0x864++0x3
line.long 0x0 "Tx_Unicast_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted good bad unicast packets count."
hexmask.long 0x0 0.--31. 1. "TXUCASTGBLO,Tx Good Bad Unicast Packet Count Low"
rgroup.long 0x86C++0x3
line.long 0x0 "Tx_Multicast_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted good bad multicast packets count."
hexmask.long 0x0 0.--31. 1. "TXMCASTGBLO,Tx Good Bad Multicast Packet Count Low"
rgroup.long 0x874++0x3
line.long 0x0 "Tx_Broadcast_Packets_Good_Bad_Low,This register provides lower 32 bits of transmitted good bad broadcast packets count."
hexmask.long 0x0 0.--31. 1. "TXBCASTGBLO,Tx Good Bad Broadcast Packet Count Low"
rgroup.long 0x87C++0x3
line.long 0x0 "Tx_Underflow_Error_Packets_Low,This register provides lower 32 bits of transmitted packets aborted due to packet underflow error count."
hexmask.long 0x0 0.--31. 1. "TXUNDRFLWLO,Tx Underflow Error Packet Count Low"
rgroup.long 0x884++0xB
line.long 0x0 "Tx_Octet_Count_Good_Low,This register provides lower 32 bits of transmitted good octets count."
hexmask.long 0x0 0.--31. 1. "TXOCTGLO,Tx Good Octet Count Low"
line.long 0x4 "Tx_Octet_Count_Good_High,This register provides upper 32 bits of transmitted good octets count."
hexmask.long 0x4 0.--31. 1. "TXOCTGHI,Tx Good Octet Count High"
line.long 0x8 "Tx_Packet_Count_Good_Low,This register provides lower 32 bits of transmitted good packets count."
hexmask.long 0x8 0.--31. 1. "TXPKTGLO,Tx Good Packet Count Low"
rgroup.long 0x894++0x3
line.long 0x0 "Tx_Pause_Packets_Low,This register provides lower 32 bits of transmitted Pause packets count."
hexmask.long 0x0 0.--31. 1. "TXPAUSEGLO,Tx Pause Packet Count Low"
rgroup.long 0x89C++0x3
line.long 0x0 "Tx_VLAN_Packets_Good_Low,This register provides lower 32 bits of transmitted good VLAN packets count."
hexmask.long 0x0 0.--31. 1. "TXVLANGLO,Tx Good VLAN Packet Count Low"
rgroup.long 0x900++0x3
line.long 0x0 "Rx_Packet_Count_Good_Bad_Low,This register provides lower 32 bits of received good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RXPKTGBLO,Rx Good Bad Packet Count Low"
rgroup.long 0x908++0x13
line.long 0x0 "Rx_Octet_Count_Good_Bad_Low,This register provides lower 32 bits of received octet count. excluding preamble. in good and bad packets."
hexmask.long 0x0 0.--31. 1. "RXOCTGBLO,Rx Good Bad Octet Count Low"
line.long 0x4 "Rx_Octet_Count_Good_Bad_High,This register provides upper 32 bits of received octet count. excluding preamble. in good and bad packets."
hexmask.long 0x4 0.--31. 1. "RXOCTGBHI,Rx Good Bad Octet Count High"
line.long 0x8 "Rx_Octet_Count_Good_Low,This register provides lower 32 bits of received good octets count."
hexmask.long 0x8 0.--31. 1. "RXOCTGLO,Rx Good Octet Count Low"
line.long 0xC "Rx_Octet_Count_Good_High,This register provides upper 32 bits of received good octets count."
hexmask.long 0xC 0.--31. 1. "RXOCTGHI,Rx Good Octet Count High"
line.long 0x10 "Rx_Broadcast_Packets_Good_Low,This register provides lower 32 bits of received good broadcast packets count."
hexmask.long 0x10 0.--31. 1. "RXBCASTGLO,Rx Good Broadcast Packet Count Low"
rgroup.long 0x920++0x3
line.long 0x0 "Rx_Multicast_Packets_Good_Low,This register provides lower 32 bits of received good multicast packets count."
hexmask.long 0x0 0.--31. 1. "RXMCASTGLO,Rx Good Multicast Packet Count Low"
rgroup.long 0x928++0x3
line.long 0x0 "Rx_CRC_Error_Packets_Low,This register provides lower 32 bits of received packets with CRC error count."
hexmask.long 0x0 0.--31. 1. "RXCRCERLO,Rx CRC Error Packet Count Low"
rgroup.long 0x930++0x13
line.long 0x0 "Rx_Runt_Error_Packets,This register provides received packets with Runt error count."
hexmask.long 0x0 0.--31. 1. "RXRUNTER,Rx Runt Error Packet Count"
line.long 0x4 "Rx_Jabber_Error_Packets,This register provides received packets with Jabber error count."
hexmask.long 0x4 0.--31. 1. "RXJABERER,Rx Jabber Error Packet Count"
line.long 0x8 "Rx_Undersize_Packets_Good,This register provides count of received good undersize packets."
hexmask.long 0x8 0.--31. 1. "RXUSIZEG,Rx Good Undersize Packet Count"
line.long 0xC "Rx_Oversize_Packets_Good,This register provides count of received good oversize packets."
hexmask.long 0xC 0.--31. 1. "RXOSIZEG,Rx Good Oversize Packet Count"
line.long 0x10 "Rx_64Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 64 octet size good and bad packets count."
hexmask.long 0x10 0.--31. 1. "RX64OCTGBLO,Rx Good Bad 64 Octet Size Packet Count Low"
rgroup.long 0x948++0x3
line.long 0x0 "Rx_65To127Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 65-to-127 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX65_127OCTGBLO,Rx Good Bad 65-to-127 Octet Size Packet Count Low"
rgroup.long 0x950++0x3
line.long 0x0 "Rx_128To255Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 128-to-255 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX128_255OCTGBLO,Rx Good Bad 128-to-255 Octet Size Packet Count Low"
rgroup.long 0x958++0x3
line.long 0x0 "Rx_256To511Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 256-to-511 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX256_511OCTGBLO,Rx Good Bad 256-to-511 Octet Size Packet Count Low"
rgroup.long 0x960++0x3
line.long 0x0 "Rx_512To1023Octets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 512-to-1023 octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX512_1023OCTGBLO,Rx Good Bad 512-to-1023 Octet Size Packet Count Low"
rgroup.long 0x968++0x3
line.long 0x0 "Rx_1024ToMaxOctets_Packets_Good_Bad_Low,This register provides lower 32 bits of received 1024-tomaxsize octet size good and bad packets count."
hexmask.long 0x0 0.--31. 1. "RX1024_MAXOCTGBLO,Rx Good Bad 1024-tomaxsize Octet Size Packet Count Low"
rgroup.long 0x970++0x3
line.long 0x0 "Rx_Unicast_Packets_Good_Low,This register provides lower 32 bits of received good unicast packets count."
hexmask.long 0x0 0.--31. 1. "RXUCASTGLO,Rx Good Unicast Packet Count Low"
rgroup.long 0x978++0x3
line.long 0x0 "Rx_Length_Error_Packets_Low,This register provides lower 32 bits of received packets with Length error count."
hexmask.long 0x0 0.--31. 1. "RXLENERRLO,Rx Length Error Packet Count Low"
rgroup.long 0x980++0x3
line.long 0x0 "Rx_OutofRange_Packets_Low,This register provides lower 32 bits of received packets with out of range length field count."
hexmask.long 0x0 0.--31. 1. "RXORANGELO,Rx Out of Range Packet Count Low"
rgroup.long 0x988++0x3
line.long 0x0 "Rx_Pause_Packets_Low,This register provides lower 32 bits of received Pause packets count."
hexmask.long 0x0 0.--31. 1. "RXPAUSELO,Rx Pause Packet Count Low"
rgroup.long 0x990++0x3
line.long 0x0 "Rx_FIFOOverflow_Packets_Low,This register provides lower 32 bits of received packets count that had Rx Queue overflow."
hexmask.long 0x0 0.--31. 1. "RXFOVFLO,Rx FIFO Overflow Packet Count Low"
rgroup.long 0x998++0x3
line.long 0x0 "Rx_VLAN_Packets_Good_Bad_Low,This register provides lower 32 bits of received good bad VLAN packets count."
hexmask.long 0x0 0.--31. 1. "RXVLANGBLO,Rx Good Bad VLAN Packet Count Low"
rgroup.long 0x9A0++0x3
line.long 0x0 "Rx_Watchdog_Error_Packets,This register has a count of packets that are received with watchdog error."
hexmask.long 0x0 0.--31. 1. "RXWDOGERR,Rx Watchdog Error Packet Count"
rgroup.long 0x9AC++0x3
line.long 0x0 "Rx_Discard_Packets_Good_Bad_Low,This register provides lower 32 bits of received good bad packets count that were discarded due to filter fail."
hexmask.long 0x0 0.--31. 1. "RXDPCNTGBLO,Rx Good Bad Discard Packet Count Low"
rgroup.long 0x9B4++0xB
line.long 0x0 "Rx_Discard_Octets_Good_Bad_Low,This register provides lower 32 bits of received good bad octets count that were discarded due to filter fail."
hexmask.long 0x0 0.--31. 1. "RXDOCNTGBLO,Rx Good Bad Discard Octet Count Low"
line.long 0x4 "Rx_Discard_Octets_Good_Bad_High,This register provides upper 32 bits of received good bad octets count that were discarded due to filter fail."
hexmask.long 0x4 0.--31. 1. "RXDOCNTGBHI,Rx Good Bad Discard Octet Count High"
line.long 0x8 "Rx_Alignment_Error_Packets,This register provides the number of packets received by DWC_xgmac with alignment (dribble) error. It is valid only in 10/100 mode."
hexmask.long 0x8 0.--31. 1. "RXALIGNERR,Rx Alignment Error Packet Count"
rgroup.long 0xA00++0x3
line.long 0x0 "MMC_FPE_Tx_Interrupt,This register maintains the interrupts generated from all FPE related Transmit statistics counters. The MMC FPE Transmit Interrupt register maintains the interrupts generated when the transmit statistic counters reach the threshold.."
hexmask.long 0x0 3.--31. 1. "Reserved_31_3,Reserved."
newline
bitfld.long 0x0 2. "GOCIS,MMC Tx Gate/Window Overrun Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status" "0,1"
group.long 0xA04++0x3
line.long 0x0 "MMC_FPE_Tx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Transmit statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.."
hexmask.long 0x0 3.--31. 1. "Reserved_31_3,Reserved."
newline
bitfld.long 0x0 2. "GOCIM,MMC Transmit Gate/Window Overrun Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask" "0,1"
rgroup.long 0xA08++0xF
line.long 0x0 "MMC_Tx_FPE_Fragment_Cntr,This register provides the number of additional mPackets transmitted due to preemption."
hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter"
line.long 0x4 "MMC_Tx_Hold_Req_Cntr,This register provides the count of number of times a hold request is given to MAC"
hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter"
line.long 0x8 "MMC_Tx_Gate_Orun_Cntr_Low,This register provides the lower 32-bits of counter that counts the number of times packets overrun the transmission gate/window."
hexmask.long 0x8 0.--31. 1. "TXGOCL,Tx Gate/Window Overrun Counter Low"
line.long 0xC "MMC_Tx_Gate_Orun_Cntr_High,This register provides the upper 32-bits of counter that counts the number of times packets overrun the transmission gate/window."
hexmask.long 0xC 0.--31. 1. "TXGOCH,Tx Gate/Window Overrun Counter High"
rgroup.long 0xA20++0x3
line.long 0x0 "MMC_FPE_Rx_Interrupt,This register maintains the interrupts generated from all FPE related Receive statistics counters. The MMC FPE Receive Interrupt register maintains the interrupts generated when receive statistic counters reach the threshold value.."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status" "0,1"
group.long 0xA24++0x3
line.long 0x0 "MMC_FPE_Rx_Interrupt_Mask,This register maintains the masks for interrupts generated from all FPE related Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask" "0,1"
rgroup.long 0xA28++0xF
line.long 0x0 "MMC_Rx_Packet_Assembly_Err_Cntr,This register provides the number of MAC frames with reassembly errors on the Receiver. due to mismatch in the Fragment Count value."
hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter"
line.long 0x4 "MMC_Rx_Packet_SMD_Err_Cntr,This register provides the number of received MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame."
hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter"
line.long 0x8 "MMC_Rx_Packet_Assembly_OK_Cntr,This register provides the number of MAC frames that were successfully reassembled and delivered to MAC."
hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter"
line.long 0xC "MMC_Rx_FPE_Fragment_Cntr,This register provides the number of additional mPackets received due to preemption."
hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter"
rgroup.long 0xA40++0x1B
line.long 0x0 "Tx_Single_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_xgmac after a single collision in the half-duplex mode."
hexmask.long 0x0 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets"
line.long 0x4 "Tx_Multiple_Collision_Good_Packets,This register provides the number of successfully transmitted packets by DWC_xgmac after multiple collisions in the half-duplex mode."
hexmask.long 0x4 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets"
line.long 0x8 "Tx_Deferred_Packets,This register provides the number of successfully transmitted by DWC_xgmac after a deferral in the half-duplex mode."
hexmask.long 0x8 0.--31. 1. "TXDEFRD,Tx Deferred Packets"
line.long 0xC "Tx_Late_Collision_Packets,This register provides the number of packets aborted by DWC_xgmac because of late collision error."
hexmask.long 0xC 0.--31. 1. "TXLATECOL,Tx Late Collision Packets"
line.long 0x10 "Tx_Excessive_Collision_Packets,This register provides the number of packets aborted by DWC_xgmac because of excessive (16) collision errors."
hexmask.long 0x10 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets"
line.long 0x14 "Tx_Carrier_Error_Packets,This register provides the number of packets aborted by DWC_xgmac because of carrier sense error (no carrier or loss of carrier)."
hexmask.long 0x14 0.--31. 1. "TXCARR,Tx Carrier Error Packets"
line.long 0x18 "Tx_Excessive_Deferral_Error,This register provides the number of packets aborted by DWC_xgmac because of excessive deferral error (deferred for more than two max-size packet times)."
hexmask.long 0x18 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error"
group.long 0xA5C++0x3
line.long 0x0 "MMC_IPC_Rx_Interrupt_Mask,This register maintains the mask for the interrupt generated from the receive IPC statistic counters."
rbitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 29. "RXICMPEROIM,MMC Receive ICMP Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 28. "RXICMPGOIM,MMC Receive ICMP Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 27. "RXTCPEROIM,MMC Receive TCP Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 26. "RXTCPGOIM,MMC Receive TCP Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 25. "RXUDPEROIM,MMC Receive UDP Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 24. "RXUDPGOIM,MMC Receive IPv6 No Payload Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 23. "RXIPV6NOPAYOIM,MMC Receive IPv6 Header Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 22. "RXIPV6HEROIM,MMC Receive IPv6 Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 21. "RXIPV6GOIM,MMC Receive IPv6 Good Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 20. "RXIPV4UDSBLOIM,MMC Receive IPv4 UDP Checksum Disabled Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 19. "RXIPV4FRAGOIM,MMC Receive IPv4 Fragmented Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 18. "RXIPV4NOPAYOIM,MMC Receive IPv4 No Payload Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 17. "RXIPV4HEROIM,MMC Receive IPv4 Header Error Octet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 16. "RXIPV4GOIM,MMC Receive IPv4 Good Octet Counter Interrupt Mask" "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 13. "RXICMPERPIM,MMC Receive ICMP Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 12. "RXICMPGPIM,MMC Receive ICMP Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 11. "RXTCPERPIM,MMC Receive TCP Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 10. "RXTCPGPIM,MMC Receive TCP Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 9. "RXUDPERPIM,MMC Receive UDP Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 8. "RXUDPGPIM,MMC Receive UDP Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 7. "RXIPV6NOPAYPIM,MMC Receive IPv6 No Payload Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 6. "RXIPV6HERPIM,MMC Receive IPv6 Header Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 5. "RXIPV6GPIM,MMC Receive IPv6 Good Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 4. "RXIPV4UDSBLPIM,MMC Receive IPv4 UDP Checksum Disabled Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXIPV4FRAGPIM,MMC Receive IPv4 Fragmented Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXIPV4NOPAYPIM,MMC Receive IPv4 No Payload Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "RXIPV4HERPIM,MMC Receive IPv4 Header Error Packet Counter Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "RXIPV4GPIM,MMC Receive IPv4 Good Packet Counter Interrupt Mask" "0,1"
rgroup.long 0xA60++0x7
line.long 0x0 "MMC_IPC_Rx_Interrupt,This register maintains the interrupt that the receive IPC statistic counters generate."
bitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 29. "RXICMPEROIS,MMC Receive ICMP Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 28. "RXICMPGOIS,MMC Receive ICMP Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 27. "RXTCPEROIS,MMC Receive TCP Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 26. "RXTCPGOIS,MMC Receive TCP Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 25. "RXUDPEROIS,MMC Receive UDP Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 24. "RXUDPGOIS,MMC Receive UDP Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 23. "RXIPV6NOPAYOIS,MMC Receive IPv6 No Payload Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 22. "RXIPV6HEROIS,MMC Receive IPv6 Header Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 21. "RXIPV6GOIS,MMC Receive IPv6 Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 20. "RXIPV4UDSBLOIS,MMC Receive IPv4 UDP Checksum Disabled Octet Counter Interrupt" "0,1"
newline
bitfld.long 0x0 19. "RXIPV4FRAGOIS,MMC Receive IPv4 Fragmented Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "RXIPV4NOPAYOIS,MMC Receive IPv4 No Payload Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "RXIPV4HEROIS,MMC Receive IPv4 Header Error Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 16. "RXIPV4GOIS,MMC Receive IPv4 Good Octet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 13. "RXICMPERPIS,MMC Receive ICMP Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 12. "RXICMPGPIS,MMC Receive ICMP Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 11. "RXTCPERPIS,MMC Receive TCP Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 10. "RXTCPGPIS,MMC Receive TCP Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 9. "RXUDPERPIS,MMC Receive UDP Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 8. "RXUDPGPIS,MC Receive UDP Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 7. "RXIPV6NOPAYPIS,MMC Receive IPv6 No Payload Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 6. "RXIPV6HERPIS,MMC Receive IPv6 Header Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 5. "RXIPV6GPIS,MMC Receive IPV6 Good Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 4. "RXIPV4UDSBLPIS,MMC Receive IPv4 UDP Checksum Disabled Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 3. "RXIPV4FRAGPIS,MMC Receive IPv4 Fragmented Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 2. "RXIPV4NOPAYPIS,MMC Receive IPv4 No Payload Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 1. "RXIPV4HERPIS,MMC Receive IPv4 Header Error Packet Counter Interrupt Status" "0,1"
newline
bitfld.long 0x0 0. "RXIPV4GPIS,MMC Receive IPv4 Good Packet Counter Interrupt Status" "0,1"
line.long 0x4 "RxIPv4_Good_Packets_Low,This register provides lower 32 bits of good IPv4 datagrams received by DWC_xgmac with the TCP. UDP. or ICMP payload."
hexmask.long 0x4 0.--31. 1. "RXIPV4GDPKTLO,RxIPv4 Good Packets"
rgroup.long 0xA6C++0x3
line.long 0x0 "RxIPv4_Header_Error_Packets_Low,RxIPv4 Header Error Packets"
hexmask.long 0x0 0.--31. 1. "RXIPV4HDRERRPKTLO,RxIPv4 Header Error Packets"
rgroup.long 0xA74++0x3
line.long 0x0 "RxIPv4_No_Payload_Packets_Low,This register provides lower 32 bits of IPv4 datagram packets received by DWC_xgmac that did not have a TCP. UDP. or ICMP payload."
hexmask.long 0x0 0.--31. 1. "RXIPV4NOPAYPKTLO,RxIPv4 Payload Packets"
rgroup.long 0xA7C++0x3
line.long 0x0 "RxIPv4_Fragmented_Packets_Low,This register provides lower 32 bits of good IPv4 datagrams received by DWC_xgmac with fragmentation."
hexmask.long 0x0 0.--31. 1. "RXIPV4FRAGPKTLO,RxIPv4 Fragmented Packets"
rgroup.long 0xA84++0x3
line.long 0x0 "RxIPv4_UDP_Checksum_Disabled_Packets_Low,This register provides lower 32 bits of good IPv4 datagrams received by DWC_xgmac that had a UDP payload with checksum disabled."
hexmask.long 0x0 0.--31. 1. "RXIPV4UDSBLPKTLO,RxIPv4 UDP Checksum Disabled Packets"
rgroup.long 0xA8C++0x3
line.long 0x0 "RxIPv6_Good_Packets_Low,This register provides lower 32 bits of good IPv6 datagrams received by DWC_xgmac with the TCP. UDP. or ICMP payload."
hexmask.long 0x0 0.--31. 1. "RXIPV6GDPKTLO,RxIPv6 Good Packets"
rgroup.long 0xA94++0x3
line.long 0x0 "RxIPv6_Header_Error_Packets_Low,This register provides lower 32 bits of IPv6 datagrams received by DWC_xgmac with header (length or version mismatch) errors."
hexmask.long 0x0 0.--31. 1. "RXIPV6HDRERRPKTLO,RxIPv6 Header Error Packets"
rgroup.long 0xA9C++0x3
line.long 0x0 "RxIPv6_No_Payload_Packets_Low,This register provides lower 32 bits of IPv6 datagram packets received by DWC_xgmac that did not have a TCP. UDP. or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers."
hexmask.long 0x0 0.--31. 1. "RXIPV6NOPAYPKTLO,RxIPv6 Payload Packets"
rgroup.long 0xAA4++0x3
line.long 0x0 "RxUDP_Good_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented."
hexmask.long 0x0 0.--31. 1. "RXUDPGDPKTLO,RxUDP Good Packets"
rgroup.long 0xAAC++0x3
line.long 0x0 "RxUDP_Error_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac whose UDP payload has a checksum error."
hexmask.long 0x0 0.--31. 1. "RXUDPERRPKTLO,RxUDP Error Packets"
rgroup.long 0xAB4++0x3
line.long 0x0 "RxTCP_Good_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac with a good TCP payload."
hexmask.long 0x0 0.--31. 1. "RXTCPGDPKTLO,RxTCP Good Packets"
rgroup.long 0xABC++0x3
line.long 0x0 "RxTCP_Error_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac whose TCP payload has a checksum error."
hexmask.long 0x0 0.--31. 1. "RXTCPERRPKTLO,RxTCP Error Packets"
rgroup.long 0xAC4++0x3
line.long 0x0 "RxICMP_Good_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac with a good ICMP payload."
hexmask.long 0x0 0.--31. 1. "RXICMPGDPKTLO,RxICMP Good Packets"
rgroup.long 0xACC++0x3
line.long 0x0 "RxICMP_Error_Packets_Low,This register provides lower 32 bits of good IP datagrams received by DWC_xgmac whose ICMP payload has a checksum error."
hexmask.long 0x0 0.--31. 1. "RXICMPERRPKTLO,RxICMP Error Packets"
rgroup.long 0xAD4++0x3
line.long 0x0 "RxIPv4_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in good IPv4 datagrams encapsulating TCP. UDP. or ICMP data. (Ethernet header. FCS. pad. or IP pad bytes are not included in this counter."
hexmask.long 0x0 0.--31. 1. "RXIPV4GDOCTLO,RxIPv4 Good Octets"
rgroup.long 0xADC++0x3
line.long 0x0 "RxIPv4_Header_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv4 datagrams with header errors (checksum. length. version mismatch). The value in the Length field of IPv4 header is used to update this counter."
hexmask.long 0x0 0.--31. 1. "RXIPV4HDRERROCTLO,RxIPv4 Header Error Octets"
rgroup.long 0xAE4++0x3
line.long 0x0 "RxIPv4_No_Payload_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv4 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. (Ethernet.."
hexmask.long 0x0 0.--31. 1. "RXIPV4NOPAYOCTLO,RxIPv4 Payload Octets"
rgroup.long 0xAEC++0x3
line.long 0x0 "RxIPv4_Fragmented_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header. FCS. pad. or IP pad bytes are.."
hexmask.long 0x0 0.--31. 1. "RXIPV4FRAGOCTLO,RxIPv4 Fragmented Octets"
rgroup.long 0xAF4++0x3
line.long 0x0 "RxIPv4_UDP_Checksum_Disable_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. (Ethernet header. FCS. pad. or IP pad bytes are.."
hexmask.long 0x0 0.--31. 1. "RXIPV4UDSBLOCTLO,RxIPv4 UDP Checksum Disable Octets"
rgroup.long 0xAFC++0x3
line.long 0x0 "RxIPv6_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in good IPv6 datagrams encapsulating TCP. UDP. or ICMP data. (Ethernet header. FCS. pad. or IP pad bytes are not included in this counter."
hexmask.long 0x0 0.--31. 1. "RXIPV6GDOCTLO,RxIPv6 Good Octets"
rgroup.long 0xB04++0x3
line.long 0x0 "RxIPv6_Header_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv6 datagrams with header errors (length. version mismatch). The value in the Length field of IPv6 header is used to update this counter. (Ethernet.."
hexmask.long 0x0 0.--31. 1. "RXIPV6HDRERROCTLO,RxIPv6 Header Error Octets"
rgroup.long 0xB0C++0x3
line.long 0x0 "RxIPv6_No_Payload_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in IPv6 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. (Ethernet.."
hexmask.long 0x0 0.--31. 1. "RXIPV6NOPAYOCTLO,RxIPv6 Payload Octets"
rgroup.long 0xB14++0x3
line.long 0x0 "RxUDP_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a good UDP segment. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXUDPGDOCTLO,RxUDP Good Octets"
rgroup.long 0xB1C++0x3
line.long 0x0 "RxUDP_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a UDP segment that had checksum errors. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXUDPERROCTLO,RxUDP Error Octets"
rgroup.long 0xB24++0x3
line.long 0x0 "RxTCP_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a good TCP segment. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXTCPGDOCTLO,RxTCP Good Octets"
rgroup.long 0xB2C++0x3
line.long 0x0 "RxTCP_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a TCP segment that had checksum errors. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXTCPERROCTLO,RxTCP Error Octets"
rgroup.long 0xB34++0x3
line.long 0x0 "RxICMP_Good_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a good ICMP segment. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXICMPGDOCTLO,RxICMP Good Octets"
rgroup.long 0xB3C++0x3
line.long 0x0 "RxICMP_Error_Octets_Low,This register provides lower 32 bits of bytes received by DWC_xgmac in a ICMP segment that had checksum errors. This counter does not count IP header bytes."
hexmask.long 0x0 0.--31. 1. "RXICMPERROCTLO,RxICMP Error Octets"
group.long 0xC00++0x7
line.long 0x0 "MAC_L3_L4_Address_Control,This register has the indirect address and control for accessing the Layer 3 and Layer 4 Filter registers."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.byte 0x0 8.--15. 1. "IDDR,L3_L4 Filter Address."
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved."
newline
bitfld.long 0x0 1. "TT,Transfer Type." "0,1"
newline
bitfld.long 0x0 0. "XB,Transfer Busy." "0,1"
line.long 0x4 "MAC_L3_L4_Data,This register has the indirect data and control for accessing the Layer 3 and Layer 4 Filter registers."
hexmask.long 0x4 0.--31. 1. "IDATA,Indirect Data."
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control0,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE0,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control1,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE1,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM1,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM1,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM1,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM1,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN1,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM1,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM1,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM1,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM1,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM1,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM1,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN1,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control10,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE10,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM10,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM10,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM10,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM10,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN10,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM10,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM10,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM10,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM10,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM10,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM10,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN10,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control11,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE11,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM11,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM11,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM11,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM11,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN11,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM11,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM11,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM11,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM11,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM11,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM11,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN11,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control12,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE12,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM12,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM12,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM12,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM12,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN12,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM12,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM12,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM12,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM12,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM12,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM12,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN12,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control13,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE13,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM13,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM13,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM13,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM13,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN13,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM13,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM13,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM13,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM13,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM13,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM13,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN13,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control14,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE14,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM14,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM14,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM14,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM14,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN14,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM14,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM14,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM14,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM14,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM14,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM14,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN14,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control15,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE15,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM15,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM15,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM15,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM15,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN15,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM15,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM15,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM15,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM15,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM15,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM15,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN15,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control2,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE2,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM2,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM2,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM2,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM2,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN2,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM2,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM2,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM2,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM2,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM2,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM2,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN2,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control3,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE3,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM3,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM3,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM3,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM3,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN3,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM3,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM3,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM3,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM3,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM3,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM3,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN3,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control4,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE4,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM4,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM4,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM4,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM4,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN4,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM4,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM4,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM4,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM4,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM4,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM4,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN4,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control5,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE5,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM5,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM5,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM5,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM5,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN5,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM5,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM5,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM5,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM5,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM5,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM5,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN5,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control6,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE6,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM6,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM6,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM6,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM6,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN6,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM6,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM6,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM6,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM6,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM6,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM6,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN6,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control7,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE7,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM7,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM7,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM7,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM7,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN7,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM7,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM7,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM7,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM7,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM7,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM7,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN7,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control8,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE8,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM8,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM8,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM8,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM8,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN8,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM8,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM8,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM8,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM8,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM8,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM8,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN8,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_L3_L4_Control9,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4."
bitfld.long 0x0 31. "DMCHEN,DMA Channel Select Enable." "0,1"
newline
rbitfld.long 0x0 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 27. "Reserved_27_y,Reserved." "0,1"
newline
bitfld.long 0x0 24.--26. "DMCHN,DMA Channel Number." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 23. "Reserved_DMCHLE9,Reserved." "0,1"
newline
rbitfld.long 0x0 22. "Reserved_22,Reserved." "0,1"
newline
bitfld.long 0x0 21. "L4DPIM9,Layer 4 Destination Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 20. "L4DPM9,Layer 4 Destination Port Match Enable." "0,1"
newline
bitfld.long 0x0 19. "L4SPIM9,Layer 4 Source Port Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 18. "L4SPM9,Layer 4 Source Port Match Enable." "0,1"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "L4PEN9,Layer 4 Protocol Enable." "0,1"
newline
hexmask.long.byte 0x0 11.--15. 1. "L3HDBM9,Layer 3 IP DA Higher Bits Match."
newline
hexmask.long.byte 0x0 6.--10. 1. "L3HSBM9,Layer 3 IP SA Higher Bits Match."
newline
bitfld.long 0x0 5. "L3DAIM9,Layer 3 IP DA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 4. "L3DAM9,Layer 3 IP DA Match Enable." "0,1"
newline
bitfld.long 0x0 3. "L3SAIM9,Layer 3 IP SA Inverse Match Enable." "0,1"
newline
bitfld.long 0x0 2. "L3SAM9,Layer 3 IP SA Match Enable." "0,1"
newline
rbitfld.long 0x0 1. "Reserved_1,Reserved." "0,1"
newline
bitfld.long 0x0 0. "L3PEN9,Layer 3 Protocol Enable." "0,1"
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg0,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg1,For IPv4 packets. the Layer 3 Address 0 Register 1 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A01,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg10,For IPv4 packets. the Layer 3 Address 0 Register 10 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A010,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg11,For IPv4 packets. the Layer 3 Address 0 Register 11 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A011,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg12,For IPv4 packets. the Layer 3 Address 0 Register 12 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A012,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg13,For IPv4 packets. the Layer 3 Address 0 Register 13 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A013,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg14,For IPv4 packets. the Layer 3 Address 0 Register 14 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A014,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg15,For IPv4 packets. the Layer 3 Address 0 Register 15 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A015,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg2,For IPv4 packets. the Layer 3 Address 0 Register 2 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A02,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg3,For IPv4 packets. the Layer 3 Address 0 Register 3 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A03,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg4,For IPv4 packets. the Layer 3 Address 0 Register 4 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A04,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg5,For IPv4 packets. the Layer 3 Address 0 Register 5 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A05,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg6,For IPv4 packets. the Layer 3 Address 0 Register 6 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A06,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg7,For IPv4 packets. the Layer 3 Address 0 Register 7 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A07,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg8,For IPv4 packets. the Layer 3 Address 0 Register 8 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A08,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr0_Reg9,For IPv4 packets. the Layer 3 Address 0 Register 9 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A09,Layer 3 Address 0 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg0,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A10,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg1,For IPv4 packets. the Layer 3 Address 1 Register 1 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A11,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg10,For IPv4 packets. the Layer 3 Address 1 Register 10 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A110,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg11,For IPv4 packets. the Layer 3 Address 1 Register 11 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A111,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg12,For IPv4 packets. the Layer 3 Address 1 Register 12 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A112,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg13,For IPv4 packets. the Layer 3 Address 1 Register 13 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A113,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg14,For IPv4 packets. the Layer 3 Address 1 Register 14 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A114,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg15,For IPv4 packets. the Layer 3 Address 1 Register 15 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A115,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg2,For IPv4 packets. the Layer 3 Address 1 Register 2 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A12,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg3,For IPv4 packets. the Layer 3 Address 1 Register 3 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A13,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg4,For IPv4 packets. the Layer 3 Address 1 Register 4 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A14,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg5,For IPv4 packets. the Layer 3 Address 1 Register 5 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A15,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg6,For IPv4 packets. the Layer 3 Address 1 Register 6 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A16,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg7,For IPv4 packets. the Layer 3 Address 1 Register 7 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A17,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg8,For IPv4 packets. the Layer 3 Address 1 Register 8 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A18,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr1_Reg9,For IPv4 packets. the Layer 3 Address 1 Register 9 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A19,Layer 3 Address 1 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg0,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A20,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg1,The Layer 3 Address 2 Register 1 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A21,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg10,The Layer 3 Address 2 Register 10 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A210,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg11,The Layer 3 Address 2 Register 11 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A211,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg12,The Layer 3 Address 2 Register 12 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A212,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg13,The Layer 3 Address 2 Register 13 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A213,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg14,The Layer 3 Address 2 Register 14 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A214,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg15,The Layer 3 Address 2 Register 15 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A215,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg2,The Layer 3 Address 2 Register 2 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A22,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg3,The Layer 3 Address 2 Register 3 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A23,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg4,The Layer 3 Address 2 Register 4 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A24,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg5,The Layer 3 Address 2 Register 5 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A25,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg6,The Layer 3 Address 2 Register 6 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A26,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg7,The Layer 3 Address 2 Register 7 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A27,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg8,The Layer 3 Address 2 Register 8 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A28,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr2_Reg9,The Layer 3 Address 2 Register 9 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A29,Layer 3 Address 2 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg0,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A30,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg1,The Layer 3 Address 3 Register 1 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A31,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg10,The Layer 3 Address 3 Register 10 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A310,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg11,The Layer 3 Address 3 Register 11 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A311,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg12,The Layer 3 Address 3 Register 12 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A312,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg13,The Layer 3 Address 3 Register 13 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A313,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg14,The Layer 3 Address 3 Register 14 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A314,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg15,The Layer 3 Address 3 Register 15 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A315,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg2,The Layer 3 Address 3 Register 2 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A32,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg3,The Layer 3 Address 3 Register 3 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A33,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg4,The Layer 3 Address 3 Register 4 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A34,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg5,The Layer 3 Address 3 Register 5 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A35,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg6,The Layer 3 Address 3 Register 6 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A36,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg7,The Layer 3 Address 3 Register 7 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A37,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg8,The Layer 3 Address 3 Register 8 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A38,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer3_Addr3_Reg9,The Layer 3 Address 3 Register 9 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field."
hexmask.long 0x0 0.--31. 1. "L3A39,Layer 3 Address 3 Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address0,Layer 4 Address 0 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address1,Layer 4 Address 1 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP1,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP1,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address10,Layer 4 Address 10 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP10,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP10,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address11,Layer 4 Address 11 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP11,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP11,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address12,Layer 4 Address 12 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP12,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP12,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address13,Layer 4 Address 13 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP13,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP13,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address14,Layer 4 Address 14 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP14,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP14,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address15,Layer 4 Address 15 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP15,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP15,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address2,Layer 4 Address 2 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP2,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP2,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address3,Layer 4 Address 3 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP3,Layer 4 Destination Port Number Field."
newline
hexmask.long.word 0x0 0.--15. 1. "L4SP3,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address4,Layer 4 Address 4 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP4,Layer 4 Destination Port Number Field."
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hexmask.long.word 0x0 0.--15. 1. "L4SP4,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address5,Layer 4 Address 5 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP5,Layer 4 Destination Port Number Field."
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hexmask.long.word 0x0 0.--15. 1. "L4SP5,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address6,Layer 4 Address 6 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP6,Layer 4 Destination Port Number Field."
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hexmask.long.word 0x0 0.--15. 1. "L4SP6,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address7,Layer 4 Address 7 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP7,Layer 4 Destination Port Number Field."
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hexmask.long.word 0x0 0.--15. 1. "L4SP7,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address8,Layer 4 Address 8 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP8,Layer 4 Destination Port Number Field."
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hexmask.long.word 0x0 0.--15. 1. "L4SP8,Layer 4 Source Port Number Field."
group.long 0xC04++0x3
line.long 0x0 "MAC_Layer4_Address9,Layer 4 Address 9 register has the Layer 4 (TCP. UDP) Source and Destination Port fields checked against the received packet."
hexmask.long.word 0x0 16.--31. 1. "L4DP9,Layer 4 Destination Port Number Field."
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hexmask.long.word 0x0 0.--15. 1. "L4SP9,Layer 4 Source Port Number Field."
group.long 0xC10++0x3
line.long 0x0 "MAC_ARP_Address,The ARP Address register contains the IPv4 Destination Address of the MAC. This register is available only when the Enable IPv4 ARP Offload option is selected."
hexmask.long 0x0 0.--31. 1. "ARPPA,ARP Protocol Address."
group.long 0xD00++0x7
line.long 0x0 "MAC_Timestamp_Control,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver."
rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 28. "AV8021ASMEN,AV IEEE 802.1AS Mode Enable." "0,1"
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rbitfld.long 0x0 25.--27. "Reserved_27_25,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode." "0,1"
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rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 20. "Reserved_ESTI,Reserved." "0,1"
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bitfld.long 0x0 19. "CSC,Enable checksum correction during OST for PTP over UDP/IPv4 packets" "0,1"
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bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering." "0,1"
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bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots." "0,1,2,3"
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bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master." "0,1"
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bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages." "0,1"
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bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP." "0,1"
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bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP." "0,1"
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bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets." "0,1"
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bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format." "0,1"
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bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control." "0,1"
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bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets." "0,1"
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rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
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bitfld.long 0x0 5. "TSADDREG,Update Addend Register." "0,1"
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rbitfld.long 0x0 4. "Reserved_TSTRIG,Reserved." "0,1"
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bitfld.long 0x0 3. "TSUPDT,Update Timestamp." "0,1"
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bitfld.long 0x0 2. "TSINIT,Initialize Timestamp." "0,1"
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bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update." "0,1"
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bitfld.long 0x0 0. "TSENA,Enable Timestamp." "0,1"
line.long 0x4 "MAC_Sub_Second_Increment,The Sub-Second Increment register is present only when the IEEE 1588 timestamp feature is selected without an external timestamp input. In Coarse Update mode [Bit 1 in MAC_Timestamp_Control register]. the value in this register.."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_31_24,Reserved."
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hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value."
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hexmask.long.byte 0x4 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value."
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hexmask.long.byte 0x4 0.--7. 1. "Reserved_7_0,Reserved."
rgroup.long 0xD08++0x7
line.long 0x0 "MAC_System_Time_Seconds,The System Time-Seconds register. along with System Time-Nanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the actual.."
hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second."
line.long 0x4 "MAC_System_Time_Nanoseconds,The System Time-Nanoseconds register. along with System Time-Seconds register. indicates the current value of the system time maintained by the MAC."
bitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
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hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds."
group.long 0xD10++0xF
line.long 0x0 "MAC_System_Time_Seconds_Update,The System Time-Seconds Update register. along with the System Time-Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or.."
hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second."
line.long 0x4 "MAC_System_Time_Nanoseconds_Update,This register is present only when the IEEE 1588 timestamp feature is selected without external timestamp input."
bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time." "0,1"
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hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds."
line.long 0x8 "MAC_Timestamp_Addend,The Timestamp Addend register is present only when the IEEE 1588 Timestamp feature is selected without external timestamp input. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit.."
hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register."
line.long 0xC "MAC_System_Time_Higher_Word_Seconds,The System Time - Higher Word Seconds register is present only when the IEEE 1588 Timestamp feature is selected without an external timestamp input."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
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hexmask.long.word 0xC 0.--15. 1. "TSHWR,Timestamp Higher Word Register."
rgroup.long 0xD20++0x3
line.long 0x0 "MAC_Timestamp_Status,The Timestamp Status register is present only when the IEEE 1588 Timestamp feature is selected. All bits except Bits[29:25] gets cleared when the application reads this register."
bitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
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hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots."
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bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed." "0,1"
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hexmask.long.byte 0x0 20.--23. 1. "Reserved_23_20,Reserved."
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hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier."
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bitfld.long 0x0 15. "TXTSC,Tx Timestamp Captured." "0,1"
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hexmask.long.byte 0x0 10.--14. 1. "TTSNS,Number of Tx Timestamp Snapshots."
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bitfld.long 0x0 9. "TSTRGTERR3,Timestamp Target Time Error." "0,1"
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bitfld.long 0x0 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3." "0,1"
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bitfld.long 0x0 7. "TSTRGTERR2,Timestamp Target Time Error." "0,1"
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bitfld.long 0x0 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2." "0,1"
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bitfld.long 0x0 5. "TSTRGTERR1,Timestamp Target Time Error." "0,1"
newline
bitfld.long 0x0 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1." "0,1"
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bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error." "0,1"
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bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot." "0,1"
newline
bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached." "0,1"
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bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow." "0,1"
rgroup.long 0xD30++0xB
line.long 0x0 "MAC_Tx_Timestamp_Status_Nanoseconds,The MAC_TxTimestamp_Status_Nanoseconds register. along with MAC_TxTimestamp_Status_Seconds. gives the 64-bit timestamp captured for the PTP packet successfully transmitted by the MAC. This value is considered to be.."
bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed." "0,1"
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hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low."
line.long 0x4 "MAC_Tx_Timestamp_Status_Seconds,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted."
hexmask.long 0x4 0.--31. 1. "TXTSSTSHI,Transmit Timestamp Status High."
line.long 0x8 "MAC_Tx_Timestamp_Status_PktID,This register contains the PTP packet ID corresponding to the Tx Timestamp Status in MAC_TxTimestamp_Status_Nanoseconds and MAC_TxTimestamp_Status_Seconds registers. This register is available when IEEE 1588 Tx Timestamp.."
hexmask.long.tbyte 0x8 10.--31. 1. "Reserved_31_10,Reserved."
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hexmask.long.word 0x8 0.--9. 1. "PKTID,Packet ID."
group.long 0xD40++0x3
line.long 0x0 "MAC_Auxiliary_Control,The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved."
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rbitfld.long 0x0 7. "Reserved_ATSEN3,Reserved." "0,1"
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rbitfld.long 0x0 6. "Reserved_ATSEN2,Reserved." "0,1"
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bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable." "0,1"
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bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable." "0,1"
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rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear." "0,1"
rgroup.long 0xD48++0x7
line.long 0x0 "MAC_Auxiliary_Timestamp_Nanoseconds,The Auxiliary Timestamp - Nanoseconds register. along with MAC_Auxiliary_Timestamp_Seconds. gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a.."
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
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hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp Low. Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp."
line.long 0x4 "MAC_Auxiliary_Timestamp_Seconds,The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register."
hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp High. Contains the lower 32 bits of the Seconds field of the auxiliary timestamp."
group.long 0xD50++0x17
line.long 0x0 "MAC_Timestamp_Ingress_Asym_Corr,The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in some PTP messages."
hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction."
line.long 0x4 "MAC_Timestamp_Egress_Asym_Corr,The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in for some PTP message types."
hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction."
line.long 0x8 "MAC_Timestamp_Ingress_Corr_Nanosecond,The MAC Timestamp Ingress Correction Nanosecond register contains the correction value to be used with the captured timestamp value in the ingress path. This is used to compensate the errors due to timestamp.."
hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction."
line.long 0xC "MAC_Timestamp_Ingress_Corr_Subnanosecond,The MAC Timestamp Ingress Correction Sub-Nanosecond register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for ingress directions."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.byte 0xC 8.--15. 1. "TSICSNS,Timestamp Ingress Correction  sub-nanoseconds."
newline
hexmask.long.byte 0xC 0.--7. 1. "Reserved_7_0,Reserved."
line.long 0x10 "MAC_Timestamp_Egress_Corr_Nanosecond,The MAC Egress Timestamp Correction Nanosecond register contains the correction value to be used with the captured timestamp value in the egress path. This is used to compensate the errors due to timestamp.."
hexmask.long 0x10 0.--31. 1. "TSEC,Timestamp Egress Correction."
line.long 0x14 "MAC_Timestamp_Egress_Corr_Subnanosecond,The MAC Timestamp Correction Egress Sub-nanosecond register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for egress directions."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_16,Reserved."
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hexmask.long.byte 0x14 8.--15. 1. "TSECSNS,Timestamp Egress Correction  sub-nanoseconds."
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hexmask.long.byte 0x14 0.--7. 1. "Reserved_7_0,Reserved."
group.long 0xD70++0x3
line.long 0x0 "MAC_PPS_Control,The PPS Control register is present only when the Timestamp feature is selected and External Timestamp is not enabled."
rbitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
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rbitfld.long 0x0 29.--30. "Reserved_TRGTMODSEL3,Reserved." "0,1,2,3"
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rbitfld.long 0x0 27.--28. "Reserved_28_27,Reserved." "0,1,2,3"
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rbitfld.long 0x0 24.--26. "Reserved_PPSCMD3,Reserved." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 23. "Reserved_23,Reserved." "0,1"
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rbitfld.long 0x0 21.--22. "Reserved_TRGTMODSEL2,Reserved." "0,1,2,3"
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rbitfld.long 0x0 19.--20. "Reserved_20_19,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 16.--18. "Reserved_PPSCMD2,Reserved." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
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bitfld.long 0x0 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output." "0,1,2,3"
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rbitfld.long 0x0 11.--12. "Reserved_12_11,Reserved." "0,1,2,3"
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bitfld.long 0x0 8.--10. "PPSCMD1,Flexible PPS1 Output Control." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
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bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output." "0: Target Time registers are programmed only for..,1: Reserved,?,?"
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bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL0_PPSCMD0,PPSCMD0: Flexible PPS Output (ptp_pps_o[0]) Control"
group.long 0xD80++0x1F
line.long 0x0 "MAC_PPS0_Target_Time_Seconds,The PPS0 Target Time Seconds register. along with PPS0 Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these.."
hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS0 Target Time Seconds Register."
line.long 0x4 "MAC_PPS0_Target_Time_Nanoseconds,The PPS0 Target Time Nanoseconds register is present only when more than one Flexible PPS output is selected."
bitfld.long 0x4 31. "TRGTBUSY0,PPS0 Target Time Register Busy." "0,1"
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hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS0 Register."
line.long 0x8 "MAC_PPS0_Interval,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS0 Output Signal Interval."
line.long 0xC "MAC_PPS0_Width,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])."
hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS0 Output Signal Width."
line.long 0x10 "MAC_PPS1_Target_Time_Seconds,The PPS1 Target Time Seconds register. along with PPS1 Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these.."
hexmask.long 0x10 0.--31. 1. "TSTRH1,PPS1 Target Time Seconds."
line.long 0x14 "MAC_PPS1_Target_Time_Nanoseconds,This register is present only when more than one Flexible PPS output is selected while configuring the controller."
bitfld.long 0x14 31. "TRGTBUSY1,PPS1 Target Time Register Busy." "0,1"
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hexmask.long 0x14 0.--30. 1. "TTSL1,Target Time Low for PPS1 Register."
line.long 0x18 "MAC_PPS1_Interval,The PPS1 Interval register contains the number of units of sub-second increment value between the rising edges of PPS1 signal output (ptp_pps_o[1])."
hexmask.long 0x18 0.--31. 1. "PPSINT1,PPS1 Output Signal Interval."
line.long 0x1C "MAC_PPS1_Width,The PPS1 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS1 signal output (ptp_pps_o[1])."
hexmask.long 0x1C 0.--31. 1. "PPSWIDTH1,PPS1 Output Signal Width."
group.long 0xDC0++0x13
line.long 0x0 "MAC_PTO_Control,This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.byte 0x0 8.--15. 1. "DN,Domain Number."
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bitfld.long 0x0 7. "PDRDIS,Disable Peer Delay Response response generation" "0,1"
newline
bitfld.long 0x0 6. "DRRDIS,Disable PTO Delay Request/Response response generation." "0,1"
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bitfld.long 0x0 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger." "0,1"
newline
bitfld.long 0x0 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger." "0,1"
newline
rbitfld.long 0x0 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x0 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable." "0,1"
newline
bitfld.long 0x0 1. "ASYNCEN,Automatic PTP SYNC message Enable." "0,1"
newline
bitfld.long 0x0 0. "PTOEN,PTP Offload Enable." "0,1"
line.long 0x4 "MAC_Source_Port_Identity0,This register along with MAC_Source_Port_Identity1 and MAC_Source_Port_Identity2 contains the 80-bit Source Port Identity of the PTP node. These registers are available only when the Enable PTP Timestamp Offload feature is.."
hexmask.long 0x4 0.--31. 1. "SPI0,Source Port Identity 0."
line.long 0x8 "MAC_Source_Port_Identity1,This register along with MAC_Source_Port_Identity0 and MAC_Source_Port_Identity2 contains the 80-bit Source Port Identity of the PTP node. These registers are available only when the Enable PTP Timestamp Offload feature is.."
hexmask.long 0x8 0.--31. 1. "SPI1,Source Port Identity 1."
line.long 0xC "MAC_Source_Port_Identity2,This register along with MAC_Source_Port_Identity0 and MAC_Source_Port_Identity1 contains the 80-bit Source Port Identity of the PTP node. These registers are available only when the Enable PTP Timestamp Offload feature is.."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "SPI2,Source Port Identity 2."
line.long 0x10 "MAC_Log_Message_Interval,This register contains the periodic intervals for automatic PTP packet generation. This register is available only when the Enable PTP Timestamp Offload feature is selected."
hexmask.long.byte 0x10 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval."
newline
hexmask.long.word 0x10 11.--23. 1. "Reserved_23_11,Reserved."
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bitfld.long 0x10 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x10 0.--7. 1. "LSI,Log Sync Interval."
group.long 0x1000++0x3
line.long 0x0 "MTL_Operation_Mode,The Operation Mode register establishes the Transmit and Receive operating modes and commands."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
bitfld.long 0x0 5.--6. "ETSALG,ETS Algorithm." "0: WRR algorithm,1: WFQ algorithm when Data Center Bridging feature..,2: DWRR algorithm when Data Center Bridging feature..,3: Reserved"
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rbitfld.long 0x0 3.--4. "Reserved_4_3,Reserved." "0,1,2,3"
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bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm." "0: Strict Priority,1: Weighted Strict Priority"
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rbitfld.long 0x0 1. "Reserved_FTS,Reserved." "0,1"
newline
rbitfld.long 0x0 0. "Reserved_0,Reserved." "0,1"
group.long 0x1008++0xB
line.long 0x0 "MTL_Debug_Control,The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access."
hexmask.long.word 0x0 19.--31. 1. "Reserved_31_19,Reserved."
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rbitfld.long 0x0 18. "Reserved_EIEC,Reserved." "0,1"
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rbitfld.long 0x0 17. "Reserved_EIAEE,Reserved." "0,1"
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rbitfld.long 0x0 16. "Reserved_EIEE,Reserved." "0,1"
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rbitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
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bitfld.long 0x0 14. "PKTIE,Receive Packet Available Interrupt Status Enable." "0,1"
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bitfld.long 0x0 12.--13. "FIFOSEL,FIFO Selected for Access." "0: Tx FIFO,1: Descriptor cache,?,?"
newline
bitfld.long 0x0 11. "FIFOWREN,FIFO Write Enable." "0,1"
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bitfld.long 0x0 10. "FIFORDEN,FIFO Read Enable." "0,1"
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bitfld.long 0x0 9. "RSTSEL,Reset Pointers of Selected FIFO." "0,1"
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bitfld.long 0x0 8. "RSTALL,Reset All Pointers." "0,1"
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rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
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bitfld.long 0x0 5.--6. "PKTSTATE,Write Control Type." "0: Packet Data,1: Normal Status,?,?"
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rbitfld.long 0x0 4. "Reserved_4,Reserved." "0,1"
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bitfld.long 0x0 2.--3. "BYTEEN,Write Data Byte Enable." "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,?,?"
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bitfld.long 0x0 1. "DBGMOD,Debug Mode Access to FIFO." "0,1"
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bitfld.long 0x0 0. "FDBGEN,FIFO Debug Access Enable." "0,1"
line.long 0x4 "MTL_Debug_Status,The FIFO Debug Status register contains the status of FIFO debug access."
hexmask.long.word 0x4 16.--31. 1. "LOCR,Remaining Locations in the FIFO."
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hexmask.long.byte 0x4 9.--15. 1. "Reserved_15_9,Reserved."
newline
bitfld.long 0x4 8. "PKTI,Receive Packet Available Interrupt Status." "0,1"
newline
rbitfld.long 0x4 5.--7. "Reserved_7_5,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 3.--4. "BYTEEN,Read Data Byte Enable." "0: Byte 0 valid,1: Byte 0 and Byte 1 are valid,?,?"
newline
rbitfld.long 0x4 1.--2. "PKTSTATE,Read Control Type." "0: Packet Data,1: Normal Status,?,?"
newline
rbitfld.long 0x4 0. "FIFOBUSY,FIFO Busy." "0,1"
line.long 0x8 "MTL_FIFO_Debug_Data,The FIFO Debug Data register contains the data to be written to or read from the FIFOs."
hexmask.long 0x8 0.--31. 1. "FDBGDATA,FIFO Debug Data."
rgroup.long 0x1020++0x3
line.long 0x0 "MTL_Interrupt_Status,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
bitfld.long 0x0 23. "Reserved_MTLPIS,Reserved." "0,1"
newline
bitfld.long 0x0 21.--22. "Reserved_22_21,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 20. "Reserved_SGFIS,Reserved." "0,1"
newline
bitfld.long 0x0 19. "TINS,TBS Interrupt Status" "0,1"
newline
bitfld.long 0x0 18. "ESTIS,EST (TAS- IEEE 802.1Qbv) Interrupt Status" "0,1"
newline
bitfld.long 0x0 17. "DBGIS,Debug Interrupt Status." "0,1"
newline
bitfld.long 0x0 16. "MACIS,MAC Interrupt Status." "0,1"
newline
bitfld.long 0x0 15. "Q15IS,Queue 15 Interrupt Status." "0,1"
newline
bitfld.long 0x0 14. "Q14IS,Queue 14 Interrupt Status." "0,1"
newline
bitfld.long 0x0 13. "Q13IS,Queue 13 Interrupt Status." "0,1"
newline
bitfld.long 0x0 12. "Q12IS,Queue 12 Interrupt Status." "0,1"
newline
bitfld.long 0x0 11. "Q11IS,Queue 11 Interrupt Status." "0,1"
newline
bitfld.long 0x0 10. "Q10IS,Queue 10 Interrupt Status." "0,1"
newline
bitfld.long 0x0 9. "Q9IS,Queue 9 Interrupt Status." "0,1"
newline
bitfld.long 0x0 8. "Q8IS,Queue 8 Interrupt Status." "0,1"
newline
bitfld.long 0x0 7. "Q7IS,Traffic Class/Queue 7 Interrupt Status." "0,1"
newline
bitfld.long 0x0 6. "Q6IS,Traffic Class/Queue 6 Interrupt Status." "0,1"
newline
bitfld.long 0x0 5. "Q5IS,Traffic Class/Queue 5 Interrupt Status." "0,1"
newline
bitfld.long 0x0 4. "Q4IS,Traffic Class/Queue 4 Interrupt Status." "0,1"
newline
bitfld.long 0x0 3. "Q3IS,Traffic Class/Queue 3 Interrupt Status." "0,1"
newline
bitfld.long 0x0 2. "Q2IS,Traffic Class/Queue 2 Interrupt Status." "0,1"
newline
bitfld.long 0x0 1. "Q1IS,Traffic Class/Queue 1 Interrupt Status." "0,1"
newline
bitfld.long 0x0 0. "Q0IS,Traffic Class/Queue 0 Interrupt Status." "0,1"
group.long 0x1030++0x7
line.long 0x0 "MTL_RxQ_DMA_Map0,The Receive Queue and DMA Channel Mapping 0 register controls the static or dynamic mapping of Receive Queues 0-3 to Receive DMA Channels."
bitfld.long 0x0 31. "Q3DDMACH,Receive Queue 3 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_y,Reserved."
newline
bitfld.long 0x0 24.--26. "Q3MDMACH,Receive Queue 3 Mapped to DMA Channel" "0: DMA Channel 0,1: DMA Channel 1,2: DMA Channel 2,3: DMA Channel 3,4: DMA Channel 4,5: DMA Channel 5,6: DMA Channel 6,7: DMA Channel 7"
newline
bitfld.long 0x0 23. "Q2DDMACH,Receive Queue 2 Enabled for Dynamic MA Channel Selection" "0,1"
newline
hexmask.long.byte 0x0 19.--22. 1. "Reserved_22_y,Reserved."
newline
bitfld.long 0x0 16.--18. "Q2MDMACH,Receive Queue 2 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Q1DDMACH,Receive Queue 1 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q1MDMACH,Receive Queue 1 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 7. "Q0DDMACH,Receive Queue 0 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x0 3.--6. 1. "Reserved_6_y,Reserved."
newline
bitfld.long 0x0 0.--2. "Q0MDMACH,Receive Queue 0 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ_DMA_Map1,The Receive Queue and DMA Channel Mapping 1 register controls the static or dynamic mapping of Receive Queues 4-7 to Receive DMA Channels."
bitfld.long 0x4 31. "Q7DDMACH,Receive Queue 7 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x4 27.--30. 1. "Reserved_30_y,Reserved."
newline
bitfld.long 0x4 24.--26. "Q7MDMACH,Receive Queue 7 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 23. "Q6DDMACH,Receive Queue 6 Enabled for Dynamic MA Channel Selection" "0,1"
newline
hexmask.long.byte 0x4 19.--22. 1. "Reserved_22_y,Reserved."
newline
bitfld.long 0x4 16.--18. "Q6MDMACH,Receive Queue 6 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 15. "Q5DDMACH,Receive Queue 5 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x4 11.--14. 1. "Reserved_14_y,Reserved."
newline
bitfld.long 0x4 8.--10. "Q5MDMACH,Receive Queue 5 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 7. "Q4DDMACH,Receive Queue 4 Enabled for Dynamic DMA Channel Selection" "0,1"
newline
hexmask.long.byte 0x4 3.--6. 1. "Reserved_6_y,Reserved."
newline
bitfld.long 0x4 0.--2. "Q4MDMACH,Receive Queue 4 Mapped to DMA Channel" "0,1,2,3,4,5,6,7"
group.long 0x1040++0x1B
line.long 0x0 "MTL_TC_Prty_Map0,This register contains the priority values assigned to traffic classes 0 to 3."
hexmask.long.byte 0x0 24.--31. 1. "PSTC3,Priorities Mapped to Traffic Class 3."
newline
hexmask.long.byte 0x0 16.--23. 1. "PSTC2,Priorities Mapped to Traffic Class 2."
newline
hexmask.long.byte 0x0 8.--15. 1. "PSTC1,Priorities Mapped to Traffic Class 1."
newline
hexmask.long.byte 0x0 0.--7. 1. "PSTC0,Priorities Mapped to Traffic Class 0."
line.long 0x4 "MTL_TC_Prty_Map1,This register contains the priority values assigned to traffic classes 4 to 7."
hexmask.long.byte 0x4 24.--31. 1. "PSTC7,Priorities Mapped to Traffic Class 7."
newline
hexmask.long.byte 0x4 16.--23. 1. "PSTC6,Priorities Mapped to Traffic Class 6."
newline
hexmask.long.byte 0x4 8.--15. 1. "PSTC5,Priorities Mapped to Traffic Class 5."
newline
hexmask.long.byte 0x4 0.--7. 1. "PSTC4,Priorities Mapped to Traffic Class 4."
line.long 0x8 "MTL_TBS_CTRL,This register controls the operation of Time Based Scheduling."
hexmask.long.tbyte 0x8 8.--31. 1. "LEOS,Launch Expiry Offset"
newline
rbitfld.long 0x8 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x8 4.--6. "LEGOS,Launch Expiry GSN Offset" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x8 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x8 2. "TIEN,TBS Interrupt Enable" "0,1"
newline
bitfld.long 0x8 1. "LEOV,Launch Expiry Offset Valid" "0,1"
newline
bitfld.long 0x8 0. "ESTM,EST offset Mode" "0,1"
line.long 0xC "MTL_TBS_STATS,This register provides the One Hot encoded Queue numbers that have the frame drop related error"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "EDQN,Expiry drop Queue number"
line.long 0x10 "MTL_EST_Control,This register controls the operation of Enhancements to Scheduled Transmission (IEEE 802.1Qbv)."
hexmask.long.word 0x10 23.--31. 1. "PTOV,PTP Time Offset Value"
newline
hexmask.long.word 0x10 11.--22. 1. "CTOV,Current Time Offset Value"
newline
bitfld.long 0x10 8.--10. "TILS,Time Interval Left Shift Amount" "0: No left shift needed,1: Left shift TI by 1 bit,?,?,?,?,?,?"
newline
bitfld.long 0x10 6.--7. "LCSE,Loop Count to report Scheduling Error" "0,1,2,3"
newline
bitfld.long 0x10 5. "DFBS,Drop Frames causing Scheduling Error" "0,1"
newline
bitfld.long 0x10 4. "DDBF,Do not Drop frames during Frame Size Error" "0,1"
newline
bitfld.long 0x10 3. "QHLBF,Quick Assertion of HLBF Error" "0,1"
newline
rbitfld.long 0x10 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x10 1. "SSWL,Switch to software owned list" "0,1"
newline
bitfld.long 0x10 0. "EEST,Enable EST" "0,1"
line.long 0x14 "MTL_EST_Overhead,This register indicates the value of Overhead."
hexmask.long.word 0x14 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.byte 0x14 16.--20. 1. "Reserved_ABYT,Reserved."
newline
hexmask.long.byte 0x14 8.--15. 1. "Reserved_15_8,Reserved."
newline
hexmask.long.byte 0x14 0.--7. 1. "OVHD,Overhead Bytes Value"
line.long 0x18 "MTL_EST_Status,This register provides Status related to Enhancements to Scheduled Transmission (IEEE 802.1Qbv)."
hexmask.long.word 0x18 20.--31. 1. "Reserved_31_20,Reserved."
newline
hexmask.long.byte 0x18 16.--19. 1. "CGSN,Current GCL Slot Number."
newline
hexmask.long.byte 0x18 8.--15. 1. "BTRL,BTR Error Loop Count"
newline
rbitfld.long 0x18 7. "SWOL,Software Owned List" "0,1"
newline
rbitfld.long 0x18 5.--6. "Reserved_6_5,Reserved." "0,1,2,3"
newline
bitfld.long 0x18 4. "CGCE,Constant Gate Control Error" "0,1"
newline
rbitfld.long 0x18 3. "HLBS,Head-Of-Line Blocking due to Scheduling" "0,1"
newline
rbitfld.long 0x18 2. "HLBF,Head-Of-Line Blocking due to Frame Size" "0,1"
newline
bitfld.long 0x18 1. "BTRE,BTR Error" "0,1"
newline
bitfld.long 0x18 0. "SWLC,Switch to Software Owned List Complete" "0,1"
group.long 0x1060++0x7
line.long 0x0 "MTL_EST_Sch_Error,This register provides the One Hot encoded Queue numbers that have the scheduling related error (timeout)."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "SETN,Schedule Error TC Number"
line.long 0x4 "MTL_EST_Frm_Size_Error,This register provides the One Hot encoded Queue numbers that have the Frame Size related error."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "FETN,Frame Size Error TC Number"
rgroup.long 0x1068++0x3
line.long 0x0 "MTL_EST_Frm_Size_Capture,This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error. Upon clearing. this register captures the data of the next occurrence of a similar error."
hexmask.long.word 0x0 19.--31. 1. "Reserved_31_x,Reserved."
newline
bitfld.long 0x0 16.--18. "HBFQ,Queue Number of HLBF" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF"
group.long 0x1070++0x3
line.long 0x0 "MTL_EST_Intr_Enable,This register implements the Interrupt Enable bits for the various events that generate an interrupt. Bit positions have a 1- to-1 correspondence with the status bit positions in MTL_EST_Status register."
hexmask.long 0x0 5.--31. 1. "Reserved_31_5,Reserved."
newline
bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE" "0,1"
newline
bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS" "0,1"
newline
bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF" "0,1"
newline
bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error" "0,1"
newline
bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List" "0,1"
group.long 0x1080++0x7
line.long 0x0 "MTL_GCL_Control,This register provides the control information for reading/writing to the Gate Control lists."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
rbitfld.long 0x0 23. "GCLEIEC,ECC Inject Error Control for GCL Memory" "0,1"
newline
rbitfld.long 0x0 22. "GCLEIAEE,GCL ECC Inject Address Error Enable" "0,1"
newline
rbitfld.long 0x0 21. "GCLEIEE,GCL ECC Inject Error Enable" "0,1"
newline
hexmask.long.byte 0x0 16.--20. 1. "Reserved_20_y,Reserved."
newline
hexmask.long.byte 0x0 8.--15. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is 0)."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select" "0,1"
newline
bitfld.long 0x0 4. "DBGM,Debug Mode" "0,1"
newline
rbitfld.long 0x0 3. "Reserved_GCLS,Reserved." "0,1"
newline
bitfld.long 0x0 2. "GCRR,Gate Control Related Registers" "0,1"
newline
bitfld.long 0x0 1. "R1W0,Read 1  Write 0:" "0: Write Operation,1: Read Operation"
newline
bitfld.long 0x0 0. "SRWO,Start Read/Write Op" "0,1"
line.long 0x4 "MTL_GCL_Data,This register holds the read data or write data in case of reads and writes respectively."
hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data"
group.long 0x1090++0x7
line.long 0x0 "MTL_FPE_CTRL_STS,This register controls the operation of. and provides status for Frame Preemption (IEEE 802.1Qbu/802.3br)."
rbitfld.long 0x0 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 28. "HRS,Hold/Release Status" "0: Indicates a Set-and-Release-MAC operation was..,1: Indicates a Set-and-Hold-MAC operation was last.."
newline
hexmask.long.word 0x0 17.--27. 1. "Reserved_27_17,Reserved."
newline
bitfld.long 0x0 16. "PHRSC,Preemption MAC Hold/Release Sideband Control Select" "0: Indicates that Set-Hold-and-Release-MAC..,1: Indicates that Set-Hold-and-Release-MAC.."
newline
hexmask.long.byte 0x0 8.--15. 1. "PEC,Preemption Classification"
newline
bitfld.long 0x0 7. "LBHT,Level Based Hold Transition" "0,1"
newline
hexmask.long.byte 0x0 2.--6. 1. "Reserved_6_2,Reserved."
newline
bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size" "0,1,2,3"
line.long 0x4 "MTL_FPE_Advance,This register holds the Hold and Release Advance time."
hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance"
newline
hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance"
group.long 0x1100++0x3
line.long 0x0 "MTL_TxQ0_Operation_Mode,The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1104++0x7
line.long 0x0 "MTL_TxQ0_Underflow,The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ0_Debug,The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 0 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1110++0x3
line.long 0x0 "MTL_TC0_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1114++0x3
line.long 0x0 "MTL_TC0_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1118++0x3
line.long 0x0 "MTL_TC0_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1140++0x3
line.long 0x0 "MTL_RxQ0_Operation_Mode,The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1144++0x7
line.long 0x0 "MTL_RxQ0_Missed_Pkt_Overflow_Cnt,The Queue 0 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ0_Debug,The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x114C++0x7
line.long 0x0 "MTL_RxQ0_Control,The Queue 0 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ0_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1170++0x7
line.long 0x0 "MTL_Q0_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 0."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q0_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 0."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1180++0x3
line.long 0x0 "MTL_TxQ1_Operation_Mode,The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1184++0x7
line.long 0x0 "MTL_TxQ1_Underflow,The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ1_Debug,The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 1 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1190++0x3
line.long 0x0 "MTL_TC1_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1194++0x3
line.long 0x0 "MTL_TC1_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1198++0x3
line.long 0x0 "MTL_TC1_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x11C0++0x3
line.long 0x0 "MTL_RxQ1_Operation_Mode,The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x11C4++0x7
line.long 0x0 "MTL_RxQ1_Missed_Pkt_Overflow_Cnt,The Queue 1 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ1_Debug,The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x11CC++0x7
line.long 0x0 "MTL_RxQ1_Control,The Queue 1 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ1_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x11F0++0x7
line.long 0x0 "MTL_Q1_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 1."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q1_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 1."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1200++0x3
line.long 0x0 "MTL_TxQ2_Operation_Mode,The Queue 2 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1204++0x7
line.long 0x0 "MTL_TxQ2_Underflow,The Queue 2 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ2_Debug,The Queue 2 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 2 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1210++0x3
line.long 0x0 "MTL_TC2_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1214++0x3
line.long 0x0 "MTL_TC2_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1218++0x3
line.long 0x0 "MTL_TC2_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1240++0x3
line.long 0x0 "MTL_RxQ2_Operation_Mode,The Queue 2 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1244++0x7
line.long 0x0 "MTL_RxQ2_Missed_Pkt_Overflow_Cnt,The Queue 2 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ2_Debug,The Queue 2 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x124C++0x7
line.long 0x0 "MTL_RxQ2_Control,The Queue 2 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ2_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1270++0x7
line.long 0x0 "MTL_Q2_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 2."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q2_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 2."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1280++0x3
line.long 0x0 "MTL_TxQ3_Operation_Mode,The Queue 3 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1284++0x7
line.long 0x0 "MTL_TxQ3_Underflow,The Queue 3 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ3_Debug,The Queue 3 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 3 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1290++0x3
line.long 0x0 "MTL_TC3_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1294++0x3
line.long 0x0 "MTL_TC3_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1298++0x3
line.long 0x0 "MTL_TC3_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x12C0++0x3
line.long 0x0 "MTL_RxQ3_Operation_Mode,The Queue 3 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x12C4++0x7
line.long 0x0 "MTL_RxQ3_Missed_Pkt_Overflow_Cnt,The Queue 3 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ3_Debug,The Queue 3 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x12CC++0x7
line.long 0x0 "MTL_RxQ3_Control,The Queue 3 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ3_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x12F0++0x7
line.long 0x0 "MTL_Q3_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 3."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q3_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 3."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1300++0x3
line.long 0x0 "MTL_TxQ4_Operation_Mode,The Queue 4 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1304++0x7
line.long 0x0 "MTL_TxQ4_Underflow,The Queue 4 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ4_Debug,The Queue 4 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 4 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1310++0x3
line.long 0x0 "MTL_TC4_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1314++0x3
line.long 0x0 "MTL_TC4_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1318++0x3
line.long 0x0 "MTL_TC4_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1340++0x3
line.long 0x0 "MTL_RxQ4_Operation_Mode,The Queue 4 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1344++0x7
line.long 0x0 "MTL_RxQ4_Missed_Pkt_Overflow_Cnt,The Queue 4 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ4_Debug,The Queue 4 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x134C++0x7
line.long 0x0 "MTL_RxQ4_Control,The Queue 4 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ4_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1370++0x7
line.long 0x0 "MTL_Q4_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 4."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q4_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 4."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1380++0x3
line.long 0x0 "MTL_TxQ5_Operation_Mode,The Queue 5 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1384++0x7
line.long 0x0 "MTL_TxQ5_Underflow,The Queue 5 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ5_Debug,The Queue 5 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 5 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1390++0x3
line.long 0x0 "MTL_TC5_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1394++0x3
line.long 0x0 "MTL_TC5_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1398++0x3
line.long 0x0 "MTL_TC5_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x13C0++0x3
line.long 0x0 "MTL_RxQ5_Operation_Mode,The Queue 5 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x13C4++0x7
line.long 0x0 "MTL_RxQ5_Missed_Pkt_Overflow_Cnt,The Queue 5 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ5_Debug,The Queue 5 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x13CC++0x7
line.long 0x0 "MTL_RxQ5_Control,The Queue 5 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ5_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x13F0++0x7
line.long 0x0 "MTL_Q5_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 5."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q5_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 5."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1400++0x3
line.long 0x0 "MTL_TxQ6_Operation_Mode,The Queue 6 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1404++0x7
line.long 0x0 "MTL_TxQ6_Underflow,The Queue 6 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ6_Debug,The Queue 6 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 6 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1410++0x3
line.long 0x0 "MTL_TC6_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
rbitfld.long 0x0 4.--6. "Reserved_SLC,Reserved." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 3. "Reserved_CC,Reserved." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1414++0x3
line.long 0x0 "MTL_TC6_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1418++0x3
line.long 0x0 "MTL_TC6_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
group.long 0x1440++0x3
line.long 0x0 "MTL_RxQ6_Operation_Mode,The Queue 6 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x1444++0x7
line.long 0x0 "MTL_RxQ6_Missed_Pkt_Overflow_Cnt,The Queue 6 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ6_Debug,The Queue 6 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x144C++0x7
line.long 0x0 "MTL_RxQ6_Control,The Queue 6 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ6_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x1470++0x7
line.long 0x0 "MTL_Q6_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 6."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q6_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 6."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x1480++0x3
line.long 0x0 "MTL_TxQ7_Operation_Mode,The Queue 7 Transmit Operation Mode register establishes the Transmit queue operating modes and commands."
hexmask.long.word 0x0 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--22. 1. "TQS,Transmit Queue Size."
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_15_y,Reserved."
newline
bitfld.long 0x0 8.--10. "Q2TCMAP,Queue to Traffic Class Mapping." "0: TC0,1: TC1,2: TC2,3: TC3,4: TC4,5: TC5,6: TC6,7: TC7"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control." "0: 64,1: Reserved,2: 96,3: 128,4: 192,5: 256,6: 384,7: 512"
newline
bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable." "0: Not enabled,1: Audio Video Bridging,2: Enabled,3: Reserved"
newline
bitfld.long 0x0 1. "TSF,Transmit Store and Forward." "0,1"
newline
bitfld.long 0x0 0. "FTQ,Flush Transmit Queue." "0,1"
rgroup.long 0x1484++0x7
line.long 0x0 "MTL_TxQ7_Underflow,The Queue 7 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x0 15. "UFCNTOVF,Overflow Bit for Underflow Packet Counter." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "UFPKTCNT,Underflow Packet Counter."
line.long 0x4 "MTL_TxQ7_Debug,The Queue 7 Transmit Debug register gives the debug status of various blocks related to the Transmit Queue 7 and Traffic Class 0."
hexmask.long 0x4 6.--31. 1. "Reserved_31_6,Reserved."
newline
bitfld.long 0x4 5. "TRCPSTS,MTL TRC Pending Status" "0,1"
newline
bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status." "0,1"
newline
bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status." "0,1"
newline
bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status." "0: Idle state,1: Read state,2: Waiting for pending Tx Status from the MAC..,3: Flushing the Tx queue because of the Packet.."
newline
bitfld.long 0x4 0. "TCPAUSED,Traffic Class in Pause." "0,1"
group.long 0x1490++0x3
line.long 0x0 "MTL_TC7_ETS_Control,This register configures the transmission selection algorithm. for Traffic Class 0.This register is not available in single traffic class configuration."
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
bitfld.long 0x0 4.--6. "SLC,Slot Count." "0: 1 Slot,1: 2 Slots,2: 4 Slots,3: 8 Slots,4: 16 Slots,?,?,?"
newline
bitfld.long 0x0 3. "CC,Credit Control." "0,1"
newline
rbitfld.long 0x0 2. "CBSEN,Credit Based Shaper Enable" "0,1"
newline
bitfld.long 0x0 0.--1. "TSA,Transmission Selection Algorithm." "0: Strict priority,1: CBS,2: ETS,3: Reserved"
rgroup.long 0x1494++0x3
line.long 0x0 "MTL_TC7_ETS_Status,This register contains the information of average bits transmitted over a slot interval of 10 million bit times. for Traffic Class 0."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved."
newline
hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot."
group.long 0x1498++0xF
line.long 0x0 "MTL_TC7_Quantum_Weight,The TC1 Quantum or Weights register provides the average traffic transmitted in Traffic Class 1. For TCn. where n = 1 to 7. this register is not available when the number of traffic classes selected is less than n + 1"
hexmask.long.word 0x0 21.--31. 1. "Reserved_31_21,Reserved."
newline
hexmask.long.tbyte 0x0 0.--20. 1. "QW,idleSlopeCredit  Quantum or Weights."
line.long 0x4 "MTL_TC7_SendSlopeCredit,MTL registers for traffic classes and queues 1 registers."
hexmask.long.word 0x4 16.--31. 1. "Reserved_31_16,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "SSC,sendSlopeCredit Value."
line.long 0x8 "MTL_TC7_HiCredit,This register contains the hiCredit value required for the credit-based shaper algorithm for TC1.."
rbitfld.long 0x8 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value."
line.long 0xC "MTL_TC7_LoCredit,This register contains the loCredit value required for the credit-based shaper algorithm for TC1."
rbitfld.long 0xC 29.--31. "Reserved_31_29,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long 0xC 0.--28. 1. "LC,loCredit Value."
group.long 0x14C0++0x3
line.long 0x0 "MTL_RxQ7_Operation_Mode,The Queue 7 Receive Operation Mode register establishes the Receive queue operating modes and command."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x0 16.--21. 1. "RQS,Receive Queue Size."
newline
hexmask.long.byte 0x0 8.--15. 1. "Reserved_15_8,Reserved."
newline
bitfld.long 0x0 7. "EHFC,Enable Hardware Flow Control." "0,1"
newline
bitfld.long 0x0 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets." "0,1"
newline
bitfld.long 0x0 5. "RSF,Receive Queue Store and Forward." "0: Rx queue operates in the Threshold,1: DWC_xgmac reads a packet from the Rx queue only.."
newline
bitfld.long 0x0 4. "FEF,Forward Error Packets." "0: Rx queue drops packets with error status,1: All packets except the runt error packets are.."
newline
bitfld.long 0x0 3. "FUF,Forward Undersized Good Packets." "0: Rx queue drops all packets of length less than..,1: Rx queue forwards the undersized good packets"
newline
rbitfld.long 0x0 2. "Reserved_2,Reserved." "0,1"
newline
bitfld.long 0x0 0.--1. "RTC,Receive Queue Threshold Control." "0: 64,1: Reserved,2: 96,3: 128"
rgroup.long 0x14C4++0x7
line.long 0x0 "MTL_RxQ7_Missed_Pkt_Overflow_Cnt,The Queue 7 Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow."
bitfld.long 0x0 31. "MISCNTOVF,Missed Packet Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "Reserved_30_27,Reserved."
newline
hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter."
newline
bitfld.long 0x0 15. "OVFCNTOVF,Overflow Counter Overflow Bit." "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter."
line.long 0x4 "MTL_RxQ7_Debug,The Queue 7 Receive Debug register gives the debug status of various blocks related to the Receive queue."
bitfld.long 0x4 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue."
newline
hexmask.long.word 0x4 6.--15. 1. "Reserved_15_6,Reserved."
newline
bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status." "0: Rx Queue empty,1: Rx Queue fill-level below flow-control..,2: Rx Queue fill-level above flow-control activate..,3: Rx Queue full"
newline
bitfld.long 0x4 3. "Reserved_3,Reserved." "0,1"
newline
bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State." "0: Idle state,1: Reading packet data,2: Reading packet status,3: Flushing the packet data and status"
newline
bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status." "0,1"
group.long 0x14CC++0x7
line.long 0x0 "MTL_RxQ7_Control,The Queue 7 Receive Control register controls the receive arbitration and passing of received packets to the application."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
bitfld.long 0x0 3. "RXQ_PKT_ARBIT,Receive Queue Packet Arbitration Control." "0: MTL enables the PBL based arbitration,1: MTL enables the packet-level arbitration"
newline
bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight." "0,1,2,3,4,5,6,7"
line.long 0x4 "MTL_RxQ7_Flow_Control,This register controls the activation and de-activation threshold in the queue for PAUSE/PFC flow control."
hexmask.long.word 0x4 22.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 17.--21. 1. "RFD,Threshold for deactivating Flow Control."
newline
hexmask.long.word 0x4 6.--16. 1. "Reserved_16_y,Reserved."
newline
hexmask.long.byte 0x4 1.--5. 1. "RFA,Threshold for activating Flow Control."
newline
rbitfld.long 0x4 0. "Reserved_0,Reserved." "0,1"
group.long 0x14F0++0x7
line.long 0x0 "MTL_Q7_Interrupt_Enable,This register contains the interrupt enable bits for Traffic class/Queue 7."
hexmask.long.word 0x0 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x0 16. "RXOIE,Receive Queue Overflow Interrupt Enable." "0: Receive Queue Overflow interrupt is disabled,1: Receive Queue Overflow interrupt is enabled"
newline
hexmask.long.word 0x0 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x0 1. "ABPSIE,Average Bits Per Slot Interrupt Enable." "0,1"
newline
bitfld.long 0x0 0. "TXUIE,Transmit Queue Underflow Interrupt Enable." "0: Transmit Queue Underflow interrupt is disabled,1: Transmit Queue Underflow interrupt is enabled"
line.long 0x4 "MTL_Q7_Interrupt_Status,This register contains the interrupt status bits for Traffic class/Queue 7."
hexmask.long.word 0x4 17.--31. 1. "Reserved_31_17,Reserved."
newline
bitfld.long 0x4 16. "RXOVFIS,Receive Queue Overflow Interrupt Status." "0,1"
newline
hexmask.long.word 0x4 2.--15. 1. "Reserved_15_2,Reserved."
newline
bitfld.long 0x4 1. "ABPSIS,Average Bits Per Slot Interrupt Status." "0,1"
newline
bitfld.long 0x4 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status." "0,1"
group.long 0x3000++0x7
line.long 0x0 "DMA_Mode,The Bus Mode register establishes the bus operating modes for the DMA."
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_31_14,Reserved."
newline
bitfld.long 0x0 12.--13. "INTM,Interrupt Mode." "0: sbd_perch_* are pulse signals for each..,1: sbd_perch_* are level signals asserted on the..,?,?"
newline
rbitfld.long 0x0 9.--11. "Reserved_11_9,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8. "DSPW,Descriptor Posted Write." "0: By default,1: All Rx DMA data and descriptor writes are posted.."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
rbitfld.long 0x0 5. "Reserved_TMRP,Reserved." "0,1"
newline
bitfld.long 0x0 4. "TDRP,Tx Descriptor Read Priority." "0,1"
newline
rbitfld.long 0x0 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "SWR,Software Reset." "0,1"
line.long 0x4 "DMA_SysBus_Mode,The System Bus mode register controls the behavior of the AXI master. It mainly controls burst splitting and number of outstanding requests."
rbitfld.long 0x4 29.--31. "Reserved_31_30,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 24.--28. 1. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit."
newline
rbitfld.long 0x4 21.--23. "Reserved_23_22,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 16.--20. 1. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit."
newline
bitfld.long 0x4 15. "EN_LPI,Enable Low Power Interface (LPI)." "0: Disables the LPI mode and always denies the LPI..,1: Enables the LPI mode supported by the AXI.."
newline
bitfld.long 0x4 14. "LPI_XIT_PKT,Unlock on Magic Packet or Remote Wake-Up Packet." "0: Enables the AXI master to come out of the LPI..,1: Enables the AXI master to come out of the LPI.."
newline
bitfld.long 0x4 13. "ONEKBBE,1 KB Boundary Crossing Enable for the AXI Master." "0: The burst transfers performed by the AXI master..,1: The burst transfers performed by the AXI master.."
newline
bitfld.long 0x4 12. "AAL,Address-Aligned Beats." "0,1"
newline
bitfld.long 0x4 11. "EAME,Enhanced Address Mode Enable." "?,1: DMA master enables the enhanced address mode"
newline
bitfld.long 0x4 10. "AALE,Automatic AXI LPI enable." "?,1: Enables the AXI master to enter into LPI state.."
newline
rbitfld.long 0x4 8.--9. "Reserved_9_8,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 7. "BLEN256,AXI Burst Length 256." "0,1"
newline
bitfld.long 0x4 6. "BLEN128,AXI Burst Length 128." "0,1"
newline
bitfld.long 0x4 5. "BLEN64,AXI Burst Length 64." "0,1"
newline
bitfld.long 0x4 4. "BLEN32,AXI Burst Length 32." "0,1"
newline
bitfld.long 0x4 3. "BLEN16,AXI Burst Length 16." "0,1"
newline
bitfld.long 0x4 2. "BLEN8,AXI Burst Length 8." "0,1"
newline
bitfld.long 0x4 1. "BLEN4,AXI Burst Length 4." "0,1"
newline
bitfld.long 0x4 0. "UBL,AXI Undefined Burst Length." "0: The AXI master performs one of the following..,1: The AXI master can perform burst transfers that.."
rgroup.long 0x3008++0x3
line.long 0x0 "DMA_Interrupt_Status,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels. MTL queues. and the MAC."
hexmask.long.word 0x0 18.--31. 1. "Reserved_31_18,Reserved."
newline
bitfld.long 0x0 17. "MACIS,MAC Interrupt Status." "0,1"
newline
bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status." "0,1"
newline
hexmask.long.byte 0x0 8.--15. 1. "DC15TC8IS,DMA Channel 15 Interrupt Status to DMA Channel 8 Interrupt Status."
newline
bitfld.long 0x0 7. "DC7IS,DMA Channel 7 Interrupt Status." "0,1"
newline
bitfld.long 0x0 6. "DC6IS,DMA Channel 6 Interrupt Status." "0,1"
newline
bitfld.long 0x0 5. "DC5IS,DMA Channel 5 Interrupt Status." "0,1"
newline
bitfld.long 0x0 4. "DC4IS,DMA Channel 4 Interrupt Status." "0,1"
newline
bitfld.long 0x0 3. "DC3IS,DMA Channel 3 Interrupt Status." "0,1"
newline
bitfld.long 0x0 2. "DC2IS,DMA Channel 2 Interrupt Status." "0,1"
newline
bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status." "0,1"
newline
bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status." "0,1"
group.long 0x3010++0x3
line.long 0x0 "AXI_Tx_AR_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for read transactions by all the Transmit DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding.."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 20.--21. "THD,Transmit DMA First Packet Buffer or TSO Header Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "THC,Transmit DMA First Packet Buffer or TSO Header Cache Control."
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "TED,Transmit DMA Extended Packet Buffer or TSO Payload Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 8.--11. 1. "TEC,Transmit DMA Extended Packet Buffer or TSO Payload Cache Control."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "TDRD,Transmit DMA Read Descriptor Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "TDRC,Transmit DMA Read Descriptor Cache Control."
group.long 0x3018++0x7
line.long 0x0 "AXI_Rx_AW_ACE_Control,This register is used to control the Cache Coherency Signals of the AXI4-ACE Lite on the Receive DMA. The programmable controllability is supported on the following signals of the AXI Write channel."
rbitfld.long 0x0 30.--31. "Reserved_31_30,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 28.--29. "RDD,Receive DMA Buffer Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--27. 1. "RDC,Receive DMA Buffer Cache Control."
newline
rbitfld.long 0x0 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 20.--21. "RHD,Receive DMA Header Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--19. 1. "RHC,Receive DMA Header Cache Control."
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "RPD,Receive DMA Payload Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 8.--11. 1. "RPC,Receive DMA Payload Cache Control."
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "RDWD,Receive DMA Write Descriptor Domain Control." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "RDWC,Receive DMA Write Descriptor Cache Control."
line.long 0x4 "AXI_TxRx_AWAR_ACE_Control,This register is used to control the AXI4 Cache Coherency Signals for Descriptor write transactions by all the TxDMA channels and Descriptor read transactions by all the RxDMA channels. It also controls the values to be driven.."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_23,Reserved."
newline
bitfld.long 0x4 20.--22. "WRP,DMA Write Protection control." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 19. "Reserved_19,Reserved." "0,1"
newline
bitfld.long 0x4 16.--18. "RDP,DMA Read Protection control." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "RDRD,Receive DMA Read Descriptor Domain control." "0,1,2,3"
newline
hexmask.long.byte 0x4 8.--11. 1. "RDRC,Receive DMA Read Descriptor Cache control."
newline
rbitfld.long 0x4 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control." "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--3. 1. "TDWC,Transmit DMA Write Descriptor Cache control."
rgroup.long 0x3020++0x7
line.long 0x0 "DMA_Debug_Status0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0 - Channel 2 for debugging purpose."
hexmask.long.byte 0x0 28.--31. 1. "TPS2,DMA Channel 2 Transmit Process State."
newline
hexmask.long.byte 0x0 24.--27. 1. "RPS2,DMA Channel 2 Receive Process State."
newline
hexmask.long.byte 0x0 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State."
newline
hexmask.long.byte 0x0 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State."
newline
hexmask.long.byte 0x0 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State."
newline
hexmask.long.byte 0x0 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State."
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_7_2,Reserved."
newline
bitfld.long 0x0 1. "AXRHSTS,AXI Master Read Channel Status." "0,1"
newline
bitfld.long 0x0 0. "AXWHSTS,AXI Master Write Channel Status." "?,1: Indicates that the write channel of the AXI.."
line.long 0x4 "DMA_Debug_Status1,The Debug Status1 register gives the per Transmit DMA active status."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "TDAS,Transmit DMA Active Status."
rgroup.long 0x302C++0x3
line.long 0x0 "DMA_Debug_Status3,The Debug Status3 register gives the per Receive DMA active status."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_x,Reserved."
newline
hexmask.long.byte 0x0 0.--7. 1. "RDAS,Receive DMA Active Status."
group.long 0x3040++0x7
line.long 0x0 "DMA_Tx_EDMA_Control,The DMA_Tx_EDMA_Control register controls the sequence of all TxDMA operations with the DMA engine."
bitfld.long 0x0 30.--31. "TEDM,Tx DMA Mode." "0: Default mode of DMA,1: The value of TDPS field is ignored and only one..,2: The value of TDPS field is ignored and only one..,3: All operations are sequential"
newline
hexmask.long 0x0 2.--29. 1. "Reserved_29_y,Reserved."
newline
bitfld.long 0x0 0.--1. "TDPS,Tx Descriptor Pre-fetch threshold Size." "0: Threshold of 0 descriptors,1: Threshold is 4 descriptors,2: Threshold is 8 descriptors,3: Threshold is 12 descriptors"
line.long 0x4 "DMA_Rx_EDMA_Control,The DMA_Rx_EDMA_Control register controls the sequence of all RxDMA operations with the DMA engine."
bitfld.long 0x4 30.--31. "REDM,Rx DMA Mode." "0: Default mode of DMA as explained in section 2,1: The value of RDPS field is ignored and only 1..,2: The value of RDPS field is ignored and only 1..,3: All operations are sequential"
newline
hexmask.long 0x4 2.--29. 1. "Reserved_29_y,Reserved."
newline
bitfld.long 0x4 0.--1. "RDPS,Rx Descriptor Pre-Fetch Threshold Size." "0: Threshold of 0 descriptors,1: Threshold is 4 descriptors,2: Threshold is 8 descriptors,3: Threshold is 12 descriptors"
group.long 0x3050++0x13
line.long 0x0 "AXI_LPI_Entry_Interval,This register is used to control the AXI LPI entry interval."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved."
newline
hexmask.long.byte 0x0 0.--3. 1. "LPIEI,LPI Entry Interval"
line.long 0x4 "DMA_TBS_CTRL0,This register is used to control the TBS0 attributes."
hexmask.long.tbyte 0x4 8.--31. 1. "FTOS,Fetch Time Offset 0"
newline
rbitfld.long 0x4 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x4 4.--6. "FGOS,Fetch GSN Offset 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "FTOV,Fetch Time Offset 0 Valid" "0,1"
line.long 0x8 "DMA_TBS_CTRL1,This register is used to control the TBS1 attributes."
hexmask.long.tbyte 0x8 8.--31. 1. "FTOS,Fetch Time Offset 1"
newline
rbitfld.long 0x8 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x8 4.--6. "FGOS,Fetch GSN Offset 1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x8 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "FTOV,Fetch Time Offset 1 Valid" "0,1"
line.long 0xC "DMA_TBS_CTRL2,This register is used to control the TBS2 attributes."
hexmask.long.tbyte 0xC 8.--31. 1. "FTOS,Fetch Time Offset 2"
newline
rbitfld.long 0xC 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0xC 4.--6. "FGOS,Fetch GSN Offset 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0xC 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 0. "FTOV,Fetch Time Offset 2 Valid" "0,1"
line.long 0x10 "DMA_TBS_CTRL3,This register is used to control the TBS3 attributes."
hexmask.long.tbyte 0x10 8.--31. 1. "FTOS,Fetch Time Offset 3"
newline
rbitfld.long 0x10 7. "Reserved_7,Reserved." "0,1"
newline
bitfld.long 0x10 4.--6. "FGOS,Fetch GSN Offset 3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "FTOV,Fetch Time Offset 3 Valid" "0,1"
group.long 0x3080++0x7
line.long 0x0 "DMA_CH_Ind_Ctrl,This register is used to program Indirect Access DMA configuration registers"
hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved."
newline
hexmask.long.byte 0x0 16.--19. 1. "MSEL,Mode Select"
newline
hexmask.long.byte 0x0 12.--15. 1. "Reserved_15_12,Reserved."
newline
hexmask.long.byte 0x0 8.--11. 1. "AOFF,Address Offset"
newline
rbitfld.long 0x0 6.--7. "Reserved_7_6,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 4.--5. "AUTO,Auto Increment" "0: No auto increment,1: Auto increment MSEL only,?,?"
newline
rbitfld.long 0x0 2.--3. "Reserved_3_2,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 1. "CT,Command Type" "0: Indicates a write operation,1: Indicates a read operation"
newline
bitfld.long 0x0 0. "OB,Operation Busy" "0,1"
line.long 0x4 "DMA_CH_Ind_Data,This register holds the read/write data for Indirect Access of the registers indicated by DMA_<MSEL>_<AOFF>. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field.."
hexmask.long 0x4 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH0_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH1_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH2_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH3_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH4_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH5_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH6_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3084++0x3
line.long 0x0 "DMA_CH7_TxExtCfg,This register contains data related to per channel Tx weights used for"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved."
newline
hexmask.long.byte 0x0 0.--6. 1. "WT,Weights"
group.long 0x3100++0x1F
line.long 0x0 "DMA_CH0_Control,The DMA Channel0 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH0_Tx_Control,The DMA Channel0 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH0_Rx_Control,The DMA Channel0 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel0 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH0_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH0_TxDesc_List_HAddress,The Channel0 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH0_TxDesc_List_LAddress,The Channel0 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH0_RxDesc_List_HAddress,The Channel0 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH0_RxDesc_List_LAddress,The Channel0 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3124++0x3
line.long 0x0 "DMA_CH0_TxDesc_Tail_LPointer,The Channel0 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x312C++0x13
line.long 0x0 "DMA_CH0_RxDesc_Tail_LPointer,The Channel0 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH0_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
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bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
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hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH0_Rx_Control2,The Channel0 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
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bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
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rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH0_Interrupt_Enable,The Channel0 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
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bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
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bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
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bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
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rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
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bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
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bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
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rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
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bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH0_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
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hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
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hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
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rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
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hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3144++0x3
line.long 0x0 "DMA_CH0_Current_App_TxDesc_L,The Channel0 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x314C++0x13
line.long 0x0 "DMA_CH0_Current_App_RxDesc_L,The Channel0 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH0_Current_App_TxBuffer_H,The Channel0 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH0_Current_App_TxBuffer_L,The Channel0 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH0_Current_App_RxBuffer_H,The Channel0 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH0_Current_App_RxBuffer_L,The Channel0 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3160++0x3
line.long 0x0 "DMA_CH0_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
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bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
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bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
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bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
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bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
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bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
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bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
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rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
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bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
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bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
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bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
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rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
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bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
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bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3164++0x1B
line.long 0x0 "DMA_CH0_Debug_Status,DMA Channe0 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
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bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
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bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
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bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
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bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH0_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
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hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
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hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH0_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH0_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
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hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
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hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH0_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH0_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH0_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
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hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH0_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3180++0x1F
line.long 0x0 "DMA_CH1_Control,The DMA Channel1 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
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bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
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rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
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bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
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rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH1_Tx_Control,The DMA Channel1 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
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rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
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rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
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rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
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rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
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bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
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hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
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rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
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rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH1_Rx_Control,The DMA Channel1 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel1 Packet Flush." "0,1"
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rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
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rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
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rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
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hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
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rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH1_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
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hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
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hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
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bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
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bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH1_TxDesc_List_HAddress,The Channel1 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH1_TxDesc_List_LAddress,The Channel1 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
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rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH1_RxDesc_List_HAddress,The Channel1 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH1_RxDesc_List_LAddress,The Channel1 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x31A4++0x3
line.long 0x0 "DMA_CH1_TxDesc_Tail_LPointer,The Channel1 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x31AC++0x13
line.long 0x0 "DMA_CH1_RxDesc_Tail_LPointer,The Channel1 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH1_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
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hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH1_Rx_Control2,The Channel1 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH1_Interrupt_Enable,The Channel1 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
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bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
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bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
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bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
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bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
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bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
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rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
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bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
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bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH1_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x31C4++0x3
line.long 0x0 "DMA_CH1_Current_App_TxDesc_L,The Channel1 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x31CC++0x13
line.long 0x0 "DMA_CH1_Current_App_RxDesc_L,The Channel1 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH1_Current_App_TxBuffer_H,The Channel1 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH1_Current_App_TxBuffer_L,The Channel1 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH1_Current_App_RxBuffer_H,The Channel1 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH1_Current_App_RxBuffer_L,The Channel1 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x31E0++0x3
line.long 0x0 "DMA_CH1_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x31E4++0x1B
line.long 0x0 "DMA_CH1_Debug_Status,DMA Channe1 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH1_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH1_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH1_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH1_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH1_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH1_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH1_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3200++0x1F
line.long 0x0 "DMA_CH2_Control,The DMA Channel2 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH2_Tx_Control,The DMA Channel2 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH2_Rx_Control,The DMA Channel2 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel2 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH2_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH2_TxDesc_List_HAddress,The Channel2 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH2_TxDesc_List_LAddress,The Channel2 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH2_RxDesc_List_HAddress,The Channel2 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH2_RxDesc_List_LAddress,The Channel2 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3224++0x3
line.long 0x0 "DMA_CH2_TxDesc_Tail_LPointer,The Channel2 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x322C++0x13
line.long 0x0 "DMA_CH2_RxDesc_Tail_LPointer,The Channel2 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH2_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH2_Rx_Control2,The Channel2 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH2_Interrupt_Enable,The Channel2 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH2_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3244++0x3
line.long 0x0 "DMA_CH2_Current_App_TxDesc_L,The Channel2 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x324C++0x13
line.long 0x0 "DMA_CH2_Current_App_RxDesc_L,The Channel2 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH2_Current_App_TxBuffer_H,The Channel2 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH2_Current_App_TxBuffer_L,The Channel2 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH2_Current_App_RxBuffer_H,The Channel2 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH2_Current_App_RxBuffer_L,The Channel2 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3260++0x3
line.long 0x0 "DMA_CH2_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3264++0x1B
line.long 0x0 "DMA_CH2_Debug_Status,DMA Channe2 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH2_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH2_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH2_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH2_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH2_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH2_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH2_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3280++0x1F
line.long 0x0 "DMA_CH3_Control,The DMA Channel3 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "MSS,Maximum Segment Size."
line.long 0x4 "DMA_CH3_Tx_Control,The DMA Channel3 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
bitfld.long 0x4 12. "TSE,TCP Segmentation Enabled." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH3_Rx_Control,The DMA Channel3 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel3 Packet Flush." "0,1"
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rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
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rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH3_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
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hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
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bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH3_TxDesc_List_HAddress,The Channel3 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH3_TxDesc_List_LAddress,The Channel3 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
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rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH3_RxDesc_List_HAddress,The Channel3 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH3_RxDesc_List_LAddress,The Channel3 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x32A4++0x3
line.long 0x0 "DMA_CH3_TxDesc_Tail_LPointer,The Channel3 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x32AC++0x13
line.long 0x0 "DMA_CH3_RxDesc_Tail_LPointer,The Channel3 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH3_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
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bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
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hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH3_Rx_Control2,The Channel3 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
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bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
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rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
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hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH3_Interrupt_Enable,The Channel3 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
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bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
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bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH3_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
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hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x32C4++0x3
line.long 0x0 "DMA_CH3_Current_App_TxDesc_L,The Channel3 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x32CC++0x13
line.long 0x0 "DMA_CH3_Current_App_RxDesc_L,The Channel3 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH3_Current_App_TxBuffer_H,The Channel3 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
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hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH3_Current_App_TxBuffer_L,The Channel3 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH3_Current_App_RxBuffer_H,The Channel3 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH3_Current_App_RxBuffer_L,The Channel3 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x32E0++0x3
line.long 0x0 "DMA_CH3_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x32E4++0x1B
line.long 0x0 "DMA_CH3_Debug_Status,DMA Channe3 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
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bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH3_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
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hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH3_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH3_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH3_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH3_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH3_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH3_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3300++0x1F
line.long 0x0 "DMA_CH4_Control,The DMA Channel4 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH4_Tx_Control,The DMA Channel4 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH4_Rx_Control,The DMA Channel4 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel4 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH4_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH4_TxDesc_List_HAddress,The Channel4 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH4_TxDesc_List_LAddress,The Channel4 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH4_RxDesc_List_HAddress,The Channel4 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH4_RxDesc_List_LAddress,The Channel4 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3324++0x3
line.long 0x0 "DMA_CH4_TxDesc_Tail_LPointer,The Channel4 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x332C++0x13
line.long 0x0 "DMA_CH4_RxDesc_Tail_LPointer,The Channel4 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH4_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH4_Rx_Control2,The Channel4 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH4_Interrupt_Enable,The Channel4 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH4_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3344++0x3
line.long 0x0 "DMA_CH4_Current_App_TxDesc_L,The Channel4 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x334C++0x13
line.long 0x0 "DMA_CH4_Current_App_RxDesc_L,The Channel4 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH4_Current_App_TxBuffer_H,The Channel4 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH4_Current_App_TxBuffer_L,The Channel4 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH4_Current_App_RxBuffer_H,The Channel4 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH4_Current_App_RxBuffer_L,The Channel4 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3360++0x3
line.long 0x0 "DMA_CH4_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3364++0x1B
line.long 0x0 "DMA_CH4_Debug_Status,DMA Channe4 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH4_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH4_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH4_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH4_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH4_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH4_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH4_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3380++0x1F
line.long 0x0 "DMA_CH5_Control,The DMA Channel5 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH5_Tx_Control,The DMA Channel5 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
rbitfld.long 0x4 28. "Reserved_EDSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH5_Rx_Control,The DMA Channel5 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel5 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH5_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH5_TxDesc_List_HAddress,The Channel5 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH5_TxDesc_List_LAddress,The Channel5 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH5_RxDesc_List_HAddress,The Channel5 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH5_RxDesc_List_LAddress,The Channel5 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x33A4++0x3
line.long 0x0 "DMA_CH5_TxDesc_Tail_LPointer,The Channel5 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x33AC++0x13
line.long 0x0 "DMA_CH5_RxDesc_Tail_LPointer,The Channel5 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH5_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH5_Rx_Control2,The Channel5 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH5_Interrupt_Enable,The Channel5 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH5_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x33C4++0x3
line.long 0x0 "DMA_CH5_Current_App_TxDesc_L,The Channel5 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x33CC++0x13
line.long 0x0 "DMA_CH5_Current_App_RxDesc_L,The Channel5 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH5_Current_App_TxBuffer_H,The Channel5 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH5_Current_App_TxBuffer_L,The Channel5 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH5_Current_App_RxBuffer_H,The Channel5 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH5_Current_App_RxBuffer_L,The Channel5 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x33E0++0x3
line.long 0x0 "DMA_CH5_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x33E4++0x1B
line.long 0x0 "DMA_CH5_Debug_Status,DMA Channe5 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH5_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
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hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH5_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH5_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH5_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH5_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH5_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH5_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3400++0x1F
line.long 0x0 "DMA_CH6_Control,The DMA Channel6 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
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bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
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rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
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hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH6_Tx_Control,The DMA Channel6 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
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hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH6_Rx_Control,The DMA Channel6 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel6 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH6_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
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bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
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bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH6_TxDesc_List_HAddress,The Channel6 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH6_TxDesc_List_LAddress,The Channel6 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH6_RxDesc_List_HAddress,The Channel6 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH6_RxDesc_List_LAddress,The Channel6 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x3424++0x3
line.long 0x0 "DMA_CH6_TxDesc_Tail_LPointer,The Channel6 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x342C++0x13
line.long 0x0 "DMA_CH6_RxDesc_Tail_LPointer,The Channel6 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH6_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
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hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH6_Rx_Control2,The Channel6 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH6_Interrupt_Enable,The Channel6 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH6_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x3444++0x3
line.long 0x0 "DMA_CH6_Current_App_TxDesc_L,The Channel6 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x344C++0x13
line.long 0x0 "DMA_CH6_Current_App_RxDesc_L,The Channel6 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH6_Current_App_TxBuffer_H,The Channel6 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH6_Current_App_TxBuffer_L,The Channel6 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH6_Current_App_RxBuffer_H,The Channel6 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH6_Current_App_RxBuffer_L,The Channel6 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x3460++0x3
line.long 0x0 "DMA_CH6_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x3464++0x1B
line.long 0x0 "DMA_CH6_Debug_Status,DMA Channe6 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH6_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH6_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH6_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH6_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH6_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH6_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH6_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
group.long 0x3480++0x1F
line.long 0x0 "DMA_CH7_Control,The DMA Channel7 Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_31_25,Reserved."
newline
bitfld.long 0x0 24. "SPH,Header-Payload Split." "0,1"
newline
rbitfld.long 0x0 21.--23. "Reserved_23_21,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x0 17. "Reserved_17,Reserved." "0,1"
newline
bitfld.long 0x0 16. "PBLx8,8xPBL mode." "0,1"
newline
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
hexmask.long.word 0x0 0.--13. 1. "Reserved_MSS,Reserved."
line.long 0x4 "DMA_CH7_Tx_Control,The DMA Channel7 Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights."
rbitfld.long 0x4 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x4 29.--30. "TFSEL,TBS Fetch Time Select." "0,1,2,3"
newline
bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable." "0,1"
newline
hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS."
newline
rbitfld.long 0x4 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x4 16.--21. 1. "TxPBL,Transmit Programmable Burst Length."
newline
rbitfld.long 0x4 15. "Reserved_IPBL,Reserved." "0,1"
newline
rbitfld.long 0x4 13.--14. "Reserved_14_13,Reserved." "0,1,2,3"
newline
rbitfld.long 0x4 12. "Reserved_TSE,Reserved." "0,1"
newline
hexmask.long.byte 0x4 5.--11. 1. "Reserved_11_5,Reserved."
newline
rbitfld.long 0x4 4. "Reserved_OSP,Reserved." "0,1"
newline
rbitfld.long 0x4 1.--3. "Reserved_3_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "ST,Start or Stop Transmission Command." "0,1"
line.long 0x8 "DMA_CH7_Rx_Control,The DMA Channel7 Receive Control register controls the Rx features such as PBL. buffer size. and extended status."
bitfld.long 0x8 31. "RPF,Rx DMA Channel7 Packet Flush." "0,1"
newline
rbitfld.long 0x8 28.--30. "Reserved_30_28,Reserved." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 24.--27. 1. "RQOS,Receive QOS."
newline
rbitfld.long 0x8 22.--23. "Reserved_23_22,Reserved." "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "RxPBL,Receive Programmable Burst Length."
newline
rbitfld.long 0x8 15. "Reserved_15,Reserved." "0,1"
newline
hexmask.long.word 0x8 4.--14. 1. "RBSZ,Receive Buffer size."
newline
rbitfld.long 0x8 1.--3. "Reserved_x_1,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 0. "SR,Start or Stop Receive." "0: Rx DMA operation is stopped after the transfer..,1: DMA tries to acquire the descriptor from the.."
line.long 0xC "DMA_CH7_Slot_Function_Control_Status,This register contains the control bits for slot function and its status for Transmit path."
hexmask.long.word 0xC 20.--31. 1. "Reserved_31_20,Reserved"
newline
hexmask.long.byte 0xC 16.--19. 1. "RSN,Reference Slot Number"
newline
hexmask.long.word 0xC 2.--15. 1. "Reserved_15_2,Reserved"
newline
bitfld.long 0xC 1. "ASC,Advance Slot Check" "0,1"
newline
bitfld.long 0xC 0. "ESC,Enable Slot Comparison" "0,1"
line.long 0x10 "DMA_CH7_TxDesc_List_HAddress,The Channel7 Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "TDESHA,Start of Transmit List."
line.long 0x14 "DMA_CH7_TxDesc_List_LAddress,The Channel7 Tx Descriptor List LAddress register has the lower 32 bits of the start address of the Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Dword. or.."
hexmask.long 0x14 3.--31. 1. "TDESLA,Start of Transmit List."
newline
rbitfld.long 0x14 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x18 "DMA_CH7_RxDesc_List_HAddress,The Channel7 Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. This register is present only when DWC_xgmac is configured for 40-bit or 48-bit addressing mode."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x18 0.--7. 1. "RDESHA,Start of Receive List."
line.long 0x1C "DMA_CH7_RxDesc_List_LAddress,The Channel7 Rx Descriptor List LAddress register has the lower 32 bits of the start address of the Receive descriptor list."
hexmask.long 0x1C 3.--31. 1. "RDESLA,Start of Receive List."
newline
rbitfld.long 0x1C 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x34A4++0x3
line.long 0x0 "DMA_CH7_TxDesc_Tail_LPointer,The Channel7 Tx Descriptor Tail LPointer register has the 32 bits end address of the Transmit descriptor list."
hexmask.long 0x0 3.--31. 1. "TDT,Transmit Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
group.long 0x34AC++0x13
line.long 0x0 "DMA_CH7_RxDesc_Tail_LPointer,The Channel7 Rx Descriptor Tail LPointer register has the 32 bits end address of the Receive descriptor list."
hexmask.long 0x0 3.--31. 1. "RDT,Receive Descriptor Tail Pointer."
newline
rbitfld.long 0x0 0.--2. "Reserved_x_0,Reserved." "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH7_Tx_Control2,The Tx_Control2 register contains programmable control to Outstanding read requests per DMA and the length of the Transmit descriptor ring."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x4 24.--25. "ORRQ,Read Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x4 16.--23. 1. "Reserved_23_12,Reserved."
newline
hexmask.long.word 0x4 0.--15. 1. "TDRL,Transmit Descriptor Ring Length."
line.long 0x8 "DMA_CH7_Rx_Control2,The Channel7 Rx Control2 register contains programmable control to Outstanding Write requests and the length of the Receive descriptor circular ring."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_31_y,Reserved."
newline
bitfld.long 0x8 24.--25. "OWRQ,Write Outstanding Requests" "?,?,2: Upto Bit 25 is Reserved,?"
newline
hexmask.long.byte 0x8 17.--23. 1. "ARBS,Alternate Receive Buffer Size"
newline
rbitfld.long 0x8 16. "Reserved_x_16,Reserved." "0,1"
newline
hexmask.long.word 0x8 0.--15. 1. "RDRL,Receive Descriptor Ring Length."
line.long 0xC "DMA_CH7_Interrupt_Enable,The Channel7 Interrupt Enable register enables the interrupts reported by the Status register."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable." "0: Transmit Interrupt,?"
newline
bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable." "?,1: Transmit Process Stopped"
newline
bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable." "0,1"
newline
bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable." "0,1"
newline
rbitfld.long 0xC 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0xC 9. "DDEE,Descriptor Definition Error Enable." "0,1"
newline
bitfld.long 0xC 8. "RSE,Receive Stopped Enable." "0,1"
newline
bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 6. "RIE,Receive Interrupt Enable." "0,1"
newline
rbitfld.long 0xC 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable." "0,1"
newline
bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable." "0,1"
newline
bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable." "0,1"
line.long 0x10 "DMA_CH7_Rx_Interrupt_Watchdog_Timer,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. This can in terms of number of clock cycles (RWT field) or number of transferred bytes or number of.."
bitfld.long 0x10 31. "PSEL,Packet Count Interrupt Select." "0: RBCT field is used to generate interrupt based..,1: RBCT field is used to generate interrupt based.."
newline
hexmask.long.byte 0x10 26.--30. 1. "Reserved_30_26,Reserved."
newline
hexmask.long.word 0x10 16.--25. 1. "RBCT,Receive Byte Count Threshold."
newline
rbitfld.long 0x10 14.--15. "Reserved_15_14,Reserved." "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "RWTU,Receive Interrupt Watchdog Timer Count Units." "0: 256,1: 512,2: 1024,3: 2048"
newline
hexmask.long.byte 0x10 8.--11. 1. "Reserved_11_8,Reserved."
newline
hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count."
rgroup.long 0x34C4++0x3
line.long 0x0 "DMA_CH7_Current_App_TxDesc_L,The Channel7 Current Application Transmit Descriptor High register has the lower 32 bits of the current address of the Transmit descriptor read by the DMA. The upper 32 address bits of the Current Transmit Descriptor are.."
hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer."
rgroup.long 0x34CC++0x13
line.long 0x0 "DMA_CH7_Current_App_RxDesc_L,The Channel7 Current Application Receive Descriptor Low register has the lower 32 bits of the current address of the Receive descriptor read by the DMA. The upper 32 address bits of the Current Receive Descriptor are equal to.."
hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer."
line.long 0x4 "DMA_CH7_Current_App_TxBuffer_H,The Channel7 Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x8 "DMA_CH7_Current_App_TxBuffer_L,The Channel7 Current Application Transmit Buffer Address Low register has the lower 32 bits of the current address of the Transmit buffer address read by the DMA."
hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer."
line.long 0xC "DMA_CH7_Current_App_RxBuffer_H,The Channel7 Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA. This register is present only when DWC_xgmac is.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer."
line.long 0x10 "DMA_CH7_Current_App_RxBuffer_L,The Channel7 Current Application Receive Buffer Address Low register has the lower 32 bits of the current address of the Receive buffer address read by the DMA."
hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer."
group.long 0x34E0++0x3
line.long 0x0 "DMA_CH7_Status,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA."
hexmask.long.word 0x0 22.--31. 1. "Reserved_31_22,Reserved."
newline
bitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits." "0: Error during write transfer,1: Error during read transfer,?,?,?,?,?,?"
newline
bitfld.long 0x0 15. "NIS,Normal Interrupt Summary." "0: Transmit Interrupt,?"
newline
bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary." "?,1: Transmit Process Stopped"
newline
bitfld.long 0x0 13. "CDE,Context Descriptor Error." "0,1"
newline
bitfld.long 0x0 12. "FBE,Fatal Bus Error." "0,1"
newline
rbitfld.long 0x0 10.--11. "Reserved_11_10,Reserved." "0,1,2,3"
newline
bitfld.long 0x0 9. "DDE,Descriptor Definition Error." "0,1"
newline
bitfld.long 0x0 8. "RPS,Receive Process Stopped." "0,1"
newline
bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 6. "RI,Receive Interrupt." "0,1"
newline
rbitfld.long 0x0 3.--5. "Reserved_5_3,Reserved." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable." "0,1"
newline
bitfld.long 0x0 1. "TPS,Transmit Process Stopped." "0,1"
newline
bitfld.long 0x0 0. "TI,Transmit Interrupt." "0,1"
rgroup.long 0x34E4++0x1B
line.long 0x0 "DMA_CH7_Debug_Status,DMA Channe7 Debug Status register"
bitfld.long 0x0 31. "Reserved_31,Reserved." "0,1"
newline
bitfld.long 0x0 28.--30. "RDWS,RxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 19.--27. 1. "RDTS,RxDMA Data Transfer FSM State"
newline
bitfld.long 0x0 16.--18. "RDFS,RxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15. "Reserved_15,Reserved." "0,1"
newline
bitfld.long 0x0 12.--14. "TDWS,TxDMA Descriptor Write FSM state" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 8.--11. 1. "TDTS,TxDMA Data Transfer Control Module FSM State"
newline
bitfld.long 0x0 6.--7. "TDRS,TxDMA Data Request FSM State" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "TDXS,TxDMA Data Transfer FSM State" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "TDFS,TxDMA Descriptor Fetch FSM State" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMA_CH7_Desc_Mem_Cache_Fill_Level,The DMA Channel0 Descriptor Cache Fill Level Status register."
hexmask.long.word 0x4 23.--31. 1. "Reserved_31_y,Reserved."
newline
hexmask.long.byte 0x4 16.--22. 1. "RX_FILL_LVL,RxDMA Descriptor Cache Fill Level"
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_15_y,Reserved."
newline
hexmask.long.byte 0x4 0.--6. 1. "TX_FILL_LVL,TxDMA Descriptor Cache Fill Level"
line.long 0x8 "DMA_CH7_Miss_Packet_Cnt,This register has the number of the packets that are dropped by the DMA either due to Bus Error or due to programming the RPF field in the DMA_CH7_Rx_Control register."
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved."
newline
bitfld.long 0x8 15. "MFCO,Overflow status of MFC Counter" "0,1"
newline
hexmask.long.byte 0x8 11.--14. 1. "Reserved_14_11,Reserved."
newline
hexmask.long.word 0x8 0.--10. 1. "MFC,Missed Packet Counter"
line.long 0xC "DMA_CH7_Tx_Data_Xfer_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is fetching the data."
hexmask.long.word 0xC 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0xC 0.--15. 1. "DESC_OFFSET,TxDMA channel0 Data Transfer ring Offset"
line.long 0x10 "DMA_CH7_Rx_Data_Xfer_Ring_Offset,The DMA Channel0 Receive Data Transfer Ring Offset register indicates the Ring Offset of the Rx Descriptor List. for which the DMA engine is transferring the data."
hexmask.long.word 0x10 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x10 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Data Transfer Ring Offset"
line.long 0x14 "DMA_CH7_Tx_Desc_Write_Ring_Offset,This register indicates the Offset of the Tx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x14 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x14 0.--15. 1. "DESC_OFFSET,TxDMA Channel0 Descriptor Write Ring Offset"
line.long 0x18 "DMA_CH7_Rx_Desc_Write_Ring_Offset,This register indicates the Offset of the Rx Descriptor List. for which the DMA engine is closing the descriptor."
hexmask.long.word 0x18 16.--31. 1. "Reserved_31_12,Reserved."
newline
hexmask.long.word 0x18 0.--15. 1. "DESC_OFFSET,RxDMA Channel0 Descriptor Write Ring Offset"
tree.end
tree.end
tree "GIC (Generic Interrupt Controller)"
base ad:0x1D000000
group.long 0x0++0x3
line.long 0x0 "GICD_CTLR,GICD_CTLR"
rbitfld.long 0x0 31. "RWP,RWP" "0,1"
hexmask.long.tbyte 0x0 8.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0x0 7. "E1NWF,E1NWF" "0,1"
rbitfld.long 0x0 6. "DS,DS" "0,1"
newline
bitfld.long 0x0 5. "ARE_NS,ARE_NS" "0,1"
bitfld.long 0x0 4. "ARE_S,ARE_S" "0,1"
newline
bitfld.long 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x0 2. "EnableGrp1_s,EnableGrp1_s" "0,1"
newline
bitfld.long 0x0 1. "EnableGrp1_ns,EnableGrp1_ns" "0,1"
bitfld.long 0x0 0. "EnableGrp0,EnableGrp0" "0,1"
rgroup.long 0x4++0x7
line.long 0x0 "GICD_TYPER,GICD_TYPER"
hexmask.long.byte 0x0 26.--31. 1. "RESERVED1,RESERVED1"
bitfld.long 0x0 25. "No1N,No1N" "0,1"
newline
bitfld.long 0x0 24. "A3V,A3V" "0,1"
hexmask.long.byte 0x0 19.--23. 1. "IDbits,IDbits"
newline
bitfld.long 0x0 18. "DVIS,DVIS" "0,1"
bitfld.long 0x0 17. "LPIS,LPIS" "0,1"
newline
bitfld.long 0x0 16. "MBIS,MBIS" "0,1"
hexmask.long.byte 0x0 11.--15. 1. "LSPI,LSPI"
newline
bitfld.long 0x0 10. "SecurityExtn,SecurityExtn" "0,1"
bitfld.long 0x0 8.--9. "RESERVED0,RESERVED0" "0,1,2,3"
newline
bitfld.long 0x0 5.--7. "CPUNumber,CPUNumber" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--4. 1. "ITLinesNumber,ITLinesNumber"
line.long 0x4 "GICD_IIDR,GICD_IIDR"
hexmask.long.byte 0x4 24.--31. 1. "ProductID,ProductID"
hexmask.long.byte 0x4 20.--23. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x4 16.--19. 1. "Variant,Variant"
hexmask.long.byte 0x4 12.--15. 1. "Revision,Revision"
newline
hexmask.long.word 0x4 0.--11. 1. "Implementer,Implementer"
group.long 0x20++0x7
line.long 0x0 "GICD_FCTLR,GICD_FCTLR"
hexmask.long.byte 0x0 27.--31. 1. "RESERVED4,RESERVED4"
bitfld.long 0x0 26. "POS,POS" "0,1"
newline
bitfld.long 0x0 25. "QDENY,QDENY" "0,1"
bitfld.long 0x0 22.--24. "RESERVED3,RESERVED3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 21. "DCC,DCC" "0,1"
bitfld.long 0x0 18.--20. "RESERVED2,RESERVED2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16.--17. "NSACR,NSACR" "0,1,2,3"
bitfld.long 0x0 13.--15. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 4.--12. 1. "CGO,CGO"
bitfld.long 0x0 1.--3. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "SIP,SIP" "0,1"
line.long 0x4 "GICD_SAC,GICD_SAC"
hexmask.long 0x4 3.--31. 1. "RESERVED0,RESERVED0"
bitfld.long 0x4 2. "GICPNS,GICPNS" "0,1"
newline
bitfld.long 0x4 1. "GICTNS,GICTNS" "0,1"
bitfld.long 0x4 0. "DSL,DSL" "0,1"
wgroup.long 0x40++0x3
line.long 0x0 "GICD_SETSPI_NSR,GICD_SETSPI_NSR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
wgroup.long 0x48++0x3
line.long 0x0 "GICD_CLRSPI_NSR,GICD_CLRSPI_NSR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
wgroup.long 0x50++0x3
line.long 0x0 "GICD_SETSPI_SR,GICD_SETSPI_SR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
wgroup.long 0x58++0x3
line.long 0x0 "GICD_CLRSPI_SR,GICD_CLRSPI_SR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
group.long 0x84++0x43
line.long 0x0 "GICD_IGROUPR1,GICD_IGROUPR1"
bitfld.long 0x0 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x0 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x0 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x0 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x0 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x0 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x0 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x0 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x0 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x0 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x0 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x0 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x0 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x0 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x0 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x0 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x0 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x4 "GICD_IGROUPR2,GICD_IGROUPR2"
bitfld.long 0x4 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x4 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x4 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x4 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x4 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x4 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x4 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x4 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x4 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x4 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x4 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x4 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x4 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x4 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x4 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x4 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x4 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x4 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x4 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x4 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x4 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x4 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x4 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x4 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x4 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x4 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x4 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x4 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x4 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x4 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x4 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x4 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x8 "GICD_IGROUPR3,GICD_IGROUPR3"
bitfld.long 0x8 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x8 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x8 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x8 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x8 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x8 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x8 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x8 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x8 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x8 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x8 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x8 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x8 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x8 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x8 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x8 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x8 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x8 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x8 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x8 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x8 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x8 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x8 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x8 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x8 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x8 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x8 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x8 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x8 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x8 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x8 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x8 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0xC "GICD_IGROUPR4,GICD_IGROUPR4"
bitfld.long 0xC 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0xC 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0xC 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0xC 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0xC 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0xC 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0xC 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0xC 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0xC 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0xC 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0xC 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0xC 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0xC 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0xC 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0xC 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0xC 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0xC 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0xC 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0xC 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0xC 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0xC 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0xC 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0xC 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0xC 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0xC 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0xC 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0xC 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0xC 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0xC 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0xC 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0xC 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0xC 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x10 "GICD_IGROUPR5,GICD_IGROUPR5"
bitfld.long 0x10 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x10 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x10 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x10 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x10 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x10 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x10 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x10 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x10 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x10 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x10 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x10 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x10 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x10 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x10 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x10 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x10 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x10 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x10 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x10 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x10 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x10 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x10 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x10 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x10 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x10 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x10 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x10 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x10 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x10 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x10 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x10 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x14 "GICD_IGROUPR6,GICD_IGROUPR6"
bitfld.long 0x14 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x14 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x14 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x14 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x14 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x14 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x14 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x14 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x14 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x14 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x14 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x14 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x14 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x14 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x14 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x14 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x14 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x14 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x14 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x14 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x14 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x14 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x14 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x14 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x14 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x14 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x14 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x14 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x14 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x14 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x14 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x14 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x18 "GICD_IGROUPR7,GICD_IGROUPR7"
bitfld.long 0x18 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x18 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x18 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x18 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x18 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x18 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x18 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x18 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x18 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x18 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x18 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x18 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x18 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x18 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x18 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x18 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x18 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x18 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x18 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x18 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x18 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x18 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x18 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x18 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x18 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x18 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x18 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x18 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x18 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x18 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x18 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x18 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x1C "GICD_IGROUPR8,GICD_IGROUPR8"
bitfld.long 0x1C 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x1C 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x1C 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x1C 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x1C 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x1C 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x1C 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x1C 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x1C 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x1C 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x1C 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x1C 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x1C 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x1C 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x1C 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x1C 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x1C 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x1C 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x1C 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x1C 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x1C 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x1C 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x1C 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x1C 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x1C 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x1C 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x1C 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x1C 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x1C 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x1C 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x1C 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x1C 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x20 "GICD_IGROUPR9,GICD_IGROUPR9"
bitfld.long 0x20 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x20 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x20 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x20 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x20 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x20 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x20 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x20 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x20 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x20 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x20 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x20 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x20 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x20 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x20 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x20 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x20 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x20 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x20 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x20 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x20 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x20 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x20 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x20 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x20 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x20 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x20 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x20 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x20 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x20 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x20 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x20 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x24 "GICD_IGROUPR10,GICD_IGROUPR10"
bitfld.long 0x24 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x24 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x24 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x24 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x24 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x24 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x24 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x24 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x24 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x24 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x24 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x24 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x24 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x24 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x24 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x24 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x24 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x24 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x24 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x24 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x24 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x24 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x24 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x24 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x24 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x24 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x24 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x24 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x24 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x24 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x24 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x24 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x28 "GICD_IGROUPR11,GICD_IGROUPR11"
bitfld.long 0x28 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x28 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x28 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x28 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x28 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x28 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x28 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x28 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x28 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x28 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x28 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x28 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x28 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x28 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x28 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x28 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x28 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x28 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x28 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x28 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x28 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x28 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x28 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x28 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x28 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x28 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x28 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x28 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x28 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x28 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x28 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x28 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x2C "GICD_IGROUPR12,GICD_IGROUPR12"
bitfld.long 0x2C 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x2C 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x2C 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x2C 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x2C 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x2C 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x2C 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x2C 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x2C 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x2C 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x2C 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x2C 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x2C 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x2C 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x2C 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x2C 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x2C 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x2C 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x2C 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x2C 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x2C 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x2C 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x2C 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x2C 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x2C 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x2C 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x2C 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x2C 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x2C 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x2C 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x2C 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x2C 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x30 "GICD_IGROUPR13,GICD_IGROUPR13"
bitfld.long 0x30 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x30 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x30 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x30 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x30 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x30 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x30 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x30 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x30 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x30 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x30 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x30 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x30 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x30 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x30 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x30 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x30 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x30 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x30 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x30 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x30 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x30 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x30 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x30 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x30 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x30 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x30 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x30 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x30 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x30 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x30 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x30 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x34 "GICD_IGROUPR14,GICD_IGROUPR14"
bitfld.long 0x34 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x34 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x34 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x34 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x34 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x34 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x34 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x34 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x34 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x34 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x34 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x34 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x34 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x34 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x34 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x34 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x34 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x34 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x34 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x34 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x34 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x34 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x34 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x34 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x34 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x34 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x34 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x34 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x34 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x34 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x34 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x34 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x38 "GICD_IGROUPR15,GICD_IGROUPR15"
bitfld.long 0x38 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x38 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x38 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x38 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x38 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x38 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x38 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x38 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x38 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x38 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x38 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x38 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x38 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x38 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x38 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x38 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x38 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x38 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x38 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x38 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x38 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x38 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x38 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x38 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x38 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x38 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x38 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x38 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x38 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x38 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x38 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x38 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x3C "GICD_IGROUPR16,GICD_IGROUPR16"
bitfld.long 0x3C 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x3C 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x3C 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x3C 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x3C 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x3C 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x3C 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x3C 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x3C 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x3C 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x3C 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x3C 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x3C 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x3C 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x3C 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x3C 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x3C 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x3C 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x3C 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x3C 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x3C 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x3C 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x3C 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x3C 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x3C 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x3C 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x3C 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x3C 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x3C 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x3C 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x3C 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x3C 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x40 "GICD_IGROUPR17,GICD_IGROUPR17"
bitfld.long 0x40 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x40 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x40 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x40 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x40 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x40 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x40 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x40 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x40 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x40 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x40 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x40 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x40 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x40 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x40 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x40 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x40 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x40 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x40 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x40 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x40 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x40 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x40 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x40 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x40 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x40 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x40 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x40 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x40 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x40 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x40 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x40 0. "group_status_bit0,group_status_bit0" "0,1"
group.long 0x104++0x43
line.long 0x0 "GICD_ISENABLER1,GICD_ISENABLER1"
bitfld.long 0x0 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x0 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x0 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x0 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x0 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x0 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x0 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x0 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x0 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x0 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x0 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x0 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x0 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x0 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x0 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x0 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x0 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x4 "GICD_ISENABLER2,GICD_ISENABLER2"
bitfld.long 0x4 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x4 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x4 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x4 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x4 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x4 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x4 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x4 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x4 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x4 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x4 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x4 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x4 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x4 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x4 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x4 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x4 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x4 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x4 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x4 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x4 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x4 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x4 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x4 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x4 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x4 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x4 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x4 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x4 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x4 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x4 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x4 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x8 "GICD_ISENABLER3,GICD_ISENABLER3"
bitfld.long 0x8 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x8 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x8 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x8 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x8 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x8 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x8 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x8 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x8 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x8 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x8 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x8 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x8 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x8 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x8 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x8 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x8 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x8 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x8 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x8 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x8 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x8 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x8 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x8 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x8 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x8 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x8 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x8 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x8 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x8 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x8 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x8 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0xC "GICD_ISENABLER4,GICD_ISENABLER4"
bitfld.long 0xC 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0xC 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0xC 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0xC 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0xC 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0xC 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0xC 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0xC 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0xC 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0xC 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0xC 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0xC 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0xC 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0xC 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0xC 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0xC 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0xC 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0xC 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0xC 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0xC 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0xC 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0xC 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0xC 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0xC 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0xC 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0xC 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0xC 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0xC 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0xC 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0xC 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0xC 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0xC 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x10 "GICD_ISENABLER5,GICD_ISENABLER5"
bitfld.long 0x10 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x10 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x10 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x10 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x10 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x10 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x10 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x10 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x10 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x10 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x10 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x10 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x10 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x10 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x10 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x10 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x10 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x10 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x10 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x10 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x10 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x10 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x10 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x10 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x10 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x10 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x10 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x10 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x10 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x10 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x10 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x10 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x14 "GICD_ISENABLER6,GICD_ISENABLER6"
bitfld.long 0x14 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x14 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x14 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x14 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x14 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x14 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x14 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x14 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x14 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x14 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x14 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x14 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x14 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x14 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x14 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x14 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x14 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x14 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x14 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x14 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x14 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x14 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x14 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x14 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x14 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x14 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x14 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x14 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x14 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x14 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x14 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x14 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x18 "GICD_ISENABLER7,GICD_ISENABLER7"
bitfld.long 0x18 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x18 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x18 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x18 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x18 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x18 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x18 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x18 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x18 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x18 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x18 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x18 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x18 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x18 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x18 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x18 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x18 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x18 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x18 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x18 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x18 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x18 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x18 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x18 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x18 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x18 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x18 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x18 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x18 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x18 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x18 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x18 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x1C "GICD_ISENABLER8,GICD_ISENABLER8"
bitfld.long 0x1C 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x1C 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x1C 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x1C 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x1C 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x1C 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x1C 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x1C 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x1C 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x1C 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x1C 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x1C 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x1C 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x1C 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x1C 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x1C 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x1C 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x1C 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x1C 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x1C 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x1C 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x1C 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x1C 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x1C 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x1C 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x1C 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x1C 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x1C 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x1C 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x1C 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x1C 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x1C 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x20 "GICD_ISENABLER9,GICD_ISENABLER9"
bitfld.long 0x20 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x20 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x20 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x20 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x20 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x20 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x20 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x20 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x20 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x20 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x20 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x20 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x20 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x20 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x20 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x20 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x20 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x20 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x20 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x20 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x20 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x20 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x20 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x20 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x20 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x20 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x20 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x20 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x20 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x20 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x20 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x20 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x24 "GICD_ISENABLER10,GICD_ISENABLER10"
bitfld.long 0x24 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x24 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x24 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x24 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x24 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x24 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x24 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x24 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x24 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x24 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x24 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x24 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x24 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x24 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x24 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x24 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x24 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x24 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x24 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x24 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x24 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x24 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x24 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x24 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x24 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x24 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x24 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x24 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x24 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x24 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x24 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x24 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x28 "GICD_ISENABLER11,GICD_ISENABLER11"
bitfld.long 0x28 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x28 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x28 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x28 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x28 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x28 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x28 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x28 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x28 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x28 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x28 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x28 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x28 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x28 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x28 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x28 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x28 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x28 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x28 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x28 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x28 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x28 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x28 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x28 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x28 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x28 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x28 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x28 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x28 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x28 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x28 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x28 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x2C "GICD_ISENABLER12,GICD_ISENABLER12"
bitfld.long 0x2C 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x2C 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x2C 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x2C 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x2C 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x2C 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x2C 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x2C 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x2C 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x2C 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x2C 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x2C 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x2C 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x2C 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x2C 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x2C 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x2C 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x2C 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x2C 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x2C 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x2C 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x2C 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x2C 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x2C 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x2C 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x2C 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x2C 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x2C 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x2C 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x2C 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x2C 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x2C 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x30 "GICD_ISENABLER13,GICD_ISENABLER13"
bitfld.long 0x30 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x30 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x30 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x30 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x30 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x30 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x30 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x30 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x30 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x30 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x30 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x30 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x30 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x30 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x30 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x30 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x30 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x30 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x30 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x30 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x30 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x30 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x30 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x30 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x30 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x30 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x30 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x30 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x30 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x30 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x30 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x30 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x34 "GICD_ISENABLER14,GICD_ISENABLER14"
bitfld.long 0x34 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x34 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x34 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x34 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x34 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x34 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x34 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x34 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x34 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x34 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x34 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x34 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x34 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x34 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x34 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x34 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x34 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x34 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x34 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x34 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x34 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x34 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x34 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x34 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x34 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x34 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x34 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x34 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x34 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x34 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x34 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x34 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x38 "GICD_ISENABLER15,GICD_ISENABLER15"
bitfld.long 0x38 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x38 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x38 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x38 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x38 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x38 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x38 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x38 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x38 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x38 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x38 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x38 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x38 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x38 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x38 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x38 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x38 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x38 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x38 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x38 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x38 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x38 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x38 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x38 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x38 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x38 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x38 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x38 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x38 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x38 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x38 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x38 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x3C "GICD_ISENABLER16,GICD_ISENABLER16"
bitfld.long 0x3C 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x3C 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x3C 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x3C 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x3C 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x3C 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x3C 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x3C 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x3C 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x3C 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x3C 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x3C 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x3C 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x3C 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x3C 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x3C 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x3C 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x3C 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x3C 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x3C 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x3C 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x3C 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x3C 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x3C 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x3C 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x3C 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x3C 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x3C 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x3C 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x3C 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x3C 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x3C 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x40 "GICD_ISENABLER17,GICD_ISENABLER17"
bitfld.long 0x40 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x40 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x40 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x40 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x40 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x40 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x40 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x40 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x40 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x40 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x40 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x40 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x40 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x40 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x40 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x40 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x40 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x40 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x40 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x40 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x40 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x40 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x40 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x40 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x40 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x40 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x40 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x40 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x40 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x40 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x40 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x40 0. "set_enable_bit0,set_enable_bit0" "0,1"
group.long 0x184++0x43
line.long 0x0 "GICD_ICENABLER1,GICD_ICENABLER1"
bitfld.long 0x0 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x0 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x0 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x0 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x0 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x0 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x0 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x0 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x0 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x0 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x0 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x0 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x0 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x0 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x0 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x0 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x0 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x4 "GICD_ICENABLER2,GICD_ICENABLER2"
bitfld.long 0x4 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x4 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x4 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x4 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x4 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x4 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x4 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x4 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x4 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x4 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x4 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x4 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x4 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x4 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x4 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x4 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x4 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x4 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x4 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x4 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x4 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x4 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x4 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x4 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x4 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x4 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x4 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x4 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x4 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x4 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x4 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x4 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x8 "GICD_ICENABLER3,GICD_ICENABLER3"
bitfld.long 0x8 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x8 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x8 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x8 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x8 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x8 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x8 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x8 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x8 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x8 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x8 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x8 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x8 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x8 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x8 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x8 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x8 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x8 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x8 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x8 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x8 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x8 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x8 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x8 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x8 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x8 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x8 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x8 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x8 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x8 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x8 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x8 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0xC "GICD_ICENABLER4,GICD_ICENABLER4"
bitfld.long 0xC 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0xC 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0xC 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0xC 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0xC 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0xC 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0xC 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0xC 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0xC 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0xC 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0xC 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0xC 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0xC 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0xC 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0xC 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0xC 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0xC 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0xC 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0xC 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0xC 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0xC 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0xC 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0xC 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0xC 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0xC 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0xC 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0xC 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0xC 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0xC 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0xC 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0xC 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0xC 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x10 "GICD_ICENABLER5,GICD_ICENABLER5"
bitfld.long 0x10 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x10 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x10 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x10 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x10 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x10 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x10 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x10 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x10 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x10 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x10 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x10 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x10 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x10 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x10 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x10 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x10 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x10 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x10 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x10 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x10 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x10 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x10 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x10 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x10 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x10 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x10 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x10 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x10 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x10 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x10 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x10 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x14 "GICD_ICENABLER6,GICD_ICENABLER6"
bitfld.long 0x14 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x14 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x14 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x14 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x14 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x14 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x14 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x14 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x14 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x14 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x14 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x14 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x14 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x14 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x14 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x14 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x14 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x14 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x14 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x14 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x14 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x14 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x14 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x14 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x14 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x14 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x14 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x14 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x14 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x14 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x14 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x14 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x18 "GICD_ICENABLER7,GICD_ICENABLER7"
bitfld.long 0x18 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x18 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x18 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x18 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x18 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x18 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x18 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x18 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x18 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x18 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x18 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x18 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x18 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x18 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x18 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x18 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x18 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x18 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x18 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x18 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x18 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x18 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x18 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x18 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x18 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x18 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x18 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x18 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x18 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x18 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x18 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x18 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x1C "GICD_ICENABLER8,GICD_ICENABLER8"
bitfld.long 0x1C 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x1C 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x1C 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x1C 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x1C 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x1C 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x1C 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x1C 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x1C 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x1C 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x1C 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x1C 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x1C 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x1C 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x1C 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x1C 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x1C 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x1C 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x1C 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x1C 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x1C 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x1C 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x1C 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x1C 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x1C 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x1C 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x1C 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x1C 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x1C 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x1C 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x1C 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x1C 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x20 "GICD_ICENABLER9,GICD_ICENABLER9"
bitfld.long 0x20 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x20 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x20 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x20 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x20 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x20 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x20 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x20 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x20 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x20 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x20 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x20 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x20 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x20 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x20 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x20 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x20 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x20 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x20 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x20 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x20 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x20 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x20 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x20 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x20 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x20 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x20 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x20 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x20 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x20 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x20 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x20 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x24 "GICD_ICENABLER10,GICD_ICENABLER10"
bitfld.long 0x24 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x24 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x24 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x24 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x24 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x24 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x24 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x24 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x24 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x24 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x24 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x24 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x24 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x24 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x24 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x24 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x24 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x24 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x24 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x24 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x24 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x24 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x24 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x24 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x24 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x24 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x24 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x24 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x24 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x24 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x24 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x24 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x28 "GICD_ICENABLER11,GICD_ICENABLER11"
bitfld.long 0x28 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x28 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x28 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x28 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x28 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x28 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x28 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x28 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x28 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x28 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x28 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x28 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x28 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x28 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x28 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x28 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x28 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x28 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x28 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x28 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x28 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x28 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x28 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x28 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x28 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x28 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x28 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x28 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x28 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x28 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x28 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x28 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x2C "GICD_ICENABLER12,GICD_ICENABLER12"
bitfld.long 0x2C 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x2C 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x2C 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x2C 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x2C 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x2C 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x2C 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x2C 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x2C 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x2C 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x2C 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x2C 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x2C 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x2C 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x2C 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x2C 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x2C 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x2C 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x2C 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x2C 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x2C 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x2C 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x2C 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x2C 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x2C 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x2C 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x2C 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x2C 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x2C 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x2C 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x2C 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x2C 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x30 "GICD_ICENABLER13,GICD_ICENABLER13"
bitfld.long 0x30 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x30 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x30 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x30 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x30 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x30 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x30 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x30 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x30 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x30 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x30 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x30 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x30 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x30 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x30 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x30 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x30 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x30 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x30 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x30 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x30 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x30 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x30 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x30 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x30 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x30 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x30 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x30 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x30 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x30 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x30 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x30 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x34 "GICD_ICENABLER14,GICD_ICENABLER14"
bitfld.long 0x34 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x34 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x34 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x34 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x34 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x34 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x34 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x34 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x34 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x34 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x34 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x34 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x34 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x34 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x34 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x34 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x34 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x34 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x34 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x34 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x34 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x34 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x34 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x34 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x34 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x34 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x34 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x34 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x34 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x34 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x34 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x34 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x38 "GICD_ICENABLER15,GICD_ICENABLER15"
bitfld.long 0x38 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x38 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x38 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x38 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x38 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x38 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x38 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x38 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x38 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x38 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x38 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x38 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x38 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x38 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x38 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x38 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x38 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x38 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x38 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x38 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x38 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x38 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x38 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x38 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x38 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x38 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x38 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x38 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x38 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x38 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x38 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x38 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x3C "GICD_ICENABLER16,GICD_ICENABLER16"
bitfld.long 0x3C 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x3C 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x3C 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x3C 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x3C 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x3C 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x3C 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x3C 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x3C 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x3C 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x3C 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x3C 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x3C 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x3C 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x3C 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x3C 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x3C 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x3C 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x3C 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x3C 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x3C 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x3C 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x3C 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x3C 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x3C 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x3C 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x3C 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x3C 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x3C 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x3C 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x3C 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x3C 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x40 "GICD_ICENABLER17,GICD_ICENABLER17"
bitfld.long 0x40 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x40 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x40 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x40 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x40 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x40 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x40 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x40 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x40 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x40 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x40 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x40 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x40 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x40 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x40 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x40 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x40 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x40 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x40 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x40 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x40 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x40 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x40 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x40 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x40 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x40 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x40 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x40 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x40 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x40 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x40 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x40 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
group.long 0x204++0x43
line.long 0x0 "GICD_ISPENDR1,GICD_ISPENDR1"
bitfld.long 0x0 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x0 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x0 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x0 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x0 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x0 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x0 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x0 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x0 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x0 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x0 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x0 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x0 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x0 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x0 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x0 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x0 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x4 "GICD_ISPENDR2,GICD_ISPENDR2"
bitfld.long 0x4 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x4 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x4 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x4 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x4 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x4 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x4 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x4 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x4 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x4 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x4 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x4 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x4 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x4 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x4 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x4 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x4 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x4 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x4 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x4 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x4 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x4 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x4 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x4 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x4 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x4 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x4 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x4 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x4 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x4 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x4 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x4 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x8 "GICD_ISPENDR3,GICD_ISPENDR3"
bitfld.long 0x8 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x8 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x8 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x8 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x8 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x8 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x8 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x8 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x8 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x8 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x8 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x8 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x8 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x8 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x8 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x8 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x8 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x8 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x8 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x8 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x8 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x8 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x8 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x8 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x8 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x8 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x8 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x8 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x8 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x8 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x8 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x8 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0xC "GICD_ISPENDR4,GICD_ISPENDR4"
bitfld.long 0xC 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0xC 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0xC 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0xC 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0xC 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0xC 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0xC 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0xC 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0xC 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0xC 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0xC 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0xC 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0xC 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0xC 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0xC 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0xC 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0xC 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0xC 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0xC 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0xC 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0xC 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0xC 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0xC 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0xC 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0xC 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0xC 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0xC 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0xC 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0xC 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0xC 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0xC 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0xC 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x10 "GICD_ISPENDR5,GICD_ISPENDR5"
bitfld.long 0x10 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x10 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x10 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x10 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x10 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x10 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x10 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x10 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x10 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x10 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x10 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x10 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x10 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x10 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x10 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x10 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x10 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x10 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x10 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x10 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x10 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x10 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x10 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x10 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x10 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x10 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x10 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x10 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x10 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x10 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x10 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x10 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x14 "GICD_ISPENDR6,GICD_ISPENDR6"
bitfld.long 0x14 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x14 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x14 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x14 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x14 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x14 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x14 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x14 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x14 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x14 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x14 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x14 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x14 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x14 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x14 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x14 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x14 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x14 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x14 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x14 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x14 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x14 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x14 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x14 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x14 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x14 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x14 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x14 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x14 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x14 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x14 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x14 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x18 "GICD_ISPENDR7,GICD_ISPENDR7"
bitfld.long 0x18 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x18 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x18 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x18 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x18 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x18 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x18 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x18 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x18 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x18 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x18 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x18 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x18 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x18 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x18 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x18 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x18 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x18 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x18 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x18 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x18 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x18 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x18 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x18 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x18 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x18 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x18 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x18 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x18 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x18 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x18 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x18 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x1C "GICD_ISPENDR8,GICD_ISPENDR8"
bitfld.long 0x1C 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x1C 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x1C 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x1C 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x1C 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x1C 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x1C 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x1C 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x1C 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x1C 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x1C 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x1C 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x1C 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x1C 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x1C 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x1C 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x1C 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x1C 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x1C 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x1C 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x1C 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x1C 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x1C 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x1C 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x1C 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x1C 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x1C 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x1C 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x1C 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x1C 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x1C 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x1C 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x20 "GICD_ISPENDR9,GICD_ISPENDR9"
bitfld.long 0x20 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x20 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x20 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x20 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x20 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x20 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x20 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x20 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x20 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x20 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x20 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x20 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x20 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x20 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x20 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x20 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x20 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x20 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x20 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x20 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x20 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x20 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x20 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x20 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x20 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x20 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x20 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x20 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x20 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x20 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x20 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x20 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x24 "GICD_ISPENDR10,GICD_ISPENDR10"
bitfld.long 0x24 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x24 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x24 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x24 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x24 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x24 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x24 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x24 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x24 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x24 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x24 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x24 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x24 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x24 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x24 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x24 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x24 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x24 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x24 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x24 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x24 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x24 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x24 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x24 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x24 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x24 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x24 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x24 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x24 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x24 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x24 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x24 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x28 "GICD_ISPENDR11,GICD_ISPENDR11"
bitfld.long 0x28 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x28 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x28 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x28 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x28 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x28 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x28 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x28 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x28 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x28 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x28 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x28 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x28 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x28 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x28 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x28 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x28 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x28 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x28 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x28 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x28 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x28 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x28 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x28 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x28 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x28 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x28 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x28 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x28 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x28 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x28 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x28 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x2C "GICD_ISPENDR12,GICD_ISPENDR12"
bitfld.long 0x2C 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x2C 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x2C 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x2C 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x2C 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x2C 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x2C 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x2C 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x2C 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x2C 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x2C 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x2C 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x2C 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x2C 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x2C 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x2C 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x2C 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x2C 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x2C 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x2C 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x2C 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x2C 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x2C 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x2C 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x2C 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x2C 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x2C 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x2C 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x2C 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x2C 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x2C 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x2C 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x30 "GICD_ISPENDR13,GICD_ISPENDR13"
bitfld.long 0x30 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x30 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x30 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x30 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x30 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x30 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x30 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x30 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x30 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x30 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x30 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x30 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x30 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x30 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x30 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x30 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x30 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x30 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x30 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x30 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x30 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x30 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x30 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x30 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x30 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x30 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x30 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x30 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x30 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x30 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x30 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x30 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x34 "GICD_ISPENDR14,GICD_ISPENDR14"
bitfld.long 0x34 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x34 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x34 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x34 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x34 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x34 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x34 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x34 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x34 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x34 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x34 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x34 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x34 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x34 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x34 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x34 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x34 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x34 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x34 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x34 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x34 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x34 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x34 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x34 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x34 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x34 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x34 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x34 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x34 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x34 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x34 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x34 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x38 "GICD_ISPENDR15,GICD_ISPENDR15"
bitfld.long 0x38 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x38 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x38 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x38 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x38 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x38 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x38 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x38 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x38 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x38 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x38 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x38 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x38 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x38 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x38 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x38 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x38 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x38 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x38 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x38 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x38 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x38 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x38 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x38 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x38 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x38 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x38 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x38 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x38 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x38 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x38 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x38 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x3C "GICD_ISPENDR16,GICD_ISPENDR16"
bitfld.long 0x3C 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x3C 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x3C 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x3C 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x3C 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x3C 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x3C 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x3C 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x3C 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x3C 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x3C 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x3C 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x3C 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x3C 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x3C 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x3C 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x3C 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x3C 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x3C 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x3C 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x3C 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x3C 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x3C 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x3C 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x3C 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x3C 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x3C 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x3C 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x3C 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x3C 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x3C 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x3C 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x40 "GICD_ISPENDR17,GICD_ISPENDR17"
bitfld.long 0x40 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x40 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x40 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x40 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x40 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x40 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x40 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x40 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x40 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x40 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x40 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x40 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x40 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x40 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x40 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x40 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x40 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x40 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x40 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x40 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x40 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x40 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x40 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x40 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x40 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x40 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x40 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x40 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x40 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x40 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x40 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x40 0. "set_pending_bit0,set_pending_bit0" "0,1"
group.long 0x284++0x43
line.long 0x0 "GICD_ICPENDR1,GICD_ICPENDR1"
bitfld.long 0x0 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x0 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x0 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x0 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x0 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x0 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x0 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x0 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x0 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x0 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x0 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x0 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x0 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x0 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x0 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x0 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x0 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x4 "GICD_ICPENDR2,GICD_ICPENDR2"
bitfld.long 0x4 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x4 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x4 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x4 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x4 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x4 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x4 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x4 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x4 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x4 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x4 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x4 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x4 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x4 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x4 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x4 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x4 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x4 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x4 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x4 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x4 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x4 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x4 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x4 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x4 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x4 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x4 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x4 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x4 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x4 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x4 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x4 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x8 "GICD_ICPENDR3,GICD_ICPENDR3"
bitfld.long 0x8 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x8 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x8 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x8 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x8 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x8 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x8 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x8 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x8 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x8 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x8 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x8 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x8 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x8 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x8 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x8 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x8 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x8 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x8 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x8 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x8 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x8 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x8 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x8 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x8 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x8 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x8 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x8 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x8 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x8 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x8 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x8 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0xC "GICD_ICPENDR4,GICD_ICPENDR4"
bitfld.long 0xC 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0xC 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0xC 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0xC 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0xC 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0xC 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0xC 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0xC 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0xC 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0xC 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0xC 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0xC 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0xC 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0xC 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0xC 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0xC 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0xC 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0xC 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0xC 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0xC 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0xC 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0xC 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0xC 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0xC 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0xC 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0xC 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0xC 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0xC 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0xC 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0xC 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0xC 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0xC 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x10 "GICD_ICPENDR5,GICD_ICPENDR5"
bitfld.long 0x10 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x10 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x10 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x10 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x10 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x10 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x10 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x10 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x10 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x10 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x10 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x10 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x10 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x10 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x10 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x10 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x10 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x10 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x10 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x10 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x10 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x10 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x10 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x10 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x10 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x10 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x10 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x10 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x10 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x10 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x10 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x10 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x14 "GICD_ICPENDR6,GICD_ICPENDR6"
bitfld.long 0x14 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x14 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x14 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x14 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x14 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x14 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x14 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x14 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x14 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x14 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x14 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x14 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x14 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x14 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x14 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x14 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x14 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x14 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x14 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x14 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x14 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x14 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x14 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x14 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x14 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x14 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x14 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x14 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x14 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x14 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x14 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x14 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x18 "GICD_ICPENDR7,GICD_ICPENDR7"
bitfld.long 0x18 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x18 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x18 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x18 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x18 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x18 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x18 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x18 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x18 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x18 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x18 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x18 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x18 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x18 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x18 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x18 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x18 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x18 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x18 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x18 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x18 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x18 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x18 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x18 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x18 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x18 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x18 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x18 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x18 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x18 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x18 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x18 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x1C "GICD_ICPENDR8,GICD_ICPENDR8"
bitfld.long 0x1C 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x1C 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x1C 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x1C 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x1C 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x1C 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x1C 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x1C 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x1C 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x1C 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x1C 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x1C 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x1C 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x1C 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x1C 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x1C 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x1C 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x1C 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x1C 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x1C 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x1C 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x1C 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x1C 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x1C 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x1C 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x1C 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x1C 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x1C 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x1C 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x1C 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x1C 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x1C 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x20 "GICD_ICPENDR9,GICD_ICPENDR9"
bitfld.long 0x20 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x20 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x20 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x20 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x20 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x20 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x20 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x20 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x20 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x20 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x20 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x20 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x20 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x20 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x20 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x20 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x20 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x20 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x20 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x20 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x20 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x20 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x20 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x20 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x20 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x20 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x20 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x20 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x20 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x20 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x20 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x20 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x24 "GICD_ICPENDR10,GICD_ICPENDR10"
bitfld.long 0x24 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x24 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x24 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x24 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x24 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x24 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x24 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x24 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x24 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x24 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x24 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x24 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x24 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x24 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x24 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x24 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x24 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x24 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x24 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x24 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x24 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x24 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x24 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x24 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x24 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x24 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x24 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x24 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x24 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x24 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x24 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x24 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x28 "GICD_ICPENDR11,GICD_ICPENDR11"
bitfld.long 0x28 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x28 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x28 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x28 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x28 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x28 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x28 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x28 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x28 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x28 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x28 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x28 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x28 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x28 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x28 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x28 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x28 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x28 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x28 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x28 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x28 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x28 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x28 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x28 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x28 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x28 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x28 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x28 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x28 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x28 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x28 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x28 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x2C "GICD_ICPENDR12,GICD_ICPENDR12"
bitfld.long 0x2C 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x2C 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x2C 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x2C 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x2C 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x2C 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x2C 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x2C 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x2C 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x2C 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x2C 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x2C 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x2C 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x2C 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x2C 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x2C 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x2C 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x2C 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x2C 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x2C 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x2C 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x2C 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x2C 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x2C 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x2C 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x2C 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x2C 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x2C 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x2C 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x2C 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x2C 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x2C 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x30 "GICD_ICPENDR13,GICD_ICPENDR13"
bitfld.long 0x30 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x30 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x30 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x30 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x30 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x30 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x30 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x30 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x30 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x30 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x30 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x30 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x30 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x30 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x30 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x30 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x30 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x30 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x30 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x30 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x30 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x30 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x30 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x30 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x30 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x30 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x30 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x30 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x30 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x30 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x30 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x30 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x34 "GICD_ICPENDR14,GICD_ICPENDR14"
bitfld.long 0x34 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x34 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x34 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x34 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x34 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x34 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x34 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x34 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x34 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x34 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x34 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x34 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x34 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x34 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x34 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x34 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x34 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x34 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x34 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x34 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x34 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x34 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x34 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x34 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x34 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x34 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x34 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x34 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x34 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x34 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x34 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x34 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x38 "GICD_ICPENDR15,GICD_ICPENDR15"
bitfld.long 0x38 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x38 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x38 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x38 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x38 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x38 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x38 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x38 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x38 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x38 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x38 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x38 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x38 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x38 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x38 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x38 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x38 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x38 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x38 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x38 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x38 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x38 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x38 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x38 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x38 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x38 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x38 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x38 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x38 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x38 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x38 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x38 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x3C "GICD_ICPENDR16,GICD_ICPENDR16"
bitfld.long 0x3C 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x3C 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x3C 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x3C 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x3C 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x3C 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x3C 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x3C 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x3C 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x3C 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x3C 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x3C 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x3C 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x3C 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x3C 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x3C 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x3C 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x3C 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x3C 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x3C 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x3C 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x3C 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x3C 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x3C 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x3C 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x3C 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x3C 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x3C 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x3C 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x3C 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x3C 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x3C 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x40 "GICD_ICPENDR17,GICD_ICPENDR17"
bitfld.long 0x40 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x40 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x40 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x40 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x40 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x40 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x40 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x40 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x40 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x40 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x40 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x40 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x40 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x40 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x40 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x40 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x40 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x40 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x40 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x40 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x40 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x40 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x40 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x40 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x40 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x40 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x40 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x40 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x40 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x40 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x40 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x40 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
group.long 0x304++0x43
line.long 0x0 "GICD_ISACTIVER1,GICD_ISACTIVER1"
bitfld.long 0x0 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x0 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x0 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x0 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x0 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x0 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x0 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x0 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x0 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x0 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x0 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x0 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x0 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x0 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x0 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x0 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x0 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x4 "GICD_ISACTIVER2,GICD_ISACTIVER2"
bitfld.long 0x4 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x4 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x4 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x4 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x4 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x4 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x4 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x4 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x4 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x4 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x4 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x4 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x4 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x4 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x4 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x4 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x4 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x4 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x4 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x4 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x4 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x4 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x4 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x4 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x4 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x4 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x4 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x4 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x4 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x4 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x4 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x4 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x8 "GICD_ISACTIVER3,GICD_ISACTIVER3"
bitfld.long 0x8 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x8 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x8 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x8 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x8 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x8 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x8 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x8 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x8 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x8 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x8 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x8 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x8 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x8 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x8 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x8 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x8 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x8 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x8 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x8 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x8 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x8 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x8 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x8 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x8 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x8 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x8 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x8 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x8 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x8 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x8 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x8 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0xC "GICD_ISACTIVER4,GICD_ISACTIVER4"
bitfld.long 0xC 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0xC 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0xC 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0xC 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0xC 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0xC 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0xC 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0xC 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0xC 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0xC 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0xC 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0xC 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0xC 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0xC 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0xC 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0xC 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0xC 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0xC 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0xC 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0xC 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0xC 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0xC 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0xC 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0xC 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0xC 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0xC 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0xC 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0xC 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0xC 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0xC 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0xC 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0xC 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x10 "GICD_ISACTIVER5,GICD_ISACTIVER5"
bitfld.long 0x10 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x10 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x10 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x10 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x10 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x10 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x10 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x10 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x10 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x10 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x10 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x10 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x10 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x10 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x10 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x10 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x10 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x10 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x10 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x10 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x10 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x10 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x10 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x10 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x10 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x10 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x10 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x10 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x10 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x10 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x10 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x10 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x14 "GICD_ISACTIVER6,GICD_ISACTIVER6"
bitfld.long 0x14 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x14 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x14 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x14 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x14 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x14 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x14 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x14 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x14 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x14 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x14 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x14 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x14 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x14 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x14 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x14 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x14 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x14 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x14 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x14 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x14 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x14 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x14 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x14 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x14 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x14 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x14 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x14 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x14 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x14 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x14 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x14 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x18 "GICD_ISACTIVER7,GICD_ISACTIVER7"
bitfld.long 0x18 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x18 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x18 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x18 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x18 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x18 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x18 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x18 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x18 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x18 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x18 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x18 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x18 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x18 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x18 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x18 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x18 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x18 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x18 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x18 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x18 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x18 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x18 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x18 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x18 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x18 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x18 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x18 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x18 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x18 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x18 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x18 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x1C "GICD_ISACTIVER8,GICD_ISACTIVER8"
bitfld.long 0x1C 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x1C 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x1C 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x1C 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x1C 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x1C 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x1C 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x1C 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x1C 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x1C 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x1C 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x1C 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x1C 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x1C 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x1C 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x1C 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x1C 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x1C 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x1C 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x1C 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x1C 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x1C 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x1C 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x1C 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x1C 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x1C 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x1C 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x1C 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x1C 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x1C 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x1C 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x1C 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x20 "GICD_ISACTIVER9,GICD_ISACTIVER9"
bitfld.long 0x20 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x20 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x20 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x20 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x20 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x20 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x20 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x20 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x20 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x20 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x20 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x20 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x20 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x20 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x20 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x20 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x20 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x20 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x20 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x20 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x20 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x20 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x20 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x20 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x20 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x20 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x20 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x20 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x20 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x20 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x20 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x20 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x24 "GICD_ISACTIVER10,GICD_ISACTIVER10"
bitfld.long 0x24 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x24 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x24 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x24 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x24 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x24 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x24 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x24 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x24 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x24 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x24 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x24 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x24 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x24 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x24 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x24 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x24 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x24 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x24 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x24 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x24 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x24 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x24 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x24 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x24 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x24 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x24 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x24 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x24 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x24 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x24 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x24 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x28 "GICD_ISACTIVER11,GICD_ISACTIVER11"
bitfld.long 0x28 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x28 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x28 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x28 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x28 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x28 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x28 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x28 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x28 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x28 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x28 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x28 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x28 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x28 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x28 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x28 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x28 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x28 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x28 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x28 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x28 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x28 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x28 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x28 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x28 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x28 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x28 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x28 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x28 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x28 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x28 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x28 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x2C "GICD_ISACTIVER12,GICD_ISACTIVER12"
bitfld.long 0x2C 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x2C 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x2C 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x2C 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x2C 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x2C 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x2C 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x2C 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x2C 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x2C 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x2C 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x2C 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x2C 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x2C 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x2C 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x2C 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x2C 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x2C 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x2C 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x2C 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x2C 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x2C 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x2C 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x2C 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x2C 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x2C 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x2C 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x2C 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x2C 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x2C 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x2C 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x2C 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x30 "GICD_ISACTIVER13,GICD_ISACTIVER13"
bitfld.long 0x30 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x30 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x30 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x30 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x30 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x30 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x30 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x30 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x30 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x30 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x30 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x30 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x30 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x30 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x30 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x30 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x30 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x30 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x30 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x30 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x30 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x30 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x30 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x30 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x30 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x30 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x30 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x30 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x30 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x30 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x30 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x30 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x34 "GICD_ISACTIVER14,GICD_ISACTIVER14"
bitfld.long 0x34 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x34 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x34 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x34 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x34 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x34 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x34 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x34 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x34 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x34 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x34 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x34 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x34 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x34 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x34 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x34 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x34 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x34 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x34 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x34 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x34 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x34 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x34 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x34 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x34 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x34 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x34 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x34 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x34 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x34 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x34 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x34 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x38 "GICD_ISACTIVER15,GICD_ISACTIVER15"
bitfld.long 0x38 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x38 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x38 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x38 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x38 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x38 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x38 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x38 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x38 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x38 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x38 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x38 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x38 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x38 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x38 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x38 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x38 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x38 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x38 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x38 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x38 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x38 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x38 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x38 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x38 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x38 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x38 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x38 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x38 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x38 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x38 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x38 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x3C "GICD_ISACTIVER16,GICD_ISACTIVER16"
bitfld.long 0x3C 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x3C 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x3C 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x3C 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x3C 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x3C 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x3C 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x3C 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x3C 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x3C 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x3C 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x3C 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x3C 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x3C 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x3C 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x3C 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x3C 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x3C 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x3C 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x3C 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x3C 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x3C 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x3C 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x3C 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x3C 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x3C 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x3C 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x3C 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x3C 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x3C 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x3C 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x3C 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x40 "GICD_ISACTIVER17,GICD_ISACTIVER17"
bitfld.long 0x40 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x40 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x40 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x40 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x40 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x40 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x40 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x40 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x40 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x40 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x40 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x40 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x40 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x40 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x40 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x40 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x40 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x40 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x40 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x40 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x40 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x40 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x40 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x40 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x40 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x40 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x40 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x40 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x40 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x40 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x40 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x40 0. "set_active_bit0,set_active_bit0" "0,1"
group.long 0x384++0x43
line.long 0x0 "GICD_ICACTIVER1,GICD_ICACTIVER1"
bitfld.long 0x0 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x0 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x0 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x0 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x0 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x0 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x0 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x0 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x0 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x0 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x0 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x0 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x0 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x0 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x0 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x0 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x0 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x4 "GICD_ICACTIVER2,GICD_ICACTIVER2"
bitfld.long 0x4 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x4 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x4 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x4 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x4 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x4 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x4 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x4 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x4 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x4 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x4 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x4 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x4 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x4 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x4 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x4 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x4 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x4 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x4 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x4 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x4 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x4 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x4 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x4 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x4 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x4 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x4 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x4 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x4 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x4 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x4 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x4 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x8 "GICD_ICACTIVER3,GICD_ICACTIVER3"
bitfld.long 0x8 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x8 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x8 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x8 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x8 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x8 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x8 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x8 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x8 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x8 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x8 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x8 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x8 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x8 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x8 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x8 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x8 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x8 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x8 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x8 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x8 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x8 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x8 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x8 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x8 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x8 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x8 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x8 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x8 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x8 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x8 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x8 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0xC "GICD_ICACTIVER4,GICD_ICACTIVER4"
bitfld.long 0xC 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0xC 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0xC 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0xC 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0xC 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0xC 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0xC 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0xC 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0xC 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0xC 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0xC 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0xC 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0xC 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0xC 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0xC 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0xC 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0xC 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0xC 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0xC 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0xC 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0xC 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0xC 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0xC 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0xC 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0xC 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0xC 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0xC 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0xC 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0xC 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0xC 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0xC 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0xC 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x10 "GICD_ICACTIVER5,GICD_ICACTIVER5"
bitfld.long 0x10 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x10 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x10 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x10 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x10 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x10 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x10 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x10 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x10 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x10 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x10 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x10 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x10 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x10 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x10 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x10 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x10 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x10 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x10 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x10 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x10 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x10 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x10 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x10 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x10 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x10 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x10 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x10 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x10 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x10 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x10 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x10 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x14 "GICD_ICACTIVER6,GICD_ICACTIVER6"
bitfld.long 0x14 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x14 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x14 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x14 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x14 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x14 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x14 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x14 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x14 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x14 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x14 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x14 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x14 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x14 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x14 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x14 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x14 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x14 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x14 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x14 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x14 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x14 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x14 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x14 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x14 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x14 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x14 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x14 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x14 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x14 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x14 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x14 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x18 "GICD_ICACTIVER7,GICD_ICACTIVER7"
bitfld.long 0x18 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x18 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x18 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x18 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x18 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x18 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x18 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x18 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x18 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x18 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x18 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x18 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x18 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x18 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x18 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x18 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x18 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x18 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x18 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x18 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x18 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x18 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x18 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x18 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x18 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x18 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x18 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x18 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x18 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x18 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x18 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x18 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x1C "GICD_ICACTIVER8,GICD_ICACTIVER8"
bitfld.long 0x1C 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x1C 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x1C 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x1C 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x1C 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x1C 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x1C 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x1C 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x1C 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x1C 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x1C 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x1C 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x1C 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x1C 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x1C 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x1C 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x1C 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x1C 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x1C 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x1C 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x1C 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x1C 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x1C 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x1C 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x1C 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x1C 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x1C 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x1C 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x1C 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x1C 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x1C 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x1C 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x20 "GICD_ICACTIVER9,GICD_ICACTIVER9"
bitfld.long 0x20 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x20 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x20 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x20 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x20 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x20 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x20 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x20 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x20 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x20 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x20 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x20 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x20 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x20 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x20 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x20 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x20 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x20 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x20 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x20 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x20 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x20 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x20 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x20 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x20 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x20 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x20 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x20 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x20 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x20 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x20 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x20 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x24 "GICD_ICACTIVER10,GICD_ICACTIVER10"
bitfld.long 0x24 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x24 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x24 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x24 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x24 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x24 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x24 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x24 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x24 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x24 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x24 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x24 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x24 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x24 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x24 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x24 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x24 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x24 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x24 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x24 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x24 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x24 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x24 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x24 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x24 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x24 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x24 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x24 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x24 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x24 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x24 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x24 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x28 "GICD_ICACTIVER11,GICD_ICACTIVER11"
bitfld.long 0x28 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x28 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x28 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x28 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x28 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x28 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x28 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x28 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x28 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x28 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x28 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x28 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x28 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x28 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x28 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x28 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x28 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x28 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x28 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x28 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x28 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x28 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x28 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x28 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x28 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x28 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x28 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x28 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x28 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x28 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x28 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x28 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x2C "GICD_ICACTIVER12,GICD_ICACTIVER12"
bitfld.long 0x2C 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x2C 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x2C 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x2C 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x2C 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x2C 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x2C 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x2C 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x2C 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x2C 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x2C 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x2C 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x2C 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x2C 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x2C 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x2C 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x2C 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x2C 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x2C 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x2C 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x2C 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x2C 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x2C 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x2C 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x2C 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x2C 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x2C 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x2C 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x2C 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x2C 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x2C 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x2C 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x30 "GICD_ICACTIVER13,GICD_ICACTIVER13"
bitfld.long 0x30 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x30 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x30 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x30 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x30 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x30 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x30 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x30 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x30 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x30 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x30 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x30 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x30 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x30 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x30 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x30 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x30 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x30 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x30 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x30 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x30 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x30 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x30 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x30 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x30 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x30 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x30 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x30 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x30 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x30 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x30 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x30 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x34 "GICD_ICACTIVER14,GICD_ICACTIVER14"
bitfld.long 0x34 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x34 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x34 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x34 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x34 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x34 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x34 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x34 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x34 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x34 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x34 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x34 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x34 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x34 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x34 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x34 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x34 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x34 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x34 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x34 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x34 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x34 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x34 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x34 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x34 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x34 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x34 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x34 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x34 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x34 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x34 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x34 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x38 "GICD_ICACTIVER15,GICD_ICACTIVER15"
bitfld.long 0x38 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x38 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x38 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x38 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x38 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x38 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x38 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x38 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x38 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x38 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x38 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x38 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x38 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x38 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x38 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x38 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x38 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x38 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x38 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x38 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x38 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x38 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x38 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x38 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x38 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x38 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x38 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x38 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x38 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x38 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x38 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x38 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x3C "GICD_ICACTIVER16,GICD_ICACTIVER16"
bitfld.long 0x3C 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x3C 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x3C 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x3C 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x3C 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x3C 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x3C 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x3C 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x3C 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x3C 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x3C 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x3C 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x3C 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x3C 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x3C 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x3C 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x3C 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x3C 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x3C 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x3C 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x3C 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x3C 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x3C 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x3C 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x3C 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x3C 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x3C 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x3C 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x3C 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x3C 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x3C 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x3C 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x40 "GICD_ICACTIVER17,GICD_ICACTIVER17"
bitfld.long 0x40 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x40 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x40 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x40 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x40 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x40 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x40 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x40 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x40 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x40 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x40 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x40 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x40 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x40 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x40 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x40 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x40 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x40 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x40 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x40 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x40 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x40 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x40 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x40 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x40 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x40 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x40 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x40 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x40 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x40 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x40 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x40 0. "clear_active_bit0,clear_active_bit0" "0,1"
group.long 0x420++0x21F
line.long 0x0 "GICD_IPRIORITYR8,GICD_IPRIORITYR8"
hexmask.long.byte 0x0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x0 0.--7. 1. "offset0,offset0"
line.long 0x4 "GICD_IPRIORITYR9,GICD_IPRIORITYR9"
hexmask.long.byte 0x4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x4 0.--7. 1. "offset0,offset0"
line.long 0x8 "GICD_IPRIORITYR10,GICD_IPRIORITYR10"
hexmask.long.byte 0x8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x8 0.--7. 1. "offset0,offset0"
line.long 0xC "GICD_IPRIORITYR11,GICD_IPRIORITYR11"
hexmask.long.byte 0xC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC 0.--7. 1. "offset0,offset0"
line.long 0x10 "GICD_IPRIORITYR12,GICD_IPRIORITYR12"
hexmask.long.byte 0x10 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x10 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x10 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x10 0.--7. 1. "offset0,offset0"
line.long 0x14 "GICD_IPRIORITYR13,GICD_IPRIORITYR13"
hexmask.long.byte 0x14 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x14 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x14 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x14 0.--7. 1. "offset0,offset0"
line.long 0x18 "GICD_IPRIORITYR14,GICD_IPRIORITYR14"
hexmask.long.byte 0x18 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x18 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x18 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x18 0.--7. 1. "offset0,offset0"
line.long 0x1C "GICD_IPRIORITYR15,GICD_IPRIORITYR15"
hexmask.long.byte 0x1C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C 0.--7. 1. "offset0,offset0"
line.long 0x20 "GICD_IPRIORITYR16,GICD_IPRIORITYR16"
hexmask.long.byte 0x20 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x20 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x20 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x20 0.--7. 1. "offset0,offset0"
line.long 0x24 "GICD_IPRIORITYR17,GICD_IPRIORITYR17"
hexmask.long.byte 0x24 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x24 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x24 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x24 0.--7. 1. "offset0,offset0"
line.long 0x28 "GICD_IPRIORITYR18,GICD_IPRIORITYR18"
hexmask.long.byte 0x28 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x28 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x28 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x28 0.--7. 1. "offset0,offset0"
line.long 0x2C "GICD_IPRIORITYR19,GICD_IPRIORITYR19"
hexmask.long.byte 0x2C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x2C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x2C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x2C 0.--7. 1. "offset0,offset0"
line.long 0x30 "GICD_IPRIORITYR20,GICD_IPRIORITYR20"
hexmask.long.byte 0x30 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x30 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x30 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x30 0.--7. 1. "offset0,offset0"
line.long 0x34 "GICD_IPRIORITYR21,GICD_IPRIORITYR21"
hexmask.long.byte 0x34 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x34 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x34 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x34 0.--7. 1. "offset0,offset0"
line.long 0x38 "GICD_IPRIORITYR22,GICD_IPRIORITYR22"
hexmask.long.byte 0x38 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x38 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x38 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x38 0.--7. 1. "offset0,offset0"
line.long 0x3C "GICD_IPRIORITYR23,GICD_IPRIORITYR23"
hexmask.long.byte 0x3C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x3C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x3C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x3C 0.--7. 1. "offset0,offset0"
line.long 0x40 "GICD_IPRIORITYR24,GICD_IPRIORITYR24"
hexmask.long.byte 0x40 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x40 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x40 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x40 0.--7. 1. "offset0,offset0"
line.long 0x44 "GICD_IPRIORITYR25,GICD_IPRIORITYR25"
hexmask.long.byte 0x44 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x44 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x44 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x44 0.--7. 1. "offset0,offset0"
line.long 0x48 "GICD_IPRIORITYR26,GICD_IPRIORITYR26"
hexmask.long.byte 0x48 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x48 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x48 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x48 0.--7. 1. "offset0,offset0"
line.long 0x4C "GICD_IPRIORITYR27,GICD_IPRIORITYR27"
hexmask.long.byte 0x4C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x4C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x4C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x4C 0.--7. 1. "offset0,offset0"
line.long 0x50 "GICD_IPRIORITYR28,GICD_IPRIORITYR28"
hexmask.long.byte 0x50 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x50 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x50 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x50 0.--7. 1. "offset0,offset0"
line.long 0x54 "GICD_IPRIORITYR29,GICD_IPRIORITYR29"
hexmask.long.byte 0x54 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x54 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x54 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x54 0.--7. 1. "offset0,offset0"
line.long 0x58 "GICD_IPRIORITYR30,GICD_IPRIORITYR30"
hexmask.long.byte 0x58 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x58 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x58 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x58 0.--7. 1. "offset0,offset0"
line.long 0x5C "GICD_IPRIORITYR31,GICD_IPRIORITYR31"
hexmask.long.byte 0x5C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x5C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x5C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x5C 0.--7. 1. "offset0,offset0"
line.long 0x60 "GICD_IPRIORITYR32,GICD_IPRIORITYR32"
hexmask.long.byte 0x60 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x60 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x60 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x60 0.--7. 1. "offset0,offset0"
line.long 0x64 "GICD_IPRIORITYR33,GICD_IPRIORITYR33"
hexmask.long.byte 0x64 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x64 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x64 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x64 0.--7. 1. "offset0,offset0"
line.long 0x68 "GICD_IPRIORITYR34,GICD_IPRIORITYR34"
hexmask.long.byte 0x68 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x68 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x68 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x68 0.--7. 1. "offset0,offset0"
line.long 0x6C "GICD_IPRIORITYR35,GICD_IPRIORITYR35"
hexmask.long.byte 0x6C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x6C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x6C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x6C 0.--7. 1. "offset0,offset0"
line.long 0x70 "GICD_IPRIORITYR36,GICD_IPRIORITYR36"
hexmask.long.byte 0x70 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x70 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x70 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x70 0.--7. 1. "offset0,offset0"
line.long 0x74 "GICD_IPRIORITYR37,GICD_IPRIORITYR37"
hexmask.long.byte 0x74 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x74 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x74 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x74 0.--7. 1. "offset0,offset0"
line.long 0x78 "GICD_IPRIORITYR38,GICD_IPRIORITYR38"
hexmask.long.byte 0x78 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x78 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x78 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x78 0.--7. 1. "offset0,offset0"
line.long 0x7C "GICD_IPRIORITYR39,GICD_IPRIORITYR39"
hexmask.long.byte 0x7C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x7C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x7C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x7C 0.--7. 1. "offset0,offset0"
line.long 0x80 "GICD_IPRIORITYR40,GICD_IPRIORITYR40"
hexmask.long.byte 0x80 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x80 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x80 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x80 0.--7. 1. "offset0,offset0"
line.long 0x84 "GICD_IPRIORITYR41,GICD_IPRIORITYR41"
hexmask.long.byte 0x84 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x84 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x84 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x84 0.--7. 1. "offset0,offset0"
line.long 0x88 "GICD_IPRIORITYR42,GICD_IPRIORITYR42"
hexmask.long.byte 0x88 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x88 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x88 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x88 0.--7. 1. "offset0,offset0"
line.long 0x8C "GICD_IPRIORITYR43,GICD_IPRIORITYR43"
hexmask.long.byte 0x8C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x8C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x8C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x8C 0.--7. 1. "offset0,offset0"
line.long 0x90 "GICD_IPRIORITYR44,GICD_IPRIORITYR44"
hexmask.long.byte 0x90 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x90 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x90 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x90 0.--7. 1. "offset0,offset0"
line.long 0x94 "GICD_IPRIORITYR45,GICD_IPRIORITYR45"
hexmask.long.byte 0x94 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x94 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x94 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x94 0.--7. 1. "offset0,offset0"
line.long 0x98 "GICD_IPRIORITYR46,GICD_IPRIORITYR46"
hexmask.long.byte 0x98 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x98 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x98 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x98 0.--7. 1. "offset0,offset0"
line.long 0x9C "GICD_IPRIORITYR47,GICD_IPRIORITYR47"
hexmask.long.byte 0x9C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x9C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x9C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x9C 0.--7. 1. "offset0,offset0"
line.long 0xA0 "GICD_IPRIORITYR48,GICD_IPRIORITYR48"
hexmask.long.byte 0xA0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xA0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xA0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xA0 0.--7. 1. "offset0,offset0"
line.long 0xA4 "GICD_IPRIORITYR49,GICD_IPRIORITYR49"
hexmask.long.byte 0xA4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xA4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xA4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xA4 0.--7. 1. "offset0,offset0"
line.long 0xA8 "GICD_IPRIORITYR50,GICD_IPRIORITYR50"
hexmask.long.byte 0xA8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xA8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xA8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xA8 0.--7. 1. "offset0,offset0"
line.long 0xAC "GICD_IPRIORITYR51,GICD_IPRIORITYR51"
hexmask.long.byte 0xAC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xAC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xAC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xAC 0.--7. 1. "offset0,offset0"
line.long 0xB0 "GICD_IPRIORITYR52,GICD_IPRIORITYR52"
hexmask.long.byte 0xB0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xB0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xB0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xB0 0.--7. 1. "offset0,offset0"
line.long 0xB4 "GICD_IPRIORITYR53,GICD_IPRIORITYR53"
hexmask.long.byte 0xB4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xB4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xB4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xB4 0.--7. 1. "offset0,offset0"
line.long 0xB8 "GICD_IPRIORITYR54,GICD_IPRIORITYR54"
hexmask.long.byte 0xB8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xB8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xB8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xB8 0.--7. 1. "offset0,offset0"
line.long 0xBC "GICD_IPRIORITYR55,GICD_IPRIORITYR55"
hexmask.long.byte 0xBC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xBC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xBC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xBC 0.--7. 1. "offset0,offset0"
line.long 0xC0 "GICD_IPRIORITYR56,GICD_IPRIORITYR56"
hexmask.long.byte 0xC0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC0 0.--7. 1. "offset0,offset0"
line.long 0xC4 "GICD_IPRIORITYR57,GICD_IPRIORITYR57"
hexmask.long.byte 0xC4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC4 0.--7. 1. "offset0,offset0"
line.long 0xC8 "GICD_IPRIORITYR58,GICD_IPRIORITYR58"
hexmask.long.byte 0xC8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC8 0.--7. 1. "offset0,offset0"
line.long 0xCC "GICD_IPRIORITYR59,GICD_IPRIORITYR59"
hexmask.long.byte 0xCC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xCC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xCC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xCC 0.--7. 1. "offset0,offset0"
line.long 0xD0 "GICD_IPRIORITYR60,GICD_IPRIORITYR60"
hexmask.long.byte 0xD0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xD0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xD0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xD0 0.--7. 1. "offset0,offset0"
line.long 0xD4 "GICD_IPRIORITYR61,GICD_IPRIORITYR61"
hexmask.long.byte 0xD4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xD4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xD4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xD4 0.--7. 1. "offset0,offset0"
line.long 0xD8 "GICD_IPRIORITYR62,GICD_IPRIORITYR62"
hexmask.long.byte 0xD8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xD8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xD8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xD8 0.--7. 1. "offset0,offset0"
line.long 0xDC "GICD_IPRIORITYR63,GICD_IPRIORITYR63"
hexmask.long.byte 0xDC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xDC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xDC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xDC 0.--7. 1. "offset0,offset0"
line.long 0xE0 "GICD_IPRIORITYR64,GICD_IPRIORITYR64"
hexmask.long.byte 0xE0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xE0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xE0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xE0 0.--7. 1. "offset0,offset0"
line.long 0xE4 "GICD_IPRIORITYR65,GICD_IPRIORITYR65"
hexmask.long.byte 0xE4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xE4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xE4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xE4 0.--7. 1. "offset0,offset0"
line.long 0xE8 "GICD_IPRIORITYR66,GICD_IPRIORITYR66"
hexmask.long.byte 0xE8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xE8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xE8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xE8 0.--7. 1. "offset0,offset0"
line.long 0xEC "GICD_IPRIORITYR67,GICD_IPRIORITYR67"
hexmask.long.byte 0xEC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xEC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xEC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xEC 0.--7. 1. "offset0,offset0"
line.long 0xF0 "GICD_IPRIORITYR68,GICD_IPRIORITYR68"
hexmask.long.byte 0xF0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xF0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xF0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xF0 0.--7. 1. "offset0,offset0"
line.long 0xF4 "GICD_IPRIORITYR69,GICD_IPRIORITYR69"
hexmask.long.byte 0xF4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xF4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xF4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xF4 0.--7. 1. "offset0,offset0"
line.long 0xF8 "GICD_IPRIORITYR70,GICD_IPRIORITYR70"
hexmask.long.byte 0xF8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xF8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xF8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xF8 0.--7. 1. "offset0,offset0"
line.long 0xFC "GICD_IPRIORITYR71,GICD_IPRIORITYR71"
hexmask.long.byte 0xFC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xFC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xFC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xFC 0.--7. 1. "offset0,offset0"
line.long 0x100 "GICD_IPRIORITYR72,GICD_IPRIORITYR72"
hexmask.long.byte 0x100 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x100 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x100 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x100 0.--7. 1. "offset0,offset0"
line.long 0x104 "GICD_IPRIORITYR73,GICD_IPRIORITYR73"
hexmask.long.byte 0x104 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x104 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x104 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x104 0.--7. 1. "offset0,offset0"
line.long 0x108 "GICD_IPRIORITYR74,GICD_IPRIORITYR74"
hexmask.long.byte 0x108 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x108 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x108 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x108 0.--7. 1. "offset0,offset0"
line.long 0x10C "GICD_IPRIORITYR75,GICD_IPRIORITYR75"
hexmask.long.byte 0x10C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x10C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x10C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x10C 0.--7. 1. "offset0,offset0"
line.long 0x110 "GICD_IPRIORITYR76,GICD_IPRIORITYR76"
hexmask.long.byte 0x110 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x110 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x110 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x110 0.--7. 1. "offset0,offset0"
line.long 0x114 "GICD_IPRIORITYR77,GICD_IPRIORITYR77"
hexmask.long.byte 0x114 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x114 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x114 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x114 0.--7. 1. "offset0,offset0"
line.long 0x118 "GICD_IPRIORITYR78,GICD_IPRIORITYR78"
hexmask.long.byte 0x118 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x118 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x118 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x118 0.--7. 1. "offset0,offset0"
line.long 0x11C "GICD_IPRIORITYR79,GICD_IPRIORITYR79"
hexmask.long.byte 0x11C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x11C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x11C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x11C 0.--7. 1. "offset0,offset0"
line.long 0x120 "GICD_IPRIORITYR80,GICD_IPRIORITYR80"
hexmask.long.byte 0x120 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x120 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x120 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x120 0.--7. 1. "offset0,offset0"
line.long 0x124 "GICD_IPRIORITYR81,GICD_IPRIORITYR81"
hexmask.long.byte 0x124 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x124 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x124 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x124 0.--7. 1. "offset0,offset0"
line.long 0x128 "GICD_IPRIORITYR82,GICD_IPRIORITYR82"
hexmask.long.byte 0x128 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x128 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x128 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x128 0.--7. 1. "offset0,offset0"
line.long 0x12C "GICD_IPRIORITYR83,GICD_IPRIORITYR83"
hexmask.long.byte 0x12C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x12C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x12C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x12C 0.--7. 1. "offset0,offset0"
line.long 0x130 "GICD_IPRIORITYR84,GICD_IPRIORITYR84"
hexmask.long.byte 0x130 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x130 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x130 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x130 0.--7. 1. "offset0,offset0"
line.long 0x134 "GICD_IPRIORITYR85,GICD_IPRIORITYR85"
hexmask.long.byte 0x134 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x134 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x134 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x134 0.--7. 1. "offset0,offset0"
line.long 0x138 "GICD_IPRIORITYR86,GICD_IPRIORITYR86"
hexmask.long.byte 0x138 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x138 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x138 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x138 0.--7. 1. "offset0,offset0"
line.long 0x13C "GICD_IPRIORITYR87,GICD_IPRIORITYR87"
hexmask.long.byte 0x13C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x13C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x13C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x13C 0.--7. 1. "offset0,offset0"
line.long 0x140 "GICD_IPRIORITYR88,GICD_IPRIORITYR88"
hexmask.long.byte 0x140 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x140 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x140 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x140 0.--7. 1. "offset0,offset0"
line.long 0x144 "GICD_IPRIORITYR89,GICD_IPRIORITYR89"
hexmask.long.byte 0x144 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x144 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x144 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x144 0.--7. 1. "offset0,offset0"
line.long 0x148 "GICD_IPRIORITYR90,GICD_IPRIORITYR90"
hexmask.long.byte 0x148 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x148 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x148 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x148 0.--7. 1. "offset0,offset0"
line.long 0x14C "GICD_IPRIORITYR91,GICD_IPRIORITYR91"
hexmask.long.byte 0x14C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x14C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x14C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x14C 0.--7. 1. "offset0,offset0"
line.long 0x150 "GICD_IPRIORITYR92,GICD_IPRIORITYR92"
hexmask.long.byte 0x150 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x150 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x150 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x150 0.--7. 1. "offset0,offset0"
line.long 0x154 "GICD_IPRIORITYR93,GICD_IPRIORITYR93"
hexmask.long.byte 0x154 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x154 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x154 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x154 0.--7. 1. "offset0,offset0"
line.long 0x158 "GICD_IPRIORITYR94,GICD_IPRIORITYR94"
hexmask.long.byte 0x158 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x158 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x158 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x158 0.--7. 1. "offset0,offset0"
line.long 0x15C "GICD_IPRIORITYR95,GICD_IPRIORITYR95"
hexmask.long.byte 0x15C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x15C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x15C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x15C 0.--7. 1. "offset0,offset0"
line.long 0x160 "GICD_IPRIORITYR96,GICD_IPRIORITYR96"
hexmask.long.byte 0x160 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x160 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x160 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x160 0.--7. 1. "offset0,offset0"
line.long 0x164 "GICD_IPRIORITYR97,GICD_IPRIORITYR97"
hexmask.long.byte 0x164 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x164 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x164 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x164 0.--7. 1. "offset0,offset0"
line.long 0x168 "GICD_IPRIORITYR98,GICD_IPRIORITYR98"
hexmask.long.byte 0x168 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x168 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x168 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x168 0.--7. 1. "offset0,offset0"
line.long 0x16C "GICD_IPRIORITYR99,GICD_IPRIORITYR99"
hexmask.long.byte 0x16C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x16C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x16C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x16C 0.--7. 1. "offset0,offset0"
line.long 0x170 "GICD_IPRIORITYR100,GICD_IPRIORITYR100"
hexmask.long.byte 0x170 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x170 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x170 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x170 0.--7. 1. "offset0,offset0"
line.long 0x174 "GICD_IPRIORITYR101,GICD_IPRIORITYR101"
hexmask.long.byte 0x174 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x174 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x174 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x174 0.--7. 1. "offset0,offset0"
line.long 0x178 "GICD_IPRIORITYR102,GICD_IPRIORITYR102"
hexmask.long.byte 0x178 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x178 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x178 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x178 0.--7. 1. "offset0,offset0"
line.long 0x17C "GICD_IPRIORITYR103,GICD_IPRIORITYR103"
hexmask.long.byte 0x17C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x17C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x17C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x17C 0.--7. 1. "offset0,offset0"
line.long 0x180 "GICD_IPRIORITYR104,GICD_IPRIORITYR104"
hexmask.long.byte 0x180 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x180 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x180 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x180 0.--7. 1. "offset0,offset0"
line.long 0x184 "GICD_IPRIORITYR105,GICD_IPRIORITYR105"
hexmask.long.byte 0x184 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x184 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x184 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x184 0.--7. 1. "offset0,offset0"
line.long 0x188 "GICD_IPRIORITYR106,GICD_IPRIORITYR106"
hexmask.long.byte 0x188 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x188 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x188 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x188 0.--7. 1. "offset0,offset0"
line.long 0x18C "GICD_IPRIORITYR107,GICD_IPRIORITYR107"
hexmask.long.byte 0x18C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x18C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x18C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x18C 0.--7. 1. "offset0,offset0"
line.long 0x190 "GICD_IPRIORITYR108,GICD_IPRIORITYR108"
hexmask.long.byte 0x190 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x190 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x190 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x190 0.--7. 1. "offset0,offset0"
line.long 0x194 "GICD_IPRIORITYR109,GICD_IPRIORITYR109"
hexmask.long.byte 0x194 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x194 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x194 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x194 0.--7. 1. "offset0,offset0"
line.long 0x198 "GICD_IPRIORITYR110,GICD_IPRIORITYR110"
hexmask.long.byte 0x198 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x198 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x198 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x198 0.--7. 1. "offset0,offset0"
line.long 0x19C "GICD_IPRIORITYR111,GICD_IPRIORITYR111"
hexmask.long.byte 0x19C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x19C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x19C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x19C 0.--7. 1. "offset0,offset0"
line.long 0x1A0 "GICD_IPRIORITYR112,GICD_IPRIORITYR112"
hexmask.long.byte 0x1A0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1A0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1A0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1A0 0.--7. 1. "offset0,offset0"
line.long 0x1A4 "GICD_IPRIORITYR113,GICD_IPRIORITYR113"
hexmask.long.byte 0x1A4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1A4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1A4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1A4 0.--7. 1. "offset0,offset0"
line.long 0x1A8 "GICD_IPRIORITYR114,GICD_IPRIORITYR114"
hexmask.long.byte 0x1A8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1A8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1A8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1A8 0.--7. 1. "offset0,offset0"
line.long 0x1AC "GICD_IPRIORITYR115,GICD_IPRIORITYR115"
hexmask.long.byte 0x1AC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1AC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1AC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1AC 0.--7. 1. "offset0,offset0"
line.long 0x1B0 "GICD_IPRIORITYR116,GICD_IPRIORITYR116"
hexmask.long.byte 0x1B0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1B0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1B0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1B0 0.--7. 1. "offset0,offset0"
line.long 0x1B4 "GICD_IPRIORITYR117,GICD_IPRIORITYR117"
hexmask.long.byte 0x1B4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1B4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1B4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1B4 0.--7. 1. "offset0,offset0"
line.long 0x1B8 "GICD_IPRIORITYR118,GICD_IPRIORITYR118"
hexmask.long.byte 0x1B8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1B8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1B8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1B8 0.--7. 1. "offset0,offset0"
line.long 0x1BC "GICD_IPRIORITYR119,GICD_IPRIORITYR119"
hexmask.long.byte 0x1BC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1BC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1BC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1BC 0.--7. 1. "offset0,offset0"
line.long 0x1C0 "GICD_IPRIORITYR120,GICD_IPRIORITYR120"
hexmask.long.byte 0x1C0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C0 0.--7. 1. "offset0,offset0"
line.long 0x1C4 "GICD_IPRIORITYR121,GICD_IPRIORITYR121"
hexmask.long.byte 0x1C4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C4 0.--7. 1. "offset0,offset0"
line.long 0x1C8 "GICD_IPRIORITYR122,GICD_IPRIORITYR122"
hexmask.long.byte 0x1C8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C8 0.--7. 1. "offset0,offset0"
line.long 0x1CC "GICD_IPRIORITYR123,GICD_IPRIORITYR123"
hexmask.long.byte 0x1CC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1CC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1CC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1CC 0.--7. 1. "offset0,offset0"
line.long 0x1D0 "GICD_IPRIORITYR124,GICD_IPRIORITYR124"
hexmask.long.byte 0x1D0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1D0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1D0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1D0 0.--7. 1. "offset0,offset0"
line.long 0x1D4 "GICD_IPRIORITYR125,GICD_IPRIORITYR125"
hexmask.long.byte 0x1D4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1D4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1D4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1D4 0.--7. 1. "offset0,offset0"
line.long 0x1D8 "GICD_IPRIORITYR126,GICD_IPRIORITYR126"
hexmask.long.byte 0x1D8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1D8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1D8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1D8 0.--7. 1. "offset0,offset0"
line.long 0x1DC "GICD_IPRIORITYR127,GICD_IPRIORITYR127"
hexmask.long.byte 0x1DC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1DC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1DC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1DC 0.--7. 1. "offset0,offset0"
line.long 0x1E0 "GICD_IPRIORITYR128,GICD_IPRIORITYR128"
hexmask.long.byte 0x1E0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1E0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1E0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1E0 0.--7. 1. "offset0,offset0"
line.long 0x1E4 "GICD_IPRIORITYR129,GICD_IPRIORITYR129"
hexmask.long.byte 0x1E4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1E4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1E4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1E4 0.--7. 1. "offset0,offset0"
line.long 0x1E8 "GICD_IPRIORITYR130,GICD_IPRIORITYR130"
hexmask.long.byte 0x1E8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1E8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1E8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1E8 0.--7. 1. "offset0,offset0"
line.long 0x1EC "GICD_IPRIORITYR131,GICD_IPRIORITYR131"
hexmask.long.byte 0x1EC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1EC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1EC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1EC 0.--7. 1. "offset0,offset0"
line.long 0x1F0 "GICD_IPRIORITYR132,GICD_IPRIORITYR132"
hexmask.long.byte 0x1F0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1F0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1F0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1F0 0.--7. 1. "offset0,offset0"
line.long 0x1F4 "GICD_IPRIORITYR133,GICD_IPRIORITYR133"
hexmask.long.byte 0x1F4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1F4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1F4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1F4 0.--7. 1. "offset0,offset0"
line.long 0x1F8 "GICD_IPRIORITYR134,GICD_IPRIORITYR134"
hexmask.long.byte 0x1F8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1F8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1F8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1F8 0.--7. 1. "offset0,offset0"
line.long 0x1FC "GICD_IPRIORITYR135,GICD_IPRIORITYR135"
hexmask.long.byte 0x1FC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1FC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1FC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1FC 0.--7. 1. "offset0,offset0"
line.long 0x200 "GICD_IPRIORITYR136,GICD_IPRIORITYR136"
hexmask.long.byte 0x200 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x200 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x200 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x200 0.--7. 1. "offset0,offset0"
line.long 0x204 "GICD_IPRIORITYR137,GICD_IPRIORITYR137"
hexmask.long.byte 0x204 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x204 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x204 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x204 0.--7. 1. "offset0,offset0"
line.long 0x208 "GICD_IPRIORITYR138,GICD_IPRIORITYR138"
hexmask.long.byte 0x208 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x208 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x208 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x208 0.--7. 1. "offset0,offset0"
line.long 0x20C "GICD_IPRIORITYR139,GICD_IPRIORITYR139"
hexmask.long.byte 0x20C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x20C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x20C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x20C 0.--7. 1. "offset0,offset0"
line.long 0x210 "GICD_IPRIORITYR140,GICD_IPRIORITYR140"
hexmask.long.byte 0x210 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x210 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x210 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x210 0.--7. 1. "offset0,offset0"
line.long 0x214 "GICD_IPRIORITYR141,GICD_IPRIORITYR141"
hexmask.long.byte 0x214 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x214 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x214 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x214 0.--7. 1. "offset0,offset0"
line.long 0x218 "GICD_IPRIORITYR142,GICD_IPRIORITYR142"
hexmask.long.byte 0x218 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x218 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x218 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x218 0.--7. 1. "offset0,offset0"
line.long 0x21C "GICD_IPRIORITYR143,GICD_IPRIORITYR143"
hexmask.long.byte 0x21C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x21C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x21C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x21C 0.--7. 1. "offset0,offset0"
group.long 0xC08++0x87
line.long 0x0 "GICD_ICFGR2,GICD_ICFGR2"
bitfld.long 0x0 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x0 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x0 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x0 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x0 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x0 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x0 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x0 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x0 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x4 "GICD_ICFGR3,GICD_ICFGR3"
bitfld.long 0x4 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x4 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x4 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x4 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x4 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x4 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x4 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x4 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x4 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x4 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x4 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x4 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x8 "GICD_ICFGR4,GICD_ICFGR4"
bitfld.long 0x8 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x8 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x8 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x8 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x8 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x8 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x8 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x8 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x8 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x8 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x8 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x8 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x8 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x8 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0xC "GICD_ICFGR5,GICD_ICFGR5"
bitfld.long 0xC 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0xC 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0xC 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0xC 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0xC 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0xC 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0xC 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0xC 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0xC 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0xC 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0xC 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0xC 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x10 "GICD_ICFGR6,GICD_ICFGR6"
bitfld.long 0x10 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x10 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x10 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x10 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x10 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x10 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x10 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x10 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x10 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x10 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x10 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x10 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x10 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x14 "GICD_ICFGR7,GICD_ICFGR7"
bitfld.long 0x14 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x14 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x14 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x14 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x14 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x14 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x14 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x14 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x14 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x14 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x14 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x14 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x14 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x14 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x14 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x18 "GICD_ICFGR8,GICD_ICFGR8"
bitfld.long 0x18 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x18 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x18 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x18 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x18 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x18 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x18 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x18 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x18 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x18 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x18 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x18 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x18 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x18 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x18 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x1C "GICD_ICFGR9,GICD_ICFGR9"
bitfld.long 0x1C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x1C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x1C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x1C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x1C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x1C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x1C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x1C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x1C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x1C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x1C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x1C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x1C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x1C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x20 "GICD_ICFGR10,GICD_ICFGR10"
bitfld.long 0x20 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x20 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x20 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x20 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x20 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x20 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x20 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x20 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x20 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x20 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x20 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x20 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x20 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x20 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x20 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x20 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x24 "GICD_ICFGR11,GICD_ICFGR11"
bitfld.long 0x24 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x24 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x24 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x24 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x24 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x24 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x24 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x24 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x24 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x24 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x24 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x24 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x24 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x24 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x24 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x28 "GICD_ICFGR12,GICD_ICFGR12"
bitfld.long 0x28 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x28 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x28 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x28 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x28 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x28 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x28 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x28 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x28 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x28 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x28 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x28 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x28 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x28 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x28 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x28 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x2C "GICD_ICFGR13,GICD_ICFGR13"
bitfld.long 0x2C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x2C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x2C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x2C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x2C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x2C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x2C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x2C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x2C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x2C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x2C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x2C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x2C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x2C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x2C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x2C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x30 "GICD_ICFGR14,GICD_ICFGR14"
bitfld.long 0x30 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x30 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x30 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x30 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x30 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x30 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x30 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x30 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x30 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x30 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x30 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x30 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x30 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x30 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x30 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x30 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x34 "GICD_ICFGR15,GICD_ICFGR15"
bitfld.long 0x34 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x34 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x34 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x34 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x34 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x34 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x34 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x34 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x34 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x34 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x34 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x34 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x34 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x34 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x34 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x38 "GICD_ICFGR16,GICD_ICFGR16"
bitfld.long 0x38 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x38 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x38 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x38 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x38 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x38 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x38 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x38 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x38 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x38 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x38 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x38 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x38 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x38 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x38 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x38 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x3C "GICD_ICFGR17,GICD_ICFGR17"
bitfld.long 0x3C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x3C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x3C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x3C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x3C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x3C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x3C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x3C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x3C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x3C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x3C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x3C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x3C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x3C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x3C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x3C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x40 "GICD_ICFGR18,GICD_ICFGR18"
bitfld.long 0x40 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x40 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x40 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x40 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x40 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x40 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x40 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x40 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x40 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x40 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x40 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x40 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x40 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x40 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x40 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x40 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x44 "GICD_ICFGR19,GICD_ICFGR19"
bitfld.long 0x44 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x44 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x44 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x44 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x44 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x44 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x44 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x44 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x44 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x44 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x44 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x44 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x44 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x44 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x44 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x44 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x48 "GICD_ICFGR20,GICD_ICFGR20"
bitfld.long 0x48 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x48 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x48 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x48 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x48 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x48 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x48 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x48 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x48 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x48 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x48 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x48 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x48 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x48 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x48 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x48 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x4C "GICD_ICFGR21,GICD_ICFGR21"
bitfld.long 0x4C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x4C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x4C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x4C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x4C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x4C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x4C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x4C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x4C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x4C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x4C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x4C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x4C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x4C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x4C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x4C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x50 "GICD_ICFGR22,GICD_ICFGR22"
bitfld.long 0x50 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x50 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x50 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x50 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x50 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x50 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x50 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x50 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x50 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x50 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x50 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x50 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x50 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x50 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x50 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x50 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x54 "GICD_ICFGR23,GICD_ICFGR23"
bitfld.long 0x54 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x54 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x54 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x54 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x54 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x54 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x54 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x54 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x54 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x54 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x54 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x54 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x54 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x54 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x54 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x54 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x58 "GICD_ICFGR24,GICD_ICFGR24"
bitfld.long 0x58 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x58 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x58 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x58 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x58 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x58 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x58 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x58 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x58 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x58 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x58 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x58 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x58 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x58 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x58 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x58 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x5C "GICD_ICFGR25,GICD_ICFGR25"
bitfld.long 0x5C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x5C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x5C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x5C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x5C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x5C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x5C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x5C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x5C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x5C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x5C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x5C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x5C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x5C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x5C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x5C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x60 "GICD_ICFGR26,GICD_ICFGR26"
bitfld.long 0x60 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x60 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x60 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x60 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x60 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x60 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x60 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x60 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x60 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x60 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x60 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x60 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x60 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x60 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x60 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x60 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x64 "GICD_ICFGR27,GICD_ICFGR27"
bitfld.long 0x64 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x64 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x64 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x64 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x64 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x64 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x64 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x64 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x64 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x64 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x64 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x64 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x64 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x64 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x64 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x64 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x68 "GICD_ICFGR28,GICD_ICFGR28"
bitfld.long 0x68 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x68 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x68 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x68 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x68 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x68 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x68 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x68 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x68 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x68 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x68 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x68 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x68 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x68 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x68 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x68 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x6C "GICD_ICFGR29,GICD_ICFGR29"
bitfld.long 0x6C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x6C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x6C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x6C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x6C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x6C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x6C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x6C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x6C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x6C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x6C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x6C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x6C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x6C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x6C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x6C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x70 "GICD_ICFGR30,GICD_ICFGR30"
bitfld.long 0x70 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x70 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x70 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x70 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x70 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x70 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x70 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x70 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x70 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x70 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x70 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x70 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x70 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x70 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x70 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x70 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x74 "GICD_ICFGR31,GICD_ICFGR31"
bitfld.long 0x74 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x74 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x74 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x74 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x74 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x74 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x74 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x74 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x74 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x74 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x74 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x74 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x74 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x74 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x74 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x74 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x78 "GICD_ICFGR32,GICD_ICFGR32"
bitfld.long 0x78 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x78 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x78 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x78 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x78 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x78 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x78 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x78 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x78 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x78 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x78 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x78 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x78 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x78 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x78 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x78 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x7C "GICD_ICFGR33,GICD_ICFGR33"
bitfld.long 0x7C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x7C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x7C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x7C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x7C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x7C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x7C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x7C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x7C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x7C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x7C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x7C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x7C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x7C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x7C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x7C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x80 "GICD_ICFGR34,GICD_ICFGR34"
bitfld.long 0x80 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x80 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x80 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x80 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x80 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x80 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x80 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x80 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x80 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x80 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x80 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x80 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x80 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x80 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x80 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x80 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x84 "GICD_ICFGR35,GICD_ICFGR35"
bitfld.long 0x84 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x84 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x84 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x84 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x84 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x84 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x84 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x84 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x84 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x84 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x84 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x84 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x84 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x84 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x84 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x84 0.--1. "int_config0,int_config0" "0,1,2,3"
group.long 0xD04++0x43
line.long 0x0 "GICD_IGRPMODR1,GICD_IGRPMODR1"
bitfld.long 0x0 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x0 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x0 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x0 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x0 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x0 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x0 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x0 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x0 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x0 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x0 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x0 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x0 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x0 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x0 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x0 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x0 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x4 "GICD_IGRPMODR2,GICD_IGRPMODR2"
bitfld.long 0x4 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x4 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x4 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x4 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x4 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x4 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x4 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x4 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x4 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x4 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x4 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x4 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x4 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x4 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x4 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x4 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x4 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x4 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x4 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x4 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x4 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x4 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x4 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x4 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x4 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x4 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x4 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x4 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x4 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x4 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x4 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x4 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x8 "GICD_IGRPMODR3,GICD_IGRPMODR3"
bitfld.long 0x8 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x8 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x8 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x8 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x8 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x8 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x8 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x8 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x8 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x8 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x8 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x8 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x8 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x8 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x8 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x8 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x8 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x8 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x8 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x8 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x8 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x8 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x8 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x8 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x8 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x8 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x8 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x8 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x8 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x8 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x8 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x8 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0xC "GICD_IGRPMODR4,GICD_IGRPMODR4"
bitfld.long 0xC 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0xC 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0xC 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0xC 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0xC 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0xC 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0xC 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0xC 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0xC 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0xC 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0xC 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0xC 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0xC 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0xC 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0xC 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0xC 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0xC 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0xC 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0xC 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0xC 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0xC 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0xC 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0xC 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0xC 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0xC 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0xC 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0xC 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0xC 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0xC 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0xC 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0xC 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0xC 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x10 "GICD_IGRPMODR5,GICD_IGRPMODR5"
bitfld.long 0x10 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x10 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x10 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x10 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x10 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x10 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x10 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x10 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x10 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x10 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x10 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x10 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x10 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x10 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x10 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x10 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x10 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x10 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x10 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x10 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x10 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x10 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x10 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x10 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x10 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x10 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x10 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x10 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x10 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x10 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x10 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x10 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x14 "GICD_IGRPMODR6,GICD_IGRPMODR6"
bitfld.long 0x14 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x14 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x14 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x14 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x14 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x14 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x14 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x14 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x14 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x14 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x14 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x14 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x14 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x14 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x14 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x14 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x14 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x14 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x14 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x14 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x14 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x14 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x14 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x14 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x14 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x14 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x14 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x14 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x14 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x14 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x14 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x14 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x18 "GICD_IGRPMODR7,GICD_IGRPMODR7"
bitfld.long 0x18 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x18 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x18 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x18 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x18 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x18 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x18 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x18 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x18 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x18 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x18 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x18 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x18 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x18 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x18 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x18 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x18 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x18 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x18 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x18 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x18 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x18 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x18 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x18 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x18 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x18 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x18 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x18 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x18 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x18 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x18 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x18 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x1C "GICD_IGRPMODR8,GICD_IGRPMODR8"
bitfld.long 0x1C 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x1C 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x1C 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x1C 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x1C 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x1C 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x1C 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x1C 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x1C 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x1C 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x1C 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x1C 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x1C 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x1C 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x1C 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x1C 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x1C 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x1C 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x1C 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x1C 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x1C 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x1C 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x1C 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x1C 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x1C 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x1C 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x1C 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x1C 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x1C 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x1C 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x1C 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x1C 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x20 "GICD_IGRPMODR9,GICD_IGRPMODR9"
bitfld.long 0x20 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x20 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x20 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x20 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x20 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x20 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x20 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x20 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x20 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x20 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x20 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x20 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x20 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x20 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x20 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x20 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x20 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x20 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x20 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x20 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x20 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x20 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x20 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x20 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x20 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x20 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x20 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x20 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x20 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x20 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x20 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x20 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x24 "GICD_IGRPMODR10,GICD_IGRPMODR10"
bitfld.long 0x24 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x24 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x24 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x24 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x24 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x24 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x24 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x24 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x24 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x24 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x24 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x24 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x24 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x24 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x24 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x24 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x24 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x24 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x24 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x24 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x24 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x24 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x24 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x24 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x24 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x24 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x24 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x24 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x24 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x24 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x24 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x24 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x28 "GICD_IGRPMODR11,GICD_IGRPMODR11"
bitfld.long 0x28 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x28 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x28 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x28 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x28 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x28 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x28 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x28 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x28 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x28 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x28 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x28 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x28 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x28 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x28 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x28 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x28 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x28 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x28 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x28 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x28 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x28 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x28 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x28 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x28 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x28 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x28 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x28 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x28 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x28 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x28 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x28 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x2C "GICD_IGRPMODR12,GICD_IGRPMODR12"
bitfld.long 0x2C 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x2C 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x2C 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x2C 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x2C 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x2C 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x2C 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x2C 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x2C 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x2C 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x2C 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x2C 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x2C 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x2C 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x2C 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x2C 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x2C 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x2C 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x2C 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x2C 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x2C 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x2C 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x2C 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x2C 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x2C 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x2C 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x2C 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x2C 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x2C 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x2C 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x2C 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x2C 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x30 "GICD_IGRPMODR13,GICD_IGRPMODR13"
bitfld.long 0x30 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x30 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x30 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x30 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x30 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x30 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x30 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x30 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x30 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x30 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x30 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x30 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x30 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x30 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x30 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x30 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x30 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x30 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x30 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x30 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x30 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x30 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x30 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x30 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x30 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x30 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x30 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x30 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x30 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x30 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x30 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x30 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x34 "GICD_IGRPMODR14,GICD_IGRPMODR14"
bitfld.long 0x34 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x34 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x34 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x34 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x34 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x34 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x34 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x34 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x34 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x34 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x34 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x34 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x34 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x34 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x34 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x34 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x34 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x34 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x34 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x34 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x34 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x34 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x34 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x34 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x34 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x34 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x34 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x34 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x34 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x34 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x34 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x34 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x38 "GICD_IGRPMODR15,GICD_IGRPMODR15"
bitfld.long 0x38 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x38 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x38 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x38 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x38 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x38 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x38 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x38 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x38 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x38 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x38 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x38 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x38 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x38 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x38 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x38 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x38 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x38 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x38 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x38 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x38 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x38 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x38 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x38 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x38 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x38 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x38 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x38 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x38 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x38 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x38 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x38 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x3C "GICD_IGRPMODR16,GICD_IGRPMODR16"
bitfld.long 0x3C 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x3C 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x3C 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x3C 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x3C 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x3C 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x3C 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x3C 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x3C 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x3C 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x3C 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x3C 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x3C 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x3C 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x3C 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x3C 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x3C 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x3C 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x3C 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x3C 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x3C 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x3C 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x3C 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x3C 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x3C 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x3C 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x3C 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x3C 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x3C 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x3C 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x3C 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x3C 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x40 "GICD_IGRPMODR17,GICD_IGRPMODR17"
bitfld.long 0x40 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x40 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x40 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x40 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x40 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x40 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x40 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x40 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x40 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x40 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x40 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x40 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x40 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x40 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x40 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x40 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x40 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x40 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x40 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x40 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x40 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x40 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x40 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x40 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x40 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x40 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x40 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x40 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x40 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x40 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x40 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x40 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
group.long 0xE08++0x87
line.long 0x0 "GICD_NSACR2,GICD_NSACR2"
bitfld.long 0x0 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x0 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x0 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x0 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x0 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x0 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x0 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x0 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x0 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x4 "GICD_NSACR3,GICD_NSACR3"
bitfld.long 0x4 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x4 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x4 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x4 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x4 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x4 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x4 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x4 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x4 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x4 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x4 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x4 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x8 "GICD_NSACR4,GICD_NSACR4"
bitfld.long 0x8 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x8 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x8 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x8 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x8 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x8 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x8 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x8 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x8 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x8 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x8 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x8 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x8 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x8 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0xC "GICD_NSACR5,GICD_NSACR5"
bitfld.long 0xC 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0xC 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0xC 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0xC 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0xC 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0xC 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0xC 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0xC 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0xC 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0xC 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0xC 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0xC 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x10 "GICD_NSACR6,GICD_NSACR6"
bitfld.long 0x10 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x10 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x10 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x10 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x10 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x10 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x10 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x10 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x10 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x10 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x10 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x10 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x10 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x14 "GICD_NSACR7,GICD_NSACR7"
bitfld.long 0x14 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x14 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x14 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x14 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x14 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x14 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x14 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x14 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x14 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x14 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x14 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x14 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x14 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x14 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x14 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x18 "GICD_NSACR8,GICD_NSACR8"
bitfld.long 0x18 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x18 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x18 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x18 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x18 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x18 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x18 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x18 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x18 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x18 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x18 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x18 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x18 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x18 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x18 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x1C "GICD_NSACR9,GICD_NSACR9"
bitfld.long 0x1C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x1C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x1C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x1C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x1C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x1C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x1C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x1C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x1C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x1C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x1C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x1C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x1C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x1C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x20 "GICD_NSACR10,GICD_NSACR10"
bitfld.long 0x20 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x20 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x20 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x20 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x20 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x20 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x20 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x20 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x20 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x20 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x20 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x20 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x20 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x20 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x20 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x20 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x24 "GICD_NSACR11,GICD_NSACR11"
bitfld.long 0x24 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x24 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x24 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x24 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x24 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x24 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x24 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x24 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x24 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x24 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x24 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x24 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x24 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x24 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x24 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x28 "GICD_NSACR12,GICD_NSACR12"
bitfld.long 0x28 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x28 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x28 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x28 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x28 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x28 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x28 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x28 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x28 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x28 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x28 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x28 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x28 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x28 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x28 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x28 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x2C "GICD_NSACR13,GICD_NSACR13"
bitfld.long 0x2C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x2C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x2C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x2C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x2C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x2C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x2C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x2C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x2C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x2C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x2C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x2C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x2C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x2C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x2C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x2C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x30 "GICD_NSACR14,GICD_NSACR14"
bitfld.long 0x30 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x30 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x30 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x30 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x30 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x30 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x30 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x30 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x30 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x30 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x30 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x30 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x30 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x30 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x30 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x30 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x34 "GICD_NSACR15,GICD_NSACR15"
bitfld.long 0x34 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x34 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x34 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x34 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x34 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x34 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x34 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x34 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x34 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x34 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x34 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x34 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x34 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x34 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x34 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x38 "GICD_NSACR16,GICD_NSACR16"
bitfld.long 0x38 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x38 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x38 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x38 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x38 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x38 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x38 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x38 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x38 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x38 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x38 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x38 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x38 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x38 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x38 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x38 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x3C "GICD_NSACR17,GICD_NSACR17"
bitfld.long 0x3C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x3C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x3C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x3C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x3C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x3C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x3C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x3C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x3C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x3C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x3C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x3C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x3C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x3C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x3C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x3C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x40 "GICD_NSACR18,GICD_NSACR18"
bitfld.long 0x40 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x40 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x40 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x40 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x40 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x40 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x40 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x40 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x40 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x40 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x40 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x40 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x40 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x40 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x40 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x40 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x44 "GICD_NSACR19,GICD_NSACR19"
bitfld.long 0x44 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x44 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x44 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x44 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x44 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x44 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x44 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x44 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x44 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x44 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x44 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x44 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x44 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x44 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x44 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x44 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x48 "GICD_NSACR20,GICD_NSACR20"
bitfld.long 0x48 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x48 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x48 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x48 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x48 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x48 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x48 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x48 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x48 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x48 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x48 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x48 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x48 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x48 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x48 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x48 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x4C "GICD_NSACR21,GICD_NSACR21"
bitfld.long 0x4C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x4C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x4C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x4C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x4C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x4C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x4C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x4C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x4C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x4C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x4C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x4C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x4C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x4C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x4C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x4C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x50 "GICD_NSACR22,GICD_NSACR22"
bitfld.long 0x50 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x50 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x50 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x50 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x50 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x50 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x50 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x50 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x50 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x50 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x50 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x50 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x50 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x50 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x50 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x50 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x54 "GICD_NSACR23,GICD_NSACR23"
bitfld.long 0x54 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x54 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x54 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x54 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x54 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x54 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x54 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x54 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x54 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x54 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x54 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x54 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x54 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x54 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x54 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x54 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x58 "GICD_NSACR24,GICD_NSACR24"
bitfld.long 0x58 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x58 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x58 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x58 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x58 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x58 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x58 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x58 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x58 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x58 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x58 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x58 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x58 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x58 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x58 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x58 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x5C "GICD_NSACR25,GICD_NSACR25"
bitfld.long 0x5C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x5C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x5C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x5C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x5C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x5C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x5C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x5C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x5C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x5C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x5C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x5C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x5C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x5C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x5C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x5C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x60 "GICD_NSACR26,GICD_NSACR26"
bitfld.long 0x60 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x60 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x60 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x60 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x60 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x60 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x60 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x60 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x60 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x60 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x60 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x60 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x60 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x60 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x60 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x60 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x64 "GICD_NSACR27,GICD_NSACR27"
bitfld.long 0x64 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x64 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x64 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x64 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x64 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x64 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x64 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x64 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x64 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x64 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x64 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x64 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x64 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x64 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x64 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x64 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x68 "GICD_NSACR28,GICD_NSACR28"
bitfld.long 0x68 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x68 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x68 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x68 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x68 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x68 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x68 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x68 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x68 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x68 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x68 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x68 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x68 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x68 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x68 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x68 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x6C "GICD_NSACR29,GICD_NSACR29"
bitfld.long 0x6C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x6C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x6C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x6C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x6C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x6C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x6C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x6C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x6C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x6C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x6C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x6C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x6C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x6C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x6C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x6C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x70 "GICD_NSACR30,GICD_NSACR30"
bitfld.long 0x70 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x70 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x70 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x70 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x70 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x70 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x70 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x70 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x70 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x70 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x70 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x70 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x70 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x70 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x70 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x70 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x74 "GICD_NSACR31,GICD_NSACR31"
bitfld.long 0x74 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x74 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x74 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x74 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x74 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x74 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x74 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x74 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x74 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x74 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x74 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x74 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x74 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x74 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x74 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x74 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x78 "GICD_NSACR32,GICD_NSACR32"
bitfld.long 0x78 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x78 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x78 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x78 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x78 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x78 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x78 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x78 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x78 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x78 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x78 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x78 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x78 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x78 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x78 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x78 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x7C "GICD_NSACR33,GICD_NSACR33"
bitfld.long 0x7C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x7C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x7C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x7C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x7C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x7C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x7C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x7C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x7C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x7C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x7C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x7C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x7C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x7C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x7C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x7C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x80 "GICD_NSACR34,GICD_NSACR34"
bitfld.long 0x80 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x80 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x80 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x80 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x80 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x80 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x80 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x80 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x80 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x80 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x80 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x80 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x80 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x80 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x80 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x80 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x84 "GICD_NSACR35,GICD_NSACR35"
bitfld.long 0x84 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x84 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x84 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x84 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x84 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x84 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x84 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x84 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x84 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x84 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x84 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x84 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x84 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x84 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x84 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x84 0.--1. "ns_access0,ns_access0" "0,1,2,3"
group.quad 0x6100++0xFFF
line.quad 0x0 "GICD_IROUTER32,GICD_IROUTER32"
hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8 "GICD_IROUTER33,GICD_IROUTER33"
hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x10 "GICD_IROUTER34,GICD_IROUTER34"
hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x18 "GICD_IROUTER35,GICD_IROUTER35"
hexmask.quad.tbyte 0x18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x20 "GICD_IROUTER36,GICD_IROUTER36"
hexmask.quad.tbyte 0x20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x28 "GICD_IROUTER37,GICD_IROUTER37"
hexmask.quad.tbyte 0x28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x30 "GICD_IROUTER38,GICD_IROUTER38"
hexmask.quad.tbyte 0x30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x38 "GICD_IROUTER39,GICD_IROUTER39"
hexmask.quad.tbyte 0x38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x40 "GICD_IROUTER40,GICD_IROUTER40"
hexmask.quad.tbyte 0x40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x48 "GICD_IROUTER41,GICD_IROUTER41"
hexmask.quad.tbyte 0x48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x50 "GICD_IROUTER42,GICD_IROUTER42"
hexmask.quad.tbyte 0x50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x58 "GICD_IROUTER43,GICD_IROUTER43"
hexmask.quad.tbyte 0x58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x60 "GICD_IROUTER44,GICD_IROUTER44"
hexmask.quad.tbyte 0x60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x68 "GICD_IROUTER45,GICD_IROUTER45"
hexmask.quad.tbyte 0x68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x70 "GICD_IROUTER46,GICD_IROUTER46"
hexmask.quad.tbyte 0x70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x78 "GICD_IROUTER47,GICD_IROUTER47"
hexmask.quad.tbyte 0x78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x80 "GICD_IROUTER48,GICD_IROUTER48"
hexmask.quad.tbyte 0x80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x88 "GICD_IROUTER49,GICD_IROUTER49"
hexmask.quad.tbyte 0x88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x90 "GICD_IROUTER50,GICD_IROUTER50"
hexmask.quad.tbyte 0x90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x98 "GICD_IROUTER51,GICD_IROUTER51"
hexmask.quad.tbyte 0x98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA0 "GICD_IROUTER52,GICD_IROUTER52"
hexmask.quad.tbyte 0xA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA8 "GICD_IROUTER53,GICD_IROUTER53"
hexmask.quad.tbyte 0xA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB0 "GICD_IROUTER54,GICD_IROUTER54"
hexmask.quad.tbyte 0xB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB8 "GICD_IROUTER55,GICD_IROUTER55"
hexmask.quad.tbyte 0xB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC0 "GICD_IROUTER56,GICD_IROUTER56"
hexmask.quad.tbyte 0xC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC8 "GICD_IROUTER57,GICD_IROUTER57"
hexmask.quad.tbyte 0xC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD0 "GICD_IROUTER58,GICD_IROUTER58"
hexmask.quad.tbyte 0xD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD8 "GICD_IROUTER59,GICD_IROUTER59"
hexmask.quad.tbyte 0xD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE0 "GICD_IROUTER60,GICD_IROUTER60"
hexmask.quad.tbyte 0xE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE8 "GICD_IROUTER61,GICD_IROUTER61"
hexmask.quad.tbyte 0xE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF0 "GICD_IROUTER62,GICD_IROUTER62"
hexmask.quad.tbyte 0xF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF8 "GICD_IROUTER63,GICD_IROUTER63"
hexmask.quad.tbyte 0xF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x100 "GICD_IROUTER64,GICD_IROUTER64"
hexmask.quad.tbyte 0x100 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x100 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x100 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x100 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x100 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x100 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x100 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x108 "GICD_IROUTER65,GICD_IROUTER65"
hexmask.quad.tbyte 0x108 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x108 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x108 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x108 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x108 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x108 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x108 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x110 "GICD_IROUTER66,GICD_IROUTER66"
hexmask.quad.tbyte 0x110 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x110 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x110 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x110 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x110 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x110 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x110 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x118 "GICD_IROUTER67,GICD_IROUTER67"
hexmask.quad.tbyte 0x118 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x118 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x118 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x118 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x118 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x118 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x118 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x120 "GICD_IROUTER68,GICD_IROUTER68"
hexmask.quad.tbyte 0x120 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x120 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x120 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x120 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x120 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x120 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x120 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x128 "GICD_IROUTER69,GICD_IROUTER69"
hexmask.quad.tbyte 0x128 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x128 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x128 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x128 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x128 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x128 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x128 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x130 "GICD_IROUTER70,GICD_IROUTER70"
hexmask.quad.tbyte 0x130 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x130 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x130 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x130 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x130 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x130 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x130 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x138 "GICD_IROUTER71,GICD_IROUTER71"
hexmask.quad.tbyte 0x138 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x138 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x138 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x138 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x138 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x138 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x138 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x140 "GICD_IROUTER72,GICD_IROUTER72"
hexmask.quad.tbyte 0x140 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x140 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x140 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x140 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x140 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x140 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x140 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x148 "GICD_IROUTER73,GICD_IROUTER73"
hexmask.quad.tbyte 0x148 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x148 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x148 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x148 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x148 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x148 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x148 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x150 "GICD_IROUTER74,GICD_IROUTER74"
hexmask.quad.tbyte 0x150 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x150 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x150 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x150 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x150 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x150 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x150 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x158 "GICD_IROUTER75,GICD_IROUTER75"
hexmask.quad.tbyte 0x158 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x158 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x158 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x158 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x158 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x158 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x158 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x160 "GICD_IROUTER76,GICD_IROUTER76"
hexmask.quad.tbyte 0x160 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x160 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x160 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x160 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x160 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x160 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x160 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x168 "GICD_IROUTER77,GICD_IROUTER77"
hexmask.quad.tbyte 0x168 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x168 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x168 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x168 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x168 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x168 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x168 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x170 "GICD_IROUTER78,GICD_IROUTER78"
hexmask.quad.tbyte 0x170 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x170 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x170 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x170 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x170 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x170 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x170 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x178 "GICD_IROUTER79,GICD_IROUTER79"
hexmask.quad.tbyte 0x178 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x178 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x178 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x178 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x178 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x178 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x178 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x180 "GICD_IROUTER80,GICD_IROUTER80"
hexmask.quad.tbyte 0x180 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x180 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x180 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x180 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x180 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x180 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x180 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x188 "GICD_IROUTER81,GICD_IROUTER81"
hexmask.quad.tbyte 0x188 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x188 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x188 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x188 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x188 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x188 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x188 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x190 "GICD_IROUTER82,GICD_IROUTER82"
hexmask.quad.tbyte 0x190 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x190 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x190 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x190 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x190 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x190 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x190 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x198 "GICD_IROUTER83,GICD_IROUTER83"
hexmask.quad.tbyte 0x198 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x198 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x198 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x198 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x198 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x198 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x198 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1A0 "GICD_IROUTER84,GICD_IROUTER84"
hexmask.quad.tbyte 0x1A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1A8 "GICD_IROUTER85,GICD_IROUTER85"
hexmask.quad.tbyte 0x1A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1B0 "GICD_IROUTER86,GICD_IROUTER86"
hexmask.quad.tbyte 0x1B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1B8 "GICD_IROUTER87,GICD_IROUTER87"
hexmask.quad.tbyte 0x1B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1C0 "GICD_IROUTER88,GICD_IROUTER88"
hexmask.quad.tbyte 0x1C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1C8 "GICD_IROUTER89,GICD_IROUTER89"
hexmask.quad.tbyte 0x1C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1D0 "GICD_IROUTER90,GICD_IROUTER90"
hexmask.quad.tbyte 0x1D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1D8 "GICD_IROUTER91,GICD_IROUTER91"
hexmask.quad.tbyte 0x1D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1E0 "GICD_IROUTER92,GICD_IROUTER92"
hexmask.quad.tbyte 0x1E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1E8 "GICD_IROUTER93,GICD_IROUTER93"
hexmask.quad.tbyte 0x1E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1F0 "GICD_IROUTER94,GICD_IROUTER94"
hexmask.quad.tbyte 0x1F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1F8 "GICD_IROUTER95,GICD_IROUTER95"
hexmask.quad.tbyte 0x1F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x200 "GICD_IROUTER96,GICD_IROUTER96"
hexmask.quad.tbyte 0x200 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x200 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x200 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x200 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x200 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x200 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x200 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x208 "GICD_IROUTER97,GICD_IROUTER97"
hexmask.quad.tbyte 0x208 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x208 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x208 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x208 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x208 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x208 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x208 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x210 "GICD_IROUTER98,GICD_IROUTER98"
hexmask.quad.tbyte 0x210 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x210 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x210 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x210 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x210 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x210 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x210 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x218 "GICD_IROUTER99,GICD_IROUTER99"
hexmask.quad.tbyte 0x218 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x218 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x218 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x218 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x218 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x218 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x218 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x220 "GICD_IROUTER100,GICD_IROUTER100"
hexmask.quad.tbyte 0x220 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x220 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x220 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x220 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x220 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x220 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x220 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x228 "GICD_IROUTER101,GICD_IROUTER101"
hexmask.quad.tbyte 0x228 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x228 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x228 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x228 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x228 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x228 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x228 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x230 "GICD_IROUTER102,GICD_IROUTER102"
hexmask.quad.tbyte 0x230 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x230 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x230 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x230 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x230 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x230 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x230 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x238 "GICD_IROUTER103,GICD_IROUTER103"
hexmask.quad.tbyte 0x238 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x238 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x238 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x238 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x238 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x238 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x238 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x240 "GICD_IROUTER104,GICD_IROUTER104"
hexmask.quad.tbyte 0x240 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x240 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x240 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x240 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x240 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x240 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x240 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x248 "GICD_IROUTER105,GICD_IROUTER105"
hexmask.quad.tbyte 0x248 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x248 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x248 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x248 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x248 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x248 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x248 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x250 "GICD_IROUTER106,GICD_IROUTER106"
hexmask.quad.tbyte 0x250 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x250 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x250 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x250 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x250 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x250 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x250 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x258 "GICD_IROUTER107,GICD_IROUTER107"
hexmask.quad.tbyte 0x258 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x258 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x258 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x258 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x258 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x258 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x258 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x260 "GICD_IROUTER108,GICD_IROUTER108"
hexmask.quad.tbyte 0x260 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x260 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x260 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x260 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x260 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x260 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x260 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x268 "GICD_IROUTER109,GICD_IROUTER109"
hexmask.quad.tbyte 0x268 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x268 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x268 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x268 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x268 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x268 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x268 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x270 "GICD_IROUTER110,GICD_IROUTER110"
hexmask.quad.tbyte 0x270 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x270 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x270 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x270 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x270 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x270 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x270 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x278 "GICD_IROUTER111,GICD_IROUTER111"
hexmask.quad.tbyte 0x278 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x278 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x278 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x278 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x278 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x278 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x278 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x280 "GICD_IROUTER112,GICD_IROUTER112"
hexmask.quad.tbyte 0x280 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x280 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x280 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x280 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x280 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x280 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x280 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x288 "GICD_IROUTER113,GICD_IROUTER113"
hexmask.quad.tbyte 0x288 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x288 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x288 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x288 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x288 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x288 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x288 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x290 "GICD_IROUTER114,GICD_IROUTER114"
hexmask.quad.tbyte 0x290 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x290 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x290 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x290 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x290 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x290 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x290 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x298 "GICD_IROUTER115,GICD_IROUTER115"
hexmask.quad.tbyte 0x298 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x298 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x298 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x298 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x298 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x298 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x298 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2A0 "GICD_IROUTER116,GICD_IROUTER116"
hexmask.quad.tbyte 0x2A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2A8 "GICD_IROUTER117,GICD_IROUTER117"
hexmask.quad.tbyte 0x2A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2B0 "GICD_IROUTER118,GICD_IROUTER118"
hexmask.quad.tbyte 0x2B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2B8 "GICD_IROUTER119,GICD_IROUTER119"
hexmask.quad.tbyte 0x2B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2C0 "GICD_IROUTER120,GICD_IROUTER120"
hexmask.quad.tbyte 0x2C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2C8 "GICD_IROUTER121,GICD_IROUTER121"
hexmask.quad.tbyte 0x2C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2D0 "GICD_IROUTER122,GICD_IROUTER122"
hexmask.quad.tbyte 0x2D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2D8 "GICD_IROUTER123,GICD_IROUTER123"
hexmask.quad.tbyte 0x2D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2E0 "GICD_IROUTER124,GICD_IROUTER124"
hexmask.quad.tbyte 0x2E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2E8 "GICD_IROUTER125,GICD_IROUTER125"
hexmask.quad.tbyte 0x2E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2F0 "GICD_IROUTER126,GICD_IROUTER126"
hexmask.quad.tbyte 0x2F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2F8 "GICD_IROUTER127,GICD_IROUTER127"
hexmask.quad.tbyte 0x2F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x300 "GICD_IROUTER128,GICD_IROUTER128"
hexmask.quad.tbyte 0x300 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x300 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x300 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x300 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x300 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x300 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x300 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x308 "GICD_IROUTER129,GICD_IROUTER129"
hexmask.quad.tbyte 0x308 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x308 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x308 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x308 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x308 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x308 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x308 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x310 "GICD_IROUTER130,GICD_IROUTER130"
hexmask.quad.tbyte 0x310 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x310 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x310 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x310 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x310 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x310 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x310 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x318 "GICD_IROUTER131,GICD_IROUTER131"
hexmask.quad.tbyte 0x318 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x318 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x318 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x318 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x318 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x318 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x318 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x320 "GICD_IROUTER132,GICD_IROUTER132"
hexmask.quad.tbyte 0x320 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x320 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x320 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x320 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x320 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x320 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x320 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x328 "GICD_IROUTER133,GICD_IROUTER133"
hexmask.quad.tbyte 0x328 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x328 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x328 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x328 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x328 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x328 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x328 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x330 "GICD_IROUTER134,GICD_IROUTER134"
hexmask.quad.tbyte 0x330 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x330 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x330 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x330 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x330 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x330 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x330 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x338 "GICD_IROUTER135,GICD_IROUTER135"
hexmask.quad.tbyte 0x338 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x338 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x338 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x338 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x338 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x338 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x338 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x340 "GICD_IROUTER136,GICD_IROUTER136"
hexmask.quad.tbyte 0x340 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x340 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x340 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x340 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x340 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x340 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x340 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x348 "GICD_IROUTER137,GICD_IROUTER137"
hexmask.quad.tbyte 0x348 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x348 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x348 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x348 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x348 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x348 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x348 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x350 "GICD_IROUTER138,GICD_IROUTER138"
hexmask.quad.tbyte 0x350 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x350 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x350 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x350 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x350 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x350 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x350 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x358 "GICD_IROUTER139,GICD_IROUTER139"
hexmask.quad.tbyte 0x358 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x358 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x358 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x358 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x358 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x358 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x358 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x360 "GICD_IROUTER140,GICD_IROUTER140"
hexmask.quad.tbyte 0x360 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x360 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x360 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x360 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x360 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x360 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x360 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x368 "GICD_IROUTER141,GICD_IROUTER141"
hexmask.quad.tbyte 0x368 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x368 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x368 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x368 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x368 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x368 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x368 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x370 "GICD_IROUTER142,GICD_IROUTER142"
hexmask.quad.tbyte 0x370 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x370 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x370 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x370 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x370 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x370 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x370 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x378 "GICD_IROUTER143,GICD_IROUTER143"
hexmask.quad.tbyte 0x378 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x378 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x378 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x378 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x378 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x378 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x378 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x380 "GICD_IROUTER144,GICD_IROUTER144"
hexmask.quad.tbyte 0x380 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x380 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x380 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x380 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x380 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x380 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x380 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x388 "GICD_IROUTER145,GICD_IROUTER145"
hexmask.quad.tbyte 0x388 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x388 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x388 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x388 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x388 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x388 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x388 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x390 "GICD_IROUTER146,GICD_IROUTER146"
hexmask.quad.tbyte 0x390 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x390 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x390 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x390 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x390 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x390 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x390 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x398 "GICD_IROUTER147,GICD_IROUTER147"
hexmask.quad.tbyte 0x398 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x398 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x398 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x398 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x398 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x398 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x398 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3A0 "GICD_IROUTER148,GICD_IROUTER148"
hexmask.quad.tbyte 0x3A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3A8 "GICD_IROUTER149,GICD_IROUTER149"
hexmask.quad.tbyte 0x3A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3B0 "GICD_IROUTER150,GICD_IROUTER150"
hexmask.quad.tbyte 0x3B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3B8 "GICD_IROUTER151,GICD_IROUTER151"
hexmask.quad.tbyte 0x3B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3C0 "GICD_IROUTER152,GICD_IROUTER152"
hexmask.quad.tbyte 0x3C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3C8 "GICD_IROUTER153,GICD_IROUTER153"
hexmask.quad.tbyte 0x3C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3D0 "GICD_IROUTER154,GICD_IROUTER154"
hexmask.quad.tbyte 0x3D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3D8 "GICD_IROUTER155,GICD_IROUTER155"
hexmask.quad.tbyte 0x3D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3E0 "GICD_IROUTER156,GICD_IROUTER156"
hexmask.quad.tbyte 0x3E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3E8 "GICD_IROUTER157,GICD_IROUTER157"
hexmask.quad.tbyte 0x3E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3F0 "GICD_IROUTER158,GICD_IROUTER158"
hexmask.quad.tbyte 0x3F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3F8 "GICD_IROUTER159,GICD_IROUTER159"
hexmask.quad.tbyte 0x3F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x400 "GICD_IROUTER160,GICD_IROUTER160"
hexmask.quad.tbyte 0x400 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x400 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x400 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x400 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x400 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x400 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x400 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x408 "GICD_IROUTER161,GICD_IROUTER161"
hexmask.quad.tbyte 0x408 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x408 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x408 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x408 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x408 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x408 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x408 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x410 "GICD_IROUTER162,GICD_IROUTER162"
hexmask.quad.tbyte 0x410 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x410 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x410 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x410 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x410 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x410 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x410 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x418 "GICD_IROUTER163,GICD_IROUTER163"
hexmask.quad.tbyte 0x418 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x418 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x418 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x418 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x418 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x418 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x418 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x420 "GICD_IROUTER164,GICD_IROUTER164"
hexmask.quad.tbyte 0x420 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x420 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x420 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x420 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x420 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x420 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x420 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x428 "GICD_IROUTER165,GICD_IROUTER165"
hexmask.quad.tbyte 0x428 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x428 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x428 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x428 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x428 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x428 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x428 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x430 "GICD_IROUTER166,GICD_IROUTER166"
hexmask.quad.tbyte 0x430 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x430 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x430 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x430 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x430 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x430 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x430 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x438 "GICD_IROUTER167,GICD_IROUTER167"
hexmask.quad.tbyte 0x438 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x438 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x438 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x438 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x438 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x438 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x438 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x440 "GICD_IROUTER168,GICD_IROUTER168"
hexmask.quad.tbyte 0x440 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x440 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x440 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x440 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x440 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x440 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x440 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x448 "GICD_IROUTER169,GICD_IROUTER169"
hexmask.quad.tbyte 0x448 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x448 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x448 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x448 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x448 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x448 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x448 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x450 "GICD_IROUTER170,GICD_IROUTER170"
hexmask.quad.tbyte 0x450 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x450 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x450 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x450 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x450 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x450 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x450 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x458 "GICD_IROUTER171,GICD_IROUTER171"
hexmask.quad.tbyte 0x458 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x458 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x458 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x458 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x458 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x458 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x458 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x460 "GICD_IROUTER172,GICD_IROUTER172"
hexmask.quad.tbyte 0x460 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x460 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x460 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x460 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x460 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x460 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x460 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x468 "GICD_IROUTER173,GICD_IROUTER173"
hexmask.quad.tbyte 0x468 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x468 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x468 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x468 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x468 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x468 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x468 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x470 "GICD_IROUTER174,GICD_IROUTER174"
hexmask.quad.tbyte 0x470 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x470 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x470 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x470 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x470 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x470 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x470 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x478 "GICD_IROUTER175,GICD_IROUTER175"
hexmask.quad.tbyte 0x478 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x478 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x478 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x478 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x478 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x478 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x478 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x480 "GICD_IROUTER176,GICD_IROUTER176"
hexmask.quad.tbyte 0x480 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x480 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x480 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x480 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x480 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x480 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x480 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x488 "GICD_IROUTER177,GICD_IROUTER177"
hexmask.quad.tbyte 0x488 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x488 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x488 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x488 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x488 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x488 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x488 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x490 "GICD_IROUTER178,GICD_IROUTER178"
hexmask.quad.tbyte 0x490 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x490 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x490 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x490 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x490 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x490 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x490 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x498 "GICD_IROUTER179,GICD_IROUTER179"
hexmask.quad.tbyte 0x498 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x498 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x498 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x498 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x498 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x498 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x498 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4A0 "GICD_IROUTER180,GICD_IROUTER180"
hexmask.quad.tbyte 0x4A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4A8 "GICD_IROUTER181,GICD_IROUTER181"
hexmask.quad.tbyte 0x4A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4B0 "GICD_IROUTER182,GICD_IROUTER182"
hexmask.quad.tbyte 0x4B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4B8 "GICD_IROUTER183,GICD_IROUTER183"
hexmask.quad.tbyte 0x4B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4C0 "GICD_IROUTER184,GICD_IROUTER184"
hexmask.quad.tbyte 0x4C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4C8 "GICD_IROUTER185,GICD_IROUTER185"
hexmask.quad.tbyte 0x4C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4D0 "GICD_IROUTER186,GICD_IROUTER186"
hexmask.quad.tbyte 0x4D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4D8 "GICD_IROUTER187,GICD_IROUTER187"
hexmask.quad.tbyte 0x4D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4E0 "GICD_IROUTER188,GICD_IROUTER188"
hexmask.quad.tbyte 0x4E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4E8 "GICD_IROUTER189,GICD_IROUTER189"
hexmask.quad.tbyte 0x4E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4F0 "GICD_IROUTER190,GICD_IROUTER190"
hexmask.quad.tbyte 0x4F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4F8 "GICD_IROUTER191,GICD_IROUTER191"
hexmask.quad.tbyte 0x4F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x500 "GICD_IROUTER192,GICD_IROUTER192"
hexmask.quad.tbyte 0x500 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x500 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x500 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x500 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x500 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x500 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x500 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x508 "GICD_IROUTER193,GICD_IROUTER193"
hexmask.quad.tbyte 0x508 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x508 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x508 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x508 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x508 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x508 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x508 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x510 "GICD_IROUTER194,GICD_IROUTER194"
hexmask.quad.tbyte 0x510 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x510 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x510 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x510 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x510 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x510 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x510 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x518 "GICD_IROUTER195,GICD_IROUTER195"
hexmask.quad.tbyte 0x518 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x518 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x518 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x518 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x518 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x518 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x518 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x520 "GICD_IROUTER196,GICD_IROUTER196"
hexmask.quad.tbyte 0x520 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x520 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x520 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x520 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x520 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x520 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x520 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x528 "GICD_IROUTER197,GICD_IROUTER197"
hexmask.quad.tbyte 0x528 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x528 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x528 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x528 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x528 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x528 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x528 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x530 "GICD_IROUTER198,GICD_IROUTER198"
hexmask.quad.tbyte 0x530 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x530 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x530 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x530 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x530 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x530 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x530 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x538 "GICD_IROUTER199,GICD_IROUTER199"
hexmask.quad.tbyte 0x538 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x538 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x538 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x538 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x538 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x538 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x538 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x540 "GICD_IROUTER200,GICD_IROUTER200"
hexmask.quad.tbyte 0x540 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x540 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x540 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x540 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x540 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x540 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x540 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x548 "GICD_IROUTER201,GICD_IROUTER201"
hexmask.quad.tbyte 0x548 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x548 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x548 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x548 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x548 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x548 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x548 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x550 "GICD_IROUTER202,GICD_IROUTER202"
hexmask.quad.tbyte 0x550 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x550 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x550 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x550 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x550 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x550 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x550 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x558 "GICD_IROUTER203,GICD_IROUTER203"
hexmask.quad.tbyte 0x558 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x558 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x558 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x558 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x558 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x558 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x558 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x560 "GICD_IROUTER204,GICD_IROUTER204"
hexmask.quad.tbyte 0x560 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x560 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x560 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x560 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x560 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x560 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x560 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x568 "GICD_IROUTER205,GICD_IROUTER205"
hexmask.quad.tbyte 0x568 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x568 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x568 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x568 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x568 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x568 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x568 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x570 "GICD_IROUTER206,GICD_IROUTER206"
hexmask.quad.tbyte 0x570 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x570 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x570 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x570 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x570 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x570 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x570 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x578 "GICD_IROUTER207,GICD_IROUTER207"
hexmask.quad.tbyte 0x578 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x578 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x578 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x578 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x578 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x578 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x578 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x580 "GICD_IROUTER208,GICD_IROUTER208"
hexmask.quad.tbyte 0x580 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x580 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x580 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x580 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x580 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x580 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x580 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x588 "GICD_IROUTER209,GICD_IROUTER209"
hexmask.quad.tbyte 0x588 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x588 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x588 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x588 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x588 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x588 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x588 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x590 "GICD_IROUTER210,GICD_IROUTER210"
hexmask.quad.tbyte 0x590 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x590 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x590 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x590 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x590 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x590 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x590 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x598 "GICD_IROUTER211,GICD_IROUTER211"
hexmask.quad.tbyte 0x598 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x598 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x598 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x598 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x598 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x598 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x598 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5A0 "GICD_IROUTER212,GICD_IROUTER212"
hexmask.quad.tbyte 0x5A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5A8 "GICD_IROUTER213,GICD_IROUTER213"
hexmask.quad.tbyte 0x5A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5B0 "GICD_IROUTER214,GICD_IROUTER214"
hexmask.quad.tbyte 0x5B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5B8 "GICD_IROUTER215,GICD_IROUTER215"
hexmask.quad.tbyte 0x5B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5C0 "GICD_IROUTER216,GICD_IROUTER216"
hexmask.quad.tbyte 0x5C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5C8 "GICD_IROUTER217,GICD_IROUTER217"
hexmask.quad.tbyte 0x5C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5D0 "GICD_IROUTER218,GICD_IROUTER218"
hexmask.quad.tbyte 0x5D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5D8 "GICD_IROUTER219,GICD_IROUTER219"
hexmask.quad.tbyte 0x5D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5E0 "GICD_IROUTER220,GICD_IROUTER220"
hexmask.quad.tbyte 0x5E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5E8 "GICD_IROUTER221,GICD_IROUTER221"
hexmask.quad.tbyte 0x5E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5F0 "GICD_IROUTER222,GICD_IROUTER222"
hexmask.quad.tbyte 0x5F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5F8 "GICD_IROUTER223,GICD_IROUTER223"
hexmask.quad.tbyte 0x5F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x600 "GICD_IROUTER224,GICD_IROUTER224"
hexmask.quad.tbyte 0x600 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x600 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x600 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x600 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x600 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x600 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x600 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x608 "GICD_IROUTER225,GICD_IROUTER225"
hexmask.quad.tbyte 0x608 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x608 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x608 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x608 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x608 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x608 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x608 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x610 "GICD_IROUTER226,GICD_IROUTER226"
hexmask.quad.tbyte 0x610 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x610 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x610 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x610 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x610 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x610 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x610 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x618 "GICD_IROUTER227,GICD_IROUTER227"
hexmask.quad.tbyte 0x618 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x618 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x618 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x618 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x618 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x618 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x618 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x620 "GICD_IROUTER228,GICD_IROUTER228"
hexmask.quad.tbyte 0x620 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x620 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x620 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x620 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x620 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x620 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x620 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x628 "GICD_IROUTER229,GICD_IROUTER229"
hexmask.quad.tbyte 0x628 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x628 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x628 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x628 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x628 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x628 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x628 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x630 "GICD_IROUTER230,GICD_IROUTER230"
hexmask.quad.tbyte 0x630 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x630 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x630 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x630 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x630 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x630 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x630 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x638 "GICD_IROUTER231,GICD_IROUTER231"
hexmask.quad.tbyte 0x638 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x638 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x638 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x638 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x638 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x638 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x638 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x640 "GICD_IROUTER232,GICD_IROUTER232"
hexmask.quad.tbyte 0x640 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x640 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x640 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x640 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x640 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x640 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x640 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x648 "GICD_IROUTER233,GICD_IROUTER233"
hexmask.quad.tbyte 0x648 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x648 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x648 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x648 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x648 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x648 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x648 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x650 "GICD_IROUTER234,GICD_IROUTER234"
hexmask.quad.tbyte 0x650 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x650 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x650 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x650 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x650 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x650 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x650 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x658 "GICD_IROUTER235,GICD_IROUTER235"
hexmask.quad.tbyte 0x658 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x658 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x658 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x658 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x658 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x658 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x658 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x660 "GICD_IROUTER236,GICD_IROUTER236"
hexmask.quad.tbyte 0x660 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x660 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x660 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x660 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x660 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x660 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x660 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x668 "GICD_IROUTER237,GICD_IROUTER237"
hexmask.quad.tbyte 0x668 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x668 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x668 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x668 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x668 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x668 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x668 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x670 "GICD_IROUTER238,GICD_IROUTER238"
hexmask.quad.tbyte 0x670 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x670 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x670 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x670 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x670 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x670 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x670 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x678 "GICD_IROUTER239,GICD_IROUTER239"
hexmask.quad.tbyte 0x678 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x678 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x678 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x678 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x678 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x678 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x678 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x680 "GICD_IROUTER240,GICD_IROUTER240"
hexmask.quad.tbyte 0x680 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x680 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x680 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x680 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x680 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x680 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x680 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x688 "GICD_IROUTER241,GICD_IROUTER241"
hexmask.quad.tbyte 0x688 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x688 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x688 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x688 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x688 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x688 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x688 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x690 "GICD_IROUTER242,GICD_IROUTER242"
hexmask.quad.tbyte 0x690 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x690 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x690 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x690 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x690 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x690 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x690 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x698 "GICD_IROUTER243,GICD_IROUTER243"
hexmask.quad.tbyte 0x698 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x698 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x698 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x698 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x698 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x698 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x698 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6A0 "GICD_IROUTER244,GICD_IROUTER244"
hexmask.quad.tbyte 0x6A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6A8 "GICD_IROUTER245,GICD_IROUTER245"
hexmask.quad.tbyte 0x6A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6B0 "GICD_IROUTER246,GICD_IROUTER246"
hexmask.quad.tbyte 0x6B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6B8 "GICD_IROUTER247,GICD_IROUTER247"
hexmask.quad.tbyte 0x6B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6C0 "GICD_IROUTER248,GICD_IROUTER248"
hexmask.quad.tbyte 0x6C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6C8 "GICD_IROUTER249,GICD_IROUTER249"
hexmask.quad.tbyte 0x6C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6D0 "GICD_IROUTER250,GICD_IROUTER250"
hexmask.quad.tbyte 0x6D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6D8 "GICD_IROUTER251,GICD_IROUTER251"
hexmask.quad.tbyte 0x6D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6E0 "GICD_IROUTER252,GICD_IROUTER252"
hexmask.quad.tbyte 0x6E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6E8 "GICD_IROUTER253,GICD_IROUTER253"
hexmask.quad.tbyte 0x6E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6F0 "GICD_IROUTER254,GICD_IROUTER254"
hexmask.quad.tbyte 0x6F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6F8 "GICD_IROUTER255,GICD_IROUTER255"
hexmask.quad.tbyte 0x6F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x700 "GICD_IROUTER256,GICD_IROUTER256"
hexmask.quad.tbyte 0x700 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x700 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x700 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x700 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x700 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x700 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x700 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x708 "GICD_IROUTER257,GICD_IROUTER257"
hexmask.quad.tbyte 0x708 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x708 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x708 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x708 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x708 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x708 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x708 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x710 "GICD_IROUTER258,GICD_IROUTER258"
hexmask.quad.tbyte 0x710 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x710 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x710 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x710 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x710 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x710 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x710 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x718 "GICD_IROUTER259,GICD_IROUTER259"
hexmask.quad.tbyte 0x718 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x718 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x718 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x718 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x718 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x718 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x718 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x720 "GICD_IROUTER260,GICD_IROUTER260"
hexmask.quad.tbyte 0x720 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x720 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x720 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x720 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x720 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x720 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x720 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x728 "GICD_IROUTER261,GICD_IROUTER261"
hexmask.quad.tbyte 0x728 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x728 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x728 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x728 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x728 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x728 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x728 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x730 "GICD_IROUTER262,GICD_IROUTER262"
hexmask.quad.tbyte 0x730 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x730 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x730 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x730 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x730 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x730 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x730 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x738 "GICD_IROUTER263,GICD_IROUTER263"
hexmask.quad.tbyte 0x738 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x738 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x738 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x738 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x738 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x738 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x738 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x740 "GICD_IROUTER264,GICD_IROUTER264"
hexmask.quad.tbyte 0x740 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x740 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x740 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x740 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x740 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x740 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x740 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x748 "GICD_IROUTER265,GICD_IROUTER265"
hexmask.quad.tbyte 0x748 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x748 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x748 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x748 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x748 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x748 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x748 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x750 "GICD_IROUTER266,GICD_IROUTER266"
hexmask.quad.tbyte 0x750 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x750 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x750 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x750 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x750 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x750 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x750 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x758 "GICD_IROUTER267,GICD_IROUTER267"
hexmask.quad.tbyte 0x758 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x758 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x758 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x758 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x758 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x758 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x758 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x760 "GICD_IROUTER268,GICD_IROUTER268"
hexmask.quad.tbyte 0x760 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x760 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x760 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x760 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x760 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x760 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x760 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x768 "GICD_IROUTER269,GICD_IROUTER269"
hexmask.quad.tbyte 0x768 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x768 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x768 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x768 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x768 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x768 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x768 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x770 "GICD_IROUTER270,GICD_IROUTER270"
hexmask.quad.tbyte 0x770 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x770 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x770 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x770 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x770 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x770 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x770 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x778 "GICD_IROUTER271,GICD_IROUTER271"
hexmask.quad.tbyte 0x778 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x778 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x778 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x778 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x778 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x778 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x778 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x780 "GICD_IROUTER272,GICD_IROUTER272"
hexmask.quad.tbyte 0x780 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x780 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x780 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x780 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x780 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x780 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x780 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x788 "GICD_IROUTER273,GICD_IROUTER273"
hexmask.quad.tbyte 0x788 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x788 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x788 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x788 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x788 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x788 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x788 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x790 "GICD_IROUTER274,GICD_IROUTER274"
hexmask.quad.tbyte 0x790 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x790 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x790 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x790 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x790 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x790 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x790 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x798 "GICD_IROUTER275,GICD_IROUTER275"
hexmask.quad.tbyte 0x798 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x798 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x798 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x798 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x798 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x798 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x798 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7A0 "GICD_IROUTER276,GICD_IROUTER276"
hexmask.quad.tbyte 0x7A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7A8 "GICD_IROUTER277,GICD_IROUTER277"
hexmask.quad.tbyte 0x7A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7B0 "GICD_IROUTER278,GICD_IROUTER278"
hexmask.quad.tbyte 0x7B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7B8 "GICD_IROUTER279,GICD_IROUTER279"
hexmask.quad.tbyte 0x7B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7C0 "GICD_IROUTER280,GICD_IROUTER280"
hexmask.quad.tbyte 0x7C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7C8 "GICD_IROUTER281,GICD_IROUTER281"
hexmask.quad.tbyte 0x7C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7D0 "GICD_IROUTER282,GICD_IROUTER282"
hexmask.quad.tbyte 0x7D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7D8 "GICD_IROUTER283,GICD_IROUTER283"
hexmask.quad.tbyte 0x7D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7E0 "GICD_IROUTER284,GICD_IROUTER284"
hexmask.quad.tbyte 0x7E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7E8 "GICD_IROUTER285,GICD_IROUTER285"
hexmask.quad.tbyte 0x7E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7F0 "GICD_IROUTER286,GICD_IROUTER286"
hexmask.quad.tbyte 0x7F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7F8 "GICD_IROUTER287,GICD_IROUTER287"
hexmask.quad.tbyte 0x7F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x800 "GICD_IROUTER288,GICD_IROUTER288"
hexmask.quad.tbyte 0x800 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x800 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x800 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x800 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x800 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x800 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x800 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x808 "GICD_IROUTER289,GICD_IROUTER289"
hexmask.quad.tbyte 0x808 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x808 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x808 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x808 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x808 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x808 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x808 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x810 "GICD_IROUTER290,GICD_IROUTER290"
hexmask.quad.tbyte 0x810 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x810 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x810 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x810 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x810 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x810 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x810 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x818 "GICD_IROUTER291,GICD_IROUTER291"
hexmask.quad.tbyte 0x818 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x818 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x818 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x818 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x818 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x818 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x818 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x820 "GICD_IROUTER292,GICD_IROUTER292"
hexmask.quad.tbyte 0x820 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x820 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x820 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x820 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x820 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x820 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x820 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x828 "GICD_IROUTER293,GICD_IROUTER293"
hexmask.quad.tbyte 0x828 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x828 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x828 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x828 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x828 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x828 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x828 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x830 "GICD_IROUTER294,GICD_IROUTER294"
hexmask.quad.tbyte 0x830 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x830 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x830 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x830 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x830 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x830 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x830 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x838 "GICD_IROUTER295,GICD_IROUTER295"
hexmask.quad.tbyte 0x838 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x838 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x838 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x838 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x838 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x838 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x838 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x840 "GICD_IROUTER296,GICD_IROUTER296"
hexmask.quad.tbyte 0x840 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x840 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x840 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x840 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x840 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x840 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x840 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x848 "GICD_IROUTER297,GICD_IROUTER297"
hexmask.quad.tbyte 0x848 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x848 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x848 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x848 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x848 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x848 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x848 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x850 "GICD_IROUTER298,GICD_IROUTER298"
hexmask.quad.tbyte 0x850 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x850 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x850 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x850 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x850 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x850 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x850 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x858 "GICD_IROUTER299,GICD_IROUTER299"
hexmask.quad.tbyte 0x858 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x858 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x858 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x858 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x858 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x858 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x858 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x860 "GICD_IROUTER300,GICD_IROUTER300"
hexmask.quad.tbyte 0x860 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x860 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x860 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x860 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x860 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x860 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x860 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x868 "GICD_IROUTER301,GICD_IROUTER301"
hexmask.quad.tbyte 0x868 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x868 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x868 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x868 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x868 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x868 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x868 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x870 "GICD_IROUTER302,GICD_IROUTER302"
hexmask.quad.tbyte 0x870 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x870 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x870 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x870 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x870 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x870 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x870 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x878 "GICD_IROUTER303,GICD_IROUTER303"
hexmask.quad.tbyte 0x878 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x878 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x878 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x878 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x878 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x878 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x878 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x880 "GICD_IROUTER304,GICD_IROUTER304"
hexmask.quad.tbyte 0x880 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x880 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x880 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x880 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x880 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x880 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x880 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x888 "GICD_IROUTER305,GICD_IROUTER305"
hexmask.quad.tbyte 0x888 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x888 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x888 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x888 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x888 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x888 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x888 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x890 "GICD_IROUTER306,GICD_IROUTER306"
hexmask.quad.tbyte 0x890 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x890 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x890 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x890 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x890 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x890 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x890 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x898 "GICD_IROUTER307,GICD_IROUTER307"
hexmask.quad.tbyte 0x898 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x898 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x898 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x898 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x898 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x898 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x898 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8A0 "GICD_IROUTER308,GICD_IROUTER308"
hexmask.quad.tbyte 0x8A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8A8 "GICD_IROUTER309,GICD_IROUTER309"
hexmask.quad.tbyte 0x8A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8B0 "GICD_IROUTER310,GICD_IROUTER310"
hexmask.quad.tbyte 0x8B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8B8 "GICD_IROUTER311,GICD_IROUTER311"
hexmask.quad.tbyte 0x8B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8C0 "GICD_IROUTER312,GICD_IROUTER312"
hexmask.quad.tbyte 0x8C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8C8 "GICD_IROUTER313,GICD_IROUTER313"
hexmask.quad.tbyte 0x8C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8D0 "GICD_IROUTER314,GICD_IROUTER314"
hexmask.quad.tbyte 0x8D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8D8 "GICD_IROUTER315,GICD_IROUTER315"
hexmask.quad.tbyte 0x8D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8E0 "GICD_IROUTER316,GICD_IROUTER316"
hexmask.quad.tbyte 0x8E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8E8 "GICD_IROUTER317,GICD_IROUTER317"
hexmask.quad.tbyte 0x8E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8F0 "GICD_IROUTER318,GICD_IROUTER318"
hexmask.quad.tbyte 0x8F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8F8 "GICD_IROUTER319,GICD_IROUTER319"
hexmask.quad.tbyte 0x8F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x900 "GICD_IROUTER320,GICD_IROUTER320"
hexmask.quad.tbyte 0x900 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x900 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x900 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x900 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x900 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x900 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x900 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x908 "GICD_IROUTER321,GICD_IROUTER321"
hexmask.quad.tbyte 0x908 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x908 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x908 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x908 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x908 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x908 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x908 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x910 "GICD_IROUTER322,GICD_IROUTER322"
hexmask.quad.tbyte 0x910 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x910 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x910 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x910 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x910 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x910 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x910 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x918 "GICD_IROUTER323,GICD_IROUTER323"
hexmask.quad.tbyte 0x918 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x918 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x918 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x918 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x918 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x918 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x918 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x920 "GICD_IROUTER324,GICD_IROUTER324"
hexmask.quad.tbyte 0x920 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x920 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x920 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x920 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x920 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x920 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x920 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x928 "GICD_IROUTER325,GICD_IROUTER325"
hexmask.quad.tbyte 0x928 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x928 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x928 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x928 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x928 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x928 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x928 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x930 "GICD_IROUTER326,GICD_IROUTER326"
hexmask.quad.tbyte 0x930 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x930 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x930 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x930 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x930 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x930 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x930 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x938 "GICD_IROUTER327,GICD_IROUTER327"
hexmask.quad.tbyte 0x938 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x938 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x938 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x938 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x938 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x938 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x938 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x940 "GICD_IROUTER328,GICD_IROUTER328"
hexmask.quad.tbyte 0x940 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x940 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x940 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x940 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x940 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x940 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x940 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x948 "GICD_IROUTER329,GICD_IROUTER329"
hexmask.quad.tbyte 0x948 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x948 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x948 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x948 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x948 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x948 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x948 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x950 "GICD_IROUTER330,GICD_IROUTER330"
hexmask.quad.tbyte 0x950 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x950 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x950 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x950 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x950 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x950 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x950 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x958 "GICD_IROUTER331,GICD_IROUTER331"
hexmask.quad.tbyte 0x958 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x958 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x958 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x958 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x958 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x958 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x958 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x960 "GICD_IROUTER332,GICD_IROUTER332"
hexmask.quad.tbyte 0x960 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x960 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x960 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x960 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x960 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x960 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x960 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x968 "GICD_IROUTER333,GICD_IROUTER333"
hexmask.quad.tbyte 0x968 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x968 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x968 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x968 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x968 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x968 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x968 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x970 "GICD_IROUTER334,GICD_IROUTER334"
hexmask.quad.tbyte 0x970 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x970 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x970 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x970 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x970 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x970 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x970 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x978 "GICD_IROUTER335,GICD_IROUTER335"
hexmask.quad.tbyte 0x978 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x978 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x978 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x978 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x978 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x978 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x978 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x980 "GICD_IROUTER336,GICD_IROUTER336"
hexmask.quad.tbyte 0x980 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x980 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x980 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x980 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x980 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x980 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x980 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x988 "GICD_IROUTER337,GICD_IROUTER337"
hexmask.quad.tbyte 0x988 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x988 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x988 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x988 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x988 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x988 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x988 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x990 "GICD_IROUTER338,GICD_IROUTER338"
hexmask.quad.tbyte 0x990 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x990 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x990 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x990 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x990 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x990 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x990 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x998 "GICD_IROUTER339,GICD_IROUTER339"
hexmask.quad.tbyte 0x998 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x998 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x998 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x998 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x998 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x998 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x998 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9A0 "GICD_IROUTER340,GICD_IROUTER340"
hexmask.quad.tbyte 0x9A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9A8 "GICD_IROUTER341,GICD_IROUTER341"
hexmask.quad.tbyte 0x9A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9B0 "GICD_IROUTER342,GICD_IROUTER342"
hexmask.quad.tbyte 0x9B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9B8 "GICD_IROUTER343,GICD_IROUTER343"
hexmask.quad.tbyte 0x9B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9C0 "GICD_IROUTER344,GICD_IROUTER344"
hexmask.quad.tbyte 0x9C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9C8 "GICD_IROUTER345,GICD_IROUTER345"
hexmask.quad.tbyte 0x9C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9D0 "GICD_IROUTER346,GICD_IROUTER346"
hexmask.quad.tbyte 0x9D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9D8 "GICD_IROUTER347,GICD_IROUTER347"
hexmask.quad.tbyte 0x9D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9E0 "GICD_IROUTER348,GICD_IROUTER348"
hexmask.quad.tbyte 0x9E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9E8 "GICD_IROUTER349,GICD_IROUTER349"
hexmask.quad.tbyte 0x9E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9F0 "GICD_IROUTER350,GICD_IROUTER350"
hexmask.quad.tbyte 0x9F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9F8 "GICD_IROUTER351,GICD_IROUTER351"
hexmask.quad.tbyte 0x9F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA00 "GICD_IROUTER352,GICD_IROUTER352"
hexmask.quad.tbyte 0xA00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA08 "GICD_IROUTER353,GICD_IROUTER353"
hexmask.quad.tbyte 0xA08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA10 "GICD_IROUTER354,GICD_IROUTER354"
hexmask.quad.tbyte 0xA10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA18 "GICD_IROUTER355,GICD_IROUTER355"
hexmask.quad.tbyte 0xA18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA20 "GICD_IROUTER356,GICD_IROUTER356"
hexmask.quad.tbyte 0xA20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA28 "GICD_IROUTER357,GICD_IROUTER357"
hexmask.quad.tbyte 0xA28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA30 "GICD_IROUTER358,GICD_IROUTER358"
hexmask.quad.tbyte 0xA30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA38 "GICD_IROUTER359,GICD_IROUTER359"
hexmask.quad.tbyte 0xA38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA40 "GICD_IROUTER360,GICD_IROUTER360"
hexmask.quad.tbyte 0xA40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA48 "GICD_IROUTER361,GICD_IROUTER361"
hexmask.quad.tbyte 0xA48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA50 "GICD_IROUTER362,GICD_IROUTER362"
hexmask.quad.tbyte 0xA50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA58 "GICD_IROUTER363,GICD_IROUTER363"
hexmask.quad.tbyte 0xA58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA60 "GICD_IROUTER364,GICD_IROUTER364"
hexmask.quad.tbyte 0xA60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA68 "GICD_IROUTER365,GICD_IROUTER365"
hexmask.quad.tbyte 0xA68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA70 "GICD_IROUTER366,GICD_IROUTER366"
hexmask.quad.tbyte 0xA70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA78 "GICD_IROUTER367,GICD_IROUTER367"
hexmask.quad.tbyte 0xA78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA80 "GICD_IROUTER368,GICD_IROUTER368"
hexmask.quad.tbyte 0xA80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA88 "GICD_IROUTER369,GICD_IROUTER369"
hexmask.quad.tbyte 0xA88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA90 "GICD_IROUTER370,GICD_IROUTER370"
hexmask.quad.tbyte 0xA90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA98 "GICD_IROUTER371,GICD_IROUTER371"
hexmask.quad.tbyte 0xA98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAA0 "GICD_IROUTER372,GICD_IROUTER372"
hexmask.quad.tbyte 0xAA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAA8 "GICD_IROUTER373,GICD_IROUTER373"
hexmask.quad.tbyte 0xAA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAB0 "GICD_IROUTER374,GICD_IROUTER374"
hexmask.quad.tbyte 0xAB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAB8 "GICD_IROUTER375,GICD_IROUTER375"
hexmask.quad.tbyte 0xAB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAC0 "GICD_IROUTER376,GICD_IROUTER376"
hexmask.quad.tbyte 0xAC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAC8 "GICD_IROUTER377,GICD_IROUTER377"
hexmask.quad.tbyte 0xAC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAD0 "GICD_IROUTER378,GICD_IROUTER378"
hexmask.quad.tbyte 0xAD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAD8 "GICD_IROUTER379,GICD_IROUTER379"
hexmask.quad.tbyte 0xAD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAE0 "GICD_IROUTER380,GICD_IROUTER380"
hexmask.quad.tbyte 0xAE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAE8 "GICD_IROUTER381,GICD_IROUTER381"
hexmask.quad.tbyte 0xAE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAF0 "GICD_IROUTER382,GICD_IROUTER382"
hexmask.quad.tbyte 0xAF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAF8 "GICD_IROUTER383,GICD_IROUTER383"
hexmask.quad.tbyte 0xAF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB00 "GICD_IROUTER384,GICD_IROUTER384"
hexmask.quad.tbyte 0xB00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB08 "GICD_IROUTER385,GICD_IROUTER385"
hexmask.quad.tbyte 0xB08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB10 "GICD_IROUTER386,GICD_IROUTER386"
hexmask.quad.tbyte 0xB10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB18 "GICD_IROUTER387,GICD_IROUTER387"
hexmask.quad.tbyte 0xB18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB20 "GICD_IROUTER388,GICD_IROUTER388"
hexmask.quad.tbyte 0xB20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB28 "GICD_IROUTER389,GICD_IROUTER389"
hexmask.quad.tbyte 0xB28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB30 "GICD_IROUTER390,GICD_IROUTER390"
hexmask.quad.tbyte 0xB30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB38 "GICD_IROUTER391,GICD_IROUTER391"
hexmask.quad.tbyte 0xB38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB40 "GICD_IROUTER392,GICD_IROUTER392"
hexmask.quad.tbyte 0xB40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB48 "GICD_IROUTER393,GICD_IROUTER393"
hexmask.quad.tbyte 0xB48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB50 "GICD_IROUTER394,GICD_IROUTER394"
hexmask.quad.tbyte 0xB50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB58 "GICD_IROUTER395,GICD_IROUTER395"
hexmask.quad.tbyte 0xB58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB60 "GICD_IROUTER396,GICD_IROUTER396"
hexmask.quad.tbyte 0xB60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB68 "GICD_IROUTER397,GICD_IROUTER397"
hexmask.quad.tbyte 0xB68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB70 "GICD_IROUTER398,GICD_IROUTER398"
hexmask.quad.tbyte 0xB70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB78 "GICD_IROUTER399,GICD_IROUTER399"
hexmask.quad.tbyte 0xB78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB80 "GICD_IROUTER400,GICD_IROUTER400"
hexmask.quad.tbyte 0xB80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB88 "GICD_IROUTER401,GICD_IROUTER401"
hexmask.quad.tbyte 0xB88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB90 "GICD_IROUTER402,GICD_IROUTER402"
hexmask.quad.tbyte 0xB90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB98 "GICD_IROUTER403,GICD_IROUTER403"
hexmask.quad.tbyte 0xB98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBA0 "GICD_IROUTER404,GICD_IROUTER404"
hexmask.quad.tbyte 0xBA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBA8 "GICD_IROUTER405,GICD_IROUTER405"
hexmask.quad.tbyte 0xBA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBB0 "GICD_IROUTER406,GICD_IROUTER406"
hexmask.quad.tbyte 0xBB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBB8 "GICD_IROUTER407,GICD_IROUTER407"
hexmask.quad.tbyte 0xBB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBC0 "GICD_IROUTER408,GICD_IROUTER408"
hexmask.quad.tbyte 0xBC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBC8 "GICD_IROUTER409,GICD_IROUTER409"
hexmask.quad.tbyte 0xBC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBD0 "GICD_IROUTER410,GICD_IROUTER410"
hexmask.quad.tbyte 0xBD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBD8 "GICD_IROUTER411,GICD_IROUTER411"
hexmask.quad.tbyte 0xBD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBE0 "GICD_IROUTER412,GICD_IROUTER412"
hexmask.quad.tbyte 0xBE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBE8 "GICD_IROUTER413,GICD_IROUTER413"
hexmask.quad.tbyte 0xBE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBF0 "GICD_IROUTER414,GICD_IROUTER414"
hexmask.quad.tbyte 0xBF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBF8 "GICD_IROUTER415,GICD_IROUTER415"
hexmask.quad.tbyte 0xBF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC00 "GICD_IROUTER416,GICD_IROUTER416"
hexmask.quad.tbyte 0xC00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC08 "GICD_IROUTER417,GICD_IROUTER417"
hexmask.quad.tbyte 0xC08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC10 "GICD_IROUTER418,GICD_IROUTER418"
hexmask.quad.tbyte 0xC10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC18 "GICD_IROUTER419,GICD_IROUTER419"
hexmask.quad.tbyte 0xC18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC20 "GICD_IROUTER420,GICD_IROUTER420"
hexmask.quad.tbyte 0xC20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC28 "GICD_IROUTER421,GICD_IROUTER421"
hexmask.quad.tbyte 0xC28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC30 "GICD_IROUTER422,GICD_IROUTER422"
hexmask.quad.tbyte 0xC30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC38 "GICD_IROUTER423,GICD_IROUTER423"
hexmask.quad.tbyte 0xC38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC40 "GICD_IROUTER424,GICD_IROUTER424"
hexmask.quad.tbyte 0xC40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC48 "GICD_IROUTER425,GICD_IROUTER425"
hexmask.quad.tbyte 0xC48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC50 "GICD_IROUTER426,GICD_IROUTER426"
hexmask.quad.tbyte 0xC50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC58 "GICD_IROUTER427,GICD_IROUTER427"
hexmask.quad.tbyte 0xC58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC60 "GICD_IROUTER428,GICD_IROUTER428"
hexmask.quad.tbyte 0xC60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC68 "GICD_IROUTER429,GICD_IROUTER429"
hexmask.quad.tbyte 0xC68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC70 "GICD_IROUTER430,GICD_IROUTER430"
hexmask.quad.tbyte 0xC70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC78 "GICD_IROUTER431,GICD_IROUTER431"
hexmask.quad.tbyte 0xC78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC80 "GICD_IROUTER432,GICD_IROUTER432"
hexmask.quad.tbyte 0xC80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC88 "GICD_IROUTER433,GICD_IROUTER433"
hexmask.quad.tbyte 0xC88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC90 "GICD_IROUTER434,GICD_IROUTER434"
hexmask.quad.tbyte 0xC90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC98 "GICD_IROUTER435,GICD_IROUTER435"
hexmask.quad.tbyte 0xC98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCA0 "GICD_IROUTER436,GICD_IROUTER436"
hexmask.quad.tbyte 0xCA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCA8 "GICD_IROUTER437,GICD_IROUTER437"
hexmask.quad.tbyte 0xCA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCB0 "GICD_IROUTER438,GICD_IROUTER438"
hexmask.quad.tbyte 0xCB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCB8 "GICD_IROUTER439,GICD_IROUTER439"
hexmask.quad.tbyte 0xCB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCC0 "GICD_IROUTER440,GICD_IROUTER440"
hexmask.quad.tbyte 0xCC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCC8 "GICD_IROUTER441,GICD_IROUTER441"
hexmask.quad.tbyte 0xCC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCD0 "GICD_IROUTER442,GICD_IROUTER442"
hexmask.quad.tbyte 0xCD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCD8 "GICD_IROUTER443,GICD_IROUTER443"
hexmask.quad.tbyte 0xCD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCE0 "GICD_IROUTER444,GICD_IROUTER444"
hexmask.quad.tbyte 0xCE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCE8 "GICD_IROUTER445,GICD_IROUTER445"
hexmask.quad.tbyte 0xCE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCF0 "GICD_IROUTER446,GICD_IROUTER446"
hexmask.quad.tbyte 0xCF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCF8 "GICD_IROUTER447,GICD_IROUTER447"
hexmask.quad.tbyte 0xCF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD00 "GICD_IROUTER448,GICD_IROUTER448"
hexmask.quad.tbyte 0xD00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD08 "GICD_IROUTER449,GICD_IROUTER449"
hexmask.quad.tbyte 0xD08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD10 "GICD_IROUTER450,GICD_IROUTER450"
hexmask.quad.tbyte 0xD10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD18 "GICD_IROUTER451,GICD_IROUTER451"
hexmask.quad.tbyte 0xD18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD20 "GICD_IROUTER452,GICD_IROUTER452"
hexmask.quad.tbyte 0xD20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD28 "GICD_IROUTER453,GICD_IROUTER453"
hexmask.quad.tbyte 0xD28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD30 "GICD_IROUTER454,GICD_IROUTER454"
hexmask.quad.tbyte 0xD30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD38 "GICD_IROUTER455,GICD_IROUTER455"
hexmask.quad.tbyte 0xD38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD40 "GICD_IROUTER456,GICD_IROUTER456"
hexmask.quad.tbyte 0xD40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD48 "GICD_IROUTER457,GICD_IROUTER457"
hexmask.quad.tbyte 0xD48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD50 "GICD_IROUTER458,GICD_IROUTER458"
hexmask.quad.tbyte 0xD50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD58 "GICD_IROUTER459,GICD_IROUTER459"
hexmask.quad.tbyte 0xD58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD60 "GICD_IROUTER460,GICD_IROUTER460"
hexmask.quad.tbyte 0xD60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD68 "GICD_IROUTER461,GICD_IROUTER461"
hexmask.quad.tbyte 0xD68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD70 "GICD_IROUTER462,GICD_IROUTER462"
hexmask.quad.tbyte 0xD70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD78 "GICD_IROUTER463,GICD_IROUTER463"
hexmask.quad.tbyte 0xD78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD80 "GICD_IROUTER464,GICD_IROUTER464"
hexmask.quad.tbyte 0xD80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD88 "GICD_IROUTER465,GICD_IROUTER465"
hexmask.quad.tbyte 0xD88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD90 "GICD_IROUTER466,GICD_IROUTER466"
hexmask.quad.tbyte 0xD90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD98 "GICD_IROUTER467,GICD_IROUTER467"
hexmask.quad.tbyte 0xD98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDA0 "GICD_IROUTER468,GICD_IROUTER468"
hexmask.quad.tbyte 0xDA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDA8 "GICD_IROUTER469,GICD_IROUTER469"
hexmask.quad.tbyte 0xDA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDB0 "GICD_IROUTER470,GICD_IROUTER470"
hexmask.quad.tbyte 0xDB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDB8 "GICD_IROUTER471,GICD_IROUTER471"
hexmask.quad.tbyte 0xDB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDC0 "GICD_IROUTER472,GICD_IROUTER472"
hexmask.quad.tbyte 0xDC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDC8 "GICD_IROUTER473,GICD_IROUTER473"
hexmask.quad.tbyte 0xDC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDD0 "GICD_IROUTER474,GICD_IROUTER474"
hexmask.quad.tbyte 0xDD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDD8 "GICD_IROUTER475,GICD_IROUTER475"
hexmask.quad.tbyte 0xDD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDE0 "GICD_IROUTER476,GICD_IROUTER476"
hexmask.quad.tbyte 0xDE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDE8 "GICD_IROUTER477,GICD_IROUTER477"
hexmask.quad.tbyte 0xDE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDF0 "GICD_IROUTER478,GICD_IROUTER478"
hexmask.quad.tbyte 0xDF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDF8 "GICD_IROUTER479,GICD_IROUTER479"
hexmask.quad.tbyte 0xDF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE00 "GICD_IROUTER480,GICD_IROUTER480"
hexmask.quad.tbyte 0xE00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE08 "GICD_IROUTER481,GICD_IROUTER481"
hexmask.quad.tbyte 0xE08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE10 "GICD_IROUTER482,GICD_IROUTER482"
hexmask.quad.tbyte 0xE10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE18 "GICD_IROUTER483,GICD_IROUTER483"
hexmask.quad.tbyte 0xE18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE20 "GICD_IROUTER484,GICD_IROUTER484"
hexmask.quad.tbyte 0xE20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE28 "GICD_IROUTER485,GICD_IROUTER485"
hexmask.quad.tbyte 0xE28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE30 "GICD_IROUTER486,GICD_IROUTER486"
hexmask.quad.tbyte 0xE30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE38 "GICD_IROUTER487,GICD_IROUTER487"
hexmask.quad.tbyte 0xE38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE40 "GICD_IROUTER488,GICD_IROUTER488"
hexmask.quad.tbyte 0xE40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE48 "GICD_IROUTER489,GICD_IROUTER489"
hexmask.quad.tbyte 0xE48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE50 "GICD_IROUTER490,GICD_IROUTER490"
hexmask.quad.tbyte 0xE50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE58 "GICD_IROUTER491,GICD_IROUTER491"
hexmask.quad.tbyte 0xE58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE60 "GICD_IROUTER492,GICD_IROUTER492"
hexmask.quad.tbyte 0xE60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE68 "GICD_IROUTER493,GICD_IROUTER493"
hexmask.quad.tbyte 0xE68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE70 "GICD_IROUTER494,GICD_IROUTER494"
hexmask.quad.tbyte 0xE70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE78 "GICD_IROUTER495,GICD_IROUTER495"
hexmask.quad.tbyte 0xE78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE80 "GICD_IROUTER496,GICD_IROUTER496"
hexmask.quad.tbyte 0xE80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE88 "GICD_IROUTER497,GICD_IROUTER497"
hexmask.quad.tbyte 0xE88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE90 "GICD_IROUTER498,GICD_IROUTER498"
hexmask.quad.tbyte 0xE90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE98 "GICD_IROUTER499,GICD_IROUTER499"
hexmask.quad.tbyte 0xE98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEA0 "GICD_IROUTER500,GICD_IROUTER500"
hexmask.quad.tbyte 0xEA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEA8 "GICD_IROUTER501,GICD_IROUTER501"
hexmask.quad.tbyte 0xEA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEB0 "GICD_IROUTER502,GICD_IROUTER502"
hexmask.quad.tbyte 0xEB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEB8 "GICD_IROUTER503,GICD_IROUTER503"
hexmask.quad.tbyte 0xEB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEC0 "GICD_IROUTER504,GICD_IROUTER504"
hexmask.quad.tbyte 0xEC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEC8 "GICD_IROUTER505,GICD_IROUTER505"
hexmask.quad.tbyte 0xEC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xED0 "GICD_IROUTER506,GICD_IROUTER506"
hexmask.quad.tbyte 0xED0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xED0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xED0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xED0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xED0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xED0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xED0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xED8 "GICD_IROUTER507,GICD_IROUTER507"
hexmask.quad.tbyte 0xED8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xED8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xED8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xED8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xED8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xED8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xED8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEE0 "GICD_IROUTER508,GICD_IROUTER508"
hexmask.quad.tbyte 0xEE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEE8 "GICD_IROUTER509,GICD_IROUTER509"
hexmask.quad.tbyte 0xEE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEF0 "GICD_IROUTER510,GICD_IROUTER510"
hexmask.quad.tbyte 0xEF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEF8 "GICD_IROUTER511,GICD_IROUTER511"
hexmask.quad.tbyte 0xEF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF00 "GICD_IROUTER512,GICD_IROUTER512"
hexmask.quad.tbyte 0xF00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF08 "GICD_IROUTER513,GICD_IROUTER513"
hexmask.quad.tbyte 0xF08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF10 "GICD_IROUTER514,GICD_IROUTER514"
hexmask.quad.tbyte 0xF10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF18 "GICD_IROUTER515,GICD_IROUTER515"
hexmask.quad.tbyte 0xF18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF20 "GICD_IROUTER516,GICD_IROUTER516"
hexmask.quad.tbyte 0xF20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF28 "GICD_IROUTER517,GICD_IROUTER517"
hexmask.quad.tbyte 0xF28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF30 "GICD_IROUTER518,GICD_IROUTER518"
hexmask.quad.tbyte 0xF30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF38 "GICD_IROUTER519,GICD_IROUTER519"
hexmask.quad.tbyte 0xF38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF40 "GICD_IROUTER520,GICD_IROUTER520"
hexmask.quad.tbyte 0xF40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF48 "GICD_IROUTER521,GICD_IROUTER521"
hexmask.quad.tbyte 0xF48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF50 "GICD_IROUTER522,GICD_IROUTER522"
hexmask.quad.tbyte 0xF50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF58 "GICD_IROUTER523,GICD_IROUTER523"
hexmask.quad.tbyte 0xF58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF60 "GICD_IROUTER524,GICD_IROUTER524"
hexmask.quad.tbyte 0xF60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF68 "GICD_IROUTER525,GICD_IROUTER525"
hexmask.quad.tbyte 0xF68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF70 "GICD_IROUTER526,GICD_IROUTER526"
hexmask.quad.tbyte 0xF70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF78 "GICD_IROUTER527,GICD_IROUTER527"
hexmask.quad.tbyte 0xF78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF80 "GICD_IROUTER528,GICD_IROUTER528"
hexmask.quad.tbyte 0xF80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF88 "GICD_IROUTER529,GICD_IROUTER529"
hexmask.quad.tbyte 0xF88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF90 "GICD_IROUTER530,GICD_IROUTER530"
hexmask.quad.tbyte 0xF90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF98 "GICD_IROUTER531,GICD_IROUTER531"
hexmask.quad.tbyte 0xF98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFA0 "GICD_IROUTER532,GICD_IROUTER532"
hexmask.quad.tbyte 0xFA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFA8 "GICD_IROUTER533,GICD_IROUTER533"
hexmask.quad.tbyte 0xFA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFB0 "GICD_IROUTER534,GICD_IROUTER534"
hexmask.quad.tbyte 0xFB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFB8 "GICD_IROUTER535,GICD_IROUTER535"
hexmask.quad.tbyte 0xFB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFC0 "GICD_IROUTER536,GICD_IROUTER536"
hexmask.quad.tbyte 0xFC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFC8 "GICD_IROUTER537,GICD_IROUTER537"
hexmask.quad.tbyte 0xFC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFD0 "GICD_IROUTER538,GICD_IROUTER538"
hexmask.quad.tbyte 0xFD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFD8 "GICD_IROUTER539,GICD_IROUTER539"
hexmask.quad.tbyte 0xFD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFE0 "GICD_IROUTER540,GICD_IROUTER540"
hexmask.quad.tbyte 0xFE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFE8 "GICD_IROUTER541,GICD_IROUTER541"
hexmask.quad.tbyte 0xFE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFF0 "GICD_IROUTER542,GICD_IROUTER542"
hexmask.quad.tbyte 0xFF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFF8 "GICD_IROUTER543,GICD_IROUTER543"
hexmask.quad.tbyte 0xFF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFF8 0.--7. 1. "Affinity0,Affinity0"
group.quad 0x7100++0xFF
line.quad 0x0 "GICD_IROUTER544,GICD_IROUTER544"
hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8 "GICD_IROUTER545,GICD_IROUTER545"
hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x10 "GICD_IROUTER546,GICD_IROUTER546"
hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x18 "GICD_IROUTER547,GICD_IROUTER547"
hexmask.quad.tbyte 0x18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x20 "GICD_IROUTER548,GICD_IROUTER548"
hexmask.quad.tbyte 0x20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x28 "GICD_IROUTER549,GICD_IROUTER549"
hexmask.quad.tbyte 0x28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x30 "GICD_IROUTER550,GICD_IROUTER550"
hexmask.quad.tbyte 0x30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x38 "GICD_IROUTER551,GICD_IROUTER551"
hexmask.quad.tbyte 0x38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x40 "GICD_IROUTER552,GICD_IROUTER552"
hexmask.quad.tbyte 0x40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x48 "GICD_IROUTER553,GICD_IROUTER553"
hexmask.quad.tbyte 0x48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x50 "GICD_IROUTER554,GICD_IROUTER554"
hexmask.quad.tbyte 0x50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x58 "GICD_IROUTER555,GICD_IROUTER555"
hexmask.quad.tbyte 0x58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x60 "GICD_IROUTER556,GICD_IROUTER556"
hexmask.quad.tbyte 0x60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x68 "GICD_IROUTER557,GICD_IROUTER557"
hexmask.quad.tbyte 0x68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x70 "GICD_IROUTER558,GICD_IROUTER558"
hexmask.quad.tbyte 0x70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x78 "GICD_IROUTER559,GICD_IROUTER559"
hexmask.quad.tbyte 0x78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x80 "GICD_IROUTER560,GICD_IROUTER560"
hexmask.quad.tbyte 0x80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x88 "GICD_IROUTER561,GICD_IROUTER561"
hexmask.quad.tbyte 0x88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x90 "GICD_IROUTER562,GICD_IROUTER562"
hexmask.quad.tbyte 0x90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x98 "GICD_IROUTER563,GICD_IROUTER563"
hexmask.quad.tbyte 0x98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA0 "GICD_IROUTER564,GICD_IROUTER564"
hexmask.quad.tbyte 0xA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA8 "GICD_IROUTER565,GICD_IROUTER565"
hexmask.quad.tbyte 0xA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB0 "GICD_IROUTER566,GICD_IROUTER566"
hexmask.quad.tbyte 0xB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB8 "GICD_IROUTER567,GICD_IROUTER567"
hexmask.quad.tbyte 0xB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC0 "GICD_IROUTER568,GICD_IROUTER568"
hexmask.quad.tbyte 0xC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC8 "GICD_IROUTER569,GICD_IROUTER569"
hexmask.quad.tbyte 0xC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD0 "GICD_IROUTER570,GICD_IROUTER570"
hexmask.quad.tbyte 0xD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD8 "GICD_IROUTER571,GICD_IROUTER571"
hexmask.quad.tbyte 0xD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE0 "GICD_IROUTER572,GICD_IROUTER572"
hexmask.quad.tbyte 0xE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE8 "GICD_IROUTER573,GICD_IROUTER573"
hexmask.quad.tbyte 0xE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF0 "GICD_IROUTER574,GICD_IROUTER574"
hexmask.quad.tbyte 0xF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF8 "GICD_IROUTER575,GICD_IROUTER575"
hexmask.quad.tbyte 0xF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF8 0.--7. 1. "Affinity0,Affinity0"
group.long 0xE008++0x87
line.long 0x0 "GICD_ICLAR2,GICD_ICLAR2"
bitfld.long 0x0 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x0 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x0 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x0 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x0 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x0 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x0 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x0 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x0 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x4 "GICD_ICLAR3,GICD_ICLAR3"
bitfld.long 0x4 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x4 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x4 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x4 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x4 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x4 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x4 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x4 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x4 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x4 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x4 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x4 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x8 "GICD_ICLAR4,GICD_ICLAR4"
bitfld.long 0x8 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x8 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x8 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x8 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x8 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x8 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x8 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x8 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x8 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x8 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x8 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x8 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x8 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x8 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0xC "GICD_ICLAR5,GICD_ICLAR5"
bitfld.long 0xC 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0xC 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0xC 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0xC 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0xC 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0xC 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0xC 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0xC 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0xC 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0xC 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0xC 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0xC 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x10 "GICD_ICLAR6,GICD_ICLAR6"
bitfld.long 0x10 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x10 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x10 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x10 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x10 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x10 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x10 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x10 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x10 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x10 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x10 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x10 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x10 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x14 "GICD_ICLAR7,GICD_ICLAR7"
bitfld.long 0x14 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x14 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x14 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x14 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x14 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x14 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x14 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x14 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x14 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x14 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x14 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x14 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x14 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x14 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x14 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x18 "GICD_ICLAR8,GICD_ICLAR8"
bitfld.long 0x18 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x18 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x18 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x18 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x18 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x18 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x18 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x18 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x18 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x18 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x18 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x18 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x18 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x18 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x18 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x1C "GICD_ICLAR9,GICD_ICLAR9"
bitfld.long 0x1C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x1C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x1C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x1C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x1C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x1C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x1C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x1C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x1C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x1C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x1C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x1C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x1C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x1C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x20 "GICD_ICLAR10,GICD_ICLAR10"
bitfld.long 0x20 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x20 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x20 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x20 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x20 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x20 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x20 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x20 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x20 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x20 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x20 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x20 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x20 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x20 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x20 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x20 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x24 "GICD_ICLAR11,GICD_ICLAR11"
bitfld.long 0x24 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x24 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x24 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x24 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x24 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x24 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x24 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x24 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x24 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x24 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x24 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x24 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x24 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x24 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x24 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x28 "GICD_ICLAR12,GICD_ICLAR12"
bitfld.long 0x28 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x28 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x28 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x28 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x28 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x28 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x28 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x28 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x28 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x28 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x28 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x28 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x28 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x28 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x28 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x28 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x2C "GICD_ICLAR13,GICD_ICLAR13"
bitfld.long 0x2C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x2C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x2C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x2C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x2C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x2C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x2C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x2C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x2C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x2C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x2C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x2C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x2C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x2C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x2C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x2C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x30 "GICD_ICLAR14,GICD_ICLAR14"
bitfld.long 0x30 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x30 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x30 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x30 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x30 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x30 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x30 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x30 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x30 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x30 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x30 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x30 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x30 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x30 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x30 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x30 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x34 "GICD_ICLAR15,GICD_ICLAR15"
bitfld.long 0x34 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x34 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x34 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x34 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x34 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x34 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x34 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x34 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x34 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x34 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x34 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x34 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x34 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x34 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x34 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x38 "GICD_ICLAR16,GICD_ICLAR16"
bitfld.long 0x38 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x38 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x38 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x38 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x38 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x38 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x38 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x38 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x38 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x38 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x38 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x38 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x38 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x38 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x38 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x38 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x3C "GICD_ICLAR17,GICD_ICLAR17"
bitfld.long 0x3C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x3C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x3C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x3C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x3C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x3C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x3C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x3C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x3C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x3C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x3C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x3C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x3C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x3C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x3C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x3C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x40 "GICD_ICLAR18,GICD_ICLAR18"
bitfld.long 0x40 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x40 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x40 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x40 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x40 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x40 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x40 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x40 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x40 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x40 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x40 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x40 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x40 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x40 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x40 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x40 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x44 "GICD_ICLAR19,GICD_ICLAR19"
bitfld.long 0x44 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x44 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x44 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x44 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x44 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x44 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x44 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x44 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x44 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x44 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x44 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x44 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x44 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x44 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x44 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x44 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x48 "GICD_ICLAR20,GICD_ICLAR20"
bitfld.long 0x48 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x48 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x48 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x48 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x48 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x48 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x48 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x48 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x48 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x48 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x48 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x48 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x48 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x48 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x48 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x48 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x4C "GICD_ICLAR21,GICD_ICLAR21"
bitfld.long 0x4C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x4C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x4C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x4C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x4C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x4C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x4C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x4C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x4C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x4C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x4C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x4C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x4C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x4C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x4C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x4C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x50 "GICD_ICLAR22,GICD_ICLAR22"
bitfld.long 0x50 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x50 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x50 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x50 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x50 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x50 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x50 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x50 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x50 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x50 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x50 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x50 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x50 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x50 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x50 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x50 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x54 "GICD_ICLAR23,GICD_ICLAR23"
bitfld.long 0x54 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x54 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x54 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x54 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x54 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x54 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x54 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x54 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x54 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x54 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x54 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x54 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x54 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x54 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x54 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x54 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x58 "GICD_ICLAR24,GICD_ICLAR24"
bitfld.long 0x58 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x58 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x58 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x58 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x58 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x58 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x58 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x58 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x58 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x58 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x58 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x58 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x58 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x58 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x58 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x58 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x5C "GICD_ICLAR25,GICD_ICLAR25"
bitfld.long 0x5C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x5C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x5C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x5C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x5C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x5C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x5C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x5C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x5C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x5C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x5C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x5C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x5C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x5C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x5C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x5C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x60 "GICD_ICLAR26,GICD_ICLAR26"
bitfld.long 0x60 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x60 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x60 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x60 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x60 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x60 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x60 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x60 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x60 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x60 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x60 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x60 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x60 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x60 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x60 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x60 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x64 "GICD_ICLAR27,GICD_ICLAR27"
bitfld.long 0x64 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x64 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x64 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x64 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x64 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x64 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x64 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x64 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x64 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x64 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x64 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x64 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x64 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x64 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x64 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x64 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x68 "GICD_ICLAR28,GICD_ICLAR28"
bitfld.long 0x68 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x68 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x68 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x68 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x68 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x68 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x68 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x68 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x68 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x68 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x68 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x68 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x68 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x68 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x68 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x68 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x6C "GICD_ICLAR29,GICD_ICLAR29"
bitfld.long 0x6C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x6C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x6C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x6C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x6C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x6C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x6C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x6C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x6C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x6C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x6C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x6C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x6C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x6C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x6C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x6C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x70 "GICD_ICLAR30,GICD_ICLAR30"
bitfld.long 0x70 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x70 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x70 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x70 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x70 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x70 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x70 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x70 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x70 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x70 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x70 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x70 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x70 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x70 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x70 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x70 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x74 "GICD_ICLAR31,GICD_ICLAR31"
bitfld.long 0x74 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x74 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x74 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x74 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x74 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x74 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x74 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x74 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x74 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x74 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x74 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x74 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x74 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x74 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x74 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x74 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x78 "GICD_ICLAR32,GICD_ICLAR32"
bitfld.long 0x78 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x78 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x78 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x78 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x78 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x78 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x78 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x78 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x78 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x78 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x78 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x78 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x78 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x78 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x78 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x78 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x7C "GICD_ICLAR33,GICD_ICLAR33"
bitfld.long 0x7C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x7C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x7C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x7C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x7C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x7C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x7C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x7C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x7C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x7C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x7C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x7C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x7C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x7C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x7C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x7C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x80 "GICD_ICLAR34,GICD_ICLAR34"
bitfld.long 0x80 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x80 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x80 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x80 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x80 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x80 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x80 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x80 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x80 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x80 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x80 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x80 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x80 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x80 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x80 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x80 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x84 "GICD_ICLAR35,GICD_ICLAR35"
bitfld.long 0x84 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x84 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x84 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x84 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x84 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x84 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x84 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x84 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x84 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x84 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x84 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x84 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x84 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x84 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x84 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x84 0.--1. "classes0,classes0" "0,1,2,3"
group.long 0xE104++0x43
line.long 0x0 "GICD_IERRR1,GICD_IERRR1"
bitfld.long 0x0 31. "status31,status31" "0,1"
bitfld.long 0x0 30. "status30,status30" "0,1"
newline
bitfld.long 0x0 29. "status29,status29" "0,1"
bitfld.long 0x0 28. "status28,status28" "0,1"
newline
bitfld.long 0x0 27. "status27,status27" "0,1"
bitfld.long 0x0 26. "status26,status26" "0,1"
newline
bitfld.long 0x0 25. "status25,status25" "0,1"
bitfld.long 0x0 24. "status24,status24" "0,1"
newline
bitfld.long 0x0 23. "status23,status23" "0,1"
bitfld.long 0x0 22. "status22,status22" "0,1"
newline
bitfld.long 0x0 21. "status21,status21" "0,1"
bitfld.long 0x0 20. "status20,status20" "0,1"
newline
bitfld.long 0x0 19. "status19,status19" "0,1"
bitfld.long 0x0 18. "status18,status18" "0,1"
newline
bitfld.long 0x0 17. "status17,status17" "0,1"
bitfld.long 0x0 16. "status16,status16" "0,1"
newline
bitfld.long 0x0 15. "status15,status15" "0,1"
bitfld.long 0x0 14. "status14,status14" "0,1"
newline
bitfld.long 0x0 13. "status13,status13" "0,1"
bitfld.long 0x0 12. "status12,status12" "0,1"
newline
bitfld.long 0x0 11. "status11,status11" "0,1"
bitfld.long 0x0 10. "status10,status10" "0,1"
newline
bitfld.long 0x0 9. "status9,status9" "0,1"
bitfld.long 0x0 8. "status8,status8" "0,1"
newline
bitfld.long 0x0 7. "status7,status7" "0,1"
bitfld.long 0x0 6. "status6,status6" "0,1"
newline
bitfld.long 0x0 5. "status5,status5" "0,1"
bitfld.long 0x0 4. "status4,status4" "0,1"
newline
bitfld.long 0x0 3. "status3,status3" "0,1"
bitfld.long 0x0 2. "status2,status2" "0,1"
newline
bitfld.long 0x0 1. "status1,status1" "0,1"
bitfld.long 0x0 0. "status0,status0" "0,1"
line.long 0x4 "GICD_IERRR2,GICD_IERRR2"
bitfld.long 0x4 31. "status31,status31" "0,1"
bitfld.long 0x4 30. "status30,status30" "0,1"
newline
bitfld.long 0x4 29. "status29,status29" "0,1"
bitfld.long 0x4 28. "status28,status28" "0,1"
newline
bitfld.long 0x4 27. "status27,status27" "0,1"
bitfld.long 0x4 26. "status26,status26" "0,1"
newline
bitfld.long 0x4 25. "status25,status25" "0,1"
bitfld.long 0x4 24. "status24,status24" "0,1"
newline
bitfld.long 0x4 23. "status23,status23" "0,1"
bitfld.long 0x4 22. "status22,status22" "0,1"
newline
bitfld.long 0x4 21. "status21,status21" "0,1"
bitfld.long 0x4 20. "status20,status20" "0,1"
newline
bitfld.long 0x4 19. "status19,status19" "0,1"
bitfld.long 0x4 18. "status18,status18" "0,1"
newline
bitfld.long 0x4 17. "status17,status17" "0,1"
bitfld.long 0x4 16. "status16,status16" "0,1"
newline
bitfld.long 0x4 15. "status15,status15" "0,1"
bitfld.long 0x4 14. "status14,status14" "0,1"
newline
bitfld.long 0x4 13. "status13,status13" "0,1"
bitfld.long 0x4 12. "status12,status12" "0,1"
newline
bitfld.long 0x4 11. "status11,status11" "0,1"
bitfld.long 0x4 10. "status10,status10" "0,1"
newline
bitfld.long 0x4 9. "status9,status9" "0,1"
bitfld.long 0x4 8. "status8,status8" "0,1"
newline
bitfld.long 0x4 7. "status7,status7" "0,1"
bitfld.long 0x4 6. "status6,status6" "0,1"
newline
bitfld.long 0x4 5. "status5,status5" "0,1"
bitfld.long 0x4 4. "status4,status4" "0,1"
newline
bitfld.long 0x4 3. "status3,status3" "0,1"
bitfld.long 0x4 2. "status2,status2" "0,1"
newline
bitfld.long 0x4 1. "status1,status1" "0,1"
bitfld.long 0x4 0. "status0,status0" "0,1"
line.long 0x8 "GICD_IERRR3,GICD_IERRR3"
bitfld.long 0x8 31. "status31,status31" "0,1"
bitfld.long 0x8 30. "status30,status30" "0,1"
newline
bitfld.long 0x8 29. "status29,status29" "0,1"
bitfld.long 0x8 28. "status28,status28" "0,1"
newline
bitfld.long 0x8 27. "status27,status27" "0,1"
bitfld.long 0x8 26. "status26,status26" "0,1"
newline
bitfld.long 0x8 25. "status25,status25" "0,1"
bitfld.long 0x8 24. "status24,status24" "0,1"
newline
bitfld.long 0x8 23. "status23,status23" "0,1"
bitfld.long 0x8 22. "status22,status22" "0,1"
newline
bitfld.long 0x8 21. "status21,status21" "0,1"
bitfld.long 0x8 20. "status20,status20" "0,1"
newline
bitfld.long 0x8 19. "status19,status19" "0,1"
bitfld.long 0x8 18. "status18,status18" "0,1"
newline
bitfld.long 0x8 17. "status17,status17" "0,1"
bitfld.long 0x8 16. "status16,status16" "0,1"
newline
bitfld.long 0x8 15. "status15,status15" "0,1"
bitfld.long 0x8 14. "status14,status14" "0,1"
newline
bitfld.long 0x8 13. "status13,status13" "0,1"
bitfld.long 0x8 12. "status12,status12" "0,1"
newline
bitfld.long 0x8 11. "status11,status11" "0,1"
bitfld.long 0x8 10. "status10,status10" "0,1"
newline
bitfld.long 0x8 9. "status9,status9" "0,1"
bitfld.long 0x8 8. "status8,status8" "0,1"
newline
bitfld.long 0x8 7. "status7,status7" "0,1"
bitfld.long 0x8 6. "status6,status6" "0,1"
newline
bitfld.long 0x8 5. "status5,status5" "0,1"
bitfld.long 0x8 4. "status4,status4" "0,1"
newline
bitfld.long 0x8 3. "status3,status3" "0,1"
bitfld.long 0x8 2. "status2,status2" "0,1"
newline
bitfld.long 0x8 1. "status1,status1" "0,1"
bitfld.long 0x8 0. "status0,status0" "0,1"
line.long 0xC "GICD_IERRR4,GICD_IERRR4"
bitfld.long 0xC 31. "status31,status31" "0,1"
bitfld.long 0xC 30. "status30,status30" "0,1"
newline
bitfld.long 0xC 29. "status29,status29" "0,1"
bitfld.long 0xC 28. "status28,status28" "0,1"
newline
bitfld.long 0xC 27. "status27,status27" "0,1"
bitfld.long 0xC 26. "status26,status26" "0,1"
newline
bitfld.long 0xC 25. "status25,status25" "0,1"
bitfld.long 0xC 24. "status24,status24" "0,1"
newline
bitfld.long 0xC 23. "status23,status23" "0,1"
bitfld.long 0xC 22. "status22,status22" "0,1"
newline
bitfld.long 0xC 21. "status21,status21" "0,1"
bitfld.long 0xC 20. "status20,status20" "0,1"
newline
bitfld.long 0xC 19. "status19,status19" "0,1"
bitfld.long 0xC 18. "status18,status18" "0,1"
newline
bitfld.long 0xC 17. "status17,status17" "0,1"
bitfld.long 0xC 16. "status16,status16" "0,1"
newline
bitfld.long 0xC 15. "status15,status15" "0,1"
bitfld.long 0xC 14. "status14,status14" "0,1"
newline
bitfld.long 0xC 13. "status13,status13" "0,1"
bitfld.long 0xC 12. "status12,status12" "0,1"
newline
bitfld.long 0xC 11. "status11,status11" "0,1"
bitfld.long 0xC 10. "status10,status10" "0,1"
newline
bitfld.long 0xC 9. "status9,status9" "0,1"
bitfld.long 0xC 8. "status8,status8" "0,1"
newline
bitfld.long 0xC 7. "status7,status7" "0,1"
bitfld.long 0xC 6. "status6,status6" "0,1"
newline
bitfld.long 0xC 5. "status5,status5" "0,1"
bitfld.long 0xC 4. "status4,status4" "0,1"
newline
bitfld.long 0xC 3. "status3,status3" "0,1"
bitfld.long 0xC 2. "status2,status2" "0,1"
newline
bitfld.long 0xC 1. "status1,status1" "0,1"
bitfld.long 0xC 0. "status0,status0" "0,1"
line.long 0x10 "GICD_IERRR5,GICD_IERRR5"
bitfld.long 0x10 31. "status31,status31" "0,1"
bitfld.long 0x10 30. "status30,status30" "0,1"
newline
bitfld.long 0x10 29. "status29,status29" "0,1"
bitfld.long 0x10 28. "status28,status28" "0,1"
newline
bitfld.long 0x10 27. "status27,status27" "0,1"
bitfld.long 0x10 26. "status26,status26" "0,1"
newline
bitfld.long 0x10 25. "status25,status25" "0,1"
bitfld.long 0x10 24. "status24,status24" "0,1"
newline
bitfld.long 0x10 23. "status23,status23" "0,1"
bitfld.long 0x10 22. "status22,status22" "0,1"
newline
bitfld.long 0x10 21. "status21,status21" "0,1"
bitfld.long 0x10 20. "status20,status20" "0,1"
newline
bitfld.long 0x10 19. "status19,status19" "0,1"
bitfld.long 0x10 18. "status18,status18" "0,1"
newline
bitfld.long 0x10 17. "status17,status17" "0,1"
bitfld.long 0x10 16. "status16,status16" "0,1"
newline
bitfld.long 0x10 15. "status15,status15" "0,1"
bitfld.long 0x10 14. "status14,status14" "0,1"
newline
bitfld.long 0x10 13. "status13,status13" "0,1"
bitfld.long 0x10 12. "status12,status12" "0,1"
newline
bitfld.long 0x10 11. "status11,status11" "0,1"
bitfld.long 0x10 10. "status10,status10" "0,1"
newline
bitfld.long 0x10 9. "status9,status9" "0,1"
bitfld.long 0x10 8. "status8,status8" "0,1"
newline
bitfld.long 0x10 7. "status7,status7" "0,1"
bitfld.long 0x10 6. "status6,status6" "0,1"
newline
bitfld.long 0x10 5. "status5,status5" "0,1"
bitfld.long 0x10 4. "status4,status4" "0,1"
newline
bitfld.long 0x10 3. "status3,status3" "0,1"
bitfld.long 0x10 2. "status2,status2" "0,1"
newline
bitfld.long 0x10 1. "status1,status1" "0,1"
bitfld.long 0x10 0. "status0,status0" "0,1"
line.long 0x14 "GICD_IERRR6,GICD_IERRR6"
bitfld.long 0x14 31. "status31,status31" "0,1"
bitfld.long 0x14 30. "status30,status30" "0,1"
newline
bitfld.long 0x14 29. "status29,status29" "0,1"
bitfld.long 0x14 28. "status28,status28" "0,1"
newline
bitfld.long 0x14 27. "status27,status27" "0,1"
bitfld.long 0x14 26. "status26,status26" "0,1"
newline
bitfld.long 0x14 25. "status25,status25" "0,1"
bitfld.long 0x14 24. "status24,status24" "0,1"
newline
bitfld.long 0x14 23. "status23,status23" "0,1"
bitfld.long 0x14 22. "status22,status22" "0,1"
newline
bitfld.long 0x14 21. "status21,status21" "0,1"
bitfld.long 0x14 20. "status20,status20" "0,1"
newline
bitfld.long 0x14 19. "status19,status19" "0,1"
bitfld.long 0x14 18. "status18,status18" "0,1"
newline
bitfld.long 0x14 17. "status17,status17" "0,1"
bitfld.long 0x14 16. "status16,status16" "0,1"
newline
bitfld.long 0x14 15. "status15,status15" "0,1"
bitfld.long 0x14 14. "status14,status14" "0,1"
newline
bitfld.long 0x14 13. "status13,status13" "0,1"
bitfld.long 0x14 12. "status12,status12" "0,1"
newline
bitfld.long 0x14 11. "status11,status11" "0,1"
bitfld.long 0x14 10. "status10,status10" "0,1"
newline
bitfld.long 0x14 9. "status9,status9" "0,1"
bitfld.long 0x14 8. "status8,status8" "0,1"
newline
bitfld.long 0x14 7. "status7,status7" "0,1"
bitfld.long 0x14 6. "status6,status6" "0,1"
newline
bitfld.long 0x14 5. "status5,status5" "0,1"
bitfld.long 0x14 4. "status4,status4" "0,1"
newline
bitfld.long 0x14 3. "status3,status3" "0,1"
bitfld.long 0x14 2. "status2,status2" "0,1"
newline
bitfld.long 0x14 1. "status1,status1" "0,1"
bitfld.long 0x14 0. "status0,status0" "0,1"
line.long 0x18 "GICD_IERRR7,GICD_IERRR7"
bitfld.long 0x18 31. "status31,status31" "0,1"
bitfld.long 0x18 30. "status30,status30" "0,1"
newline
bitfld.long 0x18 29. "status29,status29" "0,1"
bitfld.long 0x18 28. "status28,status28" "0,1"
newline
bitfld.long 0x18 27. "status27,status27" "0,1"
bitfld.long 0x18 26. "status26,status26" "0,1"
newline
bitfld.long 0x18 25. "status25,status25" "0,1"
bitfld.long 0x18 24. "status24,status24" "0,1"
newline
bitfld.long 0x18 23. "status23,status23" "0,1"
bitfld.long 0x18 22. "status22,status22" "0,1"
newline
bitfld.long 0x18 21. "status21,status21" "0,1"
bitfld.long 0x18 20. "status20,status20" "0,1"
newline
bitfld.long 0x18 19. "status19,status19" "0,1"
bitfld.long 0x18 18. "status18,status18" "0,1"
newline
bitfld.long 0x18 17. "status17,status17" "0,1"
bitfld.long 0x18 16. "status16,status16" "0,1"
newline
bitfld.long 0x18 15. "status15,status15" "0,1"
bitfld.long 0x18 14. "status14,status14" "0,1"
newline
bitfld.long 0x18 13. "status13,status13" "0,1"
bitfld.long 0x18 12. "status12,status12" "0,1"
newline
bitfld.long 0x18 11. "status11,status11" "0,1"
bitfld.long 0x18 10. "status10,status10" "0,1"
newline
bitfld.long 0x18 9. "status9,status9" "0,1"
bitfld.long 0x18 8. "status8,status8" "0,1"
newline
bitfld.long 0x18 7. "status7,status7" "0,1"
bitfld.long 0x18 6. "status6,status6" "0,1"
newline
bitfld.long 0x18 5. "status5,status5" "0,1"
bitfld.long 0x18 4. "status4,status4" "0,1"
newline
bitfld.long 0x18 3. "status3,status3" "0,1"
bitfld.long 0x18 2. "status2,status2" "0,1"
newline
bitfld.long 0x18 1. "status1,status1" "0,1"
bitfld.long 0x18 0. "status0,status0" "0,1"
line.long 0x1C "GICD_IERRR8,GICD_IERRR8"
bitfld.long 0x1C 31. "status31,status31" "0,1"
bitfld.long 0x1C 30. "status30,status30" "0,1"
newline
bitfld.long 0x1C 29. "status29,status29" "0,1"
bitfld.long 0x1C 28. "status28,status28" "0,1"
newline
bitfld.long 0x1C 27. "status27,status27" "0,1"
bitfld.long 0x1C 26. "status26,status26" "0,1"
newline
bitfld.long 0x1C 25. "status25,status25" "0,1"
bitfld.long 0x1C 24. "status24,status24" "0,1"
newline
bitfld.long 0x1C 23. "status23,status23" "0,1"
bitfld.long 0x1C 22. "status22,status22" "0,1"
newline
bitfld.long 0x1C 21. "status21,status21" "0,1"
bitfld.long 0x1C 20. "status20,status20" "0,1"
newline
bitfld.long 0x1C 19. "status19,status19" "0,1"
bitfld.long 0x1C 18. "status18,status18" "0,1"
newline
bitfld.long 0x1C 17. "status17,status17" "0,1"
bitfld.long 0x1C 16. "status16,status16" "0,1"
newline
bitfld.long 0x1C 15. "status15,status15" "0,1"
bitfld.long 0x1C 14. "status14,status14" "0,1"
newline
bitfld.long 0x1C 13. "status13,status13" "0,1"
bitfld.long 0x1C 12. "status12,status12" "0,1"
newline
bitfld.long 0x1C 11. "status11,status11" "0,1"
bitfld.long 0x1C 10. "status10,status10" "0,1"
newline
bitfld.long 0x1C 9. "status9,status9" "0,1"
bitfld.long 0x1C 8. "status8,status8" "0,1"
newline
bitfld.long 0x1C 7. "status7,status7" "0,1"
bitfld.long 0x1C 6. "status6,status6" "0,1"
newline
bitfld.long 0x1C 5. "status5,status5" "0,1"
bitfld.long 0x1C 4. "status4,status4" "0,1"
newline
bitfld.long 0x1C 3. "status3,status3" "0,1"
bitfld.long 0x1C 2. "status2,status2" "0,1"
newline
bitfld.long 0x1C 1. "status1,status1" "0,1"
bitfld.long 0x1C 0. "status0,status0" "0,1"
line.long 0x20 "GICD_IERRR9,GICD_IERRR9"
bitfld.long 0x20 31. "status31,status31" "0,1"
bitfld.long 0x20 30. "status30,status30" "0,1"
newline
bitfld.long 0x20 29. "status29,status29" "0,1"
bitfld.long 0x20 28. "status28,status28" "0,1"
newline
bitfld.long 0x20 27. "status27,status27" "0,1"
bitfld.long 0x20 26. "status26,status26" "0,1"
newline
bitfld.long 0x20 25. "status25,status25" "0,1"
bitfld.long 0x20 24. "status24,status24" "0,1"
newline
bitfld.long 0x20 23. "status23,status23" "0,1"
bitfld.long 0x20 22. "status22,status22" "0,1"
newline
bitfld.long 0x20 21. "status21,status21" "0,1"
bitfld.long 0x20 20. "status20,status20" "0,1"
newline
bitfld.long 0x20 19. "status19,status19" "0,1"
bitfld.long 0x20 18. "status18,status18" "0,1"
newline
bitfld.long 0x20 17. "status17,status17" "0,1"
bitfld.long 0x20 16. "status16,status16" "0,1"
newline
bitfld.long 0x20 15. "status15,status15" "0,1"
bitfld.long 0x20 14. "status14,status14" "0,1"
newline
bitfld.long 0x20 13. "status13,status13" "0,1"
bitfld.long 0x20 12. "status12,status12" "0,1"
newline
bitfld.long 0x20 11. "status11,status11" "0,1"
bitfld.long 0x20 10. "status10,status10" "0,1"
newline
bitfld.long 0x20 9. "status9,status9" "0,1"
bitfld.long 0x20 8. "status8,status8" "0,1"
newline
bitfld.long 0x20 7. "status7,status7" "0,1"
bitfld.long 0x20 6. "status6,status6" "0,1"
newline
bitfld.long 0x20 5. "status5,status5" "0,1"
bitfld.long 0x20 4. "status4,status4" "0,1"
newline
bitfld.long 0x20 3. "status3,status3" "0,1"
bitfld.long 0x20 2. "status2,status2" "0,1"
newline
bitfld.long 0x20 1. "status1,status1" "0,1"
bitfld.long 0x20 0. "status0,status0" "0,1"
line.long 0x24 "GICD_IERRR10,GICD_IERRR10"
bitfld.long 0x24 31. "status31,status31" "0,1"
bitfld.long 0x24 30. "status30,status30" "0,1"
newline
bitfld.long 0x24 29. "status29,status29" "0,1"
bitfld.long 0x24 28. "status28,status28" "0,1"
newline
bitfld.long 0x24 27. "status27,status27" "0,1"
bitfld.long 0x24 26. "status26,status26" "0,1"
newline
bitfld.long 0x24 25. "status25,status25" "0,1"
bitfld.long 0x24 24. "status24,status24" "0,1"
newline
bitfld.long 0x24 23. "status23,status23" "0,1"
bitfld.long 0x24 22. "status22,status22" "0,1"
newline
bitfld.long 0x24 21. "status21,status21" "0,1"
bitfld.long 0x24 20. "status20,status20" "0,1"
newline
bitfld.long 0x24 19. "status19,status19" "0,1"
bitfld.long 0x24 18. "status18,status18" "0,1"
newline
bitfld.long 0x24 17. "status17,status17" "0,1"
bitfld.long 0x24 16. "status16,status16" "0,1"
newline
bitfld.long 0x24 15. "status15,status15" "0,1"
bitfld.long 0x24 14. "status14,status14" "0,1"
newline
bitfld.long 0x24 13. "status13,status13" "0,1"
bitfld.long 0x24 12. "status12,status12" "0,1"
newline
bitfld.long 0x24 11. "status11,status11" "0,1"
bitfld.long 0x24 10. "status10,status10" "0,1"
newline
bitfld.long 0x24 9. "status9,status9" "0,1"
bitfld.long 0x24 8. "status8,status8" "0,1"
newline
bitfld.long 0x24 7. "status7,status7" "0,1"
bitfld.long 0x24 6. "status6,status6" "0,1"
newline
bitfld.long 0x24 5. "status5,status5" "0,1"
bitfld.long 0x24 4. "status4,status4" "0,1"
newline
bitfld.long 0x24 3. "status3,status3" "0,1"
bitfld.long 0x24 2. "status2,status2" "0,1"
newline
bitfld.long 0x24 1. "status1,status1" "0,1"
bitfld.long 0x24 0. "status0,status0" "0,1"
line.long 0x28 "GICD_IERRR11,GICD_IERRR11"
bitfld.long 0x28 31. "status31,status31" "0,1"
bitfld.long 0x28 30. "status30,status30" "0,1"
newline
bitfld.long 0x28 29. "status29,status29" "0,1"
bitfld.long 0x28 28. "status28,status28" "0,1"
newline
bitfld.long 0x28 27. "status27,status27" "0,1"
bitfld.long 0x28 26. "status26,status26" "0,1"
newline
bitfld.long 0x28 25. "status25,status25" "0,1"
bitfld.long 0x28 24. "status24,status24" "0,1"
newline
bitfld.long 0x28 23. "status23,status23" "0,1"
bitfld.long 0x28 22. "status22,status22" "0,1"
newline
bitfld.long 0x28 21. "status21,status21" "0,1"
bitfld.long 0x28 20. "status20,status20" "0,1"
newline
bitfld.long 0x28 19. "status19,status19" "0,1"
bitfld.long 0x28 18. "status18,status18" "0,1"
newline
bitfld.long 0x28 17. "status17,status17" "0,1"
bitfld.long 0x28 16. "status16,status16" "0,1"
newline
bitfld.long 0x28 15. "status15,status15" "0,1"
bitfld.long 0x28 14. "status14,status14" "0,1"
newline
bitfld.long 0x28 13. "status13,status13" "0,1"
bitfld.long 0x28 12. "status12,status12" "0,1"
newline
bitfld.long 0x28 11. "status11,status11" "0,1"
bitfld.long 0x28 10. "status10,status10" "0,1"
newline
bitfld.long 0x28 9. "status9,status9" "0,1"
bitfld.long 0x28 8. "status8,status8" "0,1"
newline
bitfld.long 0x28 7. "status7,status7" "0,1"
bitfld.long 0x28 6. "status6,status6" "0,1"
newline
bitfld.long 0x28 5. "status5,status5" "0,1"
bitfld.long 0x28 4. "status4,status4" "0,1"
newline
bitfld.long 0x28 3. "status3,status3" "0,1"
bitfld.long 0x28 2. "status2,status2" "0,1"
newline
bitfld.long 0x28 1. "status1,status1" "0,1"
bitfld.long 0x28 0. "status0,status0" "0,1"
line.long 0x2C "GICD_IERRR12,GICD_IERRR12"
bitfld.long 0x2C 31. "status31,status31" "0,1"
bitfld.long 0x2C 30. "status30,status30" "0,1"
newline
bitfld.long 0x2C 29. "status29,status29" "0,1"
bitfld.long 0x2C 28. "status28,status28" "0,1"
newline
bitfld.long 0x2C 27. "status27,status27" "0,1"
bitfld.long 0x2C 26. "status26,status26" "0,1"
newline
bitfld.long 0x2C 25. "status25,status25" "0,1"
bitfld.long 0x2C 24. "status24,status24" "0,1"
newline
bitfld.long 0x2C 23. "status23,status23" "0,1"
bitfld.long 0x2C 22. "status22,status22" "0,1"
newline
bitfld.long 0x2C 21. "status21,status21" "0,1"
bitfld.long 0x2C 20. "status20,status20" "0,1"
newline
bitfld.long 0x2C 19. "status19,status19" "0,1"
bitfld.long 0x2C 18. "status18,status18" "0,1"
newline
bitfld.long 0x2C 17. "status17,status17" "0,1"
bitfld.long 0x2C 16. "status16,status16" "0,1"
newline
bitfld.long 0x2C 15. "status15,status15" "0,1"
bitfld.long 0x2C 14. "status14,status14" "0,1"
newline
bitfld.long 0x2C 13. "status13,status13" "0,1"
bitfld.long 0x2C 12. "status12,status12" "0,1"
newline
bitfld.long 0x2C 11. "status11,status11" "0,1"
bitfld.long 0x2C 10. "status10,status10" "0,1"
newline
bitfld.long 0x2C 9. "status9,status9" "0,1"
bitfld.long 0x2C 8. "status8,status8" "0,1"
newline
bitfld.long 0x2C 7. "status7,status7" "0,1"
bitfld.long 0x2C 6. "status6,status6" "0,1"
newline
bitfld.long 0x2C 5. "status5,status5" "0,1"
bitfld.long 0x2C 4. "status4,status4" "0,1"
newline
bitfld.long 0x2C 3. "status3,status3" "0,1"
bitfld.long 0x2C 2. "status2,status2" "0,1"
newline
bitfld.long 0x2C 1. "status1,status1" "0,1"
bitfld.long 0x2C 0. "status0,status0" "0,1"
line.long 0x30 "GICD_IERRR13,GICD_IERRR13"
bitfld.long 0x30 31. "status31,status31" "0,1"
bitfld.long 0x30 30. "status30,status30" "0,1"
newline
bitfld.long 0x30 29. "status29,status29" "0,1"
bitfld.long 0x30 28. "status28,status28" "0,1"
newline
bitfld.long 0x30 27. "status27,status27" "0,1"
bitfld.long 0x30 26. "status26,status26" "0,1"
newline
bitfld.long 0x30 25. "status25,status25" "0,1"
bitfld.long 0x30 24. "status24,status24" "0,1"
newline
bitfld.long 0x30 23. "status23,status23" "0,1"
bitfld.long 0x30 22. "status22,status22" "0,1"
newline
bitfld.long 0x30 21. "status21,status21" "0,1"
bitfld.long 0x30 20. "status20,status20" "0,1"
newline
bitfld.long 0x30 19. "status19,status19" "0,1"
bitfld.long 0x30 18. "status18,status18" "0,1"
newline
bitfld.long 0x30 17. "status17,status17" "0,1"
bitfld.long 0x30 16. "status16,status16" "0,1"
newline
bitfld.long 0x30 15. "status15,status15" "0,1"
bitfld.long 0x30 14. "status14,status14" "0,1"
newline
bitfld.long 0x30 13. "status13,status13" "0,1"
bitfld.long 0x30 12. "status12,status12" "0,1"
newline
bitfld.long 0x30 11. "status11,status11" "0,1"
bitfld.long 0x30 10. "status10,status10" "0,1"
newline
bitfld.long 0x30 9. "status9,status9" "0,1"
bitfld.long 0x30 8. "status8,status8" "0,1"
newline
bitfld.long 0x30 7. "status7,status7" "0,1"
bitfld.long 0x30 6. "status6,status6" "0,1"
newline
bitfld.long 0x30 5. "status5,status5" "0,1"
bitfld.long 0x30 4. "status4,status4" "0,1"
newline
bitfld.long 0x30 3. "status3,status3" "0,1"
bitfld.long 0x30 2. "status2,status2" "0,1"
newline
bitfld.long 0x30 1. "status1,status1" "0,1"
bitfld.long 0x30 0. "status0,status0" "0,1"
line.long 0x34 "GICD_IERRR14,GICD_IERRR14"
bitfld.long 0x34 31. "status31,status31" "0,1"
bitfld.long 0x34 30. "status30,status30" "0,1"
newline
bitfld.long 0x34 29. "status29,status29" "0,1"
bitfld.long 0x34 28. "status28,status28" "0,1"
newline
bitfld.long 0x34 27. "status27,status27" "0,1"
bitfld.long 0x34 26. "status26,status26" "0,1"
newline
bitfld.long 0x34 25. "status25,status25" "0,1"
bitfld.long 0x34 24. "status24,status24" "0,1"
newline
bitfld.long 0x34 23. "status23,status23" "0,1"
bitfld.long 0x34 22. "status22,status22" "0,1"
newline
bitfld.long 0x34 21. "status21,status21" "0,1"
bitfld.long 0x34 20. "status20,status20" "0,1"
newline
bitfld.long 0x34 19. "status19,status19" "0,1"
bitfld.long 0x34 18. "status18,status18" "0,1"
newline
bitfld.long 0x34 17. "status17,status17" "0,1"
bitfld.long 0x34 16. "status16,status16" "0,1"
newline
bitfld.long 0x34 15. "status15,status15" "0,1"
bitfld.long 0x34 14. "status14,status14" "0,1"
newline
bitfld.long 0x34 13. "status13,status13" "0,1"
bitfld.long 0x34 12. "status12,status12" "0,1"
newline
bitfld.long 0x34 11. "status11,status11" "0,1"
bitfld.long 0x34 10. "status10,status10" "0,1"
newline
bitfld.long 0x34 9. "status9,status9" "0,1"
bitfld.long 0x34 8. "status8,status8" "0,1"
newline
bitfld.long 0x34 7. "status7,status7" "0,1"
bitfld.long 0x34 6. "status6,status6" "0,1"
newline
bitfld.long 0x34 5. "status5,status5" "0,1"
bitfld.long 0x34 4. "status4,status4" "0,1"
newline
bitfld.long 0x34 3. "status3,status3" "0,1"
bitfld.long 0x34 2. "status2,status2" "0,1"
newline
bitfld.long 0x34 1. "status1,status1" "0,1"
bitfld.long 0x34 0. "status0,status0" "0,1"
line.long 0x38 "GICD_IERRR15,GICD_IERRR15"
bitfld.long 0x38 31. "status31,status31" "0,1"
bitfld.long 0x38 30. "status30,status30" "0,1"
newline
bitfld.long 0x38 29. "status29,status29" "0,1"
bitfld.long 0x38 28. "status28,status28" "0,1"
newline
bitfld.long 0x38 27. "status27,status27" "0,1"
bitfld.long 0x38 26. "status26,status26" "0,1"
newline
bitfld.long 0x38 25. "status25,status25" "0,1"
bitfld.long 0x38 24. "status24,status24" "0,1"
newline
bitfld.long 0x38 23. "status23,status23" "0,1"
bitfld.long 0x38 22. "status22,status22" "0,1"
newline
bitfld.long 0x38 21. "status21,status21" "0,1"
bitfld.long 0x38 20. "status20,status20" "0,1"
newline
bitfld.long 0x38 19. "status19,status19" "0,1"
bitfld.long 0x38 18. "status18,status18" "0,1"
newline
bitfld.long 0x38 17. "status17,status17" "0,1"
bitfld.long 0x38 16. "status16,status16" "0,1"
newline
bitfld.long 0x38 15. "status15,status15" "0,1"
bitfld.long 0x38 14. "status14,status14" "0,1"
newline
bitfld.long 0x38 13. "status13,status13" "0,1"
bitfld.long 0x38 12. "status12,status12" "0,1"
newline
bitfld.long 0x38 11. "status11,status11" "0,1"
bitfld.long 0x38 10. "status10,status10" "0,1"
newline
bitfld.long 0x38 9. "status9,status9" "0,1"
bitfld.long 0x38 8. "status8,status8" "0,1"
newline
bitfld.long 0x38 7. "status7,status7" "0,1"
bitfld.long 0x38 6. "status6,status6" "0,1"
newline
bitfld.long 0x38 5. "status5,status5" "0,1"
bitfld.long 0x38 4. "status4,status4" "0,1"
newline
bitfld.long 0x38 3. "status3,status3" "0,1"
bitfld.long 0x38 2. "status2,status2" "0,1"
newline
bitfld.long 0x38 1. "status1,status1" "0,1"
bitfld.long 0x38 0. "status0,status0" "0,1"
line.long 0x3C "GICD_IERRR16,GICD_IERRR16"
bitfld.long 0x3C 31. "status31,status31" "0,1"
bitfld.long 0x3C 30. "status30,status30" "0,1"
newline
bitfld.long 0x3C 29. "status29,status29" "0,1"
bitfld.long 0x3C 28. "status28,status28" "0,1"
newline
bitfld.long 0x3C 27. "status27,status27" "0,1"
bitfld.long 0x3C 26. "status26,status26" "0,1"
newline
bitfld.long 0x3C 25. "status25,status25" "0,1"
bitfld.long 0x3C 24. "status24,status24" "0,1"
newline
bitfld.long 0x3C 23. "status23,status23" "0,1"
bitfld.long 0x3C 22. "status22,status22" "0,1"
newline
bitfld.long 0x3C 21. "status21,status21" "0,1"
bitfld.long 0x3C 20. "status20,status20" "0,1"
newline
bitfld.long 0x3C 19. "status19,status19" "0,1"
bitfld.long 0x3C 18. "status18,status18" "0,1"
newline
bitfld.long 0x3C 17. "status17,status17" "0,1"
bitfld.long 0x3C 16. "status16,status16" "0,1"
newline
bitfld.long 0x3C 15. "status15,status15" "0,1"
bitfld.long 0x3C 14. "status14,status14" "0,1"
newline
bitfld.long 0x3C 13. "status13,status13" "0,1"
bitfld.long 0x3C 12. "status12,status12" "0,1"
newline
bitfld.long 0x3C 11. "status11,status11" "0,1"
bitfld.long 0x3C 10. "status10,status10" "0,1"
newline
bitfld.long 0x3C 9. "status9,status9" "0,1"
bitfld.long 0x3C 8. "status8,status8" "0,1"
newline
bitfld.long 0x3C 7. "status7,status7" "0,1"
bitfld.long 0x3C 6. "status6,status6" "0,1"
newline
bitfld.long 0x3C 5. "status5,status5" "0,1"
bitfld.long 0x3C 4. "status4,status4" "0,1"
newline
bitfld.long 0x3C 3. "status3,status3" "0,1"
bitfld.long 0x3C 2. "status2,status2" "0,1"
newline
bitfld.long 0x3C 1. "status1,status1" "0,1"
bitfld.long 0x3C 0. "status0,status0" "0,1"
line.long 0x40 "GICD_IERRR17,GICD_IERRR17"
bitfld.long 0x40 31. "status31,status31" "0,1"
bitfld.long 0x40 30. "status30,status30" "0,1"
newline
bitfld.long 0x40 29. "status29,status29" "0,1"
bitfld.long 0x40 28. "status28,status28" "0,1"
newline
bitfld.long 0x40 27. "status27,status27" "0,1"
bitfld.long 0x40 26. "status26,status26" "0,1"
newline
bitfld.long 0x40 25. "status25,status25" "0,1"
bitfld.long 0x40 24. "status24,status24" "0,1"
newline
bitfld.long 0x40 23. "status23,status23" "0,1"
bitfld.long 0x40 22. "status22,status22" "0,1"
newline
bitfld.long 0x40 21. "status21,status21" "0,1"
bitfld.long 0x40 20. "status20,status20" "0,1"
newline
bitfld.long 0x40 19. "status19,status19" "0,1"
bitfld.long 0x40 18. "status18,status18" "0,1"
newline
bitfld.long 0x40 17. "status17,status17" "0,1"
bitfld.long 0x40 16. "status16,status16" "0,1"
newline
bitfld.long 0x40 15. "status15,status15" "0,1"
bitfld.long 0x40 14. "status14,status14" "0,1"
newline
bitfld.long 0x40 13. "status13,status13" "0,1"
bitfld.long 0x40 12. "status12,status12" "0,1"
newline
bitfld.long 0x40 11. "status11,status11" "0,1"
bitfld.long 0x40 10. "status10,status10" "0,1"
newline
bitfld.long 0x40 9. "status9,status9" "0,1"
bitfld.long 0x40 8. "status8,status8" "0,1"
newline
bitfld.long 0x40 7. "status7,status7" "0,1"
bitfld.long 0x40 6. "status6,status6" "0,1"
newline
bitfld.long 0x40 5. "status5,status5" "0,1"
bitfld.long 0x40 4. "status4,status4" "0,1"
newline
bitfld.long 0x40 3. "status3,status3" "0,1"
bitfld.long 0x40 2. "status2,status2" "0,1"
newline
bitfld.long 0x40 1. "status1,status1" "0,1"
bitfld.long 0x40 0. "status0,status0" "0,1"
rgroup.quad 0xF000++0x7
line.quad 0x0 "GICD_CFGID,GICD_CFGID"
hexmask.quad.word 0x0 53.--63. 1. "RESERVED3,RESERVED3"
hexmask.quad.byte 0x0 48.--52. 1. "PEwidth,PEwidth"
newline
hexmask.quad.byte 0x0 44.--47. 1. "Affinity3Bits,Affinity3Bits"
hexmask.quad.byte 0x0 40.--43. 1. "Affinity2Bits,Affinity2Bits"
newline
hexmask.quad.byte 0x0 36.--39. 1. "Affinity1Bits,Affinity1Bits"
hexmask.quad.byte 0x0 32.--35. 1. "Affinity0Bits,Affinity0Bits"
newline
hexmask.quad.word 0x0 21.--31. 1. "RESERVED2,RESERVED2"
hexmask.quad.byte 0x0 15.--20. 1. "SPIGroups,SPIGroups"
newline
bitfld.quad 0x0 14. "ChipAffinityLevel,ChipAffinityLevel" "0,1"
bitfld.quad 0x0 13. "DirectLPI,DirectLPI" "0,1"
newline
bitfld.quad 0x0 12. "LPISupport,LPISupport" "0,1"
hexmask.quad.byte 0x0 8.--11. 1. "RESERVED1,RESERVED1"
newline
hexmask.quad.byte 0x0 4.--7. 1. "SocketNumber,SocketNumber"
bitfld.quad 0x0 1.--3. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 0. "SocketOffline,SocketOffline" "0,1"
rgroup.long 0xFFD0++0x2F
line.long 0x0 "GICD_PIDR4,GICD_PIDR4"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x0 4.--7. 1. "SIZE,SIZE"
newline
hexmask.long.byte 0x0 0.--3. 1. "DES_2,DES_2"
line.long 0x4 "GICD_PIDR5,GICD_PIDR5"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x4 0.--7. 1. "RESERVED,RESERVED"
line.long 0x8 "GICD_PIDR6,GICD_PIDR6"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x8 0.--7. 1. "RESERVED,RESERVED"
line.long 0xC "GICD_PIDR7,GICD_PIDR7"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RESERVED"
line.long 0x10 "GICD_PIDR0,GICD_PIDR0"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x10 0.--7. 1. "PART_0,PART_0"
line.long 0x14 "GICD_PIDR1,GICD_PIDR1"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x14 4.--7. 1. "DES_0,DES_0"
newline
hexmask.long.byte 0x14 0.--3. 1. "PART_1,PART_1"
line.long 0x18 "GICD_PIDR2,GICD_PIDR2"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x18 4.--7. 1. "REVISION,REVISION"
newline
bitfld.long 0x18 3. "JEDEC,JEDEC" "0,1"
bitfld.long 0x18 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7"
line.long 0x1C "GICD_PIDR3,GICD_PIDR3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,REVAND"
newline
bitfld.long 0x1C 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x1C 0.--2. "CMOD,CMOD" "0,1,2,3,4,5,6,7"
line.long 0x20 "GICD_CIDR0,GICD_CIDR0"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,PRMBL_0"
line.long 0x24 "GICD_CIDR1,GICD_CIDR1"
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS"
newline
hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,PRMBL_1"
line.long 0x28 "GICD_CIDR2,GICD_CIDR2"
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,PRMBL_2"
line.long 0x2C "GICD_CIDR3,GICD_CIDR3"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,PRMBL_3"
wgroup.long 0x10040++0x3
line.long 0x0 "GICA_SETSPI_NSR,GICA_SETSPI_NSR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
wgroup.long 0x10048++0x3
line.long 0x0 "GICA_CLRSPI_NSR,GICA_CLRSPI_NSR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
wgroup.long 0x10050++0x3
line.long 0x0 "GICA_SETSPI_SR,GICA_SETSPI_SR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
wgroup.long 0x10058++0x3
line.long 0x0 "GICA_CLRSPI_SR,GICA_CLRSPI_SR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
rgroup.quad 0x20000++0x7
line.quad 0x0 "GICT_ERR0FR,GICT_ERR0FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20008++0xF
line.quad 0x0 "GICT_ERR0CTLR,GICT_ERR0CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR0STATUS,GICT_ERR0STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
rgroup.quad 0x20018++0x7
line.quad 0x0 "GICT_ERR0ADDR,GICT_ERR0ADDR"
bitfld.quad 0x0 63. "NS,NS" "0,1"
hexmask.quad.word 0x0 48.--62. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad 0x0 0.--47. 1. "PADDR,PADDR"
group.quad 0x20020++0xF
line.quad 0x0 "GICT_ERR0MISC0,GICT_ERR0MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR0MISC1,GICT_ERR0MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x20040++0x7
line.quad 0x0 "GICT_ERR1FR,GICT_ERR1FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20048++0xF
line.quad 0x0 "GICT_ERR1CTLR,GICT_ERR1CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR1STATUS,GICT_ERR1STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x20060++0xF
line.quad 0x0 "GICT_ERR1MISC0,GICT_ERR1MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR1MISC1,GICT_ERR1MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x20080++0x7
line.quad 0x0 "GICT_ERR2FR,GICT_ERR2FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20088++0xF
line.quad 0x0 "GICT_ERR2CTLR,GICT_ERR2CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR2STATUS,GICT_ERR2STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x200A0++0xF
line.quad 0x0 "GICT_ERR2MISC0,GICT_ERR2MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR2MISC1,GICT_ERR2MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x200C0++0x7
line.quad 0x0 "GICT_ERR3FR,GICT_ERR3FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x200C8++0xF
line.quad 0x0 "GICT_ERR3CTLR,GICT_ERR3CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR3STATUS,GICT_ERR3STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x200E0++0xF
line.quad 0x0 "GICT_ERR3MISC0,GICT_ERR3MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR3MISC1,GICT_ERR3MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x20100++0x7
line.quad 0x0 "GICT_ERR4FR,GICT_ERR4FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20108++0xF
line.quad 0x0 "GICT_ERR4CTLR,GICT_ERR4CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR4STATUS,GICT_ERR4STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x20120++0xF
line.quad 0x0 "GICT_ERR4MISC0,GICT_ERR4MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR4MISC1,GICT_ERR4MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x20140++0x7
line.quad 0x0 "GICT_ERR5FR,GICT_ERR5FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20148++0xF
line.quad 0x0 "GICT_ERR5CTLR,GICT_ERR5CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR5STATUS,GICT_ERR5STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x20160++0xF
line.quad 0x0 "GICT_ERR5MISC0,GICT_ERR5MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR5MISC1,GICT_ERR5MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x20180++0x7
line.quad 0x0 "GICT_ERR6FR,GICT_ERR6FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20188++0xF
line.quad 0x0 "GICT_ERR6CTLR,GICT_ERR6CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR6STATUS,GICT_ERR6STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x201A0++0xF
line.quad 0x0 "GICT_ERR6MISC0,GICT_ERR6MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR6MISC1,GICT_ERR6MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x201C0++0x7
line.quad 0x0 "GICT_ERR7FR,GICT_ERR7FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x201C8++0xF
line.quad 0x0 "GICT_ERR7CTLR,GICT_ERR7CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR7STATUS,GICT_ERR7STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x201E0++0xF
line.quad 0x0 "GICT_ERR7MISC0,GICT_ERR7MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR7MISC1,GICT_ERR7MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x20200++0x7
line.quad 0x0 "GICT_ERR8FR,GICT_ERR8FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20208++0xF
line.quad 0x0 "GICT_ERR8CTLR,GICT_ERR8CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR8STATUS,GICT_ERR8STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x20220++0xF
line.quad 0x0 "GICT_ERR8MISC0,GICT_ERR8MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR8MISC1,GICT_ERR8MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x20240++0x7
line.quad 0x0 "GICT_ERR9FR,GICT_ERR9FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20248++0xF
line.quad 0x0 "GICT_ERR9CTLR,GICT_ERR9CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR9STATUS,GICT_ERR9STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x20260++0xF
line.quad 0x0 "GICT_ERR9MISC0,GICT_ERR9MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR9MISC1,GICT_ERR9MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x20280++0x7
line.quad 0x0 "GICT_ERR10FR,GICT_ERR10FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20288++0xF
line.quad 0x0 "GICT_ERR10CTLR,GICT_ERR10CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR10STATUS,GICT_ERR10STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x202A0++0xF
line.quad 0x0 "GICT_ERR10MISC0,GICT_ERR10MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR10MISC1,GICT_ERR10MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x202C0++0x7
line.quad 0x0 "GICT_ERR11FR,GICT_ERR11FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x202C8++0xF
line.quad 0x0 "GICT_ERR11CTLR,GICT_ERR11CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR11STATUS,GICT_ERR11STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x202E0++0xF
line.quad 0x0 "GICT_ERR11MISC0,GICT_ERR11MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR11MISC1,GICT_ERR11MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x20300++0x7
line.quad 0x0 "GICT_ERR12FR,GICT_ERR12FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20308++0xF
line.quad 0x0 "GICT_ERR12CTLR,GICT_ERR12CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR12STATUS,GICT_ERR12STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x20320++0xF
line.quad 0x0 "GICT_ERR12MISC0,GICT_ERR12MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR12MISC1,GICT_ERR12MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x20340++0x7
line.quad 0x0 "GICT_ERR13FR,GICT_ERR13FR"
hexmask.quad 0x0 16.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
bitfld.quad 0x0 12.--14. "CEC,CEC" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 10.--11. "CFI,CFI" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "UE,UE" "0,1,2,3"
bitfld.quad 0x0 6.--7. "FI,FI" "0,1,2,3"
newline
bitfld.quad 0x0 4.--5. "UI,UI" "0,1,2,3"
bitfld.quad 0x0 2.--3. "DE,DE" "0,1,2,3"
newline
bitfld.quad 0x0 0.--1. "ED,ED" "0,1,2,3"
group.quad 0x20348++0xF
line.quad 0x0 "GICT_ERR13CTLR,GICT_ERR13CTLR"
hexmask.quad 0x0 16.--63. 1. "RESERVED3,RESERVED3"
bitfld.quad 0x0 15. "RP,RP" "0,1"
newline
hexmask.quad.byte 0x0 9.--14. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 8. "CFI,CFI" "0,1"
newline
rbitfld.quad 0x0 5.--7. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 4. "UE,UE" "0,1"
newline
bitfld.quad 0x0 3. "FI,FI" "0,1"
bitfld.quad 0x0 2. "UI,UI" "0,1"
newline
rbitfld.quad 0x0 0.--1. "RESERVED0,RESERVED0" "0,1,2,3"
line.quad 0x8 "GICT_ERR13STATUS,GICT_ERR13STATUS"
hexmask.quad.long 0x8 32.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x8 31. "AV,AV" "0,1"
newline
bitfld.quad 0x8 30. "V,V" "0,1"
bitfld.quad 0x8 29. "UE,UE" "0,1"
newline
bitfld.quad 0x8 28. "ER,ER" "0,1"
bitfld.quad 0x8 27. "OF,OF" "0,1"
newline
bitfld.quad 0x8 26. "MV,MV" "0,1"
bitfld.quad 0x8 24.--25. "CE,CE" "0,1,2,3"
newline
bitfld.quad 0x8 22.--23. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x8 20.--21. "UET,UET" "0,1,2,3"
newline
hexmask.quad.byte 0x8 16.--19. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x8 8.--15. 1. "IERR,IERR"
newline
hexmask.quad.byte 0x8 0.--7. 1. "SERR,SERR"
group.quad 0x20360++0xF
line.quad 0x0 "GICT_ERR13MISC0,GICT_ERR13MISC0"
hexmask.quad.tbyte 0x0 42.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 41. "RE,RE" "0,1"
newline
bitfld.quad 0x0 40. "OF,OF" "0,1"
hexmask.quad.byte 0x0 32.--39. 1. "CNT,CNT"
newline
hexmask.quad.long 0x0 0.--31. 1. "Data,Data"
line.quad 0x8 "GICT_ERR13MISC1,GICT_ERR13MISC1"
hexmask.quad 0x8 0.--63. 1. "DATA,DATA"
rgroup.quad 0x2E000++0x7
line.quad 0x0 "GICT_ERRGSR0,GICT_ERRGSR0"
hexmask.quad 0x0 0.--63. 1. "Status,Status"
group.quad 0x2E800++0xF
line.quad 0x0 "GICT_ERRIRQCR0,GICT_ERRIRQCR0"
hexmask.quad 0x0 10.--63. 1. "RESERVED0,RESERVED0"
hexmask.quad.word 0x0 0.--9. 1. "SPIID,SPIID"
line.quad 0x8 "GICT_ERRIRQCR1,GICT_ERRIRQCR1"
hexmask.quad 0x8 10.--63. 1. "RESERVED0,RESERVED0"
hexmask.quad.word 0x8 0.--9. 1. "SPIID,SPIID"
rgroup.long 0x2FFBC++0x3
line.long 0x0 "GICT_DEVARCH,GICT_DEVARCH"
hexmask.long.word 0x0 21.--31. 1. "ARCHITECT,ARCHITECT"
bitfld.long 0x0 20. "PRESENT,PRESENT" "0,1"
newline
hexmask.long.byte 0x0 16.--19. 1. "REVISION,REVISION"
hexmask.long.byte 0x0 12.--15. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.word 0x0 0.--11. 1. "ARCHID,ARCHID"
rgroup.long 0x2FFC8++0x3
line.long 0x0 "GICT_DEVID,GICT_DEVID"
hexmask.long.word 0x0 16.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--15. 1. "NumRecords,NumRecords"
rgroup.long 0x2FFD0++0x2F
line.long 0x0 "GICT_PIDR4,GICT_PIDR4"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x0 4.--7. 1. "SIZE,SIZE"
newline
hexmask.long.byte 0x0 0.--3. 1. "DES_2,DES_2"
line.long 0x4 "GICT_PIDR5,GICT_PIDR5"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x4 0.--7. 1. "RESERVED,RESERVED"
line.long 0x8 "GICT_PIDR6,GICT_PIDR6"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x8 0.--7. 1. "RESERVED,RESERVED"
line.long 0xC "GICT_PIDR7,GICT_PIDR7"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RESERVED"
line.long 0x10 "GICT_PIDR0,GICT_PIDR0"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x10 0.--7. 1. "PART_0,PART_0"
line.long 0x14 "GICT_PIDR1,GICT_PIDR1"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x14 4.--7. 1. "DES_0,DES_0"
newline
hexmask.long.byte 0x14 0.--3. 1. "PART_1,PART_1"
line.long 0x18 "GICT_PIDR2,GICT_PIDR2"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x18 4.--7. 1. "REVISION,REVISION"
newline
bitfld.long 0x18 3. "JEDEC,JEDEC" "0,1"
bitfld.long 0x18 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7"
line.long 0x1C "GICT_PIDR3,GICT_PIDR3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,REVAND"
newline
bitfld.long 0x1C 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x1C 0.--2. "CMOD,CMOD" "0,1,2,3,4,5,6,7"
line.long 0x20 "GICT_CIDR0,GICT_CIDR0"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,PRMBL_0"
line.long 0x24 "GICT_CIDR1,GICT_CIDR1"
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS"
newline
hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,PRMBL_1"
line.long 0x28 "GICT_CIDR2,GICT_CIDR2"
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,PRMBL_2"
line.long 0x2C "GICT_CIDR3,GICT_CIDR3"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,PRMBL_3"
group.long 0x30000++0x13
line.long 0x0 "GICP_EVCNTR0,GICP_EVCNTR0"
hexmask.long 0x0 0.--31. 1. "COUNT,COUNT"
line.long 0x4 "GICP_EVCNTR1,GICP_EVCNTR1"
hexmask.long 0x4 0.--31. 1. "COUNT,COUNT"
line.long 0x8 "GICP_EVCNTR2,GICP_EVCNTR2"
hexmask.long 0x8 0.--31. 1. "COUNT,COUNT"
line.long 0xC "GICP_EVCNTR3,GICP_EVCNTR3"
hexmask.long 0xC 0.--31. 1. "COUNT,COUNT"
line.long 0x10 "GICP_EVCNTR4,GICP_EVCNTR4"
hexmask.long 0x10 0.--31. 1. "COUNT,COUNT"
group.long 0x30400++0x13
line.long 0x0 "GICP_EVTYPER0,GICP_EVTYPER0"
bitfld.long 0x0 31. "OVCAP,OVCAP" "0,1"
hexmask.long.word 0x0 18.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0x0 16.--17. "EVENT_TYPE,EVENT_TYPE" "0,1,2,3"
hexmask.long.byte 0x0 8.--15. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x0 0.--7. 1. "EVENT,EVENT"
line.long 0x4 "GICP_EVTYPER1,GICP_EVTYPER1"
bitfld.long 0x4 31. "OVCAP,OVCAP" "0,1"
hexmask.long.word 0x4 18.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0x4 16.--17. "EVENT_TYPE,EVENT_TYPE" "0,1,2,3"
hexmask.long.byte 0x4 8.--15. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x4 0.--7. 1. "EVENT,EVENT"
line.long 0x8 "GICP_EVTYPER2,GICP_EVTYPER2"
bitfld.long 0x8 31. "OVCAP,OVCAP" "0,1"
hexmask.long.word 0x8 18.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0x8 16.--17. "EVENT_TYPE,EVENT_TYPE" "0,1,2,3"
hexmask.long.byte 0x8 8.--15. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x8 0.--7. 1. "EVENT,EVENT"
line.long 0xC "GICP_EVTYPER3,GICP_EVTYPER3"
bitfld.long 0xC 31. "OVCAP,OVCAP" "0,1"
hexmask.long.word 0xC 18.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0xC 16.--17. "EVENT_TYPE,EVENT_TYPE" "0,1,2,3"
hexmask.long.byte 0xC 8.--15. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0xC 0.--7. 1. "EVENT,EVENT"
line.long 0x10 "GICP_EVTYPER4,GICP_EVTYPER4"
bitfld.long 0x10 31. "OVCAP,OVCAP" "0,1"
hexmask.long.word 0x10 18.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0x10 16.--17. "EVENT_TYPE,EVENT_TYPE" "0,1,2,3"
hexmask.long.byte 0x10 8.--15. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x10 0.--7. 1. "EVENT,EVENT"
rgroup.long 0x30600++0x13
line.long 0x0 "GICP_SVR0,GICP_SVR0"
hexmask.long 0x0 0.--31. 1. "COUNT,COUNT"
line.long 0x4 "GICP_SVR1,GICP_SVR1"
hexmask.long 0x4 0.--31. 1. "COUNT,COUNT"
line.long 0x8 "GICP_SVR2,GICP_SVR2"
hexmask.long 0x8 0.--31. 1. "COUNT,COUNT"
line.long 0xC "GICP_SVR3,GICP_SVR3"
hexmask.long 0xC 0.--31. 1. "COUNT,COUNT"
line.long 0x10 "GICP_SVR4,GICP_SVR4"
hexmask.long 0x10 0.--31. 1. "COUNT,COUNT"
group.long 0x30A00++0x13
line.long 0x0 "GICP_FR0,GICP_FR0"
bitfld.long 0x0 30.--31. "FilterType,FilterType" "0,1,2,3"
bitfld.long 0x0 29. "FilterEncoding,FilterEncoding" "0,1"
newline
hexmask.long.word 0x0 16.--28. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--15. 1. "Filter,Filter"
line.long 0x4 "GICP_FR1,GICP_FR1"
bitfld.long 0x4 30.--31. "FilterType,FilterType" "0,1,2,3"
bitfld.long 0x4 29. "FilterEncoding,FilterEncoding" "0,1"
newline
hexmask.long.word 0x4 16.--28. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x4 0.--15. 1. "Filter,Filter"
line.long 0x8 "GICP_FR2,GICP_FR2"
bitfld.long 0x8 30.--31. "FilterType,FilterType" "0,1,2,3"
bitfld.long 0x8 29. "FilterEncoding,FilterEncoding" "0,1"
newline
hexmask.long.word 0x8 16.--28. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x8 0.--15. 1. "Filter,Filter"
line.long 0xC "GICP_FR3,GICP_FR3"
bitfld.long 0xC 30.--31. "FilterType,FilterType" "0,1,2,3"
bitfld.long 0xC 29. "FilterEncoding,FilterEncoding" "0,1"
newline
hexmask.long.word 0xC 16.--28. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0xC 0.--15. 1. "Filter,Filter"
line.long 0x10 "GICP_FR4,GICP_FR4"
bitfld.long 0x10 30.--31. "FilterType,FilterType" "0,1,2,3"
bitfld.long 0x10 29. "FilterEncoding,FilterEncoding" "0,1"
newline
hexmask.long.word 0x10 16.--28. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x10 0.--15. 1. "Filter,Filter"
group.quad 0x30C00++0x7
line.quad 0x0 "GICP_CNTENSET0,GICP_CNTENSET0"
hexmask.quad 0x0 5.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 4. "CNTEN4,CNTEN4" "0,1"
newline
bitfld.quad 0x0 3. "CNTEN3,CNTEN3" "0,1"
bitfld.quad 0x0 2. "CNTEN2,CNTEN2" "0,1"
newline
bitfld.quad 0x0 1. "CNTEN1,CNTEN1" "0,1"
bitfld.quad 0x0 0. "CNTEN0,CNTEN0" "0,1"
group.quad 0x30C20++0x7
line.quad 0x0 "GICP_CNTENCLR0,GICP_CNTENCLR0"
hexmask.quad 0x0 5.--63. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 4. "CNTEN4,CNTEN4" "0,1"
newline
bitfld.quad 0x0 3. "CNTEN3,CNTEN3" "0,1"
bitfld.quad 0x0 2. "CNTEN2,CNTEN2" "0,1"
newline
bitfld.quad 0x0 1. "CNTEN1,CNTEN1" "0,1"
bitfld.quad 0x0 0. "CNTEN0,CNTEN0" "0,1"
group.quad 0x30C40++0x7
line.quad 0x0 "GICP_INTENSET0,GICP_INTENSET0"
hexmask.quad 0x0 5.--63. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x0 0.--4. 1. "INTEN,INTEN"
group.quad 0x30C60++0x7
line.quad 0x0 "GICP_INTENCLR0,GICP_INTENCLR0"
hexmask.quad 0x0 5.--63. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x0 0.--4. 1. "INTEN,INTEN"
group.quad 0x30C80++0x7
line.quad 0x0 "GICP_OVSCLR0,GICP_OVSCLR0"
hexmask.quad 0x0 5.--63. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x0 0.--4. 1. "OVS,OVS"
group.quad 0x30CC0++0x7
line.quad 0x0 "GICP_OVSSET0,GICP_OVSSET0"
hexmask.quad 0x0 5.--63. 1. "RESERVED0,RESERVED0"
hexmask.quad.byte 0x0 0.--4. 1. "OVS,OVS"
wgroup.long 0x30D88++0x3
line.long 0x0 "GICP_CAPR,GICP_CAPR"
hexmask.long 0x0 1.--31. 1. "RESERVED0,RESERVED0"
bitfld.long 0x0 0. "CAPTURE,CAPTURE" "0,1"
rgroup.long 0x30E00++0x3
line.long 0x0 "GICP_CFGR,GICP_CFGR"
hexmask.long.word 0x0 23.--31. 1. "RESERVED2,RESERVED2"
bitfld.long 0x0 22. "CAPTURE,CAPTURE" "0,1"
newline
hexmask.long.byte 0x0 14.--21. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x0 8.--13. 1. "SIZE,SIZE"
newline
bitfld.long 0x0 6.--7. "RESERVED0,RESERVED0" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "NCTR,NCTR"
group.long 0x30E04++0x3
line.long 0x0 "GICP_CR,GICP_CR"
hexmask.long 0x0 1.--31. 1. "RESERVED0,RESERVED0"
bitfld.long 0x0 0. "E,E" "0,1"
group.long 0x30E50++0x3
line.long 0x0 "GICP_IRQCR,GICP_IRQCR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "SPIID,SPIID"
rgroup.long 0x30FB8++0x7
line.long 0x0 "GICP_PMAUTHSTATUS,GICP_PMAUTHSTATUS"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED0,RESERVED0"
bitfld.long 0x0 7. "SNI,SNI" "0,1"
newline
bitfld.long 0x0 6. "SNE,SNE" "0,1"
bitfld.long 0x0 5. "SI,SI" "0,1"
newline
bitfld.long 0x0 4. "SE,SE" "0,1"
bitfld.long 0x0 3. "NSNI,NSNI" "0,1"
newline
bitfld.long 0x0 2. "NSNE,NSNE" "0,1"
bitfld.long 0x0 1. "NSI,NSI" "0,1"
newline
bitfld.long 0x0 0. "NSE,NSE" "0,1"
line.long 0x4 "GICP_PMDEVARCH,GICP_PMDEVARCH"
hexmask.long.word 0x4 21.--31. 1. "ARCHITECT,ARCHITECT"
bitfld.long 0x4 20. "PRESENT,PRESENT" "0,1"
newline
hexmask.long.byte 0x4 16.--19. 1. "REVISION,REVISION"
hexmask.long.word 0x4 0.--15. 1. "ARCHID,ARCHID"
rgroup.long 0x30FCC++0x33
line.long 0x0 "GICP_PMDEVTYPE,GICP_PMDEVTYPE"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x0 4.--7. 1. "SubType,SubType"
newline
hexmask.long.byte 0x0 0.--3. 1. "Class,Class"
line.long 0x4 "GICP_PIDR4,GICP_PIDR4"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x4 4.--7. 1. "SIZE,SIZE"
newline
hexmask.long.byte 0x4 0.--3. 1. "DES_2,DES_2"
line.long 0x8 "GICP_PIDR5,GICP_PIDR5"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x8 0.--7. 1. "RESERVED,RESERVED"
line.long 0xC "GICP_PIDR6,GICP_PIDR6"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RESERVED"
line.long 0x10 "GICP_PIDR7,GICP_PIDR7"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x10 0.--7. 1. "RESERVED,RESERVED"
line.long 0x14 "GICP_PIDR0,GICP_PIDR0"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x14 0.--7. 1. "PART_0,PART_0"
line.long 0x18 "GICP_PIDR1,GICP_PIDR1"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x18 4.--7. 1. "DES_0,DES_0"
newline
hexmask.long.byte 0x18 0.--3. 1. "PART_1,PART_1"
line.long 0x1C "GICP_PIDR2,GICP_PIDR2"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x1C 4.--7. 1. "REVISION,REVISION"
newline
bitfld.long 0x1C 3. "JEDEC,JEDEC" "0,1"
bitfld.long 0x1C 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7"
line.long 0x20 "GICP_PIDR3,GICP_PIDR3"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x20 4.--7. 1. "REVAND,REVAND"
newline
bitfld.long 0x20 3. "RESERVED1,RESERVED1" "0,1"
bitfld.long 0x20 0.--2. "CMOD,CMOD" "0,1,2,3,4,5,6,7"
line.long 0x24 "GICP_CIDR0,GICP_CIDR0"
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x24 0.--7. 1. "PRMBL_0,PRMBL_0"
line.long 0x28 "GICP_CIDR1,GICP_CIDR1"
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x28 4.--7. 1. "CLASS,CLASS"
newline
hexmask.long.byte 0x28 0.--3. 1. "PRMBL_1,PRMBL_1"
line.long 0x2C "GICP_CIDR2,GICP_CIDR2"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_2,PRMBL_2"
line.long 0x30 "GICP_CIDR3,GICP_CIDR3"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_3,PRMBL_3"
group.long 0x40000++0x3
line.long 0x0 "GITS0_CTLR,GITS0_CTLR"
rbitfld.long 0x0 31. "Quiescent,Quiescent" "0,1"
hexmask.long 0x0 1.--30. 1. "RESERVED0,RESERVED0"
newline
bitfld.long 0x0 0. "Enabled,Enabled" "0,1"
rgroup.long 0x40004++0x3
line.long 0x0 "GITS0_IIDR,GITS0_IIDR"
hexmask.long.byte 0x0 24.--31. 1. "ProductID,ProductID"
hexmask.long.byte 0x0 20.--23. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x0 16.--19. 1. "Variant,Variant"
hexmask.long.byte 0x0 12.--15. 1. "Revision,Revision"
newline
hexmask.long.word 0x0 0.--11. 1. "Implementer,Implementer"
rgroup.quad 0x40008++0x7
line.quad 0x0 "GITS0_TYPER,GITS0_TYPER"
hexmask.quad.long 0x0 37.--63. 1. "RESERVED1,RESERVED1"
bitfld.quad 0x0 36. "CIL,CIL" "0,1"
newline
hexmask.quad.byte 0x0 32.--35. 1. "CIDBits,CIDBits"
hexmask.quad.byte 0x0 24.--31. 1. "HCC,HCC"
newline
hexmask.quad.byte 0x0 20.--23. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 19. "PTA,PTA" "0,1"
newline
bitfld.quad 0x0 18. "SEIS,SEIS" "0,1"
hexmask.quad.byte 0x0 13.--17. 1. "DevBits,DevBits"
newline
hexmask.quad.byte 0x0 8.--12. 1. "IDBits,IDBits"
hexmask.quad.byte 0x0 4.--7. 1. "ITTEntrySize,ITTEntrySize"
newline
bitfld.quad 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.quad 0x0 2. "CCT,CCT" "0,1"
newline
bitfld.quad 0x0 1. "Virtual,Virtual" "0,1"
bitfld.quad 0x0 0. "Physical,Physical" "0,1"
group.long 0x40020++0x3
line.long 0x0 "GITS0_FCTLR,GITS0_FCTLR"
bitfld.long 0x0 31. "DCC,DCC" "0,1"
bitfld.long 0x0 30. "PWE,PWE" "0,1"
newline
hexmask.long.word 0x0 19.--29. 1. "RESERVED2,RESERVED2"
bitfld.long 0x0 18. "IEC,IEC" "0,1"
newline
bitfld.long 0x0 17. "IDC,IDC" "0,1"
bitfld.long 0x0 16. "ICC,ICC" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RESERVED1,RESERVED1"
bitfld.long 0x0 11. "DMA,DMA" "0,1"
newline
rbitfld.long 0x0 10. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x0 9. "QD,QD" "0,1"
newline
bitfld.long 0x0 8. "AEE,AEE" "0,1"
hexmask.long.byte 0x0 4.--7. 1. "CGO,CGO"
newline
bitfld.long 0x0 3. "CEE,CEE" "0,1"
bitfld.long 0x0 2. "UEE,UEE" "0,1"
newline
bitfld.long 0x0 1. "LTE,LTE" "0,1"
bitfld.long 0x0 0. "SIP,SIP" "0,1"
group.quad 0x40028++0x7
line.quad 0x0 "GITS0_OPR,GITS0_OPR"
hexmask.quad.byte 0x0 60.--63. 1. "LOCK_TYPE,LOCK_TYPE"
hexmask.quad.byte 0x0 52.--59. 1. "RESERVED1,RESERVED1"
newline
hexmask.quad.tbyte 0x0 32.--51. 1. "DEVICE_ID,DEVICE_ID"
hexmask.quad.word 0x0 16.--31. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.word 0x0 0.--15. 1. "EVENT_ID,EVENT_ID"
rgroup.quad 0x40030++0x7
line.quad 0x0 "GITS0_OPSR,GITS0_OPSR"
bitfld.quad 0x0 63. "REQUEST_COMPLETE,REQUEST_COMPLETE" "0,1"
bitfld.quad 0x0 62. "REQUEST_PASS,REQUEST_PASS" "0,1"
newline
bitfld.quad 0x0 61. "REQUEST_IN_PROGRESS,REQUEST_IN_PROGRESS" "0,1"
hexmask.quad.word 0x0 49.--60. 1. "RESERVED2,RESERVED2"
newline
bitfld.quad 0x0 48. "ENTRY_LOCKED,ENTRY_LOCKED" "0,1"
bitfld.quad 0x0 45.--47. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.word 0x0 32.--44. 1. "TARGET,TARGET"
hexmask.quad.word 0x0 16.--31. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.word 0x0 0.--15. 1. "PID,PID"
group.quad 0x40080++0xF
line.quad 0x0 "GITS0_CBASER,GITS0_CBASER"
bitfld.quad 0x0 63. "Valid,Valid" "0,1"
bitfld.quad 0x0 62. "RESERVED3,RESERVED3" "0,1"
newline
bitfld.quad 0x0 59.--61. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 56.--58. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 53.--55. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
hexmask.quad.tbyte 0x0 32.--52. 1. "RESERVED2,RESERVED2"
newline
hexmask.quad.tbyte 0x0 12.--31. 1. "PhysicalAddress,PhysicalAddress"
bitfld.quad 0x0 10.--11. "Shareablity,Shareablity" "0,1,2,3"
newline
bitfld.quad 0x0 8.--9. "RESERVED0,RESERVED0" "0,1,2,3"
hexmask.quad.byte 0x0 0.--7. 1. "Size,Size"
line.quad 0x8 "GITS0_CWRITER,GITS0_CWRITER"
hexmask.quad 0x8 20.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.word 0x8 5.--19. 1. "Offset,Offset"
newline
hexmask.quad.byte 0x8 1.--4. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x8 0. "Retry,Retry" "0,1"
rgroup.quad 0x40090++0x7
line.quad 0x0 "GITS0_CREADR,GITS0_CREADR"
hexmask.quad 0x0 20.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.word 0x0 5.--19. 1. "Offset,Offset"
newline
hexmask.quad.byte 0x0 1.--4. 1. "RESERVED0,RESERVED0"
bitfld.quad 0x0 0. "Stalled,Stalled" "0,1"
group.quad 0x40100++0xF
line.quad 0x0 "GITS0_BASER0,GITS0_BASER0"
bitfld.quad 0x0 63. "Valid,Valid" "0,1"
bitfld.quad 0x0 62. "Indirect,Indirect" "0,1"
newline
bitfld.quad 0x0 59.--61. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
bitfld.quad 0x0 56.--58. "Type,Type" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 53.--55. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
hexmask.quad.byte 0x0 48.--52. 1. "EntrySize,EntrySize"
newline
hexmask.quad.word 0x0 32.--47. 1. "RESERVED0,RESERVED0"
hexmask.quad.tbyte 0x0 12.--31. 1. "PhysicalAddress,PhysicalAddress"
newline
bitfld.quad 0x0 10.--11. "Shareability,Shareability" "0,1,2,3"
bitfld.quad 0x0 8.--9. "PageSize,PageSize" "0,1,2,3"
newline
hexmask.quad.byte 0x0 0.--7. 1. "Size,Size"
line.quad 0x8 "GITS0_BASER1,GITS0_BASER1"
bitfld.quad 0x8 63. "Valid,Valid" "0,1"
bitfld.quad 0x8 62. "Indirect,Indirect" "0,1"
newline
bitfld.quad 0x8 59.--61. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
bitfld.quad 0x8 56.--58. "Type,Type" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x8 53.--55. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
hexmask.quad.byte 0x8 48.--52. 1. "EntrySize,EntrySize"
newline
hexmask.quad.word 0x8 32.--47. 1. "RESERVED0,RESERVED0"
hexmask.quad.tbyte 0x8 12.--31. 1. "PhysicalAddress,PhysicalAddress"
newline
bitfld.quad 0x8 10.--11. "Shareability,Shareability" "0,1,2,3"
bitfld.quad 0x8 8.--9. "PageSize,PageSize" "0,1,2,3"
newline
hexmask.quad.byte 0x8 0.--7. 1. "Size,Size"
rgroup.long 0x4F000++0x3
line.long 0x0 "GITS0_CFGID,GITS0_CFGID"
hexmask.long.byte 0x0 28.--31. 1. "Event_Cache_Index_Bits,Event_Cache_Index_Bits"
hexmask.long.byte 0x0 24.--27. 1. "Device_Cache_Index_Bits,Device_Cache_Index_Bits"
newline
hexmask.long.byte 0x0 20.--23. 1. "Collection_Cache_Index_Bits,Collection_Cache_Index_Bits"
bitfld.long 0x0 19. "RESERVED0,RESERVED0" "0,1"
newline
bitfld.long 0x0 18. "Cache_ECC,Cache_ECC" "0,1"
bitfld.long 0x0 17. "Low_Latency_Support,Low_Latency_Support" "0,1"
newline
bitfld.long 0x0 16. "MSI_64,MSI_64" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "Target_Bits,Target_Bits"
newline
hexmask.long.byte 0x0 8.--11. 1. "LPI_Credit_Count,LPI_Credit_Count"
hexmask.long.byte 0x0 0.--7. 1. "ITS_NUMBER,ITS_NUMBER"
rgroup.long 0x4FFD0++0x2F
line.long 0x0 "GITS0_PIDR4,GITS0_PIDR4"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x0 4.--7. 1. "SIZE,SIZE"
newline
hexmask.long.byte 0x0 0.--3. 1. "DES_2,DES_2"
line.long 0x4 "GITS0_PIDR5,GITS0_PIDR5"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x4 0.--7. 1. "RESERVED,RESERVED"
line.long 0x8 "GITS0_PIDR6,GITS0_PIDR6"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x8 0.--7. 1. "RESERVED,RESERVED"
line.long 0xC "GITS0_PIDR7,GITS0_PIDR7"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RESERVED"
line.long 0x10 "GITS0_PIDR0,GITS0_PIDR0"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x10 0.--7. 1. "PART_0,PART_0"
line.long 0x14 "GITS0_PIDR1,GITS0_PIDR1"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x14 4.--7. 1. "DES_0,DES_0"
newline
hexmask.long.byte 0x14 0.--3. 1. "PART_1,PART_1"
line.long 0x18 "GITS0_PIDR2,GITS0_PIDR2"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x18 4.--7. 1. "REVISION,REVISION"
newline
bitfld.long 0x18 3. "JEDEC,JEDEC" "0,1"
bitfld.long 0x18 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7"
line.long 0x1C "GITS0_PIDR3,GITS0_PIDR3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,REVAND"
newline
bitfld.long 0x1C 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x1C 0.--2. "CMOD,CMOD" "0,1,2,3,4,5,6,7"
line.long 0x20 "GITS0_CIDR0,GITS0_CIDR0"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,PRMBL_0"
line.long 0x24 "GITS0_CIDR1,GITS0_CIDR1"
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS"
newline
hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,PRMBL_1"
line.long 0x28 "GITS0_CIDR2,GITS0_CIDR2"
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,PRMBL_2"
line.long 0x2C "GITS0_CIDR3,GITS0_CIDR3"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,PRMBL_3"
wgroup.long 0x50040++0x3
line.long 0x0 "GITS0_TRANSLATER,GITS0_TRANSLATER"
hexmask.long 0x0 0.--31. 1. "InterruptID,InterruptID"
group.long 0x60000++0x3
line.long 0x0 "GICR0_CTLR,GICR0_CTLR"
rbitfld.long 0x0 31. "UWP,UWP" "0,1"
hexmask.long.byte 0x0 27.--30. 1. "RESERVED2,RESERVED2"
newline
bitfld.long 0x0 26. "DPG1S,DPG1S" "0,1"
bitfld.long 0x0 25. "DPG1NS,DPG1NS" "0,1"
newline
bitfld.long 0x0 24. "DPG0,DPG0" "0,1"
hexmask.long.tbyte 0x0 4.--23. 1. "RESERVED1,RESERVED1"
newline
rbitfld.long 0x0 3. "RWP,RWP" "0,1"
bitfld.long 0x0 1.--2. "RESERVED0,RESERVED0" "0,1,2,3"
newline
bitfld.long 0x0 0. "EnableLPIs,EnableLPIs" "0,1"
rgroup.long 0x60004++0x3
line.long 0x0 "GICR0_IIDR,GICR0_IIDR"
hexmask.long.byte 0x0 24.--31. 1. "ProductID,ProductID"
hexmask.long.byte 0x0 20.--23. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x0 16.--19. 1. "Variant,Variant"
hexmask.long.byte 0x0 12.--15. 1. "Revision,Revision"
newline
hexmask.long.word 0x0 0.--11. 1. "Implementer,Implementer"
rgroup.quad 0x60008++0x7
line.quad 0x0 "GICR0_TYPER,GICR0_TYPER"
hexmask.quad.long 0x0 32.--63. 1. "AffinityValue,AffinityValue"
hexmask.quad.byte 0x0 26.--31. 1. "RESERVED2,RESERVED2"
newline
bitfld.quad 0x0 24.--25. "CommonLPIAff,CommonLPIAff" "0,1,2,3"
hexmask.quad.word 0x0 8.--23. 1. "ProcessorNumber,ProcessorNumber"
newline
bitfld.quad 0x0 6.--7. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x0 5. "DPGS,DPGS" "0,1"
newline
bitfld.quad 0x0 4. "Last,Last" "0,1"
bitfld.quad 0x0 3. "DirectLPI,DirectLPI" "0,1"
newline
bitfld.quad 0x0 2. "RESERVED0,RESERVED0" "0,1"
bitfld.quad 0x0 1. "VLPIS,VLPIS" "0,1"
newline
bitfld.quad 0x0 0. "PLPIS,PLPIS" "0,1"
group.long 0x60014++0x3
line.long 0x0 "GICR0_WAKER,GICR0_WAKER"
rbitfld.long 0x0 31. "Quiescent,Quiescent" "0,1"
hexmask.long 0x0 3.--30. 1. "RESERVED0,RESERVED0"
newline
rbitfld.long 0x0 2. "ChildrenAsleep,ChildrenAsleep" "0,1"
bitfld.long 0x0 1. "ProcessorSleep,ProcessorSleep" "0,1"
newline
bitfld.long 0x0 0. "Sleep,Sleep" "0,1"
group.long 0x60020++0xB
line.long 0x0 "GICR0_FCTLR,GICR0_FCTLR"
bitfld.long 0x0 31. "QD,QD" "0,1"
hexmask.long.tbyte 0x0 7.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0x0 4.--6. "CGO,CGO" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 1.--3. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "SIP,SIP" "0,1"
line.long 0x4 "GICR0_PWRR,GICR0_PWRR"
hexmask.long.byte 0x4 24.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.word 0x4 15.--23. 1. "RDG,RDG"
newline
hexmask.long.byte 0x4 8.--14. 1. "RDGO,RDGO"
hexmask.long.byte 0x4 4.--7. 1. "RESERVED0,RESERVED0"
newline
rbitfld.long 0x4 3. "RDGPO,RDGPO" "0,1"
bitfld.long 0x4 2. "RDGPD,RDGPD" "0,1"
newline
bitfld.long 0x4 1. "RDAG,RDAG" "0,1"
bitfld.long 0x4 0. "RDPD,RDPD" "0,1"
line.long 0x8 "GICR0_CLASS,GICR0_CLASS"
hexmask.long 0x8 1.--31. 1. "RESERVED0,RESERVED0"
bitfld.long 0x8 0. "Class,Class" "0,1"
group.quad 0x60070++0xF
line.quad 0x0 "GICR0_PROPBASER,GICR0_PROPBASER"
hexmask.quad.byte 0x0 59.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 56.--58. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.tbyte 0x0 32.--55. 1. "RESERVED1,RESERVED1"
hexmask.quad.tbyte 0x0 12.--31. 1. "PhysicalAddress,PhysicalAddress"
newline
bitfld.quad 0x0 10.--11. "Shareability,Shareability" "0,1,2,3"
bitfld.quad 0x0 7.--9. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 5.--6. "RESERVED0,RESERVED0" "0,1,2,3"
hexmask.quad.byte 0x0 0.--4. 1. "IDBits,IDBits"
line.quad 0x8 "GICR0_PENDBASER,GICR0_PENDBASER"
bitfld.quad 0x8 63. "RESERVED4,RESERVED4" "0,1"
bitfld.quad 0x8 62. "PendingTableZero,PendingTableZero" "0,1"
newline
bitfld.quad 0x8 59.--61. "RESERVED3,RESERVED3" "0,1,2,3,4,5,6,7"
bitfld.quad 0x8 56.--58. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.tbyte 0x8 32.--55. 1. "RESERVED2,RESERVED2"
hexmask.quad.word 0x8 16.--31. 1. "PhysicalAddress,PhysicalAddress"
newline
hexmask.quad.byte 0x8 12.--15. 1. "RESERVED1,RESERVED1"
bitfld.quad 0x8 10.--11. "Shareability,Shareability" "0,1,2,3"
newline
bitfld.quad 0x8 7.--9. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
hexmask.quad.byte 0x8 0.--6. 1. "RESERVED0,RESERVED0"
rgroup.long 0x6FFD0++0x2F
line.long 0x0 "GICR0_PIDR4,GICR0_PIDR4"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x0 4.--7. 1. "SIZE,SIZE"
newline
hexmask.long.byte 0x0 0.--3. 1. "DES_2,DES_2"
line.long 0x4 "GICR0_PIDR5,GICR0_PIDR5"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x4 0.--7. 1. "RESERVED,RESERVED"
line.long 0x8 "GICR0_PIDR6,GICR0_PIDR6"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x8 0.--7. 1. "RESERVED,RESERVED"
line.long 0xC "GICR0_PIDR7,GICR0_PIDR7"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RESERVED"
line.long 0x10 "GICR0_PIDR0,GICR0_PIDR0"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x10 0.--7. 1. "PART_0,PART_0"
line.long 0x14 "GICR0_PIDR1,GICR0_PIDR1"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x14 4.--7. 1. "DES_0,DES_0"
newline
hexmask.long.byte 0x14 0.--3. 1. "PART_1,PART_1"
line.long 0x18 "GICR0_PIDR2,GICR0_PIDR2"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x18 4.--7. 1. "REVISION,REVISION"
newline
bitfld.long 0x18 3. "JEDEC,JEDEC" "0,1"
bitfld.long 0x18 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7"
line.long 0x1C "GICR0_PIDR3,GICR0_PIDR3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,REVAND"
newline
bitfld.long 0x1C 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x1C 0.--2. "CMOD,CMOD" "0,1,2,3,4,5,6,7"
line.long 0x20 "GICR0_CIDR0,GICR0_CIDR0"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,PRMBL_0"
line.long 0x24 "GICR0_CIDR1,GICR0_CIDR1"
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS"
newline
hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,PRMBL_1"
line.long 0x28 "GICR0_CIDR2,GICR0_CIDR2"
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,PRMBL_2"
line.long 0x2C "GICR0_CIDR3,GICR0_CIDR3"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,PRMBL_3"
group.long 0x70080++0x3
line.long 0x0 "GICR0_IGROUPR0,GICR0_IGROUPR0"
bitfld.long 0x0 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x0 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x0 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x0 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x0 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x0 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x0 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x0 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x0 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x0 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x0 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x0 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x0 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x0 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x0 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x0 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x0 0. "group_status_bit0,group_status_bit0" "0,1"
group.long 0x70100++0x3
line.long 0x0 "GICR0_ISENABLER0,GICR0_ISENABLER0"
bitfld.long 0x0 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x0 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x0 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x0 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x0 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x0 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x0 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x0 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x0 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x0 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x0 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x0 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x0 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x0 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x0 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x0 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x0 0. "set_enable_bit0,set_enable_bit0" "0,1"
group.long 0x70180++0x3
line.long 0x0 "GICR0_ICENABLER0,GICR0_ICENABLER0"
bitfld.long 0x0 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x0 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x0 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x0 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x0 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x0 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x0 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x0 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x0 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x0 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x0 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x0 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x0 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x0 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x0 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x0 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x0 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
group.long 0x70200++0x3
line.long 0x0 "GICR0_ISPENDR0,GICR0_ISPENDR0"
bitfld.long 0x0 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x0 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x0 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x0 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x0 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x0 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x0 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x0 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x0 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x0 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x0 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x0 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x0 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x0 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x0 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x0 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x0 0. "set_pending_bit0,set_pending_bit0" "0,1"
group.long 0x70280++0x3
line.long 0x0 "GICR0_ICPENDR0,GICR0_ICPENDR0"
bitfld.long 0x0 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x0 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x0 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x0 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x0 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x0 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x0 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x0 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x0 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x0 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x0 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x0 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x0 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x0 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x0 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x0 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x0 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
group.long 0x70300++0x3
line.long 0x0 "GICR0_ISACTIVER0,GICR0_ISACTIVER0"
bitfld.long 0x0 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x0 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x0 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x0 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x0 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x0 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x0 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x0 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x0 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x0 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x0 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x0 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x0 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x0 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x0 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x0 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x0 0. "set_active_bit0,set_active_bit0" "0,1"
group.long 0x70380++0x3
line.long 0x0 "GICR0_ICACTIVER0,GICR0_ICACTIVER0"
bitfld.long 0x0 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x0 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x0 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x0 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x0 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x0 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x0 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x0 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x0 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x0 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x0 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x0 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x0 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x0 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x0 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x0 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x0 0. "clear_active_bit0,clear_active_bit0" "0,1"
group.long 0x70400++0x1F
line.long 0x0 "GICR0_IPRIORITYR0,GICR0_IPRIORITYR0"
hexmask.long.byte 0x0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x0 0.--7. 1. "offset0,offset0"
line.long 0x4 "GICR0_IPRIORITYR1,GICR0_IPRIORITYR1"
hexmask.long.byte 0x4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x4 0.--7. 1. "offset0,offset0"
line.long 0x8 "GICR0_IPRIORITYR2,GICR0_IPRIORITYR2"
hexmask.long.byte 0x8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x8 0.--7. 1. "offset0,offset0"
line.long 0xC "GICR0_IPRIORITYR3,GICR0_IPRIORITYR3"
hexmask.long.byte 0xC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC 0.--7. 1. "offset0,offset0"
line.long 0x10 "GICR0_IPRIORITYR4,GICR0_IPRIORITYR4"
hexmask.long.byte 0x10 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x10 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x10 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x10 0.--7. 1. "offset0,offset0"
line.long 0x14 "GICR0_IPRIORITYR5,GICR0_IPRIORITYR5"
hexmask.long.byte 0x14 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x14 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x14 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x14 0.--7. 1. "offset0,offset0"
line.long 0x18 "GICR0_IPRIORITYR6,GICR0_IPRIORITYR6"
hexmask.long.byte 0x18 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x18 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x18 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x18 0.--7. 1. "offset0,offset0"
line.long 0x1C "GICR0_IPRIORITYR7,GICR0_IPRIORITYR7"
hexmask.long.byte 0x1C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C 0.--7. 1. "offset0,offset0"
rgroup.long 0x70C00++0x3
line.long 0x0 "GICR0_ICFGR0,GICR0_ICFGR0"
bitfld.long 0x0 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x0 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x0 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x0 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x0 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x0 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x0 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x0 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x0 0.--1. "int_config0,int_config0" "0,1,2,3"
group.long 0x70C04++0x3
line.long 0x0 "GICR0_ICFGR1,GICR0_ICFGR1"
bitfld.long 0x0 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x0 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x0 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x0 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x0 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x0 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x0 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x0 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x0 0.--1. "int_config0,int_config0" "0,1,2,3"
group.long 0x70D00++0x3
line.long 0x0 "GICR0_IGRPMODR0,GICR0_IGRPMODR0"
bitfld.long 0x0 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x0 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x0 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x0 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x0 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x0 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x0 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x0 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x0 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x0 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x0 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x0 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x0 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x0 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x0 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x0 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x0 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
group.long 0x70E00++0x3
line.long 0x0 "GICR0_NSACR,GICR0_NSACR"
bitfld.long 0x0 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x0 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x0 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x0 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x0 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x0 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x0 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x0 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x0 0.--1. "ns_access0,ns_access0" "0,1,2,3"
rgroup.long 0x7C000++0x3
line.long 0x0 "GICR0_MISCSTATUSR,GICR0_MISCSTATUSR"
bitfld.long 0x0 31. "cpu_active,cpu_active" "0,1"
bitfld.long 0x0 30. "wake_request,wake_request" "0,1"
newline
hexmask.long 0x0 5.--29. 1. "RESERVED1,RESERVED1"
bitfld.long 0x0 4. "access_type,access_type" "0,1"
newline
bitfld.long 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x0 2. "EnableGrp1_s,EnableGrp1_s" "0,1"
newline
bitfld.long 0x0 1. "EnableGrp1_ns,EnableGrp1_ns" "0,1"
bitfld.long 0x0 0. "EnableGrp0,EnableGrp0" "0,1"
rgroup.long 0x7C008++0x3
line.long 0x0 "GICR0_IERRVR,GICR0_IERRVR"
bitfld.long 0x0 31. "valid_bit31,valid_bit31" "0,1"
bitfld.long 0x0 30. "valid_bit30,valid_bit30" "0,1"
newline
bitfld.long 0x0 29. "valid_bit29,valid_bit29" "0,1"
bitfld.long 0x0 28. "valid_bit28,valid_bit28" "0,1"
newline
bitfld.long 0x0 27. "valid_bit27,valid_bit27" "0,1"
bitfld.long 0x0 26. "valid_bit26,valid_bit26" "0,1"
newline
bitfld.long 0x0 25. "valid_bit25,valid_bit25" "0,1"
bitfld.long 0x0 24. "valid_bit24,valid_bit24" "0,1"
newline
bitfld.long 0x0 23. "valid_bit23,valid_bit23" "0,1"
bitfld.long 0x0 22. "valid_bit22,valid_bit22" "0,1"
newline
bitfld.long 0x0 21. "valid_bit21,valid_bit21" "0,1"
bitfld.long 0x0 20. "valid_bit20,valid_bit20" "0,1"
newline
bitfld.long 0x0 19. "valid_bit19,valid_bit19" "0,1"
bitfld.long 0x0 18. "valid_bit18,valid_bit18" "0,1"
newline
bitfld.long 0x0 17. "valid_bit17,valid_bit17" "0,1"
bitfld.long 0x0 16. "valid_bit16,valid_bit16" "0,1"
newline
bitfld.long 0x0 15. "valid_bit15,valid_bit15" "0,1"
bitfld.long 0x0 14. "valid_bit14,valid_bit14" "0,1"
newline
bitfld.long 0x0 13. "valid_bit13,valid_bit13" "0,1"
bitfld.long 0x0 12. "valid_bit12,valid_bit12" "0,1"
newline
bitfld.long 0x0 11. "valid_bit11,valid_bit11" "0,1"
bitfld.long 0x0 10. "valid_bit10,valid_bit10" "0,1"
newline
bitfld.long 0x0 9. "valid_bit9,valid_bit9" "0,1"
bitfld.long 0x0 8. "valid_bit8,valid_bit8" "0,1"
newline
bitfld.long 0x0 7. "valid_bit7,valid_bit7" "0,1"
bitfld.long 0x0 6. "valid_bit6,valid_bit6" "0,1"
newline
bitfld.long 0x0 5. "valid_bit5,valid_bit5" "0,1"
bitfld.long 0x0 4. "valid_bit4,valid_bit4" "0,1"
newline
bitfld.long 0x0 3. "valid_bit3,valid_bit3" "0,1"
bitfld.long 0x0 2. "valid_bit2,valid_bit2" "0,1"
newline
bitfld.long 0x0 1. "valid_bit1,valid_bit1" "0,1"
bitfld.long 0x0 0. "valid_bit0,valid_bit0" "0,1"
group.quad 0x7C010++0x7
line.quad 0x0 "GICR0_SGIDR,GICR0_SGIDR"
bitfld.quad 0x0 63. "RESERVED16,RESERVED16" "0,1"
bitfld.quad 0x0 62. "grpmod15,grpmod15" "0,1"
newline
bitfld.quad 0x0 61. "grp15,grp15" "0,1"
bitfld.quad 0x0 60. "nsacr15,nsacr15" "0,1"
newline
bitfld.quad 0x0 59. "RESERVED15,RESERVED15" "0,1"
bitfld.quad 0x0 58. "grpmod14,grpmod14" "0,1"
newline
bitfld.quad 0x0 57. "grp14,grp14" "0,1"
bitfld.quad 0x0 56. "nsacr14,nsacr14" "0,1"
newline
bitfld.quad 0x0 55. "RESERVED13,RESERVED13" "0,1"
bitfld.quad 0x0 54. "grpmod13,grpmod13" "0,1"
newline
bitfld.quad 0x0 53. "grp13,grp13" "0,1"
bitfld.quad 0x0 52. "nsacr13,nsacr13" "0,1"
newline
bitfld.quad 0x0 51. "RESERVED12,RESERVED12" "0,1"
bitfld.quad 0x0 50. "grpmod12,grpmod12" "0,1"
newline
bitfld.quad 0x0 49. "grp12,grp12" "0,1"
bitfld.quad 0x0 48. "nsacr12,nsacr12" "0,1"
newline
bitfld.quad 0x0 47. "RESERVED11,RESERVED11" "0,1"
bitfld.quad 0x0 46. "grpmod11,grpmod11" "0,1"
newline
bitfld.quad 0x0 45. "grp11,grp11" "0,1"
bitfld.quad 0x0 44. "nsacr11,nsacr11" "0,1"
newline
bitfld.quad 0x0 43. "RESERVED10,RESERVED10" "0,1"
bitfld.quad 0x0 42. "grpmod10,grpmod10" "0,1"
newline
bitfld.quad 0x0 41. "grp10,grp10" "0,1"
bitfld.quad 0x0 40. "nsacr10,nsacr10" "0,1"
newline
bitfld.quad 0x0 39. "RESERVED9,RESERVED9" "0,1"
bitfld.quad 0x0 38. "grpmod9,grpmod9" "0,1"
newline
bitfld.quad 0x0 37. "grp9,grp9" "0,1"
bitfld.quad 0x0 36. "nsacr9,nsacr9" "0,1"
newline
bitfld.quad 0x0 35. "RESERVED8,RESERVED8" "0,1"
bitfld.quad 0x0 34. "grpmod8,grpmod8" "0,1"
newline
bitfld.quad 0x0 33. "grp8,grp8" "0,1"
bitfld.quad 0x0 32. "nsacr8,nsacr8" "0,1"
newline
bitfld.quad 0x0 31. "RESERVED7,RESERVED7" "0,1"
bitfld.quad 0x0 30. "grpmod7,grpmod7" "0,1"
newline
bitfld.quad 0x0 29. "grp7,grp7" "0,1"
bitfld.quad 0x0 28. "nsacr7,nsacr7" "0,1"
newline
bitfld.quad 0x0 27. "RESERVED6,RESERVED6" "0,1"
bitfld.quad 0x0 26. "grpmod6,grpmod6" "0,1"
newline
bitfld.quad 0x0 25. "grp6,grp6" "0,1"
bitfld.quad 0x0 24. "nsacr6,nsacr6" "0,1"
newline
bitfld.quad 0x0 23. "RESERVED5,RESERVED5" "0,1"
bitfld.quad 0x0 22. "grpmod5,grpmod5" "0,1"
newline
bitfld.quad 0x0 21. "grp5,grp5" "0,1"
bitfld.quad 0x0 20. "nsacr5,nsacr5" "0,1"
newline
bitfld.quad 0x0 19. "RESERVED4,RESERVED4" "0,1"
bitfld.quad 0x0 18. "grpmod4,grpmod4" "0,1"
newline
bitfld.quad 0x0 17. "grp4,grp4" "0,1"
bitfld.quad 0x0 16. "nsacr4,nsacr4" "0,1"
newline
bitfld.quad 0x0 15. "RESERVED3,RESERVED3" "0,1"
bitfld.quad 0x0 14. "grpmod3,grpmod3" "0,1"
newline
bitfld.quad 0x0 13. "grp3,grp3" "0,1"
bitfld.quad 0x0 12. "nsacr3,nsacr3" "0,1"
newline
bitfld.quad 0x0 11. "RESERVED2,RESERVED2" "0,1"
bitfld.quad 0x0 10. "grpmod2,grpmod2" "0,1"
newline
bitfld.quad 0x0 9. "grp2,grp2" "0,1"
bitfld.quad 0x0 8. "nsacr2,nsacr2" "0,1"
newline
bitfld.quad 0x0 7. "RESERVED1,RESERVED1" "0,1"
bitfld.quad 0x0 6. "grpmod1,grpmod1" "0,1"
newline
bitfld.quad 0x0 5. "grp1,grp1" "0,1"
bitfld.quad 0x0 4. "nsacr1,nsacr1" "0,1"
newline
bitfld.quad 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.quad 0x0 2. "grpmod0,grpmod0" "0,1"
newline
bitfld.quad 0x0 1. "grp0,grp0" "0,1"
bitfld.quad 0x0 0. "nsacr0,nsacr0" "0,1"
rgroup.long 0x7F000++0x7
line.long 0x0 "GICR0_CFGID0,GICR0_CFGID0"
hexmask.long.byte 0x0 28.--31. 1. "Af3width,Af3width"
hexmask.long.byte 0x0 24.--27. 1. "Af2width,Af2width"
newline
hexmask.long.byte 0x0 20.--23. 1. "Af1width,Af1width"
hexmask.long.byte 0x0 16.--19. 1. "Af0width,Af0width"
newline
hexmask.long.byte 0x0 12.--15. 1. "TargetlistWidth,TargetlistWidth"
bitfld.long 0x0 11. "ECCSupport,ECCSupport" "0,1"
newline
bitfld.long 0x0 9.--10. "RESERVED0,RESERVED0" "0,1,2,3"
hexmask.long.word 0x0 0.--8. 1. "PPINumber,PPINumber"
line.long 0x4 "GICR0_CFGID1,GICR0_CFGID1"
hexmask.long.byte 0x4 28.--31. 1. "Version,Version"
hexmask.long.byte 0x4 24.--27. 1. "REVAND,REVAND"
newline
hexmask.long.byte 0x4 20.--23. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x4 16.--19. 1. "PPIsPerProcessor,PPIsPerProcessor"
newline
bitfld.long 0x4 13.--15. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "DirectUpstream,DirectUpstream" "0,1"
newline
hexmask.long.byte 0x4 4.--11. 1. "NumCPUs,NumCPUs"
hexmask.long.byte 0x4 0.--3. 1. "NumARE0CPUs,NumARE0CPUs"
group.long 0x80000++0x3
line.long 0x0 "GICR1_CTLR,GICR1_CTLR"
rbitfld.long 0x0 31. "UWP,UWP" "0,1"
hexmask.long.byte 0x0 27.--30. 1. "RESERVED2,RESERVED2"
newline
bitfld.long 0x0 26. "DPG1S,DPG1S" "0,1"
bitfld.long 0x0 25. "DPG1NS,DPG1NS" "0,1"
newline
bitfld.long 0x0 24. "DPG0,DPG0" "0,1"
hexmask.long.tbyte 0x0 4.--23. 1. "RESERVED1,RESERVED1"
newline
rbitfld.long 0x0 3. "RWP,RWP" "0,1"
bitfld.long 0x0 1.--2. "RESERVED0,RESERVED0" "0,1,2,3"
newline
bitfld.long 0x0 0. "EnableLPIs,EnableLPIs" "0,1"
rgroup.long 0x80004++0x3
line.long 0x0 "GICR1_IIDR,GICR1_IIDR"
hexmask.long.byte 0x0 24.--31. 1. "ProductID,ProductID"
hexmask.long.byte 0x0 20.--23. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x0 16.--19. 1. "Variant,Variant"
hexmask.long.byte 0x0 12.--15. 1. "Revision,Revision"
newline
hexmask.long.word 0x0 0.--11. 1. "Implementer,Implementer"
rgroup.quad 0x80008++0x7
line.quad 0x0 "GICR1_TYPER,GICR1_TYPER"
hexmask.quad.long 0x0 32.--63. 1. "AffinityValue,AffinityValue"
hexmask.quad.byte 0x0 26.--31. 1. "RESERVED2,RESERVED2"
newline
bitfld.quad 0x0 24.--25. "CommonLPIAff,CommonLPIAff" "0,1,2,3"
hexmask.quad.word 0x0 8.--23. 1. "ProcessorNumber,ProcessorNumber"
newline
bitfld.quad 0x0 6.--7. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x0 5. "DPGS,DPGS" "0,1"
newline
bitfld.quad 0x0 4. "Last,Last" "0,1"
bitfld.quad 0x0 3. "DirectLPI,DirectLPI" "0,1"
newline
bitfld.quad 0x0 2. "RESERVED0,RESERVED0" "0,1"
bitfld.quad 0x0 1. "VLPIS,VLPIS" "0,1"
newline
bitfld.quad 0x0 0. "PLPIS,PLPIS" "0,1"
group.long 0x80014++0x3
line.long 0x0 "GICR1_WAKER,GICR1_WAKER"
rbitfld.long 0x0 31. "Quiescent,Quiescent" "0,1"
hexmask.long 0x0 3.--30. 1. "RESERVED0,RESERVED0"
newline
rbitfld.long 0x0 2. "ChildrenAsleep,ChildrenAsleep" "0,1"
bitfld.long 0x0 1. "ProcessorSleep,ProcessorSleep" "0,1"
newline
bitfld.long 0x0 0. "Sleep,Sleep" "0,1"
group.long 0x80020++0xB
line.long 0x0 "GICR1_FCTLR,GICR1_FCTLR"
bitfld.long 0x0 31. "QD,QD" "0,1"
hexmask.long.tbyte 0x0 7.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0x0 4.--6. "CGO,CGO" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 1.--3. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "SIP,SIP" "0,1"
line.long 0x4 "GICR1_PWRR,GICR1_PWRR"
hexmask.long.byte 0x4 24.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.word 0x4 15.--23. 1. "RDG,RDG"
newline
hexmask.long.byte 0x4 8.--14. 1. "RDGO,RDGO"
hexmask.long.byte 0x4 4.--7. 1. "RESERVED0,RESERVED0"
newline
rbitfld.long 0x4 3. "RDGPO,RDGPO" "0,1"
bitfld.long 0x4 2. "RDGPD,RDGPD" "0,1"
newline
bitfld.long 0x4 1. "RDAG,RDAG" "0,1"
bitfld.long 0x4 0. "RDPD,RDPD" "0,1"
line.long 0x8 "GICR1_CLASS,GICR1_CLASS"
hexmask.long 0x8 1.--31. 1. "RESERVED0,RESERVED0"
bitfld.long 0x8 0. "Class,Class" "0,1"
group.quad 0x80070++0xF
line.quad 0x0 "GICR1_PROPBASER,GICR1_PROPBASER"
hexmask.quad.byte 0x0 59.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 56.--58. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.tbyte 0x0 32.--55. 1. "RESERVED1,RESERVED1"
hexmask.quad.tbyte 0x0 12.--31. 1. "PhysicalAddress,PhysicalAddress"
newline
bitfld.quad 0x0 10.--11. "Shareability,Shareability" "0,1,2,3"
bitfld.quad 0x0 7.--9. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 5.--6. "RESERVED0,RESERVED0" "0,1,2,3"
hexmask.quad.byte 0x0 0.--4. 1. "IDBits,IDBits"
line.quad 0x8 "GICR1_PENDBASER,GICR1_PENDBASER"
bitfld.quad 0x8 63. "RESERVED4,RESERVED4" "0,1"
bitfld.quad 0x8 62. "PendingTableZero,PendingTableZero" "0,1"
newline
bitfld.quad 0x8 59.--61. "RESERVED3,RESERVED3" "0,1,2,3,4,5,6,7"
bitfld.quad 0x8 56.--58. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.tbyte 0x8 32.--55. 1. "RESERVED2,RESERVED2"
hexmask.quad.word 0x8 16.--31. 1. "PhysicalAddress,PhysicalAddress"
newline
hexmask.quad.byte 0x8 12.--15. 1. "RESERVED1,RESERVED1"
bitfld.quad 0x8 10.--11. "Shareability,Shareability" "0,1,2,3"
newline
bitfld.quad 0x8 7.--9. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
hexmask.quad.byte 0x8 0.--6. 1. "RESERVED0,RESERVED0"
rgroup.long 0x8FFD0++0x2F
line.long 0x0 "GICR1_PIDR4,GICR1_PIDR4"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x0 4.--7. 1. "SIZE,SIZE"
newline
hexmask.long.byte 0x0 0.--3. 1. "DES_2,DES_2"
line.long 0x4 "GICR1_PIDR5,GICR1_PIDR5"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x4 0.--7. 1. "RESERVED,RESERVED"
line.long 0x8 "GICR1_PIDR6,GICR1_PIDR6"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x8 0.--7. 1. "RESERVED,RESERVED"
line.long 0xC "GICR1_PIDR7,GICR1_PIDR7"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RESERVED"
line.long 0x10 "GICR1_PIDR0,GICR1_PIDR0"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x10 0.--7. 1. "PART_0,PART_0"
line.long 0x14 "GICR1_PIDR1,GICR1_PIDR1"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x14 4.--7. 1. "DES_0,DES_0"
newline
hexmask.long.byte 0x14 0.--3. 1. "PART_1,PART_1"
line.long 0x18 "GICR1_PIDR2,GICR1_PIDR2"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x18 4.--7. 1. "REVISION,REVISION"
newline
bitfld.long 0x18 3. "JEDEC,JEDEC" "0,1"
bitfld.long 0x18 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7"
line.long 0x1C "GICR1_PIDR3,GICR1_PIDR3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,REVAND"
newline
bitfld.long 0x1C 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x1C 0.--2. "CMOD,CMOD" "0,1,2,3,4,5,6,7"
line.long 0x20 "GICR1_CIDR0,GICR1_CIDR0"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,PRMBL_0"
line.long 0x24 "GICR1_CIDR1,GICR1_CIDR1"
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS"
newline
hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,PRMBL_1"
line.long 0x28 "GICR1_CIDR2,GICR1_CIDR2"
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,PRMBL_2"
line.long 0x2C "GICR1_CIDR3,GICR1_CIDR3"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,PRMBL_3"
group.long 0x90080++0x3
line.long 0x0 "GICR1_IGROUPR0,GICR1_IGROUPR0"
bitfld.long 0x0 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x0 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x0 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x0 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x0 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x0 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x0 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x0 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x0 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x0 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x0 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x0 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x0 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x0 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x0 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x0 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x0 0. "group_status_bit0,group_status_bit0" "0,1"
group.long 0x90100++0x3
line.long 0x0 "GICR1_ISENABLER0,GICR1_ISENABLER0"
bitfld.long 0x0 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x0 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x0 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x0 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x0 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x0 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x0 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x0 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x0 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x0 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x0 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x0 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x0 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x0 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x0 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x0 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x0 0. "set_enable_bit0,set_enable_bit0" "0,1"
group.long 0x90180++0x3
line.long 0x0 "GICR1_ICENABLER0,GICR1_ICENABLER0"
bitfld.long 0x0 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x0 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x0 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x0 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x0 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x0 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x0 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x0 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x0 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x0 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x0 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x0 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x0 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x0 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x0 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x0 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x0 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
group.long 0x90200++0x3
line.long 0x0 "GICR1_ISPENDR0,GICR1_ISPENDR0"
bitfld.long 0x0 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x0 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x0 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x0 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x0 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x0 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x0 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x0 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x0 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x0 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x0 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x0 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x0 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x0 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x0 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x0 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x0 0. "set_pending_bit0,set_pending_bit0" "0,1"
group.long 0x90280++0x3
line.long 0x0 "GICR1_ICPENDR0,GICR1_ICPENDR0"
bitfld.long 0x0 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x0 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x0 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x0 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x0 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x0 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x0 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x0 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x0 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x0 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x0 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x0 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x0 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x0 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x0 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x0 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x0 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
group.long 0x90300++0x3
line.long 0x0 "GICR1_ISACTIVER0,GICR1_ISACTIVER0"
bitfld.long 0x0 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x0 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x0 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x0 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x0 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x0 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x0 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x0 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x0 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x0 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x0 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x0 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x0 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x0 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x0 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x0 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x0 0. "set_active_bit0,set_active_bit0" "0,1"
group.long 0x90380++0x3
line.long 0x0 "GICR1_ICACTIVER0,GICR1_ICACTIVER0"
bitfld.long 0x0 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x0 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x0 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x0 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x0 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x0 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x0 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x0 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x0 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x0 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x0 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x0 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x0 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x0 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x0 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x0 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x0 0. "clear_active_bit0,clear_active_bit0" "0,1"
group.long 0x90400++0x1F
line.long 0x0 "GICR1_IPRIORITYR0,GICR1_IPRIORITYR0"
hexmask.long.byte 0x0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x0 0.--7. 1. "offset0,offset0"
line.long 0x4 "GICR1_IPRIORITYR1,GICR1_IPRIORITYR1"
hexmask.long.byte 0x4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x4 0.--7. 1. "offset0,offset0"
line.long 0x8 "GICR1_IPRIORITYR2,GICR1_IPRIORITYR2"
hexmask.long.byte 0x8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x8 0.--7. 1. "offset0,offset0"
line.long 0xC "GICR1_IPRIORITYR3,GICR1_IPRIORITYR3"
hexmask.long.byte 0xC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC 0.--7. 1. "offset0,offset0"
line.long 0x10 "GICR1_IPRIORITYR4,GICR1_IPRIORITYR4"
hexmask.long.byte 0x10 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x10 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x10 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x10 0.--7. 1. "offset0,offset0"
line.long 0x14 "GICR1_IPRIORITYR5,GICR1_IPRIORITYR5"
hexmask.long.byte 0x14 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x14 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x14 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x14 0.--7. 1. "offset0,offset0"
line.long 0x18 "GICR1_IPRIORITYR6,GICR1_IPRIORITYR6"
hexmask.long.byte 0x18 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x18 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x18 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x18 0.--7. 1. "offset0,offset0"
line.long 0x1C "GICR1_IPRIORITYR7,GICR1_IPRIORITYR7"
hexmask.long.byte 0x1C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C 0.--7. 1. "offset0,offset0"
rgroup.long 0x90C00++0x3
line.long 0x0 "GICR1_ICFGR0,GICR1_ICFGR0"
bitfld.long 0x0 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x0 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x0 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x0 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x0 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x0 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x0 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x0 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x0 0.--1. "int_config0,int_config0" "0,1,2,3"
group.long 0x90C04++0x3
line.long 0x0 "GICR1_ICFGR1,GICR1_ICFGR1"
bitfld.long 0x0 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x0 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x0 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x0 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x0 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x0 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x0 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x0 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x0 0.--1. "int_config0,int_config0" "0,1,2,3"
group.long 0x90D00++0x3
line.long 0x0 "GICR1_IGRPMODR0,GICR1_IGRPMODR0"
bitfld.long 0x0 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x0 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x0 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x0 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x0 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x0 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x0 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x0 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x0 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x0 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x0 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x0 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x0 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x0 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x0 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x0 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x0 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
group.long 0x90E00++0x3
line.long 0x0 "GICR1_NSACR,GICR1_NSACR"
bitfld.long 0x0 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x0 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x0 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x0 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x0 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x0 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x0 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x0 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x0 0.--1. "ns_access0,ns_access0" "0,1,2,3"
rgroup.long 0x9C000++0x3
line.long 0x0 "GICR1_MISCSTATUSR,GICR1_MISCSTATUSR"
bitfld.long 0x0 31. "cpu_active,cpu_active" "0,1"
bitfld.long 0x0 30. "wake_request,wake_request" "0,1"
newline
hexmask.long 0x0 5.--29. 1. "RESERVED1,RESERVED1"
bitfld.long 0x0 4. "access_type,access_type" "0,1"
newline
bitfld.long 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x0 2. "EnableGrp1_s,EnableGrp1_s" "0,1"
newline
bitfld.long 0x0 1. "EnableGrp1_ns,EnableGrp1_ns" "0,1"
bitfld.long 0x0 0. "EnableGrp0,EnableGrp0" "0,1"
rgroup.long 0x9C008++0x3
line.long 0x0 "GICR1_IERRVR,GICR1_IERRVR"
bitfld.long 0x0 31. "valid_bit31,valid_bit31" "0,1"
bitfld.long 0x0 30. "valid_bit30,valid_bit30" "0,1"
newline
bitfld.long 0x0 29. "valid_bit29,valid_bit29" "0,1"
bitfld.long 0x0 28. "valid_bit28,valid_bit28" "0,1"
newline
bitfld.long 0x0 27. "valid_bit27,valid_bit27" "0,1"
bitfld.long 0x0 26. "valid_bit26,valid_bit26" "0,1"
newline
bitfld.long 0x0 25. "valid_bit25,valid_bit25" "0,1"
bitfld.long 0x0 24. "valid_bit24,valid_bit24" "0,1"
newline
bitfld.long 0x0 23. "valid_bit23,valid_bit23" "0,1"
bitfld.long 0x0 22. "valid_bit22,valid_bit22" "0,1"
newline
bitfld.long 0x0 21. "valid_bit21,valid_bit21" "0,1"
bitfld.long 0x0 20. "valid_bit20,valid_bit20" "0,1"
newline
bitfld.long 0x0 19. "valid_bit19,valid_bit19" "0,1"
bitfld.long 0x0 18. "valid_bit18,valid_bit18" "0,1"
newline
bitfld.long 0x0 17. "valid_bit17,valid_bit17" "0,1"
bitfld.long 0x0 16. "valid_bit16,valid_bit16" "0,1"
newline
bitfld.long 0x0 15. "valid_bit15,valid_bit15" "0,1"
bitfld.long 0x0 14. "valid_bit14,valid_bit14" "0,1"
newline
bitfld.long 0x0 13. "valid_bit13,valid_bit13" "0,1"
bitfld.long 0x0 12. "valid_bit12,valid_bit12" "0,1"
newline
bitfld.long 0x0 11. "valid_bit11,valid_bit11" "0,1"
bitfld.long 0x0 10. "valid_bit10,valid_bit10" "0,1"
newline
bitfld.long 0x0 9. "valid_bit9,valid_bit9" "0,1"
bitfld.long 0x0 8. "valid_bit8,valid_bit8" "0,1"
newline
bitfld.long 0x0 7. "valid_bit7,valid_bit7" "0,1"
bitfld.long 0x0 6. "valid_bit6,valid_bit6" "0,1"
newline
bitfld.long 0x0 5. "valid_bit5,valid_bit5" "0,1"
bitfld.long 0x0 4. "valid_bit4,valid_bit4" "0,1"
newline
bitfld.long 0x0 3. "valid_bit3,valid_bit3" "0,1"
bitfld.long 0x0 2. "valid_bit2,valid_bit2" "0,1"
newline
bitfld.long 0x0 1. "valid_bit1,valid_bit1" "0,1"
bitfld.long 0x0 0. "valid_bit0,valid_bit0" "0,1"
group.quad 0x9C010++0x7
line.quad 0x0 "GICR1_SGIDR,GICR1_SGIDR"
bitfld.quad 0x0 63. "RESERVED16,RESERVED16" "0,1"
bitfld.quad 0x0 62. "grpmod15,grpmod15" "0,1"
newline
bitfld.quad 0x0 61. "grp15,grp15" "0,1"
bitfld.quad 0x0 60. "nsacr15,nsacr15" "0,1"
newline
bitfld.quad 0x0 59. "RESERVED15,RESERVED15" "0,1"
bitfld.quad 0x0 58. "grpmod14,grpmod14" "0,1"
newline
bitfld.quad 0x0 57. "grp14,grp14" "0,1"
bitfld.quad 0x0 56. "nsacr14,nsacr14" "0,1"
newline
bitfld.quad 0x0 55. "RESERVED13,RESERVED13" "0,1"
bitfld.quad 0x0 54. "grpmod13,grpmod13" "0,1"
newline
bitfld.quad 0x0 53. "grp13,grp13" "0,1"
bitfld.quad 0x0 52. "nsacr13,nsacr13" "0,1"
newline
bitfld.quad 0x0 51. "RESERVED12,RESERVED12" "0,1"
bitfld.quad 0x0 50. "grpmod12,grpmod12" "0,1"
newline
bitfld.quad 0x0 49. "grp12,grp12" "0,1"
bitfld.quad 0x0 48. "nsacr12,nsacr12" "0,1"
newline
bitfld.quad 0x0 47. "RESERVED11,RESERVED11" "0,1"
bitfld.quad 0x0 46. "grpmod11,grpmod11" "0,1"
newline
bitfld.quad 0x0 45. "grp11,grp11" "0,1"
bitfld.quad 0x0 44. "nsacr11,nsacr11" "0,1"
newline
bitfld.quad 0x0 43. "RESERVED10,RESERVED10" "0,1"
bitfld.quad 0x0 42. "grpmod10,grpmod10" "0,1"
newline
bitfld.quad 0x0 41. "grp10,grp10" "0,1"
bitfld.quad 0x0 40. "nsacr10,nsacr10" "0,1"
newline
bitfld.quad 0x0 39. "RESERVED9,RESERVED9" "0,1"
bitfld.quad 0x0 38. "grpmod9,grpmod9" "0,1"
newline
bitfld.quad 0x0 37. "grp9,grp9" "0,1"
bitfld.quad 0x0 36. "nsacr9,nsacr9" "0,1"
newline
bitfld.quad 0x0 35. "RESERVED8,RESERVED8" "0,1"
bitfld.quad 0x0 34. "grpmod8,grpmod8" "0,1"
newline
bitfld.quad 0x0 33. "grp8,grp8" "0,1"
bitfld.quad 0x0 32. "nsacr8,nsacr8" "0,1"
newline
bitfld.quad 0x0 31. "RESERVED7,RESERVED7" "0,1"
bitfld.quad 0x0 30. "grpmod7,grpmod7" "0,1"
newline
bitfld.quad 0x0 29. "grp7,grp7" "0,1"
bitfld.quad 0x0 28. "nsacr7,nsacr7" "0,1"
newline
bitfld.quad 0x0 27. "RESERVED6,RESERVED6" "0,1"
bitfld.quad 0x0 26. "grpmod6,grpmod6" "0,1"
newline
bitfld.quad 0x0 25. "grp6,grp6" "0,1"
bitfld.quad 0x0 24. "nsacr6,nsacr6" "0,1"
newline
bitfld.quad 0x0 23. "RESERVED5,RESERVED5" "0,1"
bitfld.quad 0x0 22. "grpmod5,grpmod5" "0,1"
newline
bitfld.quad 0x0 21. "grp5,grp5" "0,1"
bitfld.quad 0x0 20. "nsacr5,nsacr5" "0,1"
newline
bitfld.quad 0x0 19. "RESERVED4,RESERVED4" "0,1"
bitfld.quad 0x0 18. "grpmod4,grpmod4" "0,1"
newline
bitfld.quad 0x0 17. "grp4,grp4" "0,1"
bitfld.quad 0x0 16. "nsacr4,nsacr4" "0,1"
newline
bitfld.quad 0x0 15. "RESERVED3,RESERVED3" "0,1"
bitfld.quad 0x0 14. "grpmod3,grpmod3" "0,1"
newline
bitfld.quad 0x0 13. "grp3,grp3" "0,1"
bitfld.quad 0x0 12. "nsacr3,nsacr3" "0,1"
newline
bitfld.quad 0x0 11. "RESERVED2,RESERVED2" "0,1"
bitfld.quad 0x0 10. "grpmod2,grpmod2" "0,1"
newline
bitfld.quad 0x0 9. "grp2,grp2" "0,1"
bitfld.quad 0x0 8. "nsacr2,nsacr2" "0,1"
newline
bitfld.quad 0x0 7. "RESERVED1,RESERVED1" "0,1"
bitfld.quad 0x0 6. "grpmod1,grpmod1" "0,1"
newline
bitfld.quad 0x0 5. "grp1,grp1" "0,1"
bitfld.quad 0x0 4. "nsacr1,nsacr1" "0,1"
newline
bitfld.quad 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.quad 0x0 2. "grpmod0,grpmod0" "0,1"
newline
bitfld.quad 0x0 1. "grp0,grp0" "0,1"
bitfld.quad 0x0 0. "nsacr0,nsacr0" "0,1"
rgroup.long 0x9F000++0x7
line.long 0x0 "GICR1_CFGID0,GICR1_CFGID0"
hexmask.long.byte 0x0 28.--31. 1. "Af3width,Af3width"
hexmask.long.byte 0x0 24.--27. 1. "Af2width,Af2width"
newline
hexmask.long.byte 0x0 20.--23. 1. "Af1width,Af1width"
hexmask.long.byte 0x0 16.--19. 1. "Af0width,Af0width"
newline
hexmask.long.byte 0x0 12.--15. 1. "TargetlistWidth,TargetlistWidth"
bitfld.long 0x0 11. "ECCSupport,ECCSupport" "0,1"
newline
bitfld.long 0x0 9.--10. "RESERVED0,RESERVED0" "0,1,2,3"
hexmask.long.word 0x0 0.--8. 1. "PPINumber,PPINumber"
line.long 0x4 "GICR1_CFGID1,GICR1_CFGID1"
hexmask.long.byte 0x4 28.--31. 1. "Version,Version"
hexmask.long.byte 0x4 24.--27. 1. "REVAND,REVAND"
newline
hexmask.long.byte 0x4 20.--23. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x4 16.--19. 1. "PPIsPerProcessor,PPIsPerProcessor"
newline
bitfld.long 0x4 13.--15. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "DirectUpstream,DirectUpstream" "0,1"
newline
hexmask.long.byte 0x4 4.--11. 1. "NumCPUs,NumCPUs"
hexmask.long.byte 0x4 0.--3. 1. "NumARE0CPUs,NumARE0CPUs"
group.long 0xA0000++0x3
line.long 0x0 "GICR2_CTLR,GICR2_CTLR"
rbitfld.long 0x0 31. "UWP,UWP" "0,1"
hexmask.long.byte 0x0 27.--30. 1. "RESERVED2,RESERVED2"
newline
bitfld.long 0x0 26. "DPG1S,DPG1S" "0,1"
bitfld.long 0x0 25. "DPG1NS,DPG1NS" "0,1"
newline
bitfld.long 0x0 24. "DPG0,DPG0" "0,1"
hexmask.long.tbyte 0x0 4.--23. 1. "RESERVED1,RESERVED1"
newline
rbitfld.long 0x0 3. "RWP,RWP" "0,1"
bitfld.long 0x0 1.--2. "RESERVED0,RESERVED0" "0,1,2,3"
newline
bitfld.long 0x0 0. "EnableLPIs,EnableLPIs" "0,1"
rgroup.long 0xA0004++0x3
line.long 0x0 "GICR2_IIDR,GICR2_IIDR"
hexmask.long.byte 0x0 24.--31. 1. "ProductID,ProductID"
hexmask.long.byte 0x0 20.--23. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x0 16.--19. 1. "Variant,Variant"
hexmask.long.byte 0x0 12.--15. 1. "Revision,Revision"
newline
hexmask.long.word 0x0 0.--11. 1. "Implementer,Implementer"
rgroup.quad 0xA0008++0x7
line.quad 0x0 "GICR2_TYPER,GICR2_TYPER"
hexmask.quad.long 0x0 32.--63. 1. "AffinityValue,AffinityValue"
hexmask.quad.byte 0x0 26.--31. 1. "RESERVED2,RESERVED2"
newline
bitfld.quad 0x0 24.--25. "CommonLPIAff,CommonLPIAff" "0,1,2,3"
hexmask.quad.word 0x0 8.--23. 1. "ProcessorNumber,ProcessorNumber"
newline
bitfld.quad 0x0 6.--7. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x0 5. "DPGS,DPGS" "0,1"
newline
bitfld.quad 0x0 4. "Last,Last" "0,1"
bitfld.quad 0x0 3. "DirectLPI,DirectLPI" "0,1"
newline
bitfld.quad 0x0 2. "RESERVED0,RESERVED0" "0,1"
bitfld.quad 0x0 1. "VLPIS,VLPIS" "0,1"
newline
bitfld.quad 0x0 0. "PLPIS,PLPIS" "0,1"
group.long 0xA0014++0x3
line.long 0x0 "GICR2_WAKER,GICR2_WAKER"
rbitfld.long 0x0 31. "Quiescent,Quiescent" "0,1"
hexmask.long 0x0 3.--30. 1. "RESERVED0,RESERVED0"
newline
rbitfld.long 0x0 2. "ChildrenAsleep,ChildrenAsleep" "0,1"
bitfld.long 0x0 1. "ProcessorSleep,ProcessorSleep" "0,1"
newline
bitfld.long 0x0 0. "Sleep,Sleep" "0,1"
group.long 0xA0020++0xB
line.long 0x0 "GICR2_FCTLR,GICR2_FCTLR"
bitfld.long 0x0 31. "QD,QD" "0,1"
hexmask.long.tbyte 0x0 7.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0x0 4.--6. "CGO,CGO" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 1.--3. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "SIP,SIP" "0,1"
line.long 0x4 "GICR2_PWRR,GICR2_PWRR"
hexmask.long.byte 0x4 24.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.word 0x4 15.--23. 1. "RDG,RDG"
newline
hexmask.long.byte 0x4 8.--14. 1. "RDGO,RDGO"
hexmask.long.byte 0x4 4.--7. 1. "RESERVED0,RESERVED0"
newline
rbitfld.long 0x4 3. "RDGPO,RDGPO" "0,1"
bitfld.long 0x4 2. "RDGPD,RDGPD" "0,1"
newline
bitfld.long 0x4 1. "RDAG,RDAG" "0,1"
bitfld.long 0x4 0. "RDPD,RDPD" "0,1"
line.long 0x8 "GICR2_CLASS,GICR2_CLASS"
hexmask.long 0x8 1.--31. 1. "RESERVED0,RESERVED0"
bitfld.long 0x8 0. "Class,Class" "0,1"
group.quad 0xA0070++0xF
line.quad 0x0 "GICR2_PROPBASER,GICR2_PROPBASER"
hexmask.quad.byte 0x0 59.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 56.--58. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.tbyte 0x0 32.--55. 1. "RESERVED1,RESERVED1"
hexmask.quad.tbyte 0x0 12.--31. 1. "PhysicalAddress,PhysicalAddress"
newline
bitfld.quad 0x0 10.--11. "Shareability,Shareability" "0,1,2,3"
bitfld.quad 0x0 7.--9. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 5.--6. "RESERVED0,RESERVED0" "0,1,2,3"
hexmask.quad.byte 0x0 0.--4. 1. "IDBits,IDBits"
line.quad 0x8 "GICR2_PENDBASER,GICR2_PENDBASER"
bitfld.quad 0x8 63. "RESERVED4,RESERVED4" "0,1"
bitfld.quad 0x8 62. "PendingTableZero,PendingTableZero" "0,1"
newline
bitfld.quad 0x8 59.--61. "RESERVED3,RESERVED3" "0,1,2,3,4,5,6,7"
bitfld.quad 0x8 56.--58. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.tbyte 0x8 32.--55. 1. "RESERVED2,RESERVED2"
hexmask.quad.word 0x8 16.--31. 1. "PhysicalAddress,PhysicalAddress"
newline
hexmask.quad.byte 0x8 12.--15. 1. "RESERVED1,RESERVED1"
bitfld.quad 0x8 10.--11. "Shareability,Shareability" "0,1,2,3"
newline
bitfld.quad 0x8 7.--9. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
hexmask.quad.byte 0x8 0.--6. 1. "RESERVED0,RESERVED0"
rgroup.long 0xAFFD0++0x2F
line.long 0x0 "GICR2_PIDR4,GICR2_PIDR4"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x0 4.--7. 1. "SIZE,SIZE"
newline
hexmask.long.byte 0x0 0.--3. 1. "DES_2,DES_2"
line.long 0x4 "GICR2_PIDR5,GICR2_PIDR5"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x4 0.--7. 1. "RESERVED,RESERVED"
line.long 0x8 "GICR2_PIDR6,GICR2_PIDR6"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x8 0.--7. 1. "RESERVED,RESERVED"
line.long 0xC "GICR2_PIDR7,GICR2_PIDR7"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RESERVED"
line.long 0x10 "GICR2_PIDR0,GICR2_PIDR0"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x10 0.--7. 1. "PART_0,PART_0"
line.long 0x14 "GICR2_PIDR1,GICR2_PIDR1"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x14 4.--7. 1. "DES_0,DES_0"
newline
hexmask.long.byte 0x14 0.--3. 1. "PART_1,PART_1"
line.long 0x18 "GICR2_PIDR2,GICR2_PIDR2"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x18 4.--7. 1. "REVISION,REVISION"
newline
bitfld.long 0x18 3. "JEDEC,JEDEC" "0,1"
bitfld.long 0x18 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7"
line.long 0x1C "GICR2_PIDR3,GICR2_PIDR3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,REVAND"
newline
bitfld.long 0x1C 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x1C 0.--2. "CMOD,CMOD" "0,1,2,3,4,5,6,7"
line.long 0x20 "GICR2_CIDR0,GICR2_CIDR0"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,PRMBL_0"
line.long 0x24 "GICR2_CIDR1,GICR2_CIDR1"
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS"
newline
hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,PRMBL_1"
line.long 0x28 "GICR2_CIDR2,GICR2_CIDR2"
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,PRMBL_2"
line.long 0x2C "GICR2_CIDR3,GICR2_CIDR3"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,PRMBL_3"
group.long 0xB0080++0x3
line.long 0x0 "GICR2_IGROUPR0,GICR2_IGROUPR0"
bitfld.long 0x0 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x0 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x0 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x0 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x0 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x0 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x0 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x0 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x0 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x0 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x0 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x0 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x0 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x0 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x0 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x0 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x0 0. "group_status_bit0,group_status_bit0" "0,1"
group.long 0xB0100++0x3
line.long 0x0 "GICR2_ISENABLER0,GICR2_ISENABLER0"
bitfld.long 0x0 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x0 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x0 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x0 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x0 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x0 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x0 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x0 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x0 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x0 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x0 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x0 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x0 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x0 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x0 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x0 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x0 0. "set_enable_bit0,set_enable_bit0" "0,1"
group.long 0xB0180++0x3
line.long 0x0 "GICR2_ICENABLER0,GICR2_ICENABLER0"
bitfld.long 0x0 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x0 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x0 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x0 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x0 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x0 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x0 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x0 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x0 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x0 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x0 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x0 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x0 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x0 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x0 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x0 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x0 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
group.long 0xB0200++0x3
line.long 0x0 "GICR2_ISPENDR0,GICR2_ISPENDR0"
bitfld.long 0x0 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x0 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x0 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x0 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x0 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x0 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x0 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x0 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x0 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x0 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x0 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x0 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x0 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x0 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x0 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x0 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x0 0. "set_pending_bit0,set_pending_bit0" "0,1"
group.long 0xB0280++0x3
line.long 0x0 "GICR2_ICPENDR0,GICR2_ICPENDR0"
bitfld.long 0x0 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x0 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x0 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x0 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x0 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x0 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x0 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x0 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x0 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x0 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x0 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x0 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x0 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x0 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x0 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x0 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x0 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
group.long 0xB0300++0x3
line.long 0x0 "GICR2_ISACTIVER0,GICR2_ISACTIVER0"
bitfld.long 0x0 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x0 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x0 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x0 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x0 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x0 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x0 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x0 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x0 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x0 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x0 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x0 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x0 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x0 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x0 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x0 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x0 0. "set_active_bit0,set_active_bit0" "0,1"
group.long 0xB0380++0x3
line.long 0x0 "GICR2_ICACTIVER0,GICR2_ICACTIVER0"
bitfld.long 0x0 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x0 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x0 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x0 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x0 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x0 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x0 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x0 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x0 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x0 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x0 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x0 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x0 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x0 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x0 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x0 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x0 0. "clear_active_bit0,clear_active_bit0" "0,1"
group.long 0xB0400++0x1F
line.long 0x0 "GICR2_IPRIORITYR0,GICR2_IPRIORITYR0"
hexmask.long.byte 0x0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x0 0.--7. 1. "offset0,offset0"
line.long 0x4 "GICR2_IPRIORITYR1,GICR2_IPRIORITYR1"
hexmask.long.byte 0x4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x4 0.--7. 1. "offset0,offset0"
line.long 0x8 "GICR2_IPRIORITYR2,GICR2_IPRIORITYR2"
hexmask.long.byte 0x8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x8 0.--7. 1. "offset0,offset0"
line.long 0xC "GICR2_IPRIORITYR3,GICR2_IPRIORITYR3"
hexmask.long.byte 0xC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC 0.--7. 1. "offset0,offset0"
line.long 0x10 "GICR2_IPRIORITYR4,GICR2_IPRIORITYR4"
hexmask.long.byte 0x10 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x10 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x10 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x10 0.--7. 1. "offset0,offset0"
line.long 0x14 "GICR2_IPRIORITYR5,GICR2_IPRIORITYR5"
hexmask.long.byte 0x14 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x14 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x14 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x14 0.--7. 1. "offset0,offset0"
line.long 0x18 "GICR2_IPRIORITYR6,GICR2_IPRIORITYR6"
hexmask.long.byte 0x18 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x18 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x18 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x18 0.--7. 1. "offset0,offset0"
line.long 0x1C "GICR2_IPRIORITYR7,GICR2_IPRIORITYR7"
hexmask.long.byte 0x1C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C 0.--7. 1. "offset0,offset0"
rgroup.long 0xB0C00++0x3
line.long 0x0 "GICR2_ICFGR0,GICR2_ICFGR0"
bitfld.long 0x0 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x0 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x0 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x0 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x0 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x0 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x0 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x0 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x0 0.--1. "int_config0,int_config0" "0,1,2,3"
group.long 0xB0C04++0x3
line.long 0x0 "GICR2_ICFGR1,GICR2_ICFGR1"
bitfld.long 0x0 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x0 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x0 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x0 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x0 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x0 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x0 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x0 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x0 0.--1. "int_config0,int_config0" "0,1,2,3"
group.long 0xB0D00++0x3
line.long 0x0 "GICR2_IGRPMODR0,GICR2_IGRPMODR0"
bitfld.long 0x0 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x0 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x0 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x0 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x0 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x0 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x0 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x0 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x0 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x0 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x0 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x0 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x0 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x0 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x0 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x0 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x0 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
group.long 0xB0E00++0x3
line.long 0x0 "GICR2_NSACR,GICR2_NSACR"
bitfld.long 0x0 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x0 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x0 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x0 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x0 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x0 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x0 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x0 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x0 0.--1. "ns_access0,ns_access0" "0,1,2,3"
rgroup.long 0xBC000++0x3
line.long 0x0 "GICR2_MISCSTATUSR,GICR2_MISCSTATUSR"
bitfld.long 0x0 31. "cpu_active,cpu_active" "0,1"
bitfld.long 0x0 30. "wake_request,wake_request" "0,1"
newline
hexmask.long 0x0 5.--29. 1. "RESERVED1,RESERVED1"
bitfld.long 0x0 4. "access_type,access_type" "0,1"
newline
bitfld.long 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x0 2. "EnableGrp1_s,EnableGrp1_s" "0,1"
newline
bitfld.long 0x0 1. "EnableGrp1_ns,EnableGrp1_ns" "0,1"
bitfld.long 0x0 0. "EnableGrp0,EnableGrp0" "0,1"
rgroup.long 0xBC008++0x3
line.long 0x0 "GICR2_IERRVR,GICR2_IERRVR"
bitfld.long 0x0 31. "valid_bit31,valid_bit31" "0,1"
bitfld.long 0x0 30. "valid_bit30,valid_bit30" "0,1"
newline
bitfld.long 0x0 29. "valid_bit29,valid_bit29" "0,1"
bitfld.long 0x0 28. "valid_bit28,valid_bit28" "0,1"
newline
bitfld.long 0x0 27. "valid_bit27,valid_bit27" "0,1"
bitfld.long 0x0 26. "valid_bit26,valid_bit26" "0,1"
newline
bitfld.long 0x0 25. "valid_bit25,valid_bit25" "0,1"
bitfld.long 0x0 24. "valid_bit24,valid_bit24" "0,1"
newline
bitfld.long 0x0 23. "valid_bit23,valid_bit23" "0,1"
bitfld.long 0x0 22. "valid_bit22,valid_bit22" "0,1"
newline
bitfld.long 0x0 21. "valid_bit21,valid_bit21" "0,1"
bitfld.long 0x0 20. "valid_bit20,valid_bit20" "0,1"
newline
bitfld.long 0x0 19. "valid_bit19,valid_bit19" "0,1"
bitfld.long 0x0 18. "valid_bit18,valid_bit18" "0,1"
newline
bitfld.long 0x0 17. "valid_bit17,valid_bit17" "0,1"
bitfld.long 0x0 16. "valid_bit16,valid_bit16" "0,1"
newline
bitfld.long 0x0 15. "valid_bit15,valid_bit15" "0,1"
bitfld.long 0x0 14. "valid_bit14,valid_bit14" "0,1"
newline
bitfld.long 0x0 13. "valid_bit13,valid_bit13" "0,1"
bitfld.long 0x0 12. "valid_bit12,valid_bit12" "0,1"
newline
bitfld.long 0x0 11. "valid_bit11,valid_bit11" "0,1"
bitfld.long 0x0 10. "valid_bit10,valid_bit10" "0,1"
newline
bitfld.long 0x0 9. "valid_bit9,valid_bit9" "0,1"
bitfld.long 0x0 8. "valid_bit8,valid_bit8" "0,1"
newline
bitfld.long 0x0 7. "valid_bit7,valid_bit7" "0,1"
bitfld.long 0x0 6. "valid_bit6,valid_bit6" "0,1"
newline
bitfld.long 0x0 5. "valid_bit5,valid_bit5" "0,1"
bitfld.long 0x0 4. "valid_bit4,valid_bit4" "0,1"
newline
bitfld.long 0x0 3. "valid_bit3,valid_bit3" "0,1"
bitfld.long 0x0 2. "valid_bit2,valid_bit2" "0,1"
newline
bitfld.long 0x0 1. "valid_bit1,valid_bit1" "0,1"
bitfld.long 0x0 0. "valid_bit0,valid_bit0" "0,1"
group.quad 0xBC010++0x7
line.quad 0x0 "GICR2_SGIDR,GICR2_SGIDR"
bitfld.quad 0x0 63. "RESERVED16,RESERVED16" "0,1"
bitfld.quad 0x0 62. "grpmod15,grpmod15" "0,1"
newline
bitfld.quad 0x0 61. "grp15,grp15" "0,1"
bitfld.quad 0x0 60. "nsacr15,nsacr15" "0,1"
newline
bitfld.quad 0x0 59. "RESERVED15,RESERVED15" "0,1"
bitfld.quad 0x0 58. "grpmod14,grpmod14" "0,1"
newline
bitfld.quad 0x0 57. "grp14,grp14" "0,1"
bitfld.quad 0x0 56. "nsacr14,nsacr14" "0,1"
newline
bitfld.quad 0x0 55. "RESERVED13,RESERVED13" "0,1"
bitfld.quad 0x0 54. "grpmod13,grpmod13" "0,1"
newline
bitfld.quad 0x0 53. "grp13,grp13" "0,1"
bitfld.quad 0x0 52. "nsacr13,nsacr13" "0,1"
newline
bitfld.quad 0x0 51. "RESERVED12,RESERVED12" "0,1"
bitfld.quad 0x0 50. "grpmod12,grpmod12" "0,1"
newline
bitfld.quad 0x0 49. "grp12,grp12" "0,1"
bitfld.quad 0x0 48. "nsacr12,nsacr12" "0,1"
newline
bitfld.quad 0x0 47. "RESERVED11,RESERVED11" "0,1"
bitfld.quad 0x0 46. "grpmod11,grpmod11" "0,1"
newline
bitfld.quad 0x0 45. "grp11,grp11" "0,1"
bitfld.quad 0x0 44. "nsacr11,nsacr11" "0,1"
newline
bitfld.quad 0x0 43. "RESERVED10,RESERVED10" "0,1"
bitfld.quad 0x0 42. "grpmod10,grpmod10" "0,1"
newline
bitfld.quad 0x0 41. "grp10,grp10" "0,1"
bitfld.quad 0x0 40. "nsacr10,nsacr10" "0,1"
newline
bitfld.quad 0x0 39. "RESERVED9,RESERVED9" "0,1"
bitfld.quad 0x0 38. "grpmod9,grpmod9" "0,1"
newline
bitfld.quad 0x0 37. "grp9,grp9" "0,1"
bitfld.quad 0x0 36. "nsacr9,nsacr9" "0,1"
newline
bitfld.quad 0x0 35. "RESERVED8,RESERVED8" "0,1"
bitfld.quad 0x0 34. "grpmod8,grpmod8" "0,1"
newline
bitfld.quad 0x0 33. "grp8,grp8" "0,1"
bitfld.quad 0x0 32. "nsacr8,nsacr8" "0,1"
newline
bitfld.quad 0x0 31. "RESERVED7,RESERVED7" "0,1"
bitfld.quad 0x0 30. "grpmod7,grpmod7" "0,1"
newline
bitfld.quad 0x0 29. "grp7,grp7" "0,1"
bitfld.quad 0x0 28. "nsacr7,nsacr7" "0,1"
newline
bitfld.quad 0x0 27. "RESERVED6,RESERVED6" "0,1"
bitfld.quad 0x0 26. "grpmod6,grpmod6" "0,1"
newline
bitfld.quad 0x0 25. "grp6,grp6" "0,1"
bitfld.quad 0x0 24. "nsacr6,nsacr6" "0,1"
newline
bitfld.quad 0x0 23. "RESERVED5,RESERVED5" "0,1"
bitfld.quad 0x0 22. "grpmod5,grpmod5" "0,1"
newline
bitfld.quad 0x0 21. "grp5,grp5" "0,1"
bitfld.quad 0x0 20. "nsacr5,nsacr5" "0,1"
newline
bitfld.quad 0x0 19. "RESERVED4,RESERVED4" "0,1"
bitfld.quad 0x0 18. "grpmod4,grpmod4" "0,1"
newline
bitfld.quad 0x0 17. "grp4,grp4" "0,1"
bitfld.quad 0x0 16. "nsacr4,nsacr4" "0,1"
newline
bitfld.quad 0x0 15. "RESERVED3,RESERVED3" "0,1"
bitfld.quad 0x0 14. "grpmod3,grpmod3" "0,1"
newline
bitfld.quad 0x0 13. "grp3,grp3" "0,1"
bitfld.quad 0x0 12. "nsacr3,nsacr3" "0,1"
newline
bitfld.quad 0x0 11. "RESERVED2,RESERVED2" "0,1"
bitfld.quad 0x0 10. "grpmod2,grpmod2" "0,1"
newline
bitfld.quad 0x0 9. "grp2,grp2" "0,1"
bitfld.quad 0x0 8. "nsacr2,nsacr2" "0,1"
newline
bitfld.quad 0x0 7. "RESERVED1,RESERVED1" "0,1"
bitfld.quad 0x0 6. "grpmod1,grpmod1" "0,1"
newline
bitfld.quad 0x0 5. "grp1,grp1" "0,1"
bitfld.quad 0x0 4. "nsacr1,nsacr1" "0,1"
newline
bitfld.quad 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.quad 0x0 2. "grpmod0,grpmod0" "0,1"
newline
bitfld.quad 0x0 1. "grp0,grp0" "0,1"
bitfld.quad 0x0 0. "nsacr0,nsacr0" "0,1"
rgroup.long 0xBF000++0x7
line.long 0x0 "GICR2_CFGID0,GICR2_CFGID0"
hexmask.long.byte 0x0 28.--31. 1. "Af3width,Af3width"
hexmask.long.byte 0x0 24.--27. 1. "Af2width,Af2width"
newline
hexmask.long.byte 0x0 20.--23. 1. "Af1width,Af1width"
hexmask.long.byte 0x0 16.--19. 1. "Af0width,Af0width"
newline
hexmask.long.byte 0x0 12.--15. 1. "TargetlistWidth,TargetlistWidth"
bitfld.long 0x0 11. "ECCSupport,ECCSupport" "0,1"
newline
bitfld.long 0x0 9.--10. "RESERVED0,RESERVED0" "0,1,2,3"
hexmask.long.word 0x0 0.--8. 1. "PPINumber,PPINumber"
line.long 0x4 "GICR2_CFGID1,GICR2_CFGID1"
hexmask.long.byte 0x4 28.--31. 1. "Version,Version"
hexmask.long.byte 0x4 24.--27. 1. "REVAND,REVAND"
newline
hexmask.long.byte 0x4 20.--23. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x4 16.--19. 1. "PPIsPerProcessor,PPIsPerProcessor"
newline
bitfld.long 0x4 13.--15. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "DirectUpstream,DirectUpstream" "0,1"
newline
hexmask.long.byte 0x4 4.--11. 1. "NumCPUs,NumCPUs"
hexmask.long.byte 0x4 0.--3. 1. "NumARE0CPUs,NumARE0CPUs"
group.long 0xC0000++0x3
line.long 0x0 "GICR3_CTLR,GICR3_CTLR"
rbitfld.long 0x0 31. "UWP,UWP" "0,1"
hexmask.long.byte 0x0 27.--30. 1. "RESERVED2,RESERVED2"
newline
bitfld.long 0x0 26. "DPG1S,DPG1S" "0,1"
bitfld.long 0x0 25. "DPG1NS,DPG1NS" "0,1"
newline
bitfld.long 0x0 24. "DPG0,DPG0" "0,1"
hexmask.long.tbyte 0x0 4.--23. 1. "RESERVED1,RESERVED1"
newline
rbitfld.long 0x0 3. "RWP,RWP" "0,1"
bitfld.long 0x0 1.--2. "RESERVED0,RESERVED0" "0,1,2,3"
newline
bitfld.long 0x0 0. "EnableLPIs,EnableLPIs" "0,1"
rgroup.long 0xC0004++0x3
line.long 0x0 "GICR3_IIDR,GICR3_IIDR"
hexmask.long.byte 0x0 24.--31. 1. "ProductID,ProductID"
hexmask.long.byte 0x0 20.--23. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x0 16.--19. 1. "Variant,Variant"
hexmask.long.byte 0x0 12.--15. 1. "Revision,Revision"
newline
hexmask.long.word 0x0 0.--11. 1. "Implementer,Implementer"
rgroup.quad 0xC0008++0x7
line.quad 0x0 "GICR3_TYPER,GICR3_TYPER"
hexmask.quad.long 0x0 32.--63. 1. "AffinityValue,AffinityValue"
hexmask.quad.byte 0x0 26.--31. 1. "RESERVED2,RESERVED2"
newline
bitfld.quad 0x0 24.--25. "CommonLPIAff,CommonLPIAff" "0,1,2,3"
hexmask.quad.word 0x0 8.--23. 1. "ProcessorNumber,ProcessorNumber"
newline
bitfld.quad 0x0 6.--7. "RESERVED1,RESERVED1" "0,1,2,3"
bitfld.quad 0x0 5. "DPGS,DPGS" "0,1"
newline
bitfld.quad 0x0 4. "Last,Last" "0,1"
bitfld.quad 0x0 3. "DirectLPI,DirectLPI" "0,1"
newline
bitfld.quad 0x0 2. "RESERVED0,RESERVED0" "0,1"
bitfld.quad 0x0 1. "VLPIS,VLPIS" "0,1"
newline
bitfld.quad 0x0 0. "PLPIS,PLPIS" "0,1"
group.long 0xC0014++0x3
line.long 0x0 "GICR3_WAKER,GICR3_WAKER"
rbitfld.long 0x0 31. "Quiescent,Quiescent" "0,1"
hexmask.long 0x0 3.--30. 1. "RESERVED0,RESERVED0"
newline
rbitfld.long 0x0 2. "ChildrenAsleep,ChildrenAsleep" "0,1"
bitfld.long 0x0 1. "ProcessorSleep,ProcessorSleep" "0,1"
newline
bitfld.long 0x0 0. "Sleep,Sleep" "0,1"
group.long 0xC0020++0xB
line.long 0x0 "GICR3_FCTLR,GICR3_FCTLR"
bitfld.long 0x0 31. "QD,QD" "0,1"
hexmask.long.tbyte 0x0 7.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0x0 4.--6. "CGO,CGO" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 1.--3. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "SIP,SIP" "0,1"
line.long 0x4 "GICR3_PWRR,GICR3_PWRR"
hexmask.long.byte 0x4 24.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.word 0x4 15.--23. 1. "RDG,RDG"
newline
hexmask.long.byte 0x4 8.--14. 1. "RDGO,RDGO"
hexmask.long.byte 0x4 4.--7. 1. "RESERVED0,RESERVED0"
newline
rbitfld.long 0x4 3. "RDGPO,RDGPO" "0,1"
bitfld.long 0x4 2. "RDGPD,RDGPD" "0,1"
newline
bitfld.long 0x4 1. "RDAG,RDAG" "0,1"
bitfld.long 0x4 0. "RDPD,RDPD" "0,1"
line.long 0x8 "GICR3_CLASS,GICR3_CLASS"
hexmask.long 0x8 1.--31. 1. "RESERVED0,RESERVED0"
bitfld.long 0x8 0. "Class,Class" "0,1"
group.quad 0xC0070++0xF
line.quad 0x0 "GICR3_PROPBASER,GICR3_PROPBASER"
hexmask.quad.byte 0x0 59.--63. 1. "RESERVED2,RESERVED2"
bitfld.quad 0x0 56.--58. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.tbyte 0x0 32.--55. 1. "RESERVED1,RESERVED1"
hexmask.quad.tbyte 0x0 12.--31. 1. "PhysicalAddress,PhysicalAddress"
newline
bitfld.quad 0x0 10.--11. "Shareability,Shareability" "0,1,2,3"
bitfld.quad 0x0 7.--9. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 5.--6. "RESERVED0,RESERVED0" "0,1,2,3"
hexmask.quad.byte 0x0 0.--4. 1. "IDBits,IDBits"
line.quad 0x8 "GICR3_PENDBASER,GICR3_PENDBASER"
bitfld.quad 0x8 63. "RESERVED4,RESERVED4" "0,1"
bitfld.quad 0x8 62. "PendingTableZero,PendingTableZero" "0,1"
newline
bitfld.quad 0x8 59.--61. "RESERVED3,RESERVED3" "0,1,2,3,4,5,6,7"
bitfld.quad 0x8 56.--58. "OuterCacheability,OuterCacheability" "0,1,2,3,4,5,6,7"
newline
hexmask.quad.tbyte 0x8 32.--55. 1. "RESERVED2,RESERVED2"
hexmask.quad.word 0x8 16.--31. 1. "PhysicalAddress,PhysicalAddress"
newline
hexmask.quad.byte 0x8 12.--15. 1. "RESERVED1,RESERVED1"
bitfld.quad 0x8 10.--11. "Shareability,Shareability" "0,1,2,3"
newline
bitfld.quad 0x8 7.--9. "Cacheability,Cacheability" "0,1,2,3,4,5,6,7"
hexmask.quad.byte 0x8 0.--6. 1. "RESERVED0,RESERVED0"
rgroup.long 0xCFFD0++0x2F
line.long 0x0 "GICR3_PIDR4,GICR3_PIDR4"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x0 4.--7. 1. "SIZE,SIZE"
newline
hexmask.long.byte 0x0 0.--3. 1. "DES_2,DES_2"
line.long 0x4 "GICR3_PIDR5,GICR3_PIDR5"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x4 0.--7. 1. "RESERVED,RESERVED"
line.long 0x8 "GICR3_PIDR6,GICR3_PIDR6"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x8 0.--7. 1. "RESERVED,RESERVED"
line.long 0xC "GICR3_PIDR7,GICR3_PIDR7"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RESERVED"
line.long 0x10 "GICR3_PIDR0,GICR3_PIDR0"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x10 0.--7. 1. "PART_0,PART_0"
line.long 0x14 "GICR3_PIDR1,GICR3_PIDR1"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x14 4.--7. 1. "DES_0,DES_0"
newline
hexmask.long.byte 0x14 0.--3. 1. "PART_1,PART_1"
line.long 0x18 "GICR3_PIDR2,GICR3_PIDR2"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x18 4.--7. 1. "REVISION,REVISION"
newline
bitfld.long 0x18 3. "JEDEC,JEDEC" "0,1"
bitfld.long 0x18 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7"
line.long 0x1C "GICR3_PIDR3,GICR3_PIDR3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,REVAND"
newline
bitfld.long 0x1C 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x1C 0.--2. "CMOD,CMOD" "0,1,2,3,4,5,6,7"
line.long 0x20 "GICR3_CIDR0,GICR3_CIDR0"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,PRMBL_0"
line.long 0x24 "GICR3_CIDR1,GICR3_CIDR1"
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS"
newline
hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,PRMBL_1"
line.long 0x28 "GICR3_CIDR2,GICR3_CIDR2"
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,PRMBL_2"
line.long 0x2C "GICR3_CIDR3,GICR3_CIDR3"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,PRMBL_3"
group.long 0xD0080++0x3
line.long 0x0 "GICR3_IGROUPR0,GICR3_IGROUPR0"
bitfld.long 0x0 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x0 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x0 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x0 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x0 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x0 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x0 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x0 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x0 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x0 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x0 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x0 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x0 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x0 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x0 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x0 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x0 0. "group_status_bit0,group_status_bit0" "0,1"
group.long 0xD0100++0x3
line.long 0x0 "GICR3_ISENABLER0,GICR3_ISENABLER0"
bitfld.long 0x0 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x0 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x0 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x0 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x0 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x0 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x0 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x0 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x0 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x0 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x0 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x0 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x0 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x0 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x0 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x0 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x0 0. "set_enable_bit0,set_enable_bit0" "0,1"
group.long 0xD0180++0x3
line.long 0x0 "GICR3_ICENABLER0,GICR3_ICENABLER0"
bitfld.long 0x0 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x0 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x0 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x0 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x0 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x0 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x0 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x0 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x0 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x0 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x0 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x0 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x0 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x0 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x0 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x0 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x0 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
group.long 0xD0200++0x3
line.long 0x0 "GICR3_ISPENDR0,GICR3_ISPENDR0"
bitfld.long 0x0 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x0 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x0 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x0 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x0 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x0 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x0 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x0 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x0 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x0 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x0 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x0 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x0 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x0 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x0 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x0 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x0 0. "set_pending_bit0,set_pending_bit0" "0,1"
group.long 0xD0280++0x3
line.long 0x0 "GICR3_ICPENDR0,GICR3_ICPENDR0"
bitfld.long 0x0 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x0 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x0 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x0 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x0 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x0 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x0 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x0 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x0 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x0 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x0 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x0 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x0 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x0 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x0 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x0 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x0 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
group.long 0xD0300++0x3
line.long 0x0 "GICR3_ISACTIVER0,GICR3_ISACTIVER0"
bitfld.long 0x0 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x0 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x0 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x0 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x0 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x0 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x0 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x0 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x0 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x0 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x0 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x0 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x0 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x0 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x0 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x0 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x0 0. "set_active_bit0,set_active_bit0" "0,1"
group.long 0xD0380++0x3
line.long 0x0 "GICR3_ICACTIVER0,GICR3_ICACTIVER0"
bitfld.long 0x0 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x0 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x0 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x0 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x0 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x0 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x0 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x0 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x0 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x0 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x0 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x0 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x0 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x0 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x0 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x0 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x0 0. "clear_active_bit0,clear_active_bit0" "0,1"
group.long 0xD0400++0x1F
line.long 0x0 "GICR3_IPRIORITYR0,GICR3_IPRIORITYR0"
hexmask.long.byte 0x0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x0 0.--7. 1. "offset0,offset0"
line.long 0x4 "GICR3_IPRIORITYR1,GICR3_IPRIORITYR1"
hexmask.long.byte 0x4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x4 0.--7. 1. "offset0,offset0"
line.long 0x8 "GICR3_IPRIORITYR2,GICR3_IPRIORITYR2"
hexmask.long.byte 0x8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x8 0.--7. 1. "offset0,offset0"
line.long 0xC "GICR3_IPRIORITYR3,GICR3_IPRIORITYR3"
hexmask.long.byte 0xC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC 0.--7. 1. "offset0,offset0"
line.long 0x10 "GICR3_IPRIORITYR4,GICR3_IPRIORITYR4"
hexmask.long.byte 0x10 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x10 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x10 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x10 0.--7. 1. "offset0,offset0"
line.long 0x14 "GICR3_IPRIORITYR5,GICR3_IPRIORITYR5"
hexmask.long.byte 0x14 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x14 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x14 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x14 0.--7. 1. "offset0,offset0"
line.long 0x18 "GICR3_IPRIORITYR6,GICR3_IPRIORITYR6"
hexmask.long.byte 0x18 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x18 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x18 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x18 0.--7. 1. "offset0,offset0"
line.long 0x1C "GICR3_IPRIORITYR7,GICR3_IPRIORITYR7"
hexmask.long.byte 0x1C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C 0.--7. 1. "offset0,offset0"
rgroup.long 0xD0C00++0x3
line.long 0x0 "GICR3_ICFGR0,GICR3_ICFGR0"
bitfld.long 0x0 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x0 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x0 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x0 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x0 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x0 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x0 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x0 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x0 0.--1. "int_config0,int_config0" "0,1,2,3"
group.long 0xD0C04++0x3
line.long 0x0 "GICR3_ICFGR1,GICR3_ICFGR1"
bitfld.long 0x0 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x0 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x0 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x0 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x0 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x0 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x0 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x0 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x0 0.--1. "int_config0,int_config0" "0,1,2,3"
group.long 0xD0D00++0x3
line.long 0x0 "GICR3_IGRPMODR0,GICR3_IGRPMODR0"
bitfld.long 0x0 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x0 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x0 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x0 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x0 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x0 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x0 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x0 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x0 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x0 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x0 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x0 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x0 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x0 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x0 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x0 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x0 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
group.long 0xD0E00++0x3
line.long 0x0 "GICR3_NSACR,GICR3_NSACR"
bitfld.long 0x0 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x0 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x0 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x0 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x0 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x0 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x0 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x0 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x0 0.--1. "ns_access0,ns_access0" "0,1,2,3"
rgroup.long 0xDC000++0x3
line.long 0x0 "GICR3_MISCSTATUSR,GICR3_MISCSTATUSR"
bitfld.long 0x0 31. "cpu_active,cpu_active" "0,1"
bitfld.long 0x0 30. "wake_request,wake_request" "0,1"
newline
hexmask.long 0x0 5.--29. 1. "RESERVED1,RESERVED1"
bitfld.long 0x0 4. "access_type,access_type" "0,1"
newline
bitfld.long 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x0 2. "EnableGrp1_s,EnableGrp1_s" "0,1"
newline
bitfld.long 0x0 1. "EnableGrp1_ns,EnableGrp1_ns" "0,1"
bitfld.long 0x0 0. "EnableGrp0,EnableGrp0" "0,1"
rgroup.long 0xDC008++0x3
line.long 0x0 "GICR3_IERRVR,GICR3_IERRVR"
bitfld.long 0x0 31. "valid_bit31,valid_bit31" "0,1"
bitfld.long 0x0 30. "valid_bit30,valid_bit30" "0,1"
newline
bitfld.long 0x0 29. "valid_bit29,valid_bit29" "0,1"
bitfld.long 0x0 28. "valid_bit28,valid_bit28" "0,1"
newline
bitfld.long 0x0 27. "valid_bit27,valid_bit27" "0,1"
bitfld.long 0x0 26. "valid_bit26,valid_bit26" "0,1"
newline
bitfld.long 0x0 25. "valid_bit25,valid_bit25" "0,1"
bitfld.long 0x0 24. "valid_bit24,valid_bit24" "0,1"
newline
bitfld.long 0x0 23. "valid_bit23,valid_bit23" "0,1"
bitfld.long 0x0 22. "valid_bit22,valid_bit22" "0,1"
newline
bitfld.long 0x0 21. "valid_bit21,valid_bit21" "0,1"
bitfld.long 0x0 20. "valid_bit20,valid_bit20" "0,1"
newline
bitfld.long 0x0 19. "valid_bit19,valid_bit19" "0,1"
bitfld.long 0x0 18. "valid_bit18,valid_bit18" "0,1"
newline
bitfld.long 0x0 17. "valid_bit17,valid_bit17" "0,1"
bitfld.long 0x0 16. "valid_bit16,valid_bit16" "0,1"
newline
bitfld.long 0x0 15. "valid_bit15,valid_bit15" "0,1"
bitfld.long 0x0 14. "valid_bit14,valid_bit14" "0,1"
newline
bitfld.long 0x0 13. "valid_bit13,valid_bit13" "0,1"
bitfld.long 0x0 12. "valid_bit12,valid_bit12" "0,1"
newline
bitfld.long 0x0 11. "valid_bit11,valid_bit11" "0,1"
bitfld.long 0x0 10. "valid_bit10,valid_bit10" "0,1"
newline
bitfld.long 0x0 9. "valid_bit9,valid_bit9" "0,1"
bitfld.long 0x0 8. "valid_bit8,valid_bit8" "0,1"
newline
bitfld.long 0x0 7. "valid_bit7,valid_bit7" "0,1"
bitfld.long 0x0 6. "valid_bit6,valid_bit6" "0,1"
newline
bitfld.long 0x0 5. "valid_bit5,valid_bit5" "0,1"
bitfld.long 0x0 4. "valid_bit4,valid_bit4" "0,1"
newline
bitfld.long 0x0 3. "valid_bit3,valid_bit3" "0,1"
bitfld.long 0x0 2. "valid_bit2,valid_bit2" "0,1"
newline
bitfld.long 0x0 1. "valid_bit1,valid_bit1" "0,1"
bitfld.long 0x0 0. "valid_bit0,valid_bit0" "0,1"
group.quad 0xDC010++0x7
line.quad 0x0 "GICR3_SGIDR,GICR3_SGIDR"
bitfld.quad 0x0 63. "RESERVED16,RESERVED16" "0,1"
bitfld.quad 0x0 62. "grpmod15,grpmod15" "0,1"
newline
bitfld.quad 0x0 61. "grp15,grp15" "0,1"
bitfld.quad 0x0 60. "nsacr15,nsacr15" "0,1"
newline
bitfld.quad 0x0 59. "RESERVED15,RESERVED15" "0,1"
bitfld.quad 0x0 58. "grpmod14,grpmod14" "0,1"
newline
bitfld.quad 0x0 57. "grp14,grp14" "0,1"
bitfld.quad 0x0 56. "nsacr14,nsacr14" "0,1"
newline
bitfld.quad 0x0 55. "RESERVED13,RESERVED13" "0,1"
bitfld.quad 0x0 54. "grpmod13,grpmod13" "0,1"
newline
bitfld.quad 0x0 53. "grp13,grp13" "0,1"
bitfld.quad 0x0 52. "nsacr13,nsacr13" "0,1"
newline
bitfld.quad 0x0 51. "RESERVED12,RESERVED12" "0,1"
bitfld.quad 0x0 50. "grpmod12,grpmod12" "0,1"
newline
bitfld.quad 0x0 49. "grp12,grp12" "0,1"
bitfld.quad 0x0 48. "nsacr12,nsacr12" "0,1"
newline
bitfld.quad 0x0 47. "RESERVED11,RESERVED11" "0,1"
bitfld.quad 0x0 46. "grpmod11,grpmod11" "0,1"
newline
bitfld.quad 0x0 45. "grp11,grp11" "0,1"
bitfld.quad 0x0 44. "nsacr11,nsacr11" "0,1"
newline
bitfld.quad 0x0 43. "RESERVED10,RESERVED10" "0,1"
bitfld.quad 0x0 42. "grpmod10,grpmod10" "0,1"
newline
bitfld.quad 0x0 41. "grp10,grp10" "0,1"
bitfld.quad 0x0 40. "nsacr10,nsacr10" "0,1"
newline
bitfld.quad 0x0 39. "RESERVED9,RESERVED9" "0,1"
bitfld.quad 0x0 38. "grpmod9,grpmod9" "0,1"
newline
bitfld.quad 0x0 37. "grp9,grp9" "0,1"
bitfld.quad 0x0 36. "nsacr9,nsacr9" "0,1"
newline
bitfld.quad 0x0 35. "RESERVED8,RESERVED8" "0,1"
bitfld.quad 0x0 34. "grpmod8,grpmod8" "0,1"
newline
bitfld.quad 0x0 33. "grp8,grp8" "0,1"
bitfld.quad 0x0 32. "nsacr8,nsacr8" "0,1"
newline
bitfld.quad 0x0 31. "RESERVED7,RESERVED7" "0,1"
bitfld.quad 0x0 30. "grpmod7,grpmod7" "0,1"
newline
bitfld.quad 0x0 29. "grp7,grp7" "0,1"
bitfld.quad 0x0 28. "nsacr7,nsacr7" "0,1"
newline
bitfld.quad 0x0 27. "RESERVED6,RESERVED6" "0,1"
bitfld.quad 0x0 26. "grpmod6,grpmod6" "0,1"
newline
bitfld.quad 0x0 25. "grp6,grp6" "0,1"
bitfld.quad 0x0 24. "nsacr6,nsacr6" "0,1"
newline
bitfld.quad 0x0 23. "RESERVED5,RESERVED5" "0,1"
bitfld.quad 0x0 22. "grpmod5,grpmod5" "0,1"
newline
bitfld.quad 0x0 21. "grp5,grp5" "0,1"
bitfld.quad 0x0 20. "nsacr5,nsacr5" "0,1"
newline
bitfld.quad 0x0 19. "RESERVED4,RESERVED4" "0,1"
bitfld.quad 0x0 18. "grpmod4,grpmod4" "0,1"
newline
bitfld.quad 0x0 17. "grp4,grp4" "0,1"
bitfld.quad 0x0 16. "nsacr4,nsacr4" "0,1"
newline
bitfld.quad 0x0 15. "RESERVED3,RESERVED3" "0,1"
bitfld.quad 0x0 14. "grpmod3,grpmod3" "0,1"
newline
bitfld.quad 0x0 13. "grp3,grp3" "0,1"
bitfld.quad 0x0 12. "nsacr3,nsacr3" "0,1"
newline
bitfld.quad 0x0 11. "RESERVED2,RESERVED2" "0,1"
bitfld.quad 0x0 10. "grpmod2,grpmod2" "0,1"
newline
bitfld.quad 0x0 9. "grp2,grp2" "0,1"
bitfld.quad 0x0 8. "nsacr2,nsacr2" "0,1"
newline
bitfld.quad 0x0 7. "RESERVED1,RESERVED1" "0,1"
bitfld.quad 0x0 6. "grpmod1,grpmod1" "0,1"
newline
bitfld.quad 0x0 5. "grp1,grp1" "0,1"
bitfld.quad 0x0 4. "nsacr1,nsacr1" "0,1"
newline
bitfld.quad 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.quad 0x0 2. "grpmod0,grpmod0" "0,1"
newline
bitfld.quad 0x0 1. "grp0,grp0" "0,1"
bitfld.quad 0x0 0. "nsacr0,nsacr0" "0,1"
rgroup.long 0xDF000++0x7
line.long 0x0 "GICR3_CFGID0,GICR3_CFGID0"
hexmask.long.byte 0x0 28.--31. 1. "Af3width,Af3width"
hexmask.long.byte 0x0 24.--27. 1. "Af2width,Af2width"
newline
hexmask.long.byte 0x0 20.--23. 1. "Af1width,Af1width"
hexmask.long.byte 0x0 16.--19. 1. "Af0width,Af0width"
newline
hexmask.long.byte 0x0 12.--15. 1. "TargetlistWidth,TargetlistWidth"
bitfld.long 0x0 11. "ECCSupport,ECCSupport" "0,1"
newline
bitfld.long 0x0 9.--10. "RESERVED0,RESERVED0" "0,1,2,3"
hexmask.long.word 0x0 0.--8. 1. "PPINumber,PPINumber"
line.long 0x4 "GICR3_CFGID1,GICR3_CFGID1"
hexmask.long.byte 0x4 28.--31. 1. "Version,Version"
hexmask.long.byte 0x4 24.--27. 1. "REVAND,REVAND"
newline
hexmask.long.byte 0x4 20.--23. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x4 16.--19. 1. "PPIsPerProcessor,PPIsPerProcessor"
newline
bitfld.long 0x4 13.--15. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 12. "DirectUpstream,DirectUpstream" "0,1"
newline
hexmask.long.byte 0x4 4.--11. 1. "NumCPUs,NumCPUs"
hexmask.long.byte 0x4 0.--3. 1. "NumARE0CPUs,NumARE0CPUs"
group.long 0xE0000++0x3
line.long 0x0 "GICDA_CTLR,GICDA_CTLR"
rbitfld.long 0x0 31. "RWP,RWP" "0,1"
hexmask.long.tbyte 0x0 8.--30. 1. "RESERVED1,RESERVED1"
newline
bitfld.long 0x0 7. "E1NWF,E1NWF" "0,1"
rbitfld.long 0x0 6. "DS,DS" "0,1"
newline
bitfld.long 0x0 5. "ARE_NS,ARE_NS" "0,1"
bitfld.long 0x0 4. "ARE_S,ARE_S" "0,1"
newline
bitfld.long 0x0 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x0 2. "EnableGrp1_s,EnableGrp1_s" "0,1"
newline
bitfld.long 0x0 1. "EnableGrp1_ns,EnableGrp1_ns" "0,1"
bitfld.long 0x0 0. "EnableGrp0,EnableGrp0" "0,1"
rgroup.long 0xE0004++0x7
line.long 0x0 "GICDA_TYPER,GICDA_TYPER"
hexmask.long.byte 0x0 26.--31. 1. "RESERVED1,RESERVED1"
bitfld.long 0x0 25. "No1N,No1N" "0,1"
newline
bitfld.long 0x0 24. "A3V,A3V" "0,1"
hexmask.long.byte 0x0 19.--23. 1. "IDbits,IDbits"
newline
bitfld.long 0x0 18. "DVIS,DVIS" "0,1"
bitfld.long 0x0 17. "LPIS,LPIS" "0,1"
newline
bitfld.long 0x0 16. "MBIS,MBIS" "0,1"
hexmask.long.byte 0x0 11.--15. 1. "LSPI,LSPI"
newline
bitfld.long 0x0 10. "SecurityExtn,SecurityExtn" "0,1"
bitfld.long 0x0 8.--9. "RESERVED0,RESERVED0" "0,1,2,3"
newline
bitfld.long 0x0 5.--7. "CPUNumber,CPUNumber" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 0.--4. 1. "ITLinesNumber,ITLinesNumber"
line.long 0x4 "GICDA_IIDR,GICDA_IIDR"
hexmask.long.byte 0x4 24.--31. 1. "ProductID,ProductID"
hexmask.long.byte 0x4 20.--23. 1. "RESERVED0,RESERVED0"
newline
hexmask.long.byte 0x4 16.--19. 1. "Variant,Variant"
hexmask.long.byte 0x4 12.--15. 1. "Revision,Revision"
newline
hexmask.long.word 0x4 0.--11. 1. "Implementer,Implementer"
group.long 0xE0020++0x7
line.long 0x0 "GICDA_FCTLR,GICDA_FCTLR"
hexmask.long.byte 0x0 27.--31. 1. "RESERVED4,RESERVED4"
bitfld.long 0x0 26. "POS,POS" "0,1"
newline
bitfld.long 0x0 25. "QDENY,QDENY" "0,1"
bitfld.long 0x0 22.--24. "RESERVED3,RESERVED3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 21. "DCC,DCC" "0,1"
bitfld.long 0x0 18.--20. "RESERVED2,RESERVED2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 16.--17. "NSACR,NSACR" "0,1,2,3"
bitfld.long 0x0 13.--15. "RESERVED1,RESERVED1" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 4.--12. 1. "CGO,CGO"
bitfld.long 0x0 1.--3. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "SIP,SIP" "0,1"
line.long 0x4 "GICDA_SAC,GICDA_SAC"
hexmask.long 0x4 3.--31. 1. "RESERVED0,RESERVED0"
bitfld.long 0x4 2. "GICPNS,GICPNS" "0,1"
newline
bitfld.long 0x4 1. "GICTNS,GICTNS" "0,1"
bitfld.long 0x4 0. "DSL,DSL" "0,1"
wgroup.long 0xE0040++0x3
line.long 0x0 "GICDA_SETSPI_NSR,GICDA_SETSPI_NSR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
wgroup.long 0xE0048++0x3
line.long 0x0 "GICDA_CLRSPI_NSR,GICDA_CLRSPI_NSR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
wgroup.long 0xE0050++0x3
line.long 0x0 "GICDA_SETSPI_SR,GICDA_SETSPI_SR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
wgroup.long 0xE0058++0x3
line.long 0x0 "GICDA_CLRSPI_SR,GICDA_CLRSPI_SR"
hexmask.long.tbyte 0x0 10.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.word 0x0 0.--9. 1. "ID,ID"
group.long 0xE0084++0x43
line.long 0x0 "GICDA_IGROUPR1,GICDA_IGROUPR1"
bitfld.long 0x0 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x0 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x0 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x0 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x0 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x0 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x0 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x0 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x0 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x0 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x0 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x0 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x0 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x0 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x0 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x0 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x0 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x4 "GICDA_IGROUPR2,GICDA_IGROUPR2"
bitfld.long 0x4 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x4 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x4 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x4 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x4 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x4 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x4 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x4 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x4 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x4 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x4 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x4 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x4 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x4 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x4 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x4 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x4 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x4 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x4 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x4 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x4 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x4 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x4 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x4 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x4 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x4 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x4 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x4 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x4 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x4 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x4 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x4 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x8 "GICDA_IGROUPR3,GICDA_IGROUPR3"
bitfld.long 0x8 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x8 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x8 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x8 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x8 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x8 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x8 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x8 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x8 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x8 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x8 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x8 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x8 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x8 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x8 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x8 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x8 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x8 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x8 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x8 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x8 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x8 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x8 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x8 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x8 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x8 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x8 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x8 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x8 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x8 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x8 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x8 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0xC "GICDA_IGROUPR4,GICDA_IGROUPR4"
bitfld.long 0xC 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0xC 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0xC 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0xC 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0xC 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0xC 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0xC 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0xC 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0xC 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0xC 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0xC 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0xC 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0xC 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0xC 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0xC 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0xC 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0xC 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0xC 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0xC 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0xC 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0xC 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0xC 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0xC 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0xC 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0xC 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0xC 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0xC 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0xC 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0xC 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0xC 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0xC 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0xC 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x10 "GICDA_IGROUPR5,GICDA_IGROUPR5"
bitfld.long 0x10 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x10 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x10 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x10 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x10 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x10 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x10 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x10 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x10 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x10 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x10 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x10 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x10 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x10 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x10 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x10 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x10 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x10 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x10 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x10 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x10 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x10 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x10 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x10 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x10 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x10 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x10 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x10 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x10 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x10 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x10 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x10 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x14 "GICDA_IGROUPR6,GICDA_IGROUPR6"
bitfld.long 0x14 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x14 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x14 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x14 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x14 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x14 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x14 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x14 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x14 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x14 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x14 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x14 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x14 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x14 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x14 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x14 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x14 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x14 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x14 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x14 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x14 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x14 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x14 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x14 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x14 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x14 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x14 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x14 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x14 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x14 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x14 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x14 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x18 "GICDA_IGROUPR7,GICDA_IGROUPR7"
bitfld.long 0x18 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x18 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x18 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x18 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x18 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x18 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x18 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x18 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x18 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x18 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x18 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x18 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x18 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x18 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x18 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x18 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x18 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x18 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x18 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x18 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x18 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x18 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x18 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x18 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x18 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x18 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x18 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x18 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x18 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x18 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x18 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x18 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x1C "GICDA_IGROUPR8,GICDA_IGROUPR8"
bitfld.long 0x1C 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x1C 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x1C 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x1C 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x1C 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x1C 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x1C 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x1C 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x1C 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x1C 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x1C 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x1C 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x1C 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x1C 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x1C 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x1C 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x1C 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x1C 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x1C 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x1C 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x1C 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x1C 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x1C 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x1C 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x1C 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x1C 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x1C 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x1C 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x1C 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x1C 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x1C 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x1C 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x20 "GICDA_IGROUPR9,GICDA_IGROUPR9"
bitfld.long 0x20 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x20 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x20 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x20 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x20 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x20 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x20 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x20 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x20 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x20 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x20 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x20 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x20 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x20 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x20 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x20 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x20 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x20 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x20 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x20 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x20 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x20 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x20 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x20 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x20 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x20 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x20 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x20 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x20 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x20 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x20 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x20 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x24 "GICDA_IGROUPR10,GICDA_IGROUPR10"
bitfld.long 0x24 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x24 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x24 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x24 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x24 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x24 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x24 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x24 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x24 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x24 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x24 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x24 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x24 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x24 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x24 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x24 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x24 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x24 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x24 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x24 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x24 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x24 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x24 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x24 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x24 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x24 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x24 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x24 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x24 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x24 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x24 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x24 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x28 "GICDA_IGROUPR11,GICDA_IGROUPR11"
bitfld.long 0x28 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x28 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x28 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x28 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x28 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x28 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x28 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x28 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x28 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x28 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x28 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x28 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x28 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x28 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x28 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x28 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x28 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x28 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x28 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x28 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x28 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x28 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x28 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x28 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x28 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x28 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x28 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x28 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x28 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x28 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x28 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x28 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x2C "GICDA_IGROUPR12,GICDA_IGROUPR12"
bitfld.long 0x2C 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x2C 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x2C 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x2C 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x2C 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x2C 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x2C 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x2C 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x2C 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x2C 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x2C 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x2C 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x2C 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x2C 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x2C 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x2C 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x2C 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x2C 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x2C 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x2C 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x2C 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x2C 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x2C 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x2C 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x2C 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x2C 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x2C 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x2C 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x2C 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x2C 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x2C 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x2C 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x30 "GICDA_IGROUPR13,GICDA_IGROUPR13"
bitfld.long 0x30 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x30 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x30 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x30 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x30 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x30 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x30 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x30 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x30 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x30 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x30 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x30 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x30 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x30 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x30 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x30 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x30 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x30 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x30 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x30 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x30 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x30 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x30 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x30 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x30 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x30 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x30 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x30 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x30 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x30 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x30 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x30 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x34 "GICDA_IGROUPR14,GICDA_IGROUPR14"
bitfld.long 0x34 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x34 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x34 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x34 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x34 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x34 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x34 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x34 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x34 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x34 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x34 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x34 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x34 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x34 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x34 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x34 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x34 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x34 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x34 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x34 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x34 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x34 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x34 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x34 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x34 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x34 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x34 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x34 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x34 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x34 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x34 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x34 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x38 "GICDA_IGROUPR15,GICDA_IGROUPR15"
bitfld.long 0x38 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x38 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x38 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x38 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x38 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x38 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x38 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x38 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x38 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x38 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x38 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x38 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x38 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x38 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x38 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x38 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x38 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x38 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x38 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x38 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x38 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x38 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x38 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x38 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x38 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x38 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x38 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x38 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x38 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x38 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x38 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x38 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x3C "GICDA_IGROUPR16,GICDA_IGROUPR16"
bitfld.long 0x3C 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x3C 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x3C 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x3C 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x3C 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x3C 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x3C 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x3C 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x3C 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x3C 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x3C 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x3C 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x3C 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x3C 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x3C 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x3C 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x3C 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x3C 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x3C 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x3C 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x3C 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x3C 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x3C 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x3C 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x3C 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x3C 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x3C 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x3C 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x3C 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x3C 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x3C 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x3C 0. "group_status_bit0,group_status_bit0" "0,1"
line.long 0x40 "GICDA_IGROUPR17,GICDA_IGROUPR17"
bitfld.long 0x40 31. "group_status_bit31,group_status_bit31" "0,1"
bitfld.long 0x40 30. "group_status_bit30,group_status_bit30" "0,1"
newline
bitfld.long 0x40 29. "group_status_bit29,group_status_bit29" "0,1"
bitfld.long 0x40 28. "group_status_bit28,group_status_bit28" "0,1"
newline
bitfld.long 0x40 27. "group_status_bit27,group_status_bit27" "0,1"
bitfld.long 0x40 26. "group_status_bit26,group_status_bit26" "0,1"
newline
bitfld.long 0x40 25. "group_status_bit25,group_status_bit25" "0,1"
bitfld.long 0x40 24. "group_status_bit24,group_status_bit24" "0,1"
newline
bitfld.long 0x40 23. "group_status_bit23,group_status_bit23" "0,1"
bitfld.long 0x40 22. "group_status_bit22,group_status_bit22" "0,1"
newline
bitfld.long 0x40 21. "group_status_bit21,group_status_bit21" "0,1"
bitfld.long 0x40 20. "group_status_bit20,group_status_bit20" "0,1"
newline
bitfld.long 0x40 19. "group_status_bit19,group_status_bit19" "0,1"
bitfld.long 0x40 18. "group_status_bit18,group_status_bit18" "0,1"
newline
bitfld.long 0x40 17. "group_status_bit17,group_status_bit17" "0,1"
bitfld.long 0x40 16. "group_status_bit16,group_status_bit16" "0,1"
newline
bitfld.long 0x40 15. "group_status_bit15,group_status_bit15" "0,1"
bitfld.long 0x40 14. "group_status_bit14,group_status_bit14" "0,1"
newline
bitfld.long 0x40 13. "group_status_bit13,group_status_bit13" "0,1"
bitfld.long 0x40 12. "group_status_bit12,group_status_bit12" "0,1"
newline
bitfld.long 0x40 11. "group_status_bit11,group_status_bit11" "0,1"
bitfld.long 0x40 10. "group_status_bit10,group_status_bit10" "0,1"
newline
bitfld.long 0x40 9. "group_status_bit9,group_status_bit9" "0,1"
bitfld.long 0x40 8. "group_status_bit8,group_status_bit8" "0,1"
newline
bitfld.long 0x40 7. "group_status_bit7,group_status_bit7" "0,1"
bitfld.long 0x40 6. "group_status_bit6,group_status_bit6" "0,1"
newline
bitfld.long 0x40 5. "group_status_bit5,group_status_bit5" "0,1"
bitfld.long 0x40 4. "group_status_bit4,group_status_bit4" "0,1"
newline
bitfld.long 0x40 3. "group_status_bit3,group_status_bit3" "0,1"
bitfld.long 0x40 2. "group_status_bit2,group_status_bit2" "0,1"
newline
bitfld.long 0x40 1. "group_status_bit1,group_status_bit1" "0,1"
bitfld.long 0x40 0. "group_status_bit0,group_status_bit0" "0,1"
group.long 0xE0104++0x43
line.long 0x0 "GICDA_ISENABLER1,GICDA_ISENABLER1"
bitfld.long 0x0 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x0 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x0 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x0 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x0 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x0 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x0 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x0 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x0 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x0 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x0 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x0 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x0 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x0 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x0 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x0 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x0 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x4 "GICDA_ISENABLER2,GICDA_ISENABLER2"
bitfld.long 0x4 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x4 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x4 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x4 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x4 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x4 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x4 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x4 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x4 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x4 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x4 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x4 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x4 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x4 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x4 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x4 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x4 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x4 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x4 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x4 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x4 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x4 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x4 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x4 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x4 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x4 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x4 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x4 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x4 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x4 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x4 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x4 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x8 "GICDA_ISENABLER3,GICDA_ISENABLER3"
bitfld.long 0x8 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x8 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x8 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x8 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x8 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x8 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x8 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x8 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x8 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x8 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x8 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x8 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x8 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x8 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x8 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x8 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x8 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x8 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x8 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x8 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x8 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x8 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x8 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x8 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x8 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x8 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x8 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x8 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x8 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x8 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x8 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x8 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0xC "GICDA_ISENABLER4,GICDA_ISENABLER4"
bitfld.long 0xC 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0xC 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0xC 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0xC 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0xC 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0xC 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0xC 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0xC 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0xC 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0xC 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0xC 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0xC 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0xC 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0xC 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0xC 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0xC 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0xC 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0xC 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0xC 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0xC 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0xC 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0xC 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0xC 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0xC 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0xC 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0xC 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0xC 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0xC 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0xC 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0xC 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0xC 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0xC 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x10 "GICDA_ISENABLER5,GICDA_ISENABLER5"
bitfld.long 0x10 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x10 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x10 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x10 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x10 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x10 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x10 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x10 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x10 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x10 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x10 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x10 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x10 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x10 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x10 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x10 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x10 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x10 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x10 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x10 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x10 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x10 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x10 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x10 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x10 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x10 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x10 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x10 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x10 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x10 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x10 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x10 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x14 "GICDA_ISENABLER6,GICDA_ISENABLER6"
bitfld.long 0x14 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x14 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x14 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x14 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x14 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x14 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x14 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x14 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x14 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x14 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x14 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x14 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x14 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x14 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x14 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x14 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x14 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x14 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x14 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x14 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x14 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x14 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x14 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x14 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x14 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x14 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x14 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x14 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x14 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x14 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x14 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x14 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x18 "GICDA_ISENABLER7,GICDA_ISENABLER7"
bitfld.long 0x18 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x18 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x18 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x18 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x18 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x18 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x18 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x18 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x18 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x18 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x18 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x18 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x18 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x18 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x18 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x18 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x18 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x18 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x18 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x18 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x18 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x18 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x18 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x18 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x18 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x18 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x18 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x18 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x18 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x18 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x18 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x18 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x1C "GICDA_ISENABLER8,GICDA_ISENABLER8"
bitfld.long 0x1C 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x1C 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x1C 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x1C 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x1C 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x1C 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x1C 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x1C 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x1C 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x1C 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x1C 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x1C 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x1C 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x1C 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x1C 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x1C 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x1C 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x1C 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x1C 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x1C 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x1C 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x1C 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x1C 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x1C 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x1C 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x1C 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x1C 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x1C 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x1C 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x1C 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x1C 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x1C 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x20 "GICDA_ISENABLER9,GICDA_ISENABLER9"
bitfld.long 0x20 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x20 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x20 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x20 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x20 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x20 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x20 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x20 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x20 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x20 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x20 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x20 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x20 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x20 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x20 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x20 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x20 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x20 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x20 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x20 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x20 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x20 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x20 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x20 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x20 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x20 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x20 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x20 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x20 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x20 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x20 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x20 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x24 "GICDA_ISENABLER10,GICDA_ISENABLER10"
bitfld.long 0x24 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x24 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x24 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x24 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x24 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x24 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x24 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x24 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x24 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x24 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x24 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x24 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x24 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x24 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x24 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x24 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x24 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x24 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x24 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x24 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x24 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x24 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x24 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x24 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x24 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x24 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x24 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x24 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x24 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x24 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x24 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x24 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x28 "GICDA_ISENABLER11,GICDA_ISENABLER11"
bitfld.long 0x28 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x28 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x28 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x28 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x28 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x28 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x28 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x28 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x28 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x28 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x28 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x28 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x28 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x28 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x28 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x28 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x28 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x28 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x28 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x28 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x28 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x28 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x28 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x28 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x28 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x28 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x28 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x28 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x28 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x28 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x28 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x28 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x2C "GICDA_ISENABLER12,GICDA_ISENABLER12"
bitfld.long 0x2C 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x2C 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x2C 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x2C 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x2C 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x2C 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x2C 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x2C 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x2C 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x2C 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x2C 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x2C 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x2C 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x2C 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x2C 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x2C 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x2C 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x2C 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x2C 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x2C 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x2C 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x2C 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x2C 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x2C 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x2C 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x2C 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x2C 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x2C 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x2C 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x2C 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x2C 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x2C 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x30 "GICDA_ISENABLER13,GICDA_ISENABLER13"
bitfld.long 0x30 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x30 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x30 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x30 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x30 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x30 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x30 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x30 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x30 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x30 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x30 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x30 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x30 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x30 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x30 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x30 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x30 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x30 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x30 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x30 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x30 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x30 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x30 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x30 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x30 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x30 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x30 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x30 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x30 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x30 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x30 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x30 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x34 "GICDA_ISENABLER14,GICDA_ISENABLER14"
bitfld.long 0x34 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x34 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x34 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x34 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x34 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x34 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x34 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x34 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x34 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x34 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x34 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x34 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x34 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x34 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x34 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x34 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x34 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x34 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x34 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x34 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x34 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x34 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x34 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x34 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x34 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x34 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x34 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x34 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x34 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x34 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x34 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x34 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x38 "GICDA_ISENABLER15,GICDA_ISENABLER15"
bitfld.long 0x38 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x38 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x38 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x38 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x38 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x38 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x38 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x38 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x38 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x38 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x38 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x38 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x38 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x38 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x38 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x38 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x38 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x38 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x38 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x38 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x38 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x38 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x38 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x38 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x38 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x38 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x38 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x38 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x38 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x38 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x38 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x38 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x3C "GICDA_ISENABLER16,GICDA_ISENABLER16"
bitfld.long 0x3C 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x3C 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x3C 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x3C 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x3C 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x3C 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x3C 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x3C 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x3C 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x3C 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x3C 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x3C 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x3C 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x3C 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x3C 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x3C 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x3C 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x3C 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x3C 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x3C 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x3C 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x3C 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x3C 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x3C 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x3C 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x3C 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x3C 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x3C 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x3C 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x3C 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x3C 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x3C 0. "set_enable_bit0,set_enable_bit0" "0,1"
line.long 0x40 "GICDA_ISENABLER17,GICDA_ISENABLER17"
bitfld.long 0x40 31. "set_enable_bit31,set_enable_bit31" "0,1"
bitfld.long 0x40 30. "set_enable_bit30,set_enable_bit30" "0,1"
newline
bitfld.long 0x40 29. "set_enable_bit29,set_enable_bit29" "0,1"
bitfld.long 0x40 28. "set_enable_bit28,set_enable_bit28" "0,1"
newline
bitfld.long 0x40 27. "set_enable_bit27,set_enable_bit27" "0,1"
bitfld.long 0x40 26. "set_enable_bit26,set_enable_bit26" "0,1"
newline
bitfld.long 0x40 25. "set_enable_bit25,set_enable_bit25" "0,1"
bitfld.long 0x40 24. "set_enable_bit24,set_enable_bit24" "0,1"
newline
bitfld.long 0x40 23. "set_enable_bit23,set_enable_bit23" "0,1"
bitfld.long 0x40 22. "set_enable_bit22,set_enable_bit22" "0,1"
newline
bitfld.long 0x40 21. "set_enable_bit21,set_enable_bit21" "0,1"
bitfld.long 0x40 20. "set_enable_bit20,set_enable_bit20" "0,1"
newline
bitfld.long 0x40 19. "set_enable_bit19,set_enable_bit19" "0,1"
bitfld.long 0x40 18. "set_enable_bit18,set_enable_bit18" "0,1"
newline
bitfld.long 0x40 17. "set_enable_bit17,set_enable_bit17" "0,1"
bitfld.long 0x40 16. "set_enable_bit16,set_enable_bit16" "0,1"
newline
bitfld.long 0x40 15. "set_enable_bit15,set_enable_bit15" "0,1"
bitfld.long 0x40 14. "set_enable_bit14,set_enable_bit14" "0,1"
newline
bitfld.long 0x40 13. "set_enable_bit13,set_enable_bit13" "0,1"
bitfld.long 0x40 12. "set_enable_bit12,set_enable_bit12" "0,1"
newline
bitfld.long 0x40 11. "set_enable_bit11,set_enable_bit11" "0,1"
bitfld.long 0x40 10. "set_enable_bit10,set_enable_bit10" "0,1"
newline
bitfld.long 0x40 9. "set_enable_bit9,set_enable_bit9" "0,1"
bitfld.long 0x40 8. "set_enable_bit8,set_enable_bit8" "0,1"
newline
bitfld.long 0x40 7. "set_enable_bit7,set_enable_bit7" "0,1"
bitfld.long 0x40 6. "set_enable_bit6,set_enable_bit6" "0,1"
newline
bitfld.long 0x40 5. "set_enable_bit5,set_enable_bit5" "0,1"
bitfld.long 0x40 4. "set_enable_bit4,set_enable_bit4" "0,1"
newline
bitfld.long 0x40 3. "set_enable_bit3,set_enable_bit3" "0,1"
bitfld.long 0x40 2. "set_enable_bit2,set_enable_bit2" "0,1"
newline
bitfld.long 0x40 1. "set_enable_bit1,set_enable_bit1" "0,1"
bitfld.long 0x40 0. "set_enable_bit0,set_enable_bit0" "0,1"
group.long 0xE0184++0x43
line.long 0x0 "GICDA_ICENABLER1,GICDA_ICENABLER1"
bitfld.long 0x0 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x0 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x0 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x0 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x0 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x0 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x0 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x0 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x0 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x0 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x0 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x0 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x0 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x0 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x0 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x0 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x0 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x4 "GICDA_ICENABLER2,GICDA_ICENABLER2"
bitfld.long 0x4 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x4 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x4 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x4 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x4 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x4 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x4 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x4 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x4 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x4 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x4 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x4 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x4 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x4 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x4 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x4 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x4 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x4 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x4 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x4 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x4 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x4 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x4 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x4 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x4 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x4 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x4 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x4 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x4 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x4 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x4 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x4 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x8 "GICDA_ICENABLER3,GICDA_ICENABLER3"
bitfld.long 0x8 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x8 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x8 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x8 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x8 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x8 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x8 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x8 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x8 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x8 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x8 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x8 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x8 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x8 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x8 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x8 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x8 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x8 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x8 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x8 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x8 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x8 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x8 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x8 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x8 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x8 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x8 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x8 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x8 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x8 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x8 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x8 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0xC "GICDA_ICENABLER4,GICDA_ICENABLER4"
bitfld.long 0xC 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0xC 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0xC 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0xC 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0xC 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0xC 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0xC 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0xC 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0xC 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0xC 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0xC 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0xC 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0xC 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0xC 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0xC 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0xC 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0xC 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0xC 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0xC 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0xC 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0xC 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0xC 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0xC 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0xC 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0xC 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0xC 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0xC 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0xC 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0xC 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0xC 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0xC 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0xC 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x10 "GICDA_ICENABLER5,GICDA_ICENABLER5"
bitfld.long 0x10 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x10 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x10 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x10 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x10 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x10 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x10 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x10 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x10 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x10 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x10 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x10 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x10 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x10 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x10 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x10 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x10 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x10 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x10 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x10 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x10 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x10 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x10 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x10 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x10 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x10 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x10 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x10 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x10 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x10 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x10 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x10 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x14 "GICDA_ICENABLER6,GICDA_ICENABLER6"
bitfld.long 0x14 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x14 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x14 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x14 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x14 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x14 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x14 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x14 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x14 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x14 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x14 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x14 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x14 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x14 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x14 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x14 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x14 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x14 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x14 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x14 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x14 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x14 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x14 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x14 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x14 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x14 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x14 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x14 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x14 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x14 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x14 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x14 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x18 "GICDA_ICENABLER7,GICDA_ICENABLER7"
bitfld.long 0x18 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x18 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x18 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x18 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x18 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x18 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x18 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x18 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x18 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x18 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x18 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x18 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x18 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x18 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x18 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x18 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x18 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x18 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x18 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x18 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x18 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x18 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x18 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x18 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x18 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x18 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x18 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x18 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x18 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x18 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x18 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x18 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x1C "GICDA_ICENABLER8,GICDA_ICENABLER8"
bitfld.long 0x1C 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x1C 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x1C 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x1C 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x1C 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x1C 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x1C 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x1C 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x1C 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x1C 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x1C 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x1C 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x1C 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x1C 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x1C 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x1C 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x1C 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x1C 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x1C 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x1C 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x1C 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x1C 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x1C 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x1C 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x1C 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x1C 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x1C 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x1C 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x1C 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x1C 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x1C 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x1C 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x20 "GICDA_ICENABLER9,GICDA_ICENABLER9"
bitfld.long 0x20 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x20 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x20 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x20 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x20 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x20 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x20 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x20 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x20 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x20 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x20 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x20 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x20 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x20 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x20 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x20 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x20 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x20 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x20 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x20 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x20 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x20 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x20 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x20 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x20 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x20 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x20 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x20 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x20 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x20 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x20 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x20 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x24 "GICDA_ICENABLER10,GICDA_ICENABLER10"
bitfld.long 0x24 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x24 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x24 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x24 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x24 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x24 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x24 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x24 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x24 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x24 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x24 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x24 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x24 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x24 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x24 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x24 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x24 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x24 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x24 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x24 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x24 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x24 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x24 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x24 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x24 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x24 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x24 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x24 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x24 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x24 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x24 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x24 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x28 "GICDA_ICENABLER11,GICDA_ICENABLER11"
bitfld.long 0x28 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x28 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x28 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x28 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x28 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x28 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x28 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x28 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x28 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x28 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x28 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x28 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x28 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x28 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x28 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x28 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x28 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x28 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x28 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x28 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x28 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x28 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x28 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x28 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x28 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x28 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x28 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x28 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x28 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x28 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x28 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x28 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x2C "GICDA_ICENABLER12,GICDA_ICENABLER12"
bitfld.long 0x2C 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x2C 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x2C 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x2C 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x2C 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x2C 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x2C 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x2C 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x2C 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x2C 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x2C 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x2C 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x2C 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x2C 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x2C 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x2C 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x2C 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x2C 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x2C 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x2C 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x2C 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x2C 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x2C 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x2C 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x2C 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x2C 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x2C 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x2C 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x2C 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x2C 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x2C 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x2C 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x30 "GICDA_ICENABLER13,GICDA_ICENABLER13"
bitfld.long 0x30 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x30 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x30 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x30 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x30 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x30 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x30 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x30 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x30 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x30 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x30 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x30 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x30 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x30 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x30 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x30 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x30 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x30 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x30 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x30 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x30 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x30 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x30 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x30 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x30 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x30 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x30 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x30 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x30 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x30 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x30 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x30 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x34 "GICDA_ICENABLER14,GICDA_ICENABLER14"
bitfld.long 0x34 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x34 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x34 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x34 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x34 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x34 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x34 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x34 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x34 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x34 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x34 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x34 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x34 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x34 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x34 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x34 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x34 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x34 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x34 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x34 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x34 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x34 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x34 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x34 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x34 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x34 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x34 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x34 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x34 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x34 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x34 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x34 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x38 "GICDA_ICENABLER15,GICDA_ICENABLER15"
bitfld.long 0x38 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x38 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x38 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x38 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x38 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x38 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x38 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x38 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x38 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x38 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x38 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x38 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x38 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x38 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x38 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x38 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x38 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x38 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x38 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x38 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x38 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x38 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x38 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x38 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x38 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x38 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x38 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x38 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x38 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x38 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x38 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x38 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x3C "GICDA_ICENABLER16,GICDA_ICENABLER16"
bitfld.long 0x3C 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x3C 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x3C 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x3C 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x3C 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x3C 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x3C 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x3C 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x3C 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x3C 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x3C 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x3C 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x3C 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x3C 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x3C 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x3C 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x3C 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x3C 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x3C 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x3C 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x3C 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x3C 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x3C 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x3C 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x3C 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x3C 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x3C 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x3C 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x3C 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x3C 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x3C 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x3C 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
line.long 0x40 "GICDA_ICENABLER17,GICDA_ICENABLER17"
bitfld.long 0x40 31. "clear_enable_bit31,clear_enable_bit31" "0,1"
bitfld.long 0x40 30. "clear_enable_bit30,clear_enable_bit30" "0,1"
newline
bitfld.long 0x40 29. "clear_enable_bit29,clear_enable_bit29" "0,1"
bitfld.long 0x40 28. "clear_enable_bit28,clear_enable_bit28" "0,1"
newline
bitfld.long 0x40 27. "clear_enable_bit27,clear_enable_bit27" "0,1"
bitfld.long 0x40 26. "clear_enable_bit26,clear_enable_bit26" "0,1"
newline
bitfld.long 0x40 25. "clear_enable_bit25,clear_enable_bit25" "0,1"
bitfld.long 0x40 24. "clear_enable_bit24,clear_enable_bit24" "0,1"
newline
bitfld.long 0x40 23. "clear_enable_bit23,clear_enable_bit23" "0,1"
bitfld.long 0x40 22. "clear_enable_bit22,clear_enable_bit22" "0,1"
newline
bitfld.long 0x40 21. "clear_enable_bit21,clear_enable_bit21" "0,1"
bitfld.long 0x40 20. "clear_enable_bit20,clear_enable_bit20" "0,1"
newline
bitfld.long 0x40 19. "clear_enable_bit19,clear_enable_bit19" "0,1"
bitfld.long 0x40 18. "clear_enable_bit18,clear_enable_bit18" "0,1"
newline
bitfld.long 0x40 17. "clear_enable_bit17,clear_enable_bit17" "0,1"
bitfld.long 0x40 16. "clear_enable_bit16,clear_enable_bit16" "0,1"
newline
bitfld.long 0x40 15. "clear_enable_bit15,clear_enable_bit15" "0,1"
bitfld.long 0x40 14. "clear_enable_bit14,clear_enable_bit14" "0,1"
newline
bitfld.long 0x40 13. "clear_enable_bit13,clear_enable_bit13" "0,1"
bitfld.long 0x40 12. "clear_enable_bit12,clear_enable_bit12" "0,1"
newline
bitfld.long 0x40 11. "clear_enable_bit11,clear_enable_bit11" "0,1"
bitfld.long 0x40 10. "clear_enable_bit10,clear_enable_bit10" "0,1"
newline
bitfld.long 0x40 9. "clear_enable_bit9,clear_enable_bit9" "0,1"
bitfld.long 0x40 8. "clear_enable_bit8,clear_enable_bit8" "0,1"
newline
bitfld.long 0x40 7. "clear_enable_bit7,clear_enable_bit7" "0,1"
bitfld.long 0x40 6. "clear_enable_bit6,clear_enable_bit6" "0,1"
newline
bitfld.long 0x40 5. "clear_enable_bit5,clear_enable_bit5" "0,1"
bitfld.long 0x40 4. "clear_enable_bit4,clear_enable_bit4" "0,1"
newline
bitfld.long 0x40 3. "clear_enable_bit3,clear_enable_bit3" "0,1"
bitfld.long 0x40 2. "clear_enable_bit2,clear_enable_bit2" "0,1"
newline
bitfld.long 0x40 1. "clear_enable_bit1,clear_enable_bit1" "0,1"
bitfld.long 0x40 0. "clear_enable_bit0,clear_enable_bit0" "0,1"
group.long 0xE0204++0x43
line.long 0x0 "GICDA_ISPENDR1,GICDA_ISPENDR1"
bitfld.long 0x0 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x0 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x0 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x0 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x0 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x0 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x0 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x0 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x0 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x0 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x0 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x0 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x0 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x0 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x0 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x0 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x0 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x4 "GICDA_ISPENDR2,GICDA_ISPENDR2"
bitfld.long 0x4 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x4 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x4 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x4 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x4 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x4 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x4 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x4 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x4 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x4 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x4 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x4 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x4 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x4 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x4 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x4 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x4 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x4 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x4 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x4 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x4 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x4 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x4 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x4 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x4 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x4 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x4 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x4 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x4 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x4 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x4 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x4 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x8 "GICDA_ISPENDR3,GICDA_ISPENDR3"
bitfld.long 0x8 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x8 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x8 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x8 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x8 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x8 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x8 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x8 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x8 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x8 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x8 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x8 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x8 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x8 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x8 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x8 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x8 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x8 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x8 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x8 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x8 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x8 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x8 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x8 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x8 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x8 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x8 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x8 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x8 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x8 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x8 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x8 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0xC "GICDA_ISPENDR4,GICDA_ISPENDR4"
bitfld.long 0xC 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0xC 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0xC 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0xC 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0xC 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0xC 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0xC 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0xC 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0xC 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0xC 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0xC 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0xC 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0xC 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0xC 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0xC 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0xC 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0xC 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0xC 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0xC 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0xC 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0xC 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0xC 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0xC 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0xC 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0xC 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0xC 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0xC 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0xC 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0xC 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0xC 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0xC 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0xC 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x10 "GICDA_ISPENDR5,GICDA_ISPENDR5"
bitfld.long 0x10 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x10 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x10 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x10 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x10 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x10 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x10 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x10 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x10 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x10 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x10 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x10 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x10 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x10 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x10 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x10 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x10 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x10 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x10 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x10 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x10 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x10 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x10 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x10 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x10 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x10 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x10 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x10 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x10 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x10 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x10 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x10 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x14 "GICDA_ISPENDR6,GICDA_ISPENDR6"
bitfld.long 0x14 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x14 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x14 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x14 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x14 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x14 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x14 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x14 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x14 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x14 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x14 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x14 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x14 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x14 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x14 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x14 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x14 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x14 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x14 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x14 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x14 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x14 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x14 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x14 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x14 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x14 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x14 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x14 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x14 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x14 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x14 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x14 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x18 "GICDA_ISPENDR7,GICDA_ISPENDR7"
bitfld.long 0x18 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x18 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x18 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x18 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x18 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x18 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x18 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x18 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x18 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x18 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x18 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x18 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x18 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x18 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x18 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x18 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x18 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x18 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x18 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x18 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x18 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x18 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x18 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x18 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x18 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x18 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x18 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x18 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x18 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x18 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x18 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x18 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x1C "GICDA_ISPENDR8,GICDA_ISPENDR8"
bitfld.long 0x1C 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x1C 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x1C 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x1C 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x1C 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x1C 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x1C 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x1C 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x1C 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x1C 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x1C 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x1C 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x1C 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x1C 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x1C 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x1C 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x1C 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x1C 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x1C 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x1C 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x1C 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x1C 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x1C 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x1C 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x1C 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x1C 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x1C 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x1C 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x1C 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x1C 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x1C 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x1C 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x20 "GICDA_ISPENDR9,GICDA_ISPENDR9"
bitfld.long 0x20 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x20 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x20 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x20 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x20 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x20 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x20 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x20 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x20 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x20 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x20 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x20 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x20 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x20 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x20 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x20 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x20 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x20 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x20 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x20 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x20 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x20 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x20 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x20 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x20 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x20 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x20 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x20 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x20 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x20 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x20 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x20 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x24 "GICDA_ISPENDR10,GICDA_ISPENDR10"
bitfld.long 0x24 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x24 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x24 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x24 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x24 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x24 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x24 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x24 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x24 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x24 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x24 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x24 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x24 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x24 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x24 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x24 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x24 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x24 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x24 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x24 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x24 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x24 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x24 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x24 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x24 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x24 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x24 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x24 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x24 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x24 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x24 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x24 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x28 "GICDA_ISPENDR11,GICDA_ISPENDR11"
bitfld.long 0x28 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x28 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x28 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x28 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x28 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x28 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x28 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x28 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x28 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x28 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x28 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x28 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x28 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x28 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x28 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x28 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x28 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x28 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x28 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x28 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x28 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x28 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x28 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x28 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x28 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x28 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x28 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x28 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x28 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x28 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x28 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x28 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x2C "GICDA_ISPENDR12,GICDA_ISPENDR12"
bitfld.long 0x2C 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x2C 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x2C 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x2C 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x2C 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x2C 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x2C 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x2C 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x2C 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x2C 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x2C 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x2C 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x2C 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x2C 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x2C 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x2C 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x2C 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x2C 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x2C 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x2C 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x2C 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x2C 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x2C 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x2C 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x2C 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x2C 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x2C 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x2C 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x2C 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x2C 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x2C 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x2C 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x30 "GICDA_ISPENDR13,GICDA_ISPENDR13"
bitfld.long 0x30 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x30 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x30 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x30 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x30 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x30 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x30 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x30 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x30 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x30 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x30 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x30 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x30 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x30 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x30 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x30 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x30 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x30 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x30 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x30 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x30 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x30 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x30 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x30 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x30 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x30 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x30 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x30 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x30 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x30 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x30 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x30 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x34 "GICDA_ISPENDR14,GICDA_ISPENDR14"
bitfld.long 0x34 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x34 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x34 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x34 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x34 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x34 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x34 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x34 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x34 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x34 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x34 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x34 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x34 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x34 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x34 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x34 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x34 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x34 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x34 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x34 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x34 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x34 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x34 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x34 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x34 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x34 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x34 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x34 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x34 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x34 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x34 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x34 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x38 "GICDA_ISPENDR15,GICDA_ISPENDR15"
bitfld.long 0x38 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x38 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x38 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x38 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x38 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x38 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x38 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x38 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x38 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x38 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x38 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x38 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x38 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x38 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x38 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x38 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x38 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x38 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x38 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x38 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x38 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x38 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x38 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x38 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x38 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x38 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x38 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x38 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x38 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x38 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x38 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x38 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x3C "GICDA_ISPENDR16,GICDA_ISPENDR16"
bitfld.long 0x3C 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x3C 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x3C 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x3C 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x3C 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x3C 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x3C 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x3C 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x3C 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x3C 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x3C 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x3C 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x3C 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x3C 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x3C 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x3C 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x3C 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x3C 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x3C 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x3C 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x3C 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x3C 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x3C 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x3C 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x3C 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x3C 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x3C 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x3C 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x3C 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x3C 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x3C 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x3C 0. "set_pending_bit0,set_pending_bit0" "0,1"
line.long 0x40 "GICDA_ISPENDR17,GICDA_ISPENDR17"
bitfld.long 0x40 31. "set_pending_bit31,set_pending_bit31" "0,1"
bitfld.long 0x40 30. "set_pending_bit30,set_pending_bit30" "0,1"
newline
bitfld.long 0x40 29. "set_pending_bit29,set_pending_bit29" "0,1"
bitfld.long 0x40 28. "set_pending_bit28,set_pending_bit28" "0,1"
newline
bitfld.long 0x40 27. "set_pending_bit27,set_pending_bit27" "0,1"
bitfld.long 0x40 26. "set_pending_bit26,set_pending_bit26" "0,1"
newline
bitfld.long 0x40 25. "set_pending_bit25,set_pending_bit25" "0,1"
bitfld.long 0x40 24. "set_pending_bit24,set_pending_bit24" "0,1"
newline
bitfld.long 0x40 23. "set_pending_bit23,set_pending_bit23" "0,1"
bitfld.long 0x40 22. "set_pending_bit22,set_pending_bit22" "0,1"
newline
bitfld.long 0x40 21. "set_pending_bit21,set_pending_bit21" "0,1"
bitfld.long 0x40 20. "set_pending_bit20,set_pending_bit20" "0,1"
newline
bitfld.long 0x40 19. "set_pending_bit19,set_pending_bit19" "0,1"
bitfld.long 0x40 18. "set_pending_bit18,set_pending_bit18" "0,1"
newline
bitfld.long 0x40 17. "set_pending_bit17,set_pending_bit17" "0,1"
bitfld.long 0x40 16. "set_pending_bit16,set_pending_bit16" "0,1"
newline
bitfld.long 0x40 15. "set_pending_bit15,set_pending_bit15" "0,1"
bitfld.long 0x40 14. "set_pending_bit14,set_pending_bit14" "0,1"
newline
bitfld.long 0x40 13. "set_pending_bit13,set_pending_bit13" "0,1"
bitfld.long 0x40 12. "set_pending_bit12,set_pending_bit12" "0,1"
newline
bitfld.long 0x40 11. "set_pending_bit11,set_pending_bit11" "0,1"
bitfld.long 0x40 10. "set_pending_bit10,set_pending_bit10" "0,1"
newline
bitfld.long 0x40 9. "set_pending_bit9,set_pending_bit9" "0,1"
bitfld.long 0x40 8. "set_pending_bit8,set_pending_bit8" "0,1"
newline
bitfld.long 0x40 7. "set_pending_bit7,set_pending_bit7" "0,1"
bitfld.long 0x40 6. "set_pending_bit6,set_pending_bit6" "0,1"
newline
bitfld.long 0x40 5. "set_pending_bit5,set_pending_bit5" "0,1"
bitfld.long 0x40 4. "set_pending_bit4,set_pending_bit4" "0,1"
newline
bitfld.long 0x40 3. "set_pending_bit3,set_pending_bit3" "0,1"
bitfld.long 0x40 2. "set_pending_bit2,set_pending_bit2" "0,1"
newline
bitfld.long 0x40 1. "set_pending_bit1,set_pending_bit1" "0,1"
bitfld.long 0x40 0. "set_pending_bit0,set_pending_bit0" "0,1"
group.long 0xE0284++0x43
line.long 0x0 "GICDA_ICPENDR1,GICDA_ICPENDR1"
bitfld.long 0x0 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x0 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x0 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x0 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x0 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x0 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x0 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x0 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x0 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x0 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x0 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x0 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x0 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x0 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x0 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x0 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x0 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x4 "GICDA_ICPENDR2,GICDA_ICPENDR2"
bitfld.long 0x4 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x4 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x4 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x4 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x4 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x4 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x4 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x4 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x4 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x4 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x4 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x4 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x4 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x4 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x4 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x4 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x4 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x4 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x4 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x4 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x4 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x4 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x4 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x4 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x4 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x4 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x4 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x4 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x4 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x4 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x4 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x4 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x8 "GICDA_ICPENDR3,GICDA_ICPENDR3"
bitfld.long 0x8 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x8 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x8 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x8 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x8 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x8 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x8 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x8 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x8 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x8 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x8 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x8 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x8 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x8 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x8 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x8 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x8 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x8 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x8 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x8 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x8 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x8 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x8 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x8 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x8 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x8 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x8 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x8 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x8 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x8 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x8 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x8 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0xC "GICDA_ICPENDR4,GICDA_ICPENDR4"
bitfld.long 0xC 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0xC 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0xC 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0xC 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0xC 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0xC 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0xC 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0xC 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0xC 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0xC 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0xC 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0xC 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0xC 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0xC 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0xC 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0xC 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0xC 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0xC 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0xC 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0xC 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0xC 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0xC 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0xC 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0xC 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0xC 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0xC 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0xC 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0xC 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0xC 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0xC 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0xC 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0xC 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x10 "GICDA_ICPENDR5,GICDA_ICPENDR5"
bitfld.long 0x10 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x10 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x10 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x10 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x10 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x10 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x10 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x10 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x10 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x10 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x10 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x10 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x10 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x10 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x10 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x10 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x10 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x10 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x10 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x10 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x10 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x10 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x10 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x10 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x10 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x10 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x10 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x10 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x10 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x10 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x10 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x10 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x14 "GICDA_ICPENDR6,GICDA_ICPENDR6"
bitfld.long 0x14 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x14 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x14 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x14 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x14 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x14 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x14 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x14 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x14 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x14 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x14 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x14 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x14 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x14 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x14 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x14 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x14 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x14 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x14 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x14 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x14 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x14 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x14 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x14 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x14 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x14 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x14 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x14 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x14 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x14 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x14 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x14 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x18 "GICDA_ICPENDR7,GICDA_ICPENDR7"
bitfld.long 0x18 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x18 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x18 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x18 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x18 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x18 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x18 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x18 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x18 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x18 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x18 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x18 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x18 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x18 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x18 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x18 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x18 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x18 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x18 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x18 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x18 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x18 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x18 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x18 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x18 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x18 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x18 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x18 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x18 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x18 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x18 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x18 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x1C "GICDA_ICPENDR8,GICDA_ICPENDR8"
bitfld.long 0x1C 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x1C 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x1C 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x1C 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x1C 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x1C 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x1C 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x1C 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x1C 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x1C 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x1C 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x1C 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x1C 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x1C 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x1C 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x1C 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x1C 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x1C 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x1C 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x1C 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x1C 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x1C 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x1C 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x1C 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x1C 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x1C 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x1C 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x1C 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x1C 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x1C 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x1C 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x1C 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x20 "GICDA_ICPENDR9,GICDA_ICPENDR9"
bitfld.long 0x20 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x20 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x20 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x20 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x20 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x20 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x20 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x20 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x20 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x20 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x20 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x20 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x20 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x20 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x20 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x20 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x20 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x20 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x20 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x20 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x20 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x20 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x20 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x20 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x20 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x20 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x20 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x20 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x20 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x20 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x20 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x20 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x24 "GICDA_ICPENDR10,GICDA_ICPENDR10"
bitfld.long 0x24 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x24 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x24 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x24 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x24 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x24 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x24 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x24 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x24 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x24 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x24 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x24 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x24 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x24 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x24 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x24 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x24 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x24 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x24 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x24 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x24 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x24 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x24 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x24 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x24 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x24 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x24 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x24 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x24 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x24 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x24 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x24 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x28 "GICDA_ICPENDR11,GICDA_ICPENDR11"
bitfld.long 0x28 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x28 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x28 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x28 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x28 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x28 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x28 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x28 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x28 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x28 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x28 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x28 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x28 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x28 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x28 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x28 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x28 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x28 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x28 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x28 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x28 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x28 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x28 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x28 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x28 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x28 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x28 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x28 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x28 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x28 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x28 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x28 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x2C "GICDA_ICPENDR12,GICDA_ICPENDR12"
bitfld.long 0x2C 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x2C 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x2C 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x2C 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x2C 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x2C 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x2C 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x2C 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x2C 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x2C 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x2C 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x2C 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x2C 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x2C 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x2C 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x2C 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x2C 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x2C 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x2C 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x2C 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x2C 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x2C 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x2C 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x2C 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x2C 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x2C 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x2C 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x2C 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x2C 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x2C 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x2C 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x2C 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x30 "GICDA_ICPENDR13,GICDA_ICPENDR13"
bitfld.long 0x30 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x30 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x30 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x30 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x30 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x30 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x30 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x30 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x30 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x30 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x30 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x30 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x30 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x30 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x30 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x30 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x30 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x30 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x30 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x30 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x30 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x30 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x30 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x30 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x30 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x30 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x30 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x30 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x30 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x30 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x30 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x30 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x34 "GICDA_ICPENDR14,GICDA_ICPENDR14"
bitfld.long 0x34 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x34 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x34 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x34 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x34 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x34 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x34 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x34 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x34 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x34 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x34 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x34 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x34 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x34 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x34 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x34 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x34 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x34 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x34 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x34 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x34 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x34 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x34 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x34 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x34 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x34 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x34 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x34 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x34 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x34 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x34 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x34 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x38 "GICDA_ICPENDR15,GICDA_ICPENDR15"
bitfld.long 0x38 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x38 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x38 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x38 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x38 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x38 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x38 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x38 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x38 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x38 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x38 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x38 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x38 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x38 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x38 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x38 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x38 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x38 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x38 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x38 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x38 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x38 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x38 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x38 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x38 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x38 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x38 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x38 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x38 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x38 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x38 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x38 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x3C "GICDA_ICPENDR16,GICDA_ICPENDR16"
bitfld.long 0x3C 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x3C 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x3C 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x3C 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x3C 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x3C 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x3C 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x3C 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x3C 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x3C 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x3C 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x3C 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x3C 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x3C 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x3C 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x3C 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x3C 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x3C 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x3C 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x3C 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x3C 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x3C 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x3C 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x3C 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x3C 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x3C 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x3C 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x3C 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x3C 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x3C 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x3C 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x3C 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
line.long 0x40 "GICDA_ICPENDR17,GICDA_ICPENDR17"
bitfld.long 0x40 31. "clear_pending_bit31,clear_pending_bit31" "0,1"
bitfld.long 0x40 30. "clear_pending_bit30,clear_pending_bit30" "0,1"
newline
bitfld.long 0x40 29. "clear_pending_bit29,clear_pending_bit29" "0,1"
bitfld.long 0x40 28. "clear_pending_bit28,clear_pending_bit28" "0,1"
newline
bitfld.long 0x40 27. "clear_pending_bit27,clear_pending_bit27" "0,1"
bitfld.long 0x40 26. "clear_pending_bit26,clear_pending_bit26" "0,1"
newline
bitfld.long 0x40 25. "clear_pending_bit25,clear_pending_bit25" "0,1"
bitfld.long 0x40 24. "clear_pending_bit24,clear_pending_bit24" "0,1"
newline
bitfld.long 0x40 23. "clear_pending_bit23,clear_pending_bit23" "0,1"
bitfld.long 0x40 22. "clear_pending_bit22,clear_pending_bit22" "0,1"
newline
bitfld.long 0x40 21. "clear_pending_bit21,clear_pending_bit21" "0,1"
bitfld.long 0x40 20. "clear_pending_bit20,clear_pending_bit20" "0,1"
newline
bitfld.long 0x40 19. "clear_pending_bit19,clear_pending_bit19" "0,1"
bitfld.long 0x40 18. "clear_pending_bit18,clear_pending_bit18" "0,1"
newline
bitfld.long 0x40 17. "clear_pending_bit17,clear_pending_bit17" "0,1"
bitfld.long 0x40 16. "clear_pending_bit16,clear_pending_bit16" "0,1"
newline
bitfld.long 0x40 15. "clear_pending_bit15,clear_pending_bit15" "0,1"
bitfld.long 0x40 14. "clear_pending_bit14,clear_pending_bit14" "0,1"
newline
bitfld.long 0x40 13. "clear_pending_bit13,clear_pending_bit13" "0,1"
bitfld.long 0x40 12. "clear_pending_bit12,clear_pending_bit12" "0,1"
newline
bitfld.long 0x40 11. "clear_pending_bit11,clear_pending_bit11" "0,1"
bitfld.long 0x40 10. "clear_pending_bit10,clear_pending_bit10" "0,1"
newline
bitfld.long 0x40 9. "clear_pending_bit9,clear_pending_bit9" "0,1"
bitfld.long 0x40 8. "clear_pending_bit8,clear_pending_bit8" "0,1"
newline
bitfld.long 0x40 7. "clear_pending_bit7,clear_pending_bit7" "0,1"
bitfld.long 0x40 6. "clear_pending_bit6,clear_pending_bit6" "0,1"
newline
bitfld.long 0x40 5. "clear_pending_bit5,clear_pending_bit5" "0,1"
bitfld.long 0x40 4. "clear_pending_bit4,clear_pending_bit4" "0,1"
newline
bitfld.long 0x40 3. "clear_pending_bit3,clear_pending_bit3" "0,1"
bitfld.long 0x40 2. "clear_pending_bit2,clear_pending_bit2" "0,1"
newline
bitfld.long 0x40 1. "clear_pending_bit1,clear_pending_bit1" "0,1"
bitfld.long 0x40 0. "clear_pending_bit0,clear_pending_bit0" "0,1"
group.long 0xE0304++0x43
line.long 0x0 "GICDA_ISACTIVER1,GICDA_ISACTIVER1"
bitfld.long 0x0 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x0 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x0 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x0 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x0 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x0 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x0 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x0 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x0 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x0 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x0 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x0 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x0 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x0 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x0 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x0 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x0 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x4 "GICDA_ISACTIVER2,GICDA_ISACTIVER2"
bitfld.long 0x4 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x4 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x4 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x4 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x4 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x4 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x4 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x4 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x4 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x4 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x4 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x4 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x4 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x4 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x4 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x4 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x4 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x4 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x4 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x4 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x4 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x4 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x4 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x4 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x4 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x4 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x4 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x4 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x4 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x4 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x4 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x4 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x8 "GICDA_ISACTIVER3,GICDA_ISACTIVER3"
bitfld.long 0x8 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x8 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x8 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x8 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x8 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x8 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x8 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x8 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x8 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x8 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x8 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x8 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x8 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x8 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x8 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x8 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x8 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x8 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x8 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x8 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x8 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x8 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x8 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x8 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x8 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x8 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x8 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x8 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x8 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x8 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x8 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x8 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0xC "GICDA_ISACTIVER4,GICDA_ISACTIVER4"
bitfld.long 0xC 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0xC 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0xC 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0xC 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0xC 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0xC 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0xC 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0xC 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0xC 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0xC 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0xC 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0xC 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0xC 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0xC 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0xC 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0xC 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0xC 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0xC 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0xC 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0xC 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0xC 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0xC 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0xC 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0xC 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0xC 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0xC 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0xC 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0xC 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0xC 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0xC 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0xC 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0xC 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x10 "GICDA_ISACTIVER5,GICDA_ISACTIVER5"
bitfld.long 0x10 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x10 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x10 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x10 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x10 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x10 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x10 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x10 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x10 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x10 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x10 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x10 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x10 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x10 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x10 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x10 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x10 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x10 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x10 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x10 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x10 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x10 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x10 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x10 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x10 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x10 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x10 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x10 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x10 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x10 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x10 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x10 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x14 "GICDA_ISACTIVER6,GICDA_ISACTIVER6"
bitfld.long 0x14 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x14 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x14 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x14 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x14 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x14 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x14 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x14 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x14 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x14 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x14 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x14 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x14 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x14 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x14 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x14 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x14 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x14 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x14 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x14 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x14 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x14 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x14 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x14 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x14 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x14 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x14 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x14 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x14 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x14 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x14 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x14 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x18 "GICDA_ISACTIVER7,GICDA_ISACTIVER7"
bitfld.long 0x18 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x18 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x18 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x18 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x18 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x18 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x18 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x18 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x18 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x18 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x18 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x18 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x18 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x18 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x18 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x18 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x18 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x18 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x18 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x18 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x18 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x18 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x18 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x18 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x18 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x18 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x18 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x18 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x18 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x18 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x18 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x18 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x1C "GICDA_ISACTIVER8,GICDA_ISACTIVER8"
bitfld.long 0x1C 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x1C 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x1C 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x1C 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x1C 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x1C 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x1C 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x1C 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x1C 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x1C 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x1C 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x1C 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x1C 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x1C 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x1C 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x1C 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x1C 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x1C 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x1C 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x1C 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x1C 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x1C 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x1C 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x1C 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x1C 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x1C 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x1C 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x1C 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x1C 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x1C 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x1C 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x1C 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x20 "GICDA_ISACTIVER9,GICDA_ISACTIVER9"
bitfld.long 0x20 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x20 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x20 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x20 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x20 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x20 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x20 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x20 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x20 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x20 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x20 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x20 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x20 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x20 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x20 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x20 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x20 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x20 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x20 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x20 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x20 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x20 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x20 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x20 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x20 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x20 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x20 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x20 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x20 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x20 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x20 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x20 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x24 "GICDA_ISACTIVER10,GICDA_ISACTIVER10"
bitfld.long 0x24 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x24 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x24 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x24 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x24 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x24 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x24 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x24 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x24 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x24 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x24 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x24 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x24 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x24 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x24 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x24 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x24 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x24 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x24 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x24 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x24 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x24 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x24 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x24 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x24 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x24 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x24 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x24 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x24 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x24 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x24 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x24 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x28 "GICDA_ISACTIVER11,GICDA_ISACTIVER11"
bitfld.long 0x28 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x28 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x28 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x28 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x28 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x28 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x28 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x28 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x28 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x28 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x28 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x28 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x28 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x28 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x28 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x28 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x28 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x28 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x28 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x28 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x28 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x28 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x28 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x28 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x28 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x28 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x28 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x28 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x28 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x28 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x28 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x28 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x2C "GICDA_ISACTIVER12,GICDA_ISACTIVER12"
bitfld.long 0x2C 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x2C 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x2C 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x2C 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x2C 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x2C 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x2C 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x2C 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x2C 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x2C 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x2C 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x2C 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x2C 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x2C 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x2C 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x2C 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x2C 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x2C 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x2C 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x2C 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x2C 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x2C 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x2C 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x2C 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x2C 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x2C 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x2C 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x2C 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x2C 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x2C 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x2C 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x2C 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x30 "GICDA_ISACTIVER13,GICDA_ISACTIVER13"
bitfld.long 0x30 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x30 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x30 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x30 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x30 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x30 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x30 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x30 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x30 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x30 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x30 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x30 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x30 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x30 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x30 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x30 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x30 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x30 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x30 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x30 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x30 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x30 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x30 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x30 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x30 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x30 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x30 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x30 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x30 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x30 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x30 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x30 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x34 "GICDA_ISACTIVER14,GICDA_ISACTIVER14"
bitfld.long 0x34 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x34 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x34 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x34 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x34 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x34 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x34 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x34 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x34 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x34 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x34 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x34 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x34 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x34 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x34 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x34 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x34 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x34 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x34 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x34 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x34 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x34 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x34 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x34 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x34 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x34 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x34 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x34 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x34 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x34 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x34 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x34 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x38 "GICDA_ISACTIVER15,GICDA_ISACTIVER15"
bitfld.long 0x38 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x38 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x38 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x38 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x38 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x38 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x38 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x38 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x38 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x38 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x38 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x38 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x38 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x38 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x38 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x38 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x38 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x38 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x38 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x38 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x38 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x38 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x38 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x38 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x38 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x38 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x38 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x38 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x38 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x38 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x38 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x38 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x3C "GICDA_ISACTIVER16,GICDA_ISACTIVER16"
bitfld.long 0x3C 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x3C 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x3C 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x3C 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x3C 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x3C 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x3C 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x3C 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x3C 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x3C 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x3C 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x3C 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x3C 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x3C 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x3C 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x3C 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x3C 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x3C 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x3C 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x3C 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x3C 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x3C 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x3C 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x3C 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x3C 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x3C 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x3C 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x3C 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x3C 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x3C 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x3C 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x3C 0. "set_active_bit0,set_active_bit0" "0,1"
line.long 0x40 "GICDA_ISACTIVER17,GICDA_ISACTIVER17"
bitfld.long 0x40 31. "set_active_bit31,set_active_bit31" "0,1"
bitfld.long 0x40 30. "set_active_bit30,set_active_bit30" "0,1"
newline
bitfld.long 0x40 29. "set_active_bit29,set_active_bit29" "0,1"
bitfld.long 0x40 28. "set_active_bit28,set_active_bit28" "0,1"
newline
bitfld.long 0x40 27. "set_active_bit27,set_active_bit27" "0,1"
bitfld.long 0x40 26. "set_active_bit26,set_active_bit26" "0,1"
newline
bitfld.long 0x40 25. "set_active_bit25,set_active_bit25" "0,1"
bitfld.long 0x40 24. "set_active_bit24,set_active_bit24" "0,1"
newline
bitfld.long 0x40 23. "set_active_bit23,set_active_bit23" "0,1"
bitfld.long 0x40 22. "set_active_bit22,set_active_bit22" "0,1"
newline
bitfld.long 0x40 21. "set_active_bit21,set_active_bit21" "0,1"
bitfld.long 0x40 20. "set_active_bit20,set_active_bit20" "0,1"
newline
bitfld.long 0x40 19. "set_active_bit19,set_active_bit19" "0,1"
bitfld.long 0x40 18. "set_active_bit18,set_active_bit18" "0,1"
newline
bitfld.long 0x40 17. "set_active_bit17,set_active_bit17" "0,1"
bitfld.long 0x40 16. "set_active_bit16,set_active_bit16" "0,1"
newline
bitfld.long 0x40 15. "set_active_bit15,set_active_bit15" "0,1"
bitfld.long 0x40 14. "set_active_bit14,set_active_bit14" "0,1"
newline
bitfld.long 0x40 13. "set_active_bit13,set_active_bit13" "0,1"
bitfld.long 0x40 12. "set_active_bit12,set_active_bit12" "0,1"
newline
bitfld.long 0x40 11. "set_active_bit11,set_active_bit11" "0,1"
bitfld.long 0x40 10. "set_active_bit10,set_active_bit10" "0,1"
newline
bitfld.long 0x40 9. "set_active_bit9,set_active_bit9" "0,1"
bitfld.long 0x40 8. "set_active_bit8,set_active_bit8" "0,1"
newline
bitfld.long 0x40 7. "set_active_bit7,set_active_bit7" "0,1"
bitfld.long 0x40 6. "set_active_bit6,set_active_bit6" "0,1"
newline
bitfld.long 0x40 5. "set_active_bit5,set_active_bit5" "0,1"
bitfld.long 0x40 4. "set_active_bit4,set_active_bit4" "0,1"
newline
bitfld.long 0x40 3. "set_active_bit3,set_active_bit3" "0,1"
bitfld.long 0x40 2. "set_active_bit2,set_active_bit2" "0,1"
newline
bitfld.long 0x40 1. "set_active_bit1,set_active_bit1" "0,1"
bitfld.long 0x40 0. "set_active_bit0,set_active_bit0" "0,1"
group.long 0xE0384++0x43
line.long 0x0 "GICDA_ICACTIVER1,GICDA_ICACTIVER1"
bitfld.long 0x0 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x0 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x0 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x0 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x0 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x0 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x0 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x0 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x0 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x0 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x0 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x0 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x0 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x0 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x0 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x0 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x0 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x0 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x0 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x0 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x0 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x0 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x0 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x0 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x0 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x0 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x0 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x0 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x0 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x0 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x0 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x0 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x4 "GICDA_ICACTIVER2,GICDA_ICACTIVER2"
bitfld.long 0x4 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x4 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x4 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x4 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x4 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x4 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x4 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x4 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x4 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x4 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x4 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x4 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x4 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x4 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x4 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x4 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x4 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x4 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x4 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x4 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x4 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x4 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x4 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x4 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x4 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x4 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x4 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x4 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x4 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x4 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x4 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x4 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x8 "GICDA_ICACTIVER3,GICDA_ICACTIVER3"
bitfld.long 0x8 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x8 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x8 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x8 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x8 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x8 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x8 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x8 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x8 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x8 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x8 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x8 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x8 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x8 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x8 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x8 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x8 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x8 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x8 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x8 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x8 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x8 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x8 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x8 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x8 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x8 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x8 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x8 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x8 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x8 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x8 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x8 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0xC "GICDA_ICACTIVER4,GICDA_ICACTIVER4"
bitfld.long 0xC 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0xC 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0xC 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0xC 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0xC 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0xC 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0xC 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0xC 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0xC 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0xC 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0xC 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0xC 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0xC 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0xC 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0xC 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0xC 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0xC 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0xC 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0xC 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0xC 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0xC 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0xC 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0xC 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0xC 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0xC 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0xC 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0xC 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0xC 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0xC 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0xC 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0xC 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0xC 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x10 "GICDA_ICACTIVER5,GICDA_ICACTIVER5"
bitfld.long 0x10 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x10 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x10 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x10 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x10 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x10 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x10 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x10 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x10 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x10 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x10 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x10 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x10 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x10 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x10 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x10 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x10 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x10 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x10 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x10 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x10 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x10 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x10 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x10 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x10 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x10 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x10 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x10 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x10 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x10 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x10 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x10 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x14 "GICDA_ICACTIVER6,GICDA_ICACTIVER6"
bitfld.long 0x14 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x14 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x14 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x14 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x14 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x14 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x14 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x14 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x14 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x14 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x14 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x14 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x14 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x14 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x14 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x14 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x14 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x14 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x14 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x14 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x14 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x14 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x14 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x14 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x14 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x14 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x14 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x14 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x14 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x14 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x14 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x14 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x18 "GICDA_ICACTIVER7,GICDA_ICACTIVER7"
bitfld.long 0x18 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x18 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x18 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x18 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x18 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x18 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x18 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x18 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x18 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x18 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x18 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x18 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x18 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x18 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x18 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x18 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x18 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x18 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x18 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x18 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x18 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x18 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x18 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x18 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x18 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x18 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x18 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x18 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x18 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x18 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x18 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x18 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x1C "GICDA_ICACTIVER8,GICDA_ICACTIVER8"
bitfld.long 0x1C 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x1C 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x1C 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x1C 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x1C 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x1C 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x1C 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x1C 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x1C 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x1C 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x1C 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x1C 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x1C 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x1C 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x1C 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x1C 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x1C 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x1C 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x1C 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x1C 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x1C 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x1C 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x1C 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x1C 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x1C 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x1C 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x1C 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x1C 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x1C 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x1C 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x1C 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x1C 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x20 "GICDA_ICACTIVER9,GICDA_ICACTIVER9"
bitfld.long 0x20 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x20 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x20 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x20 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x20 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x20 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x20 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x20 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x20 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x20 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x20 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x20 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x20 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x20 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x20 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x20 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x20 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x20 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x20 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x20 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x20 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x20 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x20 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x20 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x20 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x20 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x20 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x20 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x20 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x20 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x20 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x20 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x24 "GICDA_ICACTIVER10,GICDA_ICACTIVER10"
bitfld.long 0x24 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x24 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x24 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x24 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x24 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x24 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x24 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x24 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x24 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x24 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x24 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x24 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x24 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x24 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x24 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x24 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x24 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x24 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x24 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x24 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x24 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x24 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x24 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x24 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x24 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x24 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x24 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x24 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x24 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x24 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x24 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x24 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x28 "GICDA_ICACTIVER11,GICDA_ICACTIVER11"
bitfld.long 0x28 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x28 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x28 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x28 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x28 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x28 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x28 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x28 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x28 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x28 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x28 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x28 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x28 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x28 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x28 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x28 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x28 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x28 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x28 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x28 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x28 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x28 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x28 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x28 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x28 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x28 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x28 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x28 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x28 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x28 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x28 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x28 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x2C "GICDA_ICACTIVER12,GICDA_ICACTIVER12"
bitfld.long 0x2C 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x2C 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x2C 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x2C 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x2C 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x2C 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x2C 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x2C 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x2C 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x2C 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x2C 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x2C 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x2C 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x2C 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x2C 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x2C 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x2C 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x2C 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x2C 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x2C 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x2C 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x2C 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x2C 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x2C 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x2C 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x2C 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x2C 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x2C 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x2C 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x2C 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x2C 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x2C 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x30 "GICDA_ICACTIVER13,GICDA_ICACTIVER13"
bitfld.long 0x30 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x30 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x30 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x30 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x30 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x30 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x30 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x30 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x30 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x30 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x30 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x30 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x30 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x30 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x30 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x30 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x30 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x30 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x30 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x30 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x30 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x30 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x30 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x30 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x30 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x30 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x30 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x30 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x30 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x30 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x30 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x30 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x34 "GICDA_ICACTIVER14,GICDA_ICACTIVER14"
bitfld.long 0x34 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x34 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x34 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x34 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x34 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x34 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x34 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x34 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x34 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x34 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x34 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x34 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x34 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x34 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x34 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x34 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x34 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x34 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x34 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x34 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x34 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x34 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x34 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x34 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x34 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x34 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x34 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x34 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x34 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x34 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x34 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x34 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x38 "GICDA_ICACTIVER15,GICDA_ICACTIVER15"
bitfld.long 0x38 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x38 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x38 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x38 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x38 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x38 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x38 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x38 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x38 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x38 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x38 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x38 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x38 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x38 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x38 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x38 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x38 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x38 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x38 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x38 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x38 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x38 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x38 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x38 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x38 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x38 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x38 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x38 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x38 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x38 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x38 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x38 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x3C "GICDA_ICACTIVER16,GICDA_ICACTIVER16"
bitfld.long 0x3C 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x3C 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x3C 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x3C 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x3C 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x3C 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x3C 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x3C 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x3C 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x3C 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x3C 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x3C 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x3C 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x3C 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x3C 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x3C 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x3C 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x3C 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x3C 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x3C 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x3C 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x3C 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x3C 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x3C 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x3C 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x3C 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x3C 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x3C 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x3C 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x3C 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x3C 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x3C 0. "clear_active_bit0,clear_active_bit0" "0,1"
line.long 0x40 "GICDA_ICACTIVER17,GICDA_ICACTIVER17"
bitfld.long 0x40 31. "clear_active_bit31,clear_active_bit31" "0,1"
bitfld.long 0x40 30. "clear_active_bit30,clear_active_bit30" "0,1"
newline
bitfld.long 0x40 29. "clear_active_bit29,clear_active_bit29" "0,1"
bitfld.long 0x40 28. "clear_active_bit28,clear_active_bit28" "0,1"
newline
bitfld.long 0x40 27. "clear_active_bit27,clear_active_bit27" "0,1"
bitfld.long 0x40 26. "clear_active_bit26,clear_active_bit26" "0,1"
newline
bitfld.long 0x40 25. "clear_active_bit25,clear_active_bit25" "0,1"
bitfld.long 0x40 24. "clear_active_bit24,clear_active_bit24" "0,1"
newline
bitfld.long 0x40 23. "clear_active_bit23,clear_active_bit23" "0,1"
bitfld.long 0x40 22. "clear_active_bit22,clear_active_bit22" "0,1"
newline
bitfld.long 0x40 21. "clear_active_bit21,clear_active_bit21" "0,1"
bitfld.long 0x40 20. "clear_active_bit20,clear_active_bit20" "0,1"
newline
bitfld.long 0x40 19. "clear_active_bit19,clear_active_bit19" "0,1"
bitfld.long 0x40 18. "clear_active_bit18,clear_active_bit18" "0,1"
newline
bitfld.long 0x40 17. "clear_active_bit17,clear_active_bit17" "0,1"
bitfld.long 0x40 16. "clear_active_bit16,clear_active_bit16" "0,1"
newline
bitfld.long 0x40 15. "clear_active_bit15,clear_active_bit15" "0,1"
bitfld.long 0x40 14. "clear_active_bit14,clear_active_bit14" "0,1"
newline
bitfld.long 0x40 13. "clear_active_bit13,clear_active_bit13" "0,1"
bitfld.long 0x40 12. "clear_active_bit12,clear_active_bit12" "0,1"
newline
bitfld.long 0x40 11. "clear_active_bit11,clear_active_bit11" "0,1"
bitfld.long 0x40 10. "clear_active_bit10,clear_active_bit10" "0,1"
newline
bitfld.long 0x40 9. "clear_active_bit9,clear_active_bit9" "0,1"
bitfld.long 0x40 8. "clear_active_bit8,clear_active_bit8" "0,1"
newline
bitfld.long 0x40 7. "clear_active_bit7,clear_active_bit7" "0,1"
bitfld.long 0x40 6. "clear_active_bit6,clear_active_bit6" "0,1"
newline
bitfld.long 0x40 5. "clear_active_bit5,clear_active_bit5" "0,1"
bitfld.long 0x40 4. "clear_active_bit4,clear_active_bit4" "0,1"
newline
bitfld.long 0x40 3. "clear_active_bit3,clear_active_bit3" "0,1"
bitfld.long 0x40 2. "clear_active_bit2,clear_active_bit2" "0,1"
newline
bitfld.long 0x40 1. "clear_active_bit1,clear_active_bit1" "0,1"
bitfld.long 0x40 0. "clear_active_bit0,clear_active_bit0" "0,1"
group.long 0xE0420++0x21F
line.long 0x0 "GICDA_IPRIORITYR8,GICDA_IPRIORITYR8"
hexmask.long.byte 0x0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x0 0.--7. 1. "offset0,offset0"
line.long 0x4 "GICDA_IPRIORITYR9,GICDA_IPRIORITYR9"
hexmask.long.byte 0x4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x4 0.--7. 1. "offset0,offset0"
line.long 0x8 "GICDA_IPRIORITYR10,GICDA_IPRIORITYR10"
hexmask.long.byte 0x8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x8 0.--7. 1. "offset0,offset0"
line.long 0xC "GICDA_IPRIORITYR11,GICDA_IPRIORITYR11"
hexmask.long.byte 0xC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC 0.--7. 1. "offset0,offset0"
line.long 0x10 "GICDA_IPRIORITYR12,GICDA_IPRIORITYR12"
hexmask.long.byte 0x10 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x10 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x10 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x10 0.--7. 1. "offset0,offset0"
line.long 0x14 "GICDA_IPRIORITYR13,GICDA_IPRIORITYR13"
hexmask.long.byte 0x14 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x14 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x14 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x14 0.--7. 1. "offset0,offset0"
line.long 0x18 "GICDA_IPRIORITYR14,GICDA_IPRIORITYR14"
hexmask.long.byte 0x18 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x18 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x18 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x18 0.--7. 1. "offset0,offset0"
line.long 0x1C "GICDA_IPRIORITYR15,GICDA_IPRIORITYR15"
hexmask.long.byte 0x1C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C 0.--7. 1. "offset0,offset0"
line.long 0x20 "GICDA_IPRIORITYR16,GICDA_IPRIORITYR16"
hexmask.long.byte 0x20 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x20 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x20 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x20 0.--7. 1. "offset0,offset0"
line.long 0x24 "GICDA_IPRIORITYR17,GICDA_IPRIORITYR17"
hexmask.long.byte 0x24 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x24 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x24 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x24 0.--7. 1. "offset0,offset0"
line.long 0x28 "GICDA_IPRIORITYR18,GICDA_IPRIORITYR18"
hexmask.long.byte 0x28 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x28 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x28 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x28 0.--7. 1. "offset0,offset0"
line.long 0x2C "GICDA_IPRIORITYR19,GICDA_IPRIORITYR19"
hexmask.long.byte 0x2C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x2C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x2C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x2C 0.--7. 1. "offset0,offset0"
line.long 0x30 "GICDA_IPRIORITYR20,GICDA_IPRIORITYR20"
hexmask.long.byte 0x30 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x30 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x30 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x30 0.--7. 1. "offset0,offset0"
line.long 0x34 "GICDA_IPRIORITYR21,GICDA_IPRIORITYR21"
hexmask.long.byte 0x34 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x34 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x34 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x34 0.--7. 1. "offset0,offset0"
line.long 0x38 "GICDA_IPRIORITYR22,GICDA_IPRIORITYR22"
hexmask.long.byte 0x38 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x38 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x38 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x38 0.--7. 1. "offset0,offset0"
line.long 0x3C "GICDA_IPRIORITYR23,GICDA_IPRIORITYR23"
hexmask.long.byte 0x3C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x3C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x3C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x3C 0.--7. 1. "offset0,offset0"
line.long 0x40 "GICDA_IPRIORITYR24,GICDA_IPRIORITYR24"
hexmask.long.byte 0x40 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x40 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x40 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x40 0.--7. 1. "offset0,offset0"
line.long 0x44 "GICDA_IPRIORITYR25,GICDA_IPRIORITYR25"
hexmask.long.byte 0x44 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x44 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x44 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x44 0.--7. 1. "offset0,offset0"
line.long 0x48 "GICDA_IPRIORITYR26,GICDA_IPRIORITYR26"
hexmask.long.byte 0x48 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x48 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x48 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x48 0.--7. 1. "offset0,offset0"
line.long 0x4C "GICDA_IPRIORITYR27,GICDA_IPRIORITYR27"
hexmask.long.byte 0x4C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x4C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x4C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x4C 0.--7. 1. "offset0,offset0"
line.long 0x50 "GICDA_IPRIORITYR28,GICDA_IPRIORITYR28"
hexmask.long.byte 0x50 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x50 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x50 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x50 0.--7. 1. "offset0,offset0"
line.long 0x54 "GICDA_IPRIORITYR29,GICDA_IPRIORITYR29"
hexmask.long.byte 0x54 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x54 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x54 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x54 0.--7. 1. "offset0,offset0"
line.long 0x58 "GICDA_IPRIORITYR30,GICDA_IPRIORITYR30"
hexmask.long.byte 0x58 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x58 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x58 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x58 0.--7. 1. "offset0,offset0"
line.long 0x5C "GICDA_IPRIORITYR31,GICDA_IPRIORITYR31"
hexmask.long.byte 0x5C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x5C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x5C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x5C 0.--7. 1. "offset0,offset0"
line.long 0x60 "GICDA_IPRIORITYR32,GICDA_IPRIORITYR32"
hexmask.long.byte 0x60 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x60 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x60 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x60 0.--7. 1. "offset0,offset0"
line.long 0x64 "GICDA_IPRIORITYR33,GICDA_IPRIORITYR33"
hexmask.long.byte 0x64 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x64 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x64 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x64 0.--7. 1. "offset0,offset0"
line.long 0x68 "GICDA_IPRIORITYR34,GICDA_IPRIORITYR34"
hexmask.long.byte 0x68 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x68 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x68 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x68 0.--7. 1. "offset0,offset0"
line.long 0x6C "GICDA_IPRIORITYR35,GICDA_IPRIORITYR35"
hexmask.long.byte 0x6C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x6C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x6C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x6C 0.--7. 1. "offset0,offset0"
line.long 0x70 "GICDA_IPRIORITYR36,GICDA_IPRIORITYR36"
hexmask.long.byte 0x70 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x70 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x70 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x70 0.--7. 1. "offset0,offset0"
line.long 0x74 "GICDA_IPRIORITYR37,GICDA_IPRIORITYR37"
hexmask.long.byte 0x74 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x74 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x74 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x74 0.--7. 1. "offset0,offset0"
line.long 0x78 "GICDA_IPRIORITYR38,GICDA_IPRIORITYR38"
hexmask.long.byte 0x78 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x78 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x78 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x78 0.--7. 1. "offset0,offset0"
line.long 0x7C "GICDA_IPRIORITYR39,GICDA_IPRIORITYR39"
hexmask.long.byte 0x7C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x7C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x7C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x7C 0.--7. 1. "offset0,offset0"
line.long 0x80 "GICDA_IPRIORITYR40,GICDA_IPRIORITYR40"
hexmask.long.byte 0x80 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x80 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x80 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x80 0.--7. 1. "offset0,offset0"
line.long 0x84 "GICDA_IPRIORITYR41,GICDA_IPRIORITYR41"
hexmask.long.byte 0x84 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x84 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x84 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x84 0.--7. 1. "offset0,offset0"
line.long 0x88 "GICDA_IPRIORITYR42,GICDA_IPRIORITYR42"
hexmask.long.byte 0x88 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x88 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x88 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x88 0.--7. 1. "offset0,offset0"
line.long 0x8C "GICDA_IPRIORITYR43,GICDA_IPRIORITYR43"
hexmask.long.byte 0x8C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x8C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x8C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x8C 0.--7. 1. "offset0,offset0"
line.long 0x90 "GICDA_IPRIORITYR44,GICDA_IPRIORITYR44"
hexmask.long.byte 0x90 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x90 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x90 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x90 0.--7. 1. "offset0,offset0"
line.long 0x94 "GICDA_IPRIORITYR45,GICDA_IPRIORITYR45"
hexmask.long.byte 0x94 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x94 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x94 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x94 0.--7. 1. "offset0,offset0"
line.long 0x98 "GICDA_IPRIORITYR46,GICDA_IPRIORITYR46"
hexmask.long.byte 0x98 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x98 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x98 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x98 0.--7. 1. "offset0,offset0"
line.long 0x9C "GICDA_IPRIORITYR47,GICDA_IPRIORITYR47"
hexmask.long.byte 0x9C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x9C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x9C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x9C 0.--7. 1. "offset0,offset0"
line.long 0xA0 "GICDA_IPRIORITYR48,GICDA_IPRIORITYR48"
hexmask.long.byte 0xA0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xA0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xA0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xA0 0.--7. 1. "offset0,offset0"
line.long 0xA4 "GICDA_IPRIORITYR49,GICDA_IPRIORITYR49"
hexmask.long.byte 0xA4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xA4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xA4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xA4 0.--7. 1. "offset0,offset0"
line.long 0xA8 "GICDA_IPRIORITYR50,GICDA_IPRIORITYR50"
hexmask.long.byte 0xA8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xA8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xA8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xA8 0.--7. 1. "offset0,offset0"
line.long 0xAC "GICDA_IPRIORITYR51,GICDA_IPRIORITYR51"
hexmask.long.byte 0xAC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xAC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xAC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xAC 0.--7. 1. "offset0,offset0"
line.long 0xB0 "GICDA_IPRIORITYR52,GICDA_IPRIORITYR52"
hexmask.long.byte 0xB0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xB0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xB0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xB0 0.--7. 1. "offset0,offset0"
line.long 0xB4 "GICDA_IPRIORITYR53,GICDA_IPRIORITYR53"
hexmask.long.byte 0xB4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xB4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xB4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xB4 0.--7. 1. "offset0,offset0"
line.long 0xB8 "GICDA_IPRIORITYR54,GICDA_IPRIORITYR54"
hexmask.long.byte 0xB8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xB8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xB8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xB8 0.--7. 1. "offset0,offset0"
line.long 0xBC "GICDA_IPRIORITYR55,GICDA_IPRIORITYR55"
hexmask.long.byte 0xBC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xBC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xBC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xBC 0.--7. 1. "offset0,offset0"
line.long 0xC0 "GICDA_IPRIORITYR56,GICDA_IPRIORITYR56"
hexmask.long.byte 0xC0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC0 0.--7. 1. "offset0,offset0"
line.long 0xC4 "GICDA_IPRIORITYR57,GICDA_IPRIORITYR57"
hexmask.long.byte 0xC4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC4 0.--7. 1. "offset0,offset0"
line.long 0xC8 "GICDA_IPRIORITYR58,GICDA_IPRIORITYR58"
hexmask.long.byte 0xC8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xC8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xC8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xC8 0.--7. 1. "offset0,offset0"
line.long 0xCC "GICDA_IPRIORITYR59,GICDA_IPRIORITYR59"
hexmask.long.byte 0xCC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xCC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xCC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xCC 0.--7. 1. "offset0,offset0"
line.long 0xD0 "GICDA_IPRIORITYR60,GICDA_IPRIORITYR60"
hexmask.long.byte 0xD0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xD0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xD0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xD0 0.--7. 1. "offset0,offset0"
line.long 0xD4 "GICDA_IPRIORITYR61,GICDA_IPRIORITYR61"
hexmask.long.byte 0xD4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xD4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xD4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xD4 0.--7. 1. "offset0,offset0"
line.long 0xD8 "GICDA_IPRIORITYR62,GICDA_IPRIORITYR62"
hexmask.long.byte 0xD8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xD8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xD8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xD8 0.--7. 1. "offset0,offset0"
line.long 0xDC "GICDA_IPRIORITYR63,GICDA_IPRIORITYR63"
hexmask.long.byte 0xDC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xDC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xDC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xDC 0.--7. 1. "offset0,offset0"
line.long 0xE0 "GICDA_IPRIORITYR64,GICDA_IPRIORITYR64"
hexmask.long.byte 0xE0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xE0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xE0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xE0 0.--7. 1. "offset0,offset0"
line.long 0xE4 "GICDA_IPRIORITYR65,GICDA_IPRIORITYR65"
hexmask.long.byte 0xE4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xE4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xE4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xE4 0.--7. 1. "offset0,offset0"
line.long 0xE8 "GICDA_IPRIORITYR66,GICDA_IPRIORITYR66"
hexmask.long.byte 0xE8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xE8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xE8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xE8 0.--7. 1. "offset0,offset0"
line.long 0xEC "GICDA_IPRIORITYR67,GICDA_IPRIORITYR67"
hexmask.long.byte 0xEC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xEC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xEC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xEC 0.--7. 1. "offset0,offset0"
line.long 0xF0 "GICDA_IPRIORITYR68,GICDA_IPRIORITYR68"
hexmask.long.byte 0xF0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xF0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xF0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xF0 0.--7. 1. "offset0,offset0"
line.long 0xF4 "GICDA_IPRIORITYR69,GICDA_IPRIORITYR69"
hexmask.long.byte 0xF4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xF4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xF4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xF4 0.--7. 1. "offset0,offset0"
line.long 0xF8 "GICDA_IPRIORITYR70,GICDA_IPRIORITYR70"
hexmask.long.byte 0xF8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xF8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xF8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xF8 0.--7. 1. "offset0,offset0"
line.long 0xFC "GICDA_IPRIORITYR71,GICDA_IPRIORITYR71"
hexmask.long.byte 0xFC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0xFC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0xFC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0xFC 0.--7. 1. "offset0,offset0"
line.long 0x100 "GICDA_IPRIORITYR72,GICDA_IPRIORITYR72"
hexmask.long.byte 0x100 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x100 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x100 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x100 0.--7. 1. "offset0,offset0"
line.long 0x104 "GICDA_IPRIORITYR73,GICDA_IPRIORITYR73"
hexmask.long.byte 0x104 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x104 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x104 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x104 0.--7. 1. "offset0,offset0"
line.long 0x108 "GICDA_IPRIORITYR74,GICDA_IPRIORITYR74"
hexmask.long.byte 0x108 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x108 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x108 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x108 0.--7. 1. "offset0,offset0"
line.long 0x10C "GICDA_IPRIORITYR75,GICDA_IPRIORITYR75"
hexmask.long.byte 0x10C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x10C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x10C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x10C 0.--7. 1. "offset0,offset0"
line.long 0x110 "GICDA_IPRIORITYR76,GICDA_IPRIORITYR76"
hexmask.long.byte 0x110 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x110 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x110 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x110 0.--7. 1. "offset0,offset0"
line.long 0x114 "GICDA_IPRIORITYR77,GICDA_IPRIORITYR77"
hexmask.long.byte 0x114 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x114 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x114 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x114 0.--7. 1. "offset0,offset0"
line.long 0x118 "GICDA_IPRIORITYR78,GICDA_IPRIORITYR78"
hexmask.long.byte 0x118 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x118 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x118 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x118 0.--7. 1. "offset0,offset0"
line.long 0x11C "GICDA_IPRIORITYR79,GICDA_IPRIORITYR79"
hexmask.long.byte 0x11C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x11C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x11C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x11C 0.--7. 1. "offset0,offset0"
line.long 0x120 "GICDA_IPRIORITYR80,GICDA_IPRIORITYR80"
hexmask.long.byte 0x120 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x120 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x120 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x120 0.--7. 1. "offset0,offset0"
line.long 0x124 "GICDA_IPRIORITYR81,GICDA_IPRIORITYR81"
hexmask.long.byte 0x124 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x124 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x124 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x124 0.--7. 1. "offset0,offset0"
line.long 0x128 "GICDA_IPRIORITYR82,GICDA_IPRIORITYR82"
hexmask.long.byte 0x128 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x128 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x128 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x128 0.--7. 1. "offset0,offset0"
line.long 0x12C "GICDA_IPRIORITYR83,GICDA_IPRIORITYR83"
hexmask.long.byte 0x12C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x12C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x12C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x12C 0.--7. 1. "offset0,offset0"
line.long 0x130 "GICDA_IPRIORITYR84,GICDA_IPRIORITYR84"
hexmask.long.byte 0x130 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x130 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x130 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x130 0.--7. 1. "offset0,offset0"
line.long 0x134 "GICDA_IPRIORITYR85,GICDA_IPRIORITYR85"
hexmask.long.byte 0x134 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x134 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x134 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x134 0.--7. 1. "offset0,offset0"
line.long 0x138 "GICDA_IPRIORITYR86,GICDA_IPRIORITYR86"
hexmask.long.byte 0x138 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x138 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x138 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x138 0.--7. 1. "offset0,offset0"
line.long 0x13C "GICDA_IPRIORITYR87,GICDA_IPRIORITYR87"
hexmask.long.byte 0x13C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x13C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x13C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x13C 0.--7. 1. "offset0,offset0"
line.long 0x140 "GICDA_IPRIORITYR88,GICDA_IPRIORITYR88"
hexmask.long.byte 0x140 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x140 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x140 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x140 0.--7. 1. "offset0,offset0"
line.long 0x144 "GICDA_IPRIORITYR89,GICDA_IPRIORITYR89"
hexmask.long.byte 0x144 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x144 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x144 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x144 0.--7. 1. "offset0,offset0"
line.long 0x148 "GICDA_IPRIORITYR90,GICDA_IPRIORITYR90"
hexmask.long.byte 0x148 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x148 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x148 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x148 0.--7. 1. "offset0,offset0"
line.long 0x14C "GICDA_IPRIORITYR91,GICDA_IPRIORITYR91"
hexmask.long.byte 0x14C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x14C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x14C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x14C 0.--7. 1. "offset0,offset0"
line.long 0x150 "GICDA_IPRIORITYR92,GICDA_IPRIORITYR92"
hexmask.long.byte 0x150 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x150 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x150 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x150 0.--7. 1. "offset0,offset0"
line.long 0x154 "GICDA_IPRIORITYR93,GICDA_IPRIORITYR93"
hexmask.long.byte 0x154 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x154 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x154 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x154 0.--7. 1. "offset0,offset0"
line.long 0x158 "GICDA_IPRIORITYR94,GICDA_IPRIORITYR94"
hexmask.long.byte 0x158 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x158 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x158 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x158 0.--7. 1. "offset0,offset0"
line.long 0x15C "GICDA_IPRIORITYR95,GICDA_IPRIORITYR95"
hexmask.long.byte 0x15C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x15C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x15C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x15C 0.--7. 1. "offset0,offset0"
line.long 0x160 "GICDA_IPRIORITYR96,GICDA_IPRIORITYR96"
hexmask.long.byte 0x160 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x160 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x160 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x160 0.--7. 1. "offset0,offset0"
line.long 0x164 "GICDA_IPRIORITYR97,GICDA_IPRIORITYR97"
hexmask.long.byte 0x164 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x164 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x164 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x164 0.--7. 1. "offset0,offset0"
line.long 0x168 "GICDA_IPRIORITYR98,GICDA_IPRIORITYR98"
hexmask.long.byte 0x168 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x168 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x168 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x168 0.--7. 1. "offset0,offset0"
line.long 0x16C "GICDA_IPRIORITYR99,GICDA_IPRIORITYR99"
hexmask.long.byte 0x16C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x16C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x16C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x16C 0.--7. 1. "offset0,offset0"
line.long 0x170 "GICDA_IPRIORITYR100,GICDA_IPRIORITYR100"
hexmask.long.byte 0x170 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x170 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x170 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x170 0.--7. 1. "offset0,offset0"
line.long 0x174 "GICDA_IPRIORITYR101,GICDA_IPRIORITYR101"
hexmask.long.byte 0x174 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x174 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x174 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x174 0.--7. 1. "offset0,offset0"
line.long 0x178 "GICDA_IPRIORITYR102,GICDA_IPRIORITYR102"
hexmask.long.byte 0x178 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x178 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x178 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x178 0.--7. 1. "offset0,offset0"
line.long 0x17C "GICDA_IPRIORITYR103,GICDA_IPRIORITYR103"
hexmask.long.byte 0x17C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x17C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x17C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x17C 0.--7. 1. "offset0,offset0"
line.long 0x180 "GICDA_IPRIORITYR104,GICDA_IPRIORITYR104"
hexmask.long.byte 0x180 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x180 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x180 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x180 0.--7. 1. "offset0,offset0"
line.long 0x184 "GICDA_IPRIORITYR105,GICDA_IPRIORITYR105"
hexmask.long.byte 0x184 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x184 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x184 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x184 0.--7. 1. "offset0,offset0"
line.long 0x188 "GICDA_IPRIORITYR106,GICDA_IPRIORITYR106"
hexmask.long.byte 0x188 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x188 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x188 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x188 0.--7. 1. "offset0,offset0"
line.long 0x18C "GICDA_IPRIORITYR107,GICDA_IPRIORITYR107"
hexmask.long.byte 0x18C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x18C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x18C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x18C 0.--7. 1. "offset0,offset0"
line.long 0x190 "GICDA_IPRIORITYR108,GICDA_IPRIORITYR108"
hexmask.long.byte 0x190 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x190 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x190 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x190 0.--7. 1. "offset0,offset0"
line.long 0x194 "GICDA_IPRIORITYR109,GICDA_IPRIORITYR109"
hexmask.long.byte 0x194 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x194 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x194 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x194 0.--7. 1. "offset0,offset0"
line.long 0x198 "GICDA_IPRIORITYR110,GICDA_IPRIORITYR110"
hexmask.long.byte 0x198 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x198 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x198 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x198 0.--7. 1. "offset0,offset0"
line.long 0x19C "GICDA_IPRIORITYR111,GICDA_IPRIORITYR111"
hexmask.long.byte 0x19C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x19C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x19C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x19C 0.--7. 1. "offset0,offset0"
line.long 0x1A0 "GICDA_IPRIORITYR112,GICDA_IPRIORITYR112"
hexmask.long.byte 0x1A0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1A0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1A0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1A0 0.--7. 1. "offset0,offset0"
line.long 0x1A4 "GICDA_IPRIORITYR113,GICDA_IPRIORITYR113"
hexmask.long.byte 0x1A4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1A4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1A4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1A4 0.--7. 1. "offset0,offset0"
line.long 0x1A8 "GICDA_IPRIORITYR114,GICDA_IPRIORITYR114"
hexmask.long.byte 0x1A8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1A8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1A8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1A8 0.--7. 1. "offset0,offset0"
line.long 0x1AC "GICDA_IPRIORITYR115,GICDA_IPRIORITYR115"
hexmask.long.byte 0x1AC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1AC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1AC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1AC 0.--7. 1. "offset0,offset0"
line.long 0x1B0 "GICDA_IPRIORITYR116,GICDA_IPRIORITYR116"
hexmask.long.byte 0x1B0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1B0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1B0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1B0 0.--7. 1. "offset0,offset0"
line.long 0x1B4 "GICDA_IPRIORITYR117,GICDA_IPRIORITYR117"
hexmask.long.byte 0x1B4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1B4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1B4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1B4 0.--7. 1. "offset0,offset0"
line.long 0x1B8 "GICDA_IPRIORITYR118,GICDA_IPRIORITYR118"
hexmask.long.byte 0x1B8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1B8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1B8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1B8 0.--7. 1. "offset0,offset0"
line.long 0x1BC "GICDA_IPRIORITYR119,GICDA_IPRIORITYR119"
hexmask.long.byte 0x1BC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1BC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1BC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1BC 0.--7. 1. "offset0,offset0"
line.long 0x1C0 "GICDA_IPRIORITYR120,GICDA_IPRIORITYR120"
hexmask.long.byte 0x1C0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C0 0.--7. 1. "offset0,offset0"
line.long 0x1C4 "GICDA_IPRIORITYR121,GICDA_IPRIORITYR121"
hexmask.long.byte 0x1C4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C4 0.--7. 1. "offset0,offset0"
line.long 0x1C8 "GICDA_IPRIORITYR122,GICDA_IPRIORITYR122"
hexmask.long.byte 0x1C8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1C8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1C8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1C8 0.--7. 1. "offset0,offset0"
line.long 0x1CC "GICDA_IPRIORITYR123,GICDA_IPRIORITYR123"
hexmask.long.byte 0x1CC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1CC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1CC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1CC 0.--7. 1. "offset0,offset0"
line.long 0x1D0 "GICDA_IPRIORITYR124,GICDA_IPRIORITYR124"
hexmask.long.byte 0x1D0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1D0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1D0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1D0 0.--7. 1. "offset0,offset0"
line.long 0x1D4 "GICDA_IPRIORITYR125,GICDA_IPRIORITYR125"
hexmask.long.byte 0x1D4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1D4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1D4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1D4 0.--7. 1. "offset0,offset0"
line.long 0x1D8 "GICDA_IPRIORITYR126,GICDA_IPRIORITYR126"
hexmask.long.byte 0x1D8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1D8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1D8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1D8 0.--7. 1. "offset0,offset0"
line.long 0x1DC "GICDA_IPRIORITYR127,GICDA_IPRIORITYR127"
hexmask.long.byte 0x1DC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1DC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1DC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1DC 0.--7. 1. "offset0,offset0"
line.long 0x1E0 "GICDA_IPRIORITYR128,GICDA_IPRIORITYR128"
hexmask.long.byte 0x1E0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1E0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1E0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1E0 0.--7. 1. "offset0,offset0"
line.long 0x1E4 "GICDA_IPRIORITYR129,GICDA_IPRIORITYR129"
hexmask.long.byte 0x1E4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1E4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1E4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1E4 0.--7. 1. "offset0,offset0"
line.long 0x1E8 "GICDA_IPRIORITYR130,GICDA_IPRIORITYR130"
hexmask.long.byte 0x1E8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1E8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1E8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1E8 0.--7. 1. "offset0,offset0"
line.long 0x1EC "GICDA_IPRIORITYR131,GICDA_IPRIORITYR131"
hexmask.long.byte 0x1EC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1EC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1EC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1EC 0.--7. 1. "offset0,offset0"
line.long 0x1F0 "GICDA_IPRIORITYR132,GICDA_IPRIORITYR132"
hexmask.long.byte 0x1F0 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1F0 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1F0 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1F0 0.--7. 1. "offset0,offset0"
line.long 0x1F4 "GICDA_IPRIORITYR133,GICDA_IPRIORITYR133"
hexmask.long.byte 0x1F4 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1F4 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1F4 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1F4 0.--7. 1. "offset0,offset0"
line.long 0x1F8 "GICDA_IPRIORITYR134,GICDA_IPRIORITYR134"
hexmask.long.byte 0x1F8 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1F8 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1F8 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1F8 0.--7. 1. "offset0,offset0"
line.long 0x1FC "GICDA_IPRIORITYR135,GICDA_IPRIORITYR135"
hexmask.long.byte 0x1FC 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x1FC 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x1FC 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x1FC 0.--7. 1. "offset0,offset0"
line.long 0x200 "GICDA_IPRIORITYR136,GICDA_IPRIORITYR136"
hexmask.long.byte 0x200 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x200 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x200 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x200 0.--7. 1. "offset0,offset0"
line.long 0x204 "GICDA_IPRIORITYR137,GICDA_IPRIORITYR137"
hexmask.long.byte 0x204 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x204 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x204 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x204 0.--7. 1. "offset0,offset0"
line.long 0x208 "GICDA_IPRIORITYR138,GICDA_IPRIORITYR138"
hexmask.long.byte 0x208 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x208 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x208 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x208 0.--7. 1. "offset0,offset0"
line.long 0x20C "GICDA_IPRIORITYR139,GICDA_IPRIORITYR139"
hexmask.long.byte 0x20C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x20C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x20C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x20C 0.--7. 1. "offset0,offset0"
line.long 0x210 "GICDA_IPRIORITYR140,GICDA_IPRIORITYR140"
hexmask.long.byte 0x210 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x210 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x210 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x210 0.--7. 1. "offset0,offset0"
line.long 0x214 "GICDA_IPRIORITYR141,GICDA_IPRIORITYR141"
hexmask.long.byte 0x214 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x214 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x214 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x214 0.--7. 1. "offset0,offset0"
line.long 0x218 "GICDA_IPRIORITYR142,GICDA_IPRIORITYR142"
hexmask.long.byte 0x218 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x218 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x218 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x218 0.--7. 1. "offset0,offset0"
line.long 0x21C "GICDA_IPRIORITYR143,GICDA_IPRIORITYR143"
hexmask.long.byte 0x21C 24.--31. 1. "offset3,offset3"
hexmask.long.byte 0x21C 16.--23. 1. "offset2,offset2"
newline
hexmask.long.byte 0x21C 8.--15. 1. "offset1,offset1"
hexmask.long.byte 0x21C 0.--7. 1. "offset0,offset0"
group.long 0xE0C08++0x87
line.long 0x0 "GICDA_ICFGR2,GICDA_ICFGR2"
bitfld.long 0x0 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x0 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x0 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x0 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x0 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x0 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x0 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x0 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x0 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x4 "GICDA_ICFGR3,GICDA_ICFGR3"
bitfld.long 0x4 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x4 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x4 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x4 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x4 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x4 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x4 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x4 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x4 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x4 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x4 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x4 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x8 "GICDA_ICFGR4,GICDA_ICFGR4"
bitfld.long 0x8 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x8 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x8 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x8 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x8 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x8 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x8 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x8 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x8 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x8 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x8 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x8 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x8 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x8 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0xC "GICDA_ICFGR5,GICDA_ICFGR5"
bitfld.long 0xC 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0xC 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0xC 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0xC 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0xC 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0xC 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0xC 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0xC 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0xC 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0xC 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0xC 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0xC 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x10 "GICDA_ICFGR6,GICDA_ICFGR6"
bitfld.long 0x10 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x10 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x10 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x10 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x10 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x10 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x10 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x10 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x10 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x10 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x10 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x10 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x10 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x14 "GICDA_ICFGR7,GICDA_ICFGR7"
bitfld.long 0x14 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x14 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x14 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x14 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x14 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x14 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x14 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x14 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x14 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x14 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x14 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x14 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x14 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x14 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x14 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x18 "GICDA_ICFGR8,GICDA_ICFGR8"
bitfld.long 0x18 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x18 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x18 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x18 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x18 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x18 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x18 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x18 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x18 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x18 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x18 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x18 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x18 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x18 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x18 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x1C "GICDA_ICFGR9,GICDA_ICFGR9"
bitfld.long 0x1C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x1C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x1C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x1C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x1C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x1C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x1C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x1C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x1C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x1C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x1C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x1C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x1C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x1C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x20 "GICDA_ICFGR10,GICDA_ICFGR10"
bitfld.long 0x20 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x20 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x20 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x20 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x20 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x20 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x20 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x20 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x20 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x20 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x20 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x20 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x20 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x20 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x20 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x20 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x24 "GICDA_ICFGR11,GICDA_ICFGR11"
bitfld.long 0x24 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x24 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x24 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x24 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x24 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x24 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x24 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x24 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x24 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x24 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x24 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x24 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x24 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x24 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x24 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x28 "GICDA_ICFGR12,GICDA_ICFGR12"
bitfld.long 0x28 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x28 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x28 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x28 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x28 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x28 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x28 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x28 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x28 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x28 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x28 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x28 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x28 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x28 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x28 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x28 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x2C "GICDA_ICFGR13,GICDA_ICFGR13"
bitfld.long 0x2C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x2C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x2C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x2C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x2C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x2C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x2C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x2C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x2C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x2C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x2C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x2C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x2C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x2C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x2C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x2C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x30 "GICDA_ICFGR14,GICDA_ICFGR14"
bitfld.long 0x30 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x30 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x30 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x30 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x30 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x30 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x30 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x30 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x30 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x30 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x30 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x30 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x30 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x30 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x30 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x30 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x34 "GICDA_ICFGR15,GICDA_ICFGR15"
bitfld.long 0x34 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x34 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x34 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x34 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x34 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x34 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x34 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x34 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x34 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x34 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x34 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x34 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x34 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x34 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x34 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x38 "GICDA_ICFGR16,GICDA_ICFGR16"
bitfld.long 0x38 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x38 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x38 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x38 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x38 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x38 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x38 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x38 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x38 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x38 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x38 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x38 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x38 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x38 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x38 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x38 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x3C "GICDA_ICFGR17,GICDA_ICFGR17"
bitfld.long 0x3C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x3C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x3C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x3C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x3C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x3C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x3C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x3C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x3C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x3C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x3C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x3C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x3C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x3C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x3C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x3C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x40 "GICDA_ICFGR18,GICDA_ICFGR18"
bitfld.long 0x40 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x40 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x40 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x40 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x40 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x40 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x40 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x40 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x40 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x40 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x40 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x40 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x40 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x40 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x40 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x40 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x44 "GICDA_ICFGR19,GICDA_ICFGR19"
bitfld.long 0x44 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x44 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x44 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x44 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x44 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x44 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x44 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x44 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x44 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x44 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x44 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x44 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x44 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x44 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x44 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x44 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x48 "GICDA_ICFGR20,GICDA_ICFGR20"
bitfld.long 0x48 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x48 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x48 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x48 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x48 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x48 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x48 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x48 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x48 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x48 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x48 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x48 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x48 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x48 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x48 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x48 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x4C "GICDA_ICFGR21,GICDA_ICFGR21"
bitfld.long 0x4C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x4C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x4C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x4C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x4C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x4C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x4C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x4C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x4C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x4C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x4C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x4C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x4C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x4C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x4C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x4C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x50 "GICDA_ICFGR22,GICDA_ICFGR22"
bitfld.long 0x50 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x50 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x50 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x50 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x50 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x50 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x50 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x50 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x50 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x50 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x50 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x50 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x50 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x50 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x50 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x50 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x54 "GICDA_ICFGR23,GICDA_ICFGR23"
bitfld.long 0x54 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x54 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x54 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x54 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x54 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x54 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x54 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x54 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x54 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x54 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x54 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x54 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x54 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x54 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x54 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x54 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x58 "GICDA_ICFGR24,GICDA_ICFGR24"
bitfld.long 0x58 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x58 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x58 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x58 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x58 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x58 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x58 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x58 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x58 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x58 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x58 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x58 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x58 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x58 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x58 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x58 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x5C "GICDA_ICFGR25,GICDA_ICFGR25"
bitfld.long 0x5C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x5C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x5C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x5C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x5C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x5C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x5C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x5C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x5C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x5C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x5C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x5C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x5C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x5C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x5C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x5C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x60 "GICDA_ICFGR26,GICDA_ICFGR26"
bitfld.long 0x60 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x60 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x60 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x60 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x60 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x60 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x60 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x60 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x60 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x60 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x60 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x60 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x60 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x60 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x60 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x60 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x64 "GICDA_ICFGR27,GICDA_ICFGR27"
bitfld.long 0x64 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x64 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x64 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x64 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x64 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x64 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x64 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x64 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x64 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x64 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x64 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x64 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x64 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x64 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x64 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x64 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x68 "GICDA_ICFGR28,GICDA_ICFGR28"
bitfld.long 0x68 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x68 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x68 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x68 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x68 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x68 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x68 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x68 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x68 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x68 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x68 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x68 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x68 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x68 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x68 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x68 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x6C "GICDA_ICFGR29,GICDA_ICFGR29"
bitfld.long 0x6C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x6C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x6C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x6C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x6C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x6C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x6C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x6C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x6C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x6C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x6C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x6C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x6C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x6C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x6C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x6C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x70 "GICDA_ICFGR30,GICDA_ICFGR30"
bitfld.long 0x70 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x70 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x70 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x70 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x70 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x70 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x70 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x70 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x70 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x70 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x70 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x70 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x70 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x70 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x70 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x70 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x74 "GICDA_ICFGR31,GICDA_ICFGR31"
bitfld.long 0x74 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x74 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x74 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x74 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x74 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x74 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x74 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x74 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x74 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x74 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x74 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x74 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x74 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x74 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x74 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x74 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x78 "GICDA_ICFGR32,GICDA_ICFGR32"
bitfld.long 0x78 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x78 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x78 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x78 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x78 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x78 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x78 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x78 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x78 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x78 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x78 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x78 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x78 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x78 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x78 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x78 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x7C "GICDA_ICFGR33,GICDA_ICFGR33"
bitfld.long 0x7C 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x7C 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x7C 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x7C 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x7C 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x7C 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x7C 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x7C 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x7C 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x7C 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x7C 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x7C 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x7C 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x7C 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x7C 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x7C 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x80 "GICDA_ICFGR34,GICDA_ICFGR34"
bitfld.long 0x80 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x80 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x80 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x80 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x80 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x80 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x80 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x80 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x80 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x80 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x80 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x80 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x80 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x80 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x80 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x80 0.--1. "int_config0,int_config0" "0,1,2,3"
line.long 0x84 "GICDA_ICFGR35,GICDA_ICFGR35"
bitfld.long 0x84 30.--31. "int_config15,int_config15" "0,1,2,3"
bitfld.long 0x84 28.--29. "int_config14,int_config14" "0,1,2,3"
newline
bitfld.long 0x84 26.--27. "int_config13,int_config13" "0,1,2,3"
bitfld.long 0x84 24.--25. "int_config12,int_config12" "0,1,2,3"
newline
bitfld.long 0x84 22.--23. "int_config11,int_config11" "0,1,2,3"
bitfld.long 0x84 20.--21. "int_config10,int_config10" "0,1,2,3"
newline
bitfld.long 0x84 18.--19. "int_config9,int_config9" "0,1,2,3"
bitfld.long 0x84 16.--17. "int_config8,int_config8" "0,1,2,3"
newline
bitfld.long 0x84 14.--15. "int_config7,int_config7" "0,1,2,3"
bitfld.long 0x84 12.--13. "int_config6,int_config6" "0,1,2,3"
newline
bitfld.long 0x84 10.--11. "int_config5,int_config5" "0,1,2,3"
bitfld.long 0x84 8.--9. "int_config4,int_config4" "0,1,2,3"
newline
bitfld.long 0x84 6.--7. "int_config3,int_config3" "0,1,2,3"
bitfld.long 0x84 4.--5. "int_config2,int_config2" "0,1,2,3"
newline
bitfld.long 0x84 2.--3. "int_config1,int_config1" "0,1,2,3"
bitfld.long 0x84 0.--1. "int_config0,int_config0" "0,1,2,3"
group.long 0xE0D04++0x43
line.long 0x0 "GICDA_IGRPMODR1,GICDA_IGRPMODR1"
bitfld.long 0x0 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x0 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x0 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x0 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x0 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x0 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x0 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x0 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x0 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x0 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x0 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x0 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x0 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x0 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x0 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x0 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x0 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x0 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x0 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x0 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x0 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x0 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x0 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x0 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x0 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x0 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x0 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x0 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x0 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x0 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x0 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x0 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x4 "GICDA_IGRPMODR2,GICDA_IGRPMODR2"
bitfld.long 0x4 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x4 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x4 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x4 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x4 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x4 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x4 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x4 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x4 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x4 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x4 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x4 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x4 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x4 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x4 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x4 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x4 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x4 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x4 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x4 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x4 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x4 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x4 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x4 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x4 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x4 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x4 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x4 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x4 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x4 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x4 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x4 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x8 "GICDA_IGRPMODR3,GICDA_IGRPMODR3"
bitfld.long 0x8 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x8 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x8 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x8 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x8 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x8 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x8 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x8 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x8 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x8 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x8 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x8 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x8 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x8 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x8 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x8 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x8 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x8 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x8 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x8 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x8 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x8 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x8 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x8 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x8 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x8 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x8 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x8 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x8 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x8 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x8 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x8 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0xC "GICDA_IGRPMODR4,GICDA_IGRPMODR4"
bitfld.long 0xC 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0xC 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0xC 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0xC 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0xC 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0xC 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0xC 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0xC 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0xC 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0xC 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0xC 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0xC 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0xC 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0xC 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0xC 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0xC 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0xC 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0xC 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0xC 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0xC 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0xC 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0xC 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0xC 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0xC 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0xC 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0xC 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0xC 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0xC 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0xC 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0xC 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0xC 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0xC 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x10 "GICDA_IGRPMODR5,GICDA_IGRPMODR5"
bitfld.long 0x10 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x10 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x10 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x10 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x10 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x10 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x10 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x10 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x10 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x10 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x10 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x10 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x10 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x10 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x10 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x10 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x10 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x10 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x10 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x10 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x10 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x10 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x10 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x10 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x10 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x10 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x10 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x10 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x10 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x10 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x10 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x10 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x14 "GICDA_IGRPMODR6,GICDA_IGRPMODR6"
bitfld.long 0x14 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x14 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x14 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x14 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x14 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x14 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x14 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x14 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x14 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x14 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x14 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x14 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x14 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x14 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x14 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x14 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x14 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x14 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x14 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x14 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x14 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x14 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x14 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x14 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x14 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x14 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x14 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x14 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x14 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x14 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x14 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x14 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x18 "GICDA_IGRPMODR7,GICDA_IGRPMODR7"
bitfld.long 0x18 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x18 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x18 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x18 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x18 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x18 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x18 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x18 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x18 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x18 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x18 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x18 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x18 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x18 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x18 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x18 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x18 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x18 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x18 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x18 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x18 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x18 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x18 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x18 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x18 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x18 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x18 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x18 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x18 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x18 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x18 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x18 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x1C "GICDA_IGRPMODR8,GICDA_IGRPMODR8"
bitfld.long 0x1C 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x1C 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x1C 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x1C 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x1C 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x1C 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x1C 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x1C 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x1C 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x1C 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x1C 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x1C 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x1C 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x1C 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x1C 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x1C 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x1C 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x1C 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x1C 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x1C 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x1C 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x1C 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x1C 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x1C 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x1C 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x1C 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x1C 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x1C 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x1C 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x1C 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x1C 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x1C 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x20 "GICDA_IGRPMODR9,GICDA_IGRPMODR9"
bitfld.long 0x20 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x20 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x20 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x20 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x20 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x20 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x20 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x20 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x20 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x20 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x20 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x20 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x20 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x20 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x20 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x20 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x20 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x20 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x20 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x20 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x20 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x20 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x20 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x20 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x20 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x20 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x20 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x20 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x20 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x20 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x20 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x20 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x24 "GICDA_IGRPMODR10,GICDA_IGRPMODR10"
bitfld.long 0x24 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x24 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x24 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x24 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x24 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x24 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x24 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x24 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x24 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x24 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x24 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x24 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x24 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x24 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x24 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x24 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x24 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x24 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x24 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x24 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x24 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x24 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x24 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x24 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x24 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x24 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x24 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x24 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x24 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x24 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x24 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x24 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x28 "GICDA_IGRPMODR11,GICDA_IGRPMODR11"
bitfld.long 0x28 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x28 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x28 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x28 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x28 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x28 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x28 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x28 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x28 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x28 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x28 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x28 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x28 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x28 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x28 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x28 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x28 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x28 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x28 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x28 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x28 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x28 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x28 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x28 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x28 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x28 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x28 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x28 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x28 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x28 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x28 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x28 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x2C "GICDA_IGRPMODR12,GICDA_IGRPMODR12"
bitfld.long 0x2C 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x2C 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x2C 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x2C 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x2C 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x2C 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x2C 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x2C 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x2C 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x2C 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x2C 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x2C 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x2C 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x2C 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x2C 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x2C 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x2C 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x2C 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x2C 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x2C 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x2C 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x2C 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x2C 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x2C 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x2C 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x2C 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x2C 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x2C 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x2C 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x2C 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x2C 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x2C 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x30 "GICDA_IGRPMODR13,GICDA_IGRPMODR13"
bitfld.long 0x30 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x30 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x30 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x30 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x30 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x30 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x30 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x30 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x30 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x30 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x30 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x30 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x30 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x30 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x30 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x30 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x30 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x30 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x30 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x30 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x30 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x30 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x30 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x30 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x30 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x30 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x30 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x30 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x30 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x30 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x30 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x30 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x34 "GICDA_IGRPMODR14,GICDA_IGRPMODR14"
bitfld.long 0x34 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x34 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x34 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x34 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x34 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x34 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x34 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x34 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x34 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x34 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x34 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x34 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x34 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x34 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x34 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x34 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x34 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x34 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x34 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x34 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x34 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x34 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x34 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x34 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x34 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x34 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x34 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x34 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x34 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x34 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x34 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x34 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x38 "GICDA_IGRPMODR15,GICDA_IGRPMODR15"
bitfld.long 0x38 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x38 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x38 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x38 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x38 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x38 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x38 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x38 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x38 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x38 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x38 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x38 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x38 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x38 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x38 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x38 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x38 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x38 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x38 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x38 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x38 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x38 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x38 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x38 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x38 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x38 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x38 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x38 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x38 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x38 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x38 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x38 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x3C "GICDA_IGRPMODR16,GICDA_IGRPMODR16"
bitfld.long 0x3C 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x3C 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x3C 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x3C 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x3C 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x3C 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x3C 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x3C 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x3C 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x3C 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x3C 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x3C 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x3C 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x3C 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x3C 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x3C 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x3C 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x3C 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x3C 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x3C 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x3C 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x3C 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x3C 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x3C 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x3C 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x3C 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x3C 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x3C 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x3C 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x3C 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x3C 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x3C 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
line.long 0x40 "GICDA_IGRPMODR17,GICDA_IGRPMODR17"
bitfld.long 0x40 31. "group_modifier_bit31,group_modifier_bit31" "0,1"
bitfld.long 0x40 30. "group_modifier_bit30,group_modifier_bit30" "0,1"
newline
bitfld.long 0x40 29. "group_modifier_bit29,group_modifier_bit29" "0,1"
bitfld.long 0x40 28. "group_modifier_bit28,group_modifier_bit28" "0,1"
newline
bitfld.long 0x40 27. "group_modifier_bit27,group_modifier_bit27" "0,1"
bitfld.long 0x40 26. "group_modifier_bit26,group_modifier_bit26" "0,1"
newline
bitfld.long 0x40 25. "group_modifier_bit25,group_modifier_bit25" "0,1"
bitfld.long 0x40 24. "group_modifier_bit24,group_modifier_bit24" "0,1"
newline
bitfld.long 0x40 23. "group_modifier_bit23,group_modifier_bit23" "0,1"
bitfld.long 0x40 22. "group_modifier_bit22,group_modifier_bit22" "0,1"
newline
bitfld.long 0x40 21. "group_modifier_bit21,group_modifier_bit21" "0,1"
bitfld.long 0x40 20. "group_modifier_bit20,group_modifier_bit20" "0,1"
newline
bitfld.long 0x40 19. "group_modifier_bit19,group_modifier_bit19" "0,1"
bitfld.long 0x40 18. "group_modifier_bit18,group_modifier_bit18" "0,1"
newline
bitfld.long 0x40 17. "group_modifier_bit17,group_modifier_bit17" "0,1"
bitfld.long 0x40 16. "group_modifier_bit16,group_modifier_bit16" "0,1"
newline
bitfld.long 0x40 15. "group_modifier_bit15,group_modifier_bit15" "0,1"
bitfld.long 0x40 14. "group_modifier_bit14,group_modifier_bit14" "0,1"
newline
bitfld.long 0x40 13. "group_modifier_bit13,group_modifier_bit13" "0,1"
bitfld.long 0x40 12. "group_modifier_bit12,group_modifier_bit12" "0,1"
newline
bitfld.long 0x40 11. "group_modifier_bit11,group_modifier_bit11" "0,1"
bitfld.long 0x40 10. "group_modifier_bit10,group_modifier_bit10" "0,1"
newline
bitfld.long 0x40 9. "group_modifier_bit9,group_modifier_bit9" "0,1"
bitfld.long 0x40 8. "group_modifier_bit8,group_modifier_bit8" "0,1"
newline
bitfld.long 0x40 7. "group_modifier_bit7,group_modifier_bit7" "0,1"
bitfld.long 0x40 6. "group_modifier_bit6,group_modifier_bit6" "0,1"
newline
bitfld.long 0x40 5. "group_modifier_bit5,group_modifier_bit5" "0,1"
bitfld.long 0x40 4. "group_modifier_bit4,group_modifier_bit4" "0,1"
newline
bitfld.long 0x40 3. "group_modifier_bit3,group_modifier_bit3" "0,1"
bitfld.long 0x40 2. "group_modifier_bit2,group_modifier_bit2" "0,1"
newline
bitfld.long 0x40 1. "group_modifier_bit1,group_modifier_bit1" "0,1"
bitfld.long 0x40 0. "group_modifier_bit0,group_modifier_bit0" "0,1"
group.long 0xE0E08++0x87
line.long 0x0 "GICDA_NSACR2,GICDA_NSACR2"
bitfld.long 0x0 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x0 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x0 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x0 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x0 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x0 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x0 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x0 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x0 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x4 "GICDA_NSACR3,GICDA_NSACR3"
bitfld.long 0x4 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x4 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x4 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x4 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x4 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x4 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x4 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x4 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x4 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x4 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x4 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x4 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x8 "GICDA_NSACR4,GICDA_NSACR4"
bitfld.long 0x8 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x8 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x8 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x8 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x8 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x8 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x8 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x8 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x8 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x8 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x8 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x8 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x8 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x8 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0xC "GICDA_NSACR5,GICDA_NSACR5"
bitfld.long 0xC 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0xC 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0xC 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0xC 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0xC 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0xC 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0xC 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0xC 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0xC 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0xC 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0xC 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0xC 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x10 "GICDA_NSACR6,GICDA_NSACR6"
bitfld.long 0x10 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x10 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x10 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x10 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x10 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x10 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x10 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x10 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x10 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x10 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x10 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x10 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x10 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x14 "GICDA_NSACR7,GICDA_NSACR7"
bitfld.long 0x14 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x14 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x14 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x14 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x14 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x14 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x14 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x14 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x14 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x14 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x14 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x14 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x14 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x14 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x14 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x18 "GICDA_NSACR8,GICDA_NSACR8"
bitfld.long 0x18 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x18 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x18 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x18 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x18 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x18 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x18 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x18 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x18 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x18 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x18 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x18 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x18 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x18 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x18 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x1C "GICDA_NSACR9,GICDA_NSACR9"
bitfld.long 0x1C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x1C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x1C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x1C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x1C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x1C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x1C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x1C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x1C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x1C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x1C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x1C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x1C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x1C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x20 "GICDA_NSACR10,GICDA_NSACR10"
bitfld.long 0x20 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x20 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x20 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x20 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x20 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x20 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x20 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x20 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x20 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x20 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x20 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x20 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x20 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x20 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x20 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x20 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x24 "GICDA_NSACR11,GICDA_NSACR11"
bitfld.long 0x24 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x24 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x24 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x24 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x24 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x24 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x24 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x24 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x24 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x24 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x24 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x24 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x24 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x24 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x24 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x28 "GICDA_NSACR12,GICDA_NSACR12"
bitfld.long 0x28 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x28 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x28 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x28 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x28 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x28 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x28 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x28 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x28 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x28 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x28 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x28 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x28 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x28 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x28 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x28 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x2C "GICDA_NSACR13,GICDA_NSACR13"
bitfld.long 0x2C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x2C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x2C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x2C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x2C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x2C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x2C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x2C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x2C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x2C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x2C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x2C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x2C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x2C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x2C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x2C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x30 "GICDA_NSACR14,GICDA_NSACR14"
bitfld.long 0x30 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x30 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x30 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x30 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x30 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x30 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x30 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x30 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x30 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x30 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x30 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x30 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x30 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x30 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x30 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x30 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x34 "GICDA_NSACR15,GICDA_NSACR15"
bitfld.long 0x34 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x34 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x34 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x34 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x34 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x34 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x34 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x34 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x34 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x34 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x34 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x34 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x34 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x34 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x34 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x38 "GICDA_NSACR16,GICDA_NSACR16"
bitfld.long 0x38 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x38 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x38 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x38 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x38 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x38 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x38 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x38 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x38 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x38 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x38 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x38 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x38 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x38 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x38 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x38 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x3C "GICDA_NSACR17,GICDA_NSACR17"
bitfld.long 0x3C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x3C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x3C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x3C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x3C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x3C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x3C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x3C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x3C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x3C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x3C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x3C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x3C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x3C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x3C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x3C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x40 "GICDA_NSACR18,GICDA_NSACR18"
bitfld.long 0x40 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x40 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x40 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x40 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x40 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x40 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x40 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x40 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x40 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x40 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x40 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x40 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x40 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x40 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x40 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x40 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x44 "GICDA_NSACR19,GICDA_NSACR19"
bitfld.long 0x44 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x44 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x44 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x44 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x44 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x44 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x44 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x44 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x44 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x44 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x44 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x44 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x44 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x44 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x44 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x44 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x48 "GICDA_NSACR20,GICDA_NSACR20"
bitfld.long 0x48 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x48 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x48 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x48 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x48 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x48 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x48 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x48 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x48 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x48 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x48 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x48 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x48 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x48 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x48 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x48 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x4C "GICDA_NSACR21,GICDA_NSACR21"
bitfld.long 0x4C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x4C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x4C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x4C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x4C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x4C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x4C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x4C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x4C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x4C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x4C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x4C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x4C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x4C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x4C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x4C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x50 "GICDA_NSACR22,GICDA_NSACR22"
bitfld.long 0x50 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x50 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x50 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x50 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x50 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x50 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x50 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x50 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x50 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x50 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x50 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x50 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x50 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x50 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x50 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x50 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x54 "GICDA_NSACR23,GICDA_NSACR23"
bitfld.long 0x54 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x54 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x54 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x54 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x54 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x54 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x54 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x54 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x54 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x54 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x54 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x54 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x54 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x54 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x54 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x54 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x58 "GICDA_NSACR24,GICDA_NSACR24"
bitfld.long 0x58 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x58 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x58 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x58 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x58 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x58 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x58 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x58 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x58 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x58 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x58 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x58 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x58 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x58 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x58 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x58 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x5C "GICDA_NSACR25,GICDA_NSACR25"
bitfld.long 0x5C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x5C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x5C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x5C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x5C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x5C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x5C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x5C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x5C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x5C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x5C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x5C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x5C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x5C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x5C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x5C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x60 "GICDA_NSACR26,GICDA_NSACR26"
bitfld.long 0x60 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x60 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x60 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x60 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x60 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x60 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x60 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x60 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x60 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x60 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x60 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x60 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x60 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x60 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x60 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x60 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x64 "GICDA_NSACR27,GICDA_NSACR27"
bitfld.long 0x64 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x64 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x64 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x64 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x64 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x64 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x64 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x64 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x64 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x64 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x64 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x64 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x64 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x64 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x64 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x64 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x68 "GICDA_NSACR28,GICDA_NSACR28"
bitfld.long 0x68 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x68 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x68 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x68 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x68 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x68 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x68 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x68 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x68 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x68 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x68 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x68 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x68 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x68 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x68 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x68 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x6C "GICDA_NSACR29,GICDA_NSACR29"
bitfld.long 0x6C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x6C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x6C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x6C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x6C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x6C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x6C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x6C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x6C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x6C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x6C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x6C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x6C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x6C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x6C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x6C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x70 "GICDA_NSACR30,GICDA_NSACR30"
bitfld.long 0x70 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x70 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x70 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x70 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x70 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x70 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x70 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x70 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x70 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x70 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x70 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x70 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x70 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x70 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x70 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x70 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x74 "GICDA_NSACR31,GICDA_NSACR31"
bitfld.long 0x74 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x74 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x74 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x74 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x74 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x74 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x74 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x74 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x74 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x74 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x74 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x74 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x74 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x74 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x74 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x74 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x78 "GICDA_NSACR32,GICDA_NSACR32"
bitfld.long 0x78 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x78 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x78 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x78 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x78 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x78 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x78 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x78 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x78 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x78 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x78 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x78 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x78 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x78 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x78 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x78 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x7C "GICDA_NSACR33,GICDA_NSACR33"
bitfld.long 0x7C 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x7C 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x7C 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x7C 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x7C 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x7C 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x7C 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x7C 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x7C 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x7C 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x7C 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x7C 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x7C 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x7C 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x7C 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x7C 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x80 "GICDA_NSACR34,GICDA_NSACR34"
bitfld.long 0x80 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x80 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x80 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x80 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x80 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x80 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x80 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x80 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x80 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x80 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x80 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x80 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x80 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x80 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x80 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x80 0.--1. "ns_access0,ns_access0" "0,1,2,3"
line.long 0x84 "GICDA_NSACR35,GICDA_NSACR35"
bitfld.long 0x84 30.--31. "ns_access15,ns_access15" "0,1,2,3"
bitfld.long 0x84 28.--29. "ns_access14,ns_access14" "0,1,2,3"
newline
bitfld.long 0x84 26.--27. "ns_access13,ns_access13" "0,1,2,3"
bitfld.long 0x84 24.--25. "ns_access12,ns_access12" "0,1,2,3"
newline
bitfld.long 0x84 22.--23. "ns_access11,ns_access11" "0,1,2,3"
bitfld.long 0x84 20.--21. "ns_access10,ns_access10" "0,1,2,3"
newline
bitfld.long 0x84 18.--19. "ns_access9,ns_access9" "0,1,2,3"
bitfld.long 0x84 16.--17. "ns_access8,ns_access8" "0,1,2,3"
newline
bitfld.long 0x84 14.--15. "ns_access7,ns_access7" "0,1,2,3"
bitfld.long 0x84 12.--13. "ns_access6,ns_access6" "0,1,2,3"
newline
bitfld.long 0x84 10.--11. "ns_access5,ns_access5" "0,1,2,3"
bitfld.long 0x84 8.--9. "ns_access4,ns_access4" "0,1,2,3"
newline
bitfld.long 0x84 6.--7. "ns_access3,ns_access3" "0,1,2,3"
bitfld.long 0x84 4.--5. "ns_access2,ns_access2" "0,1,2,3"
newline
bitfld.long 0x84 2.--3. "ns_access1,ns_access1" "0,1,2,3"
bitfld.long 0x84 0.--1. "ns_access0,ns_access0" "0,1,2,3"
group.quad 0xE6100++0xFFF
line.quad 0x0 "GICDA_IROUTER32,GICDA_IROUTER32"
hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8 "GICDA_IROUTER33,GICDA_IROUTER33"
hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x10 "GICDA_IROUTER34,GICDA_IROUTER34"
hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x18 "GICDA_IROUTER35,GICDA_IROUTER35"
hexmask.quad.tbyte 0x18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x20 "GICDA_IROUTER36,GICDA_IROUTER36"
hexmask.quad.tbyte 0x20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x28 "GICDA_IROUTER37,GICDA_IROUTER37"
hexmask.quad.tbyte 0x28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x30 "GICDA_IROUTER38,GICDA_IROUTER38"
hexmask.quad.tbyte 0x30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x38 "GICDA_IROUTER39,GICDA_IROUTER39"
hexmask.quad.tbyte 0x38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x40 "GICDA_IROUTER40,GICDA_IROUTER40"
hexmask.quad.tbyte 0x40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x48 "GICDA_IROUTER41,GICDA_IROUTER41"
hexmask.quad.tbyte 0x48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x50 "GICDA_IROUTER42,GICDA_IROUTER42"
hexmask.quad.tbyte 0x50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x58 "GICDA_IROUTER43,GICDA_IROUTER43"
hexmask.quad.tbyte 0x58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x60 "GICDA_IROUTER44,GICDA_IROUTER44"
hexmask.quad.tbyte 0x60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x68 "GICDA_IROUTER45,GICDA_IROUTER45"
hexmask.quad.tbyte 0x68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x70 "GICDA_IROUTER46,GICDA_IROUTER46"
hexmask.quad.tbyte 0x70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x78 "GICDA_IROUTER47,GICDA_IROUTER47"
hexmask.quad.tbyte 0x78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x80 "GICDA_IROUTER48,GICDA_IROUTER48"
hexmask.quad.tbyte 0x80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x88 "GICDA_IROUTER49,GICDA_IROUTER49"
hexmask.quad.tbyte 0x88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x90 "GICDA_IROUTER50,GICDA_IROUTER50"
hexmask.quad.tbyte 0x90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x98 "GICDA_IROUTER51,GICDA_IROUTER51"
hexmask.quad.tbyte 0x98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA0 "GICDA_IROUTER52,GICDA_IROUTER52"
hexmask.quad.tbyte 0xA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA8 "GICDA_IROUTER53,GICDA_IROUTER53"
hexmask.quad.tbyte 0xA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB0 "GICDA_IROUTER54,GICDA_IROUTER54"
hexmask.quad.tbyte 0xB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB8 "GICDA_IROUTER55,GICDA_IROUTER55"
hexmask.quad.tbyte 0xB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC0 "GICDA_IROUTER56,GICDA_IROUTER56"
hexmask.quad.tbyte 0xC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC8 "GICDA_IROUTER57,GICDA_IROUTER57"
hexmask.quad.tbyte 0xC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD0 "GICDA_IROUTER58,GICDA_IROUTER58"
hexmask.quad.tbyte 0xD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD8 "GICDA_IROUTER59,GICDA_IROUTER59"
hexmask.quad.tbyte 0xD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE0 "GICDA_IROUTER60,GICDA_IROUTER60"
hexmask.quad.tbyte 0xE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE8 "GICDA_IROUTER61,GICDA_IROUTER61"
hexmask.quad.tbyte 0xE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF0 "GICDA_IROUTER62,GICDA_IROUTER62"
hexmask.quad.tbyte 0xF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF8 "GICDA_IROUTER63,GICDA_IROUTER63"
hexmask.quad.tbyte 0xF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x100 "GICDA_IROUTER64,GICDA_IROUTER64"
hexmask.quad.tbyte 0x100 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x100 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x100 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x100 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x100 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x100 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x100 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x108 "GICDA_IROUTER65,GICDA_IROUTER65"
hexmask.quad.tbyte 0x108 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x108 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x108 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x108 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x108 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x108 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x108 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x110 "GICDA_IROUTER66,GICDA_IROUTER66"
hexmask.quad.tbyte 0x110 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x110 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x110 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x110 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x110 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x110 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x110 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x118 "GICDA_IROUTER67,GICDA_IROUTER67"
hexmask.quad.tbyte 0x118 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x118 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x118 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x118 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x118 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x118 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x118 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x120 "GICDA_IROUTER68,GICDA_IROUTER68"
hexmask.quad.tbyte 0x120 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x120 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x120 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x120 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x120 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x120 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x120 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x128 "GICDA_IROUTER69,GICDA_IROUTER69"
hexmask.quad.tbyte 0x128 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x128 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x128 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x128 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x128 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x128 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x128 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x130 "GICDA_IROUTER70,GICDA_IROUTER70"
hexmask.quad.tbyte 0x130 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x130 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x130 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x130 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x130 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x130 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x130 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x138 "GICDA_IROUTER71,GICDA_IROUTER71"
hexmask.quad.tbyte 0x138 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x138 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x138 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x138 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x138 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x138 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x138 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x140 "GICDA_IROUTER72,GICDA_IROUTER72"
hexmask.quad.tbyte 0x140 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x140 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x140 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x140 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x140 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x140 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x140 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x148 "GICDA_IROUTER73,GICDA_IROUTER73"
hexmask.quad.tbyte 0x148 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x148 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x148 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x148 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x148 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x148 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x148 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x150 "GICDA_IROUTER74,GICDA_IROUTER74"
hexmask.quad.tbyte 0x150 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x150 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x150 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x150 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x150 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x150 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x150 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x158 "GICDA_IROUTER75,GICDA_IROUTER75"
hexmask.quad.tbyte 0x158 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x158 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x158 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x158 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x158 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x158 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x158 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x160 "GICDA_IROUTER76,GICDA_IROUTER76"
hexmask.quad.tbyte 0x160 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x160 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x160 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x160 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x160 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x160 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x160 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x168 "GICDA_IROUTER77,GICDA_IROUTER77"
hexmask.quad.tbyte 0x168 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x168 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x168 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x168 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x168 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x168 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x168 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x170 "GICDA_IROUTER78,GICDA_IROUTER78"
hexmask.quad.tbyte 0x170 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x170 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x170 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x170 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x170 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x170 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x170 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x178 "GICDA_IROUTER79,GICDA_IROUTER79"
hexmask.quad.tbyte 0x178 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x178 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x178 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x178 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x178 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x178 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x178 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x180 "GICDA_IROUTER80,GICDA_IROUTER80"
hexmask.quad.tbyte 0x180 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x180 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x180 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x180 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x180 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x180 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x180 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x188 "GICDA_IROUTER81,GICDA_IROUTER81"
hexmask.quad.tbyte 0x188 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x188 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x188 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x188 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x188 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x188 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x188 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x190 "GICDA_IROUTER82,GICDA_IROUTER82"
hexmask.quad.tbyte 0x190 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x190 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x190 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x190 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x190 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x190 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x190 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x198 "GICDA_IROUTER83,GICDA_IROUTER83"
hexmask.quad.tbyte 0x198 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x198 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x198 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x198 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x198 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x198 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x198 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1A0 "GICDA_IROUTER84,GICDA_IROUTER84"
hexmask.quad.tbyte 0x1A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1A8 "GICDA_IROUTER85,GICDA_IROUTER85"
hexmask.quad.tbyte 0x1A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1B0 "GICDA_IROUTER86,GICDA_IROUTER86"
hexmask.quad.tbyte 0x1B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1B8 "GICDA_IROUTER87,GICDA_IROUTER87"
hexmask.quad.tbyte 0x1B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1C0 "GICDA_IROUTER88,GICDA_IROUTER88"
hexmask.quad.tbyte 0x1C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1C8 "GICDA_IROUTER89,GICDA_IROUTER89"
hexmask.quad.tbyte 0x1C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1D0 "GICDA_IROUTER90,GICDA_IROUTER90"
hexmask.quad.tbyte 0x1D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1D8 "GICDA_IROUTER91,GICDA_IROUTER91"
hexmask.quad.tbyte 0x1D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1E0 "GICDA_IROUTER92,GICDA_IROUTER92"
hexmask.quad.tbyte 0x1E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1E8 "GICDA_IROUTER93,GICDA_IROUTER93"
hexmask.quad.tbyte 0x1E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1F0 "GICDA_IROUTER94,GICDA_IROUTER94"
hexmask.quad.tbyte 0x1F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x1F8 "GICDA_IROUTER95,GICDA_IROUTER95"
hexmask.quad.tbyte 0x1F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x1F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x1F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x1F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x1F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x1F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x1F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x200 "GICDA_IROUTER96,GICDA_IROUTER96"
hexmask.quad.tbyte 0x200 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x200 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x200 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x200 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x200 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x200 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x200 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x208 "GICDA_IROUTER97,GICDA_IROUTER97"
hexmask.quad.tbyte 0x208 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x208 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x208 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x208 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x208 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x208 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x208 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x210 "GICDA_IROUTER98,GICDA_IROUTER98"
hexmask.quad.tbyte 0x210 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x210 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x210 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x210 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x210 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x210 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x210 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x218 "GICDA_IROUTER99,GICDA_IROUTER99"
hexmask.quad.tbyte 0x218 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x218 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x218 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x218 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x218 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x218 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x218 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x220 "GICDA_IROUTER100,GICDA_IROUTER100"
hexmask.quad.tbyte 0x220 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x220 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x220 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x220 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x220 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x220 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x220 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x228 "GICDA_IROUTER101,GICDA_IROUTER101"
hexmask.quad.tbyte 0x228 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x228 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x228 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x228 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x228 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x228 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x228 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x230 "GICDA_IROUTER102,GICDA_IROUTER102"
hexmask.quad.tbyte 0x230 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x230 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x230 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x230 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x230 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x230 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x230 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x238 "GICDA_IROUTER103,GICDA_IROUTER103"
hexmask.quad.tbyte 0x238 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x238 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x238 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x238 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x238 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x238 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x238 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x240 "GICDA_IROUTER104,GICDA_IROUTER104"
hexmask.quad.tbyte 0x240 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x240 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x240 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x240 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x240 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x240 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x240 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x248 "GICDA_IROUTER105,GICDA_IROUTER105"
hexmask.quad.tbyte 0x248 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x248 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x248 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x248 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x248 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x248 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x248 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x250 "GICDA_IROUTER106,GICDA_IROUTER106"
hexmask.quad.tbyte 0x250 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x250 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x250 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x250 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x250 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x250 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x250 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x258 "GICDA_IROUTER107,GICDA_IROUTER107"
hexmask.quad.tbyte 0x258 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x258 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x258 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x258 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x258 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x258 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x258 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x260 "GICDA_IROUTER108,GICDA_IROUTER108"
hexmask.quad.tbyte 0x260 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x260 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x260 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x260 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x260 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x260 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x260 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x268 "GICDA_IROUTER109,GICDA_IROUTER109"
hexmask.quad.tbyte 0x268 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x268 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x268 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x268 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x268 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x268 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x268 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x270 "GICDA_IROUTER110,GICDA_IROUTER110"
hexmask.quad.tbyte 0x270 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x270 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x270 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x270 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x270 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x270 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x270 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x278 "GICDA_IROUTER111,GICDA_IROUTER111"
hexmask.quad.tbyte 0x278 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x278 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x278 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x278 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x278 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x278 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x278 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x280 "GICDA_IROUTER112,GICDA_IROUTER112"
hexmask.quad.tbyte 0x280 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x280 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x280 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x280 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x280 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x280 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x280 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x288 "GICDA_IROUTER113,GICDA_IROUTER113"
hexmask.quad.tbyte 0x288 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x288 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x288 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x288 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x288 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x288 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x288 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x290 "GICDA_IROUTER114,GICDA_IROUTER114"
hexmask.quad.tbyte 0x290 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x290 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x290 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x290 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x290 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x290 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x290 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x298 "GICDA_IROUTER115,GICDA_IROUTER115"
hexmask.quad.tbyte 0x298 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x298 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x298 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x298 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x298 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x298 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x298 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2A0 "GICDA_IROUTER116,GICDA_IROUTER116"
hexmask.quad.tbyte 0x2A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2A8 "GICDA_IROUTER117,GICDA_IROUTER117"
hexmask.quad.tbyte 0x2A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2B0 "GICDA_IROUTER118,GICDA_IROUTER118"
hexmask.quad.tbyte 0x2B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2B8 "GICDA_IROUTER119,GICDA_IROUTER119"
hexmask.quad.tbyte 0x2B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2C0 "GICDA_IROUTER120,GICDA_IROUTER120"
hexmask.quad.tbyte 0x2C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2C8 "GICDA_IROUTER121,GICDA_IROUTER121"
hexmask.quad.tbyte 0x2C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2D0 "GICDA_IROUTER122,GICDA_IROUTER122"
hexmask.quad.tbyte 0x2D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2D8 "GICDA_IROUTER123,GICDA_IROUTER123"
hexmask.quad.tbyte 0x2D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2E0 "GICDA_IROUTER124,GICDA_IROUTER124"
hexmask.quad.tbyte 0x2E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2E8 "GICDA_IROUTER125,GICDA_IROUTER125"
hexmask.quad.tbyte 0x2E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2F0 "GICDA_IROUTER126,GICDA_IROUTER126"
hexmask.quad.tbyte 0x2F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x2F8 "GICDA_IROUTER127,GICDA_IROUTER127"
hexmask.quad.tbyte 0x2F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x2F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x2F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x2F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x2F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x2F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x2F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x300 "GICDA_IROUTER128,GICDA_IROUTER128"
hexmask.quad.tbyte 0x300 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x300 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x300 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x300 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x300 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x300 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x300 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x308 "GICDA_IROUTER129,GICDA_IROUTER129"
hexmask.quad.tbyte 0x308 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x308 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x308 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x308 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x308 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x308 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x308 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x310 "GICDA_IROUTER130,GICDA_IROUTER130"
hexmask.quad.tbyte 0x310 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x310 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x310 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x310 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x310 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x310 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x310 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x318 "GICDA_IROUTER131,GICDA_IROUTER131"
hexmask.quad.tbyte 0x318 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x318 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x318 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x318 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x318 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x318 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x318 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x320 "GICDA_IROUTER132,GICDA_IROUTER132"
hexmask.quad.tbyte 0x320 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x320 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x320 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x320 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x320 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x320 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x320 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x328 "GICDA_IROUTER133,GICDA_IROUTER133"
hexmask.quad.tbyte 0x328 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x328 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x328 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x328 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x328 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x328 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x328 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x330 "GICDA_IROUTER134,GICDA_IROUTER134"
hexmask.quad.tbyte 0x330 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x330 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x330 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x330 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x330 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x330 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x330 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x338 "GICDA_IROUTER135,GICDA_IROUTER135"
hexmask.quad.tbyte 0x338 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x338 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x338 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x338 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x338 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x338 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x338 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x340 "GICDA_IROUTER136,GICDA_IROUTER136"
hexmask.quad.tbyte 0x340 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x340 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x340 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x340 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x340 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x340 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x340 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x348 "GICDA_IROUTER137,GICDA_IROUTER137"
hexmask.quad.tbyte 0x348 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x348 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x348 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x348 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x348 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x348 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x348 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x350 "GICDA_IROUTER138,GICDA_IROUTER138"
hexmask.quad.tbyte 0x350 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x350 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x350 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x350 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x350 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x350 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x350 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x358 "GICDA_IROUTER139,GICDA_IROUTER139"
hexmask.quad.tbyte 0x358 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x358 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x358 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x358 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x358 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x358 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x358 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x360 "GICDA_IROUTER140,GICDA_IROUTER140"
hexmask.quad.tbyte 0x360 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x360 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x360 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x360 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x360 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x360 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x360 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x368 "GICDA_IROUTER141,GICDA_IROUTER141"
hexmask.quad.tbyte 0x368 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x368 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x368 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x368 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x368 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x368 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x368 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x370 "GICDA_IROUTER142,GICDA_IROUTER142"
hexmask.quad.tbyte 0x370 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x370 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x370 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x370 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x370 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x370 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x370 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x378 "GICDA_IROUTER143,GICDA_IROUTER143"
hexmask.quad.tbyte 0x378 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x378 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x378 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x378 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x378 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x378 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x378 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x380 "GICDA_IROUTER144,GICDA_IROUTER144"
hexmask.quad.tbyte 0x380 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x380 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x380 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x380 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x380 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x380 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x380 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x388 "GICDA_IROUTER145,GICDA_IROUTER145"
hexmask.quad.tbyte 0x388 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x388 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x388 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x388 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x388 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x388 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x388 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x390 "GICDA_IROUTER146,GICDA_IROUTER146"
hexmask.quad.tbyte 0x390 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x390 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x390 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x390 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x390 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x390 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x390 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x398 "GICDA_IROUTER147,GICDA_IROUTER147"
hexmask.quad.tbyte 0x398 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x398 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x398 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x398 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x398 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x398 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x398 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3A0 "GICDA_IROUTER148,GICDA_IROUTER148"
hexmask.quad.tbyte 0x3A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3A8 "GICDA_IROUTER149,GICDA_IROUTER149"
hexmask.quad.tbyte 0x3A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3B0 "GICDA_IROUTER150,GICDA_IROUTER150"
hexmask.quad.tbyte 0x3B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3B8 "GICDA_IROUTER151,GICDA_IROUTER151"
hexmask.quad.tbyte 0x3B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3C0 "GICDA_IROUTER152,GICDA_IROUTER152"
hexmask.quad.tbyte 0x3C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3C8 "GICDA_IROUTER153,GICDA_IROUTER153"
hexmask.quad.tbyte 0x3C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3D0 "GICDA_IROUTER154,GICDA_IROUTER154"
hexmask.quad.tbyte 0x3D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3D8 "GICDA_IROUTER155,GICDA_IROUTER155"
hexmask.quad.tbyte 0x3D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3E0 "GICDA_IROUTER156,GICDA_IROUTER156"
hexmask.quad.tbyte 0x3E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3E8 "GICDA_IROUTER157,GICDA_IROUTER157"
hexmask.quad.tbyte 0x3E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3F0 "GICDA_IROUTER158,GICDA_IROUTER158"
hexmask.quad.tbyte 0x3F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x3F8 "GICDA_IROUTER159,GICDA_IROUTER159"
hexmask.quad.tbyte 0x3F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x3F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x3F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x3F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x3F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x3F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x3F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x400 "GICDA_IROUTER160,GICDA_IROUTER160"
hexmask.quad.tbyte 0x400 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x400 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x400 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x400 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x400 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x400 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x400 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x408 "GICDA_IROUTER161,GICDA_IROUTER161"
hexmask.quad.tbyte 0x408 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x408 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x408 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x408 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x408 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x408 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x408 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x410 "GICDA_IROUTER162,GICDA_IROUTER162"
hexmask.quad.tbyte 0x410 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x410 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x410 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x410 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x410 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x410 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x410 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x418 "GICDA_IROUTER163,GICDA_IROUTER163"
hexmask.quad.tbyte 0x418 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x418 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x418 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x418 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x418 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x418 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x418 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x420 "GICDA_IROUTER164,GICDA_IROUTER164"
hexmask.quad.tbyte 0x420 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x420 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x420 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x420 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x420 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x420 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x420 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x428 "GICDA_IROUTER165,GICDA_IROUTER165"
hexmask.quad.tbyte 0x428 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x428 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x428 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x428 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x428 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x428 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x428 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x430 "GICDA_IROUTER166,GICDA_IROUTER166"
hexmask.quad.tbyte 0x430 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x430 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x430 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x430 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x430 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x430 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x430 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x438 "GICDA_IROUTER167,GICDA_IROUTER167"
hexmask.quad.tbyte 0x438 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x438 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x438 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x438 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x438 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x438 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x438 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x440 "GICDA_IROUTER168,GICDA_IROUTER168"
hexmask.quad.tbyte 0x440 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x440 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x440 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x440 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x440 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x440 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x440 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x448 "GICDA_IROUTER169,GICDA_IROUTER169"
hexmask.quad.tbyte 0x448 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x448 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x448 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x448 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x448 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x448 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x448 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x450 "GICDA_IROUTER170,GICDA_IROUTER170"
hexmask.quad.tbyte 0x450 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x450 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x450 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x450 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x450 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x450 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x450 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x458 "GICDA_IROUTER171,GICDA_IROUTER171"
hexmask.quad.tbyte 0x458 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x458 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x458 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x458 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x458 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x458 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x458 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x460 "GICDA_IROUTER172,GICDA_IROUTER172"
hexmask.quad.tbyte 0x460 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x460 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x460 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x460 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x460 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x460 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x460 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x468 "GICDA_IROUTER173,GICDA_IROUTER173"
hexmask.quad.tbyte 0x468 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x468 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x468 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x468 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x468 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x468 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x468 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x470 "GICDA_IROUTER174,GICDA_IROUTER174"
hexmask.quad.tbyte 0x470 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x470 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x470 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x470 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x470 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x470 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x470 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x478 "GICDA_IROUTER175,GICDA_IROUTER175"
hexmask.quad.tbyte 0x478 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x478 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x478 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x478 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x478 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x478 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x478 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x480 "GICDA_IROUTER176,GICDA_IROUTER176"
hexmask.quad.tbyte 0x480 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x480 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x480 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x480 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x480 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x480 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x480 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x488 "GICDA_IROUTER177,GICDA_IROUTER177"
hexmask.quad.tbyte 0x488 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x488 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x488 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x488 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x488 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x488 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x488 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x490 "GICDA_IROUTER178,GICDA_IROUTER178"
hexmask.quad.tbyte 0x490 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x490 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x490 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x490 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x490 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x490 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x490 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x498 "GICDA_IROUTER179,GICDA_IROUTER179"
hexmask.quad.tbyte 0x498 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x498 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x498 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x498 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x498 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x498 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x498 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4A0 "GICDA_IROUTER180,GICDA_IROUTER180"
hexmask.quad.tbyte 0x4A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4A8 "GICDA_IROUTER181,GICDA_IROUTER181"
hexmask.quad.tbyte 0x4A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4B0 "GICDA_IROUTER182,GICDA_IROUTER182"
hexmask.quad.tbyte 0x4B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4B8 "GICDA_IROUTER183,GICDA_IROUTER183"
hexmask.quad.tbyte 0x4B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4C0 "GICDA_IROUTER184,GICDA_IROUTER184"
hexmask.quad.tbyte 0x4C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4C8 "GICDA_IROUTER185,GICDA_IROUTER185"
hexmask.quad.tbyte 0x4C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4D0 "GICDA_IROUTER186,GICDA_IROUTER186"
hexmask.quad.tbyte 0x4D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4D8 "GICDA_IROUTER187,GICDA_IROUTER187"
hexmask.quad.tbyte 0x4D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4E0 "GICDA_IROUTER188,GICDA_IROUTER188"
hexmask.quad.tbyte 0x4E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4E8 "GICDA_IROUTER189,GICDA_IROUTER189"
hexmask.quad.tbyte 0x4E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4F0 "GICDA_IROUTER190,GICDA_IROUTER190"
hexmask.quad.tbyte 0x4F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x4F8 "GICDA_IROUTER191,GICDA_IROUTER191"
hexmask.quad.tbyte 0x4F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x4F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x4F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x4F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x4F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x4F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x4F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x500 "GICDA_IROUTER192,GICDA_IROUTER192"
hexmask.quad.tbyte 0x500 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x500 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x500 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x500 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x500 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x500 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x500 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x508 "GICDA_IROUTER193,GICDA_IROUTER193"
hexmask.quad.tbyte 0x508 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x508 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x508 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x508 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x508 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x508 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x508 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x510 "GICDA_IROUTER194,GICDA_IROUTER194"
hexmask.quad.tbyte 0x510 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x510 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x510 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x510 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x510 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x510 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x510 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x518 "GICDA_IROUTER195,GICDA_IROUTER195"
hexmask.quad.tbyte 0x518 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x518 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x518 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x518 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x518 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x518 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x518 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x520 "GICDA_IROUTER196,GICDA_IROUTER196"
hexmask.quad.tbyte 0x520 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x520 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x520 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x520 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x520 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x520 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x520 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x528 "GICDA_IROUTER197,GICDA_IROUTER197"
hexmask.quad.tbyte 0x528 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x528 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x528 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x528 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x528 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x528 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x528 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x530 "GICDA_IROUTER198,GICDA_IROUTER198"
hexmask.quad.tbyte 0x530 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x530 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x530 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x530 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x530 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x530 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x530 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x538 "GICDA_IROUTER199,GICDA_IROUTER199"
hexmask.quad.tbyte 0x538 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x538 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x538 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x538 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x538 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x538 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x538 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x540 "GICDA_IROUTER200,GICDA_IROUTER200"
hexmask.quad.tbyte 0x540 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x540 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x540 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x540 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x540 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x540 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x540 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x548 "GICDA_IROUTER201,GICDA_IROUTER201"
hexmask.quad.tbyte 0x548 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x548 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x548 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x548 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x548 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x548 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x548 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x550 "GICDA_IROUTER202,GICDA_IROUTER202"
hexmask.quad.tbyte 0x550 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x550 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x550 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x550 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x550 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x550 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x550 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x558 "GICDA_IROUTER203,GICDA_IROUTER203"
hexmask.quad.tbyte 0x558 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x558 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x558 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x558 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x558 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x558 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x558 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x560 "GICDA_IROUTER204,GICDA_IROUTER204"
hexmask.quad.tbyte 0x560 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x560 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x560 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x560 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x560 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x560 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x560 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x568 "GICDA_IROUTER205,GICDA_IROUTER205"
hexmask.quad.tbyte 0x568 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x568 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x568 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x568 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x568 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x568 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x568 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x570 "GICDA_IROUTER206,GICDA_IROUTER206"
hexmask.quad.tbyte 0x570 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x570 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x570 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x570 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x570 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x570 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x570 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x578 "GICDA_IROUTER207,GICDA_IROUTER207"
hexmask.quad.tbyte 0x578 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x578 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x578 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x578 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x578 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x578 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x578 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x580 "GICDA_IROUTER208,GICDA_IROUTER208"
hexmask.quad.tbyte 0x580 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x580 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x580 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x580 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x580 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x580 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x580 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x588 "GICDA_IROUTER209,GICDA_IROUTER209"
hexmask.quad.tbyte 0x588 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x588 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x588 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x588 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x588 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x588 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x588 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x590 "GICDA_IROUTER210,GICDA_IROUTER210"
hexmask.quad.tbyte 0x590 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x590 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x590 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x590 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x590 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x590 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x590 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x598 "GICDA_IROUTER211,GICDA_IROUTER211"
hexmask.quad.tbyte 0x598 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x598 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x598 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x598 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x598 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x598 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x598 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5A0 "GICDA_IROUTER212,GICDA_IROUTER212"
hexmask.quad.tbyte 0x5A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5A8 "GICDA_IROUTER213,GICDA_IROUTER213"
hexmask.quad.tbyte 0x5A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5B0 "GICDA_IROUTER214,GICDA_IROUTER214"
hexmask.quad.tbyte 0x5B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5B8 "GICDA_IROUTER215,GICDA_IROUTER215"
hexmask.quad.tbyte 0x5B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5C0 "GICDA_IROUTER216,GICDA_IROUTER216"
hexmask.quad.tbyte 0x5C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5C8 "GICDA_IROUTER217,GICDA_IROUTER217"
hexmask.quad.tbyte 0x5C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5D0 "GICDA_IROUTER218,GICDA_IROUTER218"
hexmask.quad.tbyte 0x5D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5D8 "GICDA_IROUTER219,GICDA_IROUTER219"
hexmask.quad.tbyte 0x5D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5E0 "GICDA_IROUTER220,GICDA_IROUTER220"
hexmask.quad.tbyte 0x5E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5E8 "GICDA_IROUTER221,GICDA_IROUTER221"
hexmask.quad.tbyte 0x5E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5F0 "GICDA_IROUTER222,GICDA_IROUTER222"
hexmask.quad.tbyte 0x5F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x5F8 "GICDA_IROUTER223,GICDA_IROUTER223"
hexmask.quad.tbyte 0x5F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x5F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x5F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x5F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x5F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x5F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x5F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x600 "GICDA_IROUTER224,GICDA_IROUTER224"
hexmask.quad.tbyte 0x600 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x600 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x600 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x600 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x600 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x600 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x600 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x608 "GICDA_IROUTER225,GICDA_IROUTER225"
hexmask.quad.tbyte 0x608 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x608 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x608 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x608 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x608 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x608 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x608 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x610 "GICDA_IROUTER226,GICDA_IROUTER226"
hexmask.quad.tbyte 0x610 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x610 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x610 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x610 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x610 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x610 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x610 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x618 "GICDA_IROUTER227,GICDA_IROUTER227"
hexmask.quad.tbyte 0x618 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x618 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x618 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x618 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x618 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x618 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x618 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x620 "GICDA_IROUTER228,GICDA_IROUTER228"
hexmask.quad.tbyte 0x620 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x620 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x620 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x620 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x620 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x620 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x620 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x628 "GICDA_IROUTER229,GICDA_IROUTER229"
hexmask.quad.tbyte 0x628 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x628 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x628 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x628 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x628 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x628 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x628 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x630 "GICDA_IROUTER230,GICDA_IROUTER230"
hexmask.quad.tbyte 0x630 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x630 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x630 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x630 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x630 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x630 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x630 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x638 "GICDA_IROUTER231,GICDA_IROUTER231"
hexmask.quad.tbyte 0x638 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x638 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x638 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x638 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x638 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x638 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x638 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x640 "GICDA_IROUTER232,GICDA_IROUTER232"
hexmask.quad.tbyte 0x640 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x640 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x640 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x640 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x640 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x640 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x640 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x648 "GICDA_IROUTER233,GICDA_IROUTER233"
hexmask.quad.tbyte 0x648 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x648 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x648 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x648 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x648 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x648 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x648 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x650 "GICDA_IROUTER234,GICDA_IROUTER234"
hexmask.quad.tbyte 0x650 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x650 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x650 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x650 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x650 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x650 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x650 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x658 "GICDA_IROUTER235,GICDA_IROUTER235"
hexmask.quad.tbyte 0x658 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x658 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x658 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x658 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x658 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x658 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x658 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x660 "GICDA_IROUTER236,GICDA_IROUTER236"
hexmask.quad.tbyte 0x660 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x660 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x660 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x660 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x660 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x660 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x660 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x668 "GICDA_IROUTER237,GICDA_IROUTER237"
hexmask.quad.tbyte 0x668 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x668 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x668 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x668 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x668 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x668 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x668 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x670 "GICDA_IROUTER238,GICDA_IROUTER238"
hexmask.quad.tbyte 0x670 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x670 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x670 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x670 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x670 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x670 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x670 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x678 "GICDA_IROUTER239,GICDA_IROUTER239"
hexmask.quad.tbyte 0x678 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x678 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x678 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x678 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x678 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x678 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x678 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x680 "GICDA_IROUTER240,GICDA_IROUTER240"
hexmask.quad.tbyte 0x680 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x680 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x680 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x680 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x680 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x680 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x680 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x688 "GICDA_IROUTER241,GICDA_IROUTER241"
hexmask.quad.tbyte 0x688 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x688 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x688 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x688 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x688 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x688 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x688 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x690 "GICDA_IROUTER242,GICDA_IROUTER242"
hexmask.quad.tbyte 0x690 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x690 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x690 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x690 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x690 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x690 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x690 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x698 "GICDA_IROUTER243,GICDA_IROUTER243"
hexmask.quad.tbyte 0x698 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x698 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x698 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x698 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x698 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x698 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x698 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6A0 "GICDA_IROUTER244,GICDA_IROUTER244"
hexmask.quad.tbyte 0x6A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6A8 "GICDA_IROUTER245,GICDA_IROUTER245"
hexmask.quad.tbyte 0x6A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6B0 "GICDA_IROUTER246,GICDA_IROUTER246"
hexmask.quad.tbyte 0x6B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6B8 "GICDA_IROUTER247,GICDA_IROUTER247"
hexmask.quad.tbyte 0x6B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6C0 "GICDA_IROUTER248,GICDA_IROUTER248"
hexmask.quad.tbyte 0x6C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6C8 "GICDA_IROUTER249,GICDA_IROUTER249"
hexmask.quad.tbyte 0x6C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6D0 "GICDA_IROUTER250,GICDA_IROUTER250"
hexmask.quad.tbyte 0x6D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6D8 "GICDA_IROUTER251,GICDA_IROUTER251"
hexmask.quad.tbyte 0x6D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6E0 "GICDA_IROUTER252,GICDA_IROUTER252"
hexmask.quad.tbyte 0x6E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6E8 "GICDA_IROUTER253,GICDA_IROUTER253"
hexmask.quad.tbyte 0x6E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6F0 "GICDA_IROUTER254,GICDA_IROUTER254"
hexmask.quad.tbyte 0x6F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x6F8 "GICDA_IROUTER255,GICDA_IROUTER255"
hexmask.quad.tbyte 0x6F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x6F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x6F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x6F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x6F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x6F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x6F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x700 "GICDA_IROUTER256,GICDA_IROUTER256"
hexmask.quad.tbyte 0x700 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x700 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x700 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x700 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x700 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x700 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x700 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x708 "GICDA_IROUTER257,GICDA_IROUTER257"
hexmask.quad.tbyte 0x708 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x708 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x708 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x708 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x708 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x708 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x708 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x710 "GICDA_IROUTER258,GICDA_IROUTER258"
hexmask.quad.tbyte 0x710 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x710 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x710 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x710 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x710 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x710 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x710 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x718 "GICDA_IROUTER259,GICDA_IROUTER259"
hexmask.quad.tbyte 0x718 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x718 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x718 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x718 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x718 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x718 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x718 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x720 "GICDA_IROUTER260,GICDA_IROUTER260"
hexmask.quad.tbyte 0x720 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x720 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x720 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x720 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x720 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x720 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x720 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x728 "GICDA_IROUTER261,GICDA_IROUTER261"
hexmask.quad.tbyte 0x728 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x728 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x728 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x728 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x728 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x728 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x728 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x730 "GICDA_IROUTER262,GICDA_IROUTER262"
hexmask.quad.tbyte 0x730 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x730 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x730 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x730 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x730 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x730 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x730 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x738 "GICDA_IROUTER263,GICDA_IROUTER263"
hexmask.quad.tbyte 0x738 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x738 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x738 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x738 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x738 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x738 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x738 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x740 "GICDA_IROUTER264,GICDA_IROUTER264"
hexmask.quad.tbyte 0x740 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x740 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x740 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x740 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x740 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x740 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x740 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x748 "GICDA_IROUTER265,GICDA_IROUTER265"
hexmask.quad.tbyte 0x748 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x748 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x748 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x748 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x748 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x748 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x748 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x750 "GICDA_IROUTER266,GICDA_IROUTER266"
hexmask.quad.tbyte 0x750 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x750 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x750 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x750 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x750 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x750 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x750 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x758 "GICDA_IROUTER267,GICDA_IROUTER267"
hexmask.quad.tbyte 0x758 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x758 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x758 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x758 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x758 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x758 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x758 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x760 "GICDA_IROUTER268,GICDA_IROUTER268"
hexmask.quad.tbyte 0x760 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x760 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x760 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x760 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x760 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x760 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x760 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x768 "GICDA_IROUTER269,GICDA_IROUTER269"
hexmask.quad.tbyte 0x768 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x768 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x768 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x768 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x768 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x768 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x768 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x770 "GICDA_IROUTER270,GICDA_IROUTER270"
hexmask.quad.tbyte 0x770 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x770 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x770 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x770 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x770 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x770 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x770 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x778 "GICDA_IROUTER271,GICDA_IROUTER271"
hexmask.quad.tbyte 0x778 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x778 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x778 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x778 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x778 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x778 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x778 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x780 "GICDA_IROUTER272,GICDA_IROUTER272"
hexmask.quad.tbyte 0x780 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x780 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x780 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x780 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x780 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x780 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x780 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x788 "GICDA_IROUTER273,GICDA_IROUTER273"
hexmask.quad.tbyte 0x788 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x788 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x788 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x788 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x788 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x788 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x788 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x790 "GICDA_IROUTER274,GICDA_IROUTER274"
hexmask.quad.tbyte 0x790 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x790 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x790 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x790 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x790 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x790 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x790 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x798 "GICDA_IROUTER275,GICDA_IROUTER275"
hexmask.quad.tbyte 0x798 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x798 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x798 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x798 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x798 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x798 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x798 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7A0 "GICDA_IROUTER276,GICDA_IROUTER276"
hexmask.quad.tbyte 0x7A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7A8 "GICDA_IROUTER277,GICDA_IROUTER277"
hexmask.quad.tbyte 0x7A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7B0 "GICDA_IROUTER278,GICDA_IROUTER278"
hexmask.quad.tbyte 0x7B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7B8 "GICDA_IROUTER279,GICDA_IROUTER279"
hexmask.quad.tbyte 0x7B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7C0 "GICDA_IROUTER280,GICDA_IROUTER280"
hexmask.quad.tbyte 0x7C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7C8 "GICDA_IROUTER281,GICDA_IROUTER281"
hexmask.quad.tbyte 0x7C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7D0 "GICDA_IROUTER282,GICDA_IROUTER282"
hexmask.quad.tbyte 0x7D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7D8 "GICDA_IROUTER283,GICDA_IROUTER283"
hexmask.quad.tbyte 0x7D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7E0 "GICDA_IROUTER284,GICDA_IROUTER284"
hexmask.quad.tbyte 0x7E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7E8 "GICDA_IROUTER285,GICDA_IROUTER285"
hexmask.quad.tbyte 0x7E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7F0 "GICDA_IROUTER286,GICDA_IROUTER286"
hexmask.quad.tbyte 0x7F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x7F8 "GICDA_IROUTER287,GICDA_IROUTER287"
hexmask.quad.tbyte 0x7F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x7F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x7F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x7F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x7F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x7F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x7F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x800 "GICDA_IROUTER288,GICDA_IROUTER288"
hexmask.quad.tbyte 0x800 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x800 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x800 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x800 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x800 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x800 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x800 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x808 "GICDA_IROUTER289,GICDA_IROUTER289"
hexmask.quad.tbyte 0x808 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x808 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x808 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x808 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x808 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x808 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x808 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x810 "GICDA_IROUTER290,GICDA_IROUTER290"
hexmask.quad.tbyte 0x810 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x810 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x810 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x810 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x810 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x810 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x810 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x818 "GICDA_IROUTER291,GICDA_IROUTER291"
hexmask.quad.tbyte 0x818 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x818 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x818 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x818 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x818 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x818 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x818 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x820 "GICDA_IROUTER292,GICDA_IROUTER292"
hexmask.quad.tbyte 0x820 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x820 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x820 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x820 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x820 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x820 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x820 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x828 "GICDA_IROUTER293,GICDA_IROUTER293"
hexmask.quad.tbyte 0x828 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x828 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x828 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x828 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x828 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x828 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x828 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x830 "GICDA_IROUTER294,GICDA_IROUTER294"
hexmask.quad.tbyte 0x830 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x830 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x830 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x830 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x830 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x830 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x830 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x838 "GICDA_IROUTER295,GICDA_IROUTER295"
hexmask.quad.tbyte 0x838 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x838 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x838 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x838 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x838 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x838 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x838 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x840 "GICDA_IROUTER296,GICDA_IROUTER296"
hexmask.quad.tbyte 0x840 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x840 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x840 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x840 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x840 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x840 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x840 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x848 "GICDA_IROUTER297,GICDA_IROUTER297"
hexmask.quad.tbyte 0x848 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x848 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x848 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x848 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x848 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x848 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x848 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x850 "GICDA_IROUTER298,GICDA_IROUTER298"
hexmask.quad.tbyte 0x850 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x850 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x850 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x850 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x850 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x850 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x850 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x858 "GICDA_IROUTER299,GICDA_IROUTER299"
hexmask.quad.tbyte 0x858 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x858 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x858 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x858 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x858 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x858 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x858 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x860 "GICDA_IROUTER300,GICDA_IROUTER300"
hexmask.quad.tbyte 0x860 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x860 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x860 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x860 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x860 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x860 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x860 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x868 "GICDA_IROUTER301,GICDA_IROUTER301"
hexmask.quad.tbyte 0x868 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x868 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x868 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x868 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x868 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x868 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x868 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x870 "GICDA_IROUTER302,GICDA_IROUTER302"
hexmask.quad.tbyte 0x870 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x870 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x870 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x870 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x870 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x870 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x870 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x878 "GICDA_IROUTER303,GICDA_IROUTER303"
hexmask.quad.tbyte 0x878 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x878 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x878 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x878 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x878 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x878 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x878 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x880 "GICDA_IROUTER304,GICDA_IROUTER304"
hexmask.quad.tbyte 0x880 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x880 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x880 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x880 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x880 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x880 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x880 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x888 "GICDA_IROUTER305,GICDA_IROUTER305"
hexmask.quad.tbyte 0x888 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x888 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x888 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x888 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x888 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x888 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x888 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x890 "GICDA_IROUTER306,GICDA_IROUTER306"
hexmask.quad.tbyte 0x890 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x890 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x890 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x890 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x890 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x890 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x890 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x898 "GICDA_IROUTER307,GICDA_IROUTER307"
hexmask.quad.tbyte 0x898 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x898 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x898 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x898 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x898 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x898 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x898 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8A0 "GICDA_IROUTER308,GICDA_IROUTER308"
hexmask.quad.tbyte 0x8A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8A8 "GICDA_IROUTER309,GICDA_IROUTER309"
hexmask.quad.tbyte 0x8A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8B0 "GICDA_IROUTER310,GICDA_IROUTER310"
hexmask.quad.tbyte 0x8B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8B8 "GICDA_IROUTER311,GICDA_IROUTER311"
hexmask.quad.tbyte 0x8B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8C0 "GICDA_IROUTER312,GICDA_IROUTER312"
hexmask.quad.tbyte 0x8C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8C8 "GICDA_IROUTER313,GICDA_IROUTER313"
hexmask.quad.tbyte 0x8C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8D0 "GICDA_IROUTER314,GICDA_IROUTER314"
hexmask.quad.tbyte 0x8D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8D8 "GICDA_IROUTER315,GICDA_IROUTER315"
hexmask.quad.tbyte 0x8D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8E0 "GICDA_IROUTER316,GICDA_IROUTER316"
hexmask.quad.tbyte 0x8E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8E8 "GICDA_IROUTER317,GICDA_IROUTER317"
hexmask.quad.tbyte 0x8E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8F0 "GICDA_IROUTER318,GICDA_IROUTER318"
hexmask.quad.tbyte 0x8F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8F8 "GICDA_IROUTER319,GICDA_IROUTER319"
hexmask.quad.tbyte 0x8F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x900 "GICDA_IROUTER320,GICDA_IROUTER320"
hexmask.quad.tbyte 0x900 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x900 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x900 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x900 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x900 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x900 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x900 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x908 "GICDA_IROUTER321,GICDA_IROUTER321"
hexmask.quad.tbyte 0x908 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x908 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x908 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x908 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x908 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x908 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x908 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x910 "GICDA_IROUTER322,GICDA_IROUTER322"
hexmask.quad.tbyte 0x910 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x910 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x910 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x910 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x910 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x910 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x910 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x918 "GICDA_IROUTER323,GICDA_IROUTER323"
hexmask.quad.tbyte 0x918 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x918 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x918 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x918 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x918 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x918 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x918 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x920 "GICDA_IROUTER324,GICDA_IROUTER324"
hexmask.quad.tbyte 0x920 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x920 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x920 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x920 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x920 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x920 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x920 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x928 "GICDA_IROUTER325,GICDA_IROUTER325"
hexmask.quad.tbyte 0x928 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x928 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x928 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x928 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x928 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x928 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x928 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x930 "GICDA_IROUTER326,GICDA_IROUTER326"
hexmask.quad.tbyte 0x930 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x930 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x930 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x930 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x930 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x930 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x930 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x938 "GICDA_IROUTER327,GICDA_IROUTER327"
hexmask.quad.tbyte 0x938 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x938 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x938 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x938 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x938 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x938 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x938 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x940 "GICDA_IROUTER328,GICDA_IROUTER328"
hexmask.quad.tbyte 0x940 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x940 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x940 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x940 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x940 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x940 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x940 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x948 "GICDA_IROUTER329,GICDA_IROUTER329"
hexmask.quad.tbyte 0x948 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x948 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x948 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x948 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x948 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x948 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x948 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x950 "GICDA_IROUTER330,GICDA_IROUTER330"
hexmask.quad.tbyte 0x950 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x950 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x950 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x950 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x950 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x950 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x950 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x958 "GICDA_IROUTER331,GICDA_IROUTER331"
hexmask.quad.tbyte 0x958 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x958 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x958 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x958 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x958 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x958 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x958 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x960 "GICDA_IROUTER332,GICDA_IROUTER332"
hexmask.quad.tbyte 0x960 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x960 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x960 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x960 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x960 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x960 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x960 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x968 "GICDA_IROUTER333,GICDA_IROUTER333"
hexmask.quad.tbyte 0x968 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x968 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x968 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x968 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x968 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x968 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x968 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x970 "GICDA_IROUTER334,GICDA_IROUTER334"
hexmask.quad.tbyte 0x970 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x970 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x970 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x970 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x970 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x970 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x970 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x978 "GICDA_IROUTER335,GICDA_IROUTER335"
hexmask.quad.tbyte 0x978 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x978 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x978 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x978 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x978 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x978 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x978 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x980 "GICDA_IROUTER336,GICDA_IROUTER336"
hexmask.quad.tbyte 0x980 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x980 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x980 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x980 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x980 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x980 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x980 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x988 "GICDA_IROUTER337,GICDA_IROUTER337"
hexmask.quad.tbyte 0x988 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x988 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x988 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x988 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x988 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x988 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x988 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x990 "GICDA_IROUTER338,GICDA_IROUTER338"
hexmask.quad.tbyte 0x990 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x990 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x990 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x990 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x990 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x990 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x990 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x998 "GICDA_IROUTER339,GICDA_IROUTER339"
hexmask.quad.tbyte 0x998 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x998 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x998 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x998 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x998 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x998 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x998 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9A0 "GICDA_IROUTER340,GICDA_IROUTER340"
hexmask.quad.tbyte 0x9A0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9A0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9A0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9A0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9A0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9A0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9A0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9A8 "GICDA_IROUTER341,GICDA_IROUTER341"
hexmask.quad.tbyte 0x9A8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9A8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9A8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9A8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9A8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9A8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9A8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9B0 "GICDA_IROUTER342,GICDA_IROUTER342"
hexmask.quad.tbyte 0x9B0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9B0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9B0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9B0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9B0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9B0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9B0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9B8 "GICDA_IROUTER343,GICDA_IROUTER343"
hexmask.quad.tbyte 0x9B8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9B8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9B8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9B8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9B8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9B8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9B8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9C0 "GICDA_IROUTER344,GICDA_IROUTER344"
hexmask.quad.tbyte 0x9C0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9C0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9C0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9C0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9C0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9C0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9C0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9C8 "GICDA_IROUTER345,GICDA_IROUTER345"
hexmask.quad.tbyte 0x9C8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9C8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9C8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9C8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9C8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9C8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9C8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9D0 "GICDA_IROUTER346,GICDA_IROUTER346"
hexmask.quad.tbyte 0x9D0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9D0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9D0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9D0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9D0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9D0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9D0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9D8 "GICDA_IROUTER347,GICDA_IROUTER347"
hexmask.quad.tbyte 0x9D8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9D8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9D8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9D8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9D8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9D8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9D8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9E0 "GICDA_IROUTER348,GICDA_IROUTER348"
hexmask.quad.tbyte 0x9E0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9E0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9E0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9E0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9E0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9E0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9E0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9E8 "GICDA_IROUTER349,GICDA_IROUTER349"
hexmask.quad.tbyte 0x9E8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9E8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9E8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9E8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9E8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9E8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9E8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9F0 "GICDA_IROUTER350,GICDA_IROUTER350"
hexmask.quad.tbyte 0x9F0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9F0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9F0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9F0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9F0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9F0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9F0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x9F8 "GICDA_IROUTER351,GICDA_IROUTER351"
hexmask.quad.tbyte 0x9F8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x9F8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x9F8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x9F8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x9F8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x9F8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x9F8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA00 "GICDA_IROUTER352,GICDA_IROUTER352"
hexmask.quad.tbyte 0xA00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA08 "GICDA_IROUTER353,GICDA_IROUTER353"
hexmask.quad.tbyte 0xA08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA10 "GICDA_IROUTER354,GICDA_IROUTER354"
hexmask.quad.tbyte 0xA10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA18 "GICDA_IROUTER355,GICDA_IROUTER355"
hexmask.quad.tbyte 0xA18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA20 "GICDA_IROUTER356,GICDA_IROUTER356"
hexmask.quad.tbyte 0xA20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA28 "GICDA_IROUTER357,GICDA_IROUTER357"
hexmask.quad.tbyte 0xA28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA30 "GICDA_IROUTER358,GICDA_IROUTER358"
hexmask.quad.tbyte 0xA30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA38 "GICDA_IROUTER359,GICDA_IROUTER359"
hexmask.quad.tbyte 0xA38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA40 "GICDA_IROUTER360,GICDA_IROUTER360"
hexmask.quad.tbyte 0xA40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA48 "GICDA_IROUTER361,GICDA_IROUTER361"
hexmask.quad.tbyte 0xA48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA50 "GICDA_IROUTER362,GICDA_IROUTER362"
hexmask.quad.tbyte 0xA50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA58 "GICDA_IROUTER363,GICDA_IROUTER363"
hexmask.quad.tbyte 0xA58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA60 "GICDA_IROUTER364,GICDA_IROUTER364"
hexmask.quad.tbyte 0xA60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA68 "GICDA_IROUTER365,GICDA_IROUTER365"
hexmask.quad.tbyte 0xA68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA70 "GICDA_IROUTER366,GICDA_IROUTER366"
hexmask.quad.tbyte 0xA70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA78 "GICDA_IROUTER367,GICDA_IROUTER367"
hexmask.quad.tbyte 0xA78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA80 "GICDA_IROUTER368,GICDA_IROUTER368"
hexmask.quad.tbyte 0xA80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA88 "GICDA_IROUTER369,GICDA_IROUTER369"
hexmask.quad.tbyte 0xA88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA90 "GICDA_IROUTER370,GICDA_IROUTER370"
hexmask.quad.tbyte 0xA90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA98 "GICDA_IROUTER371,GICDA_IROUTER371"
hexmask.quad.tbyte 0xA98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAA0 "GICDA_IROUTER372,GICDA_IROUTER372"
hexmask.quad.tbyte 0xAA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAA8 "GICDA_IROUTER373,GICDA_IROUTER373"
hexmask.quad.tbyte 0xAA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAB0 "GICDA_IROUTER374,GICDA_IROUTER374"
hexmask.quad.tbyte 0xAB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAB8 "GICDA_IROUTER375,GICDA_IROUTER375"
hexmask.quad.tbyte 0xAB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAC0 "GICDA_IROUTER376,GICDA_IROUTER376"
hexmask.quad.tbyte 0xAC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAC8 "GICDA_IROUTER377,GICDA_IROUTER377"
hexmask.quad.tbyte 0xAC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAD0 "GICDA_IROUTER378,GICDA_IROUTER378"
hexmask.quad.tbyte 0xAD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAD8 "GICDA_IROUTER379,GICDA_IROUTER379"
hexmask.quad.tbyte 0xAD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAE0 "GICDA_IROUTER380,GICDA_IROUTER380"
hexmask.quad.tbyte 0xAE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAE8 "GICDA_IROUTER381,GICDA_IROUTER381"
hexmask.quad.tbyte 0xAE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAF0 "GICDA_IROUTER382,GICDA_IROUTER382"
hexmask.quad.tbyte 0xAF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xAF8 "GICDA_IROUTER383,GICDA_IROUTER383"
hexmask.quad.tbyte 0xAF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xAF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xAF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xAF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xAF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xAF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xAF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB00 "GICDA_IROUTER384,GICDA_IROUTER384"
hexmask.quad.tbyte 0xB00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB08 "GICDA_IROUTER385,GICDA_IROUTER385"
hexmask.quad.tbyte 0xB08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB10 "GICDA_IROUTER386,GICDA_IROUTER386"
hexmask.quad.tbyte 0xB10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB18 "GICDA_IROUTER387,GICDA_IROUTER387"
hexmask.quad.tbyte 0xB18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB20 "GICDA_IROUTER388,GICDA_IROUTER388"
hexmask.quad.tbyte 0xB20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB28 "GICDA_IROUTER389,GICDA_IROUTER389"
hexmask.quad.tbyte 0xB28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB30 "GICDA_IROUTER390,GICDA_IROUTER390"
hexmask.quad.tbyte 0xB30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB38 "GICDA_IROUTER391,GICDA_IROUTER391"
hexmask.quad.tbyte 0xB38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB40 "GICDA_IROUTER392,GICDA_IROUTER392"
hexmask.quad.tbyte 0xB40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB48 "GICDA_IROUTER393,GICDA_IROUTER393"
hexmask.quad.tbyte 0xB48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB50 "GICDA_IROUTER394,GICDA_IROUTER394"
hexmask.quad.tbyte 0xB50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB58 "GICDA_IROUTER395,GICDA_IROUTER395"
hexmask.quad.tbyte 0xB58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB60 "GICDA_IROUTER396,GICDA_IROUTER396"
hexmask.quad.tbyte 0xB60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB68 "GICDA_IROUTER397,GICDA_IROUTER397"
hexmask.quad.tbyte 0xB68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB70 "GICDA_IROUTER398,GICDA_IROUTER398"
hexmask.quad.tbyte 0xB70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB78 "GICDA_IROUTER399,GICDA_IROUTER399"
hexmask.quad.tbyte 0xB78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB80 "GICDA_IROUTER400,GICDA_IROUTER400"
hexmask.quad.tbyte 0xB80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB88 "GICDA_IROUTER401,GICDA_IROUTER401"
hexmask.quad.tbyte 0xB88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB90 "GICDA_IROUTER402,GICDA_IROUTER402"
hexmask.quad.tbyte 0xB90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB98 "GICDA_IROUTER403,GICDA_IROUTER403"
hexmask.quad.tbyte 0xB98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBA0 "GICDA_IROUTER404,GICDA_IROUTER404"
hexmask.quad.tbyte 0xBA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBA8 "GICDA_IROUTER405,GICDA_IROUTER405"
hexmask.quad.tbyte 0xBA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBB0 "GICDA_IROUTER406,GICDA_IROUTER406"
hexmask.quad.tbyte 0xBB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBB8 "GICDA_IROUTER407,GICDA_IROUTER407"
hexmask.quad.tbyte 0xBB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBC0 "GICDA_IROUTER408,GICDA_IROUTER408"
hexmask.quad.tbyte 0xBC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBC8 "GICDA_IROUTER409,GICDA_IROUTER409"
hexmask.quad.tbyte 0xBC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBD0 "GICDA_IROUTER410,GICDA_IROUTER410"
hexmask.quad.tbyte 0xBD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBD8 "GICDA_IROUTER411,GICDA_IROUTER411"
hexmask.quad.tbyte 0xBD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBE0 "GICDA_IROUTER412,GICDA_IROUTER412"
hexmask.quad.tbyte 0xBE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBE8 "GICDA_IROUTER413,GICDA_IROUTER413"
hexmask.quad.tbyte 0xBE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBF0 "GICDA_IROUTER414,GICDA_IROUTER414"
hexmask.quad.tbyte 0xBF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xBF8 "GICDA_IROUTER415,GICDA_IROUTER415"
hexmask.quad.tbyte 0xBF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xBF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xBF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xBF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xBF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xBF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xBF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC00 "GICDA_IROUTER416,GICDA_IROUTER416"
hexmask.quad.tbyte 0xC00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC08 "GICDA_IROUTER417,GICDA_IROUTER417"
hexmask.quad.tbyte 0xC08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC10 "GICDA_IROUTER418,GICDA_IROUTER418"
hexmask.quad.tbyte 0xC10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC18 "GICDA_IROUTER419,GICDA_IROUTER419"
hexmask.quad.tbyte 0xC18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC20 "GICDA_IROUTER420,GICDA_IROUTER420"
hexmask.quad.tbyte 0xC20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC28 "GICDA_IROUTER421,GICDA_IROUTER421"
hexmask.quad.tbyte 0xC28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC30 "GICDA_IROUTER422,GICDA_IROUTER422"
hexmask.quad.tbyte 0xC30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC38 "GICDA_IROUTER423,GICDA_IROUTER423"
hexmask.quad.tbyte 0xC38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC40 "GICDA_IROUTER424,GICDA_IROUTER424"
hexmask.quad.tbyte 0xC40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC48 "GICDA_IROUTER425,GICDA_IROUTER425"
hexmask.quad.tbyte 0xC48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC50 "GICDA_IROUTER426,GICDA_IROUTER426"
hexmask.quad.tbyte 0xC50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC58 "GICDA_IROUTER427,GICDA_IROUTER427"
hexmask.quad.tbyte 0xC58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC60 "GICDA_IROUTER428,GICDA_IROUTER428"
hexmask.quad.tbyte 0xC60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC68 "GICDA_IROUTER429,GICDA_IROUTER429"
hexmask.quad.tbyte 0xC68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC70 "GICDA_IROUTER430,GICDA_IROUTER430"
hexmask.quad.tbyte 0xC70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC78 "GICDA_IROUTER431,GICDA_IROUTER431"
hexmask.quad.tbyte 0xC78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC80 "GICDA_IROUTER432,GICDA_IROUTER432"
hexmask.quad.tbyte 0xC80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC88 "GICDA_IROUTER433,GICDA_IROUTER433"
hexmask.quad.tbyte 0xC88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC90 "GICDA_IROUTER434,GICDA_IROUTER434"
hexmask.quad.tbyte 0xC90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC98 "GICDA_IROUTER435,GICDA_IROUTER435"
hexmask.quad.tbyte 0xC98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCA0 "GICDA_IROUTER436,GICDA_IROUTER436"
hexmask.quad.tbyte 0xCA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCA8 "GICDA_IROUTER437,GICDA_IROUTER437"
hexmask.quad.tbyte 0xCA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCB0 "GICDA_IROUTER438,GICDA_IROUTER438"
hexmask.quad.tbyte 0xCB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCB8 "GICDA_IROUTER439,GICDA_IROUTER439"
hexmask.quad.tbyte 0xCB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCC0 "GICDA_IROUTER440,GICDA_IROUTER440"
hexmask.quad.tbyte 0xCC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCC8 "GICDA_IROUTER441,GICDA_IROUTER441"
hexmask.quad.tbyte 0xCC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCD0 "GICDA_IROUTER442,GICDA_IROUTER442"
hexmask.quad.tbyte 0xCD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCD8 "GICDA_IROUTER443,GICDA_IROUTER443"
hexmask.quad.tbyte 0xCD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCE0 "GICDA_IROUTER444,GICDA_IROUTER444"
hexmask.quad.tbyte 0xCE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCE8 "GICDA_IROUTER445,GICDA_IROUTER445"
hexmask.quad.tbyte 0xCE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCF0 "GICDA_IROUTER446,GICDA_IROUTER446"
hexmask.quad.tbyte 0xCF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xCF8 "GICDA_IROUTER447,GICDA_IROUTER447"
hexmask.quad.tbyte 0xCF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xCF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xCF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xCF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xCF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xCF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xCF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD00 "GICDA_IROUTER448,GICDA_IROUTER448"
hexmask.quad.tbyte 0xD00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD08 "GICDA_IROUTER449,GICDA_IROUTER449"
hexmask.quad.tbyte 0xD08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD10 "GICDA_IROUTER450,GICDA_IROUTER450"
hexmask.quad.tbyte 0xD10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD18 "GICDA_IROUTER451,GICDA_IROUTER451"
hexmask.quad.tbyte 0xD18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD20 "GICDA_IROUTER452,GICDA_IROUTER452"
hexmask.quad.tbyte 0xD20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD28 "GICDA_IROUTER453,GICDA_IROUTER453"
hexmask.quad.tbyte 0xD28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD30 "GICDA_IROUTER454,GICDA_IROUTER454"
hexmask.quad.tbyte 0xD30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD38 "GICDA_IROUTER455,GICDA_IROUTER455"
hexmask.quad.tbyte 0xD38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD40 "GICDA_IROUTER456,GICDA_IROUTER456"
hexmask.quad.tbyte 0xD40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD48 "GICDA_IROUTER457,GICDA_IROUTER457"
hexmask.quad.tbyte 0xD48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD50 "GICDA_IROUTER458,GICDA_IROUTER458"
hexmask.quad.tbyte 0xD50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD58 "GICDA_IROUTER459,GICDA_IROUTER459"
hexmask.quad.tbyte 0xD58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD60 "GICDA_IROUTER460,GICDA_IROUTER460"
hexmask.quad.tbyte 0xD60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD68 "GICDA_IROUTER461,GICDA_IROUTER461"
hexmask.quad.tbyte 0xD68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD70 "GICDA_IROUTER462,GICDA_IROUTER462"
hexmask.quad.tbyte 0xD70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD78 "GICDA_IROUTER463,GICDA_IROUTER463"
hexmask.quad.tbyte 0xD78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD80 "GICDA_IROUTER464,GICDA_IROUTER464"
hexmask.quad.tbyte 0xD80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD88 "GICDA_IROUTER465,GICDA_IROUTER465"
hexmask.quad.tbyte 0xD88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD90 "GICDA_IROUTER466,GICDA_IROUTER466"
hexmask.quad.tbyte 0xD90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD98 "GICDA_IROUTER467,GICDA_IROUTER467"
hexmask.quad.tbyte 0xD98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDA0 "GICDA_IROUTER468,GICDA_IROUTER468"
hexmask.quad.tbyte 0xDA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDA8 "GICDA_IROUTER469,GICDA_IROUTER469"
hexmask.quad.tbyte 0xDA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDB0 "GICDA_IROUTER470,GICDA_IROUTER470"
hexmask.quad.tbyte 0xDB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDB8 "GICDA_IROUTER471,GICDA_IROUTER471"
hexmask.quad.tbyte 0xDB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDC0 "GICDA_IROUTER472,GICDA_IROUTER472"
hexmask.quad.tbyte 0xDC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDC8 "GICDA_IROUTER473,GICDA_IROUTER473"
hexmask.quad.tbyte 0xDC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDD0 "GICDA_IROUTER474,GICDA_IROUTER474"
hexmask.quad.tbyte 0xDD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDD8 "GICDA_IROUTER475,GICDA_IROUTER475"
hexmask.quad.tbyte 0xDD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDE0 "GICDA_IROUTER476,GICDA_IROUTER476"
hexmask.quad.tbyte 0xDE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDE8 "GICDA_IROUTER477,GICDA_IROUTER477"
hexmask.quad.tbyte 0xDE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDF0 "GICDA_IROUTER478,GICDA_IROUTER478"
hexmask.quad.tbyte 0xDF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xDF8 "GICDA_IROUTER479,GICDA_IROUTER479"
hexmask.quad.tbyte 0xDF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xDF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xDF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xDF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xDF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xDF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xDF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE00 "GICDA_IROUTER480,GICDA_IROUTER480"
hexmask.quad.tbyte 0xE00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE08 "GICDA_IROUTER481,GICDA_IROUTER481"
hexmask.quad.tbyte 0xE08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE10 "GICDA_IROUTER482,GICDA_IROUTER482"
hexmask.quad.tbyte 0xE10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE18 "GICDA_IROUTER483,GICDA_IROUTER483"
hexmask.quad.tbyte 0xE18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE20 "GICDA_IROUTER484,GICDA_IROUTER484"
hexmask.quad.tbyte 0xE20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE28 "GICDA_IROUTER485,GICDA_IROUTER485"
hexmask.quad.tbyte 0xE28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE30 "GICDA_IROUTER486,GICDA_IROUTER486"
hexmask.quad.tbyte 0xE30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE38 "GICDA_IROUTER487,GICDA_IROUTER487"
hexmask.quad.tbyte 0xE38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE40 "GICDA_IROUTER488,GICDA_IROUTER488"
hexmask.quad.tbyte 0xE40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE48 "GICDA_IROUTER489,GICDA_IROUTER489"
hexmask.quad.tbyte 0xE48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE50 "GICDA_IROUTER490,GICDA_IROUTER490"
hexmask.quad.tbyte 0xE50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE58 "GICDA_IROUTER491,GICDA_IROUTER491"
hexmask.quad.tbyte 0xE58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE60 "GICDA_IROUTER492,GICDA_IROUTER492"
hexmask.quad.tbyte 0xE60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE68 "GICDA_IROUTER493,GICDA_IROUTER493"
hexmask.quad.tbyte 0xE68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE70 "GICDA_IROUTER494,GICDA_IROUTER494"
hexmask.quad.tbyte 0xE70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE78 "GICDA_IROUTER495,GICDA_IROUTER495"
hexmask.quad.tbyte 0xE78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE80 "GICDA_IROUTER496,GICDA_IROUTER496"
hexmask.quad.tbyte 0xE80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE88 "GICDA_IROUTER497,GICDA_IROUTER497"
hexmask.quad.tbyte 0xE88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE90 "GICDA_IROUTER498,GICDA_IROUTER498"
hexmask.quad.tbyte 0xE90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE98 "GICDA_IROUTER499,GICDA_IROUTER499"
hexmask.quad.tbyte 0xE98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEA0 "GICDA_IROUTER500,GICDA_IROUTER500"
hexmask.quad.tbyte 0xEA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEA8 "GICDA_IROUTER501,GICDA_IROUTER501"
hexmask.quad.tbyte 0xEA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEB0 "GICDA_IROUTER502,GICDA_IROUTER502"
hexmask.quad.tbyte 0xEB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEB8 "GICDA_IROUTER503,GICDA_IROUTER503"
hexmask.quad.tbyte 0xEB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEC0 "GICDA_IROUTER504,GICDA_IROUTER504"
hexmask.quad.tbyte 0xEC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEC8 "GICDA_IROUTER505,GICDA_IROUTER505"
hexmask.quad.tbyte 0xEC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xED0 "GICDA_IROUTER506,GICDA_IROUTER506"
hexmask.quad.tbyte 0xED0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xED0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xED0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xED0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xED0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xED0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xED0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xED8 "GICDA_IROUTER507,GICDA_IROUTER507"
hexmask.quad.tbyte 0xED8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xED8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xED8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xED8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xED8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xED8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xED8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEE0 "GICDA_IROUTER508,GICDA_IROUTER508"
hexmask.quad.tbyte 0xEE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEE8 "GICDA_IROUTER509,GICDA_IROUTER509"
hexmask.quad.tbyte 0xEE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEF0 "GICDA_IROUTER510,GICDA_IROUTER510"
hexmask.quad.tbyte 0xEF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xEF8 "GICDA_IROUTER511,GICDA_IROUTER511"
hexmask.quad.tbyte 0xEF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xEF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xEF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xEF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xEF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xEF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xEF8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF00 "GICDA_IROUTER512,GICDA_IROUTER512"
hexmask.quad.tbyte 0xF00 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF00 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF00 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF00 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF00 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF00 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF00 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF08 "GICDA_IROUTER513,GICDA_IROUTER513"
hexmask.quad.tbyte 0xF08 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF08 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF08 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF08 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF08 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF08 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF08 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF10 "GICDA_IROUTER514,GICDA_IROUTER514"
hexmask.quad.tbyte 0xF10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF18 "GICDA_IROUTER515,GICDA_IROUTER515"
hexmask.quad.tbyte 0xF18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF20 "GICDA_IROUTER516,GICDA_IROUTER516"
hexmask.quad.tbyte 0xF20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF28 "GICDA_IROUTER517,GICDA_IROUTER517"
hexmask.quad.tbyte 0xF28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF30 "GICDA_IROUTER518,GICDA_IROUTER518"
hexmask.quad.tbyte 0xF30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF38 "GICDA_IROUTER519,GICDA_IROUTER519"
hexmask.quad.tbyte 0xF38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF40 "GICDA_IROUTER520,GICDA_IROUTER520"
hexmask.quad.tbyte 0xF40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF48 "GICDA_IROUTER521,GICDA_IROUTER521"
hexmask.quad.tbyte 0xF48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF50 "GICDA_IROUTER522,GICDA_IROUTER522"
hexmask.quad.tbyte 0xF50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF58 "GICDA_IROUTER523,GICDA_IROUTER523"
hexmask.quad.tbyte 0xF58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF60 "GICDA_IROUTER524,GICDA_IROUTER524"
hexmask.quad.tbyte 0xF60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF68 "GICDA_IROUTER525,GICDA_IROUTER525"
hexmask.quad.tbyte 0xF68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF70 "GICDA_IROUTER526,GICDA_IROUTER526"
hexmask.quad.tbyte 0xF70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF78 "GICDA_IROUTER527,GICDA_IROUTER527"
hexmask.quad.tbyte 0xF78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF80 "GICDA_IROUTER528,GICDA_IROUTER528"
hexmask.quad.tbyte 0xF80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF88 "GICDA_IROUTER529,GICDA_IROUTER529"
hexmask.quad.tbyte 0xF88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF90 "GICDA_IROUTER530,GICDA_IROUTER530"
hexmask.quad.tbyte 0xF90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF98 "GICDA_IROUTER531,GICDA_IROUTER531"
hexmask.quad.tbyte 0xF98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFA0 "GICDA_IROUTER532,GICDA_IROUTER532"
hexmask.quad.tbyte 0xFA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFA8 "GICDA_IROUTER533,GICDA_IROUTER533"
hexmask.quad.tbyte 0xFA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFB0 "GICDA_IROUTER534,GICDA_IROUTER534"
hexmask.quad.tbyte 0xFB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFB8 "GICDA_IROUTER535,GICDA_IROUTER535"
hexmask.quad.tbyte 0xFB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFC0 "GICDA_IROUTER536,GICDA_IROUTER536"
hexmask.quad.tbyte 0xFC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFC8 "GICDA_IROUTER537,GICDA_IROUTER537"
hexmask.quad.tbyte 0xFC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFD0 "GICDA_IROUTER538,GICDA_IROUTER538"
hexmask.quad.tbyte 0xFD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFD8 "GICDA_IROUTER539,GICDA_IROUTER539"
hexmask.quad.tbyte 0xFD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFE0 "GICDA_IROUTER540,GICDA_IROUTER540"
hexmask.quad.tbyte 0xFE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFE8 "GICDA_IROUTER541,GICDA_IROUTER541"
hexmask.quad.tbyte 0xFE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFF0 "GICDA_IROUTER542,GICDA_IROUTER542"
hexmask.quad.tbyte 0xFF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xFF8 "GICDA_IROUTER543,GICDA_IROUTER543"
hexmask.quad.tbyte 0xFF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xFF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xFF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xFF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xFF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xFF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xFF8 0.--7. 1. "Affinity0,Affinity0"
group.quad 0xE7100++0xFF
line.quad 0x0 "GICDA_IROUTER544,GICDA_IROUTER544"
hexmask.quad.tbyte 0x0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x8 "GICDA_IROUTER545,GICDA_IROUTER545"
hexmask.quad.tbyte 0x8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x10 "GICDA_IROUTER546,GICDA_IROUTER546"
hexmask.quad.tbyte 0x10 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x10 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x10 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x10 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x10 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x10 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x10 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x18 "GICDA_IROUTER547,GICDA_IROUTER547"
hexmask.quad.tbyte 0x18 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x18 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x18 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x18 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x18 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x18 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x18 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x20 "GICDA_IROUTER548,GICDA_IROUTER548"
hexmask.quad.tbyte 0x20 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x20 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x20 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x20 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x20 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x20 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x20 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x28 "GICDA_IROUTER549,GICDA_IROUTER549"
hexmask.quad.tbyte 0x28 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x28 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x28 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x28 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x28 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x28 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x28 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x30 "GICDA_IROUTER550,GICDA_IROUTER550"
hexmask.quad.tbyte 0x30 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x30 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x30 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x30 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x30 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x30 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x30 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x38 "GICDA_IROUTER551,GICDA_IROUTER551"
hexmask.quad.tbyte 0x38 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x38 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x38 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x38 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x38 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x38 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x38 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x40 "GICDA_IROUTER552,GICDA_IROUTER552"
hexmask.quad.tbyte 0x40 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x40 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x40 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x40 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x40 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x40 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x40 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x48 "GICDA_IROUTER553,GICDA_IROUTER553"
hexmask.quad.tbyte 0x48 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x48 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x48 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x48 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x48 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x48 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x48 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x50 "GICDA_IROUTER554,GICDA_IROUTER554"
hexmask.quad.tbyte 0x50 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x50 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x50 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x50 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x50 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x50 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x50 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x58 "GICDA_IROUTER555,GICDA_IROUTER555"
hexmask.quad.tbyte 0x58 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x58 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x58 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x58 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x58 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x58 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x58 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x60 "GICDA_IROUTER556,GICDA_IROUTER556"
hexmask.quad.tbyte 0x60 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x60 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x60 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x60 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x60 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x60 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x60 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x68 "GICDA_IROUTER557,GICDA_IROUTER557"
hexmask.quad.tbyte 0x68 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x68 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x68 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x68 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x68 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x68 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x68 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x70 "GICDA_IROUTER558,GICDA_IROUTER558"
hexmask.quad.tbyte 0x70 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x70 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x70 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x70 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x70 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x70 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x70 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x78 "GICDA_IROUTER559,GICDA_IROUTER559"
hexmask.quad.tbyte 0x78 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x78 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x78 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x78 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x78 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x78 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x78 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x80 "GICDA_IROUTER560,GICDA_IROUTER560"
hexmask.quad.tbyte 0x80 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x80 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x80 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x80 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x80 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x80 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x80 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x88 "GICDA_IROUTER561,GICDA_IROUTER561"
hexmask.quad.tbyte 0x88 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x88 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x88 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x88 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x88 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x88 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x88 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x90 "GICDA_IROUTER562,GICDA_IROUTER562"
hexmask.quad.tbyte 0x90 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x90 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x90 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x90 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x90 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x90 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x90 0.--7. 1. "Affinity0,Affinity0"
line.quad 0x98 "GICDA_IROUTER563,GICDA_IROUTER563"
hexmask.quad.tbyte 0x98 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0x98 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0x98 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0x98 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0x98 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0x98 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0x98 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA0 "GICDA_IROUTER564,GICDA_IROUTER564"
hexmask.quad.tbyte 0xA0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xA8 "GICDA_IROUTER565,GICDA_IROUTER565"
hexmask.quad.tbyte 0xA8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xA8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xA8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xA8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xA8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xA8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xA8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB0 "GICDA_IROUTER566,GICDA_IROUTER566"
hexmask.quad.tbyte 0xB0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xB8 "GICDA_IROUTER567,GICDA_IROUTER567"
hexmask.quad.tbyte 0xB8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xB8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xB8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xB8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xB8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xB8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xB8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC0 "GICDA_IROUTER568,GICDA_IROUTER568"
hexmask.quad.tbyte 0xC0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xC8 "GICDA_IROUTER569,GICDA_IROUTER569"
hexmask.quad.tbyte 0xC8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xC8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xC8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xC8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xC8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xC8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xC8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD0 "GICDA_IROUTER570,GICDA_IROUTER570"
hexmask.quad.tbyte 0xD0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xD8 "GICDA_IROUTER571,GICDA_IROUTER571"
hexmask.quad.tbyte 0xD8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xD8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xD8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xD8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xD8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xD8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xD8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE0 "GICDA_IROUTER572,GICDA_IROUTER572"
hexmask.quad.tbyte 0xE0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xE8 "GICDA_IROUTER573,GICDA_IROUTER573"
hexmask.quad.tbyte 0xE8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xE8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xE8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xE8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xE8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xE8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xE8 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF0 "GICDA_IROUTER574,GICDA_IROUTER574"
hexmask.quad.tbyte 0xF0 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF0 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF0 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF0 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF0 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF0 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF0 0.--7. 1. "Affinity0,Affinity0"
line.quad 0xF8 "GICDA_IROUTER575,GICDA_IROUTER575"
hexmask.quad.tbyte 0xF8 40.--63. 1. "RESERVED1,RESERVED1"
hexmask.quad.byte 0xF8 32.--39. 1. "Affinity3,Affinity3"
newline
bitfld.quad 0xF8 31. "InterruptRoutingMode,InterruptRoutingMode" "0,1"
hexmask.quad.byte 0xF8 24.--30. 1. "RESERVED0,RESERVED0"
newline
hexmask.quad.byte 0xF8 16.--23. 1. "Affinity2,Affinity2"
hexmask.quad.byte 0xF8 8.--15. 1. "Affinity1,Affinity1"
newline
hexmask.quad.byte 0xF8 0.--7. 1. "Affinity0,Affinity0"
group.long 0xEE008++0x87
line.long 0x0 "GICDA_ICLAR2,GICDA_ICLAR2"
bitfld.long 0x0 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x0 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x0 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x0 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x0 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x0 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x0 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x0 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x0 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x0 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x0 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x0 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x0 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x0 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x0 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x4 "GICDA_ICLAR3,GICDA_ICLAR3"
bitfld.long 0x4 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x4 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x4 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x4 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x4 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x4 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x4 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x4 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x4 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x4 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x4 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x4 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x4 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x8 "GICDA_ICLAR4,GICDA_ICLAR4"
bitfld.long 0x8 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x8 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x8 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x8 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x8 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x8 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x8 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x8 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x8 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x8 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x8 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x8 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x8 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x8 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x8 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x8 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0xC "GICDA_ICLAR5,GICDA_ICLAR5"
bitfld.long 0xC 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0xC 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0xC 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0xC 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0xC 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0xC 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0xC 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0xC 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0xC 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0xC 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0xC 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0xC 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0xC 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0xC 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0xC 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0xC 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x10 "GICDA_ICLAR6,GICDA_ICLAR6"
bitfld.long 0x10 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x10 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x10 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x10 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x10 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x10 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x10 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x10 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x10 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x10 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x10 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x10 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x10 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x10 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x14 "GICDA_ICLAR7,GICDA_ICLAR7"
bitfld.long 0x14 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x14 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x14 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x14 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x14 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x14 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x14 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x14 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x14 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x14 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x14 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x14 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x14 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x14 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x14 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x14 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x18 "GICDA_ICLAR8,GICDA_ICLAR8"
bitfld.long 0x18 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x18 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x18 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x18 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x18 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x18 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x18 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x18 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x18 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x18 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x18 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x18 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x18 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x18 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x18 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x18 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x1C "GICDA_ICLAR9,GICDA_ICLAR9"
bitfld.long 0x1C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x1C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x1C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x1C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x1C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x1C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x1C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x1C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x1C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x1C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x1C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x1C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x1C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x1C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x1C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x1C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x20 "GICDA_ICLAR10,GICDA_ICLAR10"
bitfld.long 0x20 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x20 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x20 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x20 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x20 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x20 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x20 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x20 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x20 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x20 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x20 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x20 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x20 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x20 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x20 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x20 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x24 "GICDA_ICLAR11,GICDA_ICLAR11"
bitfld.long 0x24 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x24 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x24 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x24 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x24 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x24 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x24 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x24 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x24 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x24 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x24 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x24 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x24 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x24 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x24 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x28 "GICDA_ICLAR12,GICDA_ICLAR12"
bitfld.long 0x28 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x28 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x28 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x28 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x28 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x28 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x28 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x28 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x28 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x28 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x28 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x28 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x28 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x28 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x28 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x28 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x2C "GICDA_ICLAR13,GICDA_ICLAR13"
bitfld.long 0x2C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x2C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x2C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x2C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x2C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x2C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x2C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x2C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x2C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x2C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x2C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x2C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x2C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x2C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x2C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x2C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x30 "GICDA_ICLAR14,GICDA_ICLAR14"
bitfld.long 0x30 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x30 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x30 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x30 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x30 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x30 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x30 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x30 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x30 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x30 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x30 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x30 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x30 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x30 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x30 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x30 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x34 "GICDA_ICLAR15,GICDA_ICLAR15"
bitfld.long 0x34 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x34 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x34 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x34 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x34 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x34 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x34 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x34 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x34 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x34 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x34 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x34 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x34 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x34 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x34 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x34 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x38 "GICDA_ICLAR16,GICDA_ICLAR16"
bitfld.long 0x38 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x38 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x38 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x38 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x38 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x38 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x38 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x38 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x38 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x38 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x38 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x38 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x38 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x38 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x38 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x38 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x3C "GICDA_ICLAR17,GICDA_ICLAR17"
bitfld.long 0x3C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x3C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x3C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x3C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x3C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x3C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x3C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x3C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x3C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x3C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x3C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x3C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x3C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x3C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x3C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x3C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x40 "GICDA_ICLAR18,GICDA_ICLAR18"
bitfld.long 0x40 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x40 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x40 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x40 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x40 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x40 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x40 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x40 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x40 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x40 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x40 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x40 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x40 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x40 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x40 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x40 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x44 "GICDA_ICLAR19,GICDA_ICLAR19"
bitfld.long 0x44 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x44 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x44 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x44 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x44 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x44 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x44 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x44 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x44 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x44 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x44 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x44 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x44 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x44 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x44 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x44 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x48 "GICDA_ICLAR20,GICDA_ICLAR20"
bitfld.long 0x48 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x48 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x48 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x48 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x48 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x48 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x48 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x48 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x48 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x48 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x48 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x48 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x48 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x48 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x48 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x48 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x4C "GICDA_ICLAR21,GICDA_ICLAR21"
bitfld.long 0x4C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x4C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x4C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x4C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x4C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x4C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x4C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x4C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x4C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x4C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x4C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x4C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x4C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x4C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x4C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x4C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x50 "GICDA_ICLAR22,GICDA_ICLAR22"
bitfld.long 0x50 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x50 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x50 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x50 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x50 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x50 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x50 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x50 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x50 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x50 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x50 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x50 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x50 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x50 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x50 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x50 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x54 "GICDA_ICLAR23,GICDA_ICLAR23"
bitfld.long 0x54 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x54 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x54 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x54 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x54 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x54 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x54 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x54 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x54 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x54 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x54 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x54 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x54 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x54 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x54 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x54 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x58 "GICDA_ICLAR24,GICDA_ICLAR24"
bitfld.long 0x58 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x58 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x58 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x58 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x58 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x58 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x58 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x58 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x58 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x58 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x58 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x58 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x58 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x58 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x58 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x58 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x5C "GICDA_ICLAR25,GICDA_ICLAR25"
bitfld.long 0x5C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x5C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x5C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x5C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x5C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x5C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x5C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x5C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x5C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x5C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x5C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x5C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x5C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x5C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x5C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x5C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x60 "GICDA_ICLAR26,GICDA_ICLAR26"
bitfld.long 0x60 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x60 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x60 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x60 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x60 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x60 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x60 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x60 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x60 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x60 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x60 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x60 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x60 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x60 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x60 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x60 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x64 "GICDA_ICLAR27,GICDA_ICLAR27"
bitfld.long 0x64 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x64 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x64 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x64 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x64 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x64 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x64 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x64 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x64 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x64 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x64 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x64 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x64 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x64 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x64 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x64 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x68 "GICDA_ICLAR28,GICDA_ICLAR28"
bitfld.long 0x68 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x68 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x68 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x68 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x68 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x68 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x68 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x68 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x68 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x68 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x68 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x68 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x68 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x68 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x68 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x68 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x6C "GICDA_ICLAR29,GICDA_ICLAR29"
bitfld.long 0x6C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x6C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x6C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x6C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x6C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x6C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x6C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x6C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x6C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x6C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x6C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x6C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x6C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x6C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x6C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x6C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x70 "GICDA_ICLAR30,GICDA_ICLAR30"
bitfld.long 0x70 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x70 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x70 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x70 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x70 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x70 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x70 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x70 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x70 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x70 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x70 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x70 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x70 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x70 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x70 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x70 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x74 "GICDA_ICLAR31,GICDA_ICLAR31"
bitfld.long 0x74 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x74 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x74 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x74 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x74 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x74 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x74 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x74 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x74 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x74 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x74 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x74 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x74 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x74 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x74 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x74 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x78 "GICDA_ICLAR32,GICDA_ICLAR32"
bitfld.long 0x78 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x78 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x78 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x78 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x78 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x78 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x78 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x78 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x78 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x78 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x78 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x78 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x78 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x78 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x78 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x78 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x7C "GICDA_ICLAR33,GICDA_ICLAR33"
bitfld.long 0x7C 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x7C 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x7C 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x7C 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x7C 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x7C 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x7C 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x7C 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x7C 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x7C 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x7C 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x7C 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x7C 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x7C 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x7C 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x7C 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x80 "GICDA_ICLAR34,GICDA_ICLAR34"
bitfld.long 0x80 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x80 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x80 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x80 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x80 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x80 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x80 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x80 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x80 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x80 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x80 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x80 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x80 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x80 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x80 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x80 0.--1. "classes0,classes0" "0,1,2,3"
line.long 0x84 "GICDA_ICLAR35,GICDA_ICLAR35"
bitfld.long 0x84 30.--31. "classes15,classes15" "0,1,2,3"
bitfld.long 0x84 28.--29. "classes14,classes14" "0,1,2,3"
newline
bitfld.long 0x84 26.--27. "classes13,classes13" "0,1,2,3"
bitfld.long 0x84 24.--25. "classes12,classes12" "0,1,2,3"
newline
bitfld.long 0x84 22.--23. "classes11,classes11" "0,1,2,3"
bitfld.long 0x84 20.--21. "classes10,classes10" "0,1,2,3"
newline
bitfld.long 0x84 18.--19. "classes9,classes9" "0,1,2,3"
bitfld.long 0x84 16.--17. "classes8,classes8" "0,1,2,3"
newline
bitfld.long 0x84 14.--15. "classes7,classes7" "0,1,2,3"
bitfld.long 0x84 12.--13. "classes6,classes6" "0,1,2,3"
newline
bitfld.long 0x84 10.--11. "classes5,classes5" "0,1,2,3"
bitfld.long 0x84 8.--9. "classes4,classes4" "0,1,2,3"
newline
bitfld.long 0x84 6.--7. "classes3,classes3" "0,1,2,3"
bitfld.long 0x84 4.--5. "classes2,classes2" "0,1,2,3"
newline
bitfld.long 0x84 2.--3. "classes1,classes1" "0,1,2,3"
bitfld.long 0x84 0.--1. "classes0,classes0" "0,1,2,3"
group.long 0xEE104++0x43
line.long 0x0 "GICDA_IERRR1,GICDA_IERRR1"
bitfld.long 0x0 31. "status31,status31" "0,1"
bitfld.long 0x0 30. "status30,status30" "0,1"
newline
bitfld.long 0x0 29. "status29,status29" "0,1"
bitfld.long 0x0 28. "status28,status28" "0,1"
newline
bitfld.long 0x0 27. "status27,status27" "0,1"
bitfld.long 0x0 26. "status26,status26" "0,1"
newline
bitfld.long 0x0 25. "status25,status25" "0,1"
bitfld.long 0x0 24. "status24,status24" "0,1"
newline
bitfld.long 0x0 23. "status23,status23" "0,1"
bitfld.long 0x0 22. "status22,status22" "0,1"
newline
bitfld.long 0x0 21. "status21,status21" "0,1"
bitfld.long 0x0 20. "status20,status20" "0,1"
newline
bitfld.long 0x0 19. "status19,status19" "0,1"
bitfld.long 0x0 18. "status18,status18" "0,1"
newline
bitfld.long 0x0 17. "status17,status17" "0,1"
bitfld.long 0x0 16. "status16,status16" "0,1"
newline
bitfld.long 0x0 15. "status15,status15" "0,1"
bitfld.long 0x0 14. "status14,status14" "0,1"
newline
bitfld.long 0x0 13. "status13,status13" "0,1"
bitfld.long 0x0 12. "status12,status12" "0,1"
newline
bitfld.long 0x0 11. "status11,status11" "0,1"
bitfld.long 0x0 10. "status10,status10" "0,1"
newline
bitfld.long 0x0 9. "status9,status9" "0,1"
bitfld.long 0x0 8. "status8,status8" "0,1"
newline
bitfld.long 0x0 7. "status7,status7" "0,1"
bitfld.long 0x0 6. "status6,status6" "0,1"
newline
bitfld.long 0x0 5. "status5,status5" "0,1"
bitfld.long 0x0 4. "status4,status4" "0,1"
newline
bitfld.long 0x0 3. "status3,status3" "0,1"
bitfld.long 0x0 2. "status2,status2" "0,1"
newline
bitfld.long 0x0 1. "status1,status1" "0,1"
bitfld.long 0x0 0. "status0,status0" "0,1"
line.long 0x4 "GICDA_IERRR2,GICDA_IERRR2"
bitfld.long 0x4 31. "status31,status31" "0,1"
bitfld.long 0x4 30. "status30,status30" "0,1"
newline
bitfld.long 0x4 29. "status29,status29" "0,1"
bitfld.long 0x4 28. "status28,status28" "0,1"
newline
bitfld.long 0x4 27. "status27,status27" "0,1"
bitfld.long 0x4 26. "status26,status26" "0,1"
newline
bitfld.long 0x4 25. "status25,status25" "0,1"
bitfld.long 0x4 24. "status24,status24" "0,1"
newline
bitfld.long 0x4 23. "status23,status23" "0,1"
bitfld.long 0x4 22. "status22,status22" "0,1"
newline
bitfld.long 0x4 21. "status21,status21" "0,1"
bitfld.long 0x4 20. "status20,status20" "0,1"
newline
bitfld.long 0x4 19. "status19,status19" "0,1"
bitfld.long 0x4 18. "status18,status18" "0,1"
newline
bitfld.long 0x4 17. "status17,status17" "0,1"
bitfld.long 0x4 16. "status16,status16" "0,1"
newline
bitfld.long 0x4 15. "status15,status15" "0,1"
bitfld.long 0x4 14. "status14,status14" "0,1"
newline
bitfld.long 0x4 13. "status13,status13" "0,1"
bitfld.long 0x4 12. "status12,status12" "0,1"
newline
bitfld.long 0x4 11. "status11,status11" "0,1"
bitfld.long 0x4 10. "status10,status10" "0,1"
newline
bitfld.long 0x4 9. "status9,status9" "0,1"
bitfld.long 0x4 8. "status8,status8" "0,1"
newline
bitfld.long 0x4 7. "status7,status7" "0,1"
bitfld.long 0x4 6. "status6,status6" "0,1"
newline
bitfld.long 0x4 5. "status5,status5" "0,1"
bitfld.long 0x4 4. "status4,status4" "0,1"
newline
bitfld.long 0x4 3. "status3,status3" "0,1"
bitfld.long 0x4 2. "status2,status2" "0,1"
newline
bitfld.long 0x4 1. "status1,status1" "0,1"
bitfld.long 0x4 0. "status0,status0" "0,1"
line.long 0x8 "GICDA_IERRR3,GICDA_IERRR3"
bitfld.long 0x8 31. "status31,status31" "0,1"
bitfld.long 0x8 30. "status30,status30" "0,1"
newline
bitfld.long 0x8 29. "status29,status29" "0,1"
bitfld.long 0x8 28. "status28,status28" "0,1"
newline
bitfld.long 0x8 27. "status27,status27" "0,1"
bitfld.long 0x8 26. "status26,status26" "0,1"
newline
bitfld.long 0x8 25. "status25,status25" "0,1"
bitfld.long 0x8 24. "status24,status24" "0,1"
newline
bitfld.long 0x8 23. "status23,status23" "0,1"
bitfld.long 0x8 22. "status22,status22" "0,1"
newline
bitfld.long 0x8 21. "status21,status21" "0,1"
bitfld.long 0x8 20. "status20,status20" "0,1"
newline
bitfld.long 0x8 19. "status19,status19" "0,1"
bitfld.long 0x8 18. "status18,status18" "0,1"
newline
bitfld.long 0x8 17. "status17,status17" "0,1"
bitfld.long 0x8 16. "status16,status16" "0,1"
newline
bitfld.long 0x8 15. "status15,status15" "0,1"
bitfld.long 0x8 14. "status14,status14" "0,1"
newline
bitfld.long 0x8 13. "status13,status13" "0,1"
bitfld.long 0x8 12. "status12,status12" "0,1"
newline
bitfld.long 0x8 11. "status11,status11" "0,1"
bitfld.long 0x8 10. "status10,status10" "0,1"
newline
bitfld.long 0x8 9. "status9,status9" "0,1"
bitfld.long 0x8 8. "status8,status8" "0,1"
newline
bitfld.long 0x8 7. "status7,status7" "0,1"
bitfld.long 0x8 6. "status6,status6" "0,1"
newline
bitfld.long 0x8 5. "status5,status5" "0,1"
bitfld.long 0x8 4. "status4,status4" "0,1"
newline
bitfld.long 0x8 3. "status3,status3" "0,1"
bitfld.long 0x8 2. "status2,status2" "0,1"
newline
bitfld.long 0x8 1. "status1,status1" "0,1"
bitfld.long 0x8 0. "status0,status0" "0,1"
line.long 0xC "GICDA_IERRR4,GICDA_IERRR4"
bitfld.long 0xC 31. "status31,status31" "0,1"
bitfld.long 0xC 30. "status30,status30" "0,1"
newline
bitfld.long 0xC 29. "status29,status29" "0,1"
bitfld.long 0xC 28. "status28,status28" "0,1"
newline
bitfld.long 0xC 27. "status27,status27" "0,1"
bitfld.long 0xC 26. "status26,status26" "0,1"
newline
bitfld.long 0xC 25. "status25,status25" "0,1"
bitfld.long 0xC 24. "status24,status24" "0,1"
newline
bitfld.long 0xC 23. "status23,status23" "0,1"
bitfld.long 0xC 22. "status22,status22" "0,1"
newline
bitfld.long 0xC 21. "status21,status21" "0,1"
bitfld.long 0xC 20. "status20,status20" "0,1"
newline
bitfld.long 0xC 19. "status19,status19" "0,1"
bitfld.long 0xC 18. "status18,status18" "0,1"
newline
bitfld.long 0xC 17. "status17,status17" "0,1"
bitfld.long 0xC 16. "status16,status16" "0,1"
newline
bitfld.long 0xC 15. "status15,status15" "0,1"
bitfld.long 0xC 14. "status14,status14" "0,1"
newline
bitfld.long 0xC 13. "status13,status13" "0,1"
bitfld.long 0xC 12. "status12,status12" "0,1"
newline
bitfld.long 0xC 11. "status11,status11" "0,1"
bitfld.long 0xC 10. "status10,status10" "0,1"
newline
bitfld.long 0xC 9. "status9,status9" "0,1"
bitfld.long 0xC 8. "status8,status8" "0,1"
newline
bitfld.long 0xC 7. "status7,status7" "0,1"
bitfld.long 0xC 6. "status6,status6" "0,1"
newline
bitfld.long 0xC 5. "status5,status5" "0,1"
bitfld.long 0xC 4. "status4,status4" "0,1"
newline
bitfld.long 0xC 3. "status3,status3" "0,1"
bitfld.long 0xC 2. "status2,status2" "0,1"
newline
bitfld.long 0xC 1. "status1,status1" "0,1"
bitfld.long 0xC 0. "status0,status0" "0,1"
line.long 0x10 "GICDA_IERRR5,GICDA_IERRR5"
bitfld.long 0x10 31. "status31,status31" "0,1"
bitfld.long 0x10 30. "status30,status30" "0,1"
newline
bitfld.long 0x10 29. "status29,status29" "0,1"
bitfld.long 0x10 28. "status28,status28" "0,1"
newline
bitfld.long 0x10 27. "status27,status27" "0,1"
bitfld.long 0x10 26. "status26,status26" "0,1"
newline
bitfld.long 0x10 25. "status25,status25" "0,1"
bitfld.long 0x10 24. "status24,status24" "0,1"
newline
bitfld.long 0x10 23. "status23,status23" "0,1"
bitfld.long 0x10 22. "status22,status22" "0,1"
newline
bitfld.long 0x10 21. "status21,status21" "0,1"
bitfld.long 0x10 20. "status20,status20" "0,1"
newline
bitfld.long 0x10 19. "status19,status19" "0,1"
bitfld.long 0x10 18. "status18,status18" "0,1"
newline
bitfld.long 0x10 17. "status17,status17" "0,1"
bitfld.long 0x10 16. "status16,status16" "0,1"
newline
bitfld.long 0x10 15. "status15,status15" "0,1"
bitfld.long 0x10 14. "status14,status14" "0,1"
newline
bitfld.long 0x10 13. "status13,status13" "0,1"
bitfld.long 0x10 12. "status12,status12" "0,1"
newline
bitfld.long 0x10 11. "status11,status11" "0,1"
bitfld.long 0x10 10. "status10,status10" "0,1"
newline
bitfld.long 0x10 9. "status9,status9" "0,1"
bitfld.long 0x10 8. "status8,status8" "0,1"
newline
bitfld.long 0x10 7. "status7,status7" "0,1"
bitfld.long 0x10 6. "status6,status6" "0,1"
newline
bitfld.long 0x10 5. "status5,status5" "0,1"
bitfld.long 0x10 4. "status4,status4" "0,1"
newline
bitfld.long 0x10 3. "status3,status3" "0,1"
bitfld.long 0x10 2. "status2,status2" "0,1"
newline
bitfld.long 0x10 1. "status1,status1" "0,1"
bitfld.long 0x10 0. "status0,status0" "0,1"
line.long 0x14 "GICDA_IERRR6,GICDA_IERRR6"
bitfld.long 0x14 31. "status31,status31" "0,1"
bitfld.long 0x14 30. "status30,status30" "0,1"
newline
bitfld.long 0x14 29. "status29,status29" "0,1"
bitfld.long 0x14 28. "status28,status28" "0,1"
newline
bitfld.long 0x14 27. "status27,status27" "0,1"
bitfld.long 0x14 26. "status26,status26" "0,1"
newline
bitfld.long 0x14 25. "status25,status25" "0,1"
bitfld.long 0x14 24. "status24,status24" "0,1"
newline
bitfld.long 0x14 23. "status23,status23" "0,1"
bitfld.long 0x14 22. "status22,status22" "0,1"
newline
bitfld.long 0x14 21. "status21,status21" "0,1"
bitfld.long 0x14 20. "status20,status20" "0,1"
newline
bitfld.long 0x14 19. "status19,status19" "0,1"
bitfld.long 0x14 18. "status18,status18" "0,1"
newline
bitfld.long 0x14 17. "status17,status17" "0,1"
bitfld.long 0x14 16. "status16,status16" "0,1"
newline
bitfld.long 0x14 15. "status15,status15" "0,1"
bitfld.long 0x14 14. "status14,status14" "0,1"
newline
bitfld.long 0x14 13. "status13,status13" "0,1"
bitfld.long 0x14 12. "status12,status12" "0,1"
newline
bitfld.long 0x14 11. "status11,status11" "0,1"
bitfld.long 0x14 10. "status10,status10" "0,1"
newline
bitfld.long 0x14 9. "status9,status9" "0,1"
bitfld.long 0x14 8. "status8,status8" "0,1"
newline
bitfld.long 0x14 7. "status7,status7" "0,1"
bitfld.long 0x14 6. "status6,status6" "0,1"
newline
bitfld.long 0x14 5. "status5,status5" "0,1"
bitfld.long 0x14 4. "status4,status4" "0,1"
newline
bitfld.long 0x14 3. "status3,status3" "0,1"
bitfld.long 0x14 2. "status2,status2" "0,1"
newline
bitfld.long 0x14 1. "status1,status1" "0,1"
bitfld.long 0x14 0. "status0,status0" "0,1"
line.long 0x18 "GICDA_IERRR7,GICDA_IERRR7"
bitfld.long 0x18 31. "status31,status31" "0,1"
bitfld.long 0x18 30. "status30,status30" "0,1"
newline
bitfld.long 0x18 29. "status29,status29" "0,1"
bitfld.long 0x18 28. "status28,status28" "0,1"
newline
bitfld.long 0x18 27. "status27,status27" "0,1"
bitfld.long 0x18 26. "status26,status26" "0,1"
newline
bitfld.long 0x18 25. "status25,status25" "0,1"
bitfld.long 0x18 24. "status24,status24" "0,1"
newline
bitfld.long 0x18 23. "status23,status23" "0,1"
bitfld.long 0x18 22. "status22,status22" "0,1"
newline
bitfld.long 0x18 21. "status21,status21" "0,1"
bitfld.long 0x18 20. "status20,status20" "0,1"
newline
bitfld.long 0x18 19. "status19,status19" "0,1"
bitfld.long 0x18 18. "status18,status18" "0,1"
newline
bitfld.long 0x18 17. "status17,status17" "0,1"
bitfld.long 0x18 16. "status16,status16" "0,1"
newline
bitfld.long 0x18 15. "status15,status15" "0,1"
bitfld.long 0x18 14. "status14,status14" "0,1"
newline
bitfld.long 0x18 13. "status13,status13" "0,1"
bitfld.long 0x18 12. "status12,status12" "0,1"
newline
bitfld.long 0x18 11. "status11,status11" "0,1"
bitfld.long 0x18 10. "status10,status10" "0,1"
newline
bitfld.long 0x18 9. "status9,status9" "0,1"
bitfld.long 0x18 8. "status8,status8" "0,1"
newline
bitfld.long 0x18 7. "status7,status7" "0,1"
bitfld.long 0x18 6. "status6,status6" "0,1"
newline
bitfld.long 0x18 5. "status5,status5" "0,1"
bitfld.long 0x18 4. "status4,status4" "0,1"
newline
bitfld.long 0x18 3. "status3,status3" "0,1"
bitfld.long 0x18 2. "status2,status2" "0,1"
newline
bitfld.long 0x18 1. "status1,status1" "0,1"
bitfld.long 0x18 0. "status0,status0" "0,1"
line.long 0x1C "GICDA_IERRR8,GICDA_IERRR8"
bitfld.long 0x1C 31. "status31,status31" "0,1"
bitfld.long 0x1C 30. "status30,status30" "0,1"
newline
bitfld.long 0x1C 29. "status29,status29" "0,1"
bitfld.long 0x1C 28. "status28,status28" "0,1"
newline
bitfld.long 0x1C 27. "status27,status27" "0,1"
bitfld.long 0x1C 26. "status26,status26" "0,1"
newline
bitfld.long 0x1C 25. "status25,status25" "0,1"
bitfld.long 0x1C 24. "status24,status24" "0,1"
newline
bitfld.long 0x1C 23. "status23,status23" "0,1"
bitfld.long 0x1C 22. "status22,status22" "0,1"
newline
bitfld.long 0x1C 21. "status21,status21" "0,1"
bitfld.long 0x1C 20. "status20,status20" "0,1"
newline
bitfld.long 0x1C 19. "status19,status19" "0,1"
bitfld.long 0x1C 18. "status18,status18" "0,1"
newline
bitfld.long 0x1C 17. "status17,status17" "0,1"
bitfld.long 0x1C 16. "status16,status16" "0,1"
newline
bitfld.long 0x1C 15. "status15,status15" "0,1"
bitfld.long 0x1C 14. "status14,status14" "0,1"
newline
bitfld.long 0x1C 13. "status13,status13" "0,1"
bitfld.long 0x1C 12. "status12,status12" "0,1"
newline
bitfld.long 0x1C 11. "status11,status11" "0,1"
bitfld.long 0x1C 10. "status10,status10" "0,1"
newline
bitfld.long 0x1C 9. "status9,status9" "0,1"
bitfld.long 0x1C 8. "status8,status8" "0,1"
newline
bitfld.long 0x1C 7. "status7,status7" "0,1"
bitfld.long 0x1C 6. "status6,status6" "0,1"
newline
bitfld.long 0x1C 5. "status5,status5" "0,1"
bitfld.long 0x1C 4. "status4,status4" "0,1"
newline
bitfld.long 0x1C 3. "status3,status3" "0,1"
bitfld.long 0x1C 2. "status2,status2" "0,1"
newline
bitfld.long 0x1C 1. "status1,status1" "0,1"
bitfld.long 0x1C 0. "status0,status0" "0,1"
line.long 0x20 "GICDA_IERRR9,GICDA_IERRR9"
bitfld.long 0x20 31. "status31,status31" "0,1"
bitfld.long 0x20 30. "status30,status30" "0,1"
newline
bitfld.long 0x20 29. "status29,status29" "0,1"
bitfld.long 0x20 28. "status28,status28" "0,1"
newline
bitfld.long 0x20 27. "status27,status27" "0,1"
bitfld.long 0x20 26. "status26,status26" "0,1"
newline
bitfld.long 0x20 25. "status25,status25" "0,1"
bitfld.long 0x20 24. "status24,status24" "0,1"
newline
bitfld.long 0x20 23. "status23,status23" "0,1"
bitfld.long 0x20 22. "status22,status22" "0,1"
newline
bitfld.long 0x20 21. "status21,status21" "0,1"
bitfld.long 0x20 20. "status20,status20" "0,1"
newline
bitfld.long 0x20 19. "status19,status19" "0,1"
bitfld.long 0x20 18. "status18,status18" "0,1"
newline
bitfld.long 0x20 17. "status17,status17" "0,1"
bitfld.long 0x20 16. "status16,status16" "0,1"
newline
bitfld.long 0x20 15. "status15,status15" "0,1"
bitfld.long 0x20 14. "status14,status14" "0,1"
newline
bitfld.long 0x20 13. "status13,status13" "0,1"
bitfld.long 0x20 12. "status12,status12" "0,1"
newline
bitfld.long 0x20 11. "status11,status11" "0,1"
bitfld.long 0x20 10. "status10,status10" "0,1"
newline
bitfld.long 0x20 9. "status9,status9" "0,1"
bitfld.long 0x20 8. "status8,status8" "0,1"
newline
bitfld.long 0x20 7. "status7,status7" "0,1"
bitfld.long 0x20 6. "status6,status6" "0,1"
newline
bitfld.long 0x20 5. "status5,status5" "0,1"
bitfld.long 0x20 4. "status4,status4" "0,1"
newline
bitfld.long 0x20 3. "status3,status3" "0,1"
bitfld.long 0x20 2. "status2,status2" "0,1"
newline
bitfld.long 0x20 1. "status1,status1" "0,1"
bitfld.long 0x20 0. "status0,status0" "0,1"
line.long 0x24 "GICDA_IERRR10,GICDA_IERRR10"
bitfld.long 0x24 31. "status31,status31" "0,1"
bitfld.long 0x24 30. "status30,status30" "0,1"
newline
bitfld.long 0x24 29. "status29,status29" "0,1"
bitfld.long 0x24 28. "status28,status28" "0,1"
newline
bitfld.long 0x24 27. "status27,status27" "0,1"
bitfld.long 0x24 26. "status26,status26" "0,1"
newline
bitfld.long 0x24 25. "status25,status25" "0,1"
bitfld.long 0x24 24. "status24,status24" "0,1"
newline
bitfld.long 0x24 23. "status23,status23" "0,1"
bitfld.long 0x24 22. "status22,status22" "0,1"
newline
bitfld.long 0x24 21. "status21,status21" "0,1"
bitfld.long 0x24 20. "status20,status20" "0,1"
newline
bitfld.long 0x24 19. "status19,status19" "0,1"
bitfld.long 0x24 18. "status18,status18" "0,1"
newline
bitfld.long 0x24 17. "status17,status17" "0,1"
bitfld.long 0x24 16. "status16,status16" "0,1"
newline
bitfld.long 0x24 15. "status15,status15" "0,1"
bitfld.long 0x24 14. "status14,status14" "0,1"
newline
bitfld.long 0x24 13. "status13,status13" "0,1"
bitfld.long 0x24 12. "status12,status12" "0,1"
newline
bitfld.long 0x24 11. "status11,status11" "0,1"
bitfld.long 0x24 10. "status10,status10" "0,1"
newline
bitfld.long 0x24 9. "status9,status9" "0,1"
bitfld.long 0x24 8. "status8,status8" "0,1"
newline
bitfld.long 0x24 7. "status7,status7" "0,1"
bitfld.long 0x24 6. "status6,status6" "0,1"
newline
bitfld.long 0x24 5. "status5,status5" "0,1"
bitfld.long 0x24 4. "status4,status4" "0,1"
newline
bitfld.long 0x24 3. "status3,status3" "0,1"
bitfld.long 0x24 2. "status2,status2" "0,1"
newline
bitfld.long 0x24 1. "status1,status1" "0,1"
bitfld.long 0x24 0. "status0,status0" "0,1"
line.long 0x28 "GICDA_IERRR11,GICDA_IERRR11"
bitfld.long 0x28 31. "status31,status31" "0,1"
bitfld.long 0x28 30. "status30,status30" "0,1"
newline
bitfld.long 0x28 29. "status29,status29" "0,1"
bitfld.long 0x28 28. "status28,status28" "0,1"
newline
bitfld.long 0x28 27. "status27,status27" "0,1"
bitfld.long 0x28 26. "status26,status26" "0,1"
newline
bitfld.long 0x28 25. "status25,status25" "0,1"
bitfld.long 0x28 24. "status24,status24" "0,1"
newline
bitfld.long 0x28 23. "status23,status23" "0,1"
bitfld.long 0x28 22. "status22,status22" "0,1"
newline
bitfld.long 0x28 21. "status21,status21" "0,1"
bitfld.long 0x28 20. "status20,status20" "0,1"
newline
bitfld.long 0x28 19. "status19,status19" "0,1"
bitfld.long 0x28 18. "status18,status18" "0,1"
newline
bitfld.long 0x28 17. "status17,status17" "0,1"
bitfld.long 0x28 16. "status16,status16" "0,1"
newline
bitfld.long 0x28 15. "status15,status15" "0,1"
bitfld.long 0x28 14. "status14,status14" "0,1"
newline
bitfld.long 0x28 13. "status13,status13" "0,1"
bitfld.long 0x28 12. "status12,status12" "0,1"
newline
bitfld.long 0x28 11. "status11,status11" "0,1"
bitfld.long 0x28 10. "status10,status10" "0,1"
newline
bitfld.long 0x28 9. "status9,status9" "0,1"
bitfld.long 0x28 8. "status8,status8" "0,1"
newline
bitfld.long 0x28 7. "status7,status7" "0,1"
bitfld.long 0x28 6. "status6,status6" "0,1"
newline
bitfld.long 0x28 5. "status5,status5" "0,1"
bitfld.long 0x28 4. "status4,status4" "0,1"
newline
bitfld.long 0x28 3. "status3,status3" "0,1"
bitfld.long 0x28 2. "status2,status2" "0,1"
newline
bitfld.long 0x28 1. "status1,status1" "0,1"
bitfld.long 0x28 0. "status0,status0" "0,1"
line.long 0x2C "GICDA_IERRR12,GICDA_IERRR12"
bitfld.long 0x2C 31. "status31,status31" "0,1"
bitfld.long 0x2C 30. "status30,status30" "0,1"
newline
bitfld.long 0x2C 29. "status29,status29" "0,1"
bitfld.long 0x2C 28. "status28,status28" "0,1"
newline
bitfld.long 0x2C 27. "status27,status27" "0,1"
bitfld.long 0x2C 26. "status26,status26" "0,1"
newline
bitfld.long 0x2C 25. "status25,status25" "0,1"
bitfld.long 0x2C 24. "status24,status24" "0,1"
newline
bitfld.long 0x2C 23. "status23,status23" "0,1"
bitfld.long 0x2C 22. "status22,status22" "0,1"
newline
bitfld.long 0x2C 21. "status21,status21" "0,1"
bitfld.long 0x2C 20. "status20,status20" "0,1"
newline
bitfld.long 0x2C 19. "status19,status19" "0,1"
bitfld.long 0x2C 18. "status18,status18" "0,1"
newline
bitfld.long 0x2C 17. "status17,status17" "0,1"
bitfld.long 0x2C 16. "status16,status16" "0,1"
newline
bitfld.long 0x2C 15. "status15,status15" "0,1"
bitfld.long 0x2C 14. "status14,status14" "0,1"
newline
bitfld.long 0x2C 13. "status13,status13" "0,1"
bitfld.long 0x2C 12. "status12,status12" "0,1"
newline
bitfld.long 0x2C 11. "status11,status11" "0,1"
bitfld.long 0x2C 10. "status10,status10" "0,1"
newline
bitfld.long 0x2C 9. "status9,status9" "0,1"
bitfld.long 0x2C 8. "status8,status8" "0,1"
newline
bitfld.long 0x2C 7. "status7,status7" "0,1"
bitfld.long 0x2C 6. "status6,status6" "0,1"
newline
bitfld.long 0x2C 5. "status5,status5" "0,1"
bitfld.long 0x2C 4. "status4,status4" "0,1"
newline
bitfld.long 0x2C 3. "status3,status3" "0,1"
bitfld.long 0x2C 2. "status2,status2" "0,1"
newline
bitfld.long 0x2C 1. "status1,status1" "0,1"
bitfld.long 0x2C 0. "status0,status0" "0,1"
line.long 0x30 "GICDA_IERRR13,GICDA_IERRR13"
bitfld.long 0x30 31. "status31,status31" "0,1"
bitfld.long 0x30 30. "status30,status30" "0,1"
newline
bitfld.long 0x30 29. "status29,status29" "0,1"
bitfld.long 0x30 28. "status28,status28" "0,1"
newline
bitfld.long 0x30 27. "status27,status27" "0,1"
bitfld.long 0x30 26. "status26,status26" "0,1"
newline
bitfld.long 0x30 25. "status25,status25" "0,1"
bitfld.long 0x30 24. "status24,status24" "0,1"
newline
bitfld.long 0x30 23. "status23,status23" "0,1"
bitfld.long 0x30 22. "status22,status22" "0,1"
newline
bitfld.long 0x30 21. "status21,status21" "0,1"
bitfld.long 0x30 20. "status20,status20" "0,1"
newline
bitfld.long 0x30 19. "status19,status19" "0,1"
bitfld.long 0x30 18. "status18,status18" "0,1"
newline
bitfld.long 0x30 17. "status17,status17" "0,1"
bitfld.long 0x30 16. "status16,status16" "0,1"
newline
bitfld.long 0x30 15. "status15,status15" "0,1"
bitfld.long 0x30 14. "status14,status14" "0,1"
newline
bitfld.long 0x30 13. "status13,status13" "0,1"
bitfld.long 0x30 12. "status12,status12" "0,1"
newline
bitfld.long 0x30 11. "status11,status11" "0,1"
bitfld.long 0x30 10. "status10,status10" "0,1"
newline
bitfld.long 0x30 9. "status9,status9" "0,1"
bitfld.long 0x30 8. "status8,status8" "0,1"
newline
bitfld.long 0x30 7. "status7,status7" "0,1"
bitfld.long 0x30 6. "status6,status6" "0,1"
newline
bitfld.long 0x30 5. "status5,status5" "0,1"
bitfld.long 0x30 4. "status4,status4" "0,1"
newline
bitfld.long 0x30 3. "status3,status3" "0,1"
bitfld.long 0x30 2. "status2,status2" "0,1"
newline
bitfld.long 0x30 1. "status1,status1" "0,1"
bitfld.long 0x30 0. "status0,status0" "0,1"
line.long 0x34 "GICDA_IERRR14,GICDA_IERRR14"
bitfld.long 0x34 31. "status31,status31" "0,1"
bitfld.long 0x34 30. "status30,status30" "0,1"
newline
bitfld.long 0x34 29. "status29,status29" "0,1"
bitfld.long 0x34 28. "status28,status28" "0,1"
newline
bitfld.long 0x34 27. "status27,status27" "0,1"
bitfld.long 0x34 26. "status26,status26" "0,1"
newline
bitfld.long 0x34 25. "status25,status25" "0,1"
bitfld.long 0x34 24. "status24,status24" "0,1"
newline
bitfld.long 0x34 23. "status23,status23" "0,1"
bitfld.long 0x34 22. "status22,status22" "0,1"
newline
bitfld.long 0x34 21. "status21,status21" "0,1"
bitfld.long 0x34 20. "status20,status20" "0,1"
newline
bitfld.long 0x34 19. "status19,status19" "0,1"
bitfld.long 0x34 18. "status18,status18" "0,1"
newline
bitfld.long 0x34 17. "status17,status17" "0,1"
bitfld.long 0x34 16. "status16,status16" "0,1"
newline
bitfld.long 0x34 15. "status15,status15" "0,1"
bitfld.long 0x34 14. "status14,status14" "0,1"
newline
bitfld.long 0x34 13. "status13,status13" "0,1"
bitfld.long 0x34 12. "status12,status12" "0,1"
newline
bitfld.long 0x34 11. "status11,status11" "0,1"
bitfld.long 0x34 10. "status10,status10" "0,1"
newline
bitfld.long 0x34 9. "status9,status9" "0,1"
bitfld.long 0x34 8. "status8,status8" "0,1"
newline
bitfld.long 0x34 7. "status7,status7" "0,1"
bitfld.long 0x34 6. "status6,status6" "0,1"
newline
bitfld.long 0x34 5. "status5,status5" "0,1"
bitfld.long 0x34 4. "status4,status4" "0,1"
newline
bitfld.long 0x34 3. "status3,status3" "0,1"
bitfld.long 0x34 2. "status2,status2" "0,1"
newline
bitfld.long 0x34 1. "status1,status1" "0,1"
bitfld.long 0x34 0. "status0,status0" "0,1"
line.long 0x38 "GICDA_IERRR15,GICDA_IERRR15"
bitfld.long 0x38 31. "status31,status31" "0,1"
bitfld.long 0x38 30. "status30,status30" "0,1"
newline
bitfld.long 0x38 29. "status29,status29" "0,1"
bitfld.long 0x38 28. "status28,status28" "0,1"
newline
bitfld.long 0x38 27. "status27,status27" "0,1"
bitfld.long 0x38 26. "status26,status26" "0,1"
newline
bitfld.long 0x38 25. "status25,status25" "0,1"
bitfld.long 0x38 24. "status24,status24" "0,1"
newline
bitfld.long 0x38 23. "status23,status23" "0,1"
bitfld.long 0x38 22. "status22,status22" "0,1"
newline
bitfld.long 0x38 21. "status21,status21" "0,1"
bitfld.long 0x38 20. "status20,status20" "0,1"
newline
bitfld.long 0x38 19. "status19,status19" "0,1"
bitfld.long 0x38 18. "status18,status18" "0,1"
newline
bitfld.long 0x38 17. "status17,status17" "0,1"
bitfld.long 0x38 16. "status16,status16" "0,1"
newline
bitfld.long 0x38 15. "status15,status15" "0,1"
bitfld.long 0x38 14. "status14,status14" "0,1"
newline
bitfld.long 0x38 13. "status13,status13" "0,1"
bitfld.long 0x38 12. "status12,status12" "0,1"
newline
bitfld.long 0x38 11. "status11,status11" "0,1"
bitfld.long 0x38 10. "status10,status10" "0,1"
newline
bitfld.long 0x38 9. "status9,status9" "0,1"
bitfld.long 0x38 8. "status8,status8" "0,1"
newline
bitfld.long 0x38 7. "status7,status7" "0,1"
bitfld.long 0x38 6. "status6,status6" "0,1"
newline
bitfld.long 0x38 5. "status5,status5" "0,1"
bitfld.long 0x38 4. "status4,status4" "0,1"
newline
bitfld.long 0x38 3. "status3,status3" "0,1"
bitfld.long 0x38 2. "status2,status2" "0,1"
newline
bitfld.long 0x38 1. "status1,status1" "0,1"
bitfld.long 0x38 0. "status0,status0" "0,1"
line.long 0x3C "GICDA_IERRR16,GICDA_IERRR16"
bitfld.long 0x3C 31. "status31,status31" "0,1"
bitfld.long 0x3C 30. "status30,status30" "0,1"
newline
bitfld.long 0x3C 29. "status29,status29" "0,1"
bitfld.long 0x3C 28. "status28,status28" "0,1"
newline
bitfld.long 0x3C 27. "status27,status27" "0,1"
bitfld.long 0x3C 26. "status26,status26" "0,1"
newline
bitfld.long 0x3C 25. "status25,status25" "0,1"
bitfld.long 0x3C 24. "status24,status24" "0,1"
newline
bitfld.long 0x3C 23. "status23,status23" "0,1"
bitfld.long 0x3C 22. "status22,status22" "0,1"
newline
bitfld.long 0x3C 21. "status21,status21" "0,1"
bitfld.long 0x3C 20. "status20,status20" "0,1"
newline
bitfld.long 0x3C 19. "status19,status19" "0,1"
bitfld.long 0x3C 18. "status18,status18" "0,1"
newline
bitfld.long 0x3C 17. "status17,status17" "0,1"
bitfld.long 0x3C 16. "status16,status16" "0,1"
newline
bitfld.long 0x3C 15. "status15,status15" "0,1"
bitfld.long 0x3C 14. "status14,status14" "0,1"
newline
bitfld.long 0x3C 13. "status13,status13" "0,1"
bitfld.long 0x3C 12. "status12,status12" "0,1"
newline
bitfld.long 0x3C 11. "status11,status11" "0,1"
bitfld.long 0x3C 10. "status10,status10" "0,1"
newline
bitfld.long 0x3C 9. "status9,status9" "0,1"
bitfld.long 0x3C 8. "status8,status8" "0,1"
newline
bitfld.long 0x3C 7. "status7,status7" "0,1"
bitfld.long 0x3C 6. "status6,status6" "0,1"
newline
bitfld.long 0x3C 5. "status5,status5" "0,1"
bitfld.long 0x3C 4. "status4,status4" "0,1"
newline
bitfld.long 0x3C 3. "status3,status3" "0,1"
bitfld.long 0x3C 2. "status2,status2" "0,1"
newline
bitfld.long 0x3C 1. "status1,status1" "0,1"
bitfld.long 0x3C 0. "status0,status0" "0,1"
line.long 0x40 "GICDA_IERRR17,GICDA_IERRR17"
bitfld.long 0x40 31. "status31,status31" "0,1"
bitfld.long 0x40 30. "status30,status30" "0,1"
newline
bitfld.long 0x40 29. "status29,status29" "0,1"
bitfld.long 0x40 28. "status28,status28" "0,1"
newline
bitfld.long 0x40 27. "status27,status27" "0,1"
bitfld.long 0x40 26. "status26,status26" "0,1"
newline
bitfld.long 0x40 25. "status25,status25" "0,1"
bitfld.long 0x40 24. "status24,status24" "0,1"
newline
bitfld.long 0x40 23. "status23,status23" "0,1"
bitfld.long 0x40 22. "status22,status22" "0,1"
newline
bitfld.long 0x40 21. "status21,status21" "0,1"
bitfld.long 0x40 20. "status20,status20" "0,1"
newline
bitfld.long 0x40 19. "status19,status19" "0,1"
bitfld.long 0x40 18. "status18,status18" "0,1"
newline
bitfld.long 0x40 17. "status17,status17" "0,1"
bitfld.long 0x40 16. "status16,status16" "0,1"
newline
bitfld.long 0x40 15. "status15,status15" "0,1"
bitfld.long 0x40 14. "status14,status14" "0,1"
newline
bitfld.long 0x40 13. "status13,status13" "0,1"
bitfld.long 0x40 12. "status12,status12" "0,1"
newline
bitfld.long 0x40 11. "status11,status11" "0,1"
bitfld.long 0x40 10. "status10,status10" "0,1"
newline
bitfld.long 0x40 9. "status9,status9" "0,1"
bitfld.long 0x40 8. "status8,status8" "0,1"
newline
bitfld.long 0x40 7. "status7,status7" "0,1"
bitfld.long 0x40 6. "status6,status6" "0,1"
newline
bitfld.long 0x40 5. "status5,status5" "0,1"
bitfld.long 0x40 4. "status4,status4" "0,1"
newline
bitfld.long 0x40 3. "status3,status3" "0,1"
bitfld.long 0x40 2. "status2,status2" "0,1"
newline
bitfld.long 0x40 1. "status1,status1" "0,1"
bitfld.long 0x40 0. "status0,status0" "0,1"
rgroup.quad 0xEF000++0x7
line.quad 0x0 "GICDA_CFGID,GICDA_CFGID"
hexmask.quad.word 0x0 53.--63. 1. "RESERVED3,RESERVED3"
hexmask.quad.byte 0x0 48.--52. 1. "PEwidth,PEwidth"
newline
hexmask.quad.byte 0x0 44.--47. 1. "Affinity3Bits,Affinity3Bits"
hexmask.quad.byte 0x0 40.--43. 1. "Affinity2Bits,Affinity2Bits"
newline
hexmask.quad.byte 0x0 36.--39. 1. "Affinity1Bits,Affinity1Bits"
hexmask.quad.byte 0x0 32.--35. 1. "Affinity0Bits,Affinity0Bits"
newline
hexmask.quad.word 0x0 21.--31. 1. "RESERVED2,RESERVED2"
hexmask.quad.byte 0x0 15.--20. 1. "SPIGroups,SPIGroups"
newline
bitfld.quad 0x0 14. "ChipAffinityLevel,ChipAffinityLevel" "0,1"
bitfld.quad 0x0 13. "DirectLPI,DirectLPI" "0,1"
newline
bitfld.quad 0x0 12. "LPISupport,LPISupport" "0,1"
hexmask.quad.byte 0x0 8.--11. 1. "RESERVED1,RESERVED1"
newline
hexmask.quad.byte 0x0 4.--7. 1. "SocketNumber,SocketNumber"
bitfld.quad 0x0 1.--3. "RESERVED0,RESERVED0" "0,1,2,3,4,5,6,7"
newline
bitfld.quad 0x0 0. "SocketOffline,SocketOffline" "0,1"
rgroup.long 0xEFFD0++0x2F
line.long 0x0 "GICDA_PIDR4,GICDA_PIDR4"
hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x0 4.--7. 1. "SIZE,SIZE"
newline
hexmask.long.byte 0x0 0.--3. 1. "DES_2,DES_2"
line.long 0x4 "GICDA_PIDR5,GICDA_PIDR5"
hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x4 0.--7. 1. "RESERVED,RESERVED"
line.long 0x8 "GICDA_PIDR6,GICDA_PIDR6"
hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x8 0.--7. 1. "RESERVED,RESERVED"
line.long 0xC "GICDA_PIDR7,GICDA_PIDR7"
hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0xC 0.--7. 1. "RESERVED,RESERVED"
line.long 0x10 "GICDA_PIDR0,GICDA_PIDR0"
hexmask.long.tbyte 0x10 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x10 0.--7. 1. "PART_0,PART_0"
line.long 0x14 "GICDA_PIDR1,GICDA_PIDR1"
hexmask.long.tbyte 0x14 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x14 4.--7. 1. "DES_0,DES_0"
newline
hexmask.long.byte 0x14 0.--3. 1. "PART_1,PART_1"
line.long 0x18 "GICDA_PIDR2,GICDA_PIDR2"
hexmask.long.tbyte 0x18 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x18 4.--7. 1. "REVISION,REVISION"
newline
bitfld.long 0x18 3. "JEDEC,JEDEC" "0,1"
bitfld.long 0x18 0.--2. "DES_1,DES_1" "0,1,2,3,4,5,6,7"
line.long 0x1C "GICDA_PIDR3,GICDA_PIDR3"
hexmask.long.tbyte 0x1C 8.--31. 1. "RESERVED1,RESERVED1"
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,REVAND"
newline
bitfld.long 0x1C 3. "RESERVED0,RESERVED0" "0,1"
bitfld.long 0x1C 0.--2. "CMOD,CMOD" "0,1,2,3,4,5,6,7"
line.long 0x20 "GICDA_CIDR0,GICDA_CIDR0"
hexmask.long.tbyte 0x20 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x20 0.--7. 1. "PRMBL_0,PRMBL_0"
line.long 0x24 "GICDA_CIDR1,GICDA_CIDR1"
hexmask.long.tbyte 0x24 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x24 4.--7. 1. "CLASS,CLASS"
newline
hexmask.long.byte 0x24 0.--3. 1. "PRMBL_1,PRMBL_1"
line.long 0x28 "GICDA_CIDR2,GICDA_CIDR2"
hexmask.long.tbyte 0x28 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_2,PRMBL_2"
line.long 0x2C "GICDA_CIDR3,GICDA_CIDR3"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED0,RESERVED0"
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_3,PRMBL_3"
tree.end
tree "GPIO (General-Purpose I/O Interface)"
base ad:0x0
tree "GPIO_0"
base ad:0x10C03200
group.long 0x0++0x7
line.long 0x0 "GPIO_SWPORTA_DR,Name: Port A data register"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_SWPORTA_DR,Values written to this register are output on the I/O signals"
line.long 0x4 "GPIO_SWPORTA_DDR,Name: Port A Data Direction Register"
hexmask.long.byte 0x4 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_SWPORTA_DDR,Values written to this register independently control the"
group.long 0x30++0xF
line.long 0x0 "GPIO_INTEN,Name: Interrupt enable register"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_INTEN,Allows each bit of Port A to be configured for interrupts. By"
line.long 0x4 "GPIO_INTMASK,Name: Interrupt mask register"
hexmask.long.byte 0x4 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_INTMASK,Controls whether an interrupt on Port A can create an"
line.long 0x8 "GPIO_INTTYPE_LEVEL,Name: Interrupt level"
hexmask.long.byte 0x8 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x8 0.--23. 1. "GPIO_INTTYPE_LEVEL,Controls the type of interrupt that can occur on Port A."
line.long 0xC "GPIO_INT_POLARITY,Name: Interrupt polarity"
hexmask.long.byte 0xC 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0xC 0.--23. 1. "GPIO_INT_POLARITY,Controls the polarity of edge or level sensitivity that can"
rgroup.long 0x40++0x7
line.long 0x0 "GPIO_INTSTATUS,Name: Interrupt status"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_INTSTATUS,Interrupt status of Port A."
line.long 0x4 "GPIO_RAW_INTSTATUS,Name: Raw interrupt status"
hexmask.long.byte 0x4 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_RAW_INTSTATUS,Raw interrupt of status of Port A (premasking bits)"
group.long 0x48++0x3
line.long 0x0 "GPIO_DEBOUNCE,Name: Debounce enable"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_DEBOUNCE,Controls whether an external signal that is the source"
wgroup.long 0x4C++0x3
line.long 0x0 "GPIO_PORTA_EOI,Name: Port A clear interrupt register"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_PORTA_EOI,Controls the clearing of edge type interrupts from Port A."
rgroup.long 0x50++0x3
line.long 0x0 "GPIO_EXT_PORTA,Name: Port A external port register"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_EXT_PORTA,This register always reflects the signals value on the External Port A."
group.long 0x60++0x3
line.long 0x0 "GPIO_LS_SYNC,Name: Synchronization level"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "GPIO_LS_SYNC,Writing a 1 to this register results in all level-sensitive interrupts being" "0,1"
rgroup.long 0x64++0x3
line.long 0x0 "GPIO_ID_CODE,Name: GPIO ID code"
hexmask.long 0x0 0.--31. 1. "GPIO_ID_CODE,This is a user-specified code that a system can read. It can"
rgroup.long 0x6C++0xB
line.long 0x0 "GPIO_VER_ID_CODE,Name: GPIO Component Version"
hexmask.long 0x0 0.--31. 1. "GPIO_VER_ID_CODE,ASCII value for each number in the version."
line.long 0x4 "GPIO_CONFIG_REG2,Name: GPIO Configuration Register 2"
hexmask.long.word 0x4 20.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 15.--19. 1. "ENCODED_ID_PWIDTH_D,The value of this register is derived from the"
hexmask.long.byte 0x4 10.--14. 1. "ENCODED_ID_PWIDTH_C,The value of this register is derived from the"
newline
hexmask.long.byte 0x4 5.--9. 1. "ENCODED_ID_PWIDTH_B,The value of this register is derived from the"
hexmask.long.byte 0x4 0.--4. 1. "ENCODED_ID_PWIDTH_A,The value of this register is derived from the"
line.long 0x8 "GPIO_CONFIG_REG1,Name: GPIO Configuration Register 1"
hexmask.long.word 0x8 22.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
bitfld.long 0x8 21. "INTERRUPT_BOTH_EDGE_TYPE,The value of this register is derived from the" "0,1"
hexmask.long.byte 0x8 16.--20. 1. "ENCODED_ID_WIDTH,The value of this register is derived from the"
newline
bitfld.long 0x8 15. "GPIO_ID,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 14. "ADD_ENCODED_PARAMS,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 13. "DEBOUNCE,The value of this register is derived from the" "0: Exclude,1: Include"
newline
bitfld.long 0x8 12. "PORTA_INTR,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 11. "HW_PORTD,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 10. "HW_PORTC,The value of this register is derived from the" "0: Exclude,1: Include"
newline
bitfld.long 0x8 9. "HW_PORTB,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 8. "HW_PORTA,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 7. "PORTD_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
newline
bitfld.long 0x8 6. "PORTC_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 5. "PORTB_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 4. "PORTA_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
newline
bitfld.long 0x8 2.--3. "NUM_PORTS,The value of this register is derived from the" "0: 1,1: 2,2: 3,3: 4"
bitfld.long 0x8 0.--1. "APB_DATA_WIDTH,The value of this register is derived from the" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
tree.end
tree "GPIO_1"
base ad:0x10C03300
group.long 0x0++0x7
line.long 0x0 "GPIO_SWPORTA_DR,Name: Port A data register"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_SWPORTA_DR,Values written to this register are output on the I/O signals"
line.long 0x4 "GPIO_SWPORTA_DDR,Name: Port A Data Direction Register"
hexmask.long.byte 0x4 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_SWPORTA_DDR,Values written to this register independently control the"
group.long 0x30++0xF
line.long 0x0 "GPIO_INTEN,Name: Interrupt enable register"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_INTEN,Allows each bit of Port A to be configured for interrupts. By"
line.long 0x4 "GPIO_INTMASK,Name: Interrupt mask register"
hexmask.long.byte 0x4 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_INTMASK,Controls whether an interrupt on Port A can create an"
line.long 0x8 "GPIO_INTTYPE_LEVEL,Name: Interrupt level"
hexmask.long.byte 0x8 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x8 0.--23. 1. "GPIO_INTTYPE_LEVEL,Controls the type of interrupt that can occur on Port A."
line.long 0xC "GPIO_INT_POLARITY,Name: Interrupt polarity"
hexmask.long.byte 0xC 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0xC 0.--23. 1. "GPIO_INT_POLARITY,Controls the polarity of edge or level sensitivity that can"
rgroup.long 0x40++0x7
line.long 0x0 "GPIO_INTSTATUS,Name: Interrupt status"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_INTSTATUS,Interrupt status of Port A."
line.long 0x4 "GPIO_RAW_INTSTATUS,Name: Raw interrupt status"
hexmask.long.byte 0x4 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x4 0.--23. 1. "GPIO_RAW_INTSTATUS,Raw interrupt of status of Port A (premasking bits)"
group.long 0x48++0x3
line.long 0x0 "GPIO_DEBOUNCE,Name: Debounce enable"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_DEBOUNCE,Controls whether an external signal that is the source"
wgroup.long 0x4C++0x3
line.long 0x0 "GPIO_PORTA_EOI,Name: Port A clear interrupt register"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_PORTA_EOI,Controls the clearing of edge type interrupts from Port A."
rgroup.long 0x50++0x3
line.long 0x0 "GPIO_EXT_PORTA,Name: Port A external port register"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x0 0.--23. 1. "GPIO_EXT_PORTA,This register always reflects the signals value on the External Port A."
group.long 0x60++0x3
line.long 0x0 "GPIO_LS_SYNC,Name: Synchronization level"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "GPIO_LS_SYNC,Writing a 1 to this register results in all level-sensitive interrupts being" "0,1"
rgroup.long 0x64++0x3
line.long 0x0 "GPIO_ID_CODE,Name: GPIO ID code"
hexmask.long 0x0 0.--31. 1. "GPIO_ID_CODE,This is a user-specified code that a system can read. It can"
rgroup.long 0x6C++0xB
line.long 0x0 "GPIO_VER_ID_CODE,Name: GPIO Component Version"
hexmask.long 0x0 0.--31. 1. "GPIO_VER_ID_CODE,ASCII value for each number in the version."
line.long 0x4 "GPIO_CONFIG_REG2,Name: GPIO Configuration Register 2"
hexmask.long.word 0x4 20.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 15.--19. 1. "ENCODED_ID_PWIDTH_D,The value of this register is derived from the"
hexmask.long.byte 0x4 10.--14. 1. "ENCODED_ID_PWIDTH_C,The value of this register is derived from the"
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hexmask.long.byte 0x4 5.--9. 1. "ENCODED_ID_PWIDTH_B,The value of this register is derived from the"
hexmask.long.byte 0x4 0.--4. 1. "ENCODED_ID_PWIDTH_A,The value of this register is derived from the"
line.long 0x8 "GPIO_CONFIG_REG1,Name: GPIO Configuration Register 1"
hexmask.long.word 0x8 22.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
bitfld.long 0x8 21. "INTERRUPT_BOTH_EDGE_TYPE,The value of this register is derived from the" "0,1"
hexmask.long.byte 0x8 16.--20. 1. "ENCODED_ID_WIDTH,The value of this register is derived from the"
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bitfld.long 0x8 15. "GPIO_ID,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 14. "ADD_ENCODED_PARAMS,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 13. "DEBOUNCE,The value of this register is derived from the" "0: Exclude,1: Include"
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bitfld.long 0x8 12. "PORTA_INTR,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 11. "HW_PORTD,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 10. "HW_PORTC,The value of this register is derived from the" "0: Exclude,1: Include"
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bitfld.long 0x8 9. "HW_PORTB,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 8. "HW_PORTA,The value of this register is derived from the" "0: Exclude,1: Include"
bitfld.long 0x8 7. "PORTD_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
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bitfld.long 0x8 6. "PORTC_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 5. "PORTB_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
bitfld.long 0x8 4. "PORTA_SINGLE_CTL,The value of this register is derived from the" "0: False,1: True"
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bitfld.long 0x8 2.--3. "NUM_PORTS,The value of this register is derived from the" "0: 1,1: 2,2: 3,3: 4"
bitfld.long 0x8 0.--1. "APB_DATA_WIDTH,The value of this register is derived from the" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
tree.end
tree.end
tree "I2C (I2C Controller)"
base ad:0x0
tree "I2C_0"
base ad:0x10C02800
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
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rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
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rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
newline
bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
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bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
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rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
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rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
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rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
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bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
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rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
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hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
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hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
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bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
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bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
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bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
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bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
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bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
newline
bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
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rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
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bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
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bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
newline
bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
newline
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
newline
bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
newline
bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
newline
bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
newline
bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
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rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
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hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
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rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
newline
bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
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bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
newline
bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
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bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
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bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
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bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
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bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
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bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
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hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
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bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
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bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW" "0,1"
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bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
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bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
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bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
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bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
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bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
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bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
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bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
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bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
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bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
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bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
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bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
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bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
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bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
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hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
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hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
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bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
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bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
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bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
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hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
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bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
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hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
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bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
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bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
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bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
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bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree "I2C_1"
base ad:0x10C02900
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
newline
rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
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bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
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bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
newline
rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
newline
rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
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rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
newline
bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
newline
bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
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bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
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bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
newline
bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
newline
bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
newline
bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
newline
bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
newline
bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
newline
bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
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hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
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bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
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bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
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bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
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bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
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bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
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bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
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bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
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bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
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bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
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bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
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bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
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rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
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hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
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rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
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bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
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bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
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bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
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bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
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bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
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bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
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bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
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bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
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hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
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bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
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bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW" "0,1"
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bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
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bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
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bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
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bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
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bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
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bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
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bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
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bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
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bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
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bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
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bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
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bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
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bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
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hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
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hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
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bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
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bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
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bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
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hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
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bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
newline
hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
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bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
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bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
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bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
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bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree "I2C_EMAC_0"
base ad:0x10C02A00
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
newline
rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
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bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
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bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
newline
rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
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rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
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rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
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bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
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rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
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hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
newline
hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
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bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
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bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
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bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
newline
bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
newline
rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
newline
bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
newline
bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
newline
bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
newline
bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
newline
bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
newline
bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
newline
bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
newline
bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
newline
bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
newline
bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
newline
bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
newline
bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
newline
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
newline
bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
newline
bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
newline
bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
newline
bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
newline
hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
newline
bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
newline
bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
newline
bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
newline
bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
newline
bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
newline
bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
newline
bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
newline
bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
newline
hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
newline
bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
newline
bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW" "0,1"
newline
bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
newline
bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
newline
bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
newline
bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
newline
bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
newline
bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
newline
bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
newline
bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
newline
bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
newline
bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
newline
bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
newline
bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
newline
bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
newline
bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
newline
bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
newline
bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
newline
bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
newline
bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
newline
hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
newline
bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
newline
bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
newline
bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
newline
bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
newline
hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
newline
bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
newline
bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
newline
bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree "I2C_EMAC_1"
base ad:0x10C02B00
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
newline
rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
newline
hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
newline
rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
newline
rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
newline
rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
newline
bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
newline
bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
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bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
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rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
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rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
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rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
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bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
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hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
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rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
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hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
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hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
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bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
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bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
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bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
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bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
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bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
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bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
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rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
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bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
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bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
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bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
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bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
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bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
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bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
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hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
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bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
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bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
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bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
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bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
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bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
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bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
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bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
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bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
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bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
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bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
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bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
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rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
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hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
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rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
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bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
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bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
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bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
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bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
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bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
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bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
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bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
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bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
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hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
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bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
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bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW" "0,1"
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bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
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bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
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bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
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bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
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bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
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bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
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bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
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bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
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bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
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bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
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bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
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bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
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bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
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hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
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hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
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hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
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bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
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bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
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bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
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bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
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hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
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bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
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hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
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bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
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bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
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bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
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bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
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bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
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bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree "I2C_EMAC_2"
base ad:0x10C02C00
group.long 0x0++0xB
line.long 0x0 "IC_CON,Name: I2C Control Register"
hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,Reserved bits - Read Only"
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rbitfld.long 0x0 19. "RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 18. "RSVD_SMBUS_ARP_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_QUICK_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,Reserved bits - Read Only"
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rbitfld.long 0x0 11. "RSVD_BUS_CLEAR_FEATURE_CTRL,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode:" "0: issues the STOP_DET irrespective of whether..,1: issues the STOP_DET interrupt only when master.."
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rbitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether" "0,1"
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bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation" "0,1"
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bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode:" "0: issues the STOP_DET irrespective of whether it's..,1: issues the STOP_DET interrrupt only when it is.."
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bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled " "0: slave is enabled,1: slave is disabled"
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bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when" "0: disable,1: enable"
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rbitfld.long 0x0 4. "IC_10BITADDR_MASTER_rd_only,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave  this bit controls whether the DW_apb_i2c" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its" "?,1: standard mode,2: fast mode,3: high speed mode"
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bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled." "0: master disabled,1: master enabled"
line.long 0x4 "IC_TAR,Name: I2C Target Address Register"
hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,Reserved bits - Read Only"
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rbitfld.long 0x4 16. "RSVD_SMBUS_QUICK_CMD,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,Reserved bits - Read Only" "0,1,2,3"
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rbitfld.long 0x4 13. "RSVD_DEVICE_ID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x4 12. "IC_10BITADDR_MASTER,This bit controls whether the DW_apb_i2c starts its transfers in 7-" "0: 7-bit addressing,1: 10-bit addressing"
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bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or" "0: ignore bit 10 GC_OR_START and use IC_TAR normally,1: perform special I2C command as specified in.."
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bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0  then this bit indicates whether a" "0: General Call Address after issuing a General Call,1: START BYTE"
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hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When"
line.long 0x8 "IC_SAR,Name: I2C Slave Address Register"
hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,Reserved bits - Read Only"
newline
hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit"
group.long 0x10++0x13
line.long 0x0 "IC_DATA_CMD,Name: I2C Rx/Tx Data Buffer and Command Register;"
hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,Reserved bits - Read Only"
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rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte" "0,1"
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bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received." "0,1"
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bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received." "0,1"
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bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed." "0: Write,1: Read"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus."
line.long 0x4 "IC_SS_SCL_HCNT,Name: Standard Speed I2C Clock SCL High Count Register"
hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x8 "IC_SS_SCL_LCNT,Name: Standard Speed I2C Clock SCL Low Count Register"
hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,Reserved bits - Read Only"
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hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0xC "IC_FS_SCL_HCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register"
hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,Reserved bits - Read Only"
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hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to"
line.long 0x10 "IC_FS_SCL_LCNT,Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register"
hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,Reserved bits - Read Only"
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hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0x2C++0x3
line.long 0x0 "IC_INTR_STAT,Name: I2C Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
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bitfld.long 0x0 14. "RSVD_R_SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods." "0,1"
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bitfld.long 0x0 13. "R_MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "R_RESTART_DET,Indicates a RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 11. "R_GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "R_START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "R_STOP_DET,The behavior of the STOP_DET interrupt status differs based on the" "0: Indicates whether a STOP condition has occurred..,1: In Master Mode"
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bitfld.long 0x0 8. "R_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
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bitfld.long 0x0 7. "R_RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
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bitfld.long 0x0 6. "R_TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "R_RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "R_TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the" "0: This bit is set to 1 when the transmit buffer is..,1: This bit is set to 1 when the transmit buffer is.."
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bitfld.long 0x0 3. "R_TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "R_RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "R_RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "R_RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x30++0x3
line.long 0x0 "IC_INTR_MASK,Name: I2C Interrupt Mask Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,Reserved bits - Read Only"
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rbitfld.long 0x0 14. "RSVD_M_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 13. "M_MASTER_ON_HOLD,This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register." "0,1"
newline
bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register." "0,1"
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bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register." "0,1"
rgroup.long 0x34++0x3
line.long 0x0 "IC_RAW_INTR_STAT,Name: I2C Raw Interrupt Status Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,Reserved bits - Read Only"
newline
bitfld.long 0x0 14. "RSVD_SCL_STUCK_AT_LOW,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty." "0,1"
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bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface" "0,1"
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bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It" "0,1"
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bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C" "0,1"
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bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition" "0,1"
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bitfld.long 0x0 8. "RAW_INTR_ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There" "0,1"
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bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter " "0,1"
newline
bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c  as an I2C transmitter " "0,1"
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bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C" "0,1"
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bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status" "0: This bit is set to 1 when the transmit buffer..,1: This bit is set to 1 when the transmit buffer.."
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bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH" "0,1"
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bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the" "0,1"
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bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and" "0,1"
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bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by" "0,1"
group.long 0x38++0x7
line.long 0x0 "IC_RX_TL,Name: I2C Receive FIFO Threshold Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level"
line.long 0x4 "IC_TX_TL,Name: I2C Transmit FIFO Threshold Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level"
rgroup.long 0x40++0x2B
line.long 0x0 "IC_CLR_INTR,Name: Clear Combined and Individual Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt " "0,1"
line.long 0x4 "IC_CLR_RX_UNDER,Name: Clear RX_UNDER Interrupt Register"
hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,Reserved bits - Read Only"
newline
bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER" "0,1"
line.long 0x8 "IC_CLR_RX_OVER,Name: Clear RX_OVER Interrupt Register"
hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER" "0,1"
line.long 0xC "IC_CLR_TX_OVER,Name: Clear TX_OVER Interrupt Register"
hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER" "0,1"
line.long 0x10 "IC_CLR_RD_REQ,Name: Clear RD_REQ Interrupt Register"
hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ" "0,1"
line.long 0x14 "IC_CLR_TX_ABRT,Name: Clear TX_ABRT Interrupt Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT" "0,1"
line.long 0x18 "IC_CLR_RX_DONE,Name: Clear RX_DONE Interrupt Register"
hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE" "0,1"
line.long 0x1C "IC_CLR_ACTIVITY,Name: Clear ACTIVITY Interrupt Register"
hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,Reserved bits - Read Only"
newline
bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY" "0,1"
line.long 0x20 "IC_CLR_STOP_DET,Name: Clear STOP_DET Interrupt Register"
hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,Reserved bits - Read Only"
newline
bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET" "0,1"
line.long 0x24 "IC_CLR_START_DET,Name: Clear START_DET Interrupt Register"
hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,Reserved bits - Read Only"
newline
bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET" "0,1"
line.long 0x28 "IC_CLR_GEN_CALL,Name: Clear GEN_CALL Interrupt Register"
hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,Reserved bits - Read Only"
newline
bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL" "0,1"
group.long 0x6C++0x3
line.long 0x0 "IC_ENABLE,Name: I2C Enable Register"
hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,Reserved bits - Read Only"
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rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,Reserved bits - Read Only" "0,1"
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rbitfld.long 0x0 16. "RSVD_SMBUS_CLK_RESET,Reserved bits - Read Only" "0,1"
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hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,Reserved bits - Read Only"
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rbitfld.long 0x0 3. "RSVD_SDA_STUCK_RECOVERY_ENABLE,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode" "0,1"
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bitfld.long 0x0 1. "ABORT,When set  the controller initiates the transfer abort." "0: ABORT not initiated or ABORT done,1: ABORT operation in progress"
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bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled." "0: Disables DW_apb_i2c,1: Enables DW_apb_i2c"
rgroup.long 0x70++0xB
line.long 0x0 "IC_STATUS,Name: I2C Status Register"
hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,Reserved bits - Read Only"
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bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 18. "RSVD_SMBUS_SLAVE_ADDR_RESOLVED,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 17. "RSVD_SMBUS_SLAVE_ADDR_VALID,Reserved bits - Read Only" "0,1"
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bitfld.long 0x0 16. "RSVD_SMBUS_QUICK_CMD_BIT,Reserved bits - Read Only" "0,1"
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hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,Reserved bits - Read Only"
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bitfld.long 0x0 11. "RSVD_SDA_STUCK_NOT_RECOVERED,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,Reserved bits - Read Only" "0,1"
newline
bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status." "0: Slave FSM is in IDLE state so the Slave part of,1: Slave FSM is not in IDLE state so the Slave part"
newline
bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status." "0: Master FSM is in IDLE state so the Master part,1: Master FSM is not in IDLE state so the Master"
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bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full." "0: Receive FIFO is not full,1: Receive FIFO is full"
newline
bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
newline
bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
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bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
newline
bitfld.long 0x0 0. "IC_STATUS_ACTIVITY,I2C Activity Status." "0,1"
line.long 0x4 "IC_TXFLR,Name: I2C Transmit FIFO Level Register"
hexmask.long 0x4 7.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--6. 1. "TXFLR,Transmit FIFO Level."
line.long 0x8 "IC_RXFLR,Name: I2C Receive FIFO Level Register"
hexmask.long 0x8 7.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--6. 1. "RXFLR,Receive FIFO Level."
group.long 0x7C++0x3
line.long 0x0 "IC_SDA_HOLD,Name: I2C SDA Hold Time Length Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,Reserved bits - Read Only"
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hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time"
newline
hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time"
rgroup.long 0x80++0x3
line.long 0x0 "IC_TX_ABRT_SOURCE,Name: I2C Transmit Abort Source Register"
hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the"
newline
bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,Reserved bits - Read Only" "0,1,2,3"
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bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,Reserved bits - Read Only" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 17. "RSVD_ABRT_SDA_STUCK_AT_LOW" "0,1"
newline
bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has" "0,1"
newline
bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to" "?,1: When the processor side responds to"
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bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,1: Slave lost the bus while transmitting" "?,1: Slave lost the bus while transmitting"
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bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,1: Slave has received a read command" "?,1: Slave has received a read command"
newline
bitfld.long 0x0 12. "ARB_LOST,1: Master has lost arbitration  or if" "?,1: Master has lost arbitration"
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bitfld.long 0x0 11. "ABRT_MASTER_DIS,1: User tries to initiate a Master" "?,1: User tries to initiate a Master"
newline
bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9  the source of the" "?,1: The restart is disabled"
newline
bitfld.long 0x0 8. "ABRT_HS_NORSTRT,1: The restart is disabled" "?,1: The restart is disabled"
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bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,1: Master has sent a START Byte and" "?,1: Master has sent a START Byte and"
newline
bitfld.long 0x0 6. "ABRT_HS_ACKDET,1: Master is in High Speed mode and" "?,1: Master is in High Speed mode and"
newline
bitfld.long 0x0 5. "ABRT_GCALL_READ,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
newline
bitfld.long 0x0 4. "ABRT_GCALL_NOACK,1: DW_apb_i2c in master mode sent a" "?,1: DW_apb_i2c in master mode sent a"
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bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,1: This is a master-mode only bit." "?,1: This is a master-mode only bit"
newline
bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
newline
bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,1: Master is in 10-bit address mode and" "?,1: Master is in 10-bit address mode and"
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bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,1: Master is in 7-bit addressing mode" "?,1: Master is in 7-bit addressing mode"
group.long 0x84++0x17
line.long 0x0 "IC_SLV_DATA_NACK_ONLY,Name: Generate Slave Data NACK Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_SLV_DATA_NACK_ONLY,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "NACK,Generate NACK." "0: generate NACK/ACK normally,1: generate NACK after data byte received"
line.long 0x4 "IC_DMA_CR,Name: DMA Control Register"
hexmask.long 0x4 2.--31. 1. "RSVD_IC_DMA_CR_2_31,Reserved bits [31:1] - Read Only"
newline
bitfld.long 0x4 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x4 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x8 "IC_DMA_TDLR,Name: DMA Transmit Data Level Register"
hexmask.long 0x8 6.--31. 1. "RSVD_DMA_TDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--5. 1. "DMATDL,Transmit Data Level."
line.long 0xC "IC_DMA_RDLR,Name: I2C Receive Data Level Register"
hexmask.long 0xC 6.--31. 1. "RSVD_DMA_RDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0xC 0.--5. 1. "DMARDL,Receive Data Level."
line.long 0x10 "IC_SDA_SETUP,Name: I2C SDA Setup Register"
hexmask.long.tbyte 0x10 8.--31. 1. "RSVD_IC_SDA_SETUP,Reserved bits - Read Only"
newline
hexmask.long.byte 0x10 0.--7. 1. "SDA_SETUP,SDA Setup."
line.long 0x14 "IC_ACK_GENERAL_CALL,Name: I2C ACK General Call Register"
hexmask.long 0x14 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,Reserved bits [31:1] - Read Only"
newline
bitfld.long 0x14 0. "ACK_GEN_CALL,ACK General Call." "0,1"
rgroup.long 0x9C++0x3
line.long 0x0 "IC_ENABLE_STATUS,Name: I2C Enable Status Register"
hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,Reserved bits - Read Only"
newline
bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost." "0,1"
newline
bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit  Receive)." "0,1"
newline
bitfld.long 0x0 0. "IC_EN,ic_en Status." "0,1"
group.long 0xA0++0x3
line.long 0x0 "IC_FS_SPKLEN,Name: I2C SS. FS or FM+ spike suppression limit"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to"
rgroup.long 0xA8++0x3
line.long 0x0 "IC_CLR_RESTART_DET,Name: Clear RESTART_DET Interrupt Register"
hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "IC_COMP_PARAM_1,Name: Component Parameter Register 1"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived"
newline
hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is"
newline
bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived" "0: False,1: True"
newline
bitfld.long 0x0 6. "HAS_DMA,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 5. "INTR_IO,The value of this register is" "0: Individual,1: Combined"
newline
bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is" "0: False,1: True"
newline
bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is" "0: Reserved,1: Standard,2: Fast,3: High"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is" "0: 8 bits,1: 16 bits,2: 32 bits,3: Reserved"
line.long 0x4 "IC_COMP_VERSION,Name: I2C Component Version Register"
hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are"
line.long 0x8 "IC_COMP_TYPE,Name: I2C Component Type Register"
hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number"
tree.end
tree.end
tree "I3C (I3C Controller)"
base ad:0x0
tree "I3C_MAIN_MASTER"
base ad:0x10DA0000
group.long 0x0++0x7
line.long 0x0 "DEVICE_CTRL,DWC_mipi_i3c control Register"
bitfld.long 0x0 31. "ENABLE,Controls whether or not DWC_mipi_i3c is enabled." "0: Disables the DWC_mipi_i3c controller,1: Enables the DWC_mipi_i3c controller"
newline
bitfld.long 0x0 30. "RESUME,DWC_mipi_i3c Resume" "0,1"
newline
bitfld.long 0x0 29. "ABORT,DWC_mipi_i3c Abort" "0,1"
newline
bitfld.long 0x0 28. "DMA_ENABLE,DMA Handshake Interface Enable" "0: The DMA handshake control has no significance,1: Enables the DMA handshake control to interact.."
newline
hexmask.long.tbyte 0x0 9.--27. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8. "HOT_JOIN_CTRL,Hot-Join ACK/NACK Control" "0: ACK the Hot-join request,1: NACK and send broadcast CCC to disable Hot-Join"
newline
bitfld.long 0x0 7. "I2C_SLAVE_PRESENT,I2C Slave Present" "0,1"
newline
hexmask.long.byte 0x0 1.--6. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "IBA_INCLUDE,I3C Broadcast Address include" "0,1"
line.long 0x4 "DEVICE_ADDR,In the master mode of operation this Register is used to program the Device Dynamic Addresses and its respective valid bit."
bitfld.long 0x4 31. "DYNAMIC_ADDR_VALID,Dynamic Address Valid" "0,1"
newline
hexmask.long.byte 0x4 23.--30. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 16.--22. 1. "DYNAMIC_ADDR,Device Dynamic Address."
newline
hexmask.long.word 0x4 0.--15. 1. "Reserved_0,Reserved bitfield added by Magillem"
rgroup.long 0x8++0x3
line.long 0x0 "HW_CAPABILITY,Hardware Capability register"
hexmask.long.word 0x0 20.--31. 1. "Reserved_8,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 19. "SLV_IBI_CAP,Reflects the IC_SLV_IBI Configurable Parameter." "0,1"
newline
bitfld.long 0x0 18. "SLV_HJ_CAP,Reflects the IC_SLV_HJ Configurable Parameter." "0,1"
newline
bitfld.long 0x0 17. "DMA_EN,Reflects the IC_HAS_DMA Configurable Parameter." "0,1"
newline
hexmask.long.byte 0x0 11.--16. 1. "HDR_TX_CLOCK_PERIOD,Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter."
newline
hexmask.long.byte 0x0 5.--10. 1. "CLOCK_PERIOD,Reflects the IC_CLK_PERIOD Configurable Parameter"
newline
bitfld.long 0x0 4. "HDR_TS_EN,Reflects the IC_SPEED_HDR_TS Configurable Parameter." "0: HDR-TS not supported,1: HDR-TS supported"
newline
bitfld.long 0x0 3. "HDR_DDR_EN,Reflects the IC_SPEED_HDR_DDR Configurable Parameter." "0: HDR-DDR not supported,1: HDR-DDR supported"
newline
bitfld.long 0x0 0.--2. "DEVICE_ROLE_CONFIG,Reflects the IC_DEVICE_ROLE Configurable Parameter." "?,1: Master Only,2: Programmable Master-Slave,3: Secondary Master,4: Slave Only,?,?,?"
wgroup.long 0xC++0x3
line.long 0x0 "COMMAND_QUEUE_PORT,COMMAND_QUEUE_PORT."
hexmask.long 0x0 0.--31. 1. "COMMAND,32 bit command"
rgroup.long 0x10++0x3
line.long 0x0 "RESPONSE_QUEUE_PORT,In Master mode of operation:"
hexmask.long 0x0 0.--31. 1. "RESPONSE,32 bit Response"
wgroup.long 0x14++0x3
line.long 0x0 "TX_DATA_PORT,Transmit Data Port Register"
hexmask.long 0x0 0.--31. 1. "TX_DATA_PORT,Transmit Data Port"
rgroup.long 0x14++0x7
line.long 0x0 "RX_DATA_PORT,Receive Data Port Register"
hexmask.long 0x0 0.--31. 1. "RX_DATA_PORT,Receive Data Port."
line.long 0x4 "IBI_QUEUE_STATUS,In-Band Interrupt Queue Status Register"
hexmask.long.byte 0x4 28.--31. 1. "IBI_STS,IBI Received Status."
newline
hexmask.long.word 0x4 16.--27. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 8.--15. 1. "IBI_ID,IBI Identifier."
newline
hexmask.long.byte 0x4 0.--7. 1. "DATA_LENGTH,In-Band Interrupt data length."
rgroup.long 0x18++0x3
line.long 0x0 "IBI_QUEUE_DATA,In-Band Interrupt Queue Data Register"
hexmask.long 0x0 0.--31. 1. "IBI_DATA,In-Band Interrupt Data"
group.long 0x1C++0xB
line.long 0x0 "QUEUE_THLD_CTRL,Queue Threshold Control Register"
hexmask.long.byte 0x0 24.--31. 1. "IBI_STATUS_THLD,In-Band Interrupt Status Threshold Value."
newline
hexmask.long.byte 0x0 16.--23. 1. "IBI_DATA_THLD,IBI Data Threshold Value"
newline
hexmask.long.byte 0x0 8.--15. 1. "RESP_BUF_THLD,Response Buffer Threshold Value."
newline
hexmask.long.byte 0x0 0.--7. 1. "CMD_EMPTY_BUF_THLD,Command Buffer Empty Threshold Value."
line.long 0x4 "DATA_BUFFER_THLD_CTRL,Data Buffer Threshold Control Register"
hexmask.long.byte 0x4 27.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 24.--26. "RX_START_THLD,Receive Start Threshold Value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 19.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 16.--18. "TX_START_THLD,Transfer Start Threshold Value" "0: 1,1: 4,?,?,?,?,?,?"
newline
hexmask.long.byte 0x4 11.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 8.--10. "RX_BUF_THLD,Receive Buffer Threshold Value" "0: 1,1: 4,?,?,?,?,?,?"
newline
hexmask.long.byte 0x4 3.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--2. "TX_EMPTY_BUF_THLD,Transmit Buffer Threshold Value" "0: 1,1: 4,?,?,?,?,?,?"
line.long 0x8 "IBI_QUEUE_CTRL,This Register is used to control whether or not to intimate the application if an IBI request is rejected (Nacked)."
hexmask.long 0x8 4.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 3. "NOTIFY_SIR_REJECTED,Notify Rejected Slave Interrupt Request Control." "0: Suppress passing the IBI Status to the IBI FIFO,1: Writes IBI Status to the IBI FIFO"
newline
rbitfld.long 0x8 1.--2. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x8 0. "NOTIFY_HJ_REJECTED,Notify Rejected Hot-Join Control." "0: Suppress passing the IBI Status to the IBI FIFO,1: Writes IBI Status to the IBI FIFO"
group.long 0x34++0x13
line.long 0x0 "RESET_CTRL,This Register is used for general software reset and for individual buffer reset."
hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 5. "IBI_QUEUE_RST,IBI Queue Software Reset." "0,1"
newline
bitfld.long 0x0 4. "RX_FIFO_RST,Receive Buffer Software Reset." "0,1"
newline
bitfld.long 0x0 3. "TX_FIFO_RST,Transmit Buffer Software Reset" "0,1"
newline
bitfld.long 0x0 2. "RESP_QUEUE_RST,Response Queue Software Reset" "0,1"
newline
bitfld.long 0x0 1. "CMD_QUEUE_RST,Command Queue Software Reset" "0,1"
newline
bitfld.long 0x0 0. "SOFT_RST,Core Software Reset." "0,1"
line.long 0x4 "SLV_EVENT_STATUS,This register indicates the status/values of some events/controls that are relavant to slave mode of operation. These values are set by Master initiated CCCs."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
eventfld.long 0x4 7. "MWL_UPDATED,MWL Updated Status." "0,1"
newline
eventfld.long 0x4 6. "MRL_UPDATED,MRL Updated Status." "0,1"
newline
rbitfld.long 0x4 4.--5. "ACTIVITY_STATE,Activity State Status." "0,1,2,3"
newline
hexmask.long.byte 0x4 0.--3. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x8 "INTR_STATUS,Interrupt Status Register"
hexmask.long.tbyte 0x8 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
eventfld.long 0x8 9. "TRANSFER_ERR_STS,Transfer Error Status." "0,1"
newline
rbitfld.long 0x8 6.--8. "Reserved_6,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 5. "TRANSFER_ABORT_STS,Transfer Abort Status." "0,1"
newline
rbitfld.long 0x8 4. "RESP_READY_STS,Response Queue Ready Status." "0,1"
newline
rbitfld.long 0x8 3. "CMD_QUEUE_READY_STS,Command Queue Ready." "0,1"
newline
rbitfld.long 0x8 2. "IBI_THLD_STS,IBI Buffer Threshold Status." "0,1"
newline
rbitfld.long 0x8 1. "RX_THLD_STS,Receive Buffer Threshold Status." "0,1"
newline
rbitfld.long 0x8 0. "TX_THLD_STS,Transmit Buffer Threshold Status" "0,1"
line.long 0xC "INTR_STATUS_EN,Interrupt Status Enable Register."
hexmask.long.tbyte 0xC 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 9. "TRANSFER_ERR_STS_EN,Transfer Error Status Enable" "0,1"
newline
rbitfld.long 0xC 6.--8. "Reserved_6,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 5. "TRANSFER_ABORT_STS_EN,Transfer Abort Status Enable." "0,1"
newline
bitfld.long 0xC 4. "RESP_READY_STS_EN,Response Queue Ready Status Enable" "0,1"
newline
bitfld.long 0xC 3. "CMD_QUEUE_READY_STS_EN,Command Queue Ready Status Enable" "0,1"
newline
bitfld.long 0xC 2. "IBI_THLD_STS_EN,IBI Buffer Threshold Status Enable." "0,1"
newline
bitfld.long 0xC 1. "RX_THLD_STS_EN,Receive Buffer Threshold Status Enable" "0,1"
newline
bitfld.long 0xC 0. "TX_THLD_STS_EN,Transmit Buffer Threshold Status Enable." "0,1"
line.long 0x10 "INTR_SIGNAL_EN,Interrupt Signal Enable Register"
hexmask.long.tbyte 0x10 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 9. "TRANSFER_ERR_SIGNAL_EN,Transfer Error Signal Enable" "0,1"
newline
rbitfld.long 0x10 6.--8. "Reserved_6,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 5. "TRANSFER_ABORT_SIGNAL_EN,Transfer Abort Signal Enable" "0,1"
newline
bitfld.long 0x10 4. "RESP_READY_SIGNAL_EN,Response Queue Ready Signal Enable" "0,1"
newline
bitfld.long 0x10 3. "CMD_QUEUE_READY_SIGNAL_EN,Command Queue Ready Signal Enable" "0,1"
newline
bitfld.long 0x10 2. "IBI_THLD_SIGNAL_EN,IBI Buffer Threshold Signal Enable" "0,1"
newline
bitfld.long 0x10 1. "RX_THLD_SIGNAL_EN,Receive Buffer Threshold Signal Enable" "0,1"
newline
bitfld.long 0x10 0. "TX_THLD_SIGNAL_EN,Transmit Buffer Threshold Signal Enable" "0,1"
wgroup.long 0x48++0x3
line.long 0x0 "INTR_FORCE,Interrupt Force Enable Register"
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 9. "TRANSFER_ERR_FORCE_EN,Transfer Error Force Enable" "0,1"
newline
bitfld.long 0x0 6.--8. "Reserved_6,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 5. "TRANSFER_ABORT_FORCE_EN,Transfer Abort Force Enable" "0,1"
newline
bitfld.long 0x0 4. "RESP_READY_FORCE_EN,Response Queue Ready Force Enable" "0,1"
newline
bitfld.long 0x0 3. "CMD_QUEUE_READY_FORCE_EN,Command Queue Ready Force Enable" "0,1"
newline
bitfld.long 0x0 2. "IBI_THLD_FORCE_EN,IBI Buffer Threshold Force Enable" "0,1"
newline
bitfld.long 0x0 1. "RX_THLD_FORCE_EN,Receive Buffer Threshold Force Enable" "0,1"
newline
bitfld.long 0x0 0. "TX_THLD_FORCE_EN,Transmit Buffer Threshold Force Enable" "0,1"
rgroup.long 0x4C++0xB
line.long 0x0 "QUEUE_STATUS_LEVEL,Queue Status Level Register."
bitfld.long 0x0 29.--31. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 24.--28. 1. "IBI_STS_CNT,IBI Buffer Status Count."
newline
hexmask.long.byte 0x0 16.--23. 1. "IBI_BUF_BLR,IBI Buffer Level Value."
newline
hexmask.long.byte 0x0 8.--15. 1. "RESP_BUF_BLR,Response Buffer Level Value."
newline
hexmask.long.byte 0x0 0.--7. 1. "CMD_QUEUE_EMPTY_LOC,Command Queue Empty Locations."
line.long 0x4 "DATA_BUFFER_STATUS_LEVEL,Data Buffer Status Level Register."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 16.--23. 1. "RX_BUF_BLR,Receive Buffer Level Value."
newline
hexmask.long.byte 0x4 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "TX_BUF_EMPTY_LOC,Transmit Buffer Empty Level Value."
line.long 0x8 "PRESENT_STATE,The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register. This register is relevant in both master and slave mode of operation and is meant to be used to get debug information related to the controllers.."
bitfld.long 0x8 29.--31. "Reserved_7,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 28. "MASTER_IDLE,This field reflects whether the Master Controller is in Idle state or not. This bit is set when all the Queues(Command   Response  IBI) and Buffers(Transmit and Receive) are empty along with the Master State machine is in Idle state." "0,1"
newline
hexmask.long.byte 0x8 24.--27. 1. "CMD_TID,This field reflects the Transaction-ID of the current executing command."
newline
bitfld.long 0x8 22.--23. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.byte 0x8 16.--21. 1. "CM_TFR_ST_STS,Current Master Transfer State Status."
newline
bitfld.long 0x8 14.--15. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.byte 0x8 8.--13. 1. "CM_TFR_STS,Transfer Type Status"
newline
hexmask.long.byte 0x8 3.--7. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 2. "CURRENT_MASTER,This Bit is used to check whether the Master is Current Master or not. The Current Master is the Master" "0: Master is not Current Master,1: Master is Current Master"
newline
bitfld.long 0x8 1. "SDA_LINE_SIGNAL_LEVEL,This bit is used to check the SDA line level to recover from errors and for debugging. This bit" "0,1"
newline
bitfld.long 0x8 0. "SCL_LINE_SIGNAL_LEVEL,This bit is used to check the SCL line level to recover from errors and for debugging. This bit" "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "DEVICE_ADDR_TABLE_POINTER,Pointer for Device Address Table"
hexmask.long.word 0x0 16.--31. 1. "DEV_ADDR_TABLE_DEPTH,Depth of Device Address Table"
newline
hexmask.long.word 0x0 0.--15. 1. "P_DEV_ADDR_TABLE_START_ADDR,Start Address of Device Address Table."
group.long 0x60++0x3
line.long 0x0 "DEV_CHAR_TABLE_POINTER,Pointer for Device Characteristics Table"
hexmask.long.word 0x0 22.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 19.--21. "PRESENT_DEV_CHAR_TABLE_INDX,Current index of Device Characteristics Table." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 12.--18. 1. "DEV_CHAR_TABLE_DEPTH,Depth of Device Characteristics Table"
newline
hexmask.long.word 0x0 0.--11. 1. "P_DEV_CHAR_TABLE_START_ADDR,Start Address of Device Characteristics Table."
rgroup.long 0x6C++0x3
line.long 0x0 "VENDOR_SPECIFIC_REG_POINTER,Pointer for Vendor Specific Registers."
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "P_VENDOR_REG_START_ADDR,Start Address of Vendor specific registers."
group.long 0xB0++0x13
line.long 0x0 "DEVICE_CTRL_EXTENDED,Device Control Extended register."
hexmask.long 0x0 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--1. "DEV_OPERATION_MODE,This bit is used to select the Device Operation Mode before the controller is enabled." "0: Master,1: Slave,2: Reserved,3: Reserved"
line.long 0x4 "SCL_I3C_OD_TIMING,SCL I3C Open Drain Timing Register"
hexmask.long.byte 0x4 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 16.--23. 1. "I3C_OD_HCNT,I3C Open Drain High Count."
newline
hexmask.long.byte 0x4 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "I3C_OD_LCNT,I3C Open Drain Low Count."
line.long 0x8 "SCL_I3C_PP_TIMING,SCL I3C Push Pull Timing Register"
hexmask.long.byte 0x8 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 16.--23. 1. "I3C_PP_HCNT,I3C Push Pull High Count."
newline
hexmask.long.byte 0x8 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 0.--7. 1. "I3C_PP_LCNT,I3C Push Pull Low Count."
line.long 0xC "SCL_I2C_FM_TIMING,SCL I2C Fast Mode Timing Register"
hexmask.long.word 0xC 16.--31. 1. "I2C_FM_HCNT,I2C Fast Mode High Count"
newline
hexmask.long.word 0xC 0.--15. 1. "I2C_FM_LCNT,I2C Fast Mode Low Count"
line.long 0x10 "SCL_I2C_FMP_TIMING,SCL I2C Fast Mode Plus Timing Register"
hexmask.long.byte 0x10 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 16.--23. 1. "I2C_FMP_HCNT,I2C Fast Mode Plus High Count"
newline
hexmask.long.word 0x10 0.--15. 1. "I2C_FMP_LCNT,I2C Fast Mode Plus Low Count"
group.long 0xC8++0xF
line.long 0x0 "SCL_EXT_LCNT_TIMING,SCL Extended Low Count Timing Register."
hexmask.long.byte 0x0 24.--31. 1. "I3C_EXT_LCNT_4,I3C Extended Low Count Register 4"
newline
hexmask.long.byte 0x0 16.--23. 1. "I3C_EXT_LCNT_3,I3C Extended Low Count Register 3"
newline
hexmask.long.byte 0x0 8.--15. 1. "I3C_EXT_LCNT_2,I3C Extended Low Count Register 2"
newline
hexmask.long.byte 0x0 0.--7. 1. "I3C_EXT_LCNT_1,I3C Extended Low Count Register 1"
line.long 0x4 "SCL_EXT_TERMN_LCNT_TIMING,SCL Termination Bit Low Count Timing Register"
hexmask.long 0x4 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--3. 1. "I3C_EXT_TERMN_LCNT,I3C Read Termination Bit Low count."
line.long 0x8 "SDA_HOLD_SWITCH_DLY_TIMING,SDA Hold and Mode Switch Delay Timing Register"
hexmask.long.word 0x8 19.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 16.--18. "SDA_TX_HOLD,This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x8 0.--15. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0xC "BUS_FREE_AVAIL_TIMING,Bus Free and Available Timing Register"
hexmask.long.word 0xC 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0xC 0.--15. 1. "BUS_FREE_TIME,This register field is used only in Master mode of operation"
rgroup.long 0xE0++0xB
line.long 0x0 "I3C_VER_ID,This register reflects the current release number of DWC_mipi_i3c"
hexmask.long 0x0 0.--31. 1. "I3C_VER_ID,Current release number"
line.long 0x4 "I3C_VER_TYPE,This register reflects the current release type of DWC_mipi_i3c."
hexmask.long 0x4 0.--31. 1. "I3C_VER_TYPE,Current release type"
line.long 0x8 "QUEUE_SIZE_CAPABILITY,This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_i3c."
hexmask.long.word 0x8 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 16.--19. 1. "IBI_BUF_SIZE,IBI Queue Size"
newline
hexmask.long.byte 0x8 12.--15. 1. "RESP_BUF_SIZE,Response Queue Size"
newline
hexmask.long.byte 0x8 8.--11. 1. "CMD_BUF_SIZE,Command Queue Size"
newline
hexmask.long.byte 0x8 4.--7. 1. "RX_BUF_SIZE,Receive Data Buffer Size"
newline
hexmask.long.byte 0x8 0.--3. 1. "TX_BUF_SIZE,Transmit Data Buffer Size"
rgroup.long 0x200++0x7F
line.long 0x0 "DEV_CHAR_TABLE1_LOC1,Device Characteristic Table Location-1 of Device1"
hexmask.long 0x0 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
line.long 0x4 "DEV_CHAR_TABLE1_LOC2,Device Characteristic Table Location-2 of Device1"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
line.long 0x8 "DEV_CHAR_TABLE1_LOC3,Device Characteristic Table Location-3 of Device1"
hexmask.long.word 0x8 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x8 0.--7. 1. "DCR,Device Characteristic Value"
line.long 0xC "DEV_CHAR_TABLE1_LOC4,Device Characteristic Table Location-4 of Device1"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
line.long 0x10 "DEV_CHAR_TABLE2_LOC1,Device Characteristic Table Location-1 of Device2"
hexmask.long 0x10 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
line.long 0x14 "DEV_CHAR_TABLE2_LOC2,Device Characteristic Table Location-2 of Device2"
hexmask.long.word 0x14 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x14 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
line.long 0x18 "DEV_CHAR_TABLE2_LOC3,Device Characteristic Table Location-3 of Device2"
hexmask.long.word 0x18 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x18 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x18 0.--7. 1. "DCR,Device Characteristic Value"
line.long 0x1C "DEV_CHAR_TABLE2_LOC4,Device Characteristic Table Location-4 of Device2"
hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x1C 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
line.long 0x20 "DEV_CHAR_TABLE3_LOC1,Device Characteristic Table Location-1 of Device3"
hexmask.long 0x20 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
line.long 0x24 "DEV_CHAR_TABLE3_LOC2,Device Characteristic Table Location-2 of Device3"
hexmask.long.word 0x24 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x24 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
line.long 0x28 "DEV_CHAR_TABLE3_LOC3,Device Characteristic Table Location-3 of Device3"
hexmask.long.word 0x28 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x28 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x28 0.--7. 1. "DCR,Device Characteristic Value"
line.long 0x2C "DEV_CHAR_TABLE3_LOC4,Device Characteristic Table Location-4 of Device3"
hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x2C 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
line.long 0x30 "DEV_CHAR_TABLE4_LOC1,Device Characteristic Table Location-1 of Device4"
hexmask.long 0x30 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
line.long 0x34 "DEV_CHAR_TABLE4_LOC2,Device Characteristic Table Location-2 of Device4"
hexmask.long.word 0x34 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x34 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
line.long 0x38 "DEV_CHAR_TABLE4_LOC3,Device Characteristic Table Location-3 of Device4"
hexmask.long.word 0x38 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x38 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x38 0.--7. 1. "DCR,Device Characteristic Value"
line.long 0x3C "DEV_CHAR_TABLE4_LOC4,Device Characteristic Table Location-4 of Device4"
hexmask.long.tbyte 0x3C 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x3C 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
line.long 0x40 "DEV_CHAR_TABLE5_LOC1,Device Characteristic Table Location-1 of Device5"
hexmask.long 0x40 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
line.long 0x44 "DEV_CHAR_TABLE5_LOC2,Device Characteristic Table Location-2 of Device5"
hexmask.long.word 0x44 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x44 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
line.long 0x48 "DEV_CHAR_TABLE5_LOC3,Device Characteristic Table Location-3 of Device5"
hexmask.long.word 0x48 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x48 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x48 0.--7. 1. "DCR,Device Characteristic Value"
line.long 0x4C "DEV_CHAR_TABLE5_LOC4,Device Characteristic Table Location-4 of Device5"
hexmask.long.tbyte 0x4C 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4C 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
line.long 0x50 "DEV_CHAR_TABLE6_LOC1,Device Characteristic Table Location-1 of Device6"
hexmask.long 0x50 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
line.long 0x54 "DEV_CHAR_TABLE6_LOC2,Device Characteristic Table Location-2 of Device6"
hexmask.long.word 0x54 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x54 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
line.long 0x58 "DEV_CHAR_TABLE6_LOC3,Device Characteristic Table Location-3 of Device6"
hexmask.long.word 0x58 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x58 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x58 0.--7. 1. "DCR,Device Characteristic Value"
line.long 0x5C "DEV_CHAR_TABLE6_LOC4,Device Characteristic Table Location-4 of Device6"
hexmask.long.tbyte 0x5C 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x5C 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
line.long 0x60 "DEV_CHAR_TABLE7_LOC1,Device Characteristic Table Location-1 of Device7"
hexmask.long 0x60 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
line.long 0x64 "DEV_CHAR_TABLE7_LOC2,Device Characteristic Table Location-2 of Device7"
hexmask.long.word 0x64 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x64 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
line.long 0x68 "DEV_CHAR_TABLE7_LOC3,Device Characteristic Table Location-3 of Device7"
hexmask.long.word 0x68 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x68 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x68 0.--7. 1. "DCR,Device Characteristic Value"
line.long 0x6C "DEV_CHAR_TABLE7_LOC4,Device Characteristic Table Location-4 of Device7"
hexmask.long.tbyte 0x6C 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x6C 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
line.long 0x70 "DEV_CHAR_TABLE8_LOC1,Device Characteristic Table Location-1 of Device8"
hexmask.long 0x70 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
line.long 0x74 "DEV_CHAR_TABLE8_LOC2,Device Characteristic Table Location-2 of Device8"
hexmask.long.word 0x74 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x74 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
line.long 0x78 "DEV_CHAR_TABLE8_LOC3,Device Characteristic Table Location-3 of Device8"
hexmask.long.word 0x78 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x78 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x78 0.--7. 1. "DCR,Device Characteristic Value"
line.long 0x7C "DEV_CHAR_TABLE8_LOC4,Device Characteristic Table Location-4 of Device8"
hexmask.long.tbyte 0x7C 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x7C 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
group.long 0x280++0x2B
line.long 0x0 "DEV_ADDR_TABLE1_LOC1,Device Address Table Location of Device1"
bitfld.long 0x0 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0x0 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0x0 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0x0 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0x0 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0x0 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0x0 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
line.long 0x4 "DEV_ADDR_TABLE2_LOC1,Device Address Table Location 2"
bitfld.long 0x4 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0x4 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x4 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0x4 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x4 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0x4 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0x4 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0x4 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0x4 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
line.long 0x8 "DEV_ADDR_TABLE3_LOC1,Device Address Table Location 3"
bitfld.long 0x8 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0x8 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x8 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0x8 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x8 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0x8 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0x8 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0x8 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0x8 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
line.long 0xC "DEV_ADDR_TABLE4_LOC1,Device Address Table Location 4"
bitfld.long 0xC 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0xC 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0xC 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0xC 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xC 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0xC 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0xC 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0xC 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0xC 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
line.long 0x10 "DEV_ADDR_TABLE5_LOC1,Device Address Table Location 5"
bitfld.long 0x10 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0x10 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x10 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0x10 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x10 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0x10 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0x10 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0x10 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0x10 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
line.long 0x14 "DEV_ADDR_TABLE6_LOC1,Device Address Table Location 6"
bitfld.long 0x14 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0x14 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x14 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x14 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0x14 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x14 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0x14 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0x14 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0x14 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0x14 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x14 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
line.long 0x18 "DEV_ADDR_TABLE7_LOC1,Device Address Table Location 7"
bitfld.long 0x18 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0x18 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x18 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x18 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0x18 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x18 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0x18 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0x18 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0x18 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0x18 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x18 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
line.long 0x1C "DEV_ADDR_TABLE8_LOC1,Device Address Table Location 8"
bitfld.long 0x1C 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0x1C 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x1C 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x1C 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0x1C 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x1C 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0x1C 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0x1C 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0x1C 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0x1C 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x1C 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
line.long 0x20 "DEV_ADDR_TABLE9_LOC1,Device Address Table Location 9"
bitfld.long 0x20 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0x20 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x20 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x20 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0x20 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x20 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0x20 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0x20 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0x20 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0x20 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x20 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
line.long 0x24 "DEV_ADDR_TABLE10_LOC1,Device Address Table Location 10"
bitfld.long 0x24 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0x24 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x24 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0x24 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x24 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0x24 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0x24 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0x24 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0x24 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
line.long 0x28 "DEV_ADDR_TABLE11_LOC1,Device Address Table Location 11"
bitfld.long 0x28 31. "DEVICE,Type of device" "0: I3C,1: I2C"
newline
bitfld.long 0x28 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x28 24.--28. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x28 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
rbitfld.long 0x28 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x28 14. "MR_REJECT,In-Band Master Request Reject field is used to control  per device  whether to accept Master request" "0,1"
newline
bitfld.long 0x28 13. "SIR_REJECT,In-Band Slave Interrupt Request Reject field is used to control  per device  whether to accept Slave Interrupt" "0,1"
newline
bitfld.long 0x28 12. "IBI_WITH_DATA,Mandatory one or more data bytes follow the accepted IBI from the device. Data byte continuation is indicated by T-Bit." "0,1"
newline
bitfld.long 0x28 11. "IBI_PEC_EN,Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device." "0,1"
newline
hexmask.long.byte 0x28 7.--10. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x28 0.--6. 1. "STATIC_ADDRESS,Device Static Address."
tree.end
tree "I3C_SECONDARY_MASTER"
base ad:0x10DA1000
group.long 0x0++0x7
line.long 0x0 "DEVICE_CTRL,DWC_mipi_i3c control Register"
bitfld.long 0x0 31. "ENABLE,Controls whether or not DWC_mipi_i3c is enabled." "0: Disables the DWC_mipi_i3c controller,1: Enables the DWC_mipi_i3c controller"
newline
bitfld.long 0x0 30. "RESUME,DWC_mipi_i3c Resume" "0,1"
newline
bitfld.long 0x0 29. "ABORT,DWC_mipi_i3c Abort" "0,1"
newline
bitfld.long 0x0 28. "DMA_ENABLE,DMA Handshake Interface Enable" "0: The DMA handshake control has no significance,1: Enables the DMA handshake control to interact.."
newline
bitfld.long 0x0 27. "ADAPTIVE_I2C_I3C,This field is used in Slave mode of operation." "0,1"
newline
rbitfld.long 0x0 26. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 24.--25. "IDLE_CNT_MULTPLIER,Idle Count Multiplier" "0,1,2,3"
newline
hexmask.long.word 0x0 9.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8. "HOT_JOIN_CTRL,Hot-Join ACK/NACK Control" "0: ACK the Hot-join request,1: NACK and send broadcast CCC to disable Hot-Join"
newline
bitfld.long 0x0 7. "I2C_SLAVE_PRESENT,I2C Slave Present" "0,1"
newline
hexmask.long.byte 0x0 1.--6. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "IBA_INCLUDE,I3C Broadcast Address include" "0,1"
line.long 0x4 "DEVICE_ADDR,In the master mode of operation this Register is used to program the Device Dynamic Addresses and its respective valid bit."
bitfld.long 0x4 31. "DYNAMIC_ADDR_VALID,Dynamic Address Valid" "0,1"
newline
hexmask.long.byte 0x4 23.--30. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 16.--22. 1. "DYNAMIC_ADDR,Device Dynamic Address."
newline
bitfld.long 0x4 15. "STATIC_ADDR_VALID,Static Address Valid." "0,1"
newline
hexmask.long.byte 0x4 7.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--6. 1. "STATIC_ADDR,Device Static Address."
rgroup.long 0x8++0x3
line.long 0x0 "HW_CAPABILITY,Hardware Capability register"
hexmask.long.word 0x0 20.--31. 1. "Reserved_8,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 19. "SLV_IBI_CAP,Reflects the IC_SLV_IBI Configurable Parameter." "0,1"
newline
bitfld.long 0x0 18. "SLV_HJ_CAP,Reflects the IC_SLV_HJ Configurable Parameter." "0,1"
newline
bitfld.long 0x0 17. "DMA_EN,Reflects the IC_HAS_DMA Configurable Parameter." "0,1"
newline
hexmask.long.byte 0x0 11.--16. 1. "HDR_TX_CLOCK_PERIOD,Reflects the IC_HDR_TX_CLK_PERIOD Configurable Parameter."
newline
hexmask.long.byte 0x0 5.--10. 1. "CLOCK_PERIOD,Reflects the IC_CLK_PERIOD Configurable Parameter"
newline
bitfld.long 0x0 4. "HDR_TS_EN,Reflects the IC_SPEED_HDR_TS Configurable Parameter." "0: HDR-TS not supported,1: HDR-TS supported"
newline
bitfld.long 0x0 3. "HDR_DDR_EN,Reflects the IC_SPEED_HDR_DDR Configurable Parameter." "0: HDR-DDR not supported,1: HDR-DDR supported"
newline
bitfld.long 0x0 0.--2. "DEVICE_ROLE_CONFIG,Reflects the IC_DEVICE_ROLE Configurable Parameter." "?,1: Master Only,2: Programmable Master-Slave,3: Secondary Master,4: Slave Only,?,?,?"
wgroup.long 0xC++0x3
line.long 0x0 "COMMAND_QUEUE_PORT,COMMAND_QUEUE_PORT."
hexmask.long 0x0 0.--31. 1. "COMMAND,32 bit command"
rgroup.long 0x10++0x3
line.long 0x0 "RESPONSE_QUEUE_PORT,In Master mode of operation:"
hexmask.long 0x0 0.--31. 1. "RESPONSE,32 bit Response"
wgroup.long 0x14++0x3
line.long 0x0 "TX_DATA_PORT,Transmit Data Port Register"
hexmask.long 0x0 0.--31. 1. "TX_DATA_PORT,Transmit Data Port"
rgroup.long 0x14++0x7
line.long 0x0 "RX_DATA_PORT,Receive Data Port Register"
hexmask.long 0x0 0.--31. 1. "RX_DATA_PORT,Receive Data Port."
line.long 0x4 "IBI_QUEUE_STATUS,In-Band Interrupt Queue Status Register"
hexmask.long.byte 0x4 28.--31. 1. "IBI_STS,IBI Received Status."
newline
hexmask.long.word 0x4 16.--27. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 8.--15. 1. "IBI_ID,IBI Identifier."
newline
hexmask.long.byte 0x4 0.--7. 1. "DATA_LENGTH,In-Band Interrupt data length."
rgroup.long 0x18++0x3
line.long 0x0 "IBI_QUEUE_DATA,In-Band Interrupt Queue Data Register"
hexmask.long 0x0 0.--31. 1. "IBI_DATA,In-Band Interrupt Data"
group.long 0x1C++0xB
line.long 0x0 "QUEUE_THLD_CTRL,Queue Threshold Control Register"
hexmask.long.byte 0x0 24.--31. 1. "IBI_STATUS_THLD,In-Band Interrupt Status Threshold Value."
newline
hexmask.long.byte 0x0 16.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 8.--15. 1. "RESP_BUF_THLD,Response Buffer Threshold Value."
newline
hexmask.long.byte 0x0 0.--7. 1. "CMD_EMPTY_BUF_THLD,Command Buffer Empty Threshold Value."
line.long 0x4 "DATA_BUFFER_THLD_CTRL,Data Buffer Threshold Control Register"
hexmask.long.byte 0x4 27.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 24.--26. "RX_START_THLD,Receive Start Threshold Value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 19.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 16.--18. "TX_START_THLD,Transfer Start Threshold Value" "0: 1,1: 4,?,?,?,?,?,?"
newline
hexmask.long.byte 0x4 11.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 8.--10. "RX_BUF_THLD,Receive Buffer Threshold Value" "0: 1,1: 4,?,?,?,?,?,?"
newline
hexmask.long.byte 0x4 3.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--2. "TX_EMPTY_BUF_THLD,Transmit Buffer Threshold Value" "0: 1,1: 4,?,?,?,?,?,?"
line.long 0x8 "IBI_QUEUE_CTRL,This Register is used to control whether or not to intimate the application if an IBI request is rejected (Nacked)."
hexmask.long 0x8 4.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 3. "NOTIFY_SIR_REJECTED,Notify Rejected Slave Interrupt Request Control." "0: Suppress passing the IBI Status to the IBI FIFO,1: Writes IBI Status to the IBI FIFO"
newline
rbitfld.long 0x8 2. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x8 1. "NOTIFY_MR_REJECTED,Notify Rejected Master Request Control." "0: Suppress passing the IBI Status to the IBI FIFO,1: Writes IBI Status to the IBI FIFO"
newline
bitfld.long 0x8 0. "NOTIFY_HJ_REJECTED,Notify Rejected Hot-Join Control." "0: Suppress passing the IBI Status to the IBI FIFO,1: Writes IBI Status to the IBI FIFO"
group.long 0x2C++0x1B
line.long 0x0 "IBI_MR_REQ_REJECT,IBI Master Request Rejection Control Register."
hexmask.long 0x0 0.--31. 1. "MR_REQ_REJECT,In-band Master Request Reject."
line.long 0x4 "IBI_SIR_REQ_REJECT,IBI SIR Request Rejection Control"
hexmask.long 0x4 0.--31. 1. "SIR_REQ_REJECT,In-band Slave Interrupt Request Reject"
line.long 0x8 "RESET_CTRL,This Register is used for general software reset and for individual buffer reset."
hexmask.long 0x8 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 5. "IBI_QUEUE_RST,IBI Queue Software Reset." "0,1"
newline
bitfld.long 0x8 4. "RX_FIFO_RST,Receive Buffer Software Reset." "0,1"
newline
bitfld.long 0x8 3. "TX_FIFO_RST,Transmit Buffer Software Reset" "0,1"
newline
bitfld.long 0x8 2. "RESP_QUEUE_RST,Response Queue Software Reset" "0,1"
newline
bitfld.long 0x8 1. "CMD_QUEUE_RST,Command Queue Software Reset" "0,1"
newline
bitfld.long 0x8 0. "SOFT_RST,Core Software Reset." "0,1"
line.long 0xC "SLV_EVENT_STATUS,This register indicates the status/values of some events/controls that are relavant to slave mode of operation. These values are set by Master initiated CCCs."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
newline
eventfld.long 0xC 7. "MWL_UPDATED,MWL Updated Status." "0,1"
newline
eventfld.long 0xC 6. "MRL_UPDATED,MRL Updated Status." "0,1"
newline
rbitfld.long 0xC 4.--5. "ACTIVITY_STATE,Activity State Status." "0,1,2,3"
newline
bitfld.long 0xC 3. "HJ_EN,Hot-Join Interrupt Enable" "0,1"
newline
rbitfld.long 0xC 2. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
rbitfld.long 0xC 1. "MR_EN,Master Request Enable." "0,1"
newline
rbitfld.long 0xC 0. "SIR_EN,Slave Interrupt Request Enable." "0,1"
line.long 0x10 "INTR_STATUS,Interrupt Status Register"
hexmask.long.tbyte 0x10 14.--31. 1. "Reserved_13,Reserved bitfield added by Magillem"
newline
eventfld.long 0x10 13. "BUSOWNER_UPDATED_STS,This interrupt is set when the role of the controller changes from being a Master to Slave or vice versa." "0,1"
newline
eventfld.long 0x10 12. "IBI_UPDATED_STS,IBI status is updated." "0,1"
newline
eventfld.long 0x10 11. "READ_REQ_RECV_STS,Read Request Received." "0,1"
newline
eventfld.long 0x10 10. "DEFSLV_STS,Define Slave CCC Received Status." "0,1"
newline
eventfld.long 0x10 9. "TRANSFER_ERR_STS,Transfer Error Status." "0,1"
newline
eventfld.long 0x10 8. "DYN_ADDR_ASSGN_STS,Dynamic Address Assigned Status." "0,1"
newline
rbitfld.long 0x10 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x10 6. "CCC_UPDATED_STS,CCC Table Updated Status." "0,1"
newline
eventfld.long 0x10 5. "TRANSFER_ABORT_STS,Transfer Abort Status." "0,1"
newline
rbitfld.long 0x10 4. "RESP_READY_STS,Response Queue Ready Status." "0,1"
newline
rbitfld.long 0x10 3. "CMD_QUEUE_READY_STS,Command Queue Ready." "0,1"
newline
rbitfld.long 0x10 2. "IBI_THLD_STS,IBI Buffer Threshold Status." "0,1"
newline
rbitfld.long 0x10 1. "RX_THLD_STS,Receive Buffer Threshold Status." "0,1"
newline
rbitfld.long 0x10 0. "TX_THLD_STS,Transmit Buffer Threshold Status" "0,1"
line.long 0x14 "INTR_STATUS_EN,Interrupt Status Enable Register."
hexmask.long.tbyte 0x14 14.--31. 1. "Reserved_13,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 13. "BUSOWNER_UPDATED_STS_EN,Bus owner Updated Status Enable" "0,1"
newline
bitfld.long 0x14 12. "IBI_UPDATED_STS_EN,IBI Updated Status Enable" "0,1"
newline
bitfld.long 0x14 11. "READ_REQ_RECV_STS_EN,Read Request Received Status Enable" "0,1"
newline
bitfld.long 0x14 10. "DEFSLV_STS_EN,Define Slave CCC Received Status Enable" "0,1"
newline
bitfld.long 0x14 9. "TRANSFER_ERR_STS_EN,Transfer Error Status Enable" "0,1"
newline
bitfld.long 0x14 8. "DYN_ADDR_ASSGN_STS_EN,Dynamic Address Assigned Status Enable" "0,1"
newline
rbitfld.long 0x14 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x14 6. "CCC_UPDATED_STS_EN,CCC Table Updated Status Enable." "0,1"
newline
bitfld.long 0x14 5. "TRANSFER_ABORT_STS_EN,Transfer Abort Status Enable." "0,1"
newline
bitfld.long 0x14 4. "RESP_READY_STS_EN,Response Queue Ready Status Enable" "0,1"
newline
bitfld.long 0x14 3. "CMD_QUEUE_READY_STS_EN,Command Queue Ready Status Enable" "0,1"
newline
bitfld.long 0x14 2. "IBI_THLD_STS_EN,IBI Buffer Threshold Status Enable." "0,1"
newline
bitfld.long 0x14 1. "RX_THLD_STS_EN,Receive Buffer Threshold Status Enable" "0,1"
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bitfld.long 0x14 0. "TX_THLD_STS_EN,Transmit Buffer Threshold Status Enable." "0,1"
line.long 0x18 "INTR_SIGNAL_EN,Interrupt Signal Enable Register"
hexmask.long.tbyte 0x18 14.--31. 1. "Reserved_13,Reserved bitfield added by Magillem"
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bitfld.long 0x18 13. "BUSOWNER_UPDATED_SIGNAL_EN,Bus owner Updated Signal Enable" "0,1"
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bitfld.long 0x18 12. "IBI_UPDATED_SIGNAL_EN,IBI Updated Signal Enable" "0,1"
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bitfld.long 0x18 11. "READ_REQ_RECV_SIGNAL_EN,Read Request Received Signal Enable" "0,1"
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bitfld.long 0x18 10. "DEFSLV_SIGNAL_EN,Define Slave CCC Received Signal Enable" "0,1"
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bitfld.long 0x18 9. "TRANSFER_ERR_SIGNAL_EN,Transfer Error Signal Enable" "0,1"
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bitfld.long 0x18 8. "DYN_ADDR_ASSGN_SIGNAL_EN,Dynamic Address Assigned Signal Enable" "0,1"
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rbitfld.long 0x18 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x18 6. "CCC_UPDATED_SIGNAL_EN,CCC Table Updated Signal Enable" "0,1"
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bitfld.long 0x18 5. "TRANSFER_ABORT_SIGNAL_EN,Transfer Abort Signal Enable" "0,1"
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bitfld.long 0x18 4. "RESP_READY_SIGNAL_EN,Response Queue Ready Signal Enable" "0,1"
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bitfld.long 0x18 3. "CMD_QUEUE_READY_SIGNAL_EN,Command Queue Ready Signal Enable" "0,1"
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bitfld.long 0x18 2. "IBI_THLD_SIGNAL_EN,IBI Buffer Threshold Signal Enable" "0,1"
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bitfld.long 0x18 1. "RX_THLD_SIGNAL_EN,Receive Buffer Threshold Signal Enable" "0,1"
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bitfld.long 0x18 0. "TX_THLD_SIGNAL_EN,Transmit Buffer Threshold Signal Enable" "0,1"
wgroup.long 0x48++0x3
line.long 0x0 "INTR_FORCE,Interrupt Force Enable Register"
hexmask.long.tbyte 0x0 14.--31. 1. "Reserved_13,Reserved bitfield added by Magillem"
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bitfld.long 0x0 13. "BUSOWNER_UPDATED_FORCE_EN,Bus owner Updated Force Enable" "0,1"
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bitfld.long 0x0 12. "IBI_UPDATED_FORCE_EN,IBI Updated Force Enable" "0,1"
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bitfld.long 0x0 11. "READ_REQ_FORCE_EN,Read Request Received Force Enable" "0,1"
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bitfld.long 0x0 10. "DEFSLV_FORCE_EN,Define Slave CCC Received Force Enable" "0,1"
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bitfld.long 0x0 9. "TRANSFER_ERR_FORCE_EN,Transfer Error Force Enable" "0,1"
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bitfld.long 0x0 8. "DYN_ADDR_ASSGN_FORCE_EN,Dynamic Address Assigned Force Enable" "0,1"
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bitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x0 6. "CCC_UPDATED_FORCE_EN,CCC Table Updated Force Enable" "0,1"
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bitfld.long 0x0 5. "TRANSFER_ABORT_FORCE_EN,Transfer Abort Force Enable" "0,1"
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bitfld.long 0x0 4. "RESP_READY_FORCE_EN,Response Queue Ready Force Enable" "0,1"
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bitfld.long 0x0 3. "CMD_QUEUE_READY_FORCE_EN,Command Queue Ready Force Enable" "0,1"
newline
bitfld.long 0x0 2. "IBI_THLD_FORCE_EN,IBI Buffer Threshold Force Enable" "0,1"
newline
bitfld.long 0x0 1. "RX_THLD_FORCE_EN,Receive Buffer Threshold Force Enable" "0,1"
newline
bitfld.long 0x0 0. "TX_THLD_FORCE_EN,Transmit Buffer Threshold Force Enable" "0,1"
rgroup.long 0x4C++0x13
line.long 0x0 "QUEUE_STATUS_LEVEL,Queue Status Level Register."
bitfld.long 0x0 29.--31. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 24.--28. 1. "IBI_STS_CNT,IBI Buffer Status Count."
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hexmask.long.byte 0x0 16.--23. 1. "IBI_BUF_BLR,IBI Buffer Level Value."
newline
hexmask.long.byte 0x0 8.--15. 1. "RESP_BUF_BLR,Response Buffer Level Value."
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hexmask.long.byte 0x0 0.--7. 1. "CMD_QUEUE_EMPTY_LOC,Command Queue Empty Locations."
line.long 0x4 "DATA_BUFFER_STATUS_LEVEL,Data Buffer Status Level Register."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x4 16.--23. 1. "RX_BUF_BLR,Receive Buffer Level Value."
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hexmask.long.byte 0x4 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x4 0.--7. 1. "TX_BUF_EMPTY_LOC,Transmit Buffer Empty Level Value."
line.long 0x8 "PRESENT_STATE,The user can get status of the DWC_mipi_i3c Controller from this 32-bit read only register. This register is relevant in both master and slave mode of operation and is meant to be used to get debug information related to the controllers.."
bitfld.long 0x8 29.--31. "Reserved_7,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 28. "MASTER_IDLE,This field reflects whether the Master Controller is in Idle state or not. This bit is set when all the Queues(Command   Response  IBI) and Buffers(Transmit and Receive) are empty along with the Master State machine is in Idle state." "0,1"
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hexmask.long.byte 0x8 24.--27. 1. "CMD_TID,This field reflects the Transaction-ID of the current executing command."
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bitfld.long 0x8 22.--23. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
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hexmask.long.byte 0x8 16.--21. 1. "CM_TFR_ST_STS,Current Master Transfer State Status."
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bitfld.long 0x8 14.--15. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3"
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hexmask.long.byte 0x8 8.--13. 1. "CM_TFR_STS,Transfer Type Status"
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hexmask.long.byte 0x8 3.--7. 1. "Reserved_3,Reserved bitfield added by Magillem"
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bitfld.long 0x8 2. "CURRENT_MASTER,This Bit is used to check whether the Master is Current Master or not. The Current Master is the Master" "0: Master is not Current Master,1: Master is Current Master"
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bitfld.long 0x8 1. "SDA_LINE_SIGNAL_LEVEL,This bit is used to check the SDA line level to recover from errors and for debugging. This bit" "0,1"
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bitfld.long 0x8 0. "SCL_LINE_SIGNAL_LEVEL,This bit is used to check the SCL line level to recover from errors and for debugging. This bit" "0,1"
line.long 0xC "CCC_DEVICE_STATUS,Device Operating Status Register."
hexmask.long.tbyte 0xC 14.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
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bitfld.long 0xC 13. "FRAME_ERROR,Frame Error" "0,1"
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bitfld.long 0xC 12. "BUFFER_NOT_AVAIL,Buffer not available" "0,1"
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bitfld.long 0xC 11. "DATA_NOT_READY,Data not ready" "0,1"
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bitfld.long 0xC 10. "OVERFLOW_ERR,Overflow Error" "0,1"
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bitfld.long 0xC 9. "SLAVE_BUSY,Slave Busy" "0,1"
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bitfld.long 0xC 8. "UNDERFLOW_ERR,Underflow error" "0,1"
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bitfld.long 0xC 6.--7. "ACTIVITY_MODE,Activity Mode" "0,1,2,3"
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bitfld.long 0xC 5. "PROTOCOL_ERR,Protocol Error" "0,1"
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bitfld.long 0xC 4. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
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hexmask.long.byte 0xC 0.--3. 1. "PENDING_INTR,Pending Interrupt"
line.long 0x10 "DEVICE_ADDR_TABLE_POINTER,Pointer for Device Address Table"
hexmask.long.word 0x10 16.--31. 1. "DEV_ADDR_TABLE_DEPTH,Depth of Device Address Table"
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hexmask.long.word 0x10 0.--15. 1. "P_DEV_ADDR_TABLE_START_ADDR,Start Address of Device Address Table."
group.long 0x60++0x3
line.long 0x0 "DEV_CHAR_TABLE_POINTER,Pointer for Device Characteristics Table"
hexmask.long.word 0x0 22.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
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bitfld.long 0x0 19.--21. "PRESENT_DEV_CHAR_TABLE_INDX,Current index of Device Characteristics Table." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 12.--18. 1. "DEV_CHAR_TABLE_DEPTH,Depth of Device Characteristics Table"
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hexmask.long.word 0x0 0.--11. 1. "P_DEV_CHAR_TABLE_START_ADDR,Start Address of Device Characteristics Table."
rgroup.long 0x6C++0x3
line.long 0x0 "VENDOR_SPECIFIC_REG_POINTER,Pointer for Vendor Specific Registers."
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.word 0x0 0.--15. 1. "P_VENDOR_REG_START_ADDR,Start Address of Vendor specific registers."
group.long 0x70++0xB
line.long 0x0 "SLV_MIPI_ID_VALUE,I3C MIPI Manufacturer ID Register."
hexmask.long.word 0x0 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
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hexmask.long.word 0x0 1.--15. 1. "SLV_MIPI_MFG_ID,Specifies the MIPI Manufacturer ID. (PID[47:33])."
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bitfld.long 0x0 0. "SLV_PROV_ID_SEL,Specifies the Provisional ID Type Selector (PID[32])." "0: Vendor Fixed Value,1: Random Value"
line.long 0x4 "SLV_PID_VALUE,I3C Normal Provisional ID Register."
hexmask.long.word 0x4 16.--31. 1. "SLV_PART_ID,Specifies the Part ID of DWC_mipi_i3c device (PID[31:16])"
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hexmask.long.byte 0x4 12.--15. 1. "SLV_INST_ID,This field is used to program the instance ID of the Slave. The reset value of"
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hexmask.long.word 0x4 0.--11. 1. "SLV_PID_DCR,Specifies the additional 12-bit ID of DWC_mipi_i3c device (PID[11:0])."
line.long 0x8 "SLV_CHAR_CTRL,I3C Slave Characteristic Register."
hexmask.long.byte 0x8 24.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x8 16.--23. 1. "HDR_CAP,I3C Device HDR Capability Register Value."
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hexmask.long.byte 0x8 8.--15. 1. "DCR,I3C Device Characteristic Value."
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bitfld.long 0x8 6.--7. "DEVICE_ROLE,Device Role field in Bus Characteristic Register (BCR[7:6])." "0,1,2,3"
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bitfld.long 0x8 5. "HDR_CAPABLE,SDR Only or SDR and HDR Capable field in Bus Characteristic Register (BCR[5])." "0,1"
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rbitfld.long 0x8 4. "BRIDGE_IDENTIFIER,Bridge Identifier field in Bus Characteristic Register (BCR[4])." "0,1"
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rbitfld.long 0x8 3. "OFFLINE_CAPABLE,Offline Capable field in Bus Characteristic Register (BCR[3])." "0,1"
newline
rbitfld.long 0x8 2. "IBI_PAYLOAD,IBI Payload field in Bus Characteristic Register (BCR[2])." "0,1"
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rbitfld.long 0x8 1. "IBI_REQUEST_CAPABLE,IBI Request Capable field in Bus Characteristic Register (BCR[1])." "0,1"
newline
bitfld.long 0x8 0. "MAX_DATA_SPEED_LIMIT,Max Data Speed Limitation field in Bus Characteristic Register (BCR[0])." "0,1"
rgroup.long 0x7C++0x7
line.long 0x0 "SLV_MAX_LEN,I3C Max Write/Read Length Register."
hexmask.long.word 0x0 16.--31. 1. "MRL,I3C Device Max Read Length."
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hexmask.long.word 0x0 0.--15. 1. "MWL,I3C Device Max Write Length"
line.long 0x4 "MAX_READ_TURNAROUND,MXDS Maximum Read Turnaround Time."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.tbyte 0x4 0.--23. 1. "MXDS_MAX_RD_TURN,Specifies the maximum read turnaround time (in microseconds (us)) of DWC_mipi_i3c Slave."
group.long 0x84++0x3
line.long 0x0 "MAX_DATA_SPEED,The values in this register are returned by the slave as GETACCMST CCC data. ."
hexmask.long.word 0x0 19.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
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bitfld.long 0x0 16.--18. "MXDS_CLK_DATA_TURN,Specifies the clock to data turnaround time (Tsco parameter) of DWC_mipi_i3c Slave device" "0: 8ns,1: 9ns,2: 10ns,3: 11ns,4: 12ns,?,?,?"
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8.--10. "MXDS_MAX_RD_SPEED,Specifies the Maximum Sustained Data Rate for non-CCC messages sent by DWC_mipi_i3c Slave Device to Master Device" "0: 12,1: 8MHZ,2: 6MHz,3: 4MHz,4: 2MHz,?,?,?"
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hexmask.long.byte 0x0 3.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--2. "MXDS_MAX_WR_SPEED,Specifies the Maximum Sustained Data Rate for non-CCC messages sent by Master Device to DWC_mipi_i3c Slave device" "0: 12,1: 8MHZ,2: 6MHz,3: 4MHz,4: 2MHz,?,?,?"
group.long 0x8C++0x3
line.long 0x0 "SLV_INTR_REQ,This register is used in slave mode of operation."
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x0 8.--9. "IBI_STS,IBI Completion Status" "0: Reserved,1: IBI accepted by the Master,2: Reserved,3: IBI Not Attempted"
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hexmask.long.byte 0x0 4.--7. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 3. "MR,Master Request" "0,1"
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bitfld.long 0x0 1.--2. "SIR_CTRL,Slave Interrupt Request Control" "0: Send the Assigned Dynamic Address,1: Reserved,2: Reserved,3: Reserved"
newline
bitfld.long 0x0 0. "SIR,Slave Interrupt Request" "0,1"
group.long 0xB0++0x13
line.long 0x0 "DEVICE_CTRL_EXTENDED,Device Control Extended register."
hexmask.long 0x0 4.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 3. "REQMST_ACK_CTRL,In Slave mode of operation  this bit serves as a control to ACK/NACK GETACCMST CCC from current master." "0: ACK GETACCMST CCC,1: NACK GETACCMST CCC"
newline
rbitfld.long 0x0 2. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 0.--1. "DEV_OPERATION_MODE,This bit is used to select the Device Operation Mode before the controller is enabled." "0: Master,1: Slave,2: Reserved,3: Reserved"
line.long 0x4 "SCL_I3C_OD_TIMING,SCL I3C Open Drain Timing Register"
hexmask.long.byte 0x4 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x4 16.--23. 1. "I3C_OD_HCNT,I3C Open Drain High Count."
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hexmask.long.byte 0x4 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x4 0.--7. 1. "I3C_OD_LCNT,I3C Open Drain Low Count."
line.long 0x8 "SCL_I3C_PP_TIMING,SCL I3C Push Pull Timing Register"
hexmask.long.byte 0x8 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 16.--23. 1. "I3C_PP_HCNT,I3C Push Pull High Count."
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hexmask.long.byte 0x8 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x8 0.--7. 1. "I3C_PP_LCNT,I3C Push Pull Low Count."
line.long 0xC "SCL_I2C_FM_TIMING,SCL I2C Fast Mode Timing Register"
hexmask.long.word 0xC 16.--31. 1. "I2C_FM_HCNT,I2C Fast Mode High Count"
newline
hexmask.long.word 0xC 0.--15. 1. "I2C_FM_LCNT,I2C Fast Mode Low Count"
line.long 0x10 "SCL_I2C_FMP_TIMING,SCL I2C Fast Mode Plus Timing Register"
hexmask.long.byte 0x10 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 16.--23. 1. "I2C_FMP_HCNT,I2C Fast Mode Plus High Count"
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hexmask.long.word 0x10 0.--15. 1. "I2C_FMP_LCNT,I2C Fast Mode Plus Low Count"
group.long 0xC8++0x13
line.long 0x0 "SCL_EXT_LCNT_TIMING,SCL Extended Low Count Timing Register."
hexmask.long.byte 0x0 24.--31. 1. "I3C_EXT_LCNT_4,I3C Extended Low Count Register 4"
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hexmask.long.byte 0x0 16.--23. 1. "I3C_EXT_LCNT_3,I3C Extended Low Count Register 3"
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hexmask.long.byte 0x0 8.--15. 1. "I3C_EXT_LCNT_2,I3C Extended Low Count Register 2"
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hexmask.long.byte 0x0 0.--7. 1. "I3C_EXT_LCNT_1,I3C Extended Low Count Register 1"
line.long 0x4 "SCL_EXT_TERMN_LCNT_TIMING,SCL Termination Bit Low Count Timing Register"
hexmask.long 0x4 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--3. 1. "I3C_EXT_TERMN_LCNT,I3C Read Termination Bit Low count."
line.long 0x8 "SDA_HOLD_SWITCH_DLY_TIMING,SDA Hold and Mode Switch Delay Timing Register"
hexmask.long.word 0x8 19.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 16.--18. "SDA_TX_HOLD,This field controls the hold time (in term of the core clock period) of the transmit data (SDA) with" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x8 0.--15. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0xC "BUS_FREE_AVAIL_TIMING,Bus Free and Available Timing Register"
hexmask.long.word 0xC 16.--31. 1. "BUS_AVAILABLE_TIME,This register field is used only in Slave mode of operation"
newline
hexmask.long.word 0xC 0.--15. 1. "BUS_FREE_TIME,This register field is used only in Master mode of operation"
line.long 0x10 "BUS_IDLE_TIMING,Bus Idle Timing Register"
hexmask.long.word 0x10 20.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.tbyte 0x10 0.--19. 1. "BUS_IDLE_TIME,Bus Idle Count Value."
rgroup.long 0xE0++0xB
line.long 0x0 "I3C_VER_ID,This register reflects the current release number of DWC_mipi_i3c"
hexmask.long 0x0 0.--31. 1. "I3C_VER_ID,Current release number"
line.long 0x4 "I3C_VER_TYPE,This register reflects the current release type of DWC_mipi_i3c."
hexmask.long 0x4 0.--31. 1. "I3C_VER_TYPE,Current release type"
line.long 0x8 "QUEUE_SIZE_CAPABILITY,This register reflects the configured size of the Data Buffer and Queues in DWC_mipi_i3c."
hexmask.long.word 0x8 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x8 16.--19. 1. "IBI_BUF_SIZE,IBI Queue Size"
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hexmask.long.byte 0x8 12.--15. 1. "RESP_BUF_SIZE,Response Queue Size"
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hexmask.long.byte 0x8 8.--11. 1. "CMD_BUF_SIZE,Command Queue Size"
newline
hexmask.long.byte 0x8 4.--7. 1. "RX_BUF_SIZE,Receive Data Buffer Size"
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hexmask.long.byte 0x8 0.--3. 1. "TX_BUF_SIZE,Transmit Data Buffer Size"
rgroup.long 0x200++0x3
line.long 0x0 "DEV_CHAR_TABLE1_LOC1,Device Characteristic Table Location-1 of Device1"
hexmask.long 0x0 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
rgroup.long 0x200++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE1,Secondary Master Device Characteristic Table Location of Device1"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device1"
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hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device1"
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hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device1"
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hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device1"
line.long 0x4 "DEV_CHAR_TABLE1_LOC2,Device Characteristic Table Location-2 of Device1"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
rgroup.long 0x204++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE2,Secondary Master Device Characteristic Table Location of Device2"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device2"
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hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device2"
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hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device2"
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hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device2"
line.long 0x4 "DEV_CHAR_TABLE1_LOC3,Device Characteristic Table Location-3 of Device1"
hexmask.long.word 0x4 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x4 8.--15. 1. "BCR,Bus Characteristic Value"
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hexmask.long.byte 0x4 0.--7. 1. "DCR,Device Characteristic Value"
rgroup.long 0x208++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE3,Secondary Master Device Characteristic Table Location of Device3"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device3"
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hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device3"
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hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device3"
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hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device3"
line.long 0x4 "DEV_CHAR_TABLE1_LOC4,Device Characteristic Table Location-4 of Device1"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
rgroup.long 0x20C++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE4,Secondary Master Device Characteristic Table Location of Device4"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device4"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device4"
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hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device4"
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hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device4"
line.long 0x4 "DEV_CHAR_TABLE2_LOC1,Device Characteristic Table Location-1 of Device2"
hexmask.long 0x4 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
rgroup.long 0x210++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE5,Secondary Master Device Characteristic Table Location of Device5"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device5"
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hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device5"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device5"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device5"
line.long 0x4 "DEV_CHAR_TABLE2_LOC2,Device Characteristic Table Location-2 of Device2"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
rgroup.long 0x214++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE6,Secondary Master Device Characteristic Table Location of Device6"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device6"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device6"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device6"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device6"
line.long 0x4 "DEV_CHAR_TABLE2_LOC3,Device Characteristic Table Location-3 of Device2"
hexmask.long.word 0x4 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x4 0.--7. 1. "DCR,Device Characteristic Value"
rgroup.long 0x218++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE7,Secondary Master Device Characteristic Table Location of Device7"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device7"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device7"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device7"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device7"
line.long 0x4 "DEV_CHAR_TABLE2_LOC4,Device Characteristic Table Location-4 of Device2"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
rgroup.long 0x21C++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE8,Secondary Master Device Characteristic Table Location of Device8"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device8"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device8"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device8"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device8"
line.long 0x4 "DEV_CHAR_TABLE3_LOC1,Device Characteristic Table Location-1 of Device3"
hexmask.long 0x4 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
rgroup.long 0x220++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE9,Secondary Master Device Characteristic Table Location of Device9"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device9"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device9"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device9"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device9"
line.long 0x4 "DEV_CHAR_TABLE3_LOC2,Device Characteristic Table Location-2 of Device3"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
rgroup.long 0x224++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE10,Secondary Master Device Characteristic Table Location of Device10"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device10"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device10"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device10"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device10"
line.long 0x4 "DEV_CHAR_TABLE3_LOC3,Device Characteristic Table Location-3 of Device3"
hexmask.long.word 0x4 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x4 0.--7. 1. "DCR,Device Characteristic Value"
rgroup.long 0x228++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE11,Secondary Master Device Characteristic Table Location of Device11"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device11"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device11"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device11"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device11"
line.long 0x4 "DEV_CHAR_TABLE3_LOC4,Device Characteristic Table Location-4 of Device3"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
rgroup.long 0x22C++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE12,Secondary Master Device Characteristic Table Location of Device12"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device12"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device12"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device12"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device12"
line.long 0x4 "DEV_CHAR_TABLE4_LOC1,Device Characteristic Table Location-1 of Device4"
hexmask.long 0x4 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
rgroup.long 0x230++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE13,Secondary Master Device Characteristic Table Location of Device13"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device13"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device13"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device13"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device13"
line.long 0x4 "DEV_CHAR_TABLE4_LOC2,Device Characteristic Table Location-2 of Device4"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
rgroup.long 0x234++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE14,Secondary Master Device Characteristic Table Location of Device14"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device14"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device14"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device14"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device14"
line.long 0x4 "DEV_CHAR_TABLE4_LOC3,Device Characteristic Table Location-3 of Device4"
hexmask.long.word 0x4 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x4 0.--7. 1. "DCR,Device Characteristic Value"
rgroup.long 0x238++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE15,Secondary Master Device Characteristic Table Location of Device15"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device15"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device15"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device15"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device15"
line.long 0x4 "DEV_CHAR_TABLE4_LOC4,Device Characteristic Table Location-4 of Device4"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
rgroup.long 0x23C++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE16,Secondary Master Device Characteristic Table Location of Device16"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device16"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device16"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device16"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device16"
line.long 0x4 "DEV_CHAR_TABLE5_LOC1,Device Characteristic Table Location-1 of Device5"
hexmask.long 0x4 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
rgroup.long 0x240++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE17,Secondary Master Device Characteristic Table Location of Device17"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device17"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device17"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device17"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device17"
line.long 0x4 "DEV_CHAR_TABLE5_LOC2,Device Characteristic Table Location-2 of Device5"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
rgroup.long 0x244++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE18,Secondary Master Device Characteristic Table Location of Device18"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device18"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device18"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device18"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device18"
line.long 0x4 "DEV_CHAR_TABLE5_LOC3,Device Characteristic Table Location-3 of Device5"
hexmask.long.word 0x4 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x4 0.--7. 1. "DCR,Device Characteristic Value"
rgroup.long 0x248++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE19,Secondary Master Device Characteristic Table Location of Device19"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device19"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device19"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device19"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device19"
line.long 0x4 "DEV_CHAR_TABLE5_LOC4,Device Characteristic Table Location-4 of Device5"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
rgroup.long 0x24C++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE20,Secondary Master Device Characteristic Table Location of Device20"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device20"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device20"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device20"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device20"
line.long 0x4 "DEV_CHAR_TABLE6_LOC1,Device Characteristic Table Location-1 of Device6"
hexmask.long 0x4 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
rgroup.long 0x250++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE21,Secondary Master Device Characteristic Table Location of Device21"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device21"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device21"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device21"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device21"
line.long 0x4 "DEV_CHAR_TABLE6_LOC2,Device Characteristic Table Location-2 of Device6"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
rgroup.long 0x254++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE22,Secondary Master Device Characteristic Table Location of Device22"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device22"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device22"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device22"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device22"
line.long 0x4 "DEV_CHAR_TABLE6_LOC3,Device Characteristic Table Location-3 of Device6"
hexmask.long.word 0x4 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x4 0.--7. 1. "DCR,Device Characteristic Value"
rgroup.long 0x258++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE23,Secondary Master Device Characteristic Table Location of Device23"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device23"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device23"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device23"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device23"
line.long 0x4 "DEV_CHAR_TABLE6_LOC4,Device Characteristic Table Location-4 of Device6"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
rgroup.long 0x25C++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE24,Secondary Master Device Characteristic Table Location of Device24"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device24"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device24"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device24"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device24"
line.long 0x4 "DEV_CHAR_TABLE7_LOC1,Device Characteristic Table Location-1 of Device7"
hexmask.long 0x4 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
rgroup.long 0x260++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE25,Secondary Master Device Characteristic Table Location of Device25"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device25"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device25"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device25"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device25"
line.long 0x4 "DEV_CHAR_TABLE7_LOC2,Device Characteristic Table Location-2 of Device7"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
rgroup.long 0x264++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE26,Secondary Master Device Characteristic Table Location of Device26"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device26"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device26"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device26"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device26"
line.long 0x4 "DEV_CHAR_TABLE7_LOC3,Device Characteristic Table Location-3 of Device7"
hexmask.long.word 0x4 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x4 0.--7. 1. "DCR,Device Characteristic Value"
rgroup.long 0x268++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE27,Secondary Master Device Characteristic Table Location of Device27"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device27"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device27"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device27"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device27"
line.long 0x4 "DEV_CHAR_TABLE7_LOC4,Device Characteristic Table Location-4 of Device7"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
rgroup.long 0x26C++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE28,Secondary Master Device Characteristic Table Location of Device28"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device28"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device28"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device28"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device28"
line.long 0x4 "DEV_CHAR_TABLE8_LOC1,Device Characteristic Table Location-1 of Device8"
hexmask.long 0x4 0.--31. 1. "LSB_PROVISIONAL_ID,The LSB 32-bit value of Provisional-ID"
rgroup.long 0x270++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE29,Secondary Master Device Characteristic Table Location of Device29"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device29"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device29"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device29"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device29"
line.long 0x4 "DEV_CHAR_TABLE8_LOC2,Device Characteristic Table Location-2 of Device8"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--15. 1. "MSB_PROVISIONAL_ID,The MSB 16-bit value of Provisional-ID"
rgroup.long 0x274++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE30,Secondary Master Device Characteristic Table Location of Device30"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device30"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device30"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device30"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device30"
line.long 0x4 "DEV_CHAR_TABLE8_LOC3,Device Characteristic Table Location-3 of Device8"
hexmask.long.word 0x4 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 8.--15. 1. "BCR,Bus Characteristic Value"
newline
hexmask.long.byte 0x4 0.--7. 1. "DCR,Device Characteristic Value"
rgroup.long 0x278++0x7
line.long 0x0 "SEC_DEV_CHAR_TABLE31,Secondary Master Device Characteristic Table Location of Device31"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device31"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device31"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device31"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device31"
line.long 0x4 "DEV_CHAR_TABLE8_LOC4,Device Characteristic Table Location-4 of Device8"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address assigned."
rgroup.long 0x27C++0x3
line.long 0x0 "SEC_DEV_CHAR_TABLE32,Secondary Master Device Characteristic Table Location of Device32"
hexmask.long.byte 0x0 24.--31. 1. "STATIC_ADDR,The Static Addr of Device32"
newline
hexmask.long.byte 0x0 16.--23. 1. "BCR_TYPE,The BCR TYPE of Device32"
newline
hexmask.long.byte 0x0 8.--15. 1. "DCR_TYPE,The DCR TYPE of Device32"
newline
hexmask.long.byte 0x0 0.--7. 1. "DYNAMIC_ADDR,The Dynamic Addr of Device32"
group.long 0x280++0x2B
line.long 0x0 "DEV_ADDR_TABLE_LOC1,Device Address Table of Device1"
bitfld.long 0x0 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0x0 29.--30. "DEV_NACK_RETRY_CNT,This field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x0 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0x0 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
line.long 0x4 "DEV_ADDR_TABLE_LOC2,Device Address Table of Device2"
bitfld.long 0x4 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0x4 29.--30. "DEV_NACK_RETRY_CNT,DEVICE_NACK_RETRY_CNT: These field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x4 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0x4 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
line.long 0x8 "DEV_ADDR_TABLE_LOC3,Device Address Table of Device3"
bitfld.long 0x8 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0x8 29.--30. "DEV_NACK_RETRY_CNT,DEVICE_NACK_RETRY_CNT: These field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x8 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0x8 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
line.long 0xC "DEV_ADDR_TABLE_LOC4,Device Address Table of Device4"
bitfld.long 0xC 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0xC 29.--30. "DEV_NACK_RETRY_CNT,DEVICE_NACK_RETRY_CNT: These field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0xC 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0xC 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
line.long 0x10 "DEV_ADDR_TABLE_LOC5,Device Address Table of Device5"
bitfld.long 0x10 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0x10 29.--30. "DEV_NACK_RETRY_CNT,DEVICE_NACK_RETRY_CNT: These field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x10 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0x10 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
line.long 0x14 "DEV_ADDR_TABLE_LOC6,Device Address Table of Device6"
bitfld.long 0x14 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0x14 29.--30. "DEV_NACK_RETRY_CNT,DEVICE_NACK_RETRY_CNT: These field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x14 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x14 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0x14 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x14 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
line.long 0x18 "DEV_ADDR_TABLE_LOC7,Device Address Table of Device7"
bitfld.long 0x18 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0x18 29.--30. "DEV_NACK_RETRY_CNT,DEVICE_NACK_RETRY_CNT: These field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x18 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x18 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0x18 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x18 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
line.long 0x1C "DEV_ADDR_TABLE_LOC8,Device Address Table of Device8"
bitfld.long 0x1C 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0x1C 29.--30. "DEV_NACK_RETRY_CNT,DEVICE_NACK_RETRY_CNT: These field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x1C 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x1C 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0x1C 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x1C 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
line.long 0x20 "DEV_ADDR_TABLE_LOC9,Device Address Table of Device9"
bitfld.long 0x20 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0x20 29.--30. "DEV_NACK_RETRY_CNT,DEVICE_NACK_RETRY_CNT: These field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x20 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x20 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0x20 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x20 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
line.long 0x24 "DEV_ADDR_TABLE_LOC10,Device Address Table of Device10"
bitfld.long 0x24 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0x24 29.--30. "DEV_NACK_RETRY_CNT,DEVICE_NACK_RETRY_CNT: These field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x24 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0x24 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
line.long 0x28 "DEV_ADDR_TABLE_LOC11,Device Address Table of Device11"
bitfld.long 0x28 31. "LEGACY_I2C_DEVICE,Legacy I2C device or not." "0,1"
newline
bitfld.long 0x28 29.--30. "DEV_NACK_RETRY_CNT,DEVICE_NACK_RETRY_CNT: These field is used to set the Device NACK Retry count for the particular device." "0,1,2,3"
newline
hexmask.long.byte 0x28 24.--28. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x28 16.--23. 1. "DEV_DYNAMIC_ADDR,Device Dynamic Address with parity."
newline
hexmask.long.word 0x28 7.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x28 0.--6. 1. "DEV_STATIC_ADDR,Device Static Address."
tree.end
tree.end
tree "NAND (NAND Flash Controller)"
base ad:0x10B80000
group.long 0x0++0x13
line.long 0x0 "cmd_reg0,Command register 0. Writing data to this register will initiate a new transaction of the NF controller."
hexmask.long 0x0 0.--31. 1. "cmd0,Command 0 register field."
line.long 0x4 "cmd_reg1,Command register 1."
hexmask.long 0x4 0.--31. 1. "cmd1,Command 1 register field."
line.long 0x8 "cmd_reg2,Command register 2."
hexmask.long 0x8 0.--31. 1. "cmd2,Command 2 register field."
line.long 0xC "cmd_reg3,Command register 3."
hexmask.long 0xC 0.--31. 1. "cmd3,Command 3 register field."
line.long 0x10 "cmd_status_ptr,Pointer register to select which thread status is selected."
hexmask.long 0x10 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x10 0.--2. "thrd_status_sel,Number of thread whose status is available in cmd_status register." "0,1,2,3,4,5,6,7"
rgroup.long 0x14++0x7
line.long 0x0 "cmd_status,Command status register for selected thread."
hexmask.long 0x0 0.--31. 1. "cmd_status,Command status register field. This field gives the software direct access to selected thread descriptor status. Number of accessed thread can be selected with cmd_status_ptr register"
line.long 0x4 "cmd_status_ext,Extended command status register for selected thread."
hexmask.long 0x4 0.--31. 1. "cmd_status_ext,Command status register field. This field gives the software direct access to a higher part of selected thread descriptors status. Number of accessed thread can be selected with cmd_status_ptr register"
group.long 0x20++0xB
line.long 0x0 "cmd_reg4,Command register 4."
hexmask.long 0x0 0.--31. 1. "cmd4,Command 4 register field."
line.long 0x4 "cmd_reg5,Command register 5."
hexmask.long 0x4 0.--31. 1. "cmd5,Command 5 register field."
line.long 0x8 "cmd_reg6,Command register 6."
hexmask.long 0x8 0.--31. 1. "cmd6,Command 6 register field."
group.long 0x110++0xB
line.long 0x0 "intr_status,Controller status register"
hexmask.long.byte 0x0 26.--31. 1. "Reserved_10,Reserved bitfield added by Magillem"
eventfld.long 0x0 25. "prot_err,This bit is set when access to the protected area inside" "0,1"
newline
eventfld.long 0x0 24. "di_ctx_err,This bit is set when parity error is detected during" "0,1"
eventfld.long 0x0 23. "Reserved,Reserved." "0,1"
newline
eventfld.long 0x0 22. "sdma_err,This bit is set when not allowed access to the Slave DMA interface is detected" "0,1"
eventfld.long 0x0 21. "sdma_trigg,This bit is set when trigger condition for the Slave DMA is met." "0,1"
newline
eventfld.long 0x0 20. "cmd_ignored,Detected sending of command to busy thread and ignored it." "0,1"
eventfld.long 0x0 19. "cmd_reg_par_err,Incorrect parity on SFR interface detected." "0,1"
newline
eventfld.long 0x0 18. "ddma_terr,Master Data DMA Target error. This bit is set if Master DMA Data engine module detects system bus error during reading or writing data" "0,1"
eventfld.long 0x0 17. "cdma_terr,Command DMA Target error. This bit is set if Command Engine module detects system bus error during reading descriptor from system memory or during descriptor status field write operation" "0,1"
newline
eventfld.long 0x0 16. "cdma_idle,Command DMA is in the Idle state" "0,1"
hexmask.long.word 0x0 0.--15. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x4 "intr_enable,Interrupt enable register. If selected bit of this register is set. high logic value of the corresponding bit in intr_status will generate setting of external interrupt line."
bitfld.long 0x4 31. "intr_en,Global Interrupts enable flag." "0,1"
hexmask.long.byte 0x4 26.--30. 1. "Reserved_10,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 25. "prot_err_en,Enables interrupt when access to the protected area inside" "0,1"
bitfld.long 0x4 24. "di_ctx_err_en,Enables interrupt when error was detected during ZQ Calibration process" "0,1"
newline
bitfld.long 0x4 23. "Reserved,Reserved" "0,1"
bitfld.long 0x4 22. "sdma_err_en,Enables interrupt when not allowed access to the Slave DMA interface is detected" "0,1"
newline
bitfld.long 0x4 21. "sdma_trigg_en,Enables interrupt when trigger condition for the Slave DMA is met." "0,1"
bitfld.long 0x4 20. "cmd_ignored_en,Interrupt enable for detecting of ignored command." "0,1"
newline
bitfld.long 0x4 19. "cmd_reg_par_err_en,Interrupt enable for detecting parity error on SFR interface." "0,1"
bitfld.long 0x4 18. "ddma_terr_en,Interrupt enable for detecting Data DMA Master target error." "0,1"
newline
bitfld.long 0x4 17. "cdma_terr_en,Interrupt enable for detecting CMD Engine target error." "0,1"
bitfld.long 0x4 16. "cdma_idle_en,Interrupt enable for detecting Command Engine IDLE" "0,1"
newline
hexmask.long.word 0x4 0.--15. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x8 "ctrl_status,Controller internal state."
hexmask.long.word 0x8 17.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
eventfld.long 0x8 16. "sdma_paused,This bit indicates that Slave DMA transaction was aborted due to detected error/incorrect access type on system interface. Controller will not invoke transfer of next data block through the Slave DMA interface if this bit is set." "0,1"
newline
hexmask.long.byte 0x8 11.--15. 1. "Reserved_8,Reserved bitfield added by Magillem"
rbitfld.long 0x8 10. "init_fail,Initialization process failed." "0,1"
newline
rbitfld.long 0x8 9. "init_comp,The Cadence NAND Flash Memory Controller has completed its reset and initialization process." "0,1"
rbitfld.long 0x8 8. "ctrl_busy,This bit indicates if controller is in the busy state or not. The 0x1 value informs that controller is in the busy state. This bit is routed to the controller interface as ctrl_busy pin." "0,1"
newline
rbitfld.long 0x8 5.--7. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
rbitfld.long 0x8 4. "Reserved,Reserved." "0,1"
newline
rbitfld.long 0x8 3. "mc_busy,If 1 the Mini Controller internal module is busy." "0,1"
rbitfld.long 0x8 2. "cmd_eng_busy,If 1 the Command Engine internal module is busy." "0,1"
newline
rbitfld.long 0x8 1. "mdma_busy,If 1 the Master DMA internal module is busy." "0,1"
rbitfld.long 0x8 0. "sdma_busy,If 1 the Slave DMA internal module is busy." "0,1"
rgroup.long 0x120++0x3
line.long 0x0 "trd_status,Command Engine threads state."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "trd_busy,Indicates Command Engine thread busy status. If 1 corresponding thread is busy."
group.long 0x128++0x3
line.long 0x0 "trd_error_intr_status,Thread error indicates that the Command Engine thread detected an error condition. To get more information on the error. s/w needs to read the status field of the descriptor or appropriate status register depending on current work.."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved bitfield added by Magillem"
eventfld.long 0x0 7. "trd7_error_stat,Thread 7 error." "0,1"
newline
eventfld.long 0x0 6. "trd6_error_stat,Thread 6 error." "0,1"
eventfld.long 0x0 5. "trd5_error_stat,Thread 5 error." "0,1"
newline
eventfld.long 0x0 4. "trd4_error_stat,Thread 4 error." "0,1"
eventfld.long 0x0 3. "trd3_error_stat,Thread 3 error." "0,1"
newline
eventfld.long 0x0 2. "trd2_error_stat,Thread 2 error." "0,1"
eventfld.long 0x0 1. "trd1_error_stat,Thread 1 error." "0,1"
newline
eventfld.long 0x0 0. "trd0_error_stat,Thread 0 error." "0,1"
group.long 0x130++0x3
line.long 0x0 "trd_error_intr_en,Interrupt enable register. If selected bit of this register is set. rising edge of corresponding bit in trd_error_intr_status will cause setting of the external interrupt line."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "trd_error_intr_en,Interrupt enable for detecting thread error."
group.long 0x138++0x3
line.long 0x0 "trd_comp_intr_status,Each bit of this field correspond to the Command Engine thread. Each bit informs about descriptor status for selected thread. It is set only when INT bit of descriptor is set"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved bitfield added by Magillem"
eventfld.long 0x0 7. "trd7_comp,Thread 7 operation complete flag." "0,1"
newline
eventfld.long 0x0 6. "trd6_comp,Thread 6 operation complete flag." "0,1"
eventfld.long 0x0 5. "trd5_comp,Thread 5 operation complete flag." "0,1"
newline
eventfld.long 0x0 4. "trd4_comp,Thread 4 operation complete flag." "0,1"
eventfld.long 0x0 3. "trd3_comp,Thread 3 operation complete flag." "0,1"
newline
eventfld.long 0x0 2. "trd2_comp,Thread 2 operation complete flag." "0,1"
eventfld.long 0x0 1. "trd1_comp,Thread 1 operation complete flag." "0,1"
newline
eventfld.long 0x0 0. "trd0_comp,Thread 0 operation complete flag." "0,1"
rgroup.long 0x140++0xB
line.long 0x0 "dma_target_error_l,DMA target error address [31:0]. This register can be used to obtain address of transaction which caused setting of cdma_terr or ddma_terr bits in the intr_status register."
hexmask.long 0x0 0.--31. 1. "target_err_l,Address of the first transaction on the master interface that returned error response."
line.long 0x4 "dma_target_error_h,DMA target error address [63:32]. This register can be used to obtain address of transaction which caused setting of cdma_terr or ddma_terr bits in the intr_status register."
hexmask.long 0x4 0.--31. 1. "target_err_h,Address of the first transaction on the master interface that returned error response."
line.long 0x8 "boot_status,This register provides status of the latest boot operation."
hexmask.long.tbyte 0x8 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
bitfld.long 0x8 9. "ctx_err,This field (when set) indicates that the CTX error occurred during boot sequence." "0,1"
newline
bitfld.long 0x8 8. "di_err,This field (when set) indicates that the DI error occurred during boot sequence." "0,1"
bitfld.long 0x8 7. "tim_out_err,This field (when set) indicates that the time out error occurred during boot sequence." "0,1"
newline
bitfld.long 0x8 6. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x8 4.--5. "cpy_id,This field identifies a boot block used in the latest boot sequence run. Allowed values are: [list] [*] 00 - block 0 was used  [*] 01 - block 1 was used and [*] 10 - block 2 was used.[/list]" "0,1,2,3"
newline
bitfld.long 0x8 3. "phy_err,This field describe PHY status during boot process. If it is set to high the boot process is failed due to dfi_dqs_underrun/dfi_dqs_overflow error. Allowed values are:[list] [*] 0 - no error detected  [*] 1 - error detected.[/list]" "0,1"
bitfld.long 0x8 2. "bus_err,This field describes bus status during boot process. If it is set to high  the boot process failed due to the bus interface receiving an error response from the target. Allowed values are:[list] [*] 0 - no error detected  [*] 1 - error.." "0,1"
newline
bitfld.long 0x8 0.--1. "bch_err_type,This field identifies kind of error detected during boot sequence process. Allowed values are:[list] [*] 00 - no errors detected  [*] 01 - correctable error detected  [*] 10 - uncorrectable error detected.[/list]" "0,1,2,3"
group.long 0x14C++0x3
line.long 0x0 "trd_timeout_intr_status,Timeout status register indicates that a timeout condition on the Command Engine thread was detected."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved bitfield added by Magillem"
eventfld.long 0x0 7. "trd7_timeout_stat,Thread 7 timeout." "0,1"
newline
eventfld.long 0x0 6. "trd6_timeout_stat,Thread 6 timeout." "0,1"
eventfld.long 0x0 5. "trd5_timeout_stat,Thread 5 timeout." "0,1"
newline
eventfld.long 0x0 4. "trd4_timeout_stat,Thread 4 timeout." "0,1"
eventfld.long 0x0 3. "trd3_timeout_stat,Thread 3 timeout." "0,1"
newline
eventfld.long 0x0 2. "trd2_timeout_stat,Thread 2 timeout." "0,1"
eventfld.long 0x0 1. "trd1_timeout_stat,Thread 1 timeout." "0,1"
newline
eventfld.long 0x0 0. "trd0_timeout_stat,Thread 0 timeout." "0,1"
group.long 0x154++0x3
line.long 0x0 "trd_timeout_intr_en,Interrupt enable register. If selected bit of this register is set rising edge of corresponding bit in trd_timeout_intr_status will cause setting of the external interrupt line."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "trd_timeout_intr_en,Interrupt enable for detecting thread timeout."
group.long 0x15C++0x3
line.long 0x0 "zq_cal_stat,Reserved."
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "Reserved,Reserved"
group.long 0x400++0x3F
line.long 0x0 "transfer_cfg_0,Transfer config 0 register. It is utilized to configure data transfer parameters."
hexmask.long.word 0x0 16.--31. 1. "offset,Offset value from the beginning of the page  used for data transfer."
hexmask.long.byte 0x0 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--7. 1. "sector_cnt,Number of sectors which is transferred within single NF device's page. This is one of the fields which determines size of data transfer within one NAND Flash device's page (sector_size * (sector_cnt-1) + last_sector_size). Controller will.."
line.long 0x4 "transfer_cfg_1,Transfer config 1 register. It is utilized to configure data transfer parameters."
hexmask.long.word 0x4 16.--31. 1. "last_sector_size,Size of last data sector. This is one of the fields which determines size of data transfer within one NAND Flash device's page (sector_size * (sector_cnt-1) + last_sector_size). If ECC checking is enabled the values of this register.."
hexmask.long.word 0x4 0.--15. 1. "sector_size,Size of not-last data sector. This is one of the fields which determines size of data transfer within one NAND Flash device's page (sector_size * (sector_cnt-1) + last_sector_size). If ECC checking is enabled the values of this register.."
line.long 0x8 "long_polling,Wait count value for long polling."
hexmask.long.word 0x8 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x8 0.--15. 1. "long_polling,Number of system clock cycles after issue of erase/write/read operation before the controller starts to poll for status. This value is valid only in the status polling mode. First polling will happen after this many number of system clock.."
line.long 0xC "short_polling,Status monitor cycle count value."
hexmask.long.word 0xC 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0xC 0.--15. 1. "short_polling,Number of system clocks after long polling delay before the controller starts to poll for status if first status poll attempt returned information that controller is busy. The long polling value should be significantly larger the short.."
line.long 0x10 "rdst_ctrl_0,Device ready status control register."
hexmask.long.byte 0x10 24.--31. 1. "ready_mask,If rb_enable=0 and then this field determines the mask used to comparison of response from the NF memory to the device status command and ready_value"
hexmask.long.byte 0x10 16.--23. 1. "ready_value,If rb_enable=0 then this field determines the value which is compared to response from the NF memory to the device status command"
newline
hexmask.long.word 0x10 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x10 0. "rb_enable,Selects R/B pin checks (if 1) or status polling mode (if 0). For Multi-LUN operations this bit is ignored and Read Status Enhanced command is send to check LUN status." "0,1"
line.long 0x14 "rdst_ctrl_1,Operation status control register. Controller doesn't apply any implicit checks. so host needs to unmask all status bits that need to be checked to detect error condition"
hexmask.long.byte 0x14 24.--31. 1. "error_mask,This field determines the mask used in comparison of response from the NF memory to the operation status command and status_value"
hexmask.long.byte 0x14 16.--23. 1. "error_value,This field determines the value which is compared to response from the NF memory to the operation status command"
newline
hexmask.long.word 0x14 0.--15. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x18 "lun_status_cmd,Indicates the command to be sent while checking status of the next LUN."
hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x18 0. "lun_stat_sel,This field allow to select command sequence that is used to check LUN status. Allowed values are:" "0,1"
line.long 0x1C "lun_interleaved_cmd,Interleaved commands support."
hexmask.long 0x1C 7.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 6. "program_after_read,This bit informs the controller if the device supports a program operation on a LUN while a Read operation is already ongoing in the other LUN." "0,1"
newline
hexmask.long.byte 0x1C 2.--5. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0.--1. "lun_col_cmd,This field allow to select change read column sequence type that is used for multi-LUN commands:" "0,1,2,3"
line.long 0x20 "lun_addr_offset,Indicates the starting address of next LUN."
hexmask.long 0x20 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x20 0.--4. 1. "lun_addr_offset,Bit in ROW address used for selection of the LUN"
line.long 0x24 "nf_dev_layout,NF device layout."
hexmask.long.byte 0x24 27.--31. 1. "blk_addr_idx,Block address offset - bit index at which block address starts inside the row address. If the page address and block address are continuous inside the row address then block address offset field value is equal to LOG2(PPB)."
rbitfld.long 0x24 24.--26. "Reserved_3,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x24 20.--23. 1. "LN,The number of LUN presents in the device. Up to 8 LUN-s are supported."
rbitfld.long 0x24 17.--19. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24 16. "lun_en,Enables Multi LUN operations" "0,1"
hexmask.long.word 0x24 0.--15. 1. "PPB,Pages Per Block - number of pages in a block."
line.long 0x28 "ecc_config_0,ECC engine configuration register 0."
hexmask.long.tbyte 0x28 11.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x28 8.--10. "corr_str,Correction strength. This field selects correction abilities available for the ECC engine. Correction abilities are coded using binary code starting from the lower values to higher values. Only values supported by the ECC engine are allowed." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x28 5.--7. "Reserved_3,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
bitfld.long 0x28 4. "scrambler_en,This enables scrambler logic in the controller. Scrambler removes the repeated patterns in the data and decreases the chances of read disturbance and program disturbance. Field ignored for the Generic work mode." "0,1"
newline
rbitfld.long 0x28 2.--3. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
bitfld.long 0x28 1. "erase_det_en,Enable erased pages detection mechanism. Field ignored for the Generic work mode." "0,1"
newline
bitfld.long 0x28 0. "ecc_enable,Enable controller ECC check bits generation and correction. Field ignored for the Generic work mode." "0,1"
line.long 0x2C "ecc_config_1,Erase detection config register"
hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x2C 0.--7. 1. "erase_det_lvl,This value informs the ECC logic about the number of zeros inside transferred sector that still allow consider it as Erased. If the number of zeros inside the sector being read is less than the value in this register  an erased sector is.."
line.long 0x30 "device_ctrl,Device control register."
hexmask.long.byte 0x30 24.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
hexmask.long.byte 0x30 16.--23. 1. "pslc_prefix_cmd,The pslc prefix command value. It is valid only when the"
newline
hexmask.long.byte 0x30 12.--15. 1. "Reserved_8,Reserved bitfield added by Magillem"
bitfld.long 0x30 10.--11. "pslc_prefix_sel,Filed selects row address width. Field" "0,1,2,3"
newline
rbitfld.long 0x30 9. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x30 7.--8. "row_addr_width,Filed selects row address width. Field" "0,1,2,3"
newline
bitfld.long 0x30 6. "pslc_prefix_en,Bit used to enable/disable the prefix command sending" "0,1"
bitfld.long 0x30 5. "chrc_wdth,If this bit is cleared then controller" "0,1"
newline
bitfld.long 0x30 4. "time_out_en,If this bit is set then Command Engine" "0,1"
bitfld.long 0x30 3. "cont_on_err,If this bit is cleared and any operation" "0,1"
newline
rbitfld.long 0x30 2. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x30 1. "Reserved,Reserved" "0,1"
newline
bitfld.long 0x30 0. "ce_hold,If this field is set then CE bus state" "0,1"
line.long 0x34 "multiplane_config,Multiplane settings register. The Address part of sequence is described using three symbols: col_addr - it means column address only. row_addr - it means row address only. addr - it means both row and column address"
hexmask.long.byte 0x34 27.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
bitfld.long 0x34 26. "pl_status_en,Field select status probing mechanism:[list] [*] 1'b0 - summary status for all planes is probed using single basic read status command  [*] 1'b1 - separate status for each plane is probed using multiple enhanced read status commands.[/list]" "0,1"
newline
bitfld.long 0x34 25. "last_wr_cmd,Select sequence for the Copyback Write operation:" "0,1"
bitfld.long 0x34 24. "mpl_erase_seq,Select Erase sequence in multiplane work mode:[list] [*] 1'b0 - ONFI sequence 60-row_addr-d1 60-row_addr-d0 [*] 1'b1 - JEDEC sequence 60-row_addr-60-row_addr-d0[/list]" "0,1"
newline
bitfld.long 0x34 21.--23. "mpl_rd_seq,Selects Multiplane read command sequences. The HPNFC controller can send the following sequences:" "0,1,2,3,4,5,6,7"
rbitfld.long 0x34 18.--20. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 16.--17. "mpl_prg_seq,Selects Multiplane program command sequences. If the device has N planes  the values in the field should be as follows based on which sequence the target device expects:" "0,1,2,3"
hexmask.long.byte 0x34 11.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x34 8.--10. "mpl_pl_num,Selects number of planes per" "0,1,2,3,4,5,6,7"
rbitfld.long 0x34 5.--7. "Reserved_3,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 4. "mpl_cpbk_rd_seq,Selects Multiplane copyback read command sequences. The HPNFC controller can send the following sequences:" "0,1"
rbitfld.long 0x34 2.--3. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x34 1. "mpl_wr_en,This bit enables multiplane sequences for write and erase operations." "0,1"
bitfld.long 0x34 0. "mpl_rd_en,This bit enables multiplane sequences for read operations." "0,1"
line.long 0x38 "cache_config,This register contains enable flags for cache operations."
hexmask.long 0x38 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x38 1. "cache_wr_en,This bit enables cache write command sequences support." "0,1"
newline
bitfld.long 0x38 0. "cache_rd_en,This bit enables cache read command sequences support." "0,1"
line.long 0x3C "dma_settings,DMA settings register. It is common register for both Master and Slave interface."
hexmask.long.word 0x3C 18.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x3C 17. "sdma_err_rsp,If this bit is set then ERROR response" "0,1"
newline
bitfld.long 0x3C 16. "OTE,Outstanding transaction enable. It only applies to the master interface  the slave interface will ignore this bit and will accept all incoming transactions." "0,1"
hexmask.long.byte 0x3C 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x3C 0.--7. 1. "burst_sel,Sets the burst used by data DMA for transferring data to/from flash device. The maximum burst size can be calculated as burst_sel+1. This field should be changed only if controller is in IDLE state"
rgroup.long 0x440++0x7
line.long 0x0 "sdma_size,Transferred data block size for the Slave DMA module."
hexmask.long 0x0 0.--31. 1. "sdma_size,Transferred data block size in bytes for the Slave DMA module. Data size is rounded up to the data bus word size."
line.long 0x4 "sdma_trd_num,Thread number associated with transferred data block for the Slave DMA module."
hexmask.long 0x4 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0.--2. "sdma_trd,Thread number associated with transferred data block for the Slave DMA module." "0,1,2,3,4,5,6,7"
group.long 0x448++0x3
line.long 0x0 "time_out,This register configures time out delay"
hexmask.long 0x0 0.--31. 1. "time_out_val,This value is used to initialize the"
rgroup.long 0x44C++0x7
line.long 0x0 "sdma_addr0,This register stores the buffer address in the host memory that is used as a sink/source for the SDMA transfer."
hexmask.long 0x0 0.--31. 1. "sdma_addr_l,The SDMA destination/source address - lower part."
line.long 0x4 "sdma_addr1,This register stores the buffer address in the host memory that is used as a sink/source for the SDMA transfer."
hexmask.long 0x4 0.--31. 1. "sdma_addr_h,The SDMA destination/source address - higher part."
group.long 0x454++0x13
line.long 0x0 "fifo_trigg_level,This register stores the trigger level value for TX FIFO and single package size for the DMA module."
hexmask.long.word 0x0 16.--31. 1. "dma_package_size,Number of 64b data words which are transferred after meting the trig level condition."
hexmask.long.word 0x0 0.--15. 1. "fifo_trigg_lvl,Trigger level in terms of 64b data words."
line.long 0x4 "zq_cal_config,Reserved."
rbitfld.long 0x4 31. "Reserved_6,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x4 30. "Reserved,Reserved" "0,1"
newline
rbitfld.long 0x4 29. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x4 27.--28. "Reserved,Reserved" "0,1,2,3"
newline
bitfld.long 0x4 26. "Reserved,Reserved" "0,1"
bitfld.long 0x4 25. "Reserved,Reserved" "0,1"
newline
rbitfld.long 0x4 24. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
hexmask.long.word 0x4 12.--23. 1. "Reserved,Reserved"
newline
hexmask.long.word 0x4 0.--11. 1. "Reserved,Reserved"
line.long 0x8 "zq_cal_en,Reserved."
hexmask.long.word 0x8 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x8 0.--15. 1. "Reserved,Reserved"
line.long 0xC "long_cal_period,Reserved."
hexmask.long 0xC 0.--31. 1. "Reserved,Reserved."
line.long 0x10 "short_cal_period,Reserved."
hexmask.long 0x10 0.--31. 1. "Reserved,Reserved."
group.long 0x480++0x17
line.long 0x0 "remap_ctrl,This register controls the Remap mechanism."
hexmask.long.byte 0x0 27.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 16.--26. 1. "rec_cnt,Number of records stored in Records Table"
newline
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "rmp_en,Remap Enable. Setting this bit enables the Remap mechanism" "0,1"
line.long 0x4 "remap_mask,Remap mask mechanism."
hexmask.long 0x4 0.--31. 1. "remap_mask,Mask value - utilized to specify range of single remap record"
line.long 0x8 "remap_access,Register utilized to access the Records Table."
hexmask.long.byte 0x8 26.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.word 0x8 16.--25. 1. "rec_rd_idx,For read access this field should be fill with a record number which host wants to read. Indexing starts from 0."
newline
hexmask.long.byte 0x8 12.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 8.--11. 1. "rec_trg,Remap target. This value determines which memory target is bind to current access."
newline
eventfld.long 0x8 7. "rec_di_err,Error while accessing remap table through the registers." "0,1"
hexmask.long.byte 0x8 3.--6. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 1.--2. "rec_actype,Access type: [list] [*]0 - Write single record [*]1 - Read single record [*]2 - Clear all records [*]3 - Reserved[/list]" "0,1,2,3"
bitfld.long 0x8 0. "rec_access,Writing 1 will start accessing the Records Table. Controller will automatically clear this bit when operation is finished" "0,1"
line.long 0xC "remap_log_addr,Register with logical address of the remap record."
hexmask.long 0xC 0.--31. 1. "remap_log_addr,Logical address. Remapping is done from logical to physical address."
line.long 0x10 "remap_phys_addr,Register with physical address of the remap record."
hexmask.long 0x10 0.--31. 1. "remap_phys_addr,Physical address. Remapping is done from logical to physical address."
line.long 0x14 "control_data_ctrl,Register configures control-data part of"
hexmask.long.word 0x14 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x14 0.--15. 1. "control_data_size,Control-data size."
group.long 0x700++0xB
line.long 0x0 "di_control,Register provided to control the data integrity feature."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "di_inj_type,Injection type: 0-one time injection  1-continuous injection." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "di_type,DI type: 0-even  1-odd." "0,1"
newline
bitfld.long 0x0 15. "di_par_rsp_en,Enable error response generation on SFR interface when parity error detected." "0,1"
hexmask.long.word 0x0 2.--14. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "di_crc_en,Enable CRC checking." "0,1"
bitfld.long 0x0 0. "di_parity_en,Enable parity checking." "0,1"
line.long 0x4 "di_inject0,Register provided to control the error injection feature."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--23. 1. "di_inj_ctx_value,Inject error for data of context memory."
newline
bitfld.long 0x4 15. "di_inj_ctx_addr,Inject error for address of context memory." "0,1"
hexmask.long.byte 0x4 10.--14. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 9. "di_inj_desc_rd_addr,Inject error on address for descriptor read." "0,1"
bitfld.long 0x4 8. "di_inj_desc_wr_addr,Inject error on address for descriptor status/sync flag write." "0,1"
newline
hexmask.long.byte 0x4 0.--7. 1. "di_inj_desc_value,Inject error on data for descriptor status/sync flag write."
line.long 0x8 "di_inject1,Register provided to control the error injection feature."
hexmask.long.byte 0x8 24.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 20.--23. 1. "di_inj_reg_value,Inject error for register read value."
newline
rbitfld.long 0x8 19. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x8 18. "di_inj_data_rd_addr,Inject error on address for read data." "0,1"
newline
bitfld.long 0x8 17. "di_inj_data_wr_addr,Inject error on address for write data." "0,1"
bitfld.long 0x8 16. "di_inj_data_wr_crc,Inject CRC error for write data path." "0,1"
newline
hexmask.long.byte 0x8 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 0.--7. 1. "di_inj_data_rd_par,Inject parity error for read data path."
rgroup.long 0x70C++0x3
line.long 0x0 "di_error_reg_addr,Register which contains address of last transaction with incorrect parity detected."
hexmask.long 0x0 0.--31. 1. "di_error_reg_address,Address of last incorrect transaction."
group.long 0x710++0x3
line.long 0x0 "di_inject2,Register provided to control the error injection feature for remap mechanism."
hexmask.long.byte 0x0 26.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 25. "di_inj_dbuff_rd_addr,Inject error for data buffer DPRAM memory (read address)." "0,1"
newline
bitfld.long 0x0 24. "di_inj_dbuff_wr_addr,Inject error for data buffer DPRAM memory (write address)." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 16. "di_inj_rmp_addr,Inject error for Remap SPRAM memory (address)." "0,1"
hexmask.long.byte 0x0 9.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--8. 1. "di_inj_rmp_value,Inject error for Remap SPRAM memory (write data)."
rgroup.long 0x800++0x47
line.long 0x0 "ctrl_version,Register contains release identification number."
hexmask.long.word 0x0 16.--31. 1. "hpnfc_magic_number,IP unique ID number."
hexmask.long.byte 0x0 8.--15. 1. "ctrl_fix,Fixed number (minor revision number)."
newline
hexmask.long.byte 0x0 0.--7. 1. "ctrl_rev,Controller revision number."
line.long 0x4 "ctrl_features_reg,Shows available hardware features of the controller"
bitfld.long 0x4 30.--31. "Reserved_20,Reserved bitfield added by Magillem" "0,1,2,3"
bitfld.long 0x4 29. "nf_16b_supp,Support for 16b NF interface." "0,1"
newline
bitfld.long 0x4 28. "Reserved,Reserved" "0,1"
bitfld.long 0x4 27. "nvddr,Support for NV-DDR (source synchronous) work mode." "0,1"
newline
bitfld.long 0x4 26. "async_supp,Support for asynchronous work mode." "0,1"
bitfld.long 0x4 24.--25. "n_banks,Maximum number of banks supported by hardware. This is an encoded value. [list][*]0 - One bank [*]1 - Two banks [*]2 - Four banks [*]3 - Eight banks[/list]" "0,1,2,3"
newline
bitfld.long 0x4 22.--23. "sfr_intf,SFR interface type (0-AXI4 Lite  1-OCP  2-APB  other values reserved)." "0,1,2,3"
bitfld.long 0x4 21. "dma_data_width,Slave and Master DMA data width:[list] [*]0 - 32bit [*]1 - 64bit[/list]" "0,1"
newline
bitfld.long 0x4 20. "dma_addr_width,Slave and Master DMA address width:[list] [*]0 - 32bit [*]1 - 64bit[/list]" "0,1"
bitfld.long 0x4 18.--19. "dma_intf,DMA interface type (0-AXI4  1-OCP  other values reserved)." "0,1,2,3"
newline
bitfld.long 0x4 17. "ecc_available,Data ECC protection engine present." "0,1"
bitfld.long 0x4 16. "boot_available,Reserved" "0,1"
newline
bitfld.long 0x4 15. "pre_fetch_available,Availability of pre-fetching mechanism." "0,1"
bitfld.long 0x4 14. "di_par_available,Availability of Data Integrity mechanism - parity." "0,1"
newline
bitfld.long 0x4 13. "ext_cmd_cnt,Availability Extended Command Feature. Reflects the maximum number of operations in single PIO command/CDMA descriptor: [list][*]0 - 256 operations [*]1 - 65536 operations[/list]" "0,1"
bitfld.long 0x4 12. "rmp_available,Availability of Remap mechanism." "0,1"
newline
bitfld.long 0x4 11. "ext_status,Availability Extended Status feature." "0,1"
bitfld.long 0x4 10. "control_data,Availability of Control Data feature." "0,1"
newline
bitfld.long 0x4 9. "write_protect,Availability of Write Protect feature." "0,1"
bitfld.long 0x4 8. "di_crc_available,Availability of Data Integrity mechanism - CRC." "0,1"
newline
hexmask.long.byte 0x4 4.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 0.--3. 1. "n_threads,Number of threads available in the controller. The following decoding is used: [list][*]0 - One thread [*]1 - Two threads [*]2 - Four threads [*]3 - Eight threads [*]4 - Sixteen threads [*]5-15 - Reserved[/list]"
line.long 0x8 "manufacturer_id,NAND Flash memory device ID information."
hexmask.long.byte 0x8 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 16.--23. 1. "dId,Device ID"
newline
hexmask.long.byte 0x8 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 0.--7. 1. "mId,Manufacturer ID"
line.long 0xC "nf_device_areas,Device areas settings."
hexmask.long.word 0xC 16.--31. 1. "spare_area_size,Spare area size in bytes for the NF device page"
hexmask.long.word 0xC 0.--15. 1. "main_area_size,Main area size in bytes for the NF device page"
line.long 0x10 "device_params_0,Indicates the device type and the number of LUN-s present in the device."
bitfld.long 0x10 30.--31. "device_type,Indicates if the device is an ONFI- or JEDEC-compliant device." "0,1,2,3"
hexmask.long.byte 0x10 24.--29. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 16.--23. 1. "bits_per_cell,Number of bits per cell."
hexmask.long.byte 0x10 8.--15. 1. "plane_addr_bits,Number of bits used to addressing planes."
newline
hexmask.long.byte 0x10 0.--7. 1. "no_of_luns,Indicates the number of LUN-s present in the NAND flash device."
line.long 0x14 "device_params_1,Device signature register."
hexmask.long.byte 0x14 24.--31. 1. "ReadId_6,6th byte of ReadID command related to Device Signature (ONFI or JEDEC)."
hexmask.long.byte 0x14 16.--23. 1. "ReadId_5,5th byte of ReadID command related to Device Signature (ONFI or JEDEC)."
newline
hexmask.long.byte 0x14 8.--15. 1. "ReadId_4,4th byte of ReadID command related to Device Signature (ONFI or JEDEC)."
hexmask.long.byte 0x14 0.--7. 1. "ReadId_3,3th byte of ReadID command related to Device Signature (ONFI or JEDEC)."
line.long 0x18 "device_features,Features and optional commands supported by the connected ONFI or Toggle device."
hexmask.long.word 0x18 16.--31. 1. "optional_commands,This field is a copy of bytes 8-9 from parameter page ('Optional commands supported')."
hexmask.long.word 0x18 0.--15. 1. "device_features,This field corresponds to bytes 6-7 of parameter page ('Features supported')."
line.long 0x1C "device_blocks_per_lun,Number of blocks per LUN present in the ONFI complaint/Toggle device."
hexmask.long 0x1C 0.--31. 1. "no_of_blocks,Indicates the number of blocks per LUN present in the ONFI complaint/Toggle device."
line.long 0x20 "device_revision,Device revision version (valid for ONFI and TOGGLE device)."
hexmask.long.word 0x20 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x20 0.--15. 1. "revisions,This field is a copy of bytes 4-5 from parameter page ('Revision number')."
line.long 0x24 "onfi_timing_modes_0,Device Timing modes supported by the connected ONFI device (not valid for Toggle mode devices)."
hexmask.long.byte 0x24 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
hexmask.long.byte 0x24 16.--23. 1. "nv_ddr_modes,This field corresponds to byte 141 in parameter page ('NV-DDR timing mode support'). Typically it should be interpreted as follows:[list] [*]Bit 0 - Supports Timing mode 0. [*]Bit 1 - Supports Timing mode 1. [*]Bit 2 - Supports Timing mode.."
newline
hexmask.long.word 0x24 0.--15. 1. "sdr_modes,This field reflects value of bytes 129-130 in parameter page (' SDR timing mode support'). Typically the value of this field should be interpreted as follows:[list] [*]Bit 0 - Supports Timing mode 0. [*]Bit 1 - Supports Timing mode 1. [*]Bit 2.."
line.long 0x28 "onfi_timing_modes_1,Device Timing modes supported by the connected ONFI device (not valid for Toggle mode devices)."
hexmask.long.word 0x28 16.--31. 1. "nv_ddr3_modes,This field contains value of bytes 160-161 from parameter page ('NV-DDR3 timing mode support')."
hexmask.long.word 0x28 0.--15. 1. "nv_ddr2_modes,This field contains concatenated values of bytes 142 and 162 of parameter page ('NV-DDR3 timing mode support'). Typically the values in the field should be interpreted as follows:[list] [*]Bit 0 - Supports Timing mode 0. [*]Bit 1 - Supports.."
line.long 0x2C "onfi_iterlv_op_attr,Interleaved(Multiplane) operation attributes of the connected ONFI device (not valid for Toggle mode devices)."
hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x2C 0.--7. 1. "iterlv_op,Value of this field reflects the value of byte 114 in parameter page ('Multi-plane operation attributes'). Typically the values in the field should be interpreted as follows:[list] [*]Bit 0 - Overlapped/concurrent interleaving support. [*]Bit 1.."
line.long 0x30 "onfi_sync_opt_0,ONFI synchronous device parameters - part 1 (not valid for Toggle mode devices)."
hexmask.long.word 0x30 16.--31. 1. "onfi_tccs_min,The minimum value in (ns) that is required between a change column command and the data transfer from the device (tccs). Value of this field is filled based on bytes 139-140 of parameter page."
hexmask.long.byte 0x30 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x30 0.--7. 1. "nvddr_supp_ft,NV-DDR Features. Value of this field is a copy of byte 143 from parameter page ('NV-DDR features'):[list] [*]Bit 0 - tCAD value to use. [*]Bit 1 - typical capacitance value present. [*]Bit 2 - device supports CLK stopped data input. [*]Bit.."
line.long 0x34 "onfi_sync_opt_1,ONFI synchronous device parameters - part 2 (not valid for Toggle mode devices)."
hexmask.long.byte 0x34 24.--31. 1. "warmup_cycles,Reserved"
hexmask.long.byte 0x34 16.--23. 1. "Reserved,Reserved"
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hexmask.long.byte 0x34 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x34 0.--7. 1. "adv_cmd_supp,ONFI-JEDEC JTG primary advanced command support:[list] [*]Bit 0 - Supports ONFI-JEDEC JTG Random Data Out. [*]Bit 1 - Supports ONFI-JEDEC JTG Multi-plane Page Program. [*]Bit 2 - Supports ONFI-JEDEC JTG Multi-plane Copyback Program. [*]Bit 3.."
line.long 0x38 "bch_cfg_0,BCH Engine identification register 0 - available correction strengths."
hexmask.long.byte 0x38 24.--31. 1. "bch_corr_3,BCH correction capability no. 3 (0 value means unavailable)."
hexmask.long.byte 0x38 16.--23. 1. "bch_corr_2,BCH correction capability no. 2 (0 value means unavailable)."
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hexmask.long.byte 0x38 8.--15. 1. "bch_corr_1,BCH correction capability no. 1 (0 value means unavailable)."
hexmask.long.byte 0x38 0.--7. 1. "bch_corr_0,BCH correction capability no. 0 (0 value means unavailable)."
line.long 0x3C "bch_cfg_1,BCH Engine identification register 1 - available correction strengths."
hexmask.long.byte 0x3C 24.--31. 1. "bch_corr_7,BCH correction capability no. 7 (0 value means unavailable)."
hexmask.long.byte 0x3C 16.--23. 1. "bch_corr_6,BCH correction capability no. 6 (0 value means unavailable)."
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hexmask.long.byte 0x3C 8.--15. 1. "bch_corr_5,BCH correction capability no. 5 (0 value means unavailable)."
hexmask.long.byte 0x3C 0.--7. 1. "bch_corr_4,BCH correction capability no. 4 (0 value means unavailable)."
line.long 0x40 "bch_cfg_2,BCH Engine identification register 2 - available sector sizes."
hexmask.long.word 0x40 16.--31. 1. "bch_sect_1,BCH sector size (in bytes)."
hexmask.long.word 0x40 0.--15. 1. "bch_sect_0,BCH sector size (in bytes)."
line.long 0x44 "bch_cfg_3,BCH Engine identification register 3 - additional information."
hexmask.long.byte 0x44 24.--31. 1. "bch_syndrome_factor,BCH syndrome factor."
hexmask.long.byte 0x44 16.--23. 1. "bch_metadata_size,Max metadata size (in bytes)."
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hexmask.long.byte 0x44 8.--15. 1. "bch_chien_factor,BCH paralleling factor - Chien."
hexmask.long.byte 0x44 0.--7. 1. "bch_brlk_factor,BCH paralleling factor - Berlekamp."
rgroup.long 0x850++0x3
line.long 0x0 "device_features_1,Reserved."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "Reserved,Reserved"
group.long 0x900++0xB
line.long 0x0 "prot_ctrl_0,Control register for the protect mechanism."
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "prot_en_0,Each bit of this field enable protection"
line.long 0x4 "prot_down_0,Register configure protected area address"
hexmask.long 0x4 0.--31. 1. "addr_down_0,Define lower row address limit of the"
line.long 0x8 "prot_up_0,Register configure protected area address"
hexmask.long 0x8 0.--31. 1. "addr_up_0,Define upper row address limit of the"
group.long 0x910++0xB
line.long 0x0 "prot_ctrl_1,Control register for the protect mechanism."
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "prot_en_1,Each bit of this field enable protection"
line.long 0x4 "prot_down_1,Register configure protected area address boundaries."
hexmask.long 0x4 0.--31. 1. "addr_down_1,Define lower row address limit of the"
line.long 0x8 "prot_up_1,Register configure protected area address"
hexmask.long 0x8 0.--31. 1. "addr_up_1,Define upper row address limit of the"
group.long 0x1000++0x3
line.long 0x0 "wp_settings,Write Protect"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "WP,)" "0,1"
rgroup.long 0x1004++0x3
line.long 0x0 "rbn_settings,Ready/Busy# line status. Represents the value of the Ready/Busy# lines after two stage synchronizers due to the asynchronous nature of R/B#."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "Rbn,RBn status"
group.long 0x1008++0x2F
line.long 0x0 "common_settings,Configuration of the Minicontroller."
hexmask.long.byte 0x0 24.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 20.--23. 1. "wr_warmup,Reserved."
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hexmask.long.byte 0x0 16.--19. 1. "rd_warmup,Reserved"
hexmask.long.byte 0x0 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
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bitfld.long 0x0 8. "device_16bit,16 bit device connected to the NAND Flash interface. 16bit devices may have sequences at which the data is transferred on LSB of the data bus. For such sequences this field should be set low." "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
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bitfld.long 0x0 0.--1. "opr_mode,Operation work mode [list]" "0,1,2,3"
line.long 0x4 "skip_bytes_conf,Skip bytes settings."
hexmask.long.word 0x4 16.--31. 1. "marker,A 16bit value that is written in the spare area skip bytes. In SDR 8-bit mode the LSB of this field is used only. In DDR modes all bits are used."
hexmask.long.byte 0x4 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x4 0.--7. 1. "skip_bytes,Number of bytes to skip from offset of block. The bytes are written with the value programmed in the marker register. This register could be potentially used to preserve the bad block marker in the spare area by marking it good. The default.."
line.long 0x8 "skip_bytes_offset,Skip bytes offset settings."
hexmask.long.byte 0x8 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x8 0.--23. 1. "skip_bytes_offset,Offset after which the Minicontroller starts sending the dummy bytes (defined by marker) to the device. After skip bytes the Minicontroller continues to transfer the data. The offset is counted from the beginning of the data transfer."
line.long 0xC "toggle_timings_0,Toggle Mode/NV-DDR2/NV-DDR3 timings configuration."
rbitfld.long 0xC 30.--31. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0xC 24.--29. 1. "tCR,The number of cycles the controller needs to wait after asserting CE# low before it can assert the RE low to the device. The timing value follows tCR. Some devices may define tCR2 timing also. From tCR/tCR2 the bigger value should be written to the.."
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rbitfld.long 0xC 22.--23. "Reserved_3,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0xC 16.--21. 1. "tPRE,The number of clock cycles (nf_clk) the Minicontroller needs to de-assert DQS/RE# to meet the tWPRE/tRPRE time of the toggle NAND device during data input/output cycle."
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rbitfld.long 0xC 14.--15. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0xC 8.--13. 1. "tCDQSS,The number of cycles the controller needs to wait after asserting CE# low before it can assert the DQS low to the device. The timing value follows tCDQSS. Some devices may define the tCD timing also. From tCDQSS/tCD the bigger value should be.."
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rbitfld.long 0xC 6.--7. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0xC 0.--5. 1. "tPSTH,The number of cycles the controller needs to wait after de-asserting CE# (set high) or asserting CLE before it can de-assert the RE# or DQS to the device while read/write data transfer. The timing value follows tRPSTH and tWPSTH. The number.."
line.long 0x10 "toggle_timings_1,Toggle Mode/NV-DDR2/NV-DDR3 timings configuration. Timing tWPST is also valid in NV-DDR mode."
rbitfld.long 0x10 31. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "tCDQSH,The number of clock cycles (nf_clk) the Minicontroller needs to wait after WE# high when issue command at the end of the write data transfer. The timing value follows tCDQSH. The number programmed in this register should be in terms of.."
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rbitfld.long 0x10 22.--23. "Reserved_3,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x10 16.--21. 1. "tCRES,The number of clock cycles (nf_clk) the Minicontroller needs to wait after RE# high (at the end of the read data transfer) before asserting CE# (set low) to the device for new sequence. The timing value follows tCRES. The number programmed in this.."
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rbitfld.long 0x10 14.--15. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x10 8.--13. 1. "tRPST,The number of clock cycles (nf_clk) the Minicontroller needs to wait after stop toggling RE# before de-asserting CE# (set high) or asserting CLE to the device while read data transfer. The timing value follows tRPST. The number programmed in this.."
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rbitfld.long 0x10 6.--7. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x10 0.--5. 1. "tWPST,The number of clock cycles (nf_clk) the Minicontroller needs to wait after stop toggling DQS before de-asserting CE# (set high) or asserting CLE to the device while write data transfer. The timing value follows tWPST. The number programmed in this.."
line.long 0x14 "async_toggle_timings,Toggle Mode/NV-DDR2/NV-DDR3 and SDR timings configuration."
rbitfld.long 0x14 29.--31. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 24.--28. 1. "tRH,The number of clock cycles (nf_clk) the Minicontroller needs to de-assert RE# to meet the tREH (RE# high pulse width) time of the asynchrnonous(SDR) NAND device during command/address/data sequence."
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rbitfld.long 0x14 21.--23. "Reserved_3,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 16.--20. 1. "tRP,The number of clock cycles (nf_clk) the Minicontroller needs to assert RE# to meet the tRP (RE# low pulse width)"
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rbitfld.long 0x14 13.--15. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 8.--12. 1. "tWH,The number of clock cycles (nf_clk) the Minicontroller needs to de-assert WE# to meet the tWH (WE# high pulse width)"
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rbitfld.long 0x14 5.--7. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 0.--4. 1. "tWP,The number of clock cycles (nf_clk) the Minicontroller needs to assert WE# to meet the tWP (WE# low pulse width)"
line.long 0x18 "sync_timings,Source Synchronous/NV-DDR timings configuration."
hexmask.long.word 0x18 22.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
hexmask.long.byte 0x18 16.--21. 1. "tCKWR,Timing parameter between end of the data output cycle and de-asserting the rebar signal . The timing value follows tCKWR. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to.."
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rbitfld.long 0x18 14.--15. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x18 8.--13. 1. "tWRCK,Timing parameter between driving the rebar signal low and start data output cycle. The timing value follows tWRCK. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy.."
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rbitfld.long 0x18 6.--7. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x18 0.--5. 1. "tCAD,Timing parameter between command  address and data cycles in synchronous mode. The timing value follows tCAD. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy the time."
line.long 0x1C "timings0,Global timings configuration - register 0."
hexmask.long.byte 0x1C 24.--31. 1. "tADL,Signifies the number of clock cycles that should be introduced between an address to a data input cycle. The timing value follows tADL. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be.."
hexmask.long.byte 0x1C 16.--23. 1. "tCCS,Timing parameter for minimum change column setup time. The timing value follows tCCS (tWHR2 for Toggle DDR devices)."
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hexmask.long.byte 0x1C 8.--15. 1. "tWHR,Timing parameter between we high to re low. The timing value follows tWHR. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy the time."
hexmask.long.byte 0x1C 0.--7. 1. "tRHW,Timing parameter between re high to we low. The timing value follows tRHW. The number programmed in this register should be in terms of Minicontroller clock cycles (nf_clk) that would be required to satisfy the time."
line.long 0x20 "timings1,Global timings configuration - register 1."
hexmask.long.byte 0x20 24.--31. 1. "tRHZ,Timing parameter between re high to re low for the next bank. The timing value follows tRHZ."
hexmask.long.byte 0x20 16.--23. 1. "tWB,)"
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hexmask.long.byte 0x20 8.--15. 1. "tCWAW,Signifies the number of Minicontroller clock cycles (nf_clk) that should be introduced between the command cycle of a random data input command to the address cycle of the random data input command. The timing value follows tCWAW."
hexmask.long.byte 0x20 0.--7. 1. "tVDLY,Signifies the number of Minicontroller clock cycles (nf_clk) that should be introduced after a volume select command before de-asserting the CE or before sending a command to the new volume. The timing value follows tVDLY."
line.long 0x24 "timings2,Global timings configuration - register 2."
hexmask.long.byte 0x24 26.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
hexmask.long.word 0x24 16.--25. 1. "tFEAT,Signifies the number of Minicontroller clock cycles (nf_clk) that should be introduced after a Set Features command and Reset command (since this command change the work mode of the NAND Flash device). For most devices this register refers to.."
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rbitfld.long 0x24 14.--15. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x24 8.--13. 1. "CS_hold_time,Number of Minicontroller clock cycles (nf_clk) required for meeting chip select high time. This register refers to device timing parameter tCEH. Some legacy devices may have a tWHC (WE# high to CE# low) timing requirement. To meet this.."
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rbitfld.long 0x24 6.--7. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x24 0.--5. 1. "CS_setup_time,Number of Minicontroller clock cycles (nf_clk) required for meeting chip select setup time."
line.long 0x28 "dll_phy_update_cnt,Configuration of the resynchronization of slave DLL of PHY."
hexmask.long 0x28 0.--31. 1. "resync_cnt,This field defines the time interval (in terms of Minicontroller clock cycles (nf_clk)) to send an update"
line.long 0x2C "dll_phy_ctrl,Configuration of the resynchronization of slave DLL of PHY."
hexmask.long.byte 0x2C 27.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
rbitfld.long 0x2C 26. "dll_lock_done,This signal is an equivalent of the dfi_init_complete. Refer to the DLL PHY user guide for more details on this signal." "0,1"
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bitfld.long 0x2C 25. "dfi_ctrlupd_req,Signal to resynchronize the DLLs and read and write FIFO pointers. To send the update request to the PHY  the host must first set this field high then wait until this bit is cleared." "0,1"
bitfld.long 0x2C 24. "dll_rst_n,Signal to reset the DLLs of the PHY and start searching for lock again." "0,1"
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hexmask.long.byte 0x2C 18.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x2C 17. "extended_wr_mode,Information to controller and PHY that the WE# is in extended mode. Timing of the WE# signal is controlled by the tWP and tWH timing parameters." "0,1"
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bitfld.long 0x2C 16. "extended_rd_mode,Information to controller and PHY that the RE# is in extended mode. Timing of the RE# signal is controlled by the tRP and tRH timing parameters." "0,1"
hexmask.long.byte 0x2C 12.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x2C 8.--11. 1. "resync_high_wait_cnt,This field defines the number of Minicontroller clock cycles (nf_clk) for which the DLL update request (dfi_ctrlupd_req) has to be asserted  to resynchronize the DLLs and read and write FIFO pointers."
hexmask.long.byte 0x2C 0.--7. 1. "resync_idle_cnt,This field defines the wait time(in terms of Minicontroller clock cycles (nf_clk)) between the de-assertion of the DLL update request (dfi_ctrlupd_req) and resuming traffic to the PHY"
group.long 0x2000++0x17
line.long 0x0 "phy_dq_timing_reg,This register controls the DQ related timing."
bitfld.long 0x0 31. "io_mask_always_on,Defines if the IO mask for DATA/CMD is always enabled." "0,1"
rbitfld.long 0x0 30. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x0 27.--29. "io_mask_end,Adjusts the ending point of the DQ/CMD pad input mask enable. Defines the delay after dfi_wrdata_en/dfi_wrcmd_en goes high when the mask is disabled (data/cmd are blocked and 1'b1 are passed to PHY)." "0,1,2,3,4,5,6,7"
bitfld.long 0x0 24.--26. "io_mask_start,Adjusts the starting point of the DQ/CMD pad input mask enable. Defines the delay after dfi_wrdata_en/dfi_wrcmd_en goes low when the mask is enabled (data/cmd are passed to PHY)." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 16.--23. 1. "data_clkperiod_delay,Defines additional latency on the write datapath. It also adds a clock cycle delay for the data OE path which is equivalent of adding 2 to the data_select_oe_end and data_select_oe_start."
hexmask.long.byte 0x0 12.--15. 1. "data_select_tsel_start,Defines the DQ pad dynamic termination select enable time. Larger values add greater delay to when tsel turns on. Each bit changes the output enable time by a 1/2 cycle resolution."
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hexmask.long.byte 0x0 8.--11. 1. "data_select_tsel_end,Defines the DQ pad dynamic termination select disable time. Larger values increase the delay to when tsel turns off. Each bit changes the output enable time by a 1/2 cycle resolution."
rbitfld.long 0x0 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x0 4.--6. "data_select_oe_start,Adjusts the starting point of the DQ pad output enable window. Lower numbers pull the rising edge earlier in time and larger numbers cause the rising edge to be delayed. Each bit changes the output enable time by a 1/2 cycle.." "0,1,2,3,4,5,6,7"
rbitfld.long 0x0 3. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x0 0.--2. "data_select_oe_end,Adjusts the ending point of the DQ pad output enable window. Lower numbers pull the falling edge earlier in time and larger numbers" "0,1,2,3,4,5,6,7"
line.long 0x4 "phy_dqs_timing_reg,This register controls the DQS related timing."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_10,Reserved bitfield added by Magillem"
bitfld.long 0x4 23. "dqs_clkperiod_delay,Defines additional latency on the write DQS path. It also adds a clock cycle delay for the dqs OE path which is equivalent of adding 2 to the dqs_select_oe_end and dqs_select_oe_start." "0,1"
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bitfld.long 0x4 22. "use_ext_lpbk_dqs,This bit is used in conjunction with bits 21 and 20 to control how read data is sampled by the PHY" "0,1"
bitfld.long 0x4 21. "use_lpbk_dqs,This bit is used in conjunction with bits 22 and 20 to control how read data is sampled by the PHY." "0,1"
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bitfld.long 0x4 20. "use_phony_dqs,Bit to choose lpbk_dqs or phony DQS (generated in the control slice logic) or DQS from the device to capture data for reads. [list] [*]0 - Use DQS from device for data capture.[*]1 - Use phony DQS or lpbk_dqs for data capture. Bit 21 of the.." "0,1"
bitfld.long 0x4 19. "use_phony_dqs_cmd,Bit to choose phony DQS (or lpbk_dqs) from the control slice logic or DQS from the device to capture command data for reads. [list] [*]0 - Use DQS from device for command data capture.[*]1 - Use phony DQS or lpbk_dqs for command data.." "0,1"
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rbitfld.long 0x4 17.--18. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
bitfld.long 0x4 16. "phony_dqs_sel,If this bit is cleared the phony_dqs is synchronous with rising edge of the clk_phy before sending to the entry flops. If this bit is set high the phony_dqs is synchronous with falling edge of clk_phy before sending to the entry flops." "0,1"
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hexmask.long.byte 0x4 12.--15. 1. "dqs_select_tsel_start,Defines the DQ pad dynamic termination select enable time. Larger values add greater delay to when tsel turns on. Each bit changes the output enable time by a 1/2 cycle resolution."
hexmask.long.byte 0x4 8.--11. 1. "dqs_select_tsel_end,Defines the DQ pad dynamic termination select disable time. Larger values increase the delay to when tsel turns off. Each bit changes the output enable time by a 1/2 cycle resolution."
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hexmask.long.byte 0x4 4.--7. 1. "dqs_select_oe_start,Adjusts the starting point of the DQS pad output enable window. Lower numbers pull the rising edge earlier in time and larger numbers cause the rising edge to be delayed. Each bit changes the output enable time by a 1/2 cycle.."
hexmask.long.byte 0x4 0.--3. 1. "dqs_select_oe_end,Adjusts the ending point of the DQS pad output enable window. Lower numbers pull the falling edge earlier in time and larger numbers cause the falling edge to be delayed. Each bit changes the output enable time by a 1/2 cycle.."
line.long 0x8 "phy_gate_lpbk_ctrl_reg,This register controls the gate and loopback control related timing."
bitfld.long 0x8 31. "sync_method,Defines the method of transfering the data from DQS domain flops to the clk_phy clock domain." "0,1"
bitfld.long 0x8 30. "sw_dqs_phase_bypass,[list]" "0,1"
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bitfld.long 0x8 29. "en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x8 28. "sw_half_cycle_shift,[list]" "0,1"
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bitfld.long 0x8 25.--27. "param_phase_detect_sel_oe,DLL Phase Detect Selector for DQS OE generation to handle the clock domain crossing between the clock and clk_wrdqs signal. Selects the number" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x8 19.--24. 1. "rd_del_sel,Defines the read data delay. Holds the number of cycles to delay the dfi_rddata_en signal prior to enabling the read FIFO. After this delay  the read pointers begin incrementing the read FIFO."
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bitfld.long 0x8 18. "underrun_suppress,This field turns off the generation of the underrun signal when 'sync_method' is set high." "0,1"
rbitfld.long 0x8 17. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x8 16. "rd_del_sel_empty,Defines the read data delay for the empty signal generated based on the incoming DQS strobes. For zero delay the data are passed from entry flops to the iodatain* flops one clock cycle after the !empty signals is asserted." "0,1"
bitfld.long 0x8 13.--15. "lpbk_err_check_timing,Sets the cycle delay between the LFSR and loopback error check logic to ensure that the LFSR sourced data and data being looped back arrive at the same clock cycle for comparison. This value is related to the rd_del_sel field  and.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 12. "lpbk_fail_muxsel,Selects data output type for phy_obs_reg_0[23:8]. [list][*]0 = Return the expected data. [*]1 = Return the actual data.[/list]" "0,1"
bitfld.long 0x8 10.--11. "loopback_control,Loopback control. [list][*]0 = Normal Operation Mode. [*]1 = lpbk_start; Enables loopback write mode. [*]2 = lpbk_stop; Stop loopback to check error register. [*]3 = clear; Clear loopback registers.[/list]" "0,1,2,3"
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bitfld.long 0x8 9. "lpbk_internal,Controls the loopback read multiplexer. [list][*]0 = External Loopback. [*]1 = Internal loopback.[/list]" "0,1"
bitfld.long 0x8 8. "lpbk_en,Controls internal write multiplexer. [list][*]0 = Normal Operation. [*]1 = Enable loopback.[/list]" "0,1"
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rbitfld.long 0x8 7. "Reserved_3,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x8 6. "gate_cfg_always_on,This parameter cause the gate to be always on." "0,1"
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bitfld.long 0x8 4.--5. "gate_cfg_close,Normally the gate is closing when all bits of dfi_cebar are high or when dfi_rd_pre_post_amble and rebar_dfi are high. This parameter allows to extend the closing of the DQS gate. Recommended value is zero." "0,1,2,3"
hexmask.long.byte 0x8 0.--3. 1. "gate_cfg,Coarse adjust of gate open time. This value is the number of cycles to delay the dfi_rddata_en signal prior to opening the gate in full cycle increments. Decreasing this value pulls the gate earlier in time. This field should be programmed such.."
line.long 0xC "phy_dll_master_ctrl_reg,This register holds the control for the Master DLL logic."
hexmask.long.byte 0xC 24.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0xC 23. "param_dll_bypass_mode,DLL bypass mode control. Controls the bypass mode of the master and slave DLLs. The param_dll_bypass_mode is intended to be used only for debug. [list][*]0 - Normal operational mode. DLL functioning in normal mode of operation where.." "0,1"
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bitfld.long 0xC 20.--22. "param_phase_detect_sel,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7"
rbitfld.long 0xC 19. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0xC 16.--18. "param_dll_lock_num,Holds the number of consecutive increment or decrement indications that will trigger an unlock condition and increment the dll_unlock_cnt field (bits [7:3]) and either the lock_dec_dbg (bits [23:16]) or lock_inc_dbg (bits [31:24]).." "0,1,2,3,4,5,6,7"
hexmask.long.byte 0xC 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.byte 0xC 0.--7. 1. "param_dll_start_point,This value is the initial delay value for the DLL. This value is also used as the increment value if the initial value is less than a half-clock cycle. This field should be set such that it is not greater than 7/8ths of a clock.."
line.long 0x10 "phy_dll_slave_ctrl_reg,This register holds the control for the slave DLL logic."
hexmask.long.byte 0x10 24.--31. 1. "read_dqs_cmd_delay,Controls the read command DQS delay which adjusts the timing in 1/256th of the clock period when in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements."
hexmask.long.byte 0x10 16.--23. 1. "clk_wrdqs_delay,Controls the clk_wrdqs delay line which adjusts the write DQS timing in 1/256th steps of the clock period in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements."
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hexmask.long.byte 0x10 8.--15. 1. "clk_wr_delay,Controls the clk_wr delay line which adjusts the write DQ bit timing in 1/256th steps of the clock period in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements."
hexmask.long.byte 0x10 0.--7. 1. "read_dqs_delay,Controls the read DQS delay which adjusts the timing in 1/256th of the clock period when in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements."
line.long 0x14 "phy_ie_timing_reg,This register controls the DQS related timing."
hexmask.long.word 0x14 21.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x14 20. "ie_always_on,Forces the input enable(s) to be on always." "0,1"
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rbitfld.long 0x14 19. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x14 16.--18. "dq_ie_start,Define the start position for the DQ input enable." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x14 15. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x14 12.--14. "dq_ie_stop,Define the stop position for the DQ input enable." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x14 11. "Reserved_3,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x14 8.--10. "dqs_ie_start,Define the start position for the DQS input enable." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x14 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x14 4.--6. "dqs_ie_stop,Define the stop position for the DQS input enable." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x14 0.--3. 1. "rddata_en_ie_dly,Specifies the number of clocks of delay for the dfi_rddata_en signal to line it up with the true (normal) DFI read data position. The MC must deliver an early version of the read data enable to allow time for the input pads to turn on.."
rgroup.long 0x2018++0xF
line.long 0x0 "phy_obs_reg_0,This register holds the following observable points in the PHY."
hexmask.long.byte 0x0 28.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 27. "dqs_cmd_overflow,CMD Status signal to indicate that the logic gate was closed too late" "0,1"
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bitfld.long 0x0 26. "dqs_cmd_underrun,CMD Status signal to indicate that the logic gate had to" "0,1"
bitfld.long 0x0 25. "dqs_overflow,Status signal to indicate that the logic gate was closed too late" "0,1"
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bitfld.long 0x0 24. "dqs_underrun,Status signal to indicate that the logic gate had to" "0,1"
hexmask.long.word 0x0 8.--23. 1. "lpbk_dq_data,If errors are encountered in loopback test this field reports the actual data or the expected data  depending on the setting of the phy_gate_lpbk_ctrl_reg [12] parameter bit. This field is not clear by the clear state of the loopback. If.."
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hexmask.long.byte 0x0 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0.--1. "lpbk_status,Loopback Status [list] [*] Bit0 - lpbk start; Defines the status of the loopback mode. 0 = Not in loopback mode; 1 = In loopback mode. [*] Bit1 - lpbk status; Defines the status of the loopback mode. 0 = Last Loopback test had no errors; 1 =.." "0: Last Loopback test had no errors,1: Last loopback test contained data errors,?,?"
line.long 0x4 "phy_dll_obs_reg_0,This register holds the following observable points in the PHY."
hexmask.long.byte 0x4 24.--31. 1. "lock_inc_dbg,Holds the state of the cumulative dll_lock_inc register when the dll_unlock_cnt field(bits [7:3]) of this parameter was triggered to increment or was last saturated at a value of 0x1f."
hexmask.long.byte 0x4 16.--23. 1. "lock_dec_dbg,Holds the state of the cumulative dll_lock_dec register when the dll_unlock_cnt field(bits [7:3]) of this parameter was triggered to decrement or was last saturated at a value of 0x1f."
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hexmask.long.byte 0x4 8.--15. 1. "dll_lock_value,Reports the number of delay elements that the DLL has determined for lock in either full clock or half clock mode. In full clock mode  this value equals the number of delay elements in one cycle. In half clock mode  this value equals the.."
hexmask.long.byte 0x4 3.--7. 1. "dll_unlock_cnt,Reports the number of times that the master DLL consecutive increment or decrement value programmed into the param_dll_lock_num field (bits [18:16]) of the phy_dll_master_ctrl_reg register has been triggered. The dll_unlock_cnt will.."
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bitfld.long 0x4 1.--2. "dll_locked_mode,Indicates status of DLL. Defines the mode in which the DLL has achieved the lock." "0,1,2,3"
bitfld.long 0x4 0. "dll_lock,Indicates status of DLL. It indicates the DLL locking when the DLL lock logic found (not inc AND not dec) OR (an inc then dec) OR (a dec then inc). When param_dll_start_point is set smaller than half clock period the first found (a dec then inc).." "0,1"
line.long 0x8 "phy_dll_obs_reg_1,This register holds the following observable points in the PHY."
hexmask.long.byte 0x8 24.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 16.--23. 1. "decoder_out_wr,Holds the encoded value for the clk_wr delay line for this slice."
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hexmask.long.byte 0x8 8.--15. 1. "decoder_out_rd_cmd,Holds the encoded value for the CMD read delay line for this slice."
hexmask.long.byte 0x8 0.--7. 1. "decoder_out_rd,Holds the encoded value for the read delay line for this slice."
line.long 0xC "phy_dll_obs_reg_2,This register holds the following observable points in the PHY."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0xC 0.--7. 1. "decoder_out_wrdqs,Holds the encoded value for the clk_wrdqs delay line for this slice."
group.long 0x2028++0x17
line.long 0x0 "phy_static_togg_reg,This register controls the static aging feature of the PHY."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "read_dqs_togg_enable,Enables the toggling for the active part of the read_dqs delay line in idle state." "0,1"
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hexmask.long.byte 0x0 20.--23. 1. "static_togg_enable,Control to enable the toggle signal during static activity."
rbitfld.long 0x0 17.--19. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 16. "static_togg_global_enable,Global control to enable the toggle signal during static activity." "0,1"
hexmask.long.word 0x0 0.--15. 1. "static_tog_clk_div,Clock divider to create toggle signal."
line.long 0x4 "phy_wr_deskew_reg,This register holds the values of delay of each DQ bit on the write path."
hexmask.long.byte 0x4 28.--31. 1. "wr_dq7_deskew_delay,Deskew delay for DQ bit 7."
hexmask.long.byte 0x4 24.--27. 1. "wr_dq6_deskew_delay,Deskew delay for DQ bit 6."
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hexmask.long.byte 0x4 20.--23. 1. "wr_dq5_deskew_delay,Deskew delay for DQ bit 5."
hexmask.long.byte 0x4 16.--19. 1. "wr_dq4_deskew_delay,Deskew delay for DQ bit 4."
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hexmask.long.byte 0x4 12.--15. 1. "wr_dq3_deskew_delay,Deskew delay for DQ bit 3."
hexmask.long.byte 0x4 8.--11. 1. "wr_dq2_deskew_delay,Deskew delay for DQ bit 2."
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hexmask.long.byte 0x4 4.--7. 1. "wr_dq1_deskew_delay,Deskew delay for DQ bit 1."
hexmask.long.byte 0x4 0.--3. 1. "wr_dq0_deskew_delay,Deskew delay for DQ bit 0."
line.long 0x8 "phy_wr_rd_deskew_cmd_reg,This register holds the values of delay of CMD bit on the write and read path as well as the values of phase detect block for CMD bit on the write path."
hexmask.long.byte 0x8 28.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 24.--27. 1. "rd_cmd_deskew_delay,Deskew delay for CMD signal."
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hexmask.long.byte 0x8 17.--23. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "cmd_clkperiod_delay,Defines additional latency on the CMD signal." "0,1"
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rbitfld.long 0x8 15. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x8 14. "cmd_sw_dq_phase_bypass,[list]" "0,1"
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bitfld.long 0x8 13. "cmd_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x8 12. "cmd_sw_half_cycle_shift,[list]" "0,1"
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rbitfld.long 0x8 11. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x8 8.--10. "cmd_phase_detect_sel,DLL Phase Detect Selector for CMD generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 4.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 0.--3. 1. "wr_cmd_deskew_delay,Deskew delay for CMD signal"
line.long 0xC "phy_wr_deskew_pd_ctrl_0_reg,This register holds the values of phase detect block for each DQ bit on the write path."
rbitfld.long 0xC 31. "Reserved_16,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 30. "dq3_sw_dq_phase_bypass,[list]" "0,1"
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bitfld.long 0xC 29. "dq3_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0xC 28. "dq3_sw_half_cycle_shift,[list]" "0,1"
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rbitfld.long 0xC 27. "Reserved_13,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 24.--26. "dq3_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0xC 23. "Reserved_12,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 22. "dq2_sw_dq_phase_bypass,[list]" "0,1"
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bitfld.long 0xC 21. "dq2_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0xC 20. "dq2_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0xC 19. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 16.--18. "dq2_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0xC 15. "Reserved_8,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 14. "dq1_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0xC 13. "dq1_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0xC 12. "dq1_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0xC 11. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 8.--10. "dq1_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0xC 7. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 6. "dq0_sw_dq_phase_bypass,[list]" "0,1"
newline
bitfld.long 0xC 5. "dq0_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0xC 4. "dq0_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0xC 3. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 0.--2. "dq0_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
line.long 0x10 "phy_wr_deskew_pd_ctrl_1_reg,This register holds the values of phase detect block for each DQ bit on the write path."
rbitfld.long 0x10 31. "Reserved_16,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 30. "dq7_sw_dq_phase_bypass,[list]" "0,1"
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bitfld.long 0x10 29. "dq7_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x10 28. "dq7_sw_half_cycle_shift,[list]" "0,1"
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rbitfld.long 0x10 27. "Reserved_13,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 24.--26. "dq7_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 23. "Reserved_12,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 22. "dq6_sw_dq_phase_bypass,[list]" "0,1"
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bitfld.long 0x10 21. "dq6_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x10 20. "dq6_sw_half_cycle_shift,[list]" "0,1"
newline
rbitfld.long 0x10 19. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 16.--18. "dq6_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x10 15. "Reserved_8,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 14. "dq5_sw_dq_phase_bypass,[list]" "0,1"
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bitfld.long 0x10 13. "dq5_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x10 12. "dq5_sw_half_cycle_shift,[list]" "0,1"
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rbitfld.long 0x10 11. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 8.--10. "dq5_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x10 7. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 6. "dq4_sw_dq_phase_bypass,[list]" "0,1"
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bitfld.long 0x10 5. "dq4_en_sw_half_cycle,Enables the software" "0,1"
bitfld.long 0x10 4. "dq4_sw_half_cycle_shift,[list]" "0,1"
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rbitfld.long 0x10 3. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 0.--2. "dq4_phase_detect_sel,DLL Phase Detect Selector for DQ generation to handle the clock domain crossing between the clock and clk_wr signal. Selects the number" "0,1,2,3,4,5,6,7"
line.long 0x14 "phy_rd_deskew_reg,This register holds the values of delay of each DQ bit on the read path."
hexmask.long.byte 0x14 28.--31. 1. "rd_dq7_deskew_delay,Deskew delay for DQ bit 7."
hexmask.long.byte 0x14 24.--27. 1. "rd_dq6_deskew_delay,Deskew delay for DQ bit 6."
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hexmask.long.byte 0x14 20.--23. 1. "rd_dq5_deskew_delay,Deskew delay for DQ bit 5."
hexmask.long.byte 0x14 16.--19. 1. "rd_dq4_deskew_delay,Deskew delay for DQ bit 4."
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hexmask.long.byte 0x14 12.--15. 1. "rd_dq3_deskew_delay,Deskew delay for DQ bit 3."
hexmask.long.byte 0x14 8.--11. 1. "rd_dq2_deskew_delay,Deskew delay for DQ bit 2."
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hexmask.long.byte 0x14 4.--7. 1. "rd_dq1_deskew_delay,Deskew delay for DQ bit 1."
hexmask.long.byte 0x14 0.--3. 1. "rd_dq0_deskew_delay,Deskew delay for DQ bit 0."
rgroup.long 0x2070++0x7
line.long 0x0 "phy_version_reg,This register contains release identification number."
hexmask.long.word 0x0 16.--31. 1. "combo_phy_magic_number,Magic number."
hexmask.long.byte 0x0 8.--15. 1. "phy_fix,Fixed number (minor revision number)."
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hexmask.long.byte 0x0 0.--7. 1. "phy_rev,PHY revision number."
line.long 0x4 "phy_features_reg,This register shows available hardware features."
hexmask.long.word 0x4 16.--31. 1. "Reserved_15,Reserved bitfield added by Magillem"
bitfld.long 0x4 15. "asf_sup,Support for Automotive Safety Feature." "0,1"
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bitfld.long 0x4 14. "pll_sup,Support for PLL." "0,1"
bitfld.long 0x4 13. "jtag_sup,Support for JTAG muxes." "0,1"
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bitfld.long 0x4 12. "ext_lpbk_dqs,Support for external LPBK_DQS io pad." "0,1"
bitfld.long 0x4 11. "reg_intf,SFR interface type. This is an encoded value. [list][*]0 - DFI. [*]1 - APB.[/list]" "0,1"
newline
bitfld.long 0x4 10. "per_bit_deskew,Support for per-bit deskew." "0,1"
bitfld.long 0x4 9. "dfi_clock_ratio,Support for clock ratio on DFI interface. This is an encoded value. [list][*]0 - 1:1 [*]1 - 1:2 [/list]" "?,1: 2 [/list]"
newline
bitfld.long 0x4 8. "aging,Support for aging in delay lines." "0,1"
bitfld.long 0x4 7. "dll_tap_num,Number of taps in delay line. This is an encoded value. [list][*]0 - 128. [*]1 - 256. [/list]" "0,1"
newline
bitfld.long 0x4 5.--6. "bank_num,Maximum number of banks supported by hardware. This is an encoded value. [list][*]0 - One bank. [*]1 - Two banks. [*]2 - Four banks. [*]3 - Eight banks.[/list]" "0,1,2,3"
bitfld.long 0x4 4. "sd_emmc,Support for SD/eMMC." "0,1"
newline
bitfld.long 0x4 3. "Reserved,Reserved." "0,1"
bitfld.long 0x4 2. "sdr_16bit,Support for 16bit in ONFI SDR work mode." "0,1"
newline
bitfld.long 0x4 1. "Reserved,Reserved." "0,1"
bitfld.long 0x4 0. "Reserved,Reserved." "0,1"
group.long 0x2080++0xF
line.long 0x0 "phy_ctrl_reg,This register handles the global control settings for the PHY."
hexmask.long.word 0x0 22.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 21. "pu_pd_polarity,Defines the polarity of the ALE port that in SD works as pull-up/pull-down signal for bit 2 of the DATA." "0,1"
newline
bitfld.long 0x0 20. "low_freq_sel,If this field is set high the DFI interface is synchronous to the falling edge of the clock" "0,1"
hexmask.long.byte 0x0 15.--19. 1. "Reserved_3,Reserved bitfield added by Magillem"
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bitfld.long 0x0 14. "sdr_dqs_value,The value that should be driven on the DQS pin while SDR operations are in progress. Please note that in the DDR modes of operations  the command and address cycles are still in SDR mode. This field informs the PHY of the value to be driven.." "0,1"
hexmask.long.byte 0x0 10.--13. 1. "Reserved_2,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x0 4.--9. 1. "phony_dqs_timing,The timing of assertion of phony DQS to the data slices. If the extended_read_mode is disabled the value should be zero. If the extended_read_mode is enabled the value should match the width of the rebar pulse in terms of clock PHY clock.."
rbitfld.long 0x0 1.--3. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "ctrl_clkperiod_delay,Defines additional latency on the control signals ALE/CLE/WE/RE/CE/WP." "0,1"
line.long 0x4 "phy_tsel_reg,This register handles the global control settings for the termination selects for reads."
hexmask.long.byte 0x4 24.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 20.--23. 1. "tsel_off_value_data,Termination select off value for the data."
newline
hexmask.long.byte 0x4 16.--19. 1. "tsel_rd_value_data,Termination select read value for the data."
hexmask.long.byte 0x4 12.--15. 1. "tsel_off_value_dqs,Termination select off value for the data strobe."
newline
hexmask.long.byte 0x4 8.--11. 1. "tsel_rd_value_dqs,Termination select read value for the data strobe."
hexmask.long.byte 0x4 0.--7. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x8 "phy_gpio_ctrl_0,Reserved."
hexmask.long 0x8 0.--31. 1. "Reserved,Reserved."
line.long 0xC "phy_gpio_ctrl_1,Reserved."
hexmask.long 0xC 0.--31. 1. "Reserved,Reserved."
rgroup.long 0x2090++0x7
line.long 0x0 "phy_gpio_status_0,Reserved."
hexmask.long 0x0 0.--31. 1. "reserved,Reserved."
line.long 0x4 "phy_gpio_status_1,Reserved."
hexmask.long 0x4 0.--31. 1. "reserved,Reserved."
tree.end
tree "NOC (Network-on-Chip)"
base ad:0x0
tree "NOC_FW_L4_PER"
base ad:0x10D21000
group.long 0x0++0x3
line.long 0x0 "nand_register,Per-Master Security bit for nand register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to nand_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to nand_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to nand_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0xC++0x7
line.long 0x0 "usb0_register,Per-Master Security bit for usb0_register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to usb0_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to usb0_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to usb0_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "usb1_register,Per-Master Security bit for usb1_register"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to usb1_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to usb1_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x4 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to usb1_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x1C++0x1B
line.long 0x0 "spi_master0,Per-Master Security bit for spi_master0"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to spi_master0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to spi_master0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "dmam1,Security bit configuration for transactions from dmam1 to spi_master0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 8. "dma,Security bit configuration for transactions from dma to spi_master0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to spi_master0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "spi_master1,Per-Master Security bit for spi_master1"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to spi_master1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to spi_master1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 9. "dmam1,Security bit configuration for transactions from dmam1 to spi_master1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 8. "dma,Security bit configuration for transactions from dma to spi_master1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to spi_master1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "spi_slave0,Per-Master Security bit for spi_slave0"
hexmask.long.byte 0x8 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to spi_slave0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to spi_slave0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x8 9. "dmam1,Security bit configuration for transactions from dmam1 to spi_slave0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 8. "dma,Security bit configuration for transactions from dma to spi_slave0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to spi_slave0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "spi_slave1,Per-Master Security bit for spi_slave1"
hexmask.long.byte 0xC 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to spi_slave1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to spi_slave1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0xC 9. "dmam1,Security bit configuration for transactions from dmam1 to spi_slave1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 8. "dma,Security bit configuration for transactions from dma to spi_slave1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to spi_slave1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x10 "emac0,Per-Master Security bit for emac0"
hexmask.long.byte 0x10 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x10 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x10 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x10 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x10 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x10 0. "mpu,Security bit configuration for transactions from mpu to emac0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x14 "emac1,Per-Master Security bit for emac1"
hexmask.long.byte 0x14 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x14 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x14 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "mpu,Security bit configuration for transactions from mpu to emac1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x18 "emac2,Per-Master Security bit for emac2"
hexmask.long.byte 0x18 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x18 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x18 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x18 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x18 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x18 0. "mpu,Security bit configuration for transactions from mpu to emac2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x40++0xB
line.long 0x0 "sdmmc,Per-Master Security bit for sdmmc"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to sdmmc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to sdmmc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to sdmmc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "gpio0,Per-Master Security bit for gpio0"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to gpio0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to gpio0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 9. "dmam1,Security bit configuration for transactions from dmam1 to gpio0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 8. "dma,Security bit configuration for transactions from dma to gpio0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to gpio0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "gpio1,Per-Master Security bit for gpio1"
hexmask.long.byte 0x8 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to gpio1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to gpio1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x8 9. "dmam1,Security bit configuration for transactions from dmam1 to gpio1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 8. "dma,Security bit configuration for transactions from dma to gpio1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to gpio1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x50++0x3B
line.long 0x0 "i2c0,Per-Master Security bit for i2c0"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to i2c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i2c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "dmam1,Security bit configuration for transactions from dmam1 to i2c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 8. "dma,Security bit configuration for transactions from dma to i2c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to i2c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "i2c1,Per-Master Security bit for i2c1"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to i2c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i2c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 9. "dmam1,Security bit configuration for transactions from dmam1 to i2c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x4 8. "dma,Security bit configuration for transactions from dma to i2c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to i2c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "i2c2,Per-Master Security bit for i2c2"
hexmask.long.byte 0x8 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to i2c2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i2c2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x8 9. "dmam1,Security bit configuration for transactions from dmam1 to i2c2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x8 8. "dma,Security bit configuration for transactions from dma to i2c2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to i2c2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "i2c3,Per-Master Security bit for i2c3"
hexmask.long.byte 0xC 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to i2c3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i2c3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0xC 9. "dmam1,Security bit configuration for transactions from dmam1 to i2c3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 8. "dma,Security bit configuration for transactions from dma to i2c3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to i2c3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x10 "i2c4,Per-Master Security bit for i2c4"
hexmask.long.byte 0x10 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x10 24. "axi_ap,Security bit configuration for transactions from axi_ap to. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x10 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x10 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i2c4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x10 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x10 9. "dmam1,Security bit configuration for transactions from dmam1 to i2c4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 8. "dma,Security bit configuration for transactions from dma to i2c4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x10 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 0. "mpu,Security bit configuration for transactions from mpu to i2c4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x14 "sp_timer0,Per-Master Security bit for sp_timer0"
hexmask.long.byte 0x14 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x14 24. "axi_ap,Security bit configuration for transactions from axi_ap to sp_timer0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x14 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to sp_timer0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x14 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 9. "dmam1,Security bit configuration for transactions from dmam1 to sp_timer0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 8. "dma,Security bit configuration for transactions from dma to sp_timer0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0. "mpu,Security bit configuration for transactions from mpu to sp_timer0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x18 "sp_timer1,Per-Master Security bit for sp_timer1"
hexmask.long.byte 0x18 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x18 24. "axi_ap,Security bit configuration for transactions from axi_ap to sp_timer1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x18 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x18 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to sp_timer1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x18 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x18 9. "dmam1,Security bit configuration for transactions from dmam1 to sp_timer1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 8. "dma,Security bit configuration for transactions from dma to sp_timer1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0. "mpu,Security bit configuration for transactions from mpu to sp_timer1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x1C "uart0,Per-Master Security bit for uart0"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "axi_ap,Security bit configuration for transactions from axi_ap to uart0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to uart0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x1C 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 9. "dmam1,Security bit configuration for transactions from dmam1 to uart0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x1C 8. "dma,Security bit configuration for transactions from dma to uart0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 0. "mpu,Security bit configuration for transactions from mpu to uart0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x20 "uart1,Per-Master Security bit for uart1"
hexmask.long.byte 0x20 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x20 24. "axi_ap,Security bit configuration for transactions from axi_ap to uart1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x20 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x20 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to uart1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x20 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x20 9. "dmam1,Security bit configuration for transactions from dmam1 to uart1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x20 8. "dma,Security bit configuration for transactions from dma to uart1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x20 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 0. "mpu,Security bit configuration for transactions from mpu to uart1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x24 "i3c0,Per-Master Security bit for i3c0"
hexmask.long.byte 0x24 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x24 24. "axi_ap,Security bit configuration for transactions from axi_ap to i3c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x24 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x24 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i3c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x24 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x24 9. "dmam1,Security bit configuration for transactions from dmam1 to i3c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x24 8. "dma,Security bit configuration for transactions from dma to i3c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x24 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x24 0. "mpu,Security bit configuration for transactions from mpu to i3c0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x28 "i3c1,Per-Master Security bit for i3c1"
hexmask.long.byte 0x28 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x28 24. "axi_ap,Security bit configuration for transactions from axi_ap to i3c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x28 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x28 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to i3c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x28 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x28 9. "dmam1,Security bit configuration for transactions from dmam1 to i3c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x28 8. "dma,Security bit configuration for transactions from dma to i3c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x28 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0. "mpu,Security bit configuration for transactions from mpu to i3c1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x2C "dma0,Per-Master Security bit for dma0"
hexmask.long.byte 0x2C 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x2C 24. "axi_ap,Security bit configuration for transactions from axi_ap to dma0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x2C 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x2C 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to dma0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x2C 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x2C 0. "mpu,Security bit configuration for transactions from mpu to dma0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x30 "dma1,Per-Master Security bit for dma1"
hexmask.long.byte 0x30 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x30 24. "axi_ap,Security bit configuration for transactions from axi_ap to dma1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x30 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x30 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to dma1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x30 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x30 0. "mpu,Security bit configuration for transactions from mpu to dma1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x34 "combo_phy,Per-Master Security bit for combo_phy"
hexmask.long.byte 0x34 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x34 24. "axi_ap,Security bit configuration for transactions from axi_ap to combo_phy. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x34 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x34 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to combo_phy. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x34 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x34 0. "mpu,Security bit configuration for transactions from mpu to combo_phy. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x38 "nand_sdma,Per-Master Security bit for nand_sdma"
hexmask.long.byte 0x38 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x38 24. "axi_ap,Security bit configuration for transactions from axi_ap to nand_sdma. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x38 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x38 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to nand_sdma. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x38 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x38 9. "dmam1,Security bit configuration for transactions from dmam1 to nand_sdma. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x38 8. "dma,Security bit configuration for transactions from dma to nand_sdma. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x38 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x38 0. "mpu,Security bit configuration for transactions from mpu to nand_sdma. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree "NOC_FW_L4_SYS"
base ad:0x10D21100
group.long 0x8++0x1B
line.long 0x0 "dma_ecc,Per-Master Security bit for dma_ecc"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "emac0rx_ecc,Per-Master Security bit for emac0rx_ecc"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac0rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac0rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x4 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to emac0rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "emac0tx_ecc,Per-Master Security bit for emac0tx_ecc"
hexmask.long.byte 0x8 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac0tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac0tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to emac0tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "emac1rx_ecc,Per-Master Security bit for emac1rx_ecc"
hexmask.long.byte 0xC 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac1rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac1rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0xC 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to emac1rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x10 "emac1tx_ecc,Per-Master Security bit for emac1tx_ecc"
hexmask.long.byte 0x10 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x10 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac1tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x10 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x10 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac1tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x10 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x10 0. "mpu,Security bit configuration for transactions from mpu to emac1tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x14 "emac2rx_ecc,Per-Master Security bit for emac2rx_ecc"
hexmask.long.byte 0x14 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac2rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x14 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac2rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x14 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "mpu,Security bit configuration for transactions from mpu to emac2rx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x18 "emac2tx_ecc,Per-Master Security bit for emac2tx_ecc"
hexmask.long.byte 0x18 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x18 24. "axi_ap,Security bit configuration for transactions from axi_ap to emac2tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x18 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x18 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to emac2tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x18 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x18 0. "mpu,Security bit configuration for transactions from mpu to emac2tx_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x2C++0xF
line.long 0x0 "nand_ecc,Per-Master Security bit for nand_ecc"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to nand_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to nand_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to nand_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "nand_read_ecc,Per-Master Security bit for nand_read_ecc"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to nand_read_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to nand_read_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x4 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to nand_read_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "nand_write_ecc,Per-Master Security bit for nand_write_ecc"
hexmask.long.byte 0x8 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to nand_write_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to nand_write_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to nand_write_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "ocram_ecc,Per-Master Security bit for onchipram_ecc"
hexmask.long.byte 0xC 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to onchipram_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to onchipram_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0xC 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to onchipram_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x40++0xF
line.long 0x0 "sdmmc_ecc,Per-Master Security bit for sdmmc_ecc"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to sdmmc_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to sdmmc_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to sdmmc_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "usb0_ecc,Per-Master Security bit for usb0_ecc"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to usb0_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to usb0_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x4 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to usb0_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "usb1_cacheecc,Per-Master Security bit for usb1_cacheecc"
hexmask.long.byte 0x8 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to usb1_cacheecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to usb1_cacheecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to usb1_cacheecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "clock_manager,Per-Master Security bit for clock_manager"
hexmask.long.byte 0xC 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to clock_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to clock_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0xC 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to clock_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x54++0x37
line.long 0x0 "io_manager,Per-Master Security bit for pin_mux_register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to pin_mux_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to pin_mux_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to pin_mux_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "reset_manager,Per-Master Security bit for reset_manager"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to reset_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to reset_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x4 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to reset_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x8 "system_manager,Per-Master Security bit for system_manager"
hexmask.long.byte 0x8 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x8 24. "axi_ap,Security bit configuration for transactions from axi_ap to system_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x8 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to system_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "mpu,Security bit configuration for transactions from mpu to system_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0xC "osc0_timer,Per-Master Security bit for osc0_timer"
hexmask.long.byte 0xC 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0xC 24. "axi_ap,Security bit configuration for transactions from axi_ap to osc0_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0xC 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to osc0_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0xC 9. "dmam1,Security bit configuration for transactions from dmam1 to osc0_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0xC 8. "dma,Security bit configuration for transactions from dma to osc0_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0xC 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 0. "mpu,Security bit configuration for transactions from mpu to osc0_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x10 "osc1_timer,Per-Master Security bit for osc1_timer"
hexmask.long.byte 0x10 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x10 24. "axi_ap,Security bit configuration for transactions from axi_ap to osc1_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x10 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x10 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to osc1_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x10 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x10 9. "dmam1,Security bit configuration for transactions from dmam1 to osc1_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x10 8. "dma,Security bit configuration for transactions from dma to osc1_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x10 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 0. "mpu,Security bit configuration for transactions from mpu to osc1_timer. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x14 "watchdog0,Per-Master Security bit for watchdog0"
hexmask.long.byte 0x14 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x14 24. "axi_ap,Security bit configuration for transactions from axi_ap to watchdog0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x14 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to watchdog0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x14 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 9. "dmam1,Security bit configuration for transactions from dmam1 to watchdog0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x14 8. "dma,Security bit configuration for transactions from dma to watchdog0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0. "mpu,Security bit configuration for transactions from mpu to watchdog0. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x18 "watchdog1,Per-Master Security bit for watchdog1"
hexmask.long.byte 0x18 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x18 24. "axi_ap,Security bit configuration for transactions from axi_ap to watchdog1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x18 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x18 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to watchdog1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x18 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x18 9. "dmam1,Security bit configuration for transactions from dmam1 to watchdog1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x18 8. "dma,Security bit configuration for transactions from dma to watchdog1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0. "mpu,Security bit configuration for transactions from mpu to watchdog1. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x1C "watchdog2,Per-Master Security bit for watchdog0"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "axi_ap,Security bit configuration for transactions from axi_ap to watchdog2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to watchdog2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x1C 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 9. "dmam1,Security bit configuration for transactions from dmam1 to watchdog2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x1C 8. "dma,Security bit configuration for transactions from dma to watchdog2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 0. "mpu,Security bit configuration for transactions from mpu to watchdog2. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x20 "watchdog3,Per-Master Security bit for watchdog1"
hexmask.long.byte 0x20 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x20 24. "axi_ap,Security bit configuration for transactions from axi_ap to watchdog3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x20 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x20 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to watchdog3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x20 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x20 9. "dmam1,Security bit configuration for transactions from dmam1 to watchdog3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x20 8. "dma,Security bit configuration for transactions from dma to watchdog3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x20 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 0. "mpu,Security bit configuration for transactions from mpu to watchdog3. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x24 "dap,Per-Master Security bit for dap"
hexmask.long.byte 0x24 26.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x24 25. "etr,Security bit configuration for transactions from etr to dap. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x24 24. "axi_ap,Security bit configuration for transactions from axi_ap to dap. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x24 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x24 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to dap. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x24 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x24 0. "mpu,Security bit configuration for transactions from mpu to dap. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x28 "watchdog4,Per-Master Security bit for watchdog4"
hexmask.long.byte 0x28 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x28 24. "axi_ap,Security bit configuration for transactions from axi_ap to watchdog4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x28 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x28 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to watchdog4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x28 10.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x28 9. "dmam1,Security bit configuration for transactions from dmam1 to watchdog4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x28 8. "dma,Security bit configuration for transactions from dma to watchdog4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x28 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0. "mpu,Security bit configuration for transactions from mpu to watchdog4. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x2C "power_manager,Per-Master Security bit for power_manager"
hexmask.long.byte 0x2C 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x2C 24. "axi_ap,Security bit configuration for transactions from axi_ap to power_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x2C 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x2C 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to power_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x2C 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x2C 0. "mpu,Security bit configuration for transactions from mpu to power_manager. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x30 "usb1_rxecc,Per-Master Security bit for usb1_rxecc"
hexmask.long.byte 0x30 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x30 24. "axi_ap,Security bit configuration for transactions from axi_ap to usb1_rxecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x30 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x30 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to usb1_rxecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x30 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x30 0. "mpu,Security bit configuration for transactions from mpu to usb1_rxecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x34 "usb1_txecc,Per-Master Security bit for usb1_txecc"
hexmask.long.byte 0x34 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x34 24. "axi_ap,Security bit configuration for transactions from axi_ap to usb1_txecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x34 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x34 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to usb1_txecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x34 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x34 0. "mpu,Security bit configuration for transactions from mpu to usb1_txecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
group.long 0x90++0x7
line.long 0x0 "l4_noc_probes,Per-Master Security bit for noc_probes_register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
line.long 0x4 "l4_noc_qos,Per-Master Security bit for noc_probes_register"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 24. "axi_ap,Security bit configuration for transactions from axi_ap to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x4 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x4 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "mpu,Security bit configuration for transactions from mpu to noc_probes_register. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree "NOC_FW_LWSOC2FPGA"
base ad:0x10D21300
group.long 0x0++0x3
line.long 0x0 "lwsoc2fpga,Per-Master Security bit for Lightweight SOC2FPGA"
hexmask.long.byte 0x0 28.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
bitfld.long 0x0 27. "sdm_nand,Security bit configuration for transactions from SDM NAND to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 26. "sdm_sdmmc,Security bit configuration for transactions from SDM SDMMC to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 25. "etr,Security bit configuration for transactions from etr to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 23. "nand,Security bit configuration for transactions from nand to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 22. "sdmmc,Security bit configuration for transactions from sdmmc to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 21. "usb1,Security bit configuration for transactions from usb1 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
newline
bitfld.long 0x0 20. "usb0,Security bit configuration for transactions from usb0 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 19. "emac2,Security bit configuration for transactions from emac2 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 18. "emac1,Security bit configuration for transactions from emac1 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 17. "emac0,Security bit configuration for transactions from emac0 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 10.--16. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "dmam1,Security bit configuration for transactions from dmam1 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 8. "dmam0,Security bit configuration for transactions from dma0 to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to lwsoc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree "NOC_FW_SOC2FPGA"
base ad:0x10D21200
group.long 0x0++0x3
line.long 0x0 "soc2fpga,Per-Master Security bit for SOC2FPGA"
hexmask.long.byte 0x0 28.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
bitfld.long 0x0 27. "sdm_nand,Security bit configuration for transactions from SDM NAND to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 26. "sdm_sdmmc,Security bit configuration for transactions from SDM SDMMC to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 25. "etr,Security bit configuration for transactions from etr to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 23. "nand,Security bit configuration for transactions from nand to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 22. "sdmmc,Security bit configuration for transactions from sdmmc to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 21. "usb1,Security bit configuration for transactions from usb1 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 20. "usb0,Security bit configuration for transactions from usb0 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
newline
bitfld.long 0x0 19. "emac2,Security bit configuration for transactions from emac2 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 18. "emac1,Security bit configuration for transactions from emac1 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 17. "emac0,Security bit configuration for transactions from emac0 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 10.--16. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "dmam1,Security bit configuration for transactions from dmam1 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
bitfld.long 0x0 8. "dmam0,Security bit configuration for transactions from dmam0 to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to soc2fpga. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree "NOC_FW_TCU"
base ad:0x10D21400
group.long 0x0++0x3
line.long 0x0 "tcu,Per-Master Security bit for dma_ecc"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "axi_ap,Security bit configuration for transactions from axi_ap to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.byte 0x0 17.--23. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "fpga2soc,Security bit configuration for transactions from fpga2soc to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "mpu,Security bit configuration for transactions from mpu to dma_ecc. When cleared (0)  only Secure transactions are allowed. When set (1)  both Secure and Non-Secure transactions are allowed." "0,1"
tree.end
tree "NOC_MAIN"
base ad:0x10D22000
rgroup.long 0x0++0x7
line.long 0x0 "cs_obs_at_main_AtbEndPoint_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "cs_obs_at_main_AtbEndPoint_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x8++0x7
line.long 0x0 "cs_obs_at_main_AtbEndPoint_AtbId,Register AtbId"
hexmask.long 0x0 7.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--6. 1. "ATBID,ATB AtId"
line.long 0x4 "cs_obs_at_main_AtbEndPoint_AtbEn,Register AtbEn"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "ATBEN,ATB Unit Enable" "0,1"
rgroup.long 0x80++0x7
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "cs_obs_at_main_ErrorLogger_0_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x88++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_FaultEn,Register FaultEn"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "FAULTEN,Set to 1 to enable output signal Fault. Fault asserted when ErrVld is 1." "0,1"
rgroup.long 0x8C++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrVld,Register ErrVld"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "ERRVLD,1 indicates an error has been logged" "0,1"
group.long 0x90++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrClr,Register ErrClr"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0. "ERRCLR,Set to 1 to clear ErrVld. NOTE The written value is not stored in ErrVld. A read always returns 0." "0,1"
rgroup.long 0x94++0x7
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrLog0,Stores NTTP packet header fields Lock. Opc. ErrCode. Len1 and indicates version of NTTP transport protocol"
bitfld.long 0x0 31. "FORMAT,NTTP transport protocol version" "0,1"
newline
bitfld.long 0x0 28.--30. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0 16.--27. 1. "LEN1,Len1"
newline
hexmask.long.byte 0x0 11.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8.--10. "ERRCODE,ErrCode" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 5.--7. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 1.--4. 1. "OPC,Opc"
newline
bitfld.long 0x0 0. "LOCK,Lock" "0,1"
line.long 0x4 "cs_obs_at_main_ErrorLogger_0_ErrLog1,Register ErrLog1"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x4 0.--24. 1. "ERRLOG1,Stores NTTP packet header field RouteId (LSBs) of the logged error"
rgroup.long 0xA0++0x13
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_ErrLog3,Register ErrLog3"
hexmask.long 0x0 0.--31. 1. "ERRLOG3,Stores NTTP packet header field Addr (LSBs) of the logged error"
line.long 0x4 "cs_obs_at_main_ErrorLogger_0_ErrLog4,Register ErrLog4"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "ERRLOG4,Stores NTTP packet header field Addr (MSBs) of the logged error"
line.long 0x8 "cs_obs_at_main_ErrorLogger_0_ErrLog5,Register ErrLog5"
hexmask.long 0x8 0.--31. 1. "ERRLOG5,Stores NTTP packet header field User (LSBs) of the logged error"
line.long 0xC "cs_obs_at_main_ErrorLogger_0_ErrLog6,Register ErrLog6"
hexmask.long.byte 0xC 27.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0xC 0.--26. 1. "ERRLOG6,Stores NTTP packet header field User (midrange bits) of the logged error"
line.long 0x10 "cs_obs_at_main_ErrorLogger_0_ErrLog7,Register ErrLog7"
hexmask.long 0x10 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 0.--1. "ERRLOG7,Stores NTTP packet header field Security of the logged error" "0,1,2,3"
group.long 0xCC++0x3
line.long 0x0 "cs_obs_at_main_ErrorLogger_0_StallEn,Register StallEn"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "STALLEN,Set to 1 to enable stall mode behavior." "0,1"
rgroup.long 0x100++0x7
line.long 0x0 "cs_obs_at_main_STPv2Converter_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "cs_obs_at_main_STPv2Converter_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x108++0x7
line.long 0x0 "cs_obs_at_main_STPv2Converter_AsyncPeriod,Register AsyncPeriod"
hexmask.long 0x0 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--4. 1. "ASYNCPERIOD,Defines the period of ASYNC sequences."
line.long 0x4 "cs_obs_at_main_STPv2Converter_STPV2En,Register STPV2En"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "STPV2EN,Enables the output to STP  rstVal=1." "0,1"
rgroup.long 0x400++0x7
line.long 0x0 "probe_ccu_main_Probe_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "probe_ccu_main_Probe_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x408++0x7
line.long 0x0 "probe_ccu_main_Probe_MainCtl,Register MainCtl contains probe global control bits. The register has seven bit fields:"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0  filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore  only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1  filters are.." "0,1"
newline
rbitfld.long 0x0 6. "INTRUSIVEMODE,When set to 1  register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0  the register enables trace operation in Overflow flow-control mode" "0,1"
newline
bitfld.long 0x0 5. "STATCONDDUMP,When set  register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin  StatAlarmMax  and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1"
newline
bitfld.long 0x0 4. "ALARMEN,When set  register field AlarmEn enables the probe to collect alarm-related information. When the register field bit is null  both TraceAlarm and StatAlarm outputs are driven to 0." "0,1"
newline
bitfld.long 0x0 3. "STATEN,When set to 1  register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0  counters are disabled." "0,1"
newline
bitfld.long 0x0 2. "PAYLOADEN,Register field PayloadEn  when set to 1  enables traces to contain headers and payload. When set ot 0  only headers are reported." "0,1"
newline
bitfld.long 0x0 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1"
newline
bitfld.long 0x0 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status  independently of filtering mechanisms  thus constituting a simple supplementary global filter." "0,1"
line.long 0x4 "probe_ccu_main_Probe_CfgCtl,Stores global enable and active bits related to the probe."
hexmask.long 0x4 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x4 1. "ACTIVE,Active status of the packet probe." "0,1"
newline
bitfld.long 0x4 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1"
group.long 0x414++0x7
line.long 0x0 "probe_ccu_main_Probe_FilterLut,Register FilterLut"
hexmask.long 0x0 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--3. 1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.."
line.long 0x4 "probe_ccu_main_Probe_TraceAlarmEn,Register TraceAlarmEn"
hexmask.long 0x4 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--2. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3,4,5,6,7"
rgroup.long 0x41C++0x3
line.long 0x0 "probe_ccu_main_Probe_TraceAlarmStatus,Register TraceAlarmStatus"
hexmask.long 0x0 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--2. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet  independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3,4,5,6,7"
group.long 0x420++0xF
line.long 0x0 "probe_ccu_main_Probe_TraceAlarmClr,Register TraceAlarmClr"
hexmask.long 0x0 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0.--2. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0  TraceAlarmClr is reserved.NOTE The.." "0,1,2,3,4,5,6,7"
line.long 0x4 "probe_ccu_main_Probe_StatPeriod,Register StatPeriod"
hexmask.long 0x4 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period  within a range of 2 cycles to 2 gigacycles  during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.."
line.long 0x8 "probe_ccu_main_Probe_StatGo,Register StatGo"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x8 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode  that is  when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1"
line.long 0xC "probe_ccu_main_Probe_StatAlarmMin,Register StatAlarmMin"
hexmask.long 0xC 0.--31. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
group.long 0x434++0x3
line.long 0x0 "probe_ccu_main_Probe_StatAlarmMax,Register StatAlarmMax"
hexmask.long 0x0 0.--31. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
rgroup.long 0x43C++0x3
line.long 0x0 "probe_ccu_main_Probe_StatAlarmStatus,Register StatAlarmStatus"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1"
group.long 0x440++0x7
line.long 0x0 "probe_ccu_main_Probe_StatAlarmClr,Register StatAlarmClr"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False  StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1"
line.long 0x4 "probe_ccu_main_Probe_StatAlarmEn,Register StatAlarmEn"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1"
group.long 0x480++0x2B
line.long 0x0 "probe_ccu_main_Probe_Filters_0_RouteIdBase,Register Filters_0_RouteIdBase"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x0 0.--24. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_ccu_main_Probe_Filters_0_RouteIdMask,Register Filters_0_RouteIdMask"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x4 0.--24. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId & RouteIdMask = RouteIdBase & RouteIdMask."
line.long 0x8 "probe_ccu_main_Probe_Filters_0_AddrBase_Low,Register Filters_0_AddrBase_Low"
hexmask.long 0x8 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_ccu_main_Probe_Filters_0_AddrBase_High,Register Filters_0_AddrBase_High"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_0_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_ccu_main_Probe_Filters_0_WindowSize,Register Filters_0_WindowSize"
hexmask.long 0x10 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows.."
line.long 0x14 "probe_ccu_main_Probe_Filters_0_SecurityBase,Register Filters_0_SecurityBase"
hexmask.long 0x14 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0.--1. "FILTERS_0_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_ccu_main_Probe_Filters_0_SecurityMask,Register Filters_0_SecurityMask"
hexmask.long 0x18 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0.--1. "FILTERS_0_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security & SecurityMask = SecurityBase & SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_ccu_main_Probe_Filters_0_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
hexmask.long 0x1C 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_ccu_main_Probe_Filters_0_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
hexmask.long 0x20 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_ccu_main_Probe_Filters_0_Length,Register Filters_0_Length"
hexmask.long 0x24 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_ccu_main_Probe_Filters_0_Urgency,Register Filters_0_Urgency"
hexmask.long 0x28 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0.--1. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x4E0++0x2B
line.long 0x0 "probe_ccu_main_Probe_Filters_1_RouteIdBase,Register Filters_1_RouteIdBase"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x0 0.--24. 1. "FILTERS_1_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_ccu_main_Probe_Filters_1_RouteIdMask,Register Filters_1_RouteIdMask"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x4 0.--24. 1. "FILTERS_1_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId & RouteIdMask = RouteIdBase & RouteIdMask."
line.long 0x8 "probe_ccu_main_Probe_Filters_1_AddrBase_Low,Register Filters_1_AddrBase_Low"
hexmask.long 0x8 0.--31. 1. "FILTERS_1_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_ccu_main_Probe_Filters_1_AddrBase_High,Register Filters_1_AddrBase_High"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_1_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_ccu_main_Probe_Filters_1_WindowSize,Register Filters_1_WindowSize"
hexmask.long 0x10 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_1_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows.."
line.long 0x14 "probe_ccu_main_Probe_Filters_1_SecurityBase,Register Filters_1_SecurityBase"
hexmask.long 0x14 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0.--1. "FILTERS_1_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_ccu_main_Probe_Filters_1_SecurityMask,Register Filters_1_SecurityMask"
hexmask.long 0x18 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0.--1. "FILTERS_1_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security & SecurityMask = SecurityBase & SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_ccu_main_Probe_Filters_1_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
hexmask.long 0x1C 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_ccu_main_Probe_Filters_1_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
hexmask.long 0x20 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_ccu_main_Probe_Filters_1_Length,Register Filters_1_Length"
hexmask.long 0x24 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_1_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_ccu_main_Probe_Filters_1_Urgency,Register Filters_1_Urgency"
hexmask.long 0x28 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0.--1. "FILTERS_1_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x604++0x7
line.long 0x0 "probe_ccu_main_Probe_Counters_0_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_ccu_main_Probe_Counters_0_AlarmMode,Register Counters_0_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0x60C++0x3
line.long 0x0 "probe_ccu_main_Probe_Counters_0_Val,Register Counters_0_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x614++0x7
line.long 0x0 "probe_ccu_main_Probe_Counters_1_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_ccu_main_Probe_Counters_1_AlarmMode,Register Counters_1_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0x61C++0x3
line.long 0x0 "probe_ccu_main_Probe_Counters_1_Val,Register Counters_1_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x624++0x7
line.long 0x0 "probe_ccu_main_Probe_Counters_2_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_ccu_main_Probe_Counters_2_AlarmMode,Register Counters_2_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0x62C++0x3
line.long 0x0 "probe_ccu_main_Probe_Counters_2_Val,Register Counters_2_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x634++0x7
line.long 0x0 "probe_ccu_main_Probe_Counters_3_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_ccu_main_Probe_Counters_3_AlarmMode,Register Counters_3_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0x63C++0x3
line.long 0x0 "probe_ccu_main_Probe_Counters_3_Val,Register Counters_3_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
rgroup.long 0x800++0x7
line.long 0x0 "probe_emac_main_Probe_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "probe_emac_main_Probe_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x808++0x7
line.long 0x0 "probe_emac_main_Probe_MainCtl,Register MainCtl contains probe global control bits. The register has seven bit fields:"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0  filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore  only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1  filters are.." "0,1"
newline
rbitfld.long 0x0 6. "INTRUSIVEMODE,When set to 1  register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0  the register enables trace operation in Overflow flow-control mode" "0,1"
newline
bitfld.long 0x0 5. "STATCONDDUMP,When set  register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin  StatAlarmMax  and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1"
newline
bitfld.long 0x0 4. "ALARMEN,When set  register field AlarmEn enables the probe to collect alarm-related information. When the register field bit is null  both TraceAlarm and StatAlarm outputs are driven to 0." "0,1"
newline
bitfld.long 0x0 3. "STATEN,When set to 1  register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0  counters are disabled." "0,1"
newline
bitfld.long 0x0 2. "PAYLOADEN,Register field PayloadEn  when set to 1  enables traces to contain headers and payload. When set ot 0  only headers are reported." "0,1"
newline
bitfld.long 0x0 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1"
newline
bitfld.long 0x0 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status  independently of filtering mechanisms  thus constituting a simple supplementary global filter." "0,1"
line.long 0x4 "probe_emac_main_Probe_CfgCtl,Stores global enable and active bits related to the probe."
hexmask.long 0x4 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x4 1. "ACTIVE,Active status of the packet probe." "0,1"
newline
bitfld.long 0x4 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1"
group.long 0x814++0x7
line.long 0x0 "probe_emac_main_Probe_FilterLut,Register FilterLut"
hexmask.long 0x0 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--3. 1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.."
line.long 0x4 "probe_emac_main_Probe_TraceAlarmEn,Register TraceAlarmEn"
hexmask.long 0x4 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--2. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3,4,5,6,7"
rgroup.long 0x81C++0x3
line.long 0x0 "probe_emac_main_Probe_TraceAlarmStatus,Register TraceAlarmStatus"
hexmask.long 0x0 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--2. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet  independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3,4,5,6,7"
group.long 0x820++0xF
line.long 0x0 "probe_emac_main_Probe_TraceAlarmClr,Register TraceAlarmClr"
hexmask.long 0x0 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0.--2. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0  TraceAlarmClr is reserved.NOTE The.." "0,1,2,3,4,5,6,7"
line.long 0x4 "probe_emac_main_Probe_StatPeriod,Register StatPeriod"
hexmask.long 0x4 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period  within a range of 2 cycles to 2 gigacycles  during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.."
line.long 0x8 "probe_emac_main_Probe_StatGo,Register StatGo"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x8 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode  that is  when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1"
line.long 0xC "probe_emac_main_Probe_StatAlarmMin,Register StatAlarmMin"
hexmask.long 0xC 0.--31. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
group.long 0x834++0x3
line.long 0x0 "probe_emac_main_Probe_StatAlarmMax,Register StatAlarmMax"
hexmask.long 0x0 0.--31. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
rgroup.long 0x83C++0x3
line.long 0x0 "probe_emac_main_Probe_StatAlarmStatus,Register StatAlarmStatus"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1"
group.long 0x840++0x7
line.long 0x0 "probe_emac_main_Probe_StatAlarmClr,Register StatAlarmClr"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False  StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1"
line.long 0x4 "probe_emac_main_Probe_StatAlarmEn,Register StatAlarmEn"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1"
group.long 0x880++0x2B
line.long 0x0 "probe_emac_main_Probe_Filters_0_RouteIdBase,Register Filters_0_RouteIdBase"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x0 0.--24. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_emac_main_Probe_Filters_0_RouteIdMask,Register Filters_0_RouteIdMask"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x4 0.--24. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId & RouteIdMask = RouteIdBase & RouteIdMask."
line.long 0x8 "probe_emac_main_Probe_Filters_0_AddrBase_Low,Register Filters_0_AddrBase_Low"
hexmask.long 0x8 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_emac_main_Probe_Filters_0_AddrBase_High,Register Filters_0_AddrBase_High"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_0_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_emac_main_Probe_Filters_0_WindowSize,Register Filters_0_WindowSize"
hexmask.long 0x10 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows.."
line.long 0x14 "probe_emac_main_Probe_Filters_0_SecurityBase,Register Filters_0_SecurityBase"
hexmask.long 0x14 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0.--1. "FILTERS_0_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_emac_main_Probe_Filters_0_SecurityMask,Register Filters_0_SecurityMask"
hexmask.long 0x18 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0.--1. "FILTERS_0_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security & SecurityMask = SecurityBase & SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_emac_main_Probe_Filters_0_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
hexmask.long 0x1C 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_emac_main_Probe_Filters_0_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
hexmask.long 0x20 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_emac_main_Probe_Filters_0_Length,Register Filters_0_Length"
hexmask.long 0x24 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_emac_main_Probe_Filters_0_Urgency,Register Filters_0_Urgency"
hexmask.long 0x28 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0.--1. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x8E0++0x2B
line.long 0x0 "probe_emac_main_Probe_Filters_1_RouteIdBase,Register Filters_1_RouteIdBase"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x0 0.--24. 1. "FILTERS_1_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_emac_main_Probe_Filters_1_RouteIdMask,Register Filters_1_RouteIdMask"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x4 0.--24. 1. "FILTERS_1_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId & RouteIdMask = RouteIdBase & RouteIdMask."
line.long 0x8 "probe_emac_main_Probe_Filters_1_AddrBase_Low,Register Filters_1_AddrBase_Low"
hexmask.long 0x8 0.--31. 1. "FILTERS_1_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_emac_main_Probe_Filters_1_AddrBase_High,Register Filters_1_AddrBase_High"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_1_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_emac_main_Probe_Filters_1_WindowSize,Register Filters_1_WindowSize"
hexmask.long 0x10 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_1_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows.."
line.long 0x14 "probe_emac_main_Probe_Filters_1_SecurityBase,Register Filters_1_SecurityBase"
hexmask.long 0x14 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0.--1. "FILTERS_1_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_emac_main_Probe_Filters_1_SecurityMask,Register Filters_1_SecurityMask"
hexmask.long 0x18 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0.--1. "FILTERS_1_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security & SecurityMask = SecurityBase & SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_emac_main_Probe_Filters_1_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
hexmask.long 0x1C 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_emac_main_Probe_Filters_1_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
hexmask.long 0x20 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_emac_main_Probe_Filters_1_Length,Register Filters_1_Length"
hexmask.long 0x24 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_1_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_emac_main_Probe_Filters_1_Urgency,Register Filters_1_Urgency"
hexmask.long 0x28 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0.--1. "FILTERS_1_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0xA04++0x7
line.long 0x0 "probe_emac_main_Probe_Counters_0_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 6.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 5. "EXTEVENT,When greater than 0  the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_emac_main_Probe_Counters_0_AlarmMode,Register Counters_0_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0xA0C++0x3
line.long 0x0 "probe_emac_main_Probe_Counters_0_Val,Register Counters_0_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0xA14++0x7
line.long 0x0 "probe_emac_main_Probe_Counters_1_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 6.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 5. "EXTEVENT,When greater than 0  the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_emac_main_Probe_Counters_1_AlarmMode,Register Counters_1_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0xA1C++0x3
line.long 0x0 "probe_emac_main_Probe_Counters_1_Val,Register Counters_1_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0xA24++0x7
line.long 0x0 "probe_emac_main_Probe_Counters_2_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 6.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 5. "EXTEVENT,When greater than 0  the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_emac_main_Probe_Counters_2_AlarmMode,Register Counters_2_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0xA2C++0x3
line.long 0x0 "probe_emac_main_Probe_Counters_2_Val,Register Counters_2_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0xA34++0x7
line.long 0x0 "probe_emac_main_Probe_Counters_3_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 6.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 5. "EXTEVENT,When greater than 0  the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_emac_main_Probe_Counters_3_AlarmMode,Register Counters_3_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0xA3C++0x3
line.long 0x0 "probe_emac_main_Probe_Counters_3_Val,Register Counters_3_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
rgroup.long 0xC00++0x7
line.long 0x0 "probe_soc2fpga_main_Probe_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "probe_soc2fpga_main_Probe_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0xC08++0x13
line.long 0x0 "probe_soc2fpga_main_Probe_MainCtl,Register MainCtl contains probe global control bits. The register has seven bit fields:"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0  filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore  only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1  filters are.." "0,1"
newline
rbitfld.long 0x0 6. "INTRUSIVEMODE,When set to 1  register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0  the register enables trace operation in Overflow flow-control mode" "0,1"
newline
bitfld.long 0x0 5. "STATCONDDUMP,When set  register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin  StatAlarmMax  and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1"
newline
bitfld.long 0x0 4. "ALARMEN,When set  register field AlarmEn enables the probe to collect alarm-related information. When the register field bit is null  both TraceAlarm and StatAlarm outputs are driven to 0." "0,1"
newline
bitfld.long 0x0 3. "STATEN,When set to 1  register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0  counters are disabled." "0,1"
newline
bitfld.long 0x0 2. "PAYLOADEN,Register field PayloadEn  when set to 1  enables traces to contain headers and payload. When set ot 0  only headers are reported." "0,1"
newline
bitfld.long 0x0 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1"
newline
bitfld.long 0x0 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status  independently of filtering mechanisms  thus constituting a simple supplementary global filter." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_CfgCtl,Stores global enable and active bits related to the probe."
hexmask.long 0x4 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x4 1. "ACTIVE,Active status of the packet probe." "0,1"
newline
bitfld.long 0x4 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1"
line.long 0x8 "probe_soc2fpga_main_Probe_TracePortSel,Register TracePortSel"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0. "TRACEPORTSEL,Register TracePortSel indicates which generic protocol link is currently being observed by trace logic.The number of bits in register TracePortSel is equal to log2 of the value set for parameter nPort.The register can be updated at any time .." "0,1"
line.long 0xC "probe_soc2fpga_main_Probe_FilterLut,Register FilterLut"
hexmask.long 0xC 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--3. 1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.."
line.long 0x10 "probe_soc2fpga_main_Probe_TraceAlarmEn,Register TraceAlarmEn"
hexmask.long 0x10 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 0.--2. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3,4,5,6,7"
rgroup.long 0xC1C++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_TraceAlarmStatus,Register TraceAlarmStatus"
hexmask.long 0x0 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--2. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet  independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3,4,5,6,7"
group.long 0xC20++0xF
line.long 0x0 "probe_soc2fpga_main_Probe_TraceAlarmClr,Register TraceAlarmClr"
hexmask.long 0x0 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0.--2. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0  TraceAlarmClr is reserved.NOTE The.." "0,1,2,3,4,5,6,7"
line.long 0x4 "probe_soc2fpga_main_Probe_StatPeriod,Register StatPeriod"
hexmask.long 0x4 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period  within a range of 2 cycles to 2 gigacycles  during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.."
line.long 0x8 "probe_soc2fpga_main_Probe_StatGo,Register StatGo"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x8 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode  that is  when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1"
line.long 0xC "probe_soc2fpga_main_Probe_StatAlarmMin,Register StatAlarmMin"
hexmask.long 0xC 0.--31. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
group.long 0xC34++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_StatAlarmMax,Register StatAlarmMax"
hexmask.long 0x0 0.--31. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
rgroup.long 0xC3C++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_StatAlarmStatus,Register StatAlarmStatus"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1"
group.long 0xC40++0x7
line.long 0x0 "probe_soc2fpga_main_Probe_StatAlarmClr,Register StatAlarmClr"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False  StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_StatAlarmEn,Register StatAlarmEn"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1"
group.long 0xC80++0x2B
line.long 0x0 "probe_soc2fpga_main_Probe_Filters_0_RouteIdBase,Register Filters_0_RouteIdBase"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x0 0.--24. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_soc2fpga_main_Probe_Filters_0_RouteIdMask,Register Filters_0_RouteIdMask"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x4 0.--24. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId & RouteIdMask = RouteIdBase & RouteIdMask."
line.long 0x8 "probe_soc2fpga_main_Probe_Filters_0_AddrBase_Low,Register Filters_0_AddrBase_Low"
hexmask.long 0x8 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_soc2fpga_main_Probe_Filters_0_AddrBase_High,Register Filters_0_AddrBase_High"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_0_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_soc2fpga_main_Probe_Filters_0_WindowSize,Register Filters_0_WindowSize"
hexmask.long 0x10 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows.."
line.long 0x14 "probe_soc2fpga_main_Probe_Filters_0_SecurityBase,Register Filters_0_SecurityBase"
hexmask.long 0x14 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0.--1. "FILTERS_0_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_soc2fpga_main_Probe_Filters_0_SecurityMask,Register Filters_0_SecurityMask"
hexmask.long 0x18 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0.--1. "FILTERS_0_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security & SecurityMask = SecurityBase & SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_soc2fpga_main_Probe_Filters_0_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
hexmask.long 0x1C 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_soc2fpga_main_Probe_Filters_0_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
hexmask.long 0x20 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_soc2fpga_main_Probe_Filters_0_Length,Register Filters_0_Length"
hexmask.long 0x24 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_soc2fpga_main_Probe_Filters_0_Urgency,Register Filters_0_Urgency"
hexmask.long 0x28 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0.--1. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0xCE0++0x2B
line.long 0x0 "probe_soc2fpga_main_Probe_Filters_1_RouteIdBase,Register Filters_1_RouteIdBase"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x0 0.--24. 1. "FILTERS_1_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_soc2fpga_main_Probe_Filters_1_RouteIdMask,Register Filters_1_RouteIdMask"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x4 0.--24. 1. "FILTERS_1_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId & RouteIdMask = RouteIdBase & RouteIdMask."
line.long 0x8 "probe_soc2fpga_main_Probe_Filters_1_AddrBase_Low,Register Filters_1_AddrBase_Low"
hexmask.long 0x8 0.--31. 1. "FILTERS_1_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_soc2fpga_main_Probe_Filters_1_AddrBase_High,Register Filters_1_AddrBase_High"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_1_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_soc2fpga_main_Probe_Filters_1_WindowSize,Register Filters_1_WindowSize"
hexmask.long 0x10 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_1_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows.."
line.long 0x14 "probe_soc2fpga_main_Probe_Filters_1_SecurityBase,Register Filters_1_SecurityBase"
hexmask.long 0x14 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0.--1. "FILTERS_1_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_soc2fpga_main_Probe_Filters_1_SecurityMask,Register Filters_1_SecurityMask"
hexmask.long 0x18 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0.--1. "FILTERS_1_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security & SecurityMask = SecurityBase & SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_soc2fpga_main_Probe_Filters_1_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
hexmask.long 0x1C 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_soc2fpga_main_Probe_Filters_1_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
hexmask.long 0x20 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_soc2fpga_main_Probe_Filters_1_Length,Register Filters_1_Length"
hexmask.long 0x24 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_1_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_soc2fpga_main_Probe_Filters_1_Urgency,Register Filters_1_Urgency"
hexmask.long 0x28 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0.--1. "FILTERS_1_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0xE00++0xB
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_0_PortSel,Register Counters_0_PortSel"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "COUNTERS_0_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time  with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_Counters_0_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x4 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x8 "probe_soc2fpga_main_Probe_Counters_0_AlarmMode,Register Counters_0_AlarmMode"
hexmask.long 0x8 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0xE0C++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_0_Val,Register Counters_0_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0xE10++0xB
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_1_PortSel,Register Counters_1_PortSel"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "COUNTERS_1_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time  with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_Counters_1_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x4 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x8 "probe_soc2fpga_main_Probe_Counters_1_AlarmMode,Register Counters_1_AlarmMode"
hexmask.long 0x8 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0xE1C++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_1_Val,Register Counters_1_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0xE20++0xB
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_2_PortSel,Register Counters_2_PortSel"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "COUNTERS_2_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time  with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_Counters_2_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x4 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x8 "probe_soc2fpga_main_Probe_Counters_2_AlarmMode,Register Counters_2_AlarmMode"
hexmask.long 0x8 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0xE2C++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_2_Val,Register Counters_2_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0xE30++0xB
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_3_PortSel,Register Counters_3_PortSel"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "COUNTERS_3_PORTSEL,Register PortSel indicates which NTTP link is associated with the counter. The register can be changed at any time  with the change effective immediately. The LUT and FILTx sources do not depend on this NTTP port selection." "0,1"
line.long 0x4 "probe_soc2fpga_main_Probe_Counters_3_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x4 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x8 "probe_soc2fpga_main_Probe_Counters_3_AlarmMode,Register Counters_3_AlarmMode"
hexmask.long 0x8 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0xE3C++0x3
line.long 0x0 "probe_soc2fpga_main_Probe_Counters_3_Val,Register Counters_3_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
rgroup.long 0x1000++0x7
line.long 0x0 "probe_emac_main_TransactionStatProfiler_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "probe_emac_main_TransactionStatProfiler_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x1008++0x7
line.long 0x0 "probe_emac_main_TransactionStatProfiler_En,Register En"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1"
line.long 0x4 "probe_emac_main_TransactionStatProfiler_Mode,Register Mode"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay  Mode = 1 for Pending)" "0,1"
group.long 0x102C++0xB
line.long 0x0 "probe_emac_main_TransactionStatProfiler_Thresholds_0_0,Register Thresholds_0_0"
hexmask.long 0x0 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." "0,1,2,3"
line.long 0x4 "probe_emac_main_TransactionStatProfiler_Thresholds_0_1,Register Thresholds_0_1"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." "0,1,2,3"
line.long 0x8 "probe_emac_main_TransactionStatProfiler_Thresholds_0_2,Register Thresholds_0_2"
hexmask.long 0x8 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0.--1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." "0,1,2,3"
rgroup.long 0x106C++0x3
line.long 0x0 "probe_emac_main_TransactionStatProfiler_OverflowStatus,Register OverflowStatus"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1"
group.long 0x1070++0xB
line.long 0x0 "probe_emac_main_TransactionStatProfiler_OverflowReset,Register OverflowReset"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1"
line.long 0x4 "probe_emac_main_TransactionStatProfiler_PendingEventMode,Register PendingEventMode"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE)  and when register mode is set to PENDING  the pending event is generated on each cycle when the counter is greater than.." "0,1"
line.long 0x8 "probe_emac_main_TransactionStatProfiler_PreScaler,Register PreScaler"
hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0  pre-scaling is disabled. If set to any other supported value 'n'  the threshold counter value is divided by (n + 1)."
rgroup.long 0x1400++0x7
line.long 0x0 "probe_io_tbu_main_Probe_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "probe_io_tbu_main_Probe_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x1408++0x7
line.long 0x0 "probe_io_tbu_main_Probe_MainCtl,Register MainCtl contains probe global control bits. The register has seven bit fields:"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 7. "FILTBYTEALWAYSCHAINABLEEN,When set to 0  filters are mapped to all statistic counters when counting bytes or enabled bytes. Therefore  only filter events mapped to even counters can be counted using a pair of chained counters.When set to 1  filters are.." "0,1"
newline
rbitfld.long 0x0 6. "INTRUSIVEMODE,When set to 1  register field IntrusiveMode enables trace operation in Intrusive flow-control mode. When set to 0  the register enables trace operation in Overflow flow-control mode" "0,1"
newline
bitfld.long 0x0 5. "STATCONDDUMP,When set  register field StatCondDump enables the dump of a statistics frame to the range of counter values set for registers StatAlarmMin  StatAlarmMax  and AlarmMode. This field also renders register StatAlarmStatus inoperative. When.." "0,1"
newline
bitfld.long 0x0 4. "ALARMEN,When set  register field AlarmEn enables the probe to collect alarm-related information. When the register field bit is null  both TraceAlarm and StatAlarm outputs are driven to 0." "0,1"
newline
bitfld.long 0x0 3. "STATEN,When set to 1  register field StatEn enables statistics profiling. The probe sendS statistics results to the output for signal ObsTx. All statistics counters are cleared when the StatEn bit goes from 0 to 1. When set to 0  counters are disabled." "0,1"
newline
bitfld.long 0x0 2. "PAYLOADEN,Register field PayloadEn  when set to 1  enables traces to contain headers and payload. When set ot 0  only headers are reported." "0,1"
newline
bitfld.long 0x0 1. "TRACEEN,Register field TraceEn enables the probe to send filtered packets (Trace) on the ObsTx observation output." "0,1"
newline
bitfld.long 0x0 0. "ERREN,Register field ErrEn enables the probe to send on the ObsTx output any packet with Error status  independently of filtering mechanisms  thus constituting a simple supplementary global filter." "0,1"
line.long 0x4 "probe_io_tbu_main_Probe_CfgCtl,Stores global enable and active bits related to the probe."
hexmask.long 0x4 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x4 1. "ACTIVE,Active status of the packet probe." "0,1"
newline
bitfld.long 0x4 0. "GLOBALEN,Enables or disables the tracing and statistics collection subsystems of the packet probe." "0,1"
group.long 0x1414++0x7
line.long 0x0 "probe_io_tbu_main_Probe_FilterLut,Register FilterLut"
hexmask.long 0x0 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--3. 1. "FILTERLUT,Register FilterLut contains a look-up table that is used to combine filter outputs in order to trace packets. Packet tracing is enabled when the FilterLut bit of index (FNout ... F0out) is equal to 1.The number of bits in register FilterLut is.."
line.long 0x4 "probe_io_tbu_main_Probe_TraceAlarmEn,Register TraceAlarmEn"
hexmask.long 0x4 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--2. "TRACEALARMEN,Register TraceAlarmEn controls which lookup table or filter can set the TraceAlarm signal output once the trace alarm status is set. The number of bits in register TraceAlarmEn is determined by the value set for parameter nFilter + 1.Bit.." "0,1,2,3,4,5,6,7"
rgroup.long 0x141C++0x3
line.long 0x0 "probe_io_tbu_main_Probe_TraceAlarmStatus,Register TraceAlarmStatus"
hexmask.long 0x0 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--2. "TRACEALARMSTATUS,Register TraceAlarmStatus is a read-only register that indicates which lookup table or filter has been matched by a packet  independently of register TraceAlarmEn bit configuration. The number of bits in TraceAlarmStatus is determined by.." "0,1,2,3,4,5,6,7"
group.long 0x1420++0xF
line.long 0x0 "probe_io_tbu_main_Probe_TraceAlarmClr,Register TraceAlarmClr"
hexmask.long 0x0 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0.--2. "TRACEALARMCLR,Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0  TraceAlarmClr is reserved.NOTE The.." "0,1,2,3,4,5,6,7"
line.long 0x4 "probe_io_tbu_main_Probe_StatPeriod,Register StatPeriod"
hexmask.long 0x4 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--4. 1. "STATPERIOD,Register StatPeriod is a 5-bit register that sets a period  within a range of 2 cycles to 2 gigacycles  during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation.."
line.long 0x8 "probe_io_tbu_main_Probe_StatGo,Register StatGo"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x8 0. "STATGO,Writing a 1 to the 1-bit pulse register StatGo generates a statistics dump.The register is active when statistics collection operates in manual mode  that is  when register StatPeriod is set to 0.NOTE The written value is not stored in StatGo. A.." "0,1"
line.long 0xC "probe_io_tbu_main_Probe_StatAlarmMin,Register StatAlarmMin"
hexmask.long 0xC 0.--31. 1. "STATALARMMIN,Register StatAlarmMin contains the minimum count value used in statistics alarm comparisons. The number of bits is equal to twice the value set forparameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
group.long 0x1434++0x3
line.long 0x0 "probe_io_tbu_main_Probe_StatAlarmMax,Register StatAlarmMax"
hexmask.long 0x0 0.--31. 1. "STATALARMMAX,Register StatAlarmMax contains the maximum count value used in statistics alarm comparisons.The number of bits is equal to twice the value set for parameter wStatisticsCounter. When parameter statisticsCounterAlarm is set to False .."
rgroup.long 0x143C++0x3
line.long 0x0 "probe_io_tbu_main_Probe_StatAlarmStatus,Register StatAlarmStatus"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "STATALARMSTATUS,Register StatAlarmStatus is a read-only 1-bit register indicating that at least one statistics counter has exceeded the programmed values for registers StatAlarmMin or StatAlarmMax. Output signal StatAlarm is equal to the values stored in.." "0,1"
group.long 0x1440++0x7
line.long 0x0 "probe_io_tbu_main_Probe_StatAlarmClr,Register StatAlarmClr"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0. "STATALARMCLR,Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False  StatAlarmClr is reserved.NOTE The written value is not stored in.." "0,1"
line.long 0x4 "probe_io_tbu_main_Probe_StatAlarmEn,Register StatAlarmEn"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "STATALARMEN,Register StatAlarmEn is a 1-bit register. When set to 0 it masks StatAlarm and CtiTrigOut(1) signal interrupts." "0,1"
group.long 0x1480++0x2B
line.long 0x0 "probe_io_tbu_main_Probe_Filters_0_RouteIdBase,Register Filters_0_RouteIdBase"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x0 0.--24. 1. "FILTERS_0_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_io_tbu_main_Probe_Filters_0_RouteIdMask,Register Filters_0_RouteIdMask"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x4 0.--24. 1. "FILTERS_0_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId & RouteIdMask = RouteIdBase & RouteIdMask."
line.long 0x8 "probe_io_tbu_main_Probe_Filters_0_AddrBase_Low,Register Filters_0_AddrBase_Low"
hexmask.long 0x8 0.--31. 1. "FILTERS_0_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_io_tbu_main_Probe_Filters_0_AddrBase_High,Register Filters_0_AddrBase_High"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_0_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_io_tbu_main_Probe_Filters_0_WindowSize,Register Filters_0_WindowSize"
hexmask.long 0x10 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_0_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows.."
line.long 0x14 "probe_io_tbu_main_Probe_Filters_0_SecurityBase,Register Filters_0_SecurityBase"
hexmask.long 0x14 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0.--1. "FILTERS_0_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_io_tbu_main_Probe_Filters_0_SecurityMask,Register Filters_0_SecurityMask"
hexmask.long 0x18 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0.--1. "FILTERS_0_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security & SecurityMask = SecurityBase & SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_io_tbu_main_Probe_Filters_0_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
hexmask.long 0x1C 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_io_tbu_main_Probe_Filters_0_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
hexmask.long 0x20 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_io_tbu_main_Probe_Filters_0_Length,Register Filters_0_Length"
hexmask.long 0x24 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_0_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_io_tbu_main_Probe_Filters_0_Urgency,Register Filters_0_Urgency"
hexmask.long 0x28 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0.--1. "FILTERS_0_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x14E0++0x2B
line.long 0x0 "probe_io_tbu_main_Probe_Filters_1_RouteIdBase,Register Filters_1_RouteIdBase"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x0 0.--24. 1. "FILTERS_1_ROUTEIDBASE,Register RouteIdBase contains the RouteId-lsbFilterRouteId bits base used to filter packets."
line.long 0x4 "probe_io_tbu_main_Probe_Filters_1_RouteIdMask,Register Filters_1_RouteIdMask"
hexmask.long.byte 0x4 25.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x4 0.--24. 1. "FILTERS_1_ROUTEIDMASK,Register RouteIdMask contains the RouteId-lsbFilterRouteId mask used to filter packets. A packet is a candidate when packet.RouteId>>lsbFilterRouteId & RouteIdMask = RouteIdBase & RouteIdMask."
line.long 0x8 "probe_io_tbu_main_Probe_Filters_1_AddrBase_Low,Register Filters_1_AddrBase_Low"
hexmask.long 0x8 0.--31. 1. "FILTERS_1_ADDRBASE_LOW,Address LSB register."
line.long 0xC "probe_io_tbu_main_Probe_Filters_1_AddrBase_High,Register Filters_1_AddrBase_High"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--7. 1. "FILTERS_1_ADDRBASE_HIGH,Address MSB register."
line.long 0x10 "probe_io_tbu_main_Probe_Filters_1_WindowSize,Register Filters_1_WindowSize"
hexmask.long 0x10 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--5. 1. "FILTERS_1_WINDOWSIZE,Register WindowSize contains the encoded address mask used to filter packets. The effective Mask value is equal to ~(2max(WindowSize  packet.Len) - 1). A packet is a candidate when packet.Addr & Mask = AddrBase & Mask. This allows.."
line.long 0x14 "probe_io_tbu_main_Probe_Filters_1_SecurityBase,Register Filters_1_SecurityBase"
hexmask.long 0x14 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0.--1. "FILTERS_1_SECURITYBASE,Register SecurityBase contains the security base used to filter packets." "0,1,2,3"
line.long 0x18 "probe_io_tbu_main_Probe_Filters_1_SecurityMask,Register Filters_1_SecurityMask"
hexmask.long 0x18 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0.--1. "FILTERS_1_SECURITYMASK,Register SecurityMask is contains the security mask used to filter packets. A packet is a candidate when: packet.Security & SecurityMask = SecurityBase & SecurityMasks." "0,1,2,3"
line.long 0x1C "probe_io_tbu_main_Probe_Filters_1_Opcode,Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):"
hexmask.long 0x1C 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 3. "URGEN,Selects URG packets (urgency)." "0,1"
newline
bitfld.long 0x1C 2. "LOCKEN,Selects RDX-WR  RDL  WRC and Linked sequence." "0,1"
newline
bitfld.long 0x1C 1. "WREN,Selects WR packets." "0,1"
newline
bitfld.long 0x1C 0. "RDEN,Selects RD packets." "0,1"
line.long 0x20 "probe_io_tbu_main_Probe_Filters_1_Status,Register Status is 2-bit register that selects candidate packets based on packet status."
hexmask.long 0x20 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 1. "RSPEN,Selects RSP and FAIL-CONT status packets." "0,1"
newline
bitfld.long 0x20 0. "REQEN,Selects REQ status packets." "0,1"
line.long 0x24 "probe_io_tbu_main_Probe_Filters_1_Length,Register Filters_1_Length"
hexmask.long 0x24 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--3. 1. "FILTERS_1_LENGTH,Register Length is 4-bit register that selects candidate packets if their number of bytes is less than or equal to 2**Length."
line.long 0x28 "probe_io_tbu_main_Probe_Filters_1_Urgency,Register Filters_1_Urgency"
hexmask.long 0x28 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 0.--1. "FILTERS_1_URGENCY,Register Urgency contains the minimum urgency level used to filter packets. A packet is a candidate when its socket urgency is greater than or equal to the urgency specified in the register." "0,1,2,3"
group.long 0x1604++0x7
line.long 0x0 "probe_io_tbu_main_Probe_Counters_0_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 6.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 5. "EXTEVENT,When greater than 0  the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_io_tbu_main_Probe_Counters_0_AlarmMode,Register Counters_0_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_0_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0x160C++0x3
line.long 0x0 "probe_io_tbu_main_Probe_Counters_0_Val,Register Counters_0_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_0_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x1614++0x7
line.long 0x0 "probe_io_tbu_main_Probe_Counters_1_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 6.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 5. "EXTEVENT,When greater than 0  the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_io_tbu_main_Probe_Counters_1_AlarmMode,Register Counters_1_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_1_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0x161C++0x3
line.long 0x0 "probe_io_tbu_main_Probe_Counters_1_Val,Register Counters_1_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_1_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x1624++0x7
line.long 0x0 "probe_io_tbu_main_Probe_Counters_2_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 6.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 5. "EXTEVENT,When greater than 0  the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_io_tbu_main_Probe_Counters_2_AlarmMode,Register Counters_2_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_2_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0x162C++0x3
line.long 0x0 "probe_io_tbu_main_Probe_Counters_2_Val,Register Counters_2_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_2_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
group.long 0x1634++0x7
line.long 0x0 "probe_io_tbu_main_Probe_Counters_3_Src,Register CntSrc indicates the event source used to increment the counter. Unassigned values (non-existing Press level or ExtEvent index. or unimplemented Filter) are equivalent to OFF."
hexmask.long 0x0 6.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 5. "EXTEVENT,When greater than 0  the entire register value is used to select an external hardware event source. The index of the external event is equal to {ExtEvent IntEvent}." "0,1"
newline
hexmask.long.byte 0x0 0.--4. 1. "INTEVENT,Internal packet event"
line.long 0x4 "probe_io_tbu_main_Probe_Counters_3_AlarmMode,Register Counters_3_AlarmMode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "COUNTERS_3_ALARMMODE,Register AlarmMode is a 2-bit register that is present when parameter statisticsCounterAlarm is set to True. The register defines the statistics-alarm behavior of the counter." "0: the comparison is disabled.,1: if the value of the counter is less than the..,2: if the value of the counter is greater than the..,3: if the value of the counter is less than the.."
rgroup.long 0x163C++0x3
line.long 0x0 "probe_io_tbu_main_Probe_Counters_3_Val,Register Counters_3_Val"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "COUNTERS_3_VAL,Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output  or when statisticscollection is suspended subsequent to triggers or signal statSuspend."
rgroup.long 0x1800++0x7
line.long 0x0 "probe_io_tbu_main_TransactionStatProfiler_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "probe_io_tbu_main_TransactionStatProfiler_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x1808++0x7
line.long 0x0 "probe_io_tbu_main_TransactionStatProfiler_En,Register En"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "EN,Register En is a 1-bit register that enables the transaction probe counter unit." "0,1"
line.long 0x4 "probe_io_tbu_main_TransactionStatProfiler_Mode,Register Mode"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "MODE,Register Mode sets the counting mode per observed port. Each bit per observation port defines the incrementing mode. (Mode = 0 for Delay  Mode = 1 for Pending)" "0,1"
group.long 0x182C++0xB
line.long 0x0 "probe_io_tbu_main_TransactionStatProfiler_Thresholds_0_0,Register Thresholds_0_0"
hexmask.long 0x0 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--1. "THRESHOLDS_0_0,Register Thresholds_i_j contains the threshold index '0' that allows computation of threshold values." "0,1,2,3"
line.long 0x4 "probe_io_tbu_main_TransactionStatProfiler_Thresholds_0_1,Register Thresholds_0_1"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "THRESHOLDS_0_1,Register Thresholds_i_j contains the threshold index '1' that allows computation of threshold values." "0,1,2,3"
line.long 0x8 "probe_io_tbu_main_TransactionStatProfiler_Thresholds_0_2,Register Thresholds_0_2"
hexmask.long 0x8 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0.--1. "THRESHOLDS_0_2,Register Thresholds_i_j contains the threshold index '2' that allows computation of threshold values." "0,1,2,3"
rgroup.long 0x186C++0x3
line.long 0x0 "probe_io_tbu_main_TransactionStatProfiler_OverflowStatus,Register OverflowStatus"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "OVERFLOWSTATUS,Bit n of register OverflowStatus is set to 1 if a start event occurs on observed port n and eitherof the following conditions occurs: All tenure counters allocated to the port are already in use. No tenure lines have been allocated to the.." "0,1"
group.long 0x1870++0xB
line.long 0x0 "probe_io_tbu_main_TransactionStatProfiler_OverflowReset,Register OverflowReset"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 0. "OVERFLOWRESET,Register OverflowReset is a pulse register that clears overflow status bits per observed port on each write access. OverflowReset = nObservable. Writing 0x2 clears the overflow status of observed port 1." "0,1"
line.long 0x4 "probe_io_tbu_main_TransactionStatProfiler_PendingEventMode,Register PendingEventMode"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "PENDINGEVENTMODE,Register pendingEventMode is a 1-bit register that configures the pending event mode. When set to 0 (CYCLE)  and when register mode is set to PENDING  the pending event is generated on each cycle when the counter is greater than.." "0,1"
line.long 0x8 "probe_io_tbu_main_TransactionStatProfiler_PreScaler,Register PreScaler"
hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 0.--7. 1. "PRESCALER,8Register Prescaler is an-bit pre-scaling register that accepts any pre-scaling value between 1 (default) and 256. If set to 0  pre-scaling is disabled. If set to any other supported value 'n'  the threshold counter value is divided by (n + 1)."
rgroup.long 0x2000++0x7
line.long 0x0 "ccu_ios_I_main_QosGenerator_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "ccu_ios_I_main_QosGenerator_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x2008++0x13
line.long 0x0 "ccu_ios_I_main_QosGenerator_Priority,Priority register."
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8.--9. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3"
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--1. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3"
line.long 0x4 "ccu_ios_I_main_QosGenerator_Mode,Register Mode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "ccu_ios_I_main_QosGenerator_Bandwidth,Register Bandwidth"
hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "ccu_ios_I_main_QosGenerator_Saturation,Register Saturation"
hexmask.long.tbyte 0xC 10.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "ccu_ios_I_main_QosGenerator_ExtControl,External inputs control."
hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
rgroup.long 0x2080++0x7
line.long 0x0 "dma_tbu_m_I_main_QosGenerator_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "dma_tbu_m_I_main_QosGenerator_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x2088++0x13
line.long 0x0 "dma_tbu_m_I_main_QosGenerator_Priority,Priority register."
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8.--9. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3"
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--1. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3"
line.long 0x4 "dma_tbu_m_I_main_QosGenerator_Mode,Register Mode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "dma_tbu_m_I_main_QosGenerator_Bandwidth,Register Bandwidth"
hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "dma_tbu_m_I_main_QosGenerator_Saturation,Register Saturation"
hexmask.long.tbyte 0xC 10.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "dma_tbu_m_I_main_QosGenerator_ExtControl,External inputs control."
hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
rgroup.long 0x2100++0x7
line.long 0x0 "emac_tbu_m_I_main_QosGenerator_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "emac_tbu_m_I_main_QosGenerator_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x2108++0x13
line.long 0x0 "emac_tbu_m_I_main_QosGenerator_Priority,Priority register."
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8.--9. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3"
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--1. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3"
line.long 0x4 "emac_tbu_m_I_main_QosGenerator_Mode,Register Mode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "emac_tbu_m_I_main_QosGenerator_Bandwidth,Register Bandwidth"
hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "emac_tbu_m_I_main_QosGenerator_Saturation,Register Saturation"
hexmask.long.tbyte 0xC 10.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "emac_tbu_m_I_main_QosGenerator_ExtControl,External inputs control."
hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
rgroup.long 0x2180++0x7
line.long 0x0 "io_tbu_m_I_main_QosGenerator_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "io_tbu_m_I_main_QosGenerator_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x2188++0x13
line.long 0x0 "io_tbu_m_I_main_QosGenerator_Priority,Priority register."
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8.--9. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3"
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--1. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3"
line.long 0x4 "io_tbu_m_I_main_QosGenerator_Mode,Register Mode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "io_tbu_m_I_main_QosGenerator_Bandwidth,Register Bandwidth"
hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "io_tbu_m_I_main_QosGenerator_Saturation,Register Saturation"
hexmask.long.tbyte 0xC 10.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "io_tbu_m_I_main_QosGenerator_ExtControl,External inputs control."
hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
rgroup.long 0x2200++0x7
line.long 0x0 "sdm_tbu_m_I_main_QosGenerator_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "sdm_tbu_m_I_main_QosGenerator_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x2208++0x13
line.long 0x0 "sdm_tbu_m_I_main_QosGenerator_Priority,Priority register."
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8.--9. "P1,In Regulator mode  defines the HIGH hurry level. In Fixed/Limiter mode  defines the Urgency level for READ transactions." "0,1,2,3"
newline
hexmask.long.byte 0x0 2.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0.--1. "P0,In Regulator mode  defines the LOW hurry level. In Fixed/Limiter mode  defines the Urgency level for WRITE transactions." "0,1,2,3"
line.long 0x4 "sdm_tbu_m_I_main_QosGenerator_Mode,Register Mode"
hexmask.long 0x4 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0.--1. "MODE,Functional Mode: 0=Fixed  1=Limiter  2=Bypass  3=Regulator." "0: Fixed,1: Limiter,2: Bypass,3: Regulator"
line.long 0x8 "sdm_tbu_m_I_main_QosGenerator_Bandwidth,Register Bandwidth"
hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x8 0.--11. 1. "BANDWIDTH,Defines the bandwidth threshold in 1/256th-byte-per-cycle units. In other words  the desired rate in MBps is divided by frequency in MHz of the NIU  and then multiplied by 256."
line.long 0xC "sdm_tbu_m_I_main_QosGenerator_Saturation,Register Saturation"
hexmask.long.tbyte 0xC 10.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0xC 0.--9. 1. "SATURATION,Defines the size of the bandwidth counter  that is  the measurement window  in 16-byte units. In other words  the desired number of bytes divided by 16."
line.long 0x10 "sdm_tbu_m_I_main_QosGenerator_ExtControl,External inputs control."
hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 3. "EXTLIMITEN,When register field ExtLimitEn is set  the bandwidth limiter is enabled when input signal ExtThr is asserted. When the signal is not asserted  the limiter is disabled: bandwidth is not limited  and the counter is stuck to 0. When the bit is.." "0,1"
newline
bitfld.long 0x10 2. "INTCLKEN,When set to 1  register field IntClkEn causes the QoS generator to use the NIU clock for bandwidth calculation. When set to 0  and if configuration parameter useExternalReference is set to True  an external reference clock at the socket is used.." "0,1"
newline
bitfld.long 0x10 1. "EXTTHREN,When register field ExtThrEn is set  internal signals Urgency  Press and Hurry are driven  when input signal ExtThr is low  by the value in register Priority field P0. When ExtThr is high  they are drven by the value in register Priority field P1." "0,1"
newline
bitfld.long 0x10 0. "SOCKETQOSEN,Register field SocketQosEn determines how priority levels are driven when QoS generators and socket interfaces alternatively drive the levels for Urgency  Pressure  and Hurry signals: When set to 0  the QoS generator drives the levels. When.." "0,1"
rgroup.long 0x2400++0x7
line.long 0x0 "emac_tbu_m_I_main_TransactionStatFilter_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "emac_tbu_m_I_main_TransactionStatFilter_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x2408++0xF
line.long 0x0 "emac_tbu_m_I_main_TransactionStatFilter_Mode,Register Mode"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1"
line.long 0x4 "emac_tbu_m_I_main_TransactionStatFilter_AddrBase_Low,Register AddrBase_Low"
hexmask.long 0x4 0.--31. 1. "ADDRBASE_LOW,Address base LSB register."
line.long 0x8 "emac_tbu_m_I_main_TransactionStatFilter_AddrBase_High,Register AddrBase_High"
hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 0.--7. 1. "ADDRBASE_HIGH,Address base MSB register."
line.long 0xC "emac_tbu_m_I_main_TransactionStatFilter_AddrWindowSize,Register AddrWindowSize"
hexmask.long 0xC 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr & AddrMask = AddrBase & AddrMask."
group.long 0x2420++0x1B
line.long 0x0 "emac_tbu_m_I_main_TransactionStatFilter_Opcode,This register selects candidate packets based on packet opcodes. (0 disables the filter):"
hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "WREN,When set to 1  selects WR requests." "0,1"
newline
bitfld.long 0x0 0. "RDEN,When set to 1  selects RD requests." "0,1"
line.long 0x4 "emac_tbu_m_I_main_TransactionStatFilter_UserBase,Register UserBase"
hexmask.long 0x4 0.--31. 1. "USERBASE,This register contains the User base used to filter requests."
line.long 0x8 "emac_tbu_m_I_main_TransactionStatFilter_UserMask,Register UserMask"
hexmask.long 0x8 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests."
line.long 0xC "emac_tbu_m_I_main_TransactionStatFilter_SecurityBase,Register SecurityBase"
hexmask.long 0xC 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 0.--1. "SECURITYBASE,This register contains the Security base used to filter requests." "0,1,2,3"
line.long 0x10 "emac_tbu_m_I_main_TransactionStatFilter_SecurityMask,Register SecurityMask"
hexmask.long 0x10 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 0.--1. "SECURITYMASK,This register contains the Security mask used to filter requests." "0,1,2,3"
line.long 0x14 "emac_tbu_m_I_main_TransactionStatFilter_UserBaseHigh,Register UserBaseHigh"
hexmask.long.byte 0x14 27.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x14 0.--26. 1. "USERBASEHIGH,This register contains the User base used to filter requests."
line.long 0x18 "emac_tbu_m_I_main_TransactionStatFilter_UserMaskHigh,Register UserMaskHigh"
hexmask.long.byte 0x18 27.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x18 0.--26. 1. "USERMASKHIGH,This register contains the User mask used to filter requests."
rgroup.long 0x2480++0x7
line.long 0x0 "io_tbu_m_I_main_TransactionStatFilter_Id_CoreId,Stores the Core Id and its checksum."
hexmask.long.tbyte 0x0 8.--31. 1. "CORECHECKSUM,Field containing a checksum of the parameters of the IP."
newline
hexmask.long.byte 0x0 0.--7. 1. "CORETYPEID,Field identifying the type of IP."
line.long 0x4 "io_tbu_m_I_main_TransactionStatFilter_Id_RevisionId,Stores a user-defined Id and the software revision."
hexmask.long.tbyte 0x4 8.--31. 1. "FLEXNOCID,Field containing the build revision of the software used to generate the IP HDL code."
newline
hexmask.long.byte 0x4 0.--7. 1. "USERID,Field containing a user defined value  not used anywhere inside the IP itself."
group.long 0x2488++0xF
line.long 0x0 "io_tbu_m_I_main_TransactionStatFilter_Mode,Register Mode"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "MODE,Register Mode is a 1-bit register that sets the filtering mode as follows: handshake Mode = 0 or latency Mode = 1." "0,1"
line.long 0x4 "io_tbu_m_I_main_TransactionStatFilter_AddrBase_Low,Register AddrBase_Low"
hexmask.long 0x4 0.--31. 1. "ADDRBASE_LOW,Address base LSB register."
line.long 0x8 "io_tbu_m_I_main_TransactionStatFilter_AddrBase_High,Register AddrBase_High"
hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 0.--7. 1. "ADDRBASE_HIGH,Address base MSB register."
line.long 0xC "io_tbu_m_I_main_TransactionStatFilter_AddrWindowSize,Register AddrWindowSize"
hexmask.long 0xC 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--5. 1. "ADDRWINDOWSIZE,Register AddrWindowSize contains the encoded address mask used to filter packets: the effective Mask value is equal to ~(2**AddrWindowSize - 1). A packet is a candidate when ReqInfo.Addr & AddrMask = AddrBase & AddrMask."
group.long 0x24A0++0x1B
line.long 0x0 "io_tbu_m_I_main_TransactionStatFilter_Opcode,This register selects candidate packets based on packet opcodes. (0 disables the filter):"
hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "WREN,When set to 1  selects WR requests." "0,1"
newline
bitfld.long 0x0 0. "RDEN,When set to 1  selects RD requests." "0,1"
line.long 0x4 "io_tbu_m_I_main_TransactionStatFilter_UserBase,Register UserBase"
hexmask.long 0x4 0.--31. 1. "USERBASE,This register contains the User base used to filter requests."
line.long 0x8 "io_tbu_m_I_main_TransactionStatFilter_UserMask,Register UserMask"
hexmask.long 0x8 0.--31. 1. "USERMASK,This register contains the User mask used to filter requests."
line.long 0xC "io_tbu_m_I_main_TransactionStatFilter_SecurityBase,Register SecurityBase"
hexmask.long 0xC 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 0.--1. "SECURITYBASE,This register contains the Security base used to filter requests." "0,1,2,3"
line.long 0x10 "io_tbu_m_I_main_TransactionStatFilter_SecurityMask,Register SecurityMask"
hexmask.long 0x10 2.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 0.--1. "SECURITYMASK,This register contains the Security mask used to filter requests." "0,1,2,3"
line.long 0x14 "io_tbu_m_I_main_TransactionStatFilter_UserBaseHigh,Register UserBaseHigh"
hexmask.long.byte 0x14 27.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x14 0.--26. 1. "USERBASEHIGH,This register contains the User base used to filter requests."
line.long 0x18 "io_tbu_m_I_main_TransactionStatFilter_UserMaskHigh,Register UserMaskHigh"
hexmask.long.byte 0x18 27.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long 0x18 0.--26. 1. "USERMASKHIGH,This register contains the User mask used to filter requests."
tree.end
tree.end
tree "OCRAM (On-Chip RAM)"
base ad:0x0
tree "OCRAM_ECC"
base ad:0x108CC000
rgroup.long 0x0++0x7
line.long 0x0 "IP_REV_ID,<p>IP slicon revision ID</p>"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 0.--15. 1. "SIREV,<p>IP Rev#</p>"
line.long 0x4 "IP_REV_ID2,<p>IP memory configuration</p>"
hexmask.long.word 0x4 20.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "LUT_TBL_DEP,<p>Lookup Table Depth.</p>"
newline
bitfld.long 0x4 13.--15. "RAM_TYPE,<p>Defines RAM type.</p>" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 10.--12. "ECC_SIZE,<p>ECC Size.</p>" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x4 5.--9. 1. "DAT,<p>Data Width. This field indicates the IP RAM data width. Refer to IP spec for exact data width size.</p>"
hexmask.long.byte 0x4 0.--4. 1. "ADDR,<p>Number of address bits (This represent the memory size)Support 32 - 0 address bits.</p>"
group.long 0x8++0x23
line.long 0x0 "CTRL,ECC Control Register"
hexmask.long.byte 0x0 25.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 24. "INITB,Start for the hardware memory initialization PORTB." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 16. "INITA,Start for the hardware memory initialization PORTA." "0,1"
newline
hexmask.long.byte 0x0 10.--15. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 9. "CNT_RSTB,Clear internal single-bit error counter B value to zero" "0,1"
newline
bitfld.long 0x0 8. "CNT_RSTA,Clear internal single-bit error counter A value to zero" "0,1"
hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "ECC_SLVERR_DIS,Enable to prevent double-bit ECC error from triggering BUS ERROR on IP-interface." "0,1"
bitfld.long 0x0 0. "ECC_EN,Enable for the ECC detection and correction logic." "0,1"
line.long 0x4 "INITSTAT,Initialization status used to indicate completion of hardware memory initialization done through CTRL.INITA / CTRL.INITB"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x4 8. "INITCOMPLETEB,Indicate hardware memory initialization has completed on PORTB." "0,1"
newline
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "INITCOMPLETEA,Indicate hardware memory initialization has completed on PORTA." "0,1"
line.long 0x8 "ERRINTEN,Error Interrupt enable"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "SERRINTEN,This bit is used to enable single bit error interrupt of ECC RAM system" "0,1"
line.long 0xC "ERRINTENS,Error interrupt set"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "SERRINTS,This bit is used to enable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x10 "ERRINTENR,Error Interrupt reset"
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x10 0. "SERRINTR,This bit is used to disable ERRINTENS.SERRINTEN field" "0,1"
line.long 0x14 "INTMODE,Interrupt modes of ECC RAM system"
hexmask.long.word 0x14 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x14 16. "INTONCMP,Enable interrupt on compare." "0: Disable interrupt on compare feature,1: Enable interrupt on compare feature"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x14 8. "INTONOVF,Enable interrupt on overflow." "0: Disable interrupt on LUT overflow,1: Enable interrupt on LUT overflow"
newline
hexmask.long.byte 0x14 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x14 0. "INTMODE,Interrupt mode for single-bit error" "0: Enable interrupt on all error mode. Every..,1: Enable interrupt on distinct error. Every.."
line.long 0x18 "INTSTAT,This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled. serr_req signal will be asserted."
hexmask.long.byte 0x18 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x18 24. "DERRPENB,Double-bit error pending PORTB." "0,1"
newline
hexmask.long.byte 0x18 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x18 16. "SERRPENB,Single-bit error pending for PORTB." "0,1"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
eventfld.long 0x18 8. "DERRPENA,Double-bit error pending for PORTA." "0,1"
newline
hexmask.long.byte 0x18 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x18 0. "SERRPENA,Single-bit error pending for PORTA." "0,1"
line.long 0x1C "INTTEST,This bits is used to test interrupt from ECC RAM to GIC"
hexmask.long.byte 0x1C 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x1C 24. "TDERRB,Test PORTB Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x1C 16. "TSERRB,Test PORTB Single-bit error." "0,1"
newline
hexmask.long.byte 0x1C 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x1C 8. "TDERRA,Test PORTA Double-bit error." "0,1"
newline
hexmask.long.byte 0x1C 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x1C 0. "TSERRA,Test PORTA Single-bit error." "0,1"
line.long 0x20 "MODSTAT,<p>Mode status flag</p>"
hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved bitfield added by Magillem"
eventfld.long 0x20 5. "RMW_DERRB,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
newline
eventfld.long 0x20 4. "RMW_DERRA,This bit indicates that a RMW access due to a subword access generated a DERR" "0,1"
eventfld.long 0x20 3. "RMW_SERRB,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
newline
eventfld.long 0x20 2. "RMW_SERRA,This bit indicates that a RMW access due to a subword access generated a SERR" "0,1"
eventfld.long 0x20 1. "CMPFLGB,Port B compare status flag" "0,1"
newline
eventfld.long 0x20 0. "CMPFLGA,Port A compare status flag" "0,1"
rgroup.long 0x2C++0xF
line.long 0x0 "DERRADDRA,This register shows the address of PORTA current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x0 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x0 0.--30. 1. "Address,Recent double-bit error address."
line.long 0x4 "SERRADDRA,This register shows the address of PORTA current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "Address,Recent single-bit error address."
line.long 0x8 "DERRADDRB,This register shows the address of PORTB current double-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0x8 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x8 0.--30. 1. "Address,Recent double-bit error address."
line.long 0xC "SERRADDRB,This register shows the address of PORTB current single-bit error. RAM size will determine the maximum number of address bits."
bitfld.long 0xC 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0xC 0.--30. 1. "Address,Recent single-bit error address."
group.long 0x3C++0x7
line.long 0x0 "SERRCNTREG,Maximum counter value for single-bit error interrupt"
hexmask.long 0x0 0.--31. 1. "SERRCNT,Counter value"
line.long 0x4 "ECC_Addrbus,MSB bit of address is determined by ADR."
rbitfld.long 0x4 31. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long 0x4 0.--30. 1. "ECC_AddrBUS,Address will be driven to RAM to either read or write the data. Address will be latched by the RAM when the Enbus is asserted."
rgroup.long 0x44++0xF
line.long 0x0 "ECC_RData0bus,Data will be read to this register field."
hexmask.long 0x0 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[31:0]."
line.long 0x4 "ECC_RData1bus,Data will be read to this register field."
hexmask.long 0x4 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[63:32]."
line.long 0x8 "ECC_RData2bus,Data will be read to this register field."
hexmask.long 0x8 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[95:64]."
line.long 0xC "ECC_RData3bus,Data will be read to this register field."
hexmask.long 0xC 0.--31. 1. "ECC_RDataBUS,ECC_RDataBUS[127-96]."
wgroup.long 0x54++0xF
line.long 0x0 "ECC_WData0bus,Data from the register will be written to the RAM."
hexmask.long 0x0 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[31:0]."
line.long 0x4 "ECC_WData1bus,Data from the register will be written to the RAM."
hexmask.long 0x4 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[63:32]."
line.long 0x8 "ECC_WData2bus,Data from the register will be written to the RAM."
hexmask.long 0x8 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[95-64]."
line.long 0xC "ECC_WData3bus,Data from the register will be written to the RAM."
hexmask.long 0xC 0.--31. 1. "ECC_WDataBUS,ECC_WDataBUS[127-96]."
rgroup.long 0x64++0x7
line.long 0x0 "ECC_RDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_RDataecc3BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 16.--23. 1. "ECC_RDataecc2BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_RDataecc1BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x0 0.--7. 1. "ECC_RDataecc0BUS,Eccdata will be read to this register field."
line.long 0x4 "ECC_RDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_RDataecc7BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 16.--23. 1. "ECC_RDataecc6BUS,Eccdata will be read to this register field."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_RDataecc5BUS,Eccdata will be read to this register field."
hexmask.long.byte 0x4 0.--7. 1. "ECC_RDataecc4BUS,Eccdata will be read to this register field."
wgroup.long 0x6C++0x7
line.long 0x0 "ECC_WDataecc0bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x0 24.--31. 1. "ECC_WDataecc3BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 16.--23. 1. "ECC_WDataecc2BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x0 8.--15. 1. "ECC_WDataecc1BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x0 0.--7. 1. "ECC_WDataecc0BUS,Eccdata from the register will be written to the RAM."
line.long 0x4 "ECC_WDataecc1bus,The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved."
hexmask.long.byte 0x4 24.--31. 1. "ECC_WDataecc7BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 16.--23. 1. "ECC_WDataecc6BUS,Eccdata from the register will be written to the RAM."
newline
hexmask.long.byte 0x4 8.--15. 1. "ECC_WDataecc5BUS,Eccdata from the register will be written to the RAM."
hexmask.long.byte 0x4 0.--7. 1. "ECC_WDataecc4BUS,Eccdata from the register will be written to the RAM."
group.long 0x74++0x13
line.long 0x0 "ECC_dbytectrl,Max number of implemented byte enabled is DAT/8"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "DBEN,Byte or word enable for access."
line.long 0x4 "ECC_accctrl,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "RDWR,Control for read/write." "0,1"
newline
hexmask.long.byte 0x4 2.--7. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "ECCOVR,ECC Data Override." "0,1"
newline
bitfld.long 0x4 0. "DATAOVR,RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW." "0: Data override disabled,1: Data override enabled"
line.long 0x8 "ECC_startacc,These bits determine which byte of data/ecc to write to RAM."
hexmask.long.word 0x8 17.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16. "ENBUSA,Start RAM access for PORTA." "0,1"
newline
hexmask.long.word 0x8 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "ENBUSB,Start RAM access for PORTB." "0,1"
line.long 0xC "ECC_wdctrl,Bits to Enable/Disable Watch Dog Timer"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0xC 0. "WDEN_RAM,Enable watchdog timeout for OCP register access to IP RAM." "0,1"
line.long 0x10 "ECC_DECODERSTAT,<p>Individual decoder flags for single and double bits errors.</p>"
hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
eventfld.long 0x10 15. "DEC7DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 14. "DEC6DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 13. "DEC5DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 12. "DEC4DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 11. "DEC3DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 10. "DEC2DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 9. "DEC1DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 8. "DEC0DERRFLG,This bit indicates decoder(*) has detected double-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 7. "DEC7SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 6. "DEC6SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 5. "DEC5SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 4. "DEC4SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 3. "DEC3SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 2. "DEC2SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
eventfld.long 0x10 1. "DEC1SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
newline
eventfld.long 0x10 0. "DEC0SERRFLG,This bit indicates deocder(*) has detected single-bit error." "0: No error has been captured with this flag,1: Decoder"
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x90)++0x3
line.long 0x0 "SERRLKUPA0[$1],Single-bit error address in LOOKUP TABLE for PORTA."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
repeat 20. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0xE0)++0x3
line.long 0x0 "SERRLKUPB0[$1],Single-bit error address in LOOKUP TABLE for PORTB."
eventfld.long 0x0 31. "VALID8" "0,1"
eventfld.long 0x0 30. "VALID7" "0,1"
newline
eventfld.long 0x0 29. "VALID6" "0,1"
eventfld.long 0x0 28. "VALID5" "0,1"
newline
eventfld.long 0x0 27. "VALID4" "0,1"
eventfld.long 0x0 26. "VALID3" "0,1"
newline
eventfld.long 0x0 25. "VALID2" "0,1"
eventfld.long 0x0 24. "VALID1" "0,1"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "Address,Recent Single-bit error address."
repeat.end
tree.end
tree "OCRAM_FIREWALL"
base ad:0x108CC400
rgroup.long 0x0++0x3
line.long 0x0 "enable,Enable"
hexmask.long 0x0 4.--31. 1. "RVSD,MSB field is all zeros."
bitfld.long 0x0 3. "region3,OCRAM Region 3 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 2. "region2,OCRAM Region 2 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 1. "region1,OCRAM Region 1 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
bitfld.long 0x0 0. "region0,OCRAM Region 0 Enable. Value of 1 means region is enabled  Value of 0 means region is disabled" "0,1"
wgroup.long 0x4++0x7
line.long 0x0 "enable_set,Sets Master Region Enable field when written with 1"
hexmask.long 0x0 4.--31. 1. "RVSD,MSB field is all zeros."
bitfld.long 0x0 3. "region3,OCRAM Region 3 Enable Set." "0,1"
bitfld.long 0x0 2. "region2,OCRAM Region 2 Enable Set." "0,1"
bitfld.long 0x0 1. "region1,OCRAM Region 1 Enable Set." "0,1"
bitfld.long 0x0 0. "region0,OCRAM Region 0 Enable Set." "0,1"
line.long 0x4 "enable_clear,Clears Master Region Enable field when written with 1"
hexmask.long 0x4 4.--31. 1. "RVSD,MSB field is all zeros."
eventfld.long 0x4 3. "region3,OCRAM Region 3 Enable Clear." "0,1"
eventfld.long 0x4 2. "region2,OCRAM Region 2 Enable Clear." "0,1"
eventfld.long 0x4 1. "region1,OCRAM Region 1 Enable Clear." "0,1"
eventfld.long 0x4 0. "region0,OCRAM Region 0 Enable Clear." "0,1"
group.long 0x10++0x2F
line.long 0x0 "region0_base_adresss,Base definition for OCRAM Region 0"
hexmask.long.byte 0x0 28.--31. 1. "high_fixed,RSVD"
hexmask.long.word 0x0 12.--27. 1. "select,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x0 0.--11. 1. "low_fixed,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x4 "region0_limit_adresss,Base definition for OCRAM Region 0"
hexmask.long.byte 0x4 28.--31. 1. "high_fixed,RSVD"
hexmask.long.word 0x4 12.--27. 1. "select,defines the configurable bits of the base address field."
hexmask.long.word 0x4 0.--11. 1. "low_fixed,The minimum size of a region is limited to 4Kbytes"
line.long 0x8 "region0_access,Base definition for OCRAM Region 0"
hexmask.long 0x8 1.--31. 1. "RVSD,MSB field is all zeros."
bitfld.long 0x8 0. "acess_type,If S/N = 1  then only secure access is allowed  otherwise both secure and non-secure access is allowed" "0,1"
line.long 0xC "region1_base_adresss,Base definition for OCRAM Region 0"
hexmask.long.byte 0xC 28.--31. 1. "high_fixed,RSVD"
hexmask.long.word 0xC 12.--27. 1. "select,defines the 16 bit MSB of the base address field."
hexmask.long.word 0xC 0.--11. 1. "low_fixed,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x10 "region1_limit_adresss,Base definition for OCRAM Region 0"
hexmask.long.byte 0x10 28.--31. 1. "high_fixed,MSB field is all zeros."
hexmask.long.word 0x10 12.--27. 1. "select,defines the configurable bits of the base address field."
hexmask.long.word 0x10 0.--11. 1. "low_fixed,The minimum size of a region is limited to 4Kbytes"
line.long 0x14 "region1_access,Base definition for OCRAM Region 0"
hexmask.long 0x14 1.--31. 1. "RVSD,MSB field is all zeros."
bitfld.long 0x14 0. "acess_type,If S/N = 1  then only secure access is allowed  otherwise both secure and non-secure access is allowed" "0,1"
line.long 0x18 "region2_base_adresss,Base definition for OCRAM Region 0"
hexmask.long.byte 0x18 28.--31. 1. "high_fixed,RSVD"
hexmask.long.word 0x18 12.--27. 1. "select,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x18 0.--11. 1. "low_fixed,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x1C "region2_limit_adresss,Base definition for OCRAM Region 0"
hexmask.long.byte 0x1C 28.--31. 1. "high_fixed,MSB field is all zeros."
hexmask.long.word 0x1C 12.--27. 1. "select,defines the configurable bits of the base address field."
hexmask.long.word 0x1C 0.--11. 1. "low_fixed,The minimum size of a region is limited to 4Kbytes"
line.long 0x20 "region2_access,Base definition for OCRAM Region 0"
hexmask.long 0x20 1.--31. 1. "RVSD,MSB field is all zeros."
bitfld.long 0x20 0. "acess_type,If S/N = 1  then only secure access is allowed  otherwise both secure and non-secure access is allowed" "0,1"
line.long 0x24 "region3_base_adresss,Base definition for OCRAM Region 0"
hexmask.long.byte 0x24 28.--31. 1. "high_fixed,RSVD"
hexmask.long.word 0x24 12.--27. 1. "select,defines the 16 bit MSB of the base address field."
hexmask.long.word 0x24 0.--11. 1. "low_fixed,LSB field is all zeros. Region start address is {baseext base  16'h000}"
line.long 0x28 "region3_limit_adresss,Base definition for OCRAM Region 0"
hexmask.long.byte 0x28 28.--31. 1. "high_fixed,MSB field is all zeros."
hexmask.long.word 0x28 12.--27. 1. "select,defines the configurable bits of the base address field."
hexmask.long.word 0x28 0.--11. 1. "low_fixed,The minimum size of a region is limited to 4Kbytes"
line.long 0x2C "region3_access,Base definition for OCRAM Region 0"
hexmask.long 0x2C 1.--31. 1. "RVSD,MSB field is all zeros."
bitfld.long 0x2C 0. "acess_type,If S/N = 1  then only secure access is allowed  otherwise both secure and non-secure access is allowed" "0,1"
tree.end
tree.end
tree "PIN_MUX"
base ad:0x10D13000
group.long 0x0++0x9F
line.long 0x0 "pin0sel,HPS Pinmux Select for IO0"
hexmask.long 0x0 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--3. 1. "val,Select value determines which interface has been selected for IO0. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x4 "pin1sel,HPS Pinmux Select for IO1"
hexmask.long 0x4 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--3. 1. "val,Select value determines which interface has been selected for IO1. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x8 "pin2sel,HPS Pinmux Select for IO2"
hexmask.long 0x8 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 0.--3. 1. "val,Select value determines which interface has been selected for IO2. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0xC "pin3sel,HPS Pinmux Select for IO3"
hexmask.long 0xC 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--3. 1. "val,Select value determines which interface has been selected for IO3. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x10 "pin4sel,HPS Pinmux Select for IO4"
hexmask.long 0x10 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--3. 1. "val,Select value determines which interface has been selected for IO4. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x14 "pin5sel,HPS Pinmux Select for IO5"
hexmask.long 0x14 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x14 0.--3. 1. "val,Select value determines which interface has been selected for IO5. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x18 "pin6sel,HPS Pinmux Select for IO6"
hexmask.long 0x18 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x18 0.--3. 1. "val,Select value determines which interface has been selected for IO6. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x1C "pin7sel,HPS Pinmux Select for IO7"
hexmask.long 0x1C 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x1C 0.--3. 1. "val,Select value determines which interface has been selected for IO7. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x20 "pin8sel,HPS Pinmux Select for IO8"
hexmask.long 0x20 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x20 0.--3. 1. "val,Select value determines which interface has been selected for IO8. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x24 "pin9sel,HPS Pinmux Select for IO9"
hexmask.long 0x24 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x24 0.--3. 1. "val,Select value determines which interface has been selected for IO9. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x28 "pin10sel,HPS Pinmux Select for IO10"
hexmask.long 0x28 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x28 0.--3. 1. "val,Select value determines which interface has been selected for IO10. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x2C "pin11sel,HPS Pinmux Select for IO11"
hexmask.long 0x2C 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x2C 0.--3. 1. "val,Select value determines which interface has been selected for IO11. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x30 "pin12sel,HPS Pinmux Select for IO12"
hexmask.long 0x30 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x30 0.--3. 1. "val,Select value determines which interface has been selected for IO12. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x34 "pin13sel,HPS Pinmux Select for IO13"
hexmask.long 0x34 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x34 0.--3. 1. "val,Select value determines which interface has been selected for IO13. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x38 "pin14sel,HPS Pinmux Select for IO14"
hexmask.long 0x38 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x38 0.--3. 1. "val,Select value determines which interface has been selected for IO14. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x3C "pin15sel,HPS Pinmux Select for IO15"
hexmask.long 0x3C 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x3C 0.--3. 1. "val,Select value determines which interface has been selected for IO15. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x40 "pin16sel,HPS Pinmux Select for IO16"
hexmask.long 0x40 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x40 0.--3. 1. "val,Select value determines which interface has been selected for IO16. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x44 "pin17sel,HPS Pinmux Select for IO17"
hexmask.long 0x44 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x44 0.--3. 1. "val,Select value determines which interface has been selected for IO17. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x48 "pin18sel,HPS Pinmux Select for IO18"
hexmask.long 0x48 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x48 0.--3. 1. "val,Select value determines which interface has been selected for IO18. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x4C "pin19sel,HPS Pinmux Select for IO19"
hexmask.long 0x4C 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4C 0.--3. 1. "val,Select value determines which interface has been selected for IO19. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x50 "pin20sel,HPS Pinmux Select for IO20"
hexmask.long 0x50 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x50 0.--3. 1. "val,Select value determines which interface has been selected for IO20. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x54 "pin21sel,HPS Pinmux Select for IO21"
hexmask.long 0x54 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x54 0.--3. 1. "val,Select value determines which interface has been selected for IO21. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x58 "pin22sel,HPS Pinmux Select for IO22"
hexmask.long 0x58 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x58 0.--3. 1. "val,Select value determines which interface has been selected for IO22. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x5C "pin23sel,HPS Pinmux Select for IO23"
hexmask.long 0x5C 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x5C 0.--3. 1. "val,Select value determines which interface has been selected for IO23. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x60 "pin24sel,HPS Pinmux Select for IO0"
hexmask.long 0x60 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x60 0.--3. 1. "val,Select value determines which interface has been selected for IO0. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x64 "pin25sel,HPS Pinmux Select for IO1"
hexmask.long 0x64 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x64 0.--3. 1. "val,Select value determines which interface has been selected for IO1. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x68 "pin26sel,HPS Pinmux Select for IO2"
hexmask.long 0x68 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x68 0.--3. 1. "val,Select value determines which interface has been selected for IO2. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x6C "pin27sel,HPS Pinmux Select for IO3"
hexmask.long 0x6C 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x6C 0.--3. 1. "val,Select value determines which interface has been selected for IO3. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x70 "pin28sel,HPS Pinmux Select for IO4"
hexmask.long 0x70 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x70 0.--3. 1. "val,Select value determines which interface has been selected for IO4. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x74 "pin29sel,HPS Pinmux Select for IO5"
hexmask.long 0x74 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x74 0.--3. 1. "val,Select value determines which interface has been selected for IO5. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x78 "pin30sel,HPS Pinmux Select for IO6"
hexmask.long 0x78 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x78 0.--3. 1. "val,Select value determines which interface has been selected for IO6. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x7C "pin31sel,HPS Pinmux Select for IO7"
hexmask.long 0x7C 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x7C 0.--3. 1. "val,Select value determines which interface has been selected for IO7. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x80 "pin32sel,HPS Pinmux Select for IO8"
hexmask.long 0x80 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x80 0.--3. 1. "val,Select value determines which interface has been selected for IO8. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x84 "pin33sel,HPS Pinmux Select for IO9"
hexmask.long 0x84 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x84 0.--3. 1. "val,Select value determines which interface has been selected for IO9. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x88 "pin34sel,HPS Pinmux Select for IO10"
hexmask.long 0x88 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x88 0.--3. 1. "val,Select value determines which interface has been selected for IO10. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x8C "pin35sel,HPS Pinmux Select for IO11"
hexmask.long 0x8C 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8C 0.--3. 1. "val,Select value determines which interface has been selected for IO11. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x90 "pin36sel,HPS Pinmux Select for IO12"
hexmask.long 0x90 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x90 0.--3. 1. "val,Select value determines which interface has been selected for IO12. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x94 "pin37sel,HPS Pinmux Select for IO13"
hexmask.long 0x94 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x94 0.--3. 1. "val,Select value determines which interface has been selected for IO13. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x98 "pin38sel,HPS Pinmux Select for IO14"
hexmask.long 0x98 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x98 0.--3. 1. "val,Select value determines which interface has been selected for IO14. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x9C "pin39sel,HPS Pinmux Select for IO15"
hexmask.long 0x9C 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x9C 0.--3. 1. "val,Select value determines which interface has been selected for IO15. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
group.long 0x100++0x1F
line.long 0x0 "pin40sel,HPS Pinmux Select for IO16"
hexmask.long 0x0 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--3. 1. "val,Select value determines which interface has been selected for IO16. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x4 "pin41sel,HPS Pinmux Select for IO17"
hexmask.long 0x4 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--3. 1. "val,Select value determines which interface has been selected for IO17. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x8 "pin42sel,HPS Pinmux Select for IO18"
hexmask.long 0x8 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x8 0.--3. 1. "val,Select value determines which interface has been selected for IO18. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0xC "pin43sel,HPS Pinmux Select for IO19"
hexmask.long 0xC 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0xC 0.--3. 1. "val,Select value determines which interface has been selected for IO19. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x10 "pin44sel,HPS Pinmux Select for IO20"
hexmask.long 0x10 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x10 0.--3. 1. "val,Select value determines which interface has been selected for IO20. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x14 "pin45sel,HPS Pinmux Select for IO21"
hexmask.long 0x14 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x14 0.--3. 1. "val,Select value determines which interface has been selected for IO21. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x18 "pin46sel,HPS Pinmux Select for IO22"
hexmask.long 0x18 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x18 0.--3. 1. "val,Select value determines which interface has been selected for IO22. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
line.long 0x1C "pin47sel,HPS Pinmux Select for IO23"
hexmask.long 0x1C 4.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x1C 0.--3. 1. "val,Select value determines which interface has been selected for IO23. It also detemines the output_enable for the respective interface. Its value can range from 0 to 9."
group.long 0x130++0x6F
line.long 0x0 "io0ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x0 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x0 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x0 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x0 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x0 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x4 "io1ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x4 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x4 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x4 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x4 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x4 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x4 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x8 "io2ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x8 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x8 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x8 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x8 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x8 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x8 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0xC "io3ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0xC 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0xC 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0xC 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0xC 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0xC 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0xC 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x10 "io4ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x10 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x10 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x10 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x10 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x10 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x10 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x14 "io5ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x14 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x14 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x14 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x14 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x14 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x14 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x18 "io6ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x18 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x18 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x18 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x18 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x18 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x18 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x1C "io7ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x1C 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x1C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x1C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x1C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x1C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x1C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x20 "io8ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x20 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x20 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x20 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x20 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x20 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x20 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x24 "io9ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x24 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x24 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x24 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x24 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x24 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x24 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x24 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x28 "io10ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x28 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x28 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x28 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x28 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x28 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x28 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x2C "io11ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x2C 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x2C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x2C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x2C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x2C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x2C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x2C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x30 "io12ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x30 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x30 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x30 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x30 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x30 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x30 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x30 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x34 "io13ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x34 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x34 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x34 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x34 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x34 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x34 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x34 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x38 "io14ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x38 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x38 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x38 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x38 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x38 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x38 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x38 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x3C "io15ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x3C 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x3C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x3C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x3C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x3C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x3C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x3C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x40 "io16ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x40 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x40 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x40 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x40 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x40 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x40 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x40 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x44 "io17ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x44 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x44 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x44 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x44 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x44 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x44 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x44 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x48 "io18ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x48 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x48 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x48 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x48 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x48 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x48 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x48 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x4C "io19ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x4C 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x4C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x4C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x4C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x4C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x4C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x50 "io20ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x50 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x50 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x50 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x50 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x50 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x50 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x50 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x50 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x54 "io21ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x54 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x54 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x54 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x54 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x54 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x54 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x54 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x54 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x58 "io22ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x58 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x58 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x58 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x58 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x58 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x58 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x58 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x58 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x5C "io23ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x5C 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x5C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x5C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x5C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x5C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
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bitfld.long 0x5C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x5C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x5C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x60 "io24ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x60 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x60 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x60 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x60 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x60 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x60 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x60 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x60 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x64 "io25ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x64 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x64 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x64 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x64 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x64 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x64 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x64 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x64 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x68 "io26ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x68 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x68 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x68 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x68 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x68 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x68 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x68 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x68 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x6C "io27ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x6C 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x6C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x6C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x6C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x6C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x6C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x6C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x6C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
group.long 0x200++0x4F
line.long 0x0 "io28ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x0 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x0 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x0 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x0 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x0 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x4 "io29ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x4 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x4 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x4 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x4 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x4 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x4 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x8 "io30ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x8 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x8 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x8 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x8 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x8 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x8 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0xC "io31ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0xC 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0xC 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0xC 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0xC 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0xC 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0xC 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x10 "io32ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x10 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x10 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x10 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x10 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x10 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x10 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x14 "io33ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x14 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x14 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x14 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x14 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x14 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x14 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x18 "io34ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x18 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x18 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x18 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x18 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x18 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x18 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x1C "io35ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x1C 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x1C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x1C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x1C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x1C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x1C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x1C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x20 "io36ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x20 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x20 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x20 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x20 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x20 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x20 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x24 "io37ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x24 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x24 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x24 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x24 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x24 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x24 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x24 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x24 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x28 "io38ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x28 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
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bitfld.long 0x28 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x28 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x28 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x28 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
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bitfld.long 0x28 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x28 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x2C "io39ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x2C 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x2C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x2C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x2C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x2C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x2C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x2C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x2C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x30 "io40ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x30 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x30 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x30 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x30 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x30 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x30 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x30 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x30 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x34 "io41ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x34 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x34 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x34 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x34 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x34 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x34 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x34 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x34 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x38 "io42ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x38 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x38 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x38 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x38 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x38 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x38 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x38 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x38 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x3C "io43ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x3C 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x3C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x3C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x3C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x3C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x3C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x3C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x3C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x40 "io44ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x40 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x40 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x40 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x40 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x40 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x40 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x40 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x40 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x44 "io45ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x44 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x44 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x44 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x44 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x44 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x44 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x44 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x44 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x48 "io46ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x48 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x48 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x48 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x48 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x48 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x48 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x48 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x48 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
line.long 0x4C "io47ctrl,HPS Pinmux Control Value"
hexmask.long.tbyte 0x4C 10.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4C 9. "iodt_config,Control bit to select NMOS or PMOS for On-die termination. Here the On-die termination impedance can be pull up or pull down based on iwkpullctrl settings" "0,1"
newline
bitfld.long 0x4C 8. "iodt_en,Control bit to turn on On-die termination. Its an active high signal i.e. when set to '1' it enables On-die termination. By default this bit is set to '0'" "0,1"
newline
bitfld.long 0x4C 5.--7. "iwkpullctrl,Weak pull up or pull down select bits for 3 flavors of pull up or pull down resistors i.e. 20 KOhm  50 KOhm and 80 KOhm. User can select no pull up/down by setting this 3 bit field either to 000 or 111." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4C 4. "ihysen,Control bit to select between TTL and schmitt trigger. By default schmitt trigger is selected. 0 - No hysteresis or TTL . 1- 200 mv of hysteresis i.e. receiving buffer will select schmitt trigger." "0,1"
newline
bitfld.long 0x4C 3. "ioden,Selects between open drain or normal drive mode. By default  normal drive mode is selected." "0,1"
newline
bitfld.long 0x4C 2. "islewctrl,Control bit to select fast or slow slew rate.The default setting is fast slew for 8mA of drive. This bit can be set to '0' to select slow slew.�" "0,1"
newline
bitfld.long 0x4C 0.--1. "idrvctrl,Selects pull up or pull down drive strength. The default settings select 8mA. These 2 bits can be used to select� 2mA   4mA  6 mA or 8 mA of drive strength" "0,1,2,3"
group.long 0x300++0x23
line.long 0x0 "pinmux_emac0_usefpga,Selection between HPS Pin and FPGA Interface for EMAC0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "sel,Select connection for EMAC0." "0: EMAC0 uses HPS IO Pins.,1: EMAC0 uses the FPGA Inteface."
line.long 0x4 "pinmux_emac1_usefpga,Selection between HPS Pin and FPGA Interface for EMAC1 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "sel,Select connection for EMAC1." "0: EMAC1 uses HPS IO Pins.,1: EMAC1 uses the FPGA Inteface."
line.long 0x8 "pinmux_emac2_usefpga,Selection between HPS Pin and FPGA Interface for EMAC2 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0. "sel,Select connection for EMAC2." "0: EMAC2 uses HPS IO Pins.,1: EMAC2 uses the FPGA Inteface."
line.long 0xC "pinmux_i2c0_usefpga,Selection between HPS Pin and FPGA Interface for I2C0 signals."
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 0. "sel,Select connection for I2C0." "0: I2C0 uses HPS IO Pins.,1: I2C0 uses the FPGA Inteface."
line.long 0x10 "pinmux_i2c1_usefpga,Selection between HPS Pin and FPGA Interface for I2C1 signals."
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 0. "sel,Select connection for I2C1." "0: I2C1 uses HPS IO Pins.,1: I2C1uses the FPGA Inteface."
line.long 0x14 "pinmux_i2c_emac0_usefpga,Selection between HPS Pin and FPGA Interface for I2C_EMAC0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x14 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0. "sel,Select connection for I2C_EMAC0." "0: I2C_EMAC0 uses HPS IO Pins.,1: I2C_EMAC0 uses the FPGA Inteface."
line.long 0x18 "pinmux_i2c_emac1_usefpga,Selection between HPS Pin and FPGA Interface for I2C_EMAC1 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 0. "sel,Select connection for I2C_EMAC1." "0: I2C_EMAC1 uses HPS IO Pins.,1: I2C_EMAC1uses the FPGA Inteface."
line.long 0x1C "pinmux_i2c_emac2_usefpga,Selection between HPS Pin and FPGA Interface for I2C_EMAC2 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x1C 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 0. "sel,Select connection for I2C_EMAC2." "0: I2C_EMAC2 uses HPS IO Pins.,1: I2C_EMAC2uses the FPGA Inteface."
line.long 0x20 "pinmux_nand_usefpga,Reserved"
hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 0. "sel,Select connection for NAND." "0: NAND uses HPS IO Pins.,1: NAND uses the FPGA Inteface."
group.long 0x328++0x23
line.long 0x0 "pinmux_spim0_usefpga,Selection between HPS Pin and FPGA Interface for SPIM0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "sel,Select connection for SPIM0." "0: SPIM0 uses HPS IO Pins.,1: SPIM0 uses the FPGA Inteface."
line.long 0x4 "pinmux_spim1_usefpga,Selection between HPS Pin and FPGA Interface for SPIM1 signals."
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "sel,Select connection for SPIM1." "0: SPIM1 uses HPS IO Pins.,1: SPIM1uses the FPGA Inteface."
line.long 0x8 "pinmux_spis0_usefpga,Selection between HPS Pin and FPGA Interface for SPIS0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0. "sel,Select connection for SPIS0." "0: SPIS0 uses HPS IO Pins.,1: SPIS0 uses the FPGA Inteface."
line.long 0xC "pinmux_spis1_usefpga,Selection between HPS Pin and FPGA Interface for SPIS1 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 0. "sel,Select connection for SPIS1." "0: SPIS1 uses HPS IO Pins.,1: SPIS1uses the FPGA Inteface."
line.long 0x10 "pinmux_uart0_usefpga,Selection between HPS Pin and FPGA Interface for UART0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
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bitfld.long 0x10 0. "sel,Select connection for UART0." "0: UART0 uses HPS IO Pins.,1: UART0 uses the FPGA Inteface."
line.long 0x14 "pinmux_uart1_usefpga,Selection between HPS Pin and FPGA Interface for UART1 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x14 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 0. "sel,Select connection for UART1." "0: UART1 uses HPS IO Pins.,1: UART1uses the FPGA Inteface."
line.long 0x18 "pinmux_mdio0_usefpga,Selection between HPS Pin and FPGA Interface for MDIO0 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
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bitfld.long 0x18 0. "sel,Select connection for MDIO0." "0: MDIO0 uses HPS IO Pins.,1: MDIO0 uses the FPGA Inteface."
line.long 0x1C "pinmux_mdio1_usefpga,Selection between HPS Pin and FPGA Interface for MDIO1 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x1C 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
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bitfld.long 0x1C 0. "sel,Select connection for MDIO1." "0: MDIO1 uses HPS IO Pins.,1: MDIO1uses the FPGA Inteface."
line.long 0x20 "pinmux_mdio2_usefpga,Selection between HPS Pin and FPGA Interface for MDIO2 signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
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bitfld.long 0x20 0. "sel,Select connection for MDIO2." "0: MDIO2 uses HPS IO Pins.,1: MDIO2 uses the FPGA Inteface."
group.long 0x350++0x7
line.long 0x0 "pinmux_jtag_usefpga,Selection between HPS Pin and FPGA Interface for JTAG signals. NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
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bitfld.long 0x0 0. "sel,Select connection for JTAG." "0: JTAG uses HPS IO Pins.,1: JTAG uses the FPGA Inteface."
line.long 0x4 "pinmux_sdmmc_usefpga,Reserved"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "sel,Select connection for SDMMC." "0: SDMMC uses HPS IO Pins.,1: SDMMC uses the FPGA Inteface."
group.long 0x400++0xC7
line.long 0x0 "io0_delay,Adds the delay chains in IO0."
hexmask.long.tbyte 0x0 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x0 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x0 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x0 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x0 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x4 "io1_delay,Adds the delay chains in IO1."
hexmask.long.tbyte 0x4 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
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bitfld.long 0x4 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x4 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x4 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x4 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x4 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x8 "io2_delay,Adds the delay chains in IO2."
hexmask.long.tbyte 0x8 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x8 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x8 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x8 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x8 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xC "io3_delay,Adds the delay chains in IO3."
hexmask.long.tbyte 0xC 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xC 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0xC 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xC 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xC 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x10 "io4_delay,Adds the delay chains in IO4."
hexmask.long.tbyte 0x10 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
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hexmask.long.byte 0x10 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x10 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x10 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x10 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x14 "io5_delay,Adds the delay chains in IO5."
hexmask.long.tbyte 0x14 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x14 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x14 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x14 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x14 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x18 "io6_delay,Adds the delay chains in IO6."
hexmask.long.tbyte 0x18 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x18 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x18 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x18 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x18 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x1C "io7_delay,Adds the delay chains in IO7."
hexmask.long.tbyte 0x1C 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x1C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x1C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x1C 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x1C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x1C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x20 "io8_delay,Adds the delay chains in IO8."
hexmask.long.tbyte 0x20 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x20 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x20 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x20 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x20 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x24 "io9_delay,Adds the delay chains in IO9."
hexmask.long.tbyte 0x24 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x24 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x24 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x24 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x24 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x24 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x28 "io10_delay,Adds the delay chains in IO10."
hexmask.long.tbyte 0x28 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x28 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x28 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x28 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x28 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x2C "io11_delay,Adds the delay chains in IO11."
hexmask.long.tbyte 0x2C 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x2C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x2C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x2C 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x2C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x2C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x30 "io12_delay,Adds the delay chains in IO12."
hexmask.long.tbyte 0x30 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x30 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x30 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x30 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x30 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x30 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x34 "io13_delay,Adds the delay chains in IO13."
hexmask.long.tbyte 0x34 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x34 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x34 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x34 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x34 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x34 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x38 "io14_delay,Adds the delay chains in IO14."
hexmask.long.tbyte 0x38 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x38 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x38 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x38 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x38 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x38 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x3C "io15_delay,Adds the delay chains in IO15."
hexmask.long.tbyte 0x3C 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x3C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x3C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x3C 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x3C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x3C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x40 "io16_delay,Adds the delay chains in IO16."
hexmask.long.tbyte 0x40 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x40 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x40 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x40 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x40 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x40 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x44 "io17_delay,Adds the delay chains in IO17."
hexmask.long.tbyte 0x44 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x44 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x44 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x44 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x44 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x44 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x48 "io18_delay,Adds the delay chains in IO18."
hexmask.long.tbyte 0x48 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x48 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x48 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x48 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x48 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x48 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x4C "io19_delay,Adds the delay chains in IO19."
hexmask.long.tbyte 0x4C 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x4C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x4C 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x4C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x4C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x50 "io20_delay,Adds the delay chains in IO20."
hexmask.long.tbyte 0x50 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x50 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x50 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x50 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x50 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x50 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x54 "io21_delay,Adds the delay chains in IO21."
hexmask.long.tbyte 0x54 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x54 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x54 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x54 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x54 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x54 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x58 "io22_delay,Adds the delay chains in IO22."
hexmask.long.tbyte 0x58 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x58 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x58 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x58 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x58 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x58 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x5C "io23_delay,Adds the delay chains in IO23."
hexmask.long.tbyte 0x5C 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x5C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x5C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x5C 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x5C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x5C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x60 "io24_delay,Adds the delay chains in IO24."
hexmask.long.tbyte 0x60 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x60 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x60 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x60 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x60 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x60 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x64 "io25_delay,Adds the delay chains in IO25."
hexmask.long.tbyte 0x64 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x64 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x64 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x64 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x64 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x64 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x68 "io26_delay,Adds the delay chains in IO26."
hexmask.long.tbyte 0x68 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x68 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x68 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x68 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x68 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x68 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x6C "io27_delay,Adds the delay chains in IO27."
hexmask.long.tbyte 0x6C 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x6C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x6C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x6C 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x6C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x6C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x70 "io28_delay,Adds the delay chains in IO28."
hexmask.long.tbyte 0x70 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x70 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x70 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x70 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x70 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x70 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x74 "io29_delay,Adds the delay chains in IO29."
hexmask.long.tbyte 0x74 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x74 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x74 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x74 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x74 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x74 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x78 "io30_delay,Adds the delay chains in IO30."
hexmask.long.tbyte 0x78 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x78 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x78 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x78 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x78 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x78 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x7C "io31_delay,Adds the delay chains in IO31."
hexmask.long.tbyte 0x7C 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x7C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x7C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x7C 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x7C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x7C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x80 "io32_delay,Adds the delay chains in IO32."
hexmask.long.tbyte 0x80 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x80 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x80 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x80 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x80 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x80 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x84 "io33_delay,Adds the delay chains in IO33."
hexmask.long.tbyte 0x84 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x84 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x84 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x84 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x84 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x84 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x88 "io34_delay,Adds the delay chains in IO34."
hexmask.long.tbyte 0x88 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x88 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x88 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x88 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x88 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x88 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x8C "io35_delay,Adds the delay chains in IO35."
hexmask.long.tbyte 0x8C 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x8C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x8C 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x8C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x8C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x90 "io36_delay,Adds the delay chains in IO36."
hexmask.long.tbyte 0x90 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x90 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x90 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x90 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x90 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x90 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x94 "io37_delay,Adds the delay chains in IO37."
hexmask.long.tbyte 0x94 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x94 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x94 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x94 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x94 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x94 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x98 "io38_delay,Adds the delay chains in IO38."
hexmask.long.tbyte 0x98 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x98 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x98 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x98 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x98 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x98 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0x9C "io39_delay,Adds the delay chains in IO39."
hexmask.long.tbyte 0x9C 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x9C 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x9C 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0x9C 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x9C 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0x9C 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xA0 "io40_delay,Adds the delay chains in IO40."
hexmask.long.tbyte 0xA0 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0xA0 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xA0 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0xA0 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xA0 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xA0 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xA4 "io41_delay,Adds the delay chains in IO41."
hexmask.long.tbyte 0xA4 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0xA4 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xA4 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0xA4 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xA4 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xA4 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xA8 "io42_delay,Adds the delay chains in IO42."
hexmask.long.tbyte 0xA8 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0xA8 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xA8 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0xA8 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xA8 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xA8 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xAC "io43_delay,Adds the delay chains in IO43."
hexmask.long.tbyte 0xAC 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0xAC 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xAC 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0xAC 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xAC 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xAC 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xB0 "io44_delay,Adds the delay chains in IO44."
hexmask.long.tbyte 0xB0 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0xB0 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB0 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0xB0 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xB0 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB0 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xB4 "io45_delay,Adds the delay chains in IO45."
hexmask.long.tbyte 0xB4 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0xB4 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB4 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0xB4 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xB4 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB4 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xB8 "io46_delay,Adds the delay chains in IO46."
hexmask.long.tbyte 0xB8 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0xB8 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB8 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0xB8 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xB8 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xB8 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xBC "io47_delay,Adds the delay chains in IO47."
hexmask.long.tbyte 0xBC 15.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0xBC 13.--14. "output_val_en,These bits are used to enable the delay chains on the output path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xBC 8.--12. 1. "output_val,Depending on the value  it adds the chain delays in the output path of the Pinmux."
newline
rbitfld.long 0xBC 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0xBC 5.--6. "input_val_en,These bits are used to enable the delay chains in the input path." "0: Bypasses the delay chains,1: Selects the delay chain ranging from 0 to 15..,?,3: Selects the delay chain ranging from 16 to 30.."
newline
hexmask.long.byte 0xBC 0.--4. 1. "input_val,Depending on the value  it adds the chain delays in the input path of the Pinmux."
line.long 0xC0 "pinmux_i3c0_usefpga,Selection between HPS Pin and FPGA Interface for I3C0 signals."
hexmask.long 0xC0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC0 0. "sel,Select connection for I3C0." "0: I3C0 uses HPS IO Pins.,1: I3C0 uses the FPGA Inteface."
line.long 0xC4 "pinmux_i3c1_usefpga,Selection between HPS Pin and FPGA Interface for I3C1 signals."
hexmask.long 0xC4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC4 0. "sel,Select connection for I3C1." "0: I3C1 uses HPS IO Pins.,1: I3C1uses the FPGA Inteface."
tree.end
tree "PWR_MGR (Power Management)"
base ad:0x10D14000
group.long 0x0++0x7
line.long 0x0 "FWENCTL,Bits [3:0] are ultimately inverted in dynamiq_cluster.sv and connected to each CPU core&rsquo;s nISOLATECPU input pin."
hexmask.long 0x0 5.--31. 1. "RSVD"
bitfld.long 0x0 4. "PWRCTL_WRITE_LOCK" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "DSU_FWEN"
line.long 0x4 "PGENCTL,Bits [3:0] ultimately map to shutoff signals in corinth_scu_slice.sv."
hexmask.long 0x4 4.--31. 1. "RSVD"
hexmask.long.byte 0x4 0.--3. 1. "DSU_PGEN"
rgroup.long 0x8++0x3
line.long 0x0 "PGSTAT,Bits [3:0] originate in dynamiq_cluster.sv and are connected to each CPU core&rsquo;s POWERGOOD output pin. Bits [3:2] map to the Enyo cores (CPU3 and CPU2 respectively) and bits [1:0] map to the Ananke cores (CPU1 and CPU0 respectively):"
hexmask.long 0x0 4.--31. 1. "RSVD"
hexmask.long.byte 0x0 0.--3. 1. "DSU_PGEN_OUT"
rgroup.long 0x14++0x3
line.long 0x0 "PWRSTAT,Bits [7:0] record the 8 relevant PACTIVE bits."
bitfld.long 0x0 31. "DSU_MULTI_PCH_DONE" "0,1"
hexmask.long.byte 0x0 24.--30. 1. "RSVD"
hexmask.long.byte 0x0 16.--23. 1. "DSU_MULTI_PDENY"
hexmask.long.byte 0x0 8.--15. 1. "DSU_MULTI_PACCEPT"
newline
hexmask.long.byte 0x0 0.--7. 1. "DSU_MULTI_PACTIVE_IN"
group.long 0x38++0x7
line.long 0x0 "FWENCTL,This register is currently unused and reserved for future APS power control scenarios with FWEN output bits."
hexmask.long 0x0 0.--31. 1. "RSVD"
line.long 0x4 "PGENCTL,This register is currently unused and reserved for future APS power control scenarios with PGEN output bits."
hexmask.long 0x4 0.--31. 1. "RSVD"
rgroup.long 0x40++0x3
line.long 0x0 "PGSTAT,This register is currently unused and reserved for future APS power control scenarios where PGO input bits are used."
hexmask.long 0x0 0.--31. 1. "RSVD"
group.long 0x44++0x7
line.long 0x0 "FWENCTL,This register is currently unused and reserved for PSS power control scenarios with FWEN output bits."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD"
hexmask.long.byte 0x0 0.--7. 1. "PSS_FWEN"
line.long 0x4 "PGENCTL,Bits [7:0] are sent to 8 target IPs and hooked up to the input of a daisy chain of all of the memories in each IP. with the PWR_MGMT_MISC_RF_IN or shutoff pin of each power gated memory macro serving as an input and the PWR_MGMT_MISC_RF_OUT or.."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD"
hexmask.long.byte 0x4 0.--7. 1. "PSS_PGEN"
rgroup.long 0x4C++0x3
line.long 0x0 "PGSTAT,Bits 7:0 are received from the same 8 target IPs as for PSS PGENCTL. hooked up to the output rather than the input of each daisy chain."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD"
hexmask.long.byte 0x0 0.--7. 1. "PSS_PGEN_OUT"
group.long 0x50++0x3
line.long 0x0 "PCHCTLR,Bit 0 will automatically trigger a P-Channel transaction to bring the DSU to FULL ON shortly after deassertion of the power_manager_por_rst_n signal as a starting point for the boot flow."
hexmask.long 0x0 7.--31. 1. "RSVD"
bitfld.long 0x0 6. "GLOBAL_WRITE_LOCK" "0,1"
bitfld.long 0x0 5. "TRIGGER_PCH_L3CACHE" "0,1"
hexmask.long.byte 0x0 1.--4. 1. "TRIGGER_PCH_CPU"
newline
bitfld.long 0x0 0. "TRIGGER_PCH_DSU" "0,1"
rgroup.long 0x54++0x7
line.long 0x0 "PCHSTAT,Bit 0 indicates that the DSU is powered on through the P-Channels."
hexmask.long 0x0 6.--31. 1. "RSVD"
bitfld.long 0x0 5. "STATUS_PCH_L3CACHE" "0,1"
hexmask.long.byte 0x0 1.--4. 1. "STATUS_PCH_CPU"
bitfld.long 0x0 0. "STATUS_PCH_DSU" "0,1"
line.long 0x4 "BOOTCONFIG,Bit 0 maps to mpu_bootconfig_dsu_power_state."
hexmask.long.word 0x4 23.--31. 1. "RSVD2"
bitfld.long 0x4 20.--22. "TRACK_CPU_POWER_DOMAINS" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 16.--19. 1. "CPU_AVAILABLE"
hexmask.long.byte 0x4 12.--15. 1. "RSVD1"
newline
bitfld.long 0x4 10.--11. "BOOT_CPU_CHOICE" "0,1,2,3"
bitfld.long 0x4 8.--9. "L3_CACHE_SIZE" "0,1,2,3"
bitfld.long 0x4 5.--7. "RSVD0" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 1.--4. 1. "CPU_POWER_STATE"
newline
bitfld.long 0x4 0. "DSU_POWER_STATE" "0,1"
group.long 0x0++0x3
line.long 0x0 "PWRCTLR,Bit 0 can be used to trigger a transition from the DSU_CACHE_FSM_ARMED state to the DSU_CACHE_PSTATE_START state when set to 1."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD"
hexmask.long.byte 0x0 1.--7. 1. "DSU_PROG_PSTATE"
bitfld.long 0x0 0. "DSU_RUN_PCH" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "PWRSTAT,Bit 0 records if PACCEPT was received in the most recent transaction."
bitfld.long 0x0 31. "DSU_SINGLE_PCH_DONE" "0,1"
hexmask.long.tbyte 0x0 10.--30. 1. "RSVD"
hexmask.long.byte 0x0 2.--9. 1. "DSU_SINGLE_FSM_STATE"
bitfld.long 0x0 1. "DSU_SINGLE_PDENY" "0,1"
newline
bitfld.long 0x0 0. "DSU_SINGLE_PACCEPT" "0,1"
group.long 0x0++0x3
line.long 0x0 "PWRCTLR,Bit 0 can be used to trigger a transition from the DSU_CORE0_FSM_ARMED state to the DSU_CORE0_PSTATE_START state when set to 1."
hexmask.long 0x0 7.--31. 1. "RSVD"
hexmask.long.byte 0x0 1.--6. 1. "CPU_PROG_PSTATE"
bitfld.long 0x0 0. "CPU_RUN_PCH" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "PWRSTAT,Bit 0 records if PACCEPT was received in the most recent transaction with Core 0."
bitfld.long 0x0 31. "CPU_SINGLE_PCH_DONE" "0,1"
hexmask.long.byte 0x0 24.--30. 1. "CPU_PACTIVE_IN_REQUEST"
hexmask.long.word 0x0 10.--23. 1. "RSVD"
hexmask.long.byte 0x0 2.--9. 1. "CPU_SINGLE_FSM_STATE"
newline
bitfld.long 0x0 1. "CPU_SINGLE_PDENY" "0,1"
bitfld.long 0x0 0. "CPU_SINGLE_PACCEPT" "0,1"
group.long 0x0++0x3
line.long 0x0 "PWRCTLR,Bit 0 can be used to trigger a transition from the DSU_CORE1_FSM_ARMED state to the DSU_CORE1_PSTATE_START state when set to 1."
hexmask.long 0x0 7.--31. 1. "RSVD"
hexmask.long.byte 0x0 1.--6. 1. "CPU_PROG_PSTATE"
bitfld.long 0x0 0. "CPU_RUN_PCH" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "PWRSTAT,Bit 0 records if PACCEPT was received in the most recent transaction with Core 1."
bitfld.long 0x0 31. "CPU_SINGLE_PCH_DONE" "0,1"
hexmask.long.byte 0x0 24.--30. 1. "CPU_PACTIVE_IN_REQUEST"
hexmask.long.word 0x0 10.--23. 1. "RSVD"
hexmask.long.byte 0x0 2.--9. 1. "CPU_SINGLE_FSM_STATE"
newline
bitfld.long 0x0 1. "CPU_SINGLE_PDENY" "0,1"
bitfld.long 0x0 0. "CPU_SINGLE_PACCEPT" "0,1"
group.long 0x0++0x3
line.long 0x0 "PWRCTLR,Bit 0 can be used to trigger a transition from the DSU_CORE2_FSM_ARMED state to the DSU_CORE2_PSTATE_START state when set to 1."
hexmask.long 0x0 7.--31. 1. "RSVD"
hexmask.long.byte 0x0 1.--6. 1. "CPU_PROG_PSTATE"
bitfld.long 0x0 0. "CPU_RUN_PCH" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "PWRSTAT,Bit 0 records if PACCEPT was received in the most recent transaction with Core 2."
bitfld.long 0x0 31. "CPU_SINGLE_PCH_DONE" "0,1"
hexmask.long.byte 0x0 24.--30. 1. "CPU_PACTIVE_IN_REQUEST"
hexmask.long.word 0x0 10.--23. 1. "RSVD"
hexmask.long.byte 0x0 2.--9. 1. "CPU_SINGLE_FSM_STATE"
newline
bitfld.long 0x0 1. "CPU_SINGLE_PDENY" "0,1"
bitfld.long 0x0 0. "CPU_SINGLE_PACCEPT" "0,1"
group.long 0x0++0x3
line.long 0x0 "PWRCTLR,Bit 0 can be used to trigger a transition from the DSU_CORE3_FSM_ARMED state to the DSU_CORE3_PSTATE_START state when set to 1."
hexmask.long 0x0 7.--31. 1. "RSVD"
hexmask.long.byte 0x0 1.--6. 1. "CPU_PROG_PSTATE"
bitfld.long 0x0 0. "CPU_RUN_PCH" "0,1"
rgroup.long 0x4++0x3
line.long 0x0 "PWRSTAT,Bit 0 records if PACCEPT was received in the most recent transaction with Core 3."
bitfld.long 0x0 31. "CPU_SINGLE_PCH_DONE" "0,1"
hexmask.long.byte 0x0 24.--30. 1. "CPU_PACTIVE_IN_REQUEST"
hexmask.long.word 0x0 10.--23. 1. "RSVD"
hexmask.long.byte 0x0 2.--9. 1. "CPU_SINGLE_FSM_STATE"
newline
bitfld.long 0x0 1. "CPU_SINGLE_PDENY" "0,1"
bitfld.long 0x0 0. "CPU_SINGLE_PACCEPT" "0,1"
tree.end
tree "RST_MGR (Reset Manager)"
base ad:0x10D11000
group.long 0x0++0x3
line.long 0x0 "stat,The 'stat' register contains bits that indicate the reset source. A field is 1 if its associated reset requester caused the reset."
hexmask.long.byte 0x0 26.--31. 1. "Reserved_10,Reserved bitfield added by Magillem"
eventfld.long 0x0 25. "csdaprst,This bit indicates that CS DAP block has been reset. This bit is reset to its reset value on POR  not on warm or cold reset." "0,1"
eventfld.long 0x0 24. "debugrst,debugrst ndicates if the debug reset has been asserted. This bit is reset to its reset value on POR  not on warm or cold reset." "0,1"
rbitfld.long 0x0 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x0 20. "l4wd4rst,L4 Watchdog4 triggered a hardware sequenced warm reset." "0,1"
eventfld.long 0x0 19. "l4wd3rst,L4 Watchdog3 triggered a hardware sequenced warm reset." "0,1"
eventfld.long 0x0 18. "l4wd2rst,L4 Watchdog2 triggered a hardware sequenced warm reset." "0,1"
eventfld.long 0x0 17. "l4wd1rst,L4 Watchdog1 triggered a hardware sequenced warm reset." "0,1"
newline
eventfld.long 0x0 16. "l4wd0rst,L4 Watchdog0 triggered a hardware sequenced warm reset." "0,1"
hexmask.long.word 0x0 3.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x0 2. "sdmlastporrst,SDM triggered last por reset. This bit is reset to its reset value on POR  not on warm or cold reset." "0,1"
eventfld.long 0x0 1. "sdmwarmrst,SDM triggered warm reset." "0,1"
newline
eventfld.long 0x0 0. "sdmcoldrst,SDM triggered cold reset. This bit is reset to its reset value on POR  not on warm or cold reset." "0,1"
group.long 0x8++0x3
line.long 0x0 "miscstat,The 'miscstat' register contains bits that indicate the timeout event. For timeout events. a field is 1 if its associated timeout occured as part of a hardware sequenced warm/debug reset."
hexmask.long.word 0x0 18.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
eventfld.long 0x0 17. "debugl3noctimeout,A 1 indicates that Reset Manager's request to the NOC before starting a hardware sequenced reset timed-out and the Reset Manager had to proceed with the reset anyway." "0,1"
eventfld.long 0x0 16. "l3nocdbgtimeout,A 1 indicates that Reset Manager's request to the NOC before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog reset anyway. Reset Manager performs this handshake with.." "0,1"
rbitfld.long 0x0 13.--15. "Reserved_7,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x0 12. "f2stimeout,A 1 indicates that Reset Manager's handshake request to F2S(coherent ACE-lite port in MPFE) timed out and the Reset Manager proceeded with the hardware sequenced reset." "0,1"
eventfld.long 0x0 11. "f2sdramtimeout,A 1 indicates that Reset Manager's handshake request to F2SDRAM (non-coherent AXI port in MPFE) timed out and the Reset Manager proceeded with the hardware sequenced reset." "0,1"
eventfld.long 0x0 10. "soc2fpgatimeout,A 1 indicates that Reset Manager's handshake request to SOC2FPGA timed out and the Reset Manager proceeded with the hardware sequenced reset." "0,1"
eventfld.long 0x0 9. "lwsoc2fpgatimeout,A 1 indicates that Reset Manager's handshake request to LWSOC2FPGA timed out and the Reset Manager proceeded with the hardware sequenced reset." "0,1"
newline
hexmask.long.byte 0x0 4.--8. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x0 3. "etrstalltimeout,A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to stall its AXI master port before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog.." "0,1"
eventfld.long 0x0 2. "fpgahstimeout,A 1 indicates that Reset Manager's handshake request to FPGA before starting a hardware sequenced warm/watchdog reset timed-out and the Reset Manager had to proceed with the warm/watchdog reset anyway." "0,1"
rbitfld.long 0x0 1. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 0. "emiftimeout,A 1 indicates that Reset Manager's handshake request to the SDRAM Controller Subsystem timed out and the Reset Manager had to proceed with the warm/watchdog reset anyway." "0,1"
group.long 0x10++0xF
line.long 0x0 "hdsken,This register allows software to control whether or not to perform a handshake with certain peripherals before issuing a reset. These bits are cleared on a cold reset. If these bits are not set. writing to the 'hdskreq' register to request a.."
hexmask.long.word 0x0 18.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
bitfld.long 0x0 17. "debug_l3noc,This field controls whether to perform handshake with L3 NOC before asserting the csdap_rst or/and dbg_rst. If set to 1  the Reset Manager makes a request to the L3 NOC before issuing a reset. If set to 0  the handshake is not performed." "0,1"
bitfld.long 0x0 16. "l3noc_dbg,This field controls whether to perform handshake with L3 NOC before issuing a reset. If set to 1  the Reset Manager makes a request to the L3 NOC before issuing a reset. If set to 0  the handshake is not performed." "0,1"
rbitfld.long 0x0 13.--15. "Reserved_7,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12. "f2soc_flush,This field controls whether to fence and drain traffic on the MPFE F2S ACE-lite port before resetting the HPS. If set to 1  the Reset Manager makes a handshake request to the MPFE NoC before issuing a reset. If set to 0  the handshake is not.." "0,1"
bitfld.long 0x0 11. "f2sdram_flush,This field controls whether to fence and drain traffic on the MPFE F2SDRAM AXI4 port before resetting the HPS. If set to 1  the Reset Manager makes a handshake request to the MPFE NoC before issuing a reset. If set to 0  the handshake is.." "0,1"
bitfld.long 0x0 10. "soc2fpga_flush,This field controls whether to fence and drain traffic on the SOC2FPGA port before resetting the HPS. If set to 1  the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0  the handshake is not.." "0,1"
bitfld.long 0x0 9. "lwsoc2fpga_flush,This field controls whether to fence and drain traffic on the LWSOC2FPGA port before resetting the HPS. If set to 1  the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0  the handshake is not.." "0,1"
newline
hexmask.long.byte 0x0 4.--8. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 3. "etrstallen,Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect." "0,1"
bitfld.long 0x0 2. "fpgahsen,This field controls whether to perform handshake with FPGA before issuing a reset. If set to 1  the Reset Manager makes a request to the FPGA before issuing a reset. If set to 0  the handshake is not performed." "0,1"
rbitfld.long 0x0 1. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 0. "emif_flush,This field controls whether to perform handshake with the SDRAM memory interface before issuing a reset. If set to 1  the Reset Manager makes a request to the SDRAM memory interface before issuing a reset. If set to 0  the handshake is not.." "0,1"
line.long 0x4 "hdskreq,This register includes fields for software to initiate the handshake with certain peripherals. Software must clear the request bit except for 'debug_l3noc_req' once it sees the corresponding acknowledge bit has been set in the hdskack register."
hexmask.long.word 0x4 18.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
bitfld.long 0x4 17. "debug_l3noc_req,This field controls whether to fence and drain CoreSight traffic before resetting CoreSight logic. This handshake is performed when CS DAP or/and DBG is getting reset but the HPS is not getting reset. If set to 1  the Reset Manager makes.." "0,1"
bitfld.long 0x4 16. "l3noc_dbg_req,This field controls whether to fence and drain CoreSight traffic before resetting the HPS. This handshake is performed when the HPS is getting reset but CoreSight logic not getting reset. If set to 1  the Reset Manager makes a handshake.." "0,1"
rbitfld.long 0x4 13.--15. "Reserved_7,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12. "f2s_flush_req,This field controls whether to fence and drain traffic on the MPFE F2S ACE-lite port before resetting the HPS. If set to 1  the Reset Manager makes a handshake request to the MPFE NoC before issuing a reset. If set to 0  the handshake is.." "0,1"
bitfld.long 0x4 11. "f2sdram_flush_req,This field controls whether to fence and drain traffic on the MPFE F2SDRAM AXI4 port before resetting the HPS. If set to 1  the Reset Manager makes a handshake request to the MPFE NoC before issuing a reset. If set to 0  the handshake.." "0,1"
bitfld.long 0x4 10. "soc2fpga_flush_req,This field controls whether to fence and drain traffic on the SOC2FPGA port before resetting the HPS. If set to 1  the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0  the handshake is not.." "0,1"
bitfld.long 0x4 9. "lwsoc2fpga_flush_req,This field controls whether to fence and drain traffic on the LWSOC2FPGA port before resetting the HPS. If set to 1  the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0  the handshake is not.." "0,1"
newline
hexmask.long.byte 0x4 4.--8. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x4 3. "etrstallreq,This field controls whether to fence and drain traffic on the Embedder Trace Router (ETR) before resetting the HPS. If set to 1  the Reset Manager makes a handshake request to the PSS NoC before issuing a reset. If set to 0  the handshake is.." "0,1"
bitfld.long 0x4 2. "fpgahsreq,This field controls whether to alert SoftLogic of a pending HPS reset. If set to 1  the Reset Manager makes a handshake request to the Fabric before issuing a reset. If set to 0  the handshake is not performed." "0,1"
rbitfld.long 0x4 1. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x4 0. "emif_flush_req,This field controls whether to fence and drain traffic to MPFE EMIF (and future H-NoC) ports before resetting the HPS. If set to 1  the Reset Manager makes a handshake request to the MPFE NoC before issuing a reset. If set to 0  the.." "0,1"
line.long 0x8 "hdskack,This register includes fields for software to detect the completion of the handshake with certain peripherals. Once the peripheral has completed the handshake. it will set the appropriate bit in this register. Once software has detected that the.."
hexmask.long.word 0x8 18.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
eventfld.long 0x8 17. "debug_l3noc_ack,This field indicates that L3NOC handshake acknowledge has been received by Reset Manager. A 1 indicates that the L3NOC has acknowledged the handshake request." "0,1"
eventfld.long 0x8 16. "l3noc_dbg_ack,This field indicates that L3NOC handshake acknowledge has been received by Reset Manager. A 1 indicates that the L3NOC has acknowledged the handshake request." "0,1"
rbitfld.long 0x8 13.--15. "Reserved_7,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x8 12. "f2s_flush_ack" "0,1"
eventfld.long 0x8 11. "f2sdram_flush_ack,A '1' in this field indicates fence and drain of F2SDRAM traffic has completed." "0,1"
eventfld.long 0x8 10. "soc2fpga_flush_ack,A '1' in this field indicates fence and drain of SOC2FPGA traffic has completed." "0,1"
eventfld.long 0x8 9. "lwsoc2fpga_flush_ack,A '1' in this field indicates fence and drain of LWSOC2FPGA traffic has completed." "0,1"
newline
hexmask.long.byte 0x8 4.--8. 1. "Reserved_3,Reserved bitfield added by Magillem"
eventfld.long 0x8 3. "etrstallack,This is the acknowlege for a ETR AXI master stall initiated as a part of the ETR handshake. A 1 indicates that the ETR has stalled its AXI master." "0,1"
eventfld.long 0x8 2. "fpgahsack,This is the acknowledge that the FPGA handshake acknowledge has been received by Reset Manager. A 1 indicates that the FPGA has acknowledged the handshake request." "0,1"
rbitfld.long 0x8 1. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x8 0. "emif_flush_ack,A '1' in this field indicates fence and drain of EMIF traffic has completed." "0,1"
line.long 0xC "hdskstall,This register keeps the ETR stalled after a warm/watchdog reset occurs. If the ETR handshake is enabled in the bit field ETRSTALLEN of HDSKEN register. then the hardware will perform a handshake with the ETR before asserting a warm or watchdog.."
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0xC 0. "etrstallwarmrst,If ETRSTALLEN bit field is 1 and Reset manager generates the handshake request to ETR  hardware sets this bit to 1 to indicate that the stall of the ETR AXI master. Hardware leaves the ETR stalled after a warm or watchdog reset until.." "0,1"
group.long 0x24++0xB
line.long 0x0 "per0modrst,The PER0MODRST register is used by software to control module resets for Peripheral Group and Fast Peripheral Group. Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up.."
bitfld.long 0x0 31. "dmaif7,Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA Controller" "0,1"
bitfld.long 0x0 30. "dmaif6,Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA Controller" "0,1"
bitfld.long 0x0 29. "dmaif5,Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA Controller" "0,1"
bitfld.long 0x0 28. "dmaif4,Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA Controller" "0,1"
newline
bitfld.long 0x0 27. "dmaif3,Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA Controller." "0,1"
bitfld.long 0x0 26. "dmaif2,Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA Controller." "0,1"
bitfld.long 0x0 25. "dmaif1,Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA Controller" "0,1"
bitfld.long 0x0 24. "dmaif0,Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA Controller." "0,1"
newline
rbitfld.long 0x0 23. "Reserved_22,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x0 22. "emacptp,Resets EMAC PTP." "0,1"
bitfld.long 0x0 21. "dmaecc,Resets DMA Controller ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x0 20. "spis1,Resets SPIS1 controller." "0,1"
newline
bitfld.long 0x0 19. "spis0,Resets SPIS0 controller." "0,1"
bitfld.long 0x0 18. "spim1,Resets SPIM1 controller." "0,1"
bitfld.long 0x0 17. "spim0,Resets SPIM0 controller." "0,1"
bitfld.long 0x0 16. "dma,Resets DMA controller." "0,1"
newline
bitfld.long 0x0 15. "sdmmcecc,Resets SDMMC ECC OCP DIagnostics modules." "0,1"
rbitfld.long 0x0 14. "Reserved_14,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x0 13. "nandecc,Resets NAND ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x0 12. "usb1ecc,Resets USB3.1 ECC OCP DIagnostics modules." "0,1"
newline
bitfld.long 0x0 11. "usb0ecc,Resets USB2.0 ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x0 10. "tsn2ecc,Resets TSN2 ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x0 9. "tsn1ecc,Resets TSN1 ECC OCP DIagnostics modules." "0,1"
bitfld.long 0x0 8. "tsn0ecc,Resets TSN0 ECC OCP DIagnostics modules." "0,1"
newline
bitfld.long 0x0 7. "sdmmc,Resets SD/MMC controller." "0,1"
bitfld.long 0x0 6. "softphy,Reset SoftPHY" "0,1"
bitfld.long 0x0 5. "nand,Resets NAND flash controller." "0,1"
bitfld.long 0x0 4. "usb1,Resets USB3.1." "0,1"
newline
bitfld.long 0x0 3. "usb0,Resets USB2.0." "0,1"
bitfld.long 0x0 2. "tsn2,Resets TSN2" "0,1"
bitfld.long 0x0 1. "tsn1,Resets TSN1" "0,1"
bitfld.long 0x0 0. "tsn0,Resets TSN0" "0,1"
line.long 0x4 "per1modrst,The PER1MODRST register is used by software to trigger module resets for Slow Peripheral Group. Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure.."
hexmask.long.byte 0x4 27.--31. 1. "Reserved_20,Reserved bitfield added by Magillem"
bitfld.long 0x4 26. "watchdog4" "0,1"
bitfld.long 0x4 25. "gpio1,Resets GPIO1" "0,1"
bitfld.long 0x4 24. "gpio0,Resets GPIO0" "0,1"
newline
hexmask.long.byte 0x4 18.--23. 1. "Reserved_17,Reserved bitfield added by Magillem"
bitfld.long 0x4 17. "uart1,Resets UART1" "0,1"
bitfld.long 0x4 16. "uart0,Resets UART0" "0,1"
rbitfld.long 0x4 15. "Reserved_15,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x4 14. "i3c1,reset i3c1 controller" "0,1"
bitfld.long 0x4 13. "i3c0,reset i3c0 controller" "0,1"
bitfld.long 0x4 12. "i2c4,Resets I2c4 controller" "0,1"
bitfld.long 0x4 11. "i2c3,Resets i2c3 controller" "0,1"
newline
bitfld.long 0x4 10. "i2c2,Resets I2C2 controller" "0,1"
bitfld.long 0x4 9. "i2c1,Resets I2C1 controller" "0,1"
bitfld.long 0x4 8. "i2c0,Resets I2C0 controller" "0,1"
bitfld.long 0x4 7. "sptimer1,Resets SP timer 1 connected to L4" "0,1"
newline
bitfld.long 0x4 6. "sptimer0,Resets SP timer 0 connected to L4" "0,1"
bitfld.long 0x4 5. "l4systimer1,Resets l4sys_timer1" "0,1"
bitfld.long 0x4 4. "l4systimer0,Resets l4sys_timer0" "0,1"
bitfld.long 0x4 3. "watchdog3,Resets Watchdog 3" "0,1"
newline
bitfld.long 0x4 2. "watchdog2,Resets Watchdog 2" "0,1"
bitfld.long 0x4 1. "watchdog1,Resets Watchdog 1" "0,1"
bitfld.long 0x4 0. "watchdog0,Resets Watchdog 0" "0,1"
line.long 0x8 "brgmodrst,The BRGMODRST register is used by software to control the bridge module resets. Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure module reset.."
hexmask.long 0x8 7.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x8 6. "mpfe,Resets logic in the MPFE." "0,1"
rbitfld.long 0x8 4.--5. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3"
bitfld.long 0x8 3. "fpga2sdram,Resets fpga2sdram bridge" "0,1"
newline
bitfld.long 0x8 2. "fpga2soc,Resets FPGA2SOC Bridge." "0,1"
bitfld.long 0x8 1. "lwsoc2fpga,Resets LWHPS2FPGA Bridge." "0,1"
bitfld.long 0x8 0. "soc2fpga,Resets SOC2FPGA Bridge." "0,1"
group.long 0x3C++0x3
line.long 0x0 "dbgmodrst,The DBGMODRST register is used by software to control module resets."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "dbg_rst,Resets logic located in the debug domain." "0,1"
group.long 0x4C++0x3
line.long 0x0 "brgwarmmask,The 'BRGWARMMASK' register is used by software to mask the assertion of module reset signals on a warm reset. If the bit is 1. the module reset signal is asserted during a warm reset. If the bit is 0. the module reset signal is not asserted.."
hexmask.long 0x0 7.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
bitfld.long 0x0 6. "mpfe,Masks hardware sequenced warm reset for the MPFE." "0,1"
rbitfld.long 0x0 4.--5. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3"
bitfld.long 0x0 3. "fpga2sdram,Setting to '0' masks hardware sequenced warm reset of FPGA2SDRAM bridge." "0,1"
newline
bitfld.long 0x0 2. "fpga2soc,Masks hardware sequenced warm reset for FPGA2SOC Bridge" "0,1"
bitfld.long 0x0 1. "lwsoc2fpga,Masks hardware sequenced warm reset for LWHPS2FPGA Bridge" "0,1"
bitfld.long 0x0 0. "soc2fpga,Masks hardware sequenced warm reset for SOC2FPGA Bridge." "0,1"
rgroup.long 0x5C++0x3
line.long 0x0 "tststa,Status fields used for testing the Reset Manager."
hexmask.long 0x0 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--4. 1. "rstst,Warm/cold reset control FSM state."
group.long 0x64++0x3
line.long 0x0 "hdsktimeout,The Warm Reset handshake time-out controls the amount of time to wait for the ETR. FPGA and SDRAM interface to respond to a reset handshake request. The register defaults to 10.240 l4_sys_free_clk cycles. which at 100 MHz will be 102.4.."
hexmask.long 0x0 0.--31. 1. "val,Timeout value for ETR  FPGA  SDRAM  F2SDRAM  F2SOC  SOC2HPS  LWSOC2HPS"
group.long 0x6C++0x7
line.long 0x0 "dbghdsktimeout,The reset handshake time-out register controls the amount of time to wait for the L3NOC interface to respond to a reset handshake request."
hexmask.long 0x0 0.--31. 1. "val,L3NOC interface handshake time-out value."
line.long 0x4 "dbgrstcmplt,Reset Manager sets to 1 when a SW requested debug reset sequence is completed. Cleared by Reset Manager after SW clears dbgmodrst[dbg_rst]"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x4 0. "swdbgrstcmplt,Reset Manager sets to 1 when a SW requested debug reset sequence is completed. Cleared by Reset Manager after SW clears dbgmodrst[dbg_rst]" "0,1"
group.long 0x80++0x3
line.long 0x0 "hpsrstcmplt"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
eventfld.long 0x0 0. "hpsrstcmplt,A status register indicating that an HPS reset sequence is waiting for further input from the SDM such as downloading the FSBL and/or writing a cpux_release bit. A first write to a cpurstrelease[cpux_release] bit clears this register." "0,1"
rgroup.long 0x90++0x3
line.long 0x0 "cpuinreset,The COLDMODRST register is used by software to trigger module resets. Writing 1 to any of these fields will cause the L2 or CPU POR reset signal to be asserted if that module is in WFI mode. The Reset Manager hardware will bring the module.."
hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 3. "cpu3_in_reset,CPU3 in reset" "0,1"
bitfld.long 0x0 2. "cpu2_in_reset,CPU2 in reset" "0,1"
bitfld.long 0x0 1. "cpu1_in_reset,CPU1 in reset" "0,1"
newline
bitfld.long 0x0 0. "cpu0_in_reset,CPU0 in reset" "0,1"
group.long 0x94++0x23
line.long 0x0 "cpurstrelease,Write to 0x1 to release the corresponding core from reset. The cpu shall boot from the address in the corresponding cpux_reset_base_high/cpux_reset_base_low register pair"
hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x0 3. "cpu3_release,Write to 0x1 to release the corresponding core from reset. The cpu shall boot from the address in the corresponding cpux_reset_base_high/cpux_reset_base_low register pair" "0,1"
bitfld.long 0x0 2. "cpu2_release,Write to 0x1 to release the corresponding core from reset. The cpu shall boot from the address in the corresponding cpux_reset_base_high/cpux_reset_base_low register pair" "0,1"
bitfld.long 0x0 1. "cpu1_release,Write to 0x1 to release the corresponding core from reset. The cpu shall boot from the address in the corresponding cpux_reset_base_high/cpux_reset_base_low register pair" "0,1"
newline
bitfld.long 0x0 0. "cpu0_release,Write to 0x1 to release the corresponding core from reset. The cpu shall boot from the address in the corresponding cpux_reset_base_high/cpux_reset_base_low register pair" "0,1"
line.long 0x4 "cpu0_reset_base_low,Drives RVBARAAR0[31:2]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address"
rbitfld.long 0x4 30.--31. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long 0x4 0.--29. 1. "vector_base_low,CPU0 Reset vector address [31:02]"
line.long 0x8 "cpu0_reset_base_high,Drives RVBARAAR0[39:32]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address"
hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 0.--7. 1. "vector_base_high,CPU0 Reset vector address [39:32]"
line.long 0xC "cpu1_reset_base_low,Drives RVBARAAR1[31:2]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address"
rbitfld.long 0xC 30.--31. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long 0xC 0.--29. 1. "vector_base_low,CPU1 Reset vector address [31:02]"
line.long 0x10 "cpu1_reset_base_high,Drives RVBARAAR1[39:32]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address"
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x10 0.--7. 1. "vector_base_high,CPU1 Reset vector address [39:32]"
line.long 0x14 "cpu2_reset_base_low,Drives RVBARAAR2[31:2]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address"
rbitfld.long 0x14 30.--31. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long 0x14 0.--29. 1. "vector_base_low,CPU2 Reset vector address [31:02]"
line.long 0x18 "cpu2_reset_base_high,Drives RVBARAAR2[39:32]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address"
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x18 0.--7. 1. "vector_base_high,CPU2 Reset vector address [39:32]"
line.long 0x1C "cpu3_reset_base_low,Drives RVBARAAR3[31:2]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address"
rbitfld.long 0x1C 30.--31. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long 0x1C 0.--29. 1. "vector_base_low,CPU3 Reset vector address [31:02]"
line.long 0x20 "cpu3_reset_base_high,Drives RVBARAAR3[39:32]. Defaults to 0x0 on cold reset. Can be changed by priviledged software to any other location. User responsible for supplying valid address"
hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x20 0.--7. 1. "vector_base_high,CPU3 Reset vector address [39:32]"
tree.end
tree "SDMMC"
base ad:0x10808000
group.long 0x0++0x3B
line.long 0x0 "HRS00,HRS00 - General Information Register"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 16.--23. 1. "SAV,SAV - Slot Available\n"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "SWR,SWR - Software Reset\n" "0,1"
line.long 0x4 "HRS01,HRS01 - Debounce Setting Register"
hexmask.long.byte 0x4 24.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.tbyte 0x4 0.--23. 1. "DP,DP - Debounce Period\n"
line.long 0x8 "HRS02,HRS02 - Bus Setting Register"
hexmask.long.word 0x8 18.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x8 16.--17. "OTN,OTN - Number of Outstanding Transfers\n" "0,1,2,3"
hexmask.long.word 0x8 4.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 0.--3. 1. "PBL,PBL - Programmable Burst Length\n"
line.long 0xC "HRS03,HRS03 - AXI ERROR Responses Register\n"
hexmask.long.word 0xC 20.--31. 1. "Reserved_12,Reserved bitfield added by Magillem"
bitfld.long 0xC 19. "AER_IEBS,AER_IEBS - Signal Enable for AXI ERROR Response B channel: SLVERR\n" "0,1"
bitfld.long 0xC 18. "AER_IEBD,AER_IEBD - Signal Enable for AXI ERROR Response B channel: DECERR\n" "0,1"
bitfld.long 0xC 17. "AER_IERS,AER_IERS - Signal Enable for AXI ERROR Response R channel: SLVERR\n" "0,1"
newline
bitfld.long 0xC 16. "AER_IERD,AER_IERD - Signal Enable for AXI ERROR Response R channel: DECERR\n" "0,1"
hexmask.long.byte 0xC 12.--15. 1. "Reserved_8,Reserved bitfield added by Magillem"
bitfld.long 0xC 11. "AER_SENBS,AER_SENBS - Status Enable for AXI ERROR Response B channel: SLVERR\n" "0,1"
bitfld.long 0xC 10. "AER_SENBD,AER_SENBD - Status Enable for AXI ERROR Response B channel: DECERR\n" "0,1"
newline
bitfld.long 0xC 9. "AER_SENRS,AER_SENRS - Status Enable for AXI ERROR Response R channel: SLVERR\n" "0,1"
bitfld.long 0xC 8. "AER_SENRD,AER_SENRD - Status Enable for AXI ERROR Response R channel: DECERR\n" "0,1"
hexmask.long.byte 0xC 4.--7. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0xC 3. "AER_BS,AER_BS - AXI ERROR Response B channel: SLVERR\n" "0,1"
newline
eventfld.long 0xC 2. "AER_BD,AER_BD - AXI ERROR Response B channel: DECERR\n" "0,1"
eventfld.long 0xC 1. "AER_RS,AER_RS - AXI ERROR Response R channel: SLVERR\n" "0,1"
eventfld.long 0xC 0. "AER_RD,AER_RD - AXI ERROR Response R channel: DECERR\n" "0,1"
line.long 0x10 "HRS04"
hexmask.long.word 0x10 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x10 0.--15. 1. "PHYREGADDR,PHYREGADDR - PHY Register Address\n"
line.long 0x14 "HRS05"
hexmask.long 0x14 0.--31. 1. "PHYREGDATA,PHYREGDATA - PHY Register Data Port\n"
line.long 0x18 "HRS06,HRS06 - eMMC control registers"
hexmask.long 0x18 3.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x18 0.--2. "EMM,EMM - eMMC Mode select\n" "0,1,2,3,4,5,6,7"
line.long 0x1C "HRS07,HRS07 - IO Delay Information Register"
hexmask.long.word 0x1C 21.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
hexmask.long.byte 0x1C 16.--20. 1. "RW_COMPENSATE,RW_COMPENSATE - Read Wait Compensate value \n"
hexmask.long.word 0x1C 5.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x1C 0.--4. 1. "IDELAY_VAL,IDELAY_VAL - Input delay value for IO. \n"
line.long 0x20 "HRS08,HRS08 - PHY DLL Update Control and Status Register"
hexmask.long 0x20 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
rbitfld.long 0x20 1. "PHY_DLL_UPDACK,PHY_DLL_UPDACK\n" "0,1"
bitfld.long 0x20 0. "PHY_DLL_UPDREQ,PHY_DLL_UPDREQ\n" "0,1"
line.long 0x24 "HRS09,HRS09 - PHY Control and Status Register"
hexmask.long.byte 0x24 28.--31. 1. "LVSI_CNT,LVSI_CNT\n"
hexmask.long.byte 0x24 22.--27. 1. "LVSI_TCKSEL,LVSI_TCKSEL\n"
hexmask.long.byte 0x24 17.--21. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x24 16. "RDDATA_EN,RDDATA_EN\n" "0,1"
newline
bitfld.long 0x24 15. "RDCMD_EN,RDCMD_EN\n" "0,1"
hexmask.long.word 0x24 4.--14. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x24 3. "EXTENDED_WR_MODE,EXTENDED_WR_MODE\n" "0,1"
bitfld.long 0x24 2. "EXTENDED_RD_MODE,EXTENDED_RD_MODE\n" "0,1"
newline
rbitfld.long 0x24 1. "PHY_INIT_COMPLETE,PHY_INIT_COMPLETE\n" "0,1"
bitfld.long 0x24 0. "PHY_SW_RESET,PHY_SW_RESET\n" "0,1"
line.long 0x28 "HRS10,HRS10 - Host Controller SDCLK start point adjustment"
hexmask.long.word 0x28 23.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x28 22. "RDDATA_SWAP,Reserved" "0,1"
rbitfld.long 0x28 20.--21. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x28 16.--19. 1. "HCSDCLKADJ,HCSDCLKADJ\n"
newline
hexmask.long.word 0x28 0.--15. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x2C "HRS11,Reserved"
hexmask.long 0x2C 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x2C 0. "EMMC_RST,EMMC_RST\n" "0,1"
line.long 0x30 "HRS12,HRS12 - Host Interrupt Status"
hexmask.long 0x30 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x30 3. "PHYDATOF,PHY DAT Overflow - Status received from Combo PHY informing about DAT FIFO status." "0,1"
eventfld.long 0x30 2. "PHYDATUR,PHY DAT Underrun - Status received from Combo PHY informing about DAT FIFO status." "0,1"
eventfld.long 0x30 1. "PHYCMDOF,PHY CMD Overflow - Status received from Combo PHY informing about CMD FIFO status." "0,1"
newline
eventfld.long 0x30 0. "PHYCMDUR,PHY CMD Underrun - Status received from Combo PHY informing about CMD FIFO status." "0,1"
line.long 0x34 "HRS13,HRS13 - Host Status Enable"
hexmask.long 0x34 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x34 3. "PHYDATOF_SE,Mask for PHYDATOF status\n" "0,1"
bitfld.long 0x34 2. "PHYDATUR_SE,Mask for PHYDATUR status\n" "0,1"
bitfld.long 0x34 1. "PHYCMDOF_SE,Mask for PHYCMDOF status\n" "0,1"
newline
bitfld.long 0x34 0. "PHYCMDUR_SE,Mask for PHYCMDUR status\n" "0,1"
line.long 0x38 "HRS14,HRS14 - Host Signal Enable"
hexmask.long 0x38 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x38 3. "PHYDATOF_IE,Interrupt enable for PHYDATOF status\n" "0,1"
bitfld.long 0x38 2. "PHYDATUR_IE,Interrupt enable for PHYDATUR status\n" "0,1"
bitfld.long 0x38 1. "PHYCMDOF_IE,Interrupt enable for PHYCMDOF status\n" "0,1"
newline
bitfld.long 0x38 0. "PHYCMDUR_IE,Interrupt enable for PHYCMDUR status\n" "0,1"
group.long 0x40++0x3
line.long 0x0 "HRS16,HRS16 - CMD/DAT output delay"
hexmask.long.byte 0x0 28.--31. 1. "WRDATA1_SDCLK_DLY,Reserved"
hexmask.long.byte 0x0 24.--27. 1. "WRDATA0_SDCLK_DLY,WRDATA0_SDCLK_DLY\n"
hexmask.long.byte 0x0 20.--23. 1. "WRCMD1_SDCLK_DLY,Reserved"
hexmask.long.byte 0x0 16.--19. 1. "WRCMD0_SDCLK_DLY,WRCMD0_SDCLK_DLY\n"
newline
hexmask.long.byte 0x0 12.--15. 1. "WRDATA1_DLY,Reserved"
hexmask.long.byte 0x0 8.--11. 1. "WRDATA0_DLY,WRDATA0_DLY\n"
hexmask.long.byte 0x0 4.--7. 1. "WRCMD1_DLY,Reserved"
hexmask.long.byte 0x0 0.--3. 1. "WRCMD0_DLY,WRCMD0_DLY\n"
rgroup.long 0x74++0xB
line.long 0x0 "HRS29,HRS29 - SD Magic Number\n"
hexmask.long 0x0 0.--31. 1. "SDMAGICNUM,This product number is"
line.long 0x4 "HRS30,HRS30 - Host Capability Register\n"
hexmask.long 0x4 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 1. "HS400ESSUP,High Speed 400 Enhance Strobe supported\n" "0,1"
bitfld.long 0x4 0. "CQSUP,Command Queuing supported\n" "0,1"
line.long 0x8 "HRS31,HRS31 - Host Controller Version\n"
hexmask.long.byte 0x8 28.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
hexmask.long.word 0x8 16.--27. 1. "HOSTCTRLVER,Host Controller Version\n"
hexmask.long.byte 0x8 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 0.--7. 1. "HOSTFIXVER,Fix Version Number\n"
group.long 0x80++0x3
line.long 0x0 "HRS32,HRS32 - FSM Monitor Register"
bitfld.long 0x0 31. "LOAD,LOAD - FSM monitor update request\n" "0,1"
hexmask.long.word 0x0 16.--30. 1. "ADDR,ADDR - FSM address\n"
hexmask.long.word 0x0 0.--15. 1. "DATA,DATA - FSM status\n"
rgroup.long 0x84++0x7
line.long 0x0 "HRS33,HRS33 - Tune Status 0 Register"
hexmask.long 0x0 0.--31. 1. "STAT0,STAT0 - Tune status 0\n"
line.long 0x4 "HRS34,HRS34 - Tune Status 1 Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 0.--7. 1. "STAT1,STAT1 - Tune status 1\n"
rgroup.long 0x90++0x3
line.long 0x0 "HRS36,Reserved"
hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
bitfld.long 0x0 6. "BOOT_EDM,Boot Error - Descriptor Mechanism Error" "0,1"
bitfld.long 0x0 5. "BOOT_EDE,Boot Error - End Bit Error" "0,1"
bitfld.long 0x0 4. "BOOT_EDC,Boot Error - Data CRC Error" "0,1"
newline
bitfld.long 0x0 3. "BOOT_EDT,Boot Error - Data Timeout Error" "0,1"
bitfld.long 0x0 2. "BOOT_EAI,Boot Error - Invalid Acknowledge Error" "0,1"
bitfld.long 0x0 1. "BOOT_EAT,Boot Error - Acknowledge Timeout Error" "0,1"
bitfld.long 0x0 0. "BOOT_ACT,Boot Active\n" "0,1"
group.long 0xA0++0xB
line.long 0x0 "HRS40,Reserved"
hexmask.long 0x0 0.--31. 1. "BASE_ADDR0,BASE_ADDR0 - lower descriptor list base address\n"
line.long 0x4 "HRS41,Reserved"
hexmask.long 0x4 0.--31. 1. "BASE_ADDR1,BASE_ADDR1 - higher descriptor list base address\n"
line.long 0x8 "HRS42,Reserved"
hexmask.long 0x8 5.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 1.--4. 1. "DESCMECH_TM,DESCMECH_TM - Descritor mechanism timeout value\n"
bitfld.long 0x8 0. "DESCMECH_EN,DESCMECH_EN - Enable/disable auto-configuration descritor mechanism for Host/PHY pre-initialization sequence update.\n" "0,1"
rgroup.long 0xAC++0x3
line.long 0x0 "HRS43,Reserved"
hexmask.long 0x0 4.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 1.--3. "ERROR_VAL,ERROR_VAL - auto-configuration descriptor mechanism error type\n" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 0. "ERROR_ST,Error occured during auto-configuration descriptor mechanism performance.\n" "0,1"
group.long 0x200++0xF
line.long 0x0 "SRS00,SRS00 - SDMA System Address / Argument 2"
hexmask.long 0x0 0.--31. 1. "SAAR,SAAR - System Address / Argument 2"
line.long 0x4 "SRS01,SRS01 - Block Size / Block Count"
hexmask.long.word 0x4 16.--31. 1. "BCCT,BCCT - Block Count For Current Transfer\n"
rbitfld.long 0x4 15. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x4 12.--14. "SDMABB,SDMABB - SDMA Buffer Boundary\n" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x4 0.--11. 1. "TBS,TBS - Transfer Block Size\n"
line.long 0x8 "SRS02,SRS02 - Argument 1"
hexmask.long 0x8 0.--31. 1. "ARG1,ARG1 - Command Argument 1\n"
line.long 0xC "SRS03,SRS03 - Command/Transfer Mode"
rbitfld.long 0xC 30.--31. "Reserved_15,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0xC 24.--29. 1. "CIDX,CIDX - Command Index\n"
bitfld.long 0xC 22.--23. "CT,CT - Command Type\n" "0,1,2,3"
bitfld.long 0xC 21. "DPS,DPS - Data Present Select\n" "0,1"
newline
bitfld.long 0xC 20. "CICE,CICE - Command Index Check Enable\n" "0: 0,1: 0"
bitfld.long 0xC 19. "CRCCE,CRCCE - Command CRC Check Enable\n" "0: 0,1: 1"
bitfld.long 0xC 18. "SCF,SCF - Sub Command Flag\n" "0,1"
bitfld.long 0xC 16.--17. "RTS,RTS - Response Type Select\n" "0,1,2,3"
newline
hexmask.long.byte 0xC 9.--15. 1. "Reserved_8,Reserved bitfield added by Magillem"
bitfld.long 0xC 8. "RID,RID - Response Interrupt Disable\n" "0,1"
bitfld.long 0xC 7. "RECE,RECE - Response Error Check Enable\n" "0,1"
bitfld.long 0xC 6. "RECT,RECT - Response Type R1/R5\n" "0,1"
newline
bitfld.long 0xC 5. "MSBS,MSBS - Multi/Single Block Select\n" "0,1"
bitfld.long 0xC 4. "DTDS,DTDS - Data Transfer Direction Select\n" "0,1"
bitfld.long 0xC 2.--3. "ACE,ACE - Auto CMD Enable\n" "0,1,2,3"
bitfld.long 0xC 1. "BCE,BCE - Block Count Enable\n" "0,1"
newline
bitfld.long 0xC 0. "DMAE,DMAE - DMA Enable\n" "0,1"
rgroup.long 0x210++0xF
line.long 0x0 "SRS04,The SRS04 - SRS07 registers store the response returned by the card.\n"
hexmask.long 0x0 0.--31. 1. "RESP0,RESP0 - Response Register #0"
line.long 0x4 "SRS05,Described in SRS04."
hexmask.long 0x4 0.--31. 1. "RESP1,RESP1 - Response Register #1"
line.long 0x8 "SRS06,Described in SRS04."
hexmask.long 0x8 0.--31. 1. "RESP2,RESP2 - Response Register #2"
line.long 0xC "SRS07,Described in SRS04."
hexmask.long 0xC 0.--31. 1. "RESP3,RESP3 - Response Register #3"
group.long 0x220++0x3
line.long 0x0 "SRS08,SRS08 - Data Buffer"
hexmask.long 0x0 0.--31. 1. "BDP,BDP - Buffer Data Port\n"
rgroup.long 0x224++0x3
line.long 0x0 "SRS09,SRS09 - Present State Register"
bitfld.long 0x0 29.--31. "Reserved_17,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 28. "SCMDS,SCMDS - Sub Command Status\n" "0,1"
bitfld.long 0x0 27. "CNIBE,CNIBE - Command Not Issued By Error\n" "0,1"
bitfld.long 0x0 26. "LVSIRSLT,LVSIRSLT - LVS Identification Result\n" "0,1"
newline
bitfld.long 0x0 25. "Reserved_14,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x0 24. "CMDSL,CMDSL - CMD Line Signal Level\n" "0,1"
hexmask.long.byte 0x0 20.--23. 1. "DATSL1,DATSL1 - DAT[3:0] Line Signal Level\n"
bitfld.long 0x0 19. "WPSL,WPSL - Write Protect Switch Pin Level\n" "0,1"
newline
bitfld.long 0x0 18. "CDSL,CDSL - Card Detect Pin Level\n" "0,1"
bitfld.long 0x0 17. "CSS,CSS - Card State Stable\n" "0,1"
bitfld.long 0x0 16. "CI,CI - Card Inserted\n" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "Reserved_8,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 11. "BRE,BRE - Buffer Read Enable\n" "0,1"
bitfld.long 0x0 10. "BWE,BWE - Buffer Write Enable\n" "0,1"
bitfld.long 0x0 9. "RTA,RTA - Read Transfer Active\n" "0,1"
bitfld.long 0x0 8. "WTA,WTA - Write Transfer Active\n" "0,1"
newline
hexmask.long.byte 0x0 4.--7. 1. "DATSL2,DATSL2 - DAT[7:4] Line Signal Level\n"
bitfld.long 0x0 3. "Reserved_3,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x0 2. "DLA,DLA - DAT Line Active\n" "0,1"
bitfld.long 0x0 1. "CIDAT,CIDAT - Command Inhibit DAT\n" "0,1"
newline
bitfld.long 0x0 0. "CICMD,CICMD - Command Inhibit CMD\n" "0,1"
group.long 0x228++0x17
line.long 0x0 "SRS10,SRS10 - Host Control 1 (General / Power / Block-Gap / Wake-Up)"
hexmask.long.byte 0x0 27.--31. 1. "Reserved_16,Reserved bitfield added by Magillem"
bitfld.long 0x0 26. "WORM,WORM - Wakeup Event Enable On SD Card Removal\n" "0,1"
bitfld.long 0x0 25. "WOIS,WOIS - Wake-Up Event Enable On Card Inserted\n" "0,1"
bitfld.long 0x0 24. "WOIQ,WOIQ - Wakeup Event Enable On Card Interrupt\n" "0,1"
newline
hexmask.long.byte 0x0 20.--23. 1. "Reserved_13,Reserved bitfield added by Magillem"
bitfld.long 0x0 19. "IBG,IBG - Interrupt At Block Gap\n" "0,1"
bitfld.long 0x0 18. "RWC,RWC - Read-Wait Control\n" "0,1"
bitfld.long 0x0 17. "CREQ,CR - Continue Request\n" "0,1"
newline
bitfld.long 0x0 16. "SBGR,SBGR - Stop At Block Gap Request\n" "0,1"
hexmask.long.byte 0x0 12.--15. 1. "Reserved_9,Reserved bitfield added by Magillem"
bitfld.long 0x0 9.--11. "BVS,BVS - SD Bus Voltage Select\n" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 8. "BP,BP - SD Bus Power for VDD1\n" "0,1"
newline
bitfld.long 0x0 7. "CDSS,CDSS - Card Detect Signal Selection\n" "0,1"
bitfld.long 0x0 6. "CDTL,CDTL - Card Detect Test Level\n" "0,1"
bitfld.long 0x0 5. "EDTW,EDTW - Extended Data Transfer Width\n" "0,1"
bitfld.long 0x0 3.--4. "DMASEL,DMASEL - DMA Select\n" "0,1,2,3"
newline
bitfld.long 0x0 2. "HSE,HSE - High Speed Enable\n" "0,1"
bitfld.long 0x0 1. "DTW,DTW - Data Transfer Width\n" "0,1"
bitfld.long 0x0 0. "LEDC,LEDC - LED Control\n" "0,1"
line.long 0x4 "SRS11,SRS11 - Host Control 2 (Clock. Timeout. Reset)"
hexmask.long.byte 0x4 27.--31. 1. "Reserved_9,Reserved bitfield added by Magillem"
bitfld.long 0x4 26. "SRDAT,SRDAT - Software Reset For DAT Line\n" "0,1"
bitfld.long 0x4 25. "SRCMD,SRCMD - Software Reset For CMD Line\n" "0,1"
bitfld.long 0x4 24. "SRFA,SRFA - Software Reset For All\n" "0,1"
newline
hexmask.long.byte 0x4 20.--23. 1. "Reserved_6,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 16.--19. 1. "DTCV,DTCV - Data Timeout Counter Value\n"
hexmask.long.byte 0x4 8.--15. 1. "SDCFSL,SDCFSL - SDCLK Frequency Select (lower part)\n"
bitfld.long 0x4 6.--7. "SDCFSH,SDCFSH - SDCLK Frequency Select (higher part)\n" "0,1,2,3"
newline
rbitfld.long 0x4 3.--5. "Reserved_3,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 2. "SDCE,SDCE - SD Clock Enable\n" "0,1"
rbitfld.long 0x4 1. "ICS,ICS - Internal Clock Stable\n" "0,1"
bitfld.long 0x4 0. "ICE,ICE - Internal Clock Enable\n" "0,1"
line.long 0x8 "SRS12,SRS12 - Error/Normal Interrupt Status"
hexmask.long.byte 0x8 28.--31. 1. "Reserved_23,Reserved bitfield added by Magillem"
eventfld.long 0x8 27. "ERSP,ERSP - Response Error\n" "0,1"
rbitfld.long 0x8 26. "Reserved_22,Reserved bitfield added by Magillem" "0,1"
eventfld.long 0x8 25. "EADMA,EADMA - ADMA Error\n" "0,1"
newline
eventfld.long 0x8 24. "EAC,EAC - Auto CMD Error (SD mode only)\n" "0,1"
eventfld.long 0x8 23. "ECL,ECL - Current Limit Error\n" "0,1"
eventfld.long 0x8 22. "EDEB,EDEB - Data End Bit Error (SD mode only)\n" "0,1"
eventfld.long 0x8 21. "EDCRC,EDCRC - Data CRC Error (SD mode only)\n" "0,1"
newline
eventfld.long 0x8 20. "EDT,EDT - Data Timeout Error (SD mode only)\n" "0,1"
eventfld.long 0x8 19. "ECI,ECI - Command Index Error (SD mode only)\n" "0,1"
eventfld.long 0x8 18. "ECEB,ECEB - Command End Bit Error (SD mode only)\n" "0,1"
eventfld.long 0x8 17. "ECCRC,ECCRC - Command CRC Error (SD mode only)\n" "0,1"
newline
eventfld.long 0x8 16. "ECT,ECT - Command Timeout Error\n" "0,1"
rbitfld.long 0x8 15. "EINT,EINT - Error Interrupt\n" "0,1"
rbitfld.long 0x8 14. "CQINT,CQINT - Command Queuing Interrupt\n" "0,1"
rbitfld.long 0x8 13. "FXE,FXE - FX Event\n" "0,1"
newline
hexmask.long.byte 0x8 9.--12. 1. "Reserved_9,Reserved bitfield added by Magillem"
rbitfld.long 0x8 8. "CINT,CINT - Card Interrupt\n" "0,1"
eventfld.long 0x8 7. "CR,CR - Card Removal\n" "0,1"
eventfld.long 0x8 6. "CIN,CIN - Card Insertion\n" "0,1"
newline
eventfld.long 0x8 5. "BRR,BRR - Buffer Read Ready\n" "0,1"
eventfld.long 0x8 4. "BWR,BWR - Buffer Write Ready\n" "0,1"
eventfld.long 0x8 3. "DMAINT,DMAINT - DMA Interrupt\n" "0,1"
eventfld.long 0x8 2. "BGE,BGE - Block Gap Event\n" "0,1"
newline
eventfld.long 0x8 1. "TC,TC - Transfer Complete\n" "0,1"
eventfld.long 0x8 0. "CC,CC - Command Complete\n" "0,1"
line.long 0xC "SRS13,SRS13 - Error/Normal Status Enable"
hexmask.long.byte 0xC 28.--31. 1. "Reserved_22,Reserved bitfield added by Magillem"
bitfld.long 0xC 27. "ERSP_SE,ERSP_SE - Response Error Status Enable (SD mode only)\n" "0,1"
rbitfld.long 0xC 26. "Reserved_21,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 25. "EADMA_SE,EADMA_SE - ADMA Error Status Enable (SD mode only)\n" "0,1"
newline
bitfld.long 0xC 24. "EAC_SE,EAC_SE - Auto CMD Error Status Enable (SD mode only)\n" "0,1"
bitfld.long 0xC 23. "ECL_SE,ECL_SE - Current Limit Error Status Enable (SD mode only)\n" "0,1"
bitfld.long 0xC 22. "EDEB_SE,EDEB_SE - Data End Bit Error Status Enable (SD mode only)\n" "0,1"
bitfld.long 0xC 21. "EDCRC_SE,EDCRC_SE - Data CRC Error Status Enable (SD mode only)\n" "0,1"
newline
bitfld.long 0xC 20. "EDT_SE,EDT_SE - Data Timeout Error Status Enable (SD mode only)\n" "0,1"
bitfld.long 0xC 19. "ECI_SE,ECI_SE - Command Index Error Status Enable (SD mode only)\n" "0,1"
bitfld.long 0xC 18. "ECEB_SE,ECEB_SE - Command End Bit Error Status Enable (SD mode only)\n" "0,1"
bitfld.long 0xC 17. "ECCRC_SE,ECCRC_SE - Command CRC Error Status Enable (SD mode only)\n" "0,1"
newline
bitfld.long 0xC 16. "ECT_SE,ECT_SE - Command Timeout Error Status Enable (SD mode only)\n" "0,1"
rbitfld.long 0xC 15. "Reserved_11,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0xC 14. "CQINT_SE,CQINT_SE - Command Queuing Status Enable\n" "0,1"
bitfld.long 0xC 13. "FXE_SE,FXE_SE - FX Event Status Enable \n" "0,1"
newline
hexmask.long.byte 0xC 9.--12. 1. "Reserved_9,Reserved bitfield added by Magillem"
bitfld.long 0xC 8. "CINT_SE,CINT_SE - Card Interrupt Status Enable\n" "0,1"
bitfld.long 0xC 7. "CR_SE,CR_SE - Card Removal Status Enable\n" "0,1"
bitfld.long 0xC 6. "CIN_SE,CIN_SE -Card Insertion Status Enable\n" "0,1"
newline
bitfld.long 0xC 5. "BRR_SE,BRR_SE - Buffer Read Ready Status Enable\n" "0,1"
bitfld.long 0xC 4. "BWR_SE,BWR_SE - Buffer Write Ready Status Enable\n" "0,1"
bitfld.long 0xC 3. "DMAINT_SE,DMAINT_SE - DMA Interrupt Status Enable\n" "0,1"
bitfld.long 0xC 2. "BGE_SE,BGE_SE - Block Gap Event Status Enable\n" "0,1"
newline
bitfld.long 0xC 1. "TC_SE,TC_SE - Transfer Complete Status Enable\n" "0,1"
bitfld.long 0xC 0. "CC_SE,CC_SE - Command Complete Status Enable\n" "0,1"
line.long 0x10 "SRS14,SRS14 - Error/Normal Signal Enable"
hexmask.long.byte 0x10 28.--31. 1. "Reserved_22,Reserved bitfield added by Magillem"
bitfld.long 0x10 27. "ERSP_IE,ERSP_IE - Response Error Interrupt Enable\n" "0,1"
rbitfld.long 0x10 26. "Reserved_21,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 25. "EADMA_IE,EADMA_IE - ADMA Error Interrupt Enable (SD mode only)\n" "0,1"
newline
bitfld.long 0x10 24. "EAC_IE,EAC_IE - Auto CMD Error Interrupt Enable (SD mode only)\n" "0,1"
bitfld.long 0x10 23. "ECL_IE,ECL_IE - Current Limit Error Interrupt Enable (SD mode only)\n" "0,1"
bitfld.long 0x10 22. "EDEB_IE,EDEB_IE - Data End Bit Error Interrupt Enable (SD mode only)\n" "0,1"
bitfld.long 0x10 21. "EDCRC_IE,EDCRC_IE - Data CRC Error Interrupt Enable (SD mode only)\n" "0,1"
newline
bitfld.long 0x10 20. "EDT_IE,EDT_IE - ata Timeout Error Interrupt Enable (SD mode only)\n" "0,1"
bitfld.long 0x10 19. "ECI_IE,ECI_IE - Command Index Error Interrupt Enable (SD mode only)\n" "0,1"
bitfld.long 0x10 18. "ECEB_IE,ECEB_IE - Command End Bit Error Interrupt Enable (SD mode only)\n" "0,1"
bitfld.long 0x10 17. "ECCRC_IE,ECCRC_IE - Command CRC Error Interrupt Enable (SD mode only)\n" "0,1"
newline
bitfld.long 0x10 16. "ECT_IE,ECT_IE - Command Timeout Error Interrupt Enable (SD mode only)\n" "0,1"
rbitfld.long 0x10 15. "Reserved_11,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x10 14. "CQINT_IE,CQINT_IE - Command Queuing - Interrupt Enable\n" "0,1"
bitfld.long 0x10 13. "FXE_IE,FXE_IE - FX Event Interrupt Enable \n" "0,1"
newline
hexmask.long.byte 0x10 9.--12. 1. "Reserved_9,Reserved bitfield added by Magillem"
bitfld.long 0x10 8. "CINT_IE,CINT_IE - Card Interrupt - Interrupt Enable\n" "0,1"
bitfld.long 0x10 7. "CR_IE,CR_IE - Card Removal Interrupt Enable\n" "0,1"
bitfld.long 0x10 6. "CIN_IE,CIN_IE - Card Insertion Interrupt Enable\n" "0,1"
newline
bitfld.long 0x10 5. "BRR_IE,BRR_IE - Buffer Read Ready Interrupt Enable\n" "0,1"
bitfld.long 0x10 4. "BWR_IE,BWR_IE - Buffer Write Ready Interrupt Enable\n" "0,1"
bitfld.long 0x10 3. "DMAINT_IE,DMAINT_IE - DMA Interrupt Enable\n" "0,1"
bitfld.long 0x10 2. "BGE_IE,BGE_IE - Block Gap Event Interrupt Enable\n" "0,1"
newline
bitfld.long 0x10 1. "TC_IE,TC_IE - Transfer Complete Interrupt Enable\n" "0,1"
bitfld.long 0x10 0. "CC_IE,CC_IE - Command Complete Interrupt Enable\n" "0,1"
line.long 0x14 "SRS15,SRS15 - Host Control #2 / Auto CMD Error Status"
bitfld.long 0x14 31. "PVE,PVE - Preset Value Enable\n" "0,1"
rbitfld.long 0x14 30. "Reserved_17,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x14 29. "A64B,A64B - 64-bit Addressing\n" "0,1"
bitfld.long 0x14 28. "HV4E,HV4E - Host Version 4.00 Enable\n" "0,1"
newline
bitfld.long 0x14 27. "CMD23E,CMD23E - CMD23 Enable\n" "0,1"
bitfld.long 0x14 26. "ADMA2LM,ADMA2LM - ADMA2 Length Mode\n" "0,1"
rbitfld.long 0x14 25. "Reserved_13,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x14 24. "LVSIEXEC,LVSIEXEC - LVS Identification Execution\n" "0,1"
newline
bitfld.long 0x14 23. "SCS,SCS - Sampling Clock Select\n" "0,1"
bitfld.long 0x14 22. "EXTNG,EXTNG - Execute Tuning\n" "0,1"
bitfld.long 0x14 20.--21. "DSS,DSS - Driver Strength Select\n" "0,1,2,3"
bitfld.long 0x14 19. "V18SE,V18SE - 1.8V Signaling Enable\n" "0,1"
newline
bitfld.long 0x14 16.--18. "UMS,UMS - UHS Mode Select\n" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x14 8.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
rbitfld.long 0x14 7. "CNIACE,CNIACE - Command Not Issued By Auto CMD12 Error\n" "0,1"
rbitfld.long 0x14 6. "Reserved_6,Reserved bitfield added by Magillem" "0,1"
newline
rbitfld.long 0x14 5. "ACRE,ACRE - Auto CMD Response Error\n" "0,1"
rbitfld.long 0x14 4. "ACIE,ACIE - Auto CMD Index Error\n" "0,1"
rbitfld.long 0x14 3. "ACEBE,ACEBE - Auto CMD End Bit Error\n" "0,1"
rbitfld.long 0x14 2. "ACCE,ACCE - Auto CMD CRC Error\n" "0,1"
newline
rbitfld.long 0x14 1. "ACTE,ACTE - Auto CMD Timeout Error\n" "0,1"
rbitfld.long 0x14 0. "ACNE,ACNE - Auto CMD12 Not Executed\n" "0,1"
rgroup.long 0x240++0xF
line.long 0x0 "SRS16,SRS16 - Capabilities #1"
bitfld.long 0x0 30.--31. "SLT,SLT - Slot Type\n" "0,1,2,3"
bitfld.long 0x0 29. "AIS,AIS - Asynchronous Interrupt Support\n" "0,1"
bitfld.long 0x0 28. "A64SV3,A64SV3 - 64-bit System Addressing Support\n" "0,1"
bitfld.long 0x0 27. "A64SV4,A64SV4 - 64-bit System Addressing Support for V4\n" "0,1"
newline
bitfld.long 0x0 26. "VS18,VS18 - Voltage Support 1.8V\n" "0,1"
bitfld.long 0x0 25. "VS30,VS30 - Voltage Support 3.0V\n" "0,1"
bitfld.long 0x0 24. "VS33,VS33 - Voltage Support 3.3V\n" "0,1"
bitfld.long 0x0 23. "SRS,SRS - Suspend / Resume Support\n" "0,1"
newline
bitfld.long 0x0 22. "DMAS,DMAS - SDMA Support\n" "0,1"
bitfld.long 0x0 21. "HSS,HSS - High Speed Support\n" "0,1"
bitfld.long 0x0 20. "ADMA1S,ADMA1S - ADMA1 Support\n" "0,1"
bitfld.long 0x0 19. "ADMA2S,ADMA2S - ADMA2 Support\n" "0,1"
newline
bitfld.long 0x0 18. "EDS8,8EDS - 8-bit Embedded Device Support\n" "0,1"
bitfld.long 0x0 16.--17. "MBL,SRS16.MBL - Max Block Length\n" "0,1,2,3"
hexmask.long.byte 0x0 8.--15. 1. "BCSDCLK,BCSDCLK - Base Clock Frequency for SD Clock\n"
bitfld.long 0x0 7. "TCU,TCU - Timeout Clock Unit\n" "0,1"
newline
bitfld.long 0x0 6. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "TCF,TCF - Timeout Clock Frequency\n"
line.long 0x4 "SRS17,SRS17 - Capabilities #2"
bitfld.long 0x4 31. "LVSH,LVSH - Low Voltage Signaling Host\n" "0,1"
bitfld.long 0x4 29.--30. "Reserved_13,Reserved bitfield added by Magillem" "0,1,2,3"
bitfld.long 0x4 28. "VDD2S,VDD2S - VDD2 Supported\n" "0,1"
bitfld.long 0x4 27. "ADMA3SUP,ADMA3SUP - ADMA3 Supported.\n" "0,1"
newline
bitfld.long 0x4 24.--26. "Reserved_11,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x4 16.--23. 1. "CLKMPR,CLKMPR - Clock Multiplier\n"
bitfld.long 0x4 14.--15. "RTNGM,RTNGM - Re-Tuning Modes\n" "0,1,2,3"
bitfld.long 0x4 13. "UTSM50,UTSM50 - Use Tuning for SDR50\n" "0,1"
newline
bitfld.long 0x4 12. "Reserved_8,Reserved bitfield added by Magillem" "0,1"
hexmask.long.byte 0x4 8.--11. 1. "RTNGCNT,RTNGCNT - Timer Count for Re-Tuning\n"
bitfld.long 0x4 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
bitfld.long 0x4 6. "DRVD,DRVD - 1.8V Line Driver Type D Supported\n" "0,1"
newline
bitfld.long 0x4 5. "DRVC,DRVC - 1.8V Line Driver Type C Supported\n" "0,1"
bitfld.long 0x4 4. "DRVA,DRVA - 1.8V Line Driver Type A Supported\n" "0,1"
bitfld.long 0x4 3. "UHSII,UHSII - UHS-II / UHS-III Supported\n" "0,1"
bitfld.long 0x4 2. "DDR50,DDR50 - DDR50 Supported\n" "0,1"
newline
bitfld.long 0x4 1. "SDR104,SDR104 - SDR104 Supported\n" "0,1"
bitfld.long 0x4 0. "SDR50,SDR50 - SDR50 Supported\n" "0,1"
line.long 0x8 "SRS18,SRS18 - Capabilities #3"
hexmask.long.byte 0x8 24.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
hexmask.long.byte 0x8 16.--23. 1. "MC18,MC18 - Maximum Current for 1.8V\n"
hexmask.long.byte 0x8 8.--15. 1. "MC30,MC30 - Maximum Current for 3.0V\n"
hexmask.long.byte 0x8 0.--7. 1. "MC33,MC33 - Maximum Current for 3.3V\n"
line.long 0xC "SRS19,SRS19 - Capabilities #4"
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0xC 0.--7. 1. "MC18V2,MC18V2 - Maximum Current for 1.8V VDD2\n"
group.long 0x250++0x3
line.long 0x0 "SRS20,SRS20 - Force Event\n"
hexmask.long.byte 0x0 28.--31. 1. "Reserved_18,Reserved bitfield added by Magillem"
bitfld.long 0x0 27. "ERESP_FE,ERESP_FE - Force Response Error Event" "0,1"
bitfld.long 0x0 26. "ETUNE_FE,ETUNE_FE - Force Tuning Error Event" "0,1"
bitfld.long 0x0 25. "EADMA_FE,EADMA_FE - Force ADMA Error Event" "0,1"
newline
bitfld.long 0x0 24. "EAC_FE,EAC_FE - Force Auto CMD Error Event" "0,1"
bitfld.long 0x0 23. "ECL_FE,ECL_FE - Force Current Limit Error Event" "0,1"
bitfld.long 0x0 22. "EDEB_FE,EDEB_FE - Force Data End Bit Error Event" "0,1"
bitfld.long 0x0 21. "EDCRC_FE,EDCRC_FE - Force Data CRC Error Event" "0,1"
newline
bitfld.long 0x0 20. "EDT_FE,EDT_FE - Force Data Timeout Error Event" "0,1"
bitfld.long 0x0 19. "ECI_FE,ECI_FE - Force Command Index Error Event" "0,1"
bitfld.long 0x0 18. "ECEB_FE,ECEB_FE - Force Command End Bit Error Event" "0,1"
bitfld.long 0x0 17. "ECCRC_FE,ECCRC_FE - Force Command CRC Error Event" "0,1"
newline
bitfld.long 0x0 16. "ECT_FE,ECT_FE - Force Command Timeout Error Event" "0,1"
hexmask.long.byte 0x0 8.--15. 1. "Reserved_6,Reserved bitfield added by Magillem"
bitfld.long 0x0 7. "CNIACE_FE,CNIACE_FE - Force Command Not Issued By Auto CMD12 Error Event" "0,1"
rbitfld.long 0x0 5.--6. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x0 4. "ACIE_FE,ACIE_FE - Force Auto CMD Index Error Event" "0,1"
bitfld.long 0x0 3. "ACEBE_FE,ACEBE_FE - Force Auto CMD End Bit Error Event" "0,1"
bitfld.long 0x0 2. "ACCE_FE,ACCE_FE - Force Auto CMD CRC Error Event" "0,1"
bitfld.long 0x0 1. "ACTE_FE,ACTE_FE - Force Auto CMD Timeout Error Event" "0,1"
newline
bitfld.long 0x0 0. "ACNE_FE,ACNE_FE - Force Auto CMD12 Not Executed Event" "0,1"
rgroup.long 0x254++0x3
line.long 0x0 "SRS21,SRS21 - ADMA Error Status"
hexmask.long 0x0 3.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x0 2. "EADMAL,EADMAL - ADMA Length Mismatch Error\n" "0,1"
bitfld.long 0x0 0.--1. "EADMAS,EADMAS - ADMA Error State\n" "0,1,2,3"
group.long 0x258++0x7
line.long 0x0 "SRS22,SRS22 ADMA/SDMA System Address 1"
hexmask.long 0x0 0.--31. 1. "DMASA1,DMASA1 - ADMA System Address\n"
line.long 0x4 "SRS23,SRS23 ADMA/SDMA System Address 2"
hexmask.long 0x4 0.--31. 1. "DMASA2,DMASA2 - ADMA System Address #2\n"
rgroup.long 0x260++0xF
line.long 0x0 "SRS24,SRS24 - Preset Value (Default Speed)\n"
bitfld.long 0x0 30.--31. "SRS24_DSSPV_31_30,DSSPV## - Driver Strength Select - Preset Value\n" "0,1,2,3"
hexmask.long.byte 0x0 26.--29. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x0 16.--25. 1. "SRS24_SDCFSPV_25_16,SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n"
hexmask.long.word 0x0 0.--15. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x4 "SRS25,SRS25 - Preset Value (High Speed and SDR12)\n"
bitfld.long 0x4 30.--31. "SRS25_DSSPV_31_30,DSSPV## - Driver Strength Select - Preset Value\n" "0,1,2,3"
hexmask.long.byte 0x4 26.--29. 1. "Reserved_3,Reserved bitfield added by Magillem"
hexmask.long.word 0x4 16.--25. 1. "SRS25_SDCFSPV_25_16,SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n"
bitfld.long 0x4 14.--15. "SRS25_DSSPV_15_14,DSSPV## - Driver Strength Select - Preset Value\n" "0,1,2,3"
newline
hexmask.long.byte 0x4 10.--13. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x4 0.--9. 1. "SRS25_SDCFSPV_09_00,SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n"
line.long 0x8 "SRS26,SRS26 - Preset Value (SDR25 and SDR50)\n"
bitfld.long 0x8 30.--31. "SRS26_DSSPV_31_30,DSSPV## - Driver Strength Select - Preset Value\n" "0,1,2,3"
hexmask.long.byte 0x8 26.--29. 1. "Reserved_4,Reserved bitfield added by Magillem"
hexmask.long.word 0x8 16.--25. 1. "SRS26_SDCFSPV_25_16,SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n"
bitfld.long 0x8 14.--15. "SRS26_DSSPV_15_14,DSSPV## - Driver Strength Select - Preset Value\n" "0,1,2,3"
newline
bitfld.long 0x8 11.--13. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
bitfld.long 0x8 10. "SRS26_CGSPV_10,CGSPV## - Clock Generator Select - Preset Value\n" "0,1"
hexmask.long.word 0x8 0.--9. 1. "SRS26_SDCFSPV_09_00,SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n"
line.long 0xC "SRS27,SRS27 - Preset Value (SDR104 and DDR50)\n"
bitfld.long 0xC 30.--31. "SRS27_DSSPV_31_30,DSSPV## - Driver Strength Select - Preset Value\n" "0,1,2,3"
hexmask.long.byte 0xC 26.--29. 1. "Reserved_3,Reserved bitfield added by Magillem"
hexmask.long.word 0xC 16.--25. 1. "SRS27_SDCFSPV_25_16,SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n"
bitfld.long 0xC 14.--15. "SRS27_DSSPV_15_14,DSSPV## - Driver Strength Select - Preset Value\n" "0,1,2,3"
newline
hexmask.long.byte 0xC 10.--13. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0xC 0.--9. 1. "SRS27_SDCFSPV_09_00,SDCFSPV## - SDCLK Clock Frequency Select - Preset Value\n"
group.long 0x278++0x7
line.long 0x0 "SRS30,SRS30 ADMA3 ID Address 1"
hexmask.long 0x0 0.--31. 1. "ADMA3ID1,ADMA3 Integrated Descriptor Address #1\n"
line.long 0x4 "SRS31,SRS30 ADMA3 ID Address 2"
hexmask.long 0x4 0.--31. 1. "ADMA3ID2,ADMA3 Integrated Descriptor Address #2\n"
rgroup.long 0x2FC++0x3
line.long 0x0 "CRS63,CRS63 - Host Controller Version/Slot Interrupt Status"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 16.--23. 1. "SVN,SVN - Specification Version Number.\n"
hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "ISES,ISES - Interrupt Signal For Each Slot.\n" "0,1"
rgroup.long 0x400++0x7
line.long 0x0 "CQRS00,CQRS00 - Command Queuing Version"
hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 8.--11. 1. "CQVN1,CQVN1 - eMMC Major Version Number\n"
hexmask.long.byte 0x0 4.--7. 1. "CQVN2,CQVN2 - eMMC Minor Version Number\n"
hexmask.long.byte 0x0 0.--3. 1. "CQVN3,CQVN3 - eMMC Version Suffix\n"
line.long 0x4 "CQRS01,CQRS01 - Command Queuing Capabilities"
hexmask.long.word 0x4 16.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 12.--15. 1. "ITCFMUL,ITCFMUL - Internal Timer Clock Frequency Multiplier (ITCFMUL)\n"
bitfld.long 0x4 10.--11. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.word 0x4 0.--9. 1. "ITCFVAL,ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL)\n"
group.long 0x408++0x27
line.long 0x0 "CQRS02,CQRS02 - Command Queuing Configuration"
hexmask.long.tbyte 0x0 13.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 12. "CQDCE,CQDCE - Direct Command (DCMD) Enable\n" "0,1"
rbitfld.long 0x0 9.--11. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 8. "CQTDS,CQTDS - Task Descriptor\n" "0,1"
newline
hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "CQE,CQE - Command Queuing Enable\n" "0,1"
line.long 0x4 "CQRS03,CQRS03 - Command Queuing Control"
hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
bitfld.long 0x4 8. "CQCAT,CQCAT - Clear All Tasks\n" "0,1"
hexmask.long.byte 0x4 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "CQHLT,CQHLT - Halt CQ\n" "0,1"
line.long 0x8 "CQRS04,CQRS04 - Command Queuing Interrupt Status\n"
hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
eventfld.long 0x8 3. "CQTCL,CQTCL - Task Cleared (TCL)\n" "0,1"
eventfld.long 0x8 2. "CQREDI,CQREDI - Response Error Detected Interrupt (RED)\n" "0,1"
eventfld.long 0x8 1. "CQTCC,CQTCC - Task Complete Interrupt (TCC)\n" "0,1"
newline
eventfld.long 0x8 0. "CQHAC,CQHAC - Halt Complete Interrupt (HAC)\n" "0,1"
line.long 0xC "CQRS05,CQRS05 - Command Queuing Interrupt Status Enable\n"
hexmask.long 0xC 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0xC 3. "CQTCLST,CQTCLST - Task Cleared Status Enable (TCL)\n" "0,1"
bitfld.long 0xC 2. "CQREDST,CQREDST - Response Error Detected Status Enable (RED)\n" "0,1"
bitfld.long 0xC 1. "CQTCCST,CQTCCST - Task Complete Status Enable (TCC)\n" "0,1"
newline
bitfld.long 0xC 0. "CQHACST,CQHACST - Halt Complete Status Enable (HAC)\n" "0,1"
line.long 0x10 "CQRS06,CQRS06 - Command Queuing Interrupt Signal Enable\n"
hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
bitfld.long 0x10 3. "CQTCLSI,CQTCLSI - Task Cleared Signal Enable (TCL)\n" "0,1"
bitfld.long 0x10 2. "CQREDSI,CQREDSI - Response Error Detected Signal Enable (TCC)\n" "0,1"
bitfld.long 0x10 1. "CQTCCSI,CQTCCSI - Task Complete Signal Enable (TCC)\n" "0,1"
newline
bitfld.long 0x10 0. "CQHACSI,CQHACSI - Halt Complete Signal Enable (HAC)\n" "0,1"
line.long 0x14 "CQRS07,CQRS07 - Interrupt Coalescing\n"
bitfld.long 0x14 31. "CQICED,CQICED - Interrupt Coalescing Enable/Disable\n" "0,1"
hexmask.long.word 0x14 21.--30. 1. "Reserved_6,Reserved bitfield added by Magillem"
rbitfld.long 0x14 20. "CQICSB,CQICSB - Interrupt Coalescing Status Bit (ICSB)\n" "0,1"
rbitfld.long 0x14 17.--19. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 16. "CQICCTR,CQICCTR - Counter and Timer Reset(ICCTR)\n" "0,1"
bitfld.long 0x14 15. "CQICCTHWEN,CQICCTHWEN - Interrupt Coalescing Counter Threshold Write Enable (ICCTHWEN)\n" "0,1"
rbitfld.long 0x14 13.--14. "Reserved_3,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x14 8.--12. 1. "CQICCTH,CQICCTH - Interrupt Coalescing Counter Threshold (ICCTH)\n"
newline
bitfld.long 0x14 7. "CQICTOVALEN,CQICTOVALEN - Interrupt Coalescing Timeout Value Write Enable (ICTOVALWEN)\n" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "CQICTOVAL,CQICTOVAL - Interrupt Coalescing Timeout Value (ICTOVAL)\n"
line.long 0x18 "CQRS08,CQRS08 - Command Queuing Task Descriptor List Base Address"
hexmask.long 0x18 0.--31. 1. "CQTDLBA,CQTDLBA - Task Descriptor List Base Address (lower)\n"
line.long 0x1C "CQRS09,CQRS09 - Command Queuing Task Descriptor List Base Address Upper 32 Bits"
hexmask.long 0x1C 0.--31. 1. "CQTDLBAU,CQTDLBAU - Task Descriptor List Base Address (upper)\n"
line.long 0x20 "CQRS10,CQRS10 - Command Queuing Task Doorbell\n"
bitfld.long 0x20 31. "CQTD31,CQTD31 - Command Queuing Task Doorbell #31" "0,1"
bitfld.long 0x20 30. "CQTD30,CQTD30 - Command Queuing Task Doorbell #30" "0,1"
bitfld.long 0x20 29. "CQTD29,CQTD29 - Command Queuing Task Doorbell #29" "0,1"
bitfld.long 0x20 28. "CQTD28,CQTD28 - Command Queuing Task Doorbell #28" "0,1"
newline
bitfld.long 0x20 27. "CQTD27,CQTD27 - Command Queuing Task Doorbell #27" "0,1"
bitfld.long 0x20 26. "CQTD26,CQTD26 - Command Queuing Task Doorbell #26" "0,1"
bitfld.long 0x20 25. "CQTD25,CQTD25 - Command Queuing Task Doorbell #25" "0,1"
bitfld.long 0x20 24. "CQTD24,CQTD24 - Command Queuing Task Doorbell #24" "0,1"
newline
bitfld.long 0x20 23. "CQTD23,CQTD23 - Command Queuing Task Doorbell #23" "0,1"
bitfld.long 0x20 22. "CQTD22,CQTD22 - Command Queuing Task Doorbell #22" "0,1"
bitfld.long 0x20 21. "CQTD21,CQTD21 - Command Queuing Task Doorbell #21" "0,1"
bitfld.long 0x20 20. "CQTD20,CQTD20 - Command Queuing Task Doorbell #20" "0,1"
newline
bitfld.long 0x20 19. "CQTD19,CQTD19 - Command Queuing Task Doorbell #19" "0,1"
bitfld.long 0x20 18. "CQTD18,CQTD18 - Command Queuing Task Doorbell #18" "0,1"
bitfld.long 0x20 17. "CQTD17,CQTD17 - Command Queuing Task Doorbell #17" "0,1"
bitfld.long 0x20 16. "CQTD16,CQTD16 - Command Queuing Task Doorbell #16" "0,1"
newline
bitfld.long 0x20 15. "CQTD15,CQTD15 - Command Queuing Task Doorbell #15" "0,1"
bitfld.long 0x20 14. "CQTD14,CQTD14 - Command Queuing Task Doorbell #14" "0,1"
bitfld.long 0x20 13. "CQTD13,CQTD13 - Command Queuing Task Doorbell #13" "0,1"
bitfld.long 0x20 12. "CQTD12,CQTD12 - Command Queuing Task Doorbell #12" "0,1"
newline
bitfld.long 0x20 11. "CQTD11,CQTD11 - Command Queuing Task Doorbell #11" "0,1"
bitfld.long 0x20 10. "CQTD10,CQTD10 - Command Queuing Task Doorbell #10" "0,1"
bitfld.long 0x20 9. "CQTD09,CQTD09 - Command Queuing Task Doorbell #09" "0,1"
bitfld.long 0x20 8. "CQTD08,CQTD08 - Command Queuing Task Doorbell #08" "0,1"
newline
bitfld.long 0x20 7. "CQTD07,CQTD07 - Command Queuing Task Doorbell #07" "0,1"
bitfld.long 0x20 6. "CQTD06,CQTD06 - Command Queuing Task Doorbell #06" "0,1"
bitfld.long 0x20 5. "CQTD05,CQTD05 - Command Queuing Task Doorbell #05" "0,1"
bitfld.long 0x20 4. "CQTD04,CQTD04 - Command Queuing Task Doorbell #04" "0,1"
newline
bitfld.long 0x20 3. "CQTD03,CQTD03 - Command Queuing Task Doorbell #03" "0,1"
bitfld.long 0x20 2. "CQTD02,CQTD02 - Command Queuing Task Doorbell #02" "0,1"
bitfld.long 0x20 1. "CQTD01,CQTD01 - Command Queuing Task Doorbell #01" "0,1"
bitfld.long 0x20 0. "CQTD00,CQTD00 - Command Queuing Task Doorbell #00" "0,1"
line.long 0x24 "CQRS11,CQRS11 - Task Complete Notification\n"
eventfld.long 0x24 31. "CQTCN31,CQTCN31 - Task Completion Notification #31" "0,1"
eventfld.long 0x24 30. "CQTCN30,CQTCN30 - Task Completion Notification #30" "0,1"
eventfld.long 0x24 29. "CQTCN29,CQTCN29 - Task Completion Notification #29" "0,1"
eventfld.long 0x24 28. "CQTCN28,CQTCN28 - Task Completion Notification #28" "0,1"
newline
eventfld.long 0x24 27. "CQTCN27,CQTCN27 - Task Completion Notification #27" "0,1"
eventfld.long 0x24 26. "CQTCN26,CQTCN26 - Task Completion Notification #26" "0,1"
eventfld.long 0x24 25. "CQTCN25,CQTCN25 - Task Completion Notification #25" "0,1"
eventfld.long 0x24 24. "CQTCN24,CQTCN24 - Task Completion Notification #24" "0,1"
newline
eventfld.long 0x24 23. "CQTCN23,CQTCN23 - Task Completion Notification #23" "0,1"
eventfld.long 0x24 22. "CQTCN22,CQTCN22 - Task Completion Notification #22" "0,1"
eventfld.long 0x24 21. "CQTCN21,CQTCN21 - Task Completion Notification #21" "0,1"
eventfld.long 0x24 20. "CQTCN20,CQTCN20 - Task Completion Notification #20" "0,1"
newline
eventfld.long 0x24 19. "CQTCN19,CQTCN19 - Task Completion Notification #19" "0,1"
eventfld.long 0x24 18. "CQTCN18,CQTCN18 - Task Completion Notification #18" "0,1"
eventfld.long 0x24 17. "CQTCN17,CQTCN17 - Task Completion Notification #17" "0,1"
eventfld.long 0x24 16. "CQTCN16,CQTCN16 - Task Completion Notification #16" "0,1"
newline
eventfld.long 0x24 15. "CQTCN15,CQTCN15 - Task Completion Notification #15" "0,1"
eventfld.long 0x24 14. "CQTCN14,CQTCN14 - Task Completion Notification #14" "0,1"
eventfld.long 0x24 13. "CQTCN13,CQTCN13 - Task Completion Notification #13" "0,1"
eventfld.long 0x24 12. "CQTCN12,CQTCN12 - Task Completion Notification #12" "0,1"
newline
eventfld.long 0x24 11. "CQTCN11,CQTCN11 - Task Completion Notification #11" "0,1"
eventfld.long 0x24 10. "CQTCN10,CQTCN10 - Task Completion Notification #10" "0,1"
eventfld.long 0x24 9. "CQTCN09,CQTCN09 - Task Completion Notification #09" "0,1"
eventfld.long 0x24 8. "CQTCN08,CQTCN08 - Task Completion Notification #08" "0,1"
newline
eventfld.long 0x24 7. "CQTCN07,CQTCN07 - Task Completion Notification #07" "0,1"
eventfld.long 0x24 6. "CQTCN06,CQTCN06 - Task Completion Notification #06" "0,1"
eventfld.long 0x24 5. "CQTCN05,CQTCN05 - Task Completion Notification #05" "0,1"
eventfld.long 0x24 4. "CQTCN04,CQTCN04 - Task Completion Notification #04" "0,1"
newline
eventfld.long 0x24 3. "CQTCN03,CQTCN03 - Task Completion Notification #03" "0,1"
eventfld.long 0x24 2. "CQTCN02,CQTCN02 - Task Completion Notification #02" "0,1"
eventfld.long 0x24 1. "CQTCN01,CQTCN01 - Task Completion Notification #01" "0,1"
eventfld.long 0x24 0. "CQTCN00,CQTCN00 - Task Completion Notification #00" "0,1"
rgroup.long 0x430++0x7
line.long 0x0 "CQRS12,CQRS12 - Device Queue Status"
hexmask.long 0x0 0.--31. 1. "CQDQS,CQDQS - Device Queue Status\n"
line.long 0x4 "CQRS13,CQRS13 - Device Pending Tasks\n"
bitfld.long 0x4 31. "CQDPT31,CQDPT31 - Device Pending Tasks #31" "0,1"
bitfld.long 0x4 30. "CQDPT30,CQDPT30 - Device Pending Tasks #30" "0,1"
bitfld.long 0x4 29. "CQDPT29,CQDPT29 - Device Pending Tasks #29" "0,1"
bitfld.long 0x4 28. "CQDPT28,CQDPT28 - Device Pending Tasks #28" "0,1"
newline
bitfld.long 0x4 27. "CQDPT27,CQDPT27 - Device Pending Tasks #27" "0,1"
bitfld.long 0x4 26. "CQDPT26,CQDPT26 - Device Pending Tasks #26" "0,1"
bitfld.long 0x4 25. "CQDPT25,CQDPT25 - Device Pending Tasks #25" "0,1"
bitfld.long 0x4 24. "CQDPT24,CQDPT24 - Device Pending Tasks #24" "0,1"
newline
bitfld.long 0x4 23. "CQDPT23,CQDPT23 - Device Pending Tasks #23" "0,1"
bitfld.long 0x4 22. "CQDPT22,CQDPT22 - Device Pending Tasks #22" "0,1"
bitfld.long 0x4 21. "CQDPT21,CQDPT21 - Device Pending Tasks #21" "0,1"
bitfld.long 0x4 20. "CQDPT20,CQDPT20 - Device Pending Tasks #20" "0,1"
newline
bitfld.long 0x4 19. "CQDPT19,CQDPT19 - Device Pending Tasks #19" "0,1"
bitfld.long 0x4 18. "CQDPT18,CQDPT18 - Device Pending Tasks #18" "0,1"
bitfld.long 0x4 17. "CQDPT17,CQDPT17 - Device Pending Tasks #17" "0,1"
bitfld.long 0x4 16. "CQDPT16,CQDPT16 - Device Pending Tasks #16" "0,1"
newline
bitfld.long 0x4 15. "CQDPT15,CQDPT15 - Device Pending Tasks #15" "0,1"
bitfld.long 0x4 14. "CQDPT14,CQDPT14 - Device Pending Tasks #14" "0,1"
bitfld.long 0x4 13. "CQDPT13,CQDPT13 - Device Pending Tasks #13" "0,1"
bitfld.long 0x4 12. "CQDPT12,CQDPT12 - Device Pending Tasks #12" "0,1"
newline
bitfld.long 0x4 11. "CQDPT11,CQDPT11 - Device Pending Tasks #11" "0,1"
bitfld.long 0x4 10. "CQDPT10,CQDPT10 - Device Pending Tasks #10" "0,1"
bitfld.long 0x4 9. "CQDPT09,CQDPT09 - Device Pending Tasks #09" "0,1"
bitfld.long 0x4 8. "CQDPT08,CQDPT08 - Device Pending Tasks #08" "0,1"
newline
bitfld.long 0x4 7. "CQDPT07,CQDPT07 - Device Pending Tasks #07" "0,1"
bitfld.long 0x4 6. "CQDPT06,CQDPT06 - Device Pending Tasks #06" "0,1"
bitfld.long 0x4 5. "CQDPT05,CQDPT05 - Device Pending Tasks #05" "0,1"
bitfld.long 0x4 4. "CQDPT04,CQDPT04 - Device Pending Tasks #04" "0,1"
newline
bitfld.long 0x4 3. "CQDPT03,CQDPT03 - Device Pending Tasks #03" "0,1"
bitfld.long 0x4 2. "CQDPT02,CQDPT02 - Device Pending Tasks #02" "0,1"
bitfld.long 0x4 1. "CQDPT01,CQDPT01 - Device Pending Tasks #01" "0,1"
bitfld.long 0x4 0. "CQDPT00,CQDPT00 - Device Pending Tasks #00" "0,1"
group.long 0x438++0x3
line.long 0x0 "CQRS14,CQRS14 - Task Clear\n"
bitfld.long 0x0 31. "CQTC31,CQTC31 - Command Queuing Task Clear #31" "0,1"
bitfld.long 0x0 30. "CQTC30,CQTC30 - Command Queuing Task Clear #30" "0,1"
bitfld.long 0x0 29. "CQTC29,CQTC29 - Command Queuing Task Clear #29" "0,1"
bitfld.long 0x0 28. "CQTC28,CQTC28 - Command Queuing Task Clear #28" "0,1"
newline
bitfld.long 0x0 27. "CQTC27,CQTC27 - Command Queuing Task Clear #27" "0,1"
bitfld.long 0x0 26. "CQTC26,CQTC26 - Command Queuing Task Clear #26" "0,1"
bitfld.long 0x0 25. "CQTC25,CQTC25 - Command Queuing Task Clear #25" "0,1"
bitfld.long 0x0 24. "CQTC24,CQTC24 - Command Queuing Task Clear #24" "0,1"
newline
bitfld.long 0x0 23. "CQTC23,CQTC23 - Command Queuing Task Clear #23" "0,1"
bitfld.long 0x0 22. "CQTC22,CQTC22 - Command Queuing Task Clear #22" "0,1"
bitfld.long 0x0 21. "CQTC21,CQTC21 - Command Queuing Task Clear #21" "0,1"
bitfld.long 0x0 20. "CQTC20,CQTC20 - Command Queuing Task Clear #20" "0,1"
newline
bitfld.long 0x0 19. "CQTC19,CQTC19 - Command Queuing Task Clear #19" "0,1"
bitfld.long 0x0 18. "CQTC18,CQTC18 - Command Queuing Task Clear #18" "0,1"
bitfld.long 0x0 17. "CQTC17,CQTC17 - Command Queuing Task Clear #17" "0,1"
bitfld.long 0x0 16. "CQTC16,CQTC16 - Command Queuing Task Clear #16" "0,1"
newline
bitfld.long 0x0 15. "CQTC15,CQTC15 - Command Queuing Task Clear #15" "0,1"
bitfld.long 0x0 14. "CQTC14,CQTC14 - Command Queuing Task Clear #14" "0,1"
bitfld.long 0x0 13. "CQTC13,CQTC13 - Command Queuing Task Clear #13" "0,1"
bitfld.long 0x0 12. "CQTC12,CQTC12 - Command Queuing Task Clear #12" "0,1"
newline
bitfld.long 0x0 11. "CQTC11,CQTC11 - Command Queuing Task Clear #11" "0,1"
bitfld.long 0x0 10. "CQTC10,CQTC10 - Command Queuing Task Clear #10" "0,1"
bitfld.long 0x0 9. "CQTC09,CQTC09 - Command Queuing Task Clear #09" "0,1"
bitfld.long 0x0 8. "CQTC08,CQTC08 - Command Queuing Task Clear #08" "0,1"
newline
bitfld.long 0x0 7. "CQTC07,CQTC07 - Command Queuing Task Clear #07" "0,1"
bitfld.long 0x0 6. "CQTC06,CQTC06 - Command Queuing Task Clear #06" "0,1"
bitfld.long 0x0 5. "CQTC05,CQTC05 - Command Queuing Task Clear #05" "0,1"
bitfld.long 0x0 4. "CQTC04,CQTC04 - Command Queuing Task Clear #04" "0,1"
newline
bitfld.long 0x0 3. "CQTC03,CQTC03 - Command Queuing Task Clear #03" "0,1"
bitfld.long 0x0 2. "CQTC02,CQTC02 - Command Queuing Task Clear #02" "0,1"
bitfld.long 0x0 1. "CQTC01,CQTC01 - Command Queuing Task Clear #01" "0,1"
bitfld.long 0x0 0. "CQTC00,CQTC00 - Command Queuing Task Clear #00" "0,1"
group.long 0x440++0x7
line.long 0x0 "CQRS16,CQRS16 - Send Status Configuration 1"
hexmask.long.word 0x0 20.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 16.--19. 1. "CQSSCBC,CQSSCBC - Send Status Command Block Counter (CBC)\n"
hexmask.long.word 0x0 0.--15. 1. "CQSSCIT,CQSSCIT - Send Status Command Idle Timer (CIT)\n"
line.long 0x4 "CQRS17,CQRS17 - Send Status Configuration 2"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.word 0x4 0.--15. 1. "CQSQSR,CQSQSR - Send Queue Status RCA\n"
rgroup.long 0x448++0x3
line.long 0x0 "CQRS18,CQRS18 - Command Response for Direct-Command Task"
hexmask.long 0x0 0.--31. 1. "CQDCLR,CQDCLR - Direct Command Last Response\n"
group.long 0x450++0x3
line.long 0x0 "CQRS20,CQRS20 - Response Mode Error Mask"
hexmask.long 0x0 0.--31. 1. "CQRMEM,CQRMEM - Response Mode Error Mask\n"
rgroup.long 0x454++0xB
line.long 0x0 "CQRS21,CQRS21 - Task Error Information"
bitfld.long 0x0 31. "CQDTEFV,CQDTEFV - Data Transfer Error Fields Valid\n" "0,1"
bitfld.long 0x0 29.--30. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x0 24.--28. 1. "CQDTETID,CQDTETID - Data Transfer Error Task ID\n"
bitfld.long 0x0 22.--23. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--21. 1. "CQDTECI,CQDTECI - Data Transfer Error Command Index\n"
bitfld.long 0x0 15. "CQRMEFV,CQRMEFV - Response Mode Error Fields Valid\n" "0,1"
bitfld.long 0x0 13.--14. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x0 8.--12. 1. "CQRMETID,CQRMETID - Response Mode Error Task ID\n"
newline
bitfld.long 0x0 6.--7. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "CQRMECI,CQRMECI - Response Mode Error Command Index\n"
line.long 0x4 "CQRS22,CQRS22 - Command Response Index"
hexmask.long 0x4 6.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x4 0.--5. 1. "CQLCRI,CQLCRI - Last Command Response Index\n"
line.long 0x8 "CQRS23,CQRS23 - Command Response Argument"
hexmask.long 0x8 0.--31. 1. "CQLCRA,CQLCRA - Last Command Response Argument\n"
tree.end
tree "SMMU (System Memory Management Unit)"
base ad:0x16000000
rgroup.long 0x0++0xF
line.long 0x0 "SMMU_IDR0,SMMU_IDR0"
bitfld.long 0x0 29.--31. "Reserved_31_29,Reserved_31_29" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 27.--28. "ST_LEVEL,ST_LEVEL" "0,1,2,3"
bitfld.long 0x0 26. "TERM_MODEL,TERM_MODEL" "0,1"
newline
bitfld.long 0x0 24.--25. "STALL_MODEL,STALL_MODEL" "0,1,2,3"
bitfld.long 0x0 23. "Reserved_23_23,Reserved_23_23" "0,1"
bitfld.long 0x0 21.--22. "TTENDIAN,TTENDIAN" "0,1,2,3"
newline
bitfld.long 0x0 20. "VATOS,VATOS" "0,1"
bitfld.long 0x0 19. "CD2L,CD2L" "0,1"
bitfld.long 0x0 18. "VMID16,VMID16" "0,1"
newline
bitfld.long 0x0 17. "VMW,VMW" "0,1"
bitfld.long 0x0 16. "PRI,PRI" "0,1"
bitfld.long 0x0 15. "ATOS,ATOS" "0,1"
newline
bitfld.long 0x0 14. "SEV,SEV" "0,1"
bitfld.long 0x0 13. "MSI,MSI" "0,1"
bitfld.long 0x0 12. "ASID16,ASID16" "0,1"
newline
bitfld.long 0x0 11. "NS1ATS,NS1ATS" "0,1"
bitfld.long 0x0 10. "ATS,ATS" "0,1"
bitfld.long 0x0 9. "HYP,HYP" "0,1"
newline
bitfld.long 0x0 8. "DORMHINT,DORMHINT" "0,1"
bitfld.long 0x0 6.--7. "HTTU,HTTU" "0,1,2,3"
bitfld.long 0x0 5. "BTM,BTM" "0,1"
newline
bitfld.long 0x0 4. "COHACC,COHACC" "0,1"
bitfld.long 0x0 2.--3. "TTF,TTF" "0,1,2,3"
bitfld.long 0x0 1. "S1P,S1P" "0,1"
newline
bitfld.long 0x0 0. "S2P,S2P" "0,1"
line.long 0x4 "SMMU_IDR1,SMMU_IDR1"
bitfld.long 0x4 31. "Reserved_31_31,Reserved_31_31" "0,1"
bitfld.long 0x4 30. "TABLES_PRESET,TABLES_PRESET" "0,1"
bitfld.long 0x4 29. "QUEUES_PRESET,QUEUES_PRESET" "0,1"
newline
bitfld.long 0x4 28. "REL,REL" "0,1"
bitfld.long 0x4 27. "ATTR_TYPES_OVR,ATTR_TYPES_OVR" "0,1"
bitfld.long 0x4 26. "ATTR_PERMS_OVR,ATTR_PERMS_OVR" "0,1"
newline
hexmask.long.byte 0x4 21.--25. 1. "CMDQS,CMDQS"
hexmask.long.byte 0x4 16.--20. 1. "EVENTQS,EVENTQS"
hexmask.long.byte 0x4 11.--15. 1. "PRIQS,PRIQS"
newline
hexmask.long.byte 0x4 6.--10. 1. "SSIDSIZE,SSIDSIZE"
hexmask.long.byte 0x4 0.--5. 1. "SIDSIZE,SIDSIZE"
line.long 0x8 "SMMU_IDR2,SMMU_IDR2"
hexmask.long.tbyte 0x8 10.--31. 1. "Reserved_31_10,Reserved_31_10"
hexmask.long.word 0x8 0.--9. 1. "BA_VATOS,BA_VATOS"
line.long 0xC "SMMU_IDR3,SMMU_IDR3"
hexmask.long 0xC 6.--31. 1. "Reserved_31_6,Reserved_31_6"
bitfld.long 0xC 5. "PPS,PPS" "0,1"
bitfld.long 0xC 4. "XNX,XNX" "0,1"
newline
bitfld.long 0xC 3. "PBHA,PBHA" "0,1"
bitfld.long 0xC 2. "HAD,HAD" "0,1"
bitfld.long 0xC 0.--1. "Reserved_1_0,Reserved_1_0" "0,1,2,3"
rgroup.long 0x14++0xB
line.long 0x0 "SMMU_IDR5,SMMU_IDR5"
hexmask.long.word 0x0 16.--31. 1. "STALL_MAX,STALL_MAX"
hexmask.long.byte 0x0 12.--15. 1. "Reserved_15_12,Reserved_15_12"
bitfld.long 0x0 10.--11. "VAX,VAX" "0,1,2,3"
newline
bitfld.long 0x0 7.--9. "Reserved_9_7,Reserved_9_7" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 6. "GRAN64K,GRAN64K" "0,1"
bitfld.long 0x0 5. "GRAN16K,GRAN16K" "0,1"
newline
bitfld.long 0x0 4. "GRAN4K,GRAN4K" "0,1"
bitfld.long 0x0 3. "Reserved_3_3,Reserved_3_3" "0,1"
bitfld.long 0x0 0.--2. "OAS,OAS" "0,1,2,3,4,5,6,7"
line.long 0x4 "SMMU_IIDR,SMMU_IIDR"
hexmask.long.word 0x4 20.--31. 1. "ProductID,ProductID"
hexmask.long.byte 0x4 16.--19. 1. "Variant,Variant"
hexmask.long.byte 0x4 12.--15. 1. "Revision,Revision"
newline
hexmask.long.word 0x4 0.--11. 1. "Implementer,Implementer"
line.long 0x8 "SMMU_AIDR,SMMU_AIDR"
hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x8 4.--7. 1. "ArchMajorRev,ArchMajorRev"
hexmask.long.byte 0x8 0.--3. 1. "ArchMinorRev,ArchMinorRev"
group.long 0x20++0x3
line.long 0x0 "SMMU_CR0,SMMU_CR0"
hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved_31_9"
bitfld.long 0x0 6.--8. "VMW,VMW" "0,1,2,3,4,5,6,7"
rbitfld.long 0x0 5. "Reserved_5_5,Reserved_5_5" "0,1"
newline
bitfld.long 0x0 4. "ATSCHK,ATSCHK" "0,1"
bitfld.long 0x0 3. "CMDQEN,CMDQEN" "0,1"
bitfld.long 0x0 2. "EVENTQEN,EVENTQEN" "0,1"
newline
bitfld.long 0x0 1. "PRIQEN,PRIQEN" "0,1"
bitfld.long 0x0 0. "SMMUEN,SMMUEN" "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "SMMU_CR0ACK,SMMU_CR0ACK"
hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_31_9,Reserved_31_9"
bitfld.long 0x0 6.--8. "VMW,VMW" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 5. "Reserved_5_5,Reserved_5_5" "0,1"
newline
bitfld.long 0x0 4. "ATSCHK,ATSCHK" "0,1"
bitfld.long 0x0 3. "CMDQEN,CMDQEN" "0,1"
bitfld.long 0x0 2. "EVENTQEN,EVENTQEN" "0,1"
newline
bitfld.long 0x0 1. "PRIQEN,PRIQEN" "0,1"
bitfld.long 0x0 0. "SMMUEN,SMMUEN" "0,1"
group.long 0x28++0x7
line.long 0x0 "SMMU_CR1,SMMU_CR1"
hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_31_12,Reserved_31_12"
bitfld.long 0x0 10.--11. "TABLE_SH,TABLE_SH" "0,1,2,3"
bitfld.long 0x0 8.--9. "TABLE_OC,TABLE_OC" "0,1,2,3"
newline
bitfld.long 0x0 6.--7. "TABLE_IC,TABLE_IC" "0,1,2,3"
bitfld.long 0x0 4.--5. "QUEUE_SH,QUEUE_SH" "0,1,2,3"
bitfld.long 0x0 2.--3. "QUEUE_OC,QUEUE_OC" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "QUEUE_IC,QUEUE_IC" "0,1,2,3"
line.long 0x4 "SMMU_CR2,SMMU_CR2"
hexmask.long 0x4 3.--31. 1. "Reserved_31_3,Reserved_31_3"
bitfld.long 0x4 2. "PTM,PTM" "0,1"
bitfld.long 0x4 1. "RECINVSID,RECINVSID" "0,1"
newline
bitfld.long 0x4 0. "E2H,E2H" "0,1"
group.long 0x44++0x3
line.long 0x0 "SMMU_GBPA,SMMU_GBPA"
bitfld.long 0x0 31. "Update,Update" "0,1"
hexmask.long.word 0x0 21.--30. 1. "Reserved_30_21,Reserved_30_21"
bitfld.long 0x0 20. "ABORT,ABORT" "0,1"
newline
bitfld.long 0x0 18.--19. "INSTCFG,INSTCFG" "0,1,2,3"
bitfld.long 0x0 16.--17. "PRIVCFG,PRIVCFG" "0,1,2,3"
rbitfld.long 0x0 14.--15. "Reserved_15_14,Reserved_15_14" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "SHCFG,SHCFG" "0,1,2,3"
hexmask.long.byte 0x0 8.--11. 1. "ALLOCCFG,ALLOCCFG"
rbitfld.long 0x0 5.--7. "Reserved_7_5,Reserved_7_5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "MTCFG,MTCFG" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "MemAttr,MemAttr"
group.long 0x50++0x3
line.long 0x0 "SMMU_IRQ_CTRL,SMMU_IRQ_CTRL"
hexmask.long 0x0 3.--31. 1. "Reserved_31_3,Reserved_31_3"
bitfld.long 0x0 2. "EVENTQ_IRQEN,EVENTQ_IRQEN" "0,1"
bitfld.long 0x0 1. "PRIQ_IRQEN,PRIQ_IRQEN" "0,1"
newline
bitfld.long 0x0 0. "GERROR_IRQEN,GERROR_IRQEN" "0,1"
rgroup.long 0x54++0x3
line.long 0x0 "SMMU_IRQ_CTRLACK,SMMU_IRQ_CTRLACK"
hexmask.long 0x0 3.--31. 1. "Reserved_31_3,Reserved_31_3"
bitfld.long 0x0 2. "EVENTQ_IRQEN,EVENTQ_IRQEN" "0,1"
bitfld.long 0x0 1. "PRIQ_IRQEN,PRIQ_IRQEN" "0,1"
newline
bitfld.long 0x0 0. "GERROR_IRQEN,GERROR_IRQEN" "0,1"
rgroup.long 0x60++0x3
line.long 0x0 "SMMU_GERROR,SMMU_GERROR"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved_31_8"
bitfld.long 0x0 7. "MSI_GERROR_ABT_ERR,MSI_GERROR_ABT_ERR" "0,1"
bitfld.long 0x0 6. "MSI_PRIQ_ABT_ERR,MSI_PRIQ_ABT_ERR" "0,1"
newline
bitfld.long 0x0 5. "MSI_EVENTQ_ABT_ERR,MSI_EVENTQ_ABT_ERR" "0,1"
bitfld.long 0x0 4. "MSI_CMDQ_ABT_ERR,MSI_CMDQ_ABT_ERR" "0,1"
bitfld.long 0x0 3. "PRIQ_ABT_ERR,PRIQ_ABT_ERR" "0,1"
newline
bitfld.long 0x0 2. "EVENTQ_ABT_ERR,EVENTQ_ABT_ERR" "0,1"
bitfld.long 0x0 1. "Reserved_1_1,Reserved_1_1" "0,1"
bitfld.long 0x0 0. "CMDQ_ERR,CMDQ_ERR" "0,1"
group.long 0x64++0x13
line.long 0x0 "SMMU_GERRORN,SMMU_GERRORN"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved_31_8"
bitfld.long 0x0 7. "MSI_GERROR_ABT_ERR,MSI_GERROR_ABT_ERR" "0,1"
bitfld.long 0x0 6. "MSI_PRIQ_ABT_ERR,MSI_PRIQ_ABT_ERR" "0,1"
newline
bitfld.long 0x0 5. "MSI_EVENTQ_ABT_ERR,MSI_EVENTQ_ABT_ERR" "0,1"
bitfld.long 0x0 4. "MSI_CMDQ_ABT_ERR,MSI_CMDQ_ABT_ERR" "0,1"
bitfld.long 0x0 3. "PRIQ_ABT_ERR,PRIQ_ABT_ERR" "0,1"
newline
bitfld.long 0x0 2. "EVENTQ_ABT_ERR,EVENTQ_ABT_ERR" "0,1"
rbitfld.long 0x0 1. "Reserved_1_1,Reserved_1_1" "0,1"
bitfld.long 0x0 0. "CMDQ_ERR,CMDQ_ERR" "0,1"
line.long 0x4 "SMMU_GERROR_IRQ_CFG0_LO,SMMU_GERROR_IRQ_CFG0_LO"
hexmask.long 0x4 2.--31. 1. "ADDR,ADDR"
rbitfld.long 0x4 0.--1. "Reserved_1_0,Reserved_1_0" "0,1,2,3"
line.long 0x8 "SMMU_GERROR_IRQ_CFG0_HI,SMMU_GERROR_IRQ_CFG0_HI"
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved_31_16"
hexmask.long.word 0x8 0.--15. 1. "ADDR,ADDR"
line.long 0xC "SMMU_GERROR_IRQ_CFG1,SMMU_GERROR_IRQ_CFG1"
hexmask.long 0xC 0.--31. 1. "DATA,DATA"
line.long 0x10 "SMMU_GERROR_IRQ_CFG2,SMMU_GERROR_IRQ_CFG2"
hexmask.long 0x10 6.--31. 1. "Reserved_31_6,Reserved_31_6"
bitfld.long 0x10 4.--5. "SH,SH" "0,1,2,3"
hexmask.long.byte 0x10 0.--3. 1. "MemAttr,MemAttr"
group.long 0x80++0xB
line.long 0x0 "SMMU_STRTAB_BASE_LO,SMMU_STRTAB_BASE_LO"
hexmask.long 0x0 6.--31. 1. "ADDR,ADDR"
hexmask.long.byte 0x0 0.--5. 1. "Reserved_5_0,Reserved_5_0"
line.long 0x4 "SMMU_STRTAB_BASE_HI,SMMU_STRTAB_BASE_HI"
rbitfld.long 0x4 31. "Reserved_31_31,Reserved_31_31" "0,1"
bitfld.long 0x4 30. "RA,RA" "0,1"
hexmask.long.word 0x4 16.--29. 1. "Reserved_29_16,Reserved_29_16"
newline
hexmask.long.word 0x4 0.--15. 1. "ADDR,ADDR"
line.long 0x8 "SMMU_STRTAB_BASE_CFG,SMMU_STRTAB_BASE_CFG"
hexmask.long.word 0x8 18.--31. 1. "Reserved_31_18,Reserved_31_18"
bitfld.long 0x8 16.--17. "FMT,FMT" "0,1,2,3"
hexmask.long.byte 0x8 11.--15. 1. "Reserved_15_11,Reserved_15_11"
newline
hexmask.long.byte 0x8 6.--10. 1. "SPLIT,SPLIT"
hexmask.long.byte 0x8 0.--5. 1. "LOG2SIZE,LOG2SIZE"
group.long 0x90++0x17
line.long 0x0 "SMMU_CMDQ_BASE_LO,SMMU_CMDQ_BASE_LO"
hexmask.long 0x0 5.--31. 1. "ADDR,ADDR"
hexmask.long.byte 0x0 0.--4. 1. "LOG2SIZE,LOG2SIZE"
line.long 0x4 "SMMU_CMDQ_BASE_HI,SMMU_CMDQ_BASE_HI"
rbitfld.long 0x4 31. "Reserved_31_31,Reserved_31_31" "0,1"
bitfld.long 0x4 30. "RA,RA" "0,1"
hexmask.long.word 0x4 16.--29. 1. "Reserved_29_16,Reserved_29_16"
newline
hexmask.long.word 0x4 0.--15. 1. "ADDR,ADDR"
line.long 0x8 "SMMU_CMDQ_PROD,SMMU_CMDQ_PROD"
hexmask.long.word 0x8 20.--31. 1. "Reserved_31_20,Reserved_31_20"
hexmask.long.tbyte 0x8 0.--19. 1. "WR,WR"
line.long 0xC "SMMU_CMDQ_CONS,SMMU_CMDQ_CONS"
rbitfld.long 0xC 31. "Reserved_31_31,Reserved_31_31" "0,1"
hexmask.long.byte 0xC 24.--30. 1. "ERR,ERR"
hexmask.long.byte 0xC 20.--23. 1. "Reserved_23_20,Reserved_23_20"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "RD,RD"
line.long 0x10 "SMMU_EVENTQ_BASE_LO,SMMU_EVENTQ_BASE_LO"
hexmask.long 0x10 5.--31. 1. "ADDR,ADDR"
hexmask.long.byte 0x10 0.--4. 1. "LOG2SIZE,LOG2SIZE"
line.long 0x14 "SMMU_EVENTQ_BASE_HI,SMMU_EVENTQ_BASE_HI"
rbitfld.long 0x14 31. "Reserved_31_31,Reserved_31_31" "0,1"
bitfld.long 0x14 30. "WA,WA" "0,1"
hexmask.long.word 0x14 16.--29. 1. "Reserved_29_16,Reserved_29_16"
newline
hexmask.long.word 0x14 0.--15. 1. "ADDR,ADDR"
group.long 0xB0++0x17
line.long 0x0 "SMMU_EVENTQ_IRQ_CFG0_LO,SMMU_EVENTQ_IRQ_CFG0_LO"
hexmask.long 0x0 2.--31. 1. "ADDR,ADDR"
rbitfld.long 0x0 0.--1. "Reserved_1_0,Reserved_1_0" "0,1,2,3"
line.long 0x4 "SMMU_EVENTQ_IRQ_CFG0_HI,SMMU_EVENTQ_IRQ_CFG0_HI"
hexmask.long.word 0x4 16.--31. 1. "Reserved_31_16,Reserved_31_16"
hexmask.long.word 0x4 0.--15. 1. "ADDR,ADDR"
line.long 0x8 "SMMU_EVENTQ_IRQ_CFG1,SMMU_EVENTQ_IRQ_CFG1"
hexmask.long 0x8 0.--31. 1. "DATA,DATA"
line.long 0xC "SMMU_EVENTQ_IRQ_CFG2,SMMU_EVENTQ_IRQ_CFG2"
hexmask.long 0xC 6.--31. 1. "Reserved_31_6,Reserved_31_6"
bitfld.long 0xC 4.--5. "SH,SH" "0,1,2,3"
hexmask.long.byte 0xC 0.--3. 1. "MemAttr,MemAttr"
line.long 0x10 "SMMU_PRIQ_BASE_LO,SMMU_PRIQ_BASE_LO"
hexmask.long 0x10 5.--31. 1. "ADDR,ADDR"
hexmask.long.byte 0x10 0.--4. 1. "LOG2SIZE,LOG2SIZE"
line.long 0x14 "SMMU_PRIQ_BASE_HI,SMMU_PRIQ_BASE_HI"
rbitfld.long 0x14 31. "Reserved_31_31,Reserved_31_31" "0,1"
bitfld.long 0x14 30. "WA,WA" "0,1"
hexmask.long.word 0x14 16.--29. 1. "Reserved_29_16,Reserved_29_16"
newline
hexmask.long.word 0x14 0.--15. 1. "ADDR,ADDR"
group.long 0xD0++0xF
line.long 0x0 "SMMU_PRIQ_IRQ_CFG0_LO,SMMU_PRIQ_IRQ_CFG0_LO"
hexmask.long 0x0 2.--31. 1. "ADDR,ADDR"
rbitfld.long 0x0 0.--1. "Reserved_1_0,Reserved_1_0" "0,1,2,3"
line.long 0x4 "SMMU_PRIQ_IRQ_CFG0_HI,SMMU_PRIQ_IRQ_CFG0_HI"
hexmask.long.word 0x4 16.--31. 1. "Reserved_31_16,Reserved_31_16"
hexmask.long.word 0x4 0.--15. 1. "ADDR,ADDR"
line.long 0x8 "SMMU_PRIQ_IRQ_CFG1,SMMU_PRIQ_IRQ_CFG1"
hexmask.long 0x8 0.--31. 1. "DATA,DATA"
line.long 0xC "SMMU_PRIQ_IRQ_CFG2,SMMU_PRIQ_IRQ_CFG2"
bitfld.long 0xC 31. "LO,LO" "0,1"
hexmask.long 0xC 6.--30. 1. "Reserved_30_6,Reserved_30_6"
bitfld.long 0xC 4.--5. "SH,SH" "0,1,2,3"
newline
hexmask.long.byte 0xC 0.--3. 1. "MemAttr,MemAttr"
rgroup.long 0xFD0++0x2F
line.long 0x0 "SMMU_PIDR4,This is the TCU Peripheral ID register 4. This is a standard JEP106 register that provides key information about the MMU-600 hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x0 4.--7. 1. "SIZE,4KB region count."
hexmask.long.byte 0x0 0.--3. 1. "DES_2,JEP106 continuation code for Arm."
line.long 0x4 "SMMU_PIDR5,This is the TCU Peripheral ID register 5. This is a standard JEP106 register that provides key information about the MMU-600 hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x4 0.--7. 1. "Reserved,Reserved."
line.long 0x8 "SMMU_PIDR6,This is the TCU Peripheral ID register 6. This is a standard JEP106 register that provides key information about the MMU-600 hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register."
hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x8 0.--7. 1. "Reserved,Reserved."
line.long 0xC "SMMU_PIDR7,This is the TCU Peripheral ID register 7. a standard JEP106 register that provides key information about the MMU-600 hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0xC 0.--7. 1. "Reserved,Reserved."
line.long 0x10 "SMMU_PIDR0,This is the TCU Peripheral ID register 0. a standard JEP106 register that provides key information about the MMU-600 hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x10 0.--7. 1. "PART_0,Part number[7:0]."
line.long 0x14 "SMMU_PIDR1,This is the TCU Peripheral ID register 1. a standard JEP106 register that provides key information about the MMU-600 hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register."
hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x14 4.--7. 1. "DES_0,JEP106 ID code[3:0] for Arm."
hexmask.long.byte 0x14 0.--3. 1. "PART_1,Part number[11:8]."
line.long 0x18 "SMMU_PIDR2,This is the TCU Peripheral ID register 2. a standard JEP106 register that provides key information about the MMU-600 hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x18 4.--7. 1. "REVISION,MMU-600 major revision. The value indicates major product revision rX."
bitfld.long 0x18 3. "JEDEC,IC uses a manufacturer identity code that is allocated by JEDEC  according to the JEP106 specification." "0,1"
newline
bitfld.long 0x18 0.--2. "DES_1,JEP106 ID code[6:4] for Arm." "0,1,2,3,4,5,6,7"
line.long 0x1C "SMMU_PIDR3,This is the TCU Peripheral ID register 3. a standard JEP106 register that provides key information about the MMU-600 hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID register."
hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x1C 4.--7. 1. "REVAND,MMU-600 minor revision. The value indicates minor product revision pY."
hexmask.long.byte 0x1C 0.--3. 1. "CMOD,Customer modification number. Do not modify this number unless you have permission from Arm."
line.long 0x20 "SMMU_CIDR0,This is the TCU Component Identification register 0. This register provides information that identifies the MMU-600 as an Arm component."
hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x20 0.--7. 1. "PREAMBLE,The value 0x0D identifies the MMU-600 as an Arm component."
line.long 0x24 "SMMU_CIDR1,This is the TCU Component Identification register 1. This register provides information that identifies the MMU-600 as an Arm component."
hexmask.long.tbyte 0x24 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x24 4.--7. 1. "CLASS,The value 0xF identifies the MMU-600 as an Arm CoreLink component."
hexmask.long.byte 0x24 0.--3. 1. "PREAMBLE,The value 0x0 identifies the MMU-600 as an Arm component."
line.long 0x28 "SMMU_CIDR2,This is the TCU Component Identification register 2. This register provides information that identifies the MMU-600 as an Arm component."
hexmask.long.tbyte 0x28 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x28 0.--7. 1. "PREAMBLE,The value 0x05 identifies the MMU-600 as an Arm component."
line.long 0x2C "SMMU_CIDR3,This is the TCU Component Identification register 3. This register provides information that identifies the MMU-600 as an Arm component."
hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x2C 0.--7. 1. "PREAMBLE,The value 0xB1 identifies the MMU-600 as an Arm component."
group.long 0x2400++0xF
line.long 0x0 "SMMU_PMCG_EVTYPER0,SMMU_PMCG_EVTYPER0"
bitfld.long 0x0 31. "OVFCAP,OVFCAP" "0,1"
bitfld.long 0x0 30. "FILTER_SEC_SID,FILTER_SEC_SID" "0,1"
bitfld.long 0x0 29. "FILTER_SID_SPAN,FILTER_SID_SPAN" "0,1"
newline
hexmask.long.tbyte 0x0 8.--28. 1. "Reserved_28_8,Reserved_28_8"
hexmask.long.byte 0x0 0.--7. 1. "EVNT,EVNT"
line.long 0x4 "SMMU_PMCG_EVTYPER1,SMMU_PMCG_EVTYPER1"
bitfld.long 0x4 31. "OVFCAP,OVFCAP" "0,1"
hexmask.long.tbyte 0x4 8.--30. 1. "Reserved_30_8,Reserved_30_8"
hexmask.long.byte 0x4 0.--7. 1. "EVNT,EVNT"
line.long 0x8 "SMMU_PMCG_EVTYPER2,SMMU_PMCG_EVTYPER2"
bitfld.long 0x8 31. "OVFCAP,OVFCAP" "0,1"
hexmask.long.tbyte 0x8 8.--30. 1. "Reserved_30_8,Reserved_30_8"
hexmask.long.byte 0x8 0.--7. 1. "EVNT,EVNT"
line.long 0xC "SMMU_PMCG_EVTYPER3,SMMU_PMCG_EVTYPER3"
bitfld.long 0xC 31. "OVFCAP,OVFCAP" "0,1"
hexmask.long.tbyte 0xC 8.--30. 1. "Reserved_30_8,Reserved_30_8"
hexmask.long.byte 0xC 0.--7. 1. "EVNT,EVNT"
group.long 0x2A00++0x3
line.long 0x0 "SMMU_PMCG_SMR0,SMMU_PMCG_SMR0"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved_31_24"
hexmask.long.tbyte 0x0 0.--23. 1. "STREAMID,STREAMID"
group.long 0x2C00++0x3
line.long 0x0 "SMMU_PMCG_CNTENSET0,SMMU_PMCG_CNTENSET0"
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved_31_4"
hexmask.long.byte 0x0 0.--3. 1. "CNTEN,CNTEN"
group.long 0x2C20++0x3
line.long 0x0 "SMMU_PMCG_CNTENCLR0,SMMU_PMCG_CNTENCLR0"
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved_31_4"
hexmask.long.byte 0x0 0.--3. 1. "CNTEN,CNTEN"
group.long 0x2C40++0x3
line.long 0x0 "SMMU_PMCG_INTENSET0,SMMU_PMCG_INTENSET0"
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved_31_4"
hexmask.long.byte 0x0 0.--3. 1. "INTEN,INTEN"
group.long 0x2C60++0x3
line.long 0x0 "SMMU_PMCG_INTENCLR0,SMMU_PMCG_INTENCLR0"
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved_31_4"
hexmask.long.byte 0x0 0.--3. 1. "INTEN,INTEN"
group.long 0x2DF8++0x3
line.long 0x0 "SMMU_PMCG_SCR,SMMU_PMCG_SCR"
bitfld.long 0x0 31. "READS_AS_ONE,READS_AS_ONE" "0,1"
hexmask.long 0x0 3.--30. 1. "Reserved_30_3,Reserved_30_3"
bitfld.long 0x0 2. "NSMSI,NSMSI" "0,1"
newline
bitfld.long 0x0 1. "NSRA,NSRA" "0,1"
bitfld.long 0x0 0. "SO,SO" "0,1"
rgroup.long 0x2E00++0x3
line.long 0x0 "SMMU_PMCG_CFGR,SMMU_PMCG_CFGR"
hexmask.long.byte 0x0 24.--31. 1. "Reserved_31_24,Reserved_31_24"
bitfld.long 0x0 23. "SID_FILTER_TYPE,SID_FILTER_TYPE" "0,1"
bitfld.long 0x0 22. "CAPTURE,CAPTURE" "0,1"
newline
bitfld.long 0x0 21. "MSI,MSI" "0,1"
bitfld.long 0x0 20. "RELOC_CTRS,RELOC_CTRS" "0,1"
hexmask.long.byte 0x0 14.--19. 1. "Reserved_19_14,Reserved_19_14"
newline
hexmask.long.byte 0x0 8.--13. 1. "SIZE,SIZE"
bitfld.long 0x0 6.--7. "Reserved_7_6,Reserved_7_6" "0,1,2,3"
hexmask.long.byte 0x0 0.--5. 1. "NCTR,NCTR"
group.long 0x2E04++0x3
line.long 0x0 "SMMU_PMCG_CR,SMMU_PMCG_CR"
hexmask.long 0x0 1.--31. 1. "Reserved_31_1,Reserved_31_1"
bitfld.long 0x0 0. "E,E" "0,1"
rgroup.long 0x2E20++0xF
line.long 0x0 "SMMU_PMCG_CEID0_LO,SMMU_PMCG_CEID0_LO"
hexmask.long 0x0 0.--31. 1. "N,N"
line.long 0x4 "SMMU_PMCG_CEID0_HI,SMMU_PMCG_CEID0_HI"
hexmask.long 0x4 0.--31. 1. "N,N"
line.long 0x8 "SMMU_PMCG_CEID1_LO,SMMU_PMCG_CEID1_LO"
hexmask.long 0x8 0.--31. 1. "N,N"
line.long 0xC "SMMU_PMCG_CEID1_HI,SMMU_PMCG_CEID1_HI"
hexmask.long 0xC 0.--31. 1. "N,N"
group.long 0x2E50++0x3
line.long 0x0 "SMMU_PMCG_IRQ_CTRL,SMMU_PMCG_IRQ_CTRL"
hexmask.long 0x0 1.--31. 1. "Reserved_31_1,Reserved_31_1"
bitfld.long 0x0 0. "IRQEN,IRQEN" "0,1"
rgroup.long 0x2E54++0x3
line.long 0x0 "SMMU_PMCG_IRQ_CTRLACK,SMMU_PMCG_IRQ_CTRLACK"
hexmask.long 0x0 1.--31. 1. "Reserved_31_1,Reserved_31_1"
bitfld.long 0x0 0. "IRQEN,IRQEN" "0,1"
rgroup.long 0x2E70++0x3
line.long 0x0 "SMMU_PMCG_AIDR,SMMU_PMCG_AIDR"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x0 4.--7. 1. "ARCHMAJORREV,ARCHMAJORREV"
hexmask.long.byte 0x0 0.--3. 1. "ARCHMINORREV,ARCHMINORREV"
rgroup.long 0x2FB8++0x7
line.long 0x0 "SMMU_PMCG_PMAUTHSTATUS,SMMU_PMCG_PMAUTHSTATUS"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved_31_8"
bitfld.long 0x0 7. "SNI,SNI" "0,1"
bitfld.long 0x0 6. "SNE,SNE" "0,1"
newline
bitfld.long 0x0 5. "SI,SI" "0,1"
bitfld.long 0x0 4. "SE,SE" "0,1"
bitfld.long 0x0 3. "NSNI,NSNI" "0,1"
newline
bitfld.long 0x0 2. "NSNE,NSNE" "0,1"
bitfld.long 0x0 1. "NSI,NSI" "0,1"
bitfld.long 0x0 0. "NSE,NSE" "0,1"
line.long 0x4 "SMMU_PMCG_PMDEVARCH,SMMU_PMCG_PMDEVARCH"
hexmask.long.word 0x4 21.--31. 1. "ARCHITECT,ARCHITECT"
bitfld.long 0x4 20. "PRESENT,PRESENT" "0,1"
hexmask.long.byte 0x4 16.--19. 1. "REVISION,REVISION"
newline
hexmask.long.word 0x4 0.--15. 1. "ARCHID,ARCHID"
rgroup.long 0x2FCC++0x33
line.long 0x0 "SMMU_PMCG_PMDEVTYPE,SMMU_PMCG_PMDEVTYPE"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x0 4.--7. 1. "SUB_TYPE,SUB_TYPE"
hexmask.long.byte 0x0 0.--3. 1. "CLS,CLS"
line.long 0x4 "SMMU_PMCG_PIDR4,This is the PMU Peripheral ID register 4. This is a standard JEP106 register that provides key information about the MMU-600 PMU hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual.."
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x4 4.--7. 1. "SIZE,4KB region count."
hexmask.long.byte 0x4 0.--3. 1. "DES_2,JEP106 continuation code for Arm."
line.long 0x8 "SMMU_PMCG_PIDR5,This is the PMU Peripheral ID register 5. This is a standard JEP106 register that provides key information about the MMU-600 PMU hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual.."
hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x8 0.--7. 1. "Reserved,Reserved."
line.long 0xC "SMMU_PMCG_PIDR6,This is the PMU Peripheral ID register 6. This is a standard JEP106 register that provides key information about the MMU-600 PMU hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual.."
hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0xC 0.--7. 1. "Reserved,Reserved."
line.long 0x10 "SMMU_PMCG_PIDR7,This is the PMU Peripheral ID register 7. a standard JEP106 register that provides key information about the MMU-600 PMU hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID.."
hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x10 0.--7. 1. "Reserved,Reserved."
line.long 0x14 "SMMU_PMCG_PIDR0,This is the PMU Peripheral ID register 0. a standard JEP106 register that provides key information about the MMU-600 PMU hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID.."
hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x14 0.--7. 1. "PART_0,Part number[7:0]."
line.long 0x18 "SMMU_PMCG_PIDR1,This is the PMU Peripheral ID register 1. a standard JEP106 register that provides key information about the MMU-600 PMU hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID.."
hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x18 4.--7. 1. "DES_0,JEP106 ID code[3:0] for Arm."
hexmask.long.byte 0x18 0.--3. 1. "PART_1,Part number[11:8]."
line.long 0x1C "SMMU_PMCG_PIDR2,This is the PMU Peripheral ID register 2. a standard JEP106 register that provides key information about the MMU-600 PMU hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID.."
hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x1C 4.--7. 1. "REVISION,MMU-600 major revision. The value indicates major product revision rX."
bitfld.long 0x1C 3. "JEDEC,IC uses a manufacturer identity code that is allocated by JEDEC  according to the JEP106 specification." "0,1"
newline
bitfld.long 0x1C 0.--2. "DES_1,JEP106 ID code[6:4] for Arm." "0,1,2,3,4,5,6,7"
line.long 0x20 "SMMU_PMCG_PIDR3,This is the PMU Peripheral ID register 3. a standard JEP106 register that provides key information about the MMU-600 PMU hardware. The least significant 8 bits of the eight Peripheral ID registers form a single 64-bit conceptual ID.."
hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x20 4.--7. 1. "REVAND,MMU-600 minor revision. The value indicates minor product revision pY."
hexmask.long.byte 0x20 0.--3. 1. "CMOD,Customer modification number. Do not modify this number unless you have permission from Arm."
line.long 0x24 "SMMU_PMCG_CIDR0,This is the PMU Component Identification register 0. This register provides information that identifies the MMU-600 PMU as an Arm component."
hexmask.long.tbyte 0x24 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x24 0.--7. 1. "PREAMBLE,The value 0x0D identifies the MMU-600 PMU as an Arm component."
line.long 0x28 "SMMU_PMCG_CIDR1,This is the PMU Component Identification register 1. This register provides information that identifies the MMU-600 PMU as an Arm component."
hexmask.long.tbyte 0x28 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x28 4.--7. 1. "CLASS,The value 0x9 identifies the MMU-600 as an Arm CoreSight component."
hexmask.long.byte 0x28 0.--3. 1. "PREAMBLE,The value 0x0 identifies the MMU-600 as an Arm component."
line.long 0x2C "SMMU_PMCG_CIDR2,This is the PMU Component Identification register 2. This register provides information that identifies the MMU-600 PMU as an Arm component."
hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x2C 0.--7. 1. "PREAMBLE,The value 0x05 identifies the MMU-600 PMU as an Arm component."
line.long 0x30 "SMMU_PMCG_CIDR3,This is the PMU Component Identification register 3. This register provides information that identifies the MMU-600 PMU as an Arm component."
hexmask.long.tbyte 0x30 8.--31. 1. "Reserved_31_8,Reserved_31_8"
hexmask.long.byte 0x30 0.--7. 1. "PREAMBLE,The value 0xB1 identifies the MMU-600 PMU as an Arm component."
rgroup.long 0x8000++0x7
line.long 0x0 "SMMU_S_IDR0,SMMU_S_IDR0"
hexmask.long.byte 0x0 26.--31. 1. "Reserved_31_26,Reserved_31_26"
bitfld.long 0x0 24.--25. "STALL_MODEL,STALL_MODEL" "0,1,2,3"
hexmask.long.word 0x0 14.--23. 1. "Reserved_23_14,Reserved_23_14"
newline
bitfld.long 0x0 13. "MSI,MSI" "0,1"
hexmask.long.word 0x0 0.--12. 1. "Reserved_12_0,Reserved_12_0"
line.long 0x4 "SMMU_S_IDR1,SMMU_S_IDR1"
bitfld.long 0x4 31. "SECURE_IMPL,SECURE_IMPL" "0,1"
hexmask.long 0x4 6.--30. 1. "Reserved_30_6,Reserved_30_6"
hexmask.long.byte 0x4 0.--5. 1. "S_SIDSIZE,S_SIDSIZE"
rgroup.long 0x800C++0x3
line.long 0x0 "SMMU_S_IDR3,SMMU_S_IDR3"
hexmask.long 0x0 7.--31. 1. "Reserved_31_7,Reserved_31_7"
bitfld.long 0x0 6. "SAMS,SAMS" "0,1"
hexmask.long.byte 0x0 0.--5. 1. "Reserved_5_0,Reserved_5_0"
group.long 0x8020++0xF
line.long 0x0 "SMMU_S_CR0,SMMU_S_CR0"
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_31_10,Reserved_31_10"
bitfld.long 0x0 9. "NSSTALLD,NSSTALLD" "0,1"
rbitfld.long 0x0 6.--8. "Reserved_8_6,Reserved_8_6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 5. "SIF,SIF" "0,1"
rbitfld.long 0x0 4. "Reserved_4_4,Reserved_4_4" "0,1"
bitfld.long 0x0 3. "CMDQEN,CMDQEN" "0,1"
newline
bitfld.long 0x0 2. "EVENTQEN,EVENTQEN" "0,1"
rbitfld.long 0x0 1. "Reserved_1_1,Reserved_1_1" "0,1"
bitfld.long 0x0 0. "SMMUEN,SMMUEN" "0,1"
line.long 0x4 "SMMU_S_CR0ACK,SMMU_S_CR0ACK"
hexmask.long.tbyte 0x4 10.--31. 1. "Reserved_31_10,Reserved_31_10"
bitfld.long 0x4 9. "NSSTALLD,NSSTALLD" "0,1"
rbitfld.long 0x4 6.--8. "Reserved_8_6,Reserved_8_6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 5. "SIF,SIF" "0,1"
rbitfld.long 0x4 4. "Reserved_4_4,Reserved_4_4" "0,1"
bitfld.long 0x4 3. "CMDQEN,CMDQEN" "0,1"
newline
bitfld.long 0x4 2. "EVENTQEN,EVENTQEN" "0,1"
rbitfld.long 0x4 1. "Reserved_1_1,Reserved_1_1" "0,1"
bitfld.long 0x4 0. "SMMUEN,SMMUEN" "0,1"
line.long 0x8 "SMMU_S_CR1,SMMU_S_CR1"
hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_31_12,Reserved_31_12"
bitfld.long 0x8 10.--11. "TABLE_SH,TABLE_SH" "0,1,2,3"
bitfld.long 0x8 8.--9. "TABLE_OC,TABLE_OC" "0,1,2,3"
newline
bitfld.long 0x8 6.--7. "TABLE_IC,TABLE_IC" "0,1,2,3"
bitfld.long 0x8 4.--5. "QUEUE_SH,QUEUE_SH" "0,1,2,3"
bitfld.long 0x8 2.--3. "QUEUE_OC,QUEUE_OC" "0,1,2,3"
newline
bitfld.long 0x8 0.--1. "QUEUE_IC,QUEUE_IC" "0,1,2,3"
line.long 0xC "SMMU_S_CR2,SMMU_S_CR2"
hexmask.long 0xC 3.--31. 1. "Reserved_31_3,Reserved_31_3"
bitfld.long 0xC 2. "PTM,PTM" "0,1"
bitfld.long 0xC 1. "RECINVSID,RECINVSID" "0,1"
newline
rbitfld.long 0xC 0. "Reserved_0_0,Reserved_0_0" "0,1"
group.long 0x803C++0x3
line.long 0x0 "SMMU_S_INIT,SMMU_S_INIT"
hexmask.long 0x0 1.--31. 1. "Reserved_31_1,Reserved_31_1"
bitfld.long 0x0 0. "INV_ALL,INV_ALL" "0,1"
group.long 0x8044++0x3
line.long 0x0 "SMMU_S_GBPA,SMMU_S_GBPA"
bitfld.long 0x0 31. "Update,Update" "0,1"
hexmask.long.word 0x0 21.--30. 1. "Reserved_30_21,Reserved_30_21"
bitfld.long 0x0 20. "ABORT,ABORT" "0,1"
newline
bitfld.long 0x0 18.--19. "INSTCFG,INSTCFG" "0,1,2,3"
bitfld.long 0x0 16.--17. "PRIVCFG,PRIVCFG" "0,1,2,3"
bitfld.long 0x0 14.--15. "NSCFG,NSCFG" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "SHCFG,SHCFG" "0,1,2,3"
hexmask.long.byte 0x0 8.--11. 1. "ALLOCCFG,ALLOCCFG"
rbitfld.long 0x0 5.--7. "Reserved_7_5,Reserved_7_5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "MTCFG,MTCFG" "0,1"
hexmask.long.byte 0x0 0.--3. 1. "MemAttr,MemAttr"
group.long 0x8050++0x3
line.long 0x0 "SMMU_S_IRQ_CTRL,SMMU_S_IRQ_CTRL"
hexmask.long 0x0 3.--31. 1. "Reserved_31_3,Reserved_31_3"
bitfld.long 0x0 2. "EVENTQ_IRQEN,EVENTQ_IRQEN" "0,1"
rbitfld.long 0x0 1. "Reserved_1_1,Reserved_1_1" "0,1"
newline
bitfld.long 0x0 0. "GERROR_IRQEN,GERROR_IRQEN" "0,1"
rgroup.long 0x8054++0x3
line.long 0x0 "SMMU_S_IRQ_CTRLACK,SMMU_S_IRQ_CTRLACK"
hexmask.long 0x0 3.--31. 1. "Reserved_31_3,Reserved_31_3"
bitfld.long 0x0 2. "EVENTQ_IRQEN,EVENTQ_IRQEN" "0,1"
bitfld.long 0x0 1. "Reserved_1_1,Reserved_1_1" "0,1"
newline
bitfld.long 0x0 0. "GERROR_IRQEN,GERROR_IRQEN" "0,1"
rgroup.long 0x8060++0x3
line.long 0x0 "SMMU_S_GERROR,SMMU_S_GERROR"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved_31_8"
bitfld.long 0x0 7. "MSI_GERROR_ABT_ERR,MSI_GERROR_ABT_ERR" "0,1"
bitfld.long 0x0 6. "Reserved_6_6,Reserved_6_6" "0,1"
newline
bitfld.long 0x0 5. "MSI_EVENTQ_ABT_ERR,MSI_EVENTQ_ABT_ERR" "0,1"
bitfld.long 0x0 4. "MSI_CMDQ_ABT_ERR,MSI_CMDQ_ABT_ERR" "0,1"
bitfld.long 0x0 3. "Reserved_3_3,Reserved_3_3" "0,1"
newline
bitfld.long 0x0 2. "EVENTQ_ABT_ERR,EVENTQ_ABT_ERR" "0,1"
bitfld.long 0x0 1. "Reserved_1_1,Reserved_1_1" "0,1"
bitfld.long 0x0 0. "CMDQ_ERR,CMDQ_ERR" "0,1"
group.long 0x8064++0x13
line.long 0x0 "SMMU_S_GERRORN,SMMU_S_GERRORN"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved_31_8"
bitfld.long 0x0 7. "MSI_GERROR_ABT_ERR,MSI_GERROR_ABT_ERR" "0,1"
rbitfld.long 0x0 6. "Reserved_6_6,Reserved_6_6" "0,1"
newline
bitfld.long 0x0 5. "MSI_EVENTQ_ABT_ERR,MSI_EVENTQ_ABT_ERR" "0,1"
bitfld.long 0x0 4. "MSI_CMDQ_ABT_ERR,MSI_CMDQ_ABT_ERR" "0,1"
rbitfld.long 0x0 3. "Reserved_3_3,Reserved_3_3" "0,1"
newline
bitfld.long 0x0 2. "EVENTQ_ABT_ERR,EVENTQ_ABT_ERR" "0,1"
rbitfld.long 0x0 1. "Reserved_1_1,Reserved_1_1" "0,1"
bitfld.long 0x0 0. "CMDQ_ERR,CMDQ_ERR" "0,1"
line.long 0x4 "SMMU_S_GERROR_IRQ_CFG0_LO,SMMU_S_GERROR_IRQ_CFG0_LO"
hexmask.long 0x4 2.--31. 1. "ADDR,ADDR"
rbitfld.long 0x4 0.--1. "Reserved_1_0,Reserved_1_0" "0,1,2,3"
line.long 0x8 "SMMU_S_GERROR_IRQ_CFG0_HI,SMMU_S_GERROR_IRQ_CFG0_HI"
hexmask.long.word 0x8 16.--31. 1. "Reserved_31_16,Reserved_31_16"
hexmask.long.word 0x8 0.--15. 1. "ADDR,ADDR"
line.long 0xC "SMMU_S_GERROR_IRQ_CFG1,SMMU_S_GERROR_IRQ_CFG1"
hexmask.long 0xC 0.--31. 1. "DATA,DATA"
line.long 0x10 "SMMU_S_GERROR_IRQ_CFG2,SMMU_S_GERROR_IRQ_CFG2"
hexmask.long 0x10 6.--31. 1. "Reserved_31_6,Reserved_31_6"
bitfld.long 0x10 4.--5. "SH,SH" "0,1,2,3"
hexmask.long.byte 0x10 0.--3. 1. "MemAttr,MemAttr"
group.long 0x8080++0xB
line.long 0x0 "SMMU_S_STRTAB_BASE_LO,SMMU_S_STRTAB_BASE_LO"
hexmask.long 0x0 6.--31. 1. "ADDR,ADDR"
hexmask.long.byte 0x0 0.--5. 1. "Reserved_5_0,Reserved_5_0"
line.long 0x4 "SMMU_S_STRTAB_BASE_HI,SMMU_S_STRTAB_BASE_HI"
rbitfld.long 0x4 31. "Reserved_31_31,Reserved_31_31" "0,1"
bitfld.long 0x4 30. "RA,RA" "0,1"
hexmask.long.word 0x4 16.--29. 1. "Reserved_29_16,Reserved_29_16"
newline
hexmask.long.word 0x4 0.--15. 1. "ADDR,ADDR"
line.long 0x8 "SMMU_S_STRTAB_BASE_CFG,SMMU_S_STRTAB_BASE_CFG"
hexmask.long.word 0x8 18.--31. 1. "Reserved_31_18,Reserved_31_18"
bitfld.long 0x8 16.--17. "FMT,FMT" "0,1,2,3"
hexmask.long.byte 0x8 11.--15. 1. "Reserved_15_11,Reserved_15_11"
newline
hexmask.long.byte 0x8 6.--10. 1. "SPLIT,SPLIT"
hexmask.long.byte 0x8 0.--5. 1. "LOG2SIZE,LOG2SIZE"
group.long 0x8090++0x2F
line.long 0x0 "SMMU_S_CMDQ_BASE_LO,SMMU_S_CMDQ_BASE_LO"
hexmask.long 0x0 5.--31. 1. "ADDR,ADDR"
hexmask.long.byte 0x0 0.--4. 1. "LOG2SIZE,LOG2SIZE"
line.long 0x4 "SMMU_S_CMDQ_BASE_HI,SMMU_S_CMDQ_BASE_HI"
rbitfld.long 0x4 31. "Reserved_31_31,Reserved_31_31" "0,1"
bitfld.long 0x4 30. "RA,RA" "0,1"
hexmask.long.word 0x4 16.--29. 1. "Reserved_29_16,Reserved_29_16"
newline
hexmask.long.word 0x4 0.--15. 1. "ADDR,ADDR"
line.long 0x8 "SMMU_S_CMDQ_PROD,SMMU_S_CMDQ_PROD"
hexmask.long.word 0x8 20.--31. 1. "Reserved_31_20,Reserved_31_20"
hexmask.long.tbyte 0x8 0.--19. 1. "WR,WR"
line.long 0xC "SMMU_S_CMDQ_CONS,SMMU_S_CMDQ_CONS"
rbitfld.long 0xC 31. "Reserved_31_31,Reserved_31_31" "0,1"
hexmask.long.byte 0xC 24.--30. 1. "ERR,ERR"
hexmask.long.byte 0xC 20.--23. 1. "Reserved_23_20,Reserved_23_20"
newline
hexmask.long.tbyte 0xC 0.--19. 1. "RD,RD"
line.long 0x10 "SMMU_S_EVENTQ_BASE_LO,SMMU_S_EVENTQ_BASE_LO"
hexmask.long 0x10 5.--31. 1. "ADDR,ADDR"
hexmask.long.byte 0x10 0.--4. 1. "LOG2SIZE,LOG2SIZE"
line.long 0x14 "SMMU_S_EVENTQ_BASE_HI,SMMU_S_EVENTQ_BASE_HI"
rbitfld.long 0x14 31. "Reserved_31_31,Reserved_31_31" "0,1"
bitfld.long 0x14 30. "WA,WA" "0,1"
hexmask.long.word 0x14 16.--29. 1. "Reserved_29_16,Reserved_29_16"
newline
hexmask.long.word 0x14 0.--15. 1. "ADDR,ADDR"
line.long 0x18 "SMMU_S_EVENTQ_PROD,SMMU_S_EVENTQ_PROD"
bitfld.long 0x18 31. "OVFLG,OVFLG" "0,1"
hexmask.long.word 0x18 20.--30. 1. "Reserved_30_20,Reserved_30_20"
hexmask.long.tbyte 0x18 0.--19. 1. "WR,WR"
line.long 0x1C "SMMU_S_EVENTQ_CONS,SMMU_S_EVENTQ_CONS"
bitfld.long 0x1C 31. "OVACKFLG,OVACKFLG" "0,1"
hexmask.long.word 0x1C 20.--30. 1. "Reserved_30_20,Reserved_30_20"
hexmask.long.tbyte 0x1C 0.--19. 1. "RD,RD"
line.long 0x20 "SMMU_S_EVENTQ_IRQ_CFG0_LO,SMMU_S_EVENTQ_IRQ_CFG0_LO"
hexmask.long 0x20 2.--31. 1. "ADDR,ADDR"
rbitfld.long 0x20 0.--1. "Reserved_1_0,Reserved_1_0" "0,1,2,3"
line.long 0x24 "SMMU_S_EVENTQ_IRQ_CFG0_HI,SMMU_S_EVENTQ_IRQ_CFG0_HI"
hexmask.long.word 0x24 16.--31. 1. "Reserved_31_16,Reserved_31_16"
hexmask.long.word 0x24 0.--15. 1. "ADDR,ADDR"
line.long 0x28 "SMMU_S_EVENTQ_IRQ_CFG1,SMMU_S_EVENTQ_IRQ_CFG1"
hexmask.long 0x28 0.--31. 1. "DATA,DATA"
line.long 0x2C "SMMU_S_EVENTQ_IRQ_CFG2,SMMU_S_EVENTQ_IRQ_CFG2"
hexmask.long 0x2C 6.--31. 1. "Reserved_31_6,Reserved_31_6"
bitfld.long 0x2C 4.--5. "SH,SH" "0,1,2,3"
hexmask.long.byte 0x2C 0.--3. 1. "MemAttr,MemAttr"
group.long 0x8E00++0x7
line.long 0x0 "TCU_CTRL,The TCU Control register disables TCU features. You can disable individual walk caches. which can improve performance in some systems if the hit rate of the individual walk cache is very low. Do not modify the other bits unless directed to by.."
bitfld.long 0x0 31. "AUX31,Leave this bit as zero." "0,1"
bitfld.long 0x0 30. "AUX30,Leave this bit as zero." "0,1"
bitfld.long 0x0 29. "AUX29,Leave this bit as zero." "0,1"
newline
bitfld.long 0x0 28. "AUX28,Leave this bit as zero." "0,1"
bitfld.long 0x0 27. "AUX27,Leave this bit as zero." "0,1"
bitfld.long 0x0 26. "AUX26,Leave this bit as zero." "0,1"
newline
bitfld.long 0x0 25. "AUX25,Leave this bit as zero." "0,1"
bitfld.long 0x0 24. "AUX24,Leave this bit as zero." "0,1"
bitfld.long 0x0 23. "AUX23,Leave this bit as zero." "0,1"
newline
bitfld.long 0x0 22. "AUX22,Leave this bit as zero." "0,1"
bitfld.long 0x0 21. "AUX21,Leave this bit as zero." "0,1"
bitfld.long 0x0 20. "AUX20,Leave this bit as zero." "0,1"
newline
bitfld.long 0x0 19. "AUX19,Leave this bit as zero." "0,1"
bitfld.long 0x0 18. "AUX18,Leave this bit as zero." "0,1"
bitfld.long 0x0 17. "AUX17,Leave this bit as zero." "0,1"
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bitfld.long 0x0 16. "AUX16,Leave this bit as zero." "0,1"
bitfld.long 0x0 15. "WCS2L3_DIS,Walk cache disable. When this bit is set to 1  the stage 2 level 3 walk cache is disabled." "0,1"
bitfld.long 0x0 14. "WCS2L2_DIS,Walk cache disable. When this bit is set to 1  the stage 2 level 2 walk cache is disabled." "0,1"
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bitfld.long 0x0 13. "WCS2L1_DIS,Walk cache disable. When this bit is set to 1  the stage 2 level 1 walk cache is disabled." "0,1"
bitfld.long 0x0 12. "WCS2L0_DIS,Walk cache disable. When this bit is set to 1  the stage 2 level 0 walk cache is disabled." "0,1"
bitfld.long 0x0 11. "WCS1L3_DIS,Walk cache disable. When this bit is set to 1  the stage 1 level 3 walk cache is disabled." "0,1"
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bitfld.long 0x0 10. "WCS1L2_DIS,Walk cache disable. When this bit is set to 1  the stage 1 level 2 walk cache is disabled." "0,1"
bitfld.long 0x0 9. "WCS1L1_DIS,Walk cache disable. When this bit is set to 1  the stage 1 level 1 walk cache is disabled." "0,1"
bitfld.long 0x0 8. "WCS1L0_DIS,Walk cache disable. When this bit is set to 1  the stage 2 level 0 walk cache is disabled." "0,1"
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bitfld.long 0x0 7. "AUX7,Leave this bit as zero." "0,1"
bitfld.long 0x0 6. "AUX6,Leave this bit as zero." "0,1"
bitfld.long 0x0 5. "AUX5,Leave this bit as zero." "0,1"
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bitfld.long 0x0 4. "AUX4,Leave this bit as zero." "0,1"
bitfld.long 0x0 3. "AUX3,Leave this bit as zero." "0,1"
bitfld.long 0x0 2. "AUX2,Leave this bit as zero." "0,1"
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bitfld.long 0x0 1. "AUX1,Leave this bit as zero." "0,1"
bitfld.long 0x0 0. "AUX0,Leave this bit as zero." "0,1"
line.long 0x4 "TCU_QOS,This is the TCU Quality of Service register. Use this register to specify QoS values for each transaction type. The MMU-600 uses the QoS value as a priority indicator for arbitration of requests."
hexmask.long.byte 0x4 28.--31. 1. "Reserved_31_28,Reserved_31_28"
hexmask.long.byte 0x4 24.--27. 1. "QOS_DVMSYNC,The QoS priority level that is used for DVM Sync Completion messages."
hexmask.long.byte 0x4 20.--23. 1. "QOS_MSI,The QoS priority level that is used for MSIs."
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hexmask.long.byte 0x4 16.--19. 1. "QOS_QUEUE,The QoS priority level that is used for queue accesses."
hexmask.long.byte 0x4 12.--15. 1. "QOS_PTW3,The QoS priority level that is used for translation table walks. This level is used for translations where TCU_NODE_CTRLn.PRIORITY=3 for the requesting node."
hexmask.long.byte 0x4 8.--11. 1. "QOS_PTW2,The QoS priority level that is used for translation table walks for translations where TCU_NODE_CTRLn.PRIORITY=2 for the requesting node."
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hexmask.long.byte 0x4 4.--7. 1. "QOS_PTW1,The QoS priority level that is used for translation table walks for translations where TCU_NODE_CTRLn.PRIORITY=1 for the requesting node."
hexmask.long.byte 0x4 0.--3. 1. "QOS_PTW0,The QoS priority level that is used for translation table walks for ATOS translations and for translations where TCU_NODE_CTRLn.PRIORITY=0 for the requesting node."
rgroup.long 0x8E08++0x3
line.long 0x0 "TCU_CFG,This is the TCU Configuration Information register."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved_31_16"
hexmask.long.word 0x0 4.--15. 1. "XLATE_SLOTS,This is the number of translation slots that are available for sharing between all nodes."
hexmask.long.byte 0x0 0.--3. 1. "Reserved_3_0,Reserved_3_0"
rgroup.long 0x8E10++0x3
line.long 0x0 "TCU_STATUS,This is the TCU Status Information register."
hexmask.long.word 0x0 16.--31. 1. "Reserved_31_16,Reserved_31_16"
hexmask.long.word 0x0 4.--15. 1. "GNT_XLATE_SLOTS,This is the number of translation slots that are currently allocated to connected nodes. You can use this value for debugging purposes."
hexmask.long.byte 0x0 0.--3. 1. "Reserved_3_0,Reserved_3_0"
group.long 0x8E18++0x3
line.long 0x0 "TCU_SCR,This is the TCU Secure Control register."
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved_31_4"
bitfld.long 0x0 3. "NS_INIT,Non-secure register access to SMMU_S_INIT. When this bit is set to 0  Non-secure accesses to the SMMU_S_INIT register are RAZ/WI." "0,1"
rbitfld.long 0x0 2. "Reserved_2_2,Reserved_2_2" "0,1"
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bitfld.long 0x0 1. "NS_RAS,Non-secure register access permitted for RAS registers. When this bit is set to 0  Non-secure accesses to register addresses 0x08E80-0x08EBC are RAZ/WI.The sec_override input signal defines the reset value of this bit." "0,1"
bitfld.long 0x0 0. "NS_UARCH,Non-secure register access permitted for MMU-600 registers. When this bit is set to 0  Non-secure accesses to register addresses 0x08E00-0x08E7C and 0x09000-0x093FC are RAZ/WI.The sec_override input signal defines the reset value of this bit.Arm.." "0,1"
rgroup.long 0x8E80++0x7
line.long 0x0 "TCU_ERRFR_LO,TCU_ERRFR_LO"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_31_8,Reserved_31_8"
bitfld.long 0x0 6.--7. "FI,The value 0x2 indicates that the fault handling interrupt is controllable." "0,1,2,3"
hexmask.long.byte 0x0 2.--5. 1. "Reserved_5_2,Reserved_5_2"
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bitfld.long 0x0 0.--1. "ED,The value 0x1 indicates that TCU error detection is always enabled." "0,1,2,3"
line.long 0x4 "TCU_ERRFR_HI,TCU_ERRFR_HI"
hexmask.long 0x4 0.--31. 1. "Reserved_31_0,Reserved_31_0"
group.long 0x8E88++0x3
line.long 0x0 "TCU_ERRCTLR_LO,TCU_ERRCTLR_LO"
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved_31_4"
bitfld.long 0x0 3. "FI,Set this bit to 1 to enable fault handling interrupts for the TCU." "0,1"
rbitfld.long 0x0 0.--2. "Reserved_2_0,Reserved_2_0" "0,1,2,3,4,5,6,7"
rgroup.long 0x8E8C++0x3
line.long 0x0 "TCU_ERRCTLR_HI,TCU_ERRCTLR_HI"
hexmask.long 0x0 0.--31. 1. "Reserved_31_0,Reserved_31_0"
group.long 0x8E90++0x3
line.long 0x0 "TCU_ERRSTATUS_LO,TCU_ERRSTATUS_LO"
rbitfld.long 0x0 31. "Reserved_31_31,Reserved_31_31" "0,1"
bitfld.long 0x0 30. "V,Register valid. This bit is set to 1 to indicate that at least one RAS error was recorded. Clear this bit by writing a 1 to it. If CE is not 00 and is not being cleared  the write is ignored. A write of 0 is ignored." "0,1"
rbitfld.long 0x0 28.--29. "Reserved_29_28,Reserved_29_28" "0,1,2,3"
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bitfld.long 0x0 27. "OF,Overflow. This bit is set to 1 to indicate that multiple errors were recorded. Clear this bit by writing a 1 to it. A write of 0 is ignored." "0,1"
rbitfld.long 0x0 26. "Reserved_26_26,Reserved_26_26" "0,1"
bitfld.long 0x0 24.--25. "CE,Correctable Error. This field is set to 1 to indicate that a corrected error occurred. Clear this bit by writing a 11 to it. If OF is set to 1 and is not being cleared  the write is ignored. A write of any value other than 11 is ignored." "0,1,2,3"
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hexmask.long.byte 0x0 16.--23. 1. "Reserved_23_16,Reserved_23_16"
hexmask.long.byte 0x0 8.--15. 1. "IERR,Implementation defined error code. When SERR is not set to 0  this field indicates the source of the error  as follows: 0x00 Stage 1  level 0 walk cache. 0x01 Stage 1  level 1 walk cache. 0x02 Stage 1  level 2 walk cache. 0x03 Stage 1 .."
hexmask.long.byte 0x0 0.--7. 1. "SERR,Error code. This read-only field provides information about the earliest unacknowledged correctable error  as follows: 0x00 No error. This occurs when CE = 00. 0x07 Tag corrupted. This can occur when CE != 00. 0x08 Data corrupted. This can.."
rgroup.long 0x8E94++0x3
line.long 0x0 "TCU_ERRSTATUS_HI,TCU_ERRSTATUS_HI"
hexmask.long 0x0 0.--31. 1. "Reserved_31_0,Reserved_31_0"
group.long 0x8EC0++0x3
line.long 0x0 "TCU_ERRGEN_LO,TCU_ERRGEN_LO"
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved_31_4"
bitfld.long 0x0 3. "TCC,When 1  entries allocated into the configuration cache are written with a tag parity error." "0,1"
bitfld.long 0x0 2. "DCC,When 1  entries allocated into the configuration cache are written with a data parity error." "0,1"
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bitfld.long 0x0 1. "TWC,When 1  entries allocated into any walk cache are written with a tag parity error." "0,1"
bitfld.long 0x0 0. "DWC,When 1  entries allocated into any walk cache are written with a data parity error." "0,1"
rgroup.long 0x8EC4++0x3
line.long 0x0 "TCU_ERRGEN_HI,TCU_ERRGEN_HI"
hexmask.long 0x0 0.--31. 1. "Reserved_31_0,Reserved_31_0"
group.long 0x9000++0xF7
line.long 0x0 "TCU_NODE_CTRL0,TCU_NODE_CTRL0"
hexmask.long 0x0 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x0 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x0 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x0 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x4 "TCU_NODE_CTRL1,TCU_NODE_CTRL1"
hexmask.long 0x4 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x4 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x4 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x4 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x8 "TCU_NODE_CTRL2,TCU_NODE_CTRL2"
hexmask.long 0x8 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x8 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x8 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x8 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xC "TCU_NODE_CTRL3,TCU_NODE_CTRL3"
hexmask.long 0xC 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xC 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xC 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0xC 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x10 "TCU_NODE_CTRL4,TCU_NODE_CTRL4"
hexmask.long 0x10 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x10 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x10 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x10 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x14 "TCU_NODE_CTRL5,TCU_NODE_CTRL5"
hexmask.long 0x14 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x14 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x14 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x14 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x18 "TCU_NODE_CTRL6,TCU_NODE_CTRL6"
hexmask.long 0x18 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x18 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x18 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x18 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x1C "TCU_NODE_CTRL7,TCU_NODE_CTRL7"
hexmask.long 0x1C 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x1C 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x1C 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x1C 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x20 "TCU_NODE_CTRL8,TCU_NODE_CTRL8"
hexmask.long 0x20 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x20 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x20 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x20 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x24 "TCU_NODE_CTRL9,TCU_NODE_CTRL9"
hexmask.long 0x24 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x24 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x24 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x24 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x28 "TCU_NODE_CTRL10,TCU_NODE_CTRL10"
hexmask.long 0x28 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x28 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x28 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x28 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x2C "TCU_NODE_CTRL11,TCU_NODE_CTRL11"
hexmask.long 0x2C 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x2C 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x2C 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x2C 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x30 "TCU_NODE_CTRL12,TCU_NODE_CTRL12"
hexmask.long 0x30 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x30 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x30 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x30 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x34 "TCU_NODE_CTRL13,TCU_NODE_CTRL13"
hexmask.long 0x34 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x34 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x34 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x34 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x38 "TCU_NODE_CTRL14,TCU_NODE_CTRL14"
hexmask.long 0x38 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x38 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x38 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x38 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x3C "TCU_NODE_CTRL15,TCU_NODE_CTRL15"
hexmask.long 0x3C 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x3C 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x3C 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x3C 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x40 "TCU_NODE_CTRL16,TCU_NODE_CTRL16"
hexmask.long 0x40 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x40 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x40 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x40 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x44 "TCU_NODE_CTRL17,TCU_NODE_CTRL17"
hexmask.long 0x44 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x44 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x44 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x44 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x48 "TCU_NODE_CTRL18,TCU_NODE_CTRL18"
hexmask.long 0x48 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x48 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x48 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
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bitfld.long 0x48 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x4C "TCU_NODE_CTRL19,TCU_NODE_CTRL19"
hexmask.long 0x4C 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x4C 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x4C 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x4C 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x50 "TCU_NODE_CTRL20,TCU_NODE_CTRL20"
hexmask.long 0x50 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x50 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x50 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x50 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x54 "TCU_NODE_CTRL21,TCU_NODE_CTRL21"
hexmask.long 0x54 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x54 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x54 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x54 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x58 "TCU_NODE_CTRL22,TCU_NODE_CTRL22"
hexmask.long 0x58 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x58 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x58 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x58 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x5C "TCU_NODE_CTRL23,TCU_NODE_CTRL23"
hexmask.long 0x5C 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x5C 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x5C 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x5C 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x60 "TCU_NODE_CTRL24,TCU_NODE_CTRL24"
hexmask.long 0x60 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x60 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x60 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x60 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x64 "TCU_NODE_CTRL25,TCU_NODE_CTRL25"
hexmask.long 0x64 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x64 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x64 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x64 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x68 "TCU_NODE_CTRL26,TCU_NODE_CTRL26"
hexmask.long 0x68 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x68 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x68 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x68 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x6C "TCU_NODE_CTRL27,TCU_NODE_CTRL27"
hexmask.long 0x6C 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x6C 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x6C 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x6C 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x70 "TCU_NODE_CTRL28,TCU_NODE_CTRL28"
hexmask.long 0x70 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x70 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x70 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x70 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x74 "TCU_NODE_CTRL29,TCU_NODE_CTRL29"
hexmask.long 0x74 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x74 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x74 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x74 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x78 "TCU_NODE_CTRL30,TCU_NODE_CTRL30"
hexmask.long 0x78 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x78 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x78 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x78 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x7C "TCU_NODE_CTRL31,TCU_NODE_CTRL31"
hexmask.long 0x7C 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x7C 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x7C 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x7C 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x80 "TCU_NODE_CTRL32,TCU_NODE_CTRL32"
hexmask.long 0x80 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x80 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x80 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x80 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x84 "TCU_NODE_CTRL33,TCU_NODE_CTRL33"
hexmask.long 0x84 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x84 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x84 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x84 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x88 "TCU_NODE_CTRL34,TCU_NODE_CTRL34"
hexmask.long 0x88 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x88 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x88 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x88 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x8C "TCU_NODE_CTRL35,TCU_NODE_CTRL35"
hexmask.long 0x8C 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x8C 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x8C 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x8C 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x90 "TCU_NODE_CTRL36,TCU_NODE_CTRL36"
hexmask.long 0x90 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x90 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x90 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x90 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x94 "TCU_NODE_CTRL37,TCU_NODE_CTRL37"
hexmask.long 0x94 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x94 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x94 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x94 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x98 "TCU_NODE_CTRL38,TCU_NODE_CTRL38"
hexmask.long 0x98 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x98 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x98 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x98 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0x9C "TCU_NODE_CTRL39,TCU_NODE_CTRL39"
hexmask.long 0x9C 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0x9C 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0x9C 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x9C 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xA0 "TCU_NODE_CTRL40,TCU_NODE_CTRL40"
hexmask.long 0xA0 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xA0 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xA0 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xA0 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xA4 "TCU_NODE_CTRL41,TCU_NODE_CTRL41"
hexmask.long 0xA4 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xA4 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xA4 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xA4 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xA8 "TCU_NODE_CTRL42,TCU_NODE_CTRL42"
hexmask.long 0xA8 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xA8 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xA8 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xA8 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xAC "TCU_NODE_CTRL43,TCU_NODE_CTRL43"
hexmask.long 0xAC 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xAC 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xAC 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xAC 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xB0 "TCU_NODE_CTRL44,TCU_NODE_CTRL44"
hexmask.long 0xB0 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xB0 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xB0 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xB0 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xB4 "TCU_NODE_CTRL45,TCU_NODE_CTRL45"
hexmask.long 0xB4 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xB4 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xB4 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xB4 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xB8 "TCU_NODE_CTRL46,TCU_NODE_CTRL46"
hexmask.long 0xB8 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xB8 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xB8 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xB8 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xBC "TCU_NODE_CTRL47,TCU_NODE_CTRL47"
hexmask.long 0xBC 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xBC 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xBC 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xBC 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xC0 "TCU_NODE_CTRL48,TCU_NODE_CTRL48"
hexmask.long 0xC0 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xC0 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xC0 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xC0 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xC4 "TCU_NODE_CTRL49,TCU_NODE_CTRL49"
hexmask.long 0xC4 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xC4 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xC4 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xC4 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xC8 "TCU_NODE_CTRL50,TCU_NODE_CTRL50"
hexmask.long 0xC8 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xC8 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xC8 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xC8 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xCC "TCU_NODE_CTRL51,TCU_NODE_CTRL51"
hexmask.long 0xCC 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xCC 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xCC 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xCC 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xD0 "TCU_NODE_CTRL52,TCU_NODE_CTRL52"
hexmask.long 0xD0 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xD0 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xD0 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xD0 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xD4 "TCU_NODE_CTRL53,TCU_NODE_CTRL53"
hexmask.long 0xD4 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xD4 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xD4 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xD4 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xD8 "TCU_NODE_CTRL54,TCU_NODE_CTRL54"
hexmask.long 0xD8 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xD8 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xD8 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xD8 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xDC "TCU_NODE_CTRL55,TCU_NODE_CTRL55"
hexmask.long 0xDC 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xDC 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xDC 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xDC 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xE0 "TCU_NODE_CTRL56,TCU_NODE_CTRL56"
hexmask.long 0xE0 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xE0 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xE0 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xE0 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xE4 "TCU_NODE_CTRL57,TCU_NODE_CTRL57"
hexmask.long 0xE4 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xE4 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xE4 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xE4 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xE8 "TCU_NODE_CTRL58,TCU_NODE_CTRL58"
hexmask.long 0xE8 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xE8 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xE8 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xE8 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xEC "TCU_NODE_CTRL59,TCU_NODE_CTRL59"
hexmask.long 0xEC 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xEC 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xEC 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xEC 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xF0 "TCU_NODE_CTRL60,TCU_NODE_CTRL60"
hexmask.long 0xF0 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xF0 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xF0 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xF0 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
line.long 0xF4 "TCU_NODE_CTRL61,TCU_NODE_CTRL61"
hexmask.long 0xF4 5.--31. 1. "Reserved_31_5,Reserved_31_5"
bitfld.long 0xF4 4. "DIS_DVM,Disable DVM. When this bit is set to 1  the corresponding node does not participate in DVM invalidation. Set this bit to 1 to improve performance if the node is slow to respond to invalidations issued over DTI." "0,1"
rbitfld.long 0xF4 2.--3. "Reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0xF4 0.--1. "PRI_LEVEL,Priority level. This field indicates the priority level of the corresponding node. Translation requests from a node with a higher priority level are normally progressed before those from a node with a lower priority level." "0,1,2,3"
rgroup.long 0x9400++0xF7
line.long 0x0 "TCU_NODE_STATUS0,TCU_NODE_STATUS0"
hexmask.long 0x0 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x0 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x0 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x4 "TCU_NODE_STATUS1,TCU_NODE_STATUS1"
hexmask.long 0x4 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x4 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x4 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x8 "TCU_NODE_STATUS2,TCU_NODE_STATUS2"
hexmask.long 0x8 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x8 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x8 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xC "TCU_NODE_STATUS3,TCU_NODE_STATUS3"
hexmask.long 0xC 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xC 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xC 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x10 "TCU_NODE_STATUS4,TCU_NODE_STATUS4"
hexmask.long 0x10 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x10 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x10 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x14 "TCU_NODE_STATUS5,TCU_NODE_STATUS5"
hexmask.long 0x14 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x14 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x14 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x18 "TCU_NODE_STATUS6,TCU_NODE_STATUS6"
hexmask.long 0x18 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x18 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x18 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x1C "TCU_NODE_STATUS7,TCU_NODE_STATUS7"
hexmask.long 0x1C 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x1C 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x1C 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x20 "TCU_NODE_STATUS8,TCU_NODE_STATUS8"
hexmask.long 0x20 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x20 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x20 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x24 "TCU_NODE_STATUS9,TCU_NODE_STATUS9"
hexmask.long 0x24 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x24 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x24 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x28 "TCU_NODE_STATUS10,TCU_NODE_STATUS10"
hexmask.long 0x28 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x28 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x28 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x2C "TCU_NODE_STATUS11,TCU_NODE_STATUS11"
hexmask.long 0x2C 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x2C 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x2C 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x30 "TCU_NODE_STATUS12,TCU_NODE_STATUS12"
hexmask.long 0x30 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x30 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x30 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x34 "TCU_NODE_STATUS13,TCU_NODE_STATUS13"
hexmask.long 0x34 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x34 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x34 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x38 "TCU_NODE_STATUS14,TCU_NODE_STATUS14"
hexmask.long 0x38 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x38 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x38 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x3C "TCU_NODE_STATUS15,TCU_NODE_STATUS15"
hexmask.long 0x3C 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x3C 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x3C 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x40 "TCU_NODE_STATUS16,TCU_NODE_STATUS16"
hexmask.long 0x40 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x40 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x40 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x44 "TCU_NODE_STATUS17,TCU_NODE_STATUS17"
hexmask.long 0x44 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x44 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x44 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x48 "TCU_NODE_STATUS18,TCU_NODE_STATUS18"
hexmask.long 0x48 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x48 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x48 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x4C "TCU_NODE_STATUS19,TCU_NODE_STATUS19"
hexmask.long 0x4C 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x4C 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x4C 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x50 "TCU_NODE_STATUS20,TCU_NODE_STATUS20"
hexmask.long 0x50 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x50 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x50 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x54 "TCU_NODE_STATUS21,TCU_NODE_STATUS21"
hexmask.long 0x54 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x54 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x54 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x58 "TCU_NODE_STATUS22,TCU_NODE_STATUS22"
hexmask.long 0x58 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x58 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x58 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x5C "TCU_NODE_STATUS23,TCU_NODE_STATUS23"
hexmask.long 0x5C 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x5C 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x5C 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x60 "TCU_NODE_STATUS24,TCU_NODE_STATUS24"
hexmask.long 0x60 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x60 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x60 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x64 "TCU_NODE_STATUS25,TCU_NODE_STATUS25"
hexmask.long 0x64 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x64 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x64 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x68 "TCU_NODE_STATUS26,TCU_NODE_STATUS26"
hexmask.long 0x68 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x68 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x68 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x6C "TCU_NODE_STATUS27,TCU_NODE_STATUS27"
hexmask.long 0x6C 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x6C 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x6C 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x70 "TCU_NODE_STATUS28,TCU_NODE_STATUS28"
hexmask.long 0x70 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x70 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x70 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x74 "TCU_NODE_STATUS29,TCU_NODE_STATUS29"
hexmask.long 0x74 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x74 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x74 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x78 "TCU_NODE_STATUS30,TCU_NODE_STATUS30"
hexmask.long 0x78 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x78 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x78 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x7C "TCU_NODE_STATUS31,TCU_NODE_STATUS31"
hexmask.long 0x7C 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x7C 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x7C 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x80 "TCU_NODE_STATUS32,TCU_NODE_STATUS32"
hexmask.long 0x80 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x80 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x80 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x84 "TCU_NODE_STATUS33,TCU_NODE_STATUS33"
hexmask.long 0x84 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x84 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x84 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x88 "TCU_NODE_STATUS34,TCU_NODE_STATUS34"
hexmask.long 0x88 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x88 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x88 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x8C "TCU_NODE_STATUS35,TCU_NODE_STATUS35"
hexmask.long 0x8C 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x8C 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x8C 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x90 "TCU_NODE_STATUS36,TCU_NODE_STATUS36"
hexmask.long 0x90 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x90 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x90 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x94 "TCU_NODE_STATUS37,TCU_NODE_STATUS37"
hexmask.long 0x94 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x94 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x94 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x98 "TCU_NODE_STATUS38,TCU_NODE_STATUS38"
hexmask.long 0x98 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x98 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x98 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0x9C "TCU_NODE_STATUS39,TCU_NODE_STATUS39"
hexmask.long 0x9C 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0x9C 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0x9C 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xA0 "TCU_NODE_STATUS40,TCU_NODE_STATUS40"
hexmask.long 0xA0 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xA0 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xA0 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xA4 "TCU_NODE_STATUS41,TCU_NODE_STATUS41"
hexmask.long 0xA4 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xA4 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xA4 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xA8 "TCU_NODE_STATUS42,TCU_NODE_STATUS42"
hexmask.long 0xA8 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xA8 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xA8 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xAC "TCU_NODE_STATUS43,TCU_NODE_STATUS43"
hexmask.long 0xAC 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xAC 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xAC 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xB0 "TCU_NODE_STATUS44,TCU_NODE_STATUS44"
hexmask.long 0xB0 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xB0 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xB0 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xB4 "TCU_NODE_STATUS45,TCU_NODE_STATUS45"
hexmask.long 0xB4 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xB4 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xB4 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xB8 "TCU_NODE_STATUS46,TCU_NODE_STATUS46"
hexmask.long 0xB8 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xB8 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xB8 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xBC "TCU_NODE_STATUS47,TCU_NODE_STATUS47"
hexmask.long 0xBC 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xBC 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xBC 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xC0 "TCU_NODE_STATUS48,TCU_NODE_STATUS48"
hexmask.long 0xC0 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xC0 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xC0 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xC4 "TCU_NODE_STATUS49,TCU_NODE_STATUS49"
hexmask.long 0xC4 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xC4 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xC4 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xC8 "TCU_NODE_STATUS50,TCU_NODE_STATUS50"
hexmask.long 0xC8 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xC8 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xC8 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xCC "TCU_NODE_STATUS51,TCU_NODE_STATUS51"
hexmask.long 0xCC 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xCC 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xCC 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xD0 "TCU_NODE_STATUS52,TCU_NODE_STATUS52"
hexmask.long 0xD0 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xD0 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xD0 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xD4 "TCU_NODE_STATUS53,TCU_NODE_STATUS53"
hexmask.long 0xD4 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xD4 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xD4 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xD8 "TCU_NODE_STATUS54,TCU_NODE_STATUS54"
hexmask.long 0xD8 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xD8 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xD8 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xDC "TCU_NODE_STATUS55,TCU_NODE_STATUS55"
hexmask.long 0xDC 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xDC 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xDC 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xE0 "TCU_NODE_STATUS56,TCU_NODE_STATUS56"
hexmask.long 0xE0 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xE0 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xE0 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xE4 "TCU_NODE_STATUS57,TCU_NODE_STATUS57"
hexmask.long 0xE4 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xE4 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xE4 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xE8 "TCU_NODE_STATUS58,TCU_NODE_STATUS58"
hexmask.long 0xE8 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xE8 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xE8 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xEC "TCU_NODE_STATUS59,TCU_NODE_STATUS59"
hexmask.long 0xEC 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xEC 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xEC 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xF0 "TCU_NODE_STATUS60,TCU_NODE_STATUS60"
hexmask.long 0xF0 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xF0 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xF0 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
line.long 0xF4 "TCU_NODE_STATUS61,TCU_NODE_STATUS61"
hexmask.long 0xF4 2.--31. 1. "Reserved_31_2,Reserved_31_2"
bitfld.long 0xF4 1. "ATS,ATS implemented.When this bit is set to 0  the corresponding node is a TBU that is connected to the TCU using the DTI-TBU protocol.When this bit is set to 1  the corresponding node is a PCIe Root Complex that supports ATS  and is connected to the TCU.." "0,1"
bitfld.long 0xF4 0. "CONNECTED,DTI link connected.When this bit is set to 0  the DTI link for the corresponding node is not connected.When this bit is set to 1  the DTI link for the corresponding node is connected.If a DTI link is not connected  accesses to TBU registers are.." "0,1"
group.long 0x100A8++0x7
line.long 0x0 "SMMU_EVENTQ_PROD,SMMU_EVENTQ_PROD"
bitfld.long 0x0 31. "OVFLG,OVFLG" "0,1"
hexmask.long.word 0x0 20.--30. 1. "Reserved_30_20,Reserved_30_20"
hexmask.long.tbyte 0x0 0.--19. 1. "WR,WR"
line.long 0x4 "SMMU_EVENTQ_CONS,SMMU_EVENTQ_CONS"
bitfld.long 0x4 31. "OVACKFLG,OVACKFLG" "0,1"
hexmask.long.word 0x4 20.--30. 1. "Reserved_30_20,Reserved_30_20"
hexmask.long.tbyte 0x4 0.--19. 1. "RD,RD"
group.long 0x100C8++0x7
line.long 0x0 "SMMU_PRIQ_PROD,SMMU_PRIQ_PROD"
bitfld.long 0x0 31. "OVFLG,OVFLG" "0,1"
hexmask.long.word 0x0 20.--30. 1. "Reserved_30_20,Reserved_30_20"
hexmask.long.tbyte 0x0 0.--19. 1. "WR,WR"
line.long 0x4 "SMMU_PRIQ_CONS,SMMU_PRIQ_CONS"
bitfld.long 0x4 31. "OVACKFLG,OVACKFLG" "0,1"
hexmask.long.word 0x4 20.--30. 1. "Reserved_30_20,Reserved_30_20"
hexmask.long.tbyte 0x4 0.--19. 1. "RD,RD"
group.long 0x22000++0xF
line.long 0x0 "SMMU_PMCG_EVCNTR0,SMMU_PMCG_EVCNTR0"
hexmask.long 0x0 0.--31. 1. "COUNTER_VALUE,COUNTER_VALUE"
line.long 0x4 "SMMU_PMCG_EVCNTR1,SMMU_PMCG_EVCNTR1"
hexmask.long 0x4 0.--31. 1. "COUNTER_VALUE,COUNTER_VALUE"
line.long 0x8 "SMMU_PMCG_EVCNTR2,SMMU_PMCG_EVCNTR2"
hexmask.long 0x8 0.--31. 1. "COUNTER_VALUE,COUNTER_VALUE"
line.long 0xC "SMMU_PMCG_EVCNTR3,SMMU_PMCG_EVCNTR3"
hexmask.long 0xC 0.--31. 1. "COUNTER_VALUE,COUNTER_VALUE"
rgroup.long 0x22600++0xF
line.long 0x0 "SMMU_PMCG_SVR0,SMMU_PMCG_SVR0"
hexmask.long 0x0 0.--31. 1. "SHADOW_COUNTER_VALUE,SHADOW_COUNTER_VALUE"
line.long 0x4 "SMMU_PMCG_SVR1,SMMU_PMCG_SVR1"
hexmask.long 0x4 0.--31. 1. "SHADOW_COUNTER_VALUE,SHADOW_COUNTER_VALUE"
line.long 0x8 "SMMU_PMCG_SVR2,SMMU_PMCG_SVR2"
hexmask.long 0x8 0.--31. 1. "SHADOW_COUNTER_VALUE,SHADOW_COUNTER_VALUE"
line.long 0xC "SMMU_PMCG_SVR3,SMMU_PMCG_SVR3"
hexmask.long 0xC 0.--31. 1. "SHADOW_COUNTER_VALUE,SHADOW_COUNTER_VALUE"
group.long 0x22C80++0x3
line.long 0x0 "SMMU_PMCG_OVSCLR0,SMMU_PMCG_OVSCLR0"
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved_31_4"
hexmask.long.byte 0x0 0.--3. 1. "OVS,OVS"
group.long 0x22CC0++0x3
line.long 0x0 "SMMU_PMCG_OVSSET0,SMMU_PMCG_OVSSET0"
hexmask.long 0x0 4.--31. 1. "Reserved_31_4,Reserved_31_4"
hexmask.long.byte 0x0 0.--3. 1. "OVS,OVS"
group.long 0x22D88++0x3
line.long 0x0 "SMMU_PMCG_CAPR,SMMU_PMCG_CAPR"
hexmask.long 0x0 1.--31. 1. "Reserved_31_1,Reserved_31_1"
bitfld.long 0x0 0. "CAPTURE,CAPTURE" "0,1"
tree.end
tree "SPI (SPI Controller)"
base ad:0x0
tree "SPIM_0"
base ad:0x10DA4000
group.long 0x0++0x1F
line.long 0x0 "CTRLR0,Control Register 0:"
hexmask.long.word 0x0 23.--31. 1. "RSVD_CTRLR0,Reserved bits - Read Only"
newline
rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format:" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode."
newline
hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the"
newline
bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally" "0,1"
newline
rbitfld.long 0x0 10. "RSVD_SLV_OE,Reserved field- Read-only" "0,1"
newline
bitfld.long 0x0 8.--9. "TMOD,Transfer Mode." "0,1,2,3"
newline
bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity." "0,1"
newline
bitfld.long 0x0 6. "SCPH,Serial Clock Phase." "0: Serial clock toggles in middle of first data bit,1: Serial clock toggles at start of first data bit"
newline
bitfld.long 0x0 4.--5. "FRF,Frame Format." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is"
line.long 0x4 "CTRLR1,Control Register 1"
hexmask.long.word 0x4 16.--31. 1. "RSVD_CTRLR1,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--15. 1. "NDF,Number of Data Frames."
line.long 0x8 "SSIENR,SSI Enable Register"
hexmask.long 0x8 1.--31. 1. "RSVD_SSIENR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When" "0,1"
line.long 0xC "MWCR,Microwire Control Register."
hexmask.long 0xC 3.--31. 1. "RSVD_MWCR,Reserved bits - Read Only"
newline
bitfld.long 0xC 2. "MHS,Microwire Handshaking." "0: handshaking interface is disabled,1: handshaking interface is enabled"
newline
bitfld.long 0xC 1. "MDD,Microwire Control." "0,1"
newline
bitfld.long 0xC 0. "MWMOD,Microwire Transfer Mode." "0: non-sequential transfer,1: sequential transfer"
line.long 0x10 "SER,Slave Enable Register."
hexmask.long 0x10 4.--31. 1. "RSVD_SER,Reserved bits - Read Only"
newline
hexmask.long.byte 0x10 0.--3. 1. "SER,Slave Select Enable Flag."
line.long 0x14 "BAUDR,Baud Rate Select."
hexmask.long.word 0x14 16.--31. 1. "RSVD_BAUDR,Reserved bits - Read Only"
newline
hexmask.long.word 0x14 0.--15. 1. "SCKDV,SSI Clock Divider."
line.long 0x18 "TXFTLR,Transmit FIFO Threshold Level."
hexmask.long.tbyte 0x18 8.--31. 1. "RSVD_TXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x18 0.--7. 1. "TFT,Transmit FIFO Threshold."
line.long 0x1C "RXFTLR,Receive FIFO Threshold level."
hexmask.long.tbyte 0x1C 8.--31. 1. "RSVD_RXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x1C 0.--7. 1. "RFT,Receive FIFO Threshold."
rgroup.long 0x20++0xB
line.long 0x0 "TXFLR,Transmit FIFO Level Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x0 0.--8. 1. "TXTFL,Transmit FIFO Level."
line.long 0x4 "RXFLR,Receive FIFO Level Register"
hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--8. 1. "RXTFL,Receive FIFO Level."
line.long 0x8 "SR,Status Register."
hexmask.long 0x8 7.--31. 1. "RSVD_SR,Reserved bits - Read Only"
newline
bitfld.long 0x8 6. "DCOL,Data Collision Error." "0,1"
newline
bitfld.long 0x8 5. "RSVD_TXE,Reserved field- read-only" "0,1"
newline
bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full  this bit" "0,1"
newline
bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty." "0,1"
newline
bitfld.long 0x8 2. "TFE,Transmit FIFO Empty." "0,1"
newline
bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more" "0,1"
newline
bitfld.long 0x8 0. "BUSY,SSI Busy Flag." "0,1"
group.long 0x2C++0x3
line.long 0x0 "IMR,Interrupt Mask Register"
hexmask.long 0x0 6.--31. 1. "RSVD_IMR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "MSTIM,Multi-Master Contention Interrupt Mask. This bit field is not present if" "0,1"
newline
bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
rgroup.long 0x30++0x1B
line.long 0x0 "ISR,Interrupt Status Register"
hexmask.long 0x0 6.--31. 1. "RSVD_ISR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "MSTIS,Multi-Master Contention Interrupt Status. This bit field is not present" "0: ssi_mst_intr interrupt not active after masking,1: ssi_mst_intr interrupt is active after masking"
newline
bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status" "0: ssi_rxf_intr interrupt is not active after masking,1: ssi_rxf_intr interrupt is full after masking"
newline
bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status" "0: ssi_rxo_intr interrupt is not active after masking,1: ssi_rxo_intr interrupt is active after masking"
newline
bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status" "0: ssi_rxu_intr interrupt is not active after masking,1: ssi_rxu_intr interrupt is active after masking"
newline
bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status" "0: ssi_txo_intr interrupt is not active after masking,1: ssi_txo_intr interrupt is active after masking"
newline
bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status" "0: ssi_txe_intr interrupt is not active after masking,1: ssi_txe_intr interrupt is active after masking"
line.long 0x4 "RISR,Raw Interrupt Status Register"
hexmask.long 0x4 6.--31. 1. "RSVD_RISR,Reserved bits - Read Only"
newline
bitfld.long 0x4 5. "MSTIR,Multi-Master Contention Raw Interrupt Status." "0: ssi_mst_intr interrupt is not active prior to..,1: ssi_mst_intr interrupt is active prior masking"
newline
bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status" "0: ssi_rxf_intr interrupt is not active prior to..,1: ssi_rxf_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status" "0: ssi_rxo_intr interrupt is not active prior to..,1: ssi_rxo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status" "0: ssi_rxu_intr interrupt is not active prior to..,1: ssi_rxu_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status" "0: ssi_txo_intr interrupt is not active prior to..,1: ssi_txo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status" "0: ssi_txe_intr interrupt is not active prior to..,1: ssi_txe_intr interrupt is active prior masking"
line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register"
hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt." "0,1"
line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register"
hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt." "0,1"
line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register"
hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt." "0,1"
line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register"
hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt." "0,1"
line.long 0x18 "ICR,Interrupt Clear Register"
hexmask.long 0x18 1.--31. 1. "RSVD_ICR,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "ICR,Clear Interrupts." "0,1"
group.long 0x4C++0xB
line.long 0x0 "DMACR,DMA Control Register."
hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,Reserved bits - Read Only"
newline
bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x0 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x4 "DMATDLR,DMA Transmit Data Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_DMATDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "DMATDL,Transmit Data Level."
line.long 0x8 "DMARDLR,DMA Receive Data Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_DMARDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--7. 1. "DMARDL,Receive Data Level."
rgroup.long 0x58++0x7
line.long 0x0 "IDR,Identification Register."
hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code  which is written into the register at configuration time using CoreConsultant."
line.long 0x4 "SSI_VERSION_ID,coreKit Version ID Register"
hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version  followed by *. For example 32_30_31_2A represents the version 2.01*."
group.long 0x60++0x93
line.long 0x0 "DR0,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x0 0.--31. 1. "dr0,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4 "DR1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4 0.--31. 1. "dr1,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8 "DR2,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8 0.--31. 1. "dr2,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0xC "DR3,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0xC 0.--31. 1. "dr3,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x10 "DR4,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x10 0.--31. 1. "dr4,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x14 "DR5,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x14 0.--31. 1. "dr5,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x18 "DR6,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x18 0.--31. 1. "dr6,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x1C "DR7,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x1C 0.--31. 1. "dr7,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x20 "DR8,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x20 0.--31. 1. "dr8,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x24 "DR9,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x24 0.--31. 1. "dr9,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x28 "DR10,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x28 0.--31. 1. "dr10,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x2C "DR11,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x2C 0.--31. 1. "dr11,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x30 "DR12,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x30 0.--31. 1. "dr12,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x34 "DR13,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x34 0.--31. 1. "dr13,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x38 "DR14,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x38 0.--31. 1. "dr14,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x3C "DR15,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x3C 0.--31. 1. "dr15,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x40 "DR16,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x40 0.--31. 1. "dr16,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x44 "DR17,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x44 0.--31. 1. "dr17,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x48 "DR18,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x48 0.--31. 1. "dr18,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4C "DR19,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4C 0.--31. 1. "dr19,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x50 "DR20,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x50 0.--31. 1. "dr20,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x54 "DR21,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x54 0.--31. 1. "dr21,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x58 "DR22,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x58 0.--31. 1. "dr22,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x5C "DR23,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x5C 0.--31. 1. "dr23,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x60 "DR24,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x60 0.--31. 1. "dr24,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x64 "DR25,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x64 0.--31. 1. "dr25,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x68 "DR26,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x68 0.--31. 1. "dr26,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x6C "DR27,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x6C 0.--31. 1. "dr27,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x70 "DR28,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x70 0.--31. 1. "dr28,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x74 "DR29,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x74 0.--31. 1. "dr29,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x78 "DR30,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x78 0.--31. 1. "dr30,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x7C "DR31,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x7C 0.--31. 1. "dr31,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x80 "DR32,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x80 0.--31. 1. "dr32,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x84 "DR33,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x84 0.--31. 1. "dr33,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x88 "DR34,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x88 0.--31. 1. "dr34,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8C "DR35,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8C 0.--31. 1. "dr35,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x90 "RX_SAMPLE_DLY,RX Sample Delay."
hexmask.long.tbyte 0x90 8.--31. 1. "RSVD_RX_SAMPLE_DLY,Reserved bits - Read Only"
newline
hexmask.long.byte 0x90 0.--7. 1. "RSD,Rxd Sample Delay."
rgroup.long 0xF8++0x7
line.long 0x0 "RSVD_1,RSVD_1 - Reserved address location"
hexmask.long 0x0 0.--31. 1. "RSVD1,Reserved address location"
line.long 0x4 "RSVD_2,RSVD_2 - Reserved address location"
hexmask.long 0x4 0.--31. 1. "RSVD2,Reserved address location"
tree.end
tree "SPIM_1"
base ad:0x10DA5000
group.long 0x0++0x1F
line.long 0x0 "CTRLR0,Control Register 0:"
hexmask.long.word 0x0 23.--31. 1. "RSVD_CTRLR0,Reserved bits - Read Only"
newline
rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format:" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode."
newline
hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the"
newline
bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally" "0,1"
newline
rbitfld.long 0x0 10. "RSVD_SLV_OE,Reserved field- Read-only" "0,1"
newline
bitfld.long 0x0 8.--9. "TMOD,Transfer Mode." "0,1,2,3"
newline
bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity." "0,1"
newline
bitfld.long 0x0 6. "SCPH,Serial Clock Phase." "0: Serial clock toggles in middle of first data bit,1: Serial clock toggles at start of first data bit"
newline
bitfld.long 0x0 4.--5. "FRF,Frame Format." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is"
line.long 0x4 "CTRLR1,Control Register 1"
hexmask.long.word 0x4 16.--31. 1. "RSVD_CTRLR1,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--15. 1. "NDF,Number of Data Frames."
line.long 0x8 "SSIENR,SSI Enable Register"
hexmask.long 0x8 1.--31. 1. "RSVD_SSIENR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When" "0,1"
line.long 0xC "MWCR,Microwire Control Register."
hexmask.long 0xC 3.--31. 1. "RSVD_MWCR,Reserved bits - Read Only"
newline
bitfld.long 0xC 2. "MHS,Microwire Handshaking." "0: handshaking interface is disabled,1: handshaking interface is enabled"
newline
bitfld.long 0xC 1. "MDD,Microwire Control." "0,1"
newline
bitfld.long 0xC 0. "MWMOD,Microwire Transfer Mode." "0: non-sequential transfer,1: sequential transfer"
line.long 0x10 "SER,Slave Enable Register."
hexmask.long 0x10 4.--31. 1. "RSVD_SER,Reserved bits - Read Only"
newline
hexmask.long.byte 0x10 0.--3. 1. "SER,Slave Select Enable Flag."
line.long 0x14 "BAUDR,Baud Rate Select."
hexmask.long.word 0x14 16.--31. 1. "RSVD_BAUDR,Reserved bits - Read Only"
newline
hexmask.long.word 0x14 0.--15. 1. "SCKDV,SSI Clock Divider."
line.long 0x18 "TXFTLR,Transmit FIFO Threshold Level."
hexmask.long.tbyte 0x18 8.--31. 1. "RSVD_TXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x18 0.--7. 1. "TFT,Transmit FIFO Threshold."
line.long 0x1C "RXFTLR,Receive FIFO Threshold level."
hexmask.long.tbyte 0x1C 8.--31. 1. "RSVD_RXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x1C 0.--7. 1. "RFT,Receive FIFO Threshold."
rgroup.long 0x20++0xB
line.long 0x0 "TXFLR,Transmit FIFO Level Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x0 0.--8. 1. "TXTFL,Transmit FIFO Level."
line.long 0x4 "RXFLR,Receive FIFO Level Register"
hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--8. 1. "RXTFL,Receive FIFO Level."
line.long 0x8 "SR,Status Register."
hexmask.long 0x8 7.--31. 1. "RSVD_SR,Reserved bits - Read Only"
newline
bitfld.long 0x8 6. "DCOL,Data Collision Error." "0,1"
newline
bitfld.long 0x8 5. "RSVD_TXE,Reserved field- read-only" "0,1"
newline
bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full  this bit" "0,1"
newline
bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty." "0,1"
newline
bitfld.long 0x8 2. "TFE,Transmit FIFO Empty." "0,1"
newline
bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more" "0,1"
newline
bitfld.long 0x8 0. "BUSY,SSI Busy Flag." "0,1"
group.long 0x2C++0x3
line.long 0x0 "IMR,Interrupt Mask Register"
hexmask.long 0x0 6.--31. 1. "RSVD_IMR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "MSTIM,Multi-Master Contention Interrupt Mask. This bit field is not present if" "0,1"
newline
bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
rgroup.long 0x30++0x1B
line.long 0x0 "ISR,Interrupt Status Register"
hexmask.long 0x0 6.--31. 1. "RSVD_ISR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "MSTIS,Multi-Master Contention Interrupt Status. This bit field is not present" "0: ssi_mst_intr interrupt not active after masking,1: ssi_mst_intr interrupt is active after masking"
newline
bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status" "0: ssi_rxf_intr interrupt is not active after masking,1: ssi_rxf_intr interrupt is full after masking"
newline
bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status" "0: ssi_rxo_intr interrupt is not active after masking,1: ssi_rxo_intr interrupt is active after masking"
newline
bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status" "0: ssi_rxu_intr interrupt is not active after masking,1: ssi_rxu_intr interrupt is active after masking"
newline
bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status" "0: ssi_txo_intr interrupt is not active after masking,1: ssi_txo_intr interrupt is active after masking"
newline
bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status" "0: ssi_txe_intr interrupt is not active after masking,1: ssi_txe_intr interrupt is active after masking"
line.long 0x4 "RISR,Raw Interrupt Status Register"
hexmask.long 0x4 6.--31. 1. "RSVD_RISR,Reserved bits - Read Only"
newline
bitfld.long 0x4 5. "MSTIR,Multi-Master Contention Raw Interrupt Status." "0: ssi_mst_intr interrupt is not active prior to..,1: ssi_mst_intr interrupt is active prior masking"
newline
bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status" "0: ssi_rxf_intr interrupt is not active prior to..,1: ssi_rxf_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status" "0: ssi_rxo_intr interrupt is not active prior to..,1: ssi_rxo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status" "0: ssi_rxu_intr interrupt is not active prior to..,1: ssi_rxu_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status" "0: ssi_txo_intr interrupt is not active prior to..,1: ssi_txo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status" "0: ssi_txe_intr interrupt is not active prior to..,1: ssi_txe_intr interrupt is active prior masking"
line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register"
hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt." "0,1"
line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register"
hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt." "0,1"
line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register"
hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt." "0,1"
line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register"
hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt." "0,1"
line.long 0x18 "ICR,Interrupt Clear Register"
hexmask.long 0x18 1.--31. 1. "RSVD_ICR,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "ICR,Clear Interrupts." "0,1"
group.long 0x4C++0xB
line.long 0x0 "DMACR,DMA Control Register."
hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,Reserved bits - Read Only"
newline
bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x0 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x4 "DMATDLR,DMA Transmit Data Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_DMATDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "DMATDL,Transmit Data Level."
line.long 0x8 "DMARDLR,DMA Receive Data Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_DMARDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--7. 1. "DMARDL,Receive Data Level."
rgroup.long 0x58++0x7
line.long 0x0 "IDR,Identification Register."
hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code  which is written into the register at configuration time using CoreConsultant."
line.long 0x4 "SSI_VERSION_ID,coreKit Version ID Register"
hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version  followed by *. For example 32_30_31_2A represents the version 2.01*."
group.long 0x60++0x93
line.long 0x0 "DR0,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x0 0.--31. 1. "dr0,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4 "DR1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4 0.--31. 1. "dr1,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8 "DR2,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8 0.--31. 1. "dr2,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0xC "DR3,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0xC 0.--31. 1. "dr3,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x10 "DR4,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x10 0.--31. 1. "dr4,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x14 "DR5,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x14 0.--31. 1. "dr5,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x18 "DR6,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x18 0.--31. 1. "dr6,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x1C "DR7,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x1C 0.--31. 1. "dr7,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x20 "DR8,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x20 0.--31. 1. "dr8,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x24 "DR9,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x24 0.--31. 1. "dr9,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x28 "DR10,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x28 0.--31. 1. "dr10,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x2C "DR11,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x2C 0.--31. 1. "dr11,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x30 "DR12,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x30 0.--31. 1. "dr12,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x34 "DR13,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x34 0.--31. 1. "dr13,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x38 "DR14,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x38 0.--31. 1. "dr14,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x3C "DR15,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x3C 0.--31. 1. "dr15,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x40 "DR16,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x40 0.--31. 1. "dr16,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x44 "DR17,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x44 0.--31. 1. "dr17,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x48 "DR18,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x48 0.--31. 1. "dr18,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4C "DR19,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4C 0.--31. 1. "dr19,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x50 "DR20,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x50 0.--31. 1. "dr20,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x54 "DR21,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x54 0.--31. 1. "dr21,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x58 "DR22,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x58 0.--31. 1. "dr22,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x5C "DR23,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x5C 0.--31. 1. "dr23,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x60 "DR24,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x60 0.--31. 1. "dr24,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x64 "DR25,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x64 0.--31. 1. "dr25,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x68 "DR26,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x68 0.--31. 1. "dr26,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x6C "DR27,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x6C 0.--31. 1. "dr27,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x70 "DR28,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x70 0.--31. 1. "dr28,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x74 "DR29,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x74 0.--31. 1. "dr29,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x78 "DR30,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x78 0.--31. 1. "dr30,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x7C "DR31,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x7C 0.--31. 1. "dr31,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x80 "DR32,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x80 0.--31. 1. "dr32,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x84 "DR33,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x84 0.--31. 1. "dr33,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x88 "DR34,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x88 0.--31. 1. "dr34,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8C "DR35,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8C 0.--31. 1. "dr35,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x90 "RX_SAMPLE_DLY,RX Sample Delay."
hexmask.long.tbyte 0x90 8.--31. 1. "RSVD_RX_SAMPLE_DLY,Reserved bits - Read Only"
newline
hexmask.long.byte 0x90 0.--7. 1. "RSD,Rxd Sample Delay."
rgroup.long 0xF8++0x7
line.long 0x0 "RSVD_1,RSVD_1 - Reserved address location"
hexmask.long 0x0 0.--31. 1. "RSVD1,Reserved address location"
line.long 0x4 "RSVD_2,RSVD_2 - Reserved address location"
hexmask.long 0x4 0.--31. 1. "RSVD2,Reserved address location"
tree.end
tree "SPIS_0"
base ad:0x10DA2000
group.long 0x0++0x3
line.long 0x0 "CTRLR0,Control Register 0:"
hexmask.long.word 0x0 23.--31. 1. "RSVD_CTRLR0,Reserved bits - Read Only"
newline
rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format:" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode."
newline
hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the"
newline
bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally" "0,1"
newline
bitfld.long 0x0 10. "SLV_OE,Slave Output Enable." "0,1"
newline
bitfld.long 0x0 8.--9. "TMOD,Transfer Mode." "0,1,2,3"
newline
bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity." "0,1"
newline
bitfld.long 0x0 6. "SCPH,Serial Clock Phase." "0: Serial clock toggles in middle of first data bit,1: Serial clock toggles at start of first data bit"
newline
bitfld.long 0x0 4.--5. "FRF,Frame Format." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is"
group.long 0x8++0x7
line.long 0x0 "SSIENR,SSI Enable Register"
hexmask.long 0x0 1.--31. 1. "RSVD_SSIENR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When" "0,1"
line.long 0x4 "MWCR,Microwire Control Register."
hexmask.long 0x4 3.--31. 1. "RSVD_MWCR,Reserved bits - Read Only"
newline
rbitfld.long 0x4 2. "RSVD_MHS,Reserved field- read-only" "0,1"
newline
bitfld.long 0x4 1. "MDD,Microwire Control." "0,1"
newline
bitfld.long 0x4 0. "MWMOD,Microwire Transfer Mode." "0: non-sequential transfer,1: sequential transfer"
group.long 0x18++0x7
line.long 0x0 "TXFTLR,Transmit FIFO Threshold Level."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "TFT,Transmit FIFO Threshold."
line.long 0x4 "RXFTLR,Receive FIFO Threshold level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_RXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "RFT,Receive FIFO Threshold."
rgroup.long 0x20++0xB
line.long 0x0 "TXFLR,Transmit FIFO Level Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x0 0.--8. 1. "TXTFL,Transmit FIFO Level."
line.long 0x4 "RXFLR,Receive FIFO Level Register"
hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--8. 1. "RXTFL,Receive FIFO Level."
line.long 0x8 "SR,Status Register."
hexmask.long 0x8 7.--31. 1. "RSVD_SR,Reserved bits - Read Only"
newline
bitfld.long 0x8 6. "RSVD_DCOL,Reserved field- read-only" "0,1"
newline
bitfld.long 0x8 5. "TXE,Transmission Error." "0,1"
newline
bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full  this bit" "0,1"
newline
bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty." "0,1"
newline
bitfld.long 0x8 2. "TFE,Transmit FIFO Empty." "0,1"
newline
bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more" "0,1"
newline
bitfld.long 0x8 0. "BUSY,SSI Busy Flag." "0,1"
group.long 0x2C++0x3
line.long 0x0 "IMR,Interrupt Mask Register"
hexmask.long 0x0 6.--31. 1. "RSVD_IMR,Reserved bits - Read Only"
newline
rbitfld.long 0x0 5. "RSVD_MSTIM,Reserved field- read-only" "0,1"
newline
bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
rgroup.long 0x30++0x1B
line.long 0x0 "ISR,Interrupt Status Register"
hexmask.long 0x0 6.--31. 1. "RSVD_ISR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "RSVD_MSTIS,Reserved field- read-only" "0,1"
newline
bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status" "0: ssi_rxf_intr interrupt is not active after masking,1: ssi_rxf_intr interrupt is full after masking"
newline
bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status" "0: ssi_rxo_intr interrupt is not active after masking,1: ssi_rxo_intr interrupt is active after masking"
newline
bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status" "0: ssi_rxu_intr interrupt is not active after masking,1: ssi_rxu_intr interrupt is active after masking"
newline
bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status" "0: ssi_txo_intr interrupt is not active after masking,1: ssi_txo_intr interrupt is active after masking"
newline
bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status" "0: ssi_txe_intr interrupt is not active after masking,1: ssi_txe_intr interrupt is active after masking"
line.long 0x4 "RISR,Raw Interrupt Status Register"
hexmask.long 0x4 6.--31. 1. "RSVD_RISR,Reserved bits - Read Only"
newline
bitfld.long 0x4 5. "RSVD_MSTIR,Reserved field- read-only" "0,1"
newline
bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status" "0: ssi_rxf_intr interrupt is not active prior to..,1: ssi_rxf_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status" "0: ssi_rxo_intr interrupt is not active prior to..,1: ssi_rxo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status" "0: ssi_rxu_intr interrupt is not active prior to..,1: ssi_rxu_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status" "0: ssi_txo_intr interrupt is not active prior to..,1: ssi_txo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status" "0: ssi_txe_intr interrupt is not active prior to..,1: ssi_txe_intr interrupt is active prior masking"
line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register"
hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt." "0,1"
line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register"
hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt." "0,1"
line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register"
hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt." "0,1"
line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register"
hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt." "0,1"
line.long 0x18 "ICR,Interrupt Clear Register"
hexmask.long 0x18 1.--31. 1. "RSVD_ICR,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "ICR,Clear Interrupts." "0,1"
group.long 0x4C++0xB
line.long 0x0 "DMACR,DMA Control Register."
hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,Reserved bits - Read Only"
newline
bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x0 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x4 "DMATDLR,DMA Transmit Data Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_DMATDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "DMATDL,Transmit Data Level."
line.long 0x8 "DMARDLR,DMA Receive Data Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_DMARDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--7. 1. "DMARDL,Receive Data Level."
rgroup.long 0x58++0x7
line.long 0x0 "IDR,Identification Register."
hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code  which is written into the register at configuration time using CoreConsultant."
line.long 0x4 "SSI_VERSION_ID,coreKit Version ID Register"
hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version  followed by *. For example 32_30_31_2A represents the version 2.01*."
group.long 0x60++0x8F
line.long 0x0 "DR0,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x0 0.--31. 1. "dr0,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4 "DR1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4 0.--31. 1. "dr1,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8 "DR2,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8 0.--31. 1. "dr2,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0xC "DR3,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0xC 0.--31. 1. "dr3,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x10 "DR4,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x10 0.--31. 1. "dr4,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x14 "DR5,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x14 0.--31. 1. "dr5,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x18 "DR6,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x18 0.--31. 1. "dr6,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x1C "DR7,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x1C 0.--31. 1. "dr7,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x20 "DR8,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x20 0.--31. 1. "dr8,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x24 "DR9,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x24 0.--31. 1. "dr9,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x28 "DR10,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x28 0.--31. 1. "dr10,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x2C "DR11,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x2C 0.--31. 1. "dr11,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x30 "DR12,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x30 0.--31. 1. "dr12,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x34 "DR13,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x34 0.--31. 1. "dr13,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x38 "DR14,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x38 0.--31. 1. "dr14,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x3C "DR15,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x3C 0.--31. 1. "dr15,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x40 "DR16,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x40 0.--31. 1. "dr16,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x44 "DR17,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x44 0.--31. 1. "dr17,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x48 "DR18,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x48 0.--31. 1. "dr18,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4C "DR19,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4C 0.--31. 1. "dr19,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x50 "DR20,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x50 0.--31. 1. "dr20,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x54 "DR21,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x54 0.--31. 1. "dr21,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x58 "DR22,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x58 0.--31. 1. "dr22,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x5C "DR23,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x5C 0.--31. 1. "dr23,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x60 "DR24,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x60 0.--31. 1. "dr24,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x64 "DR25,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x64 0.--31. 1. "dr25,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x68 "DR26,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x68 0.--31. 1. "dr26,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x6C "DR27,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x6C 0.--31. 1. "dr27,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x70 "DR28,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x70 0.--31. 1. "dr28,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x74 "DR29,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x74 0.--31. 1. "dr29,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x78 "DR30,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x78 0.--31. 1. "dr30,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x7C "DR31,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x7C 0.--31. 1. "dr31,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x80 "DR32,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x80 0.--31. 1. "dr32,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x84 "DR33,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x84 0.--31. 1. "dr33,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x88 "DR34,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x88 0.--31. 1. "dr34,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8C "DR35,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8C 0.--31. 1. "dr35,Data Register. When writing to this register  you must right-justify the data. Read"
rgroup.long 0xF8++0x7
line.long 0x0 "RSVD_1,RSVD_1 - Reserved address location"
hexmask.long 0x0 0.--31. 1. "RSVD1,Reserved address location"
line.long 0x4 "RSVD_2,RSVD_2 - Reserved address location"
hexmask.long 0x4 0.--31. 1. "RSVD2,Reserved address location"
tree.end
tree "SPIS_1"
base ad:0x10DA3000
group.long 0x0++0x3
line.long 0x0 "CTRLR0,Control Register 0:"
hexmask.long.word 0x0 23.--31. 1. "RSVD_CTRLR0,Reserved bits - Read Only"
newline
rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format:" "0,1,2,3"
newline
hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode."
newline
hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the"
newline
bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally" "0,1"
newline
bitfld.long 0x0 10. "SLV_OE,Slave Output Enable." "0,1"
newline
bitfld.long 0x0 8.--9. "TMOD,Transfer Mode." "0,1,2,3"
newline
bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity." "0,1"
newline
bitfld.long 0x0 6. "SCPH,Serial Clock Phase." "0: Serial clock toggles in middle of first data bit,1: Serial clock toggles at start of first data bit"
newline
bitfld.long 0x0 4.--5. "FRF,Frame Format." "0,1,2,3"
newline
hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is"
group.long 0x8++0x7
line.long 0x0 "SSIENR,SSI Enable Register"
hexmask.long 0x0 1.--31. 1. "RSVD_SSIENR,Reserved bits - Read Only"
newline
bitfld.long 0x0 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When" "0,1"
line.long 0x4 "MWCR,Microwire Control Register."
hexmask.long 0x4 3.--31. 1. "RSVD_MWCR,Reserved bits - Read Only"
newline
rbitfld.long 0x4 2. "RSVD_MHS,Reserved field- read-only" "0,1"
newline
bitfld.long 0x4 1. "MDD,Microwire Control." "0,1"
newline
bitfld.long 0x4 0. "MWMOD,Microwire Transfer Mode." "0: non-sequential transfer,1: sequential transfer"
group.long 0x18++0x7
line.long 0x0 "TXFTLR,Transmit FIFO Threshold Level."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x0 0.--7. 1. "TFT,Transmit FIFO Threshold."
line.long 0x4 "RXFTLR,Receive FIFO Threshold level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_RXFTLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "RFT,Receive FIFO Threshold."
rgroup.long 0x20++0xB
line.long 0x0 "TXFLR,Transmit FIFO Level Register"
hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_TXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x0 0.--8. 1. "TXTFL,Transmit FIFO Level."
line.long 0x4 "RXFLR,Receive FIFO Level Register"
hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_RXFLR,Reserved bits - Read Only"
newline
hexmask.long.word 0x4 0.--8. 1. "RXTFL,Receive FIFO Level."
line.long 0x8 "SR,Status Register."
hexmask.long 0x8 7.--31. 1. "RSVD_SR,Reserved bits - Read Only"
newline
bitfld.long 0x8 6. "RSVD_DCOL,Reserved field- read-only" "0,1"
newline
bitfld.long 0x8 5. "TXE,Transmission Error." "0,1"
newline
bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full  this bit" "0,1"
newline
bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty." "0,1"
newline
bitfld.long 0x8 2. "TFE,Transmit FIFO Empty." "0,1"
newline
bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more" "0,1"
newline
bitfld.long 0x8 0. "BUSY,SSI Busy Flag." "0,1"
group.long 0x2C++0x3
line.long 0x0 "IMR,Interrupt Mask Register"
hexmask.long 0x0 6.--31. 1. "RSVD_IMR,Reserved bits - Read Only"
newline
rbitfld.long 0x0 5. "RSVD_MSTIM,Reserved field- read-only" "0,1"
newline
bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask" "0,1"
newline
bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask" "0,1"
newline
bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask" "0,1"
rgroup.long 0x30++0x1B
line.long 0x0 "ISR,Interrupt Status Register"
hexmask.long 0x0 6.--31. 1. "RSVD_ISR,Reserved bits - Read Only"
newline
bitfld.long 0x0 5. "RSVD_MSTIS,Reserved field- read-only" "0,1"
newline
bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status" "0: ssi_rxf_intr interrupt is not active after masking,1: ssi_rxf_intr interrupt is full after masking"
newline
bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status" "0: ssi_rxo_intr interrupt is not active after masking,1: ssi_rxo_intr interrupt is active after masking"
newline
bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status" "0: ssi_rxu_intr interrupt is not active after masking,1: ssi_rxu_intr interrupt is active after masking"
newline
bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status" "0: ssi_txo_intr interrupt is not active after masking,1: ssi_txo_intr interrupt is active after masking"
newline
bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status" "0: ssi_txe_intr interrupt is not active after masking,1: ssi_txe_intr interrupt is active after masking"
line.long 0x4 "RISR,Raw Interrupt Status Register"
hexmask.long 0x4 6.--31. 1. "RSVD_RISR,Reserved bits - Read Only"
newline
bitfld.long 0x4 5. "RSVD_MSTIR,Reserved field- read-only" "0,1"
newline
bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status" "0: ssi_rxf_intr interrupt is not active prior to..,1: ssi_rxf_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status" "0: ssi_rxo_intr interrupt is not active prior to..,1: ssi_rxo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status" "0: ssi_rxu_intr interrupt is not active prior to..,1: ssi_rxu_intr interrupt is active prior to masking"
newline
bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status" "0: ssi_txo_intr interrupt is not active prior to..,1: ssi_txo_intr interrupt is active prior masking"
newline
bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status" "0: ssi_txe_intr interrupt is not active prior to..,1: ssi_txe_intr interrupt is active prior masking"
line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register"
hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,Reserved bits - Read Only"
newline
bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt." "0,1"
line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register"
hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,Reserved bits - Read Only"
newline
bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt." "0,1"
line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register"
hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,Reserved bits - Read Only"
newline
bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt." "0,1"
line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register"
hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,Reserved bits - Read Only"
newline
bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt." "0,1"
line.long 0x18 "ICR,Interrupt Clear Register"
hexmask.long 0x18 1.--31. 1. "RSVD_ICR,Reserved bits - Read Only"
newline
bitfld.long 0x18 0. "ICR,Clear Interrupts." "0,1"
group.long 0x4C++0xB
line.long 0x0 "DMACR,DMA Control Register."
hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,Reserved bits - Read Only"
newline
bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable." "0: Transmit DMA disabled,1: Transmit DMA enabled"
newline
bitfld.long 0x0 0. "RDMAE,Receive DMA Enable." "0: Receive DMA disabled,1: Receive DMA enabled"
line.long 0x4 "DMATDLR,DMA Transmit Data Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_DMATDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x4 0.--7. 1. "DMATDL,Transmit Data Level."
line.long 0x8 "DMARDLR,DMA Receive Data Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_DMARDLR,Reserved bits - Read Only"
newline
hexmask.long.byte 0x8 0.--7. 1. "DMARDL,Receive Data Level."
rgroup.long 0x58++0x7
line.long 0x0 "IDR,Identification Register."
hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code  which is written into the register at configuration time using CoreConsultant."
line.long 0x4 "SSI_VERSION_ID,coreKit Version ID Register"
hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version  followed by *. For example 32_30_31_2A represents the version 2.01*."
group.long 0x60++0x8F
line.long 0x0 "DR0,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x0 0.--31. 1. "dr0,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4 "DR1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4 0.--31. 1. "dr1,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8 "DR2,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8 0.--31. 1. "dr2,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0xC "DR3,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0xC 0.--31. 1. "dr3,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x10 "DR4,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x10 0.--31. 1. "dr4,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x14 "DR5,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x14 0.--31. 1. "dr5,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x18 "DR6,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x18 0.--31. 1. "dr6,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x1C "DR7,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x1C 0.--31. 1. "dr7,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x20 "DR8,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x20 0.--31. 1. "dr8,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x24 "DR9,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x24 0.--31. 1. "dr9,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x28 "DR10,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x28 0.--31. 1. "dr10,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x2C "DR11,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x2C 0.--31. 1. "dr11,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x30 "DR12,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x30 0.--31. 1. "dr12,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x34 "DR13,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x34 0.--31. 1. "dr13,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x38 "DR14,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x38 0.--31. 1. "dr14,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x3C "DR15,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x3C 0.--31. 1. "dr15,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x40 "DR16,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x40 0.--31. 1. "dr16,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x44 "DR17,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x44 0.--31. 1. "dr17,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x48 "DR18,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x48 0.--31. 1. "dr18,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x4C "DR19,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x4C 0.--31. 1. "dr19,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x50 "DR20,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x50 0.--31. 1. "dr20,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x54 "DR21,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x54 0.--31. 1. "dr21,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x58 "DR22,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x58 0.--31. 1. "dr22,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x5C "DR23,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x5C 0.--31. 1. "dr23,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x60 "DR24,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x60 0.--31. 1. "dr24,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x64 "DR25,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x64 0.--31. 1. "dr25,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x68 "DR26,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x68 0.--31. 1. "dr26,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x6C "DR27,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x6C 0.--31. 1. "dr27,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x70 "DR28,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x70 0.--31. 1. "dr28,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x74 "DR29,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x74 0.--31. 1. "dr29,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x78 "DR30,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x78 0.--31. 1. "dr30,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x7C "DR31,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x7C 0.--31. 1. "dr31,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x80 "DR32,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x80 0.--31. 1. "dr32,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x84 "DR33,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x84 0.--31. 1. "dr33,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x88 "DR34,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x88 0.--31. 1. "dr34,Data Register. When writing to this register  you must right-justify the data. Read"
line.long 0x8C "DR35,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for"
hexmask.long 0x8C 0.--31. 1. "dr35,Data Register. When writing to this register  you must right-justify the data. Read"
rgroup.long 0xF8++0x7
line.long 0x0 "RSVD_1,RSVD_1 - Reserved address location"
hexmask.long 0x0 0.--31. 1. "RSVD1,Reserved address location"
line.long 0x4 "RSVD_2,RSVD_2 - Reserved address location"
hexmask.long 0x4 0.--31. 1. "RSVD2,Reserved address location"
tree.end
tree.end
tree "SYS_MGR (System Manager)"
base ad:0x10D12000
rgroup.long 0x0++0x7
line.long 0x0 "siliconid1,Specifies Silicon ID and revision number."
hexmask.long.word 0x0 16.--31. 1. "id,Silicon ID"
newline
hexmask.long.word 0x0 0.--15. 1. "rev,Silicon revision number."
line.long 0x4 "siliconid2,Reserved for future use."
hexmask.long 0x4 4.--31. 1. "rsv,Reserved for future use."
newline
hexmask.long.byte 0x4 0.--3. 1. "device_revision,SDM writes the device revision value from fuses to HPS secure manager."
group.long 0x8++0x3
line.long 0x0 "wddbg,Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These control registers are used to drive the pause input signal of the L4 watchdogs. Note that the watchdogs built into the MPU automatically are paused when their.."
hexmask.long.byte 0x0 28.--31. 1. "mode_4,Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index."
newline
hexmask.long.byte 0x0 24.--27. 1. "mode_3,Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index."
newline
hexmask.long.byte 0x0 20.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 16.--19. 1. "mode_2,Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index."
newline
hexmask.long.byte 0x0 12.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 8.--11. 1. "mode_1,Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index."
newline
hexmask.long.byte 0x0 4.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--3. 1. "mode_0,Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index."
rgroup.long 0x10++0x3
line.long 0x0 "mpu_status,This is MPU control register"
hexmask.long 0x0 5.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x0 0.--4. 1. "uncorrerr,MPU sends 1 bit of ECC error signal(mpu_interrir_irq) to system manager. System manager synchronizes this"
group.long 0x2C++0x3
line.long 0x0 "sdmmc_l3master,Register for ACE-lite control -"
hexmask.long.byte 0x0 26.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 16.--25. 1. "aruser,aruser ID"
newline
bitfld.long 0x0 14.--15. "ardomain,ardomain" "0,1,2,3"
newline
bitfld.long 0x0 12.--13. "awdomain,awdomain" "0,1,2,3"
newline
rbitfld.long 0x0 10.--11. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x0 0.--9. 1. "awuser,awuser ID"
group.long 0x34++0x2B
line.long 0x0 "nand_l3master,Controls the L3 master ARCACHE and AWCACHE AXI signals."
hexmask.long.byte 0x0 28.--31. 1. "arcache_0,Specifies the value of the module ARCACHE signal."
newline
bitfld.long 0x0 26.--27. "ardomain,ar domain register" "0,1,2,3"
newline
hexmask.long.word 0x0 16.--25. 1. "aruser,ar user register sid"
newline
hexmask.long.byte 0x0 12.--15. 1. "awcache_0,Specifies the value of the module AWCACHE signal."
newline
bitfld.long 0x0 10.--11. "awdomain,aw domain register" "0,1,2,3"
newline
hexmask.long.word 0x0 0.--9. 1. "awuser,aw user register sid"
line.long 0x4 "usb0_l3master,Controls the L3 master HPROT AHB-Lite signal."
hexmask.long.byte 0x4 26.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 16.--25. 1. "hauser22_13,hauser[22:13]"
newline
rbitfld.long 0x4 14.--15. "Reserved_4,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "hauser7_6,hauser[7:6]" "0,1,2,3"
newline
rbitfld.long 0x4 10.--11. "Reserved_3,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x4 9. "hauser_1,hauser[1] secure" "0,1"
newline
bitfld.long 0x4 8. "hauser_0,hauser[0] allocate" "0,1"
newline
hexmask.long.byte 0x4 4.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--3. 1. "hprot,HPROT[0]: Opcode/Data"
line.long 0x8 "usb1_l3master,Register for ACE-lite control - usb31_l3master"
hexmask.long.byte 0x8 26.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x8 16.--25. 1. "aruser,ar sid register"
newline
bitfld.long 0x8 14.--15. "ardomain,ar domain regisger" "0,1,2,3"
newline
bitfld.long 0x8 12.--13. "awdomain,aw domain register" "0,1,2,3"
newline
rbitfld.long 0x8 10.--11. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x8 0.--9. 1. "awuser,aw sid register"
line.long 0xC "tsn_global,Controls the L3 master ARCACHE and AWCACHE AXI signals."
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 0. "ptp_clk_sel,Selects the source of the PTP reference clock between tsn_ptp_clk from the Clock Manager or f2s_ptp_ref_clk from the FPGA Fabric." "0,1"
line.long 0x10 "tsn0,Registers used by the TSN. All fields are reset by a cold or warm reset."
bitfld.long 0x10 31. "axi_disable,AXI Disable" "0,1"
newline
bitfld.long 0x10 30. "sbd_data_endianness,Specifies the endianness of the TSN DMA transfers." "0,1"
newline
hexmask.long.word 0x10 19.--29. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 16.--18. "emac0_dbgbus_sel" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 9.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 8. "ptp_ref_sel,reserved" "0,1"
newline
rbitfld.long 0x10 5.--7. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4. "ppstrig_sel" "?,1: 1"
newline
rbitfld.long 0x10 2.--3. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x10 0.--1. "phy_intf_sel,phy_intf_sel" "0: PHY_INTF_GMII,1: PHY_INTF_RGMII,2: Reserved,3: PHY_INTF_RESET"
line.long 0x14 "tsn1,Registers used by the TSN. All fields are reset by a cold or warm reset."
bitfld.long 0x14 31. "axi_disable,AXI Disable" "0,1"
newline
bitfld.long 0x14 30. "sbd_data_endianness,Specifies the endianness of the TSN DMA transfers." "0,1"
newline
hexmask.long.word 0x14 19.--29. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 16.--18. "emac1_dbgbus_sel" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x14 9.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 8. "ptp_ref_sel,reserved" "0,1"
newline
rbitfld.long 0x14 5.--7. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 4. "ppstrig_sel" "0,1"
newline
rbitfld.long 0x14 2.--3. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x14 0.--1. "phy_intf_sel,phy_intf_sel" "0: PHY_INTF_GMII,1: PHY_INTF_RGMII,2: Reserved,3: PHY_INTF_RESET"
line.long 0x18 "tsn2,Registers used by the TSN. All fields are reset by a cold or warm reset."
bitfld.long 0x18 31. "axi_disable,AXI Disable" "0,1"
newline
bitfld.long 0x18 30. "sbd_data_endianness,Specifies the endianness of the TSN DMA transfers." "0,1"
newline
hexmask.long.word 0x18 19.--29. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 16.--18. "emac2_dbgbus_sel" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x18 9.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x18 8. "ptp_ref_sel,Reserved" "0,1"
newline
rbitfld.long 0x18 5.--7. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 4. "ppstrig_sel" "0,1"
newline
rbitfld.long 0x18 2.--3. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x18 0.--1. "phy_intf_sel,phy_intf_sel" "0: PHY_INTF_GMII,1: PHY_INTF_RGMII,2: Reserved,3: PHY_INTF_RESET"
line.long 0x1C "tsn0_ace,The TSN0 ACE-lite control register"
rbitfld.long 0x1C 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x1C 20.--29. 1. "awsid,awsid"
newline
rbitfld.long 0x1C 18.--19. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x1C 8.--17. 1. "arsid,arsid"
newline
hexmask.long.byte 0x1C 0.--7. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x20 "tsn1_ace,The TSN1 ACE-lite control register"
rbitfld.long 0x20 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x20 20.--29. 1. "awsid,awsid register"
newline
rbitfld.long 0x20 18.--19. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x20 8.--17. 1. "arsid,arsid register"
newline
hexmask.long.byte 0x20 0.--7. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x24 "tsn2_ace,The TSN2 ACE-lite control register"
rbitfld.long 0x24 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x24 20.--29. 1. "awsid,awsid register"
newline
rbitfld.long 0x24 18.--19. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x24 8.--17. 1. "arsid,arsid register"
newline
hexmask.long.byte 0x24 0.--7. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x28 "fpga_bridge_ctrl,fpga_bridge_ctrl register"
hexmask.long 0x28 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 1. "lwsoc2fpga_ready_latency_enable" "0,1"
newline
bitfld.long 0x28 0. "soc2fpga_ready_latency_enable" "0,1"
group.long 0x68++0x17
line.long 0x0 "fpgaintf_en_1,Used to disable individual interfaces between the FPGA and HPS."
hexmask.long.byte 0x0 25.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 24. "ctmtrigger,Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note that this doesn't prevent the HPS debug logic from sending triggers to the FPGA Fabric." "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 16. "stmevent,Used to disable the STM event interface. This interface allows logic in the FPGA fabric to trigger events to the STM debug module in the HPS." "0,1"
newline
hexmask.long.byte 0x0 9.--15. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 8. "dbgapb,Used to disable the debug APB interface. This interface allows the HPS debug logic to communicate with debug APB slaves in the FPGA fabric." "0,1"
newline
rbitfld.long 0x0 5.--7. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 4. "traceout,Gates the isolator of CoreSight" "0,1"
newline
rbitfld.long 0x0 1.--3. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "tracein,Gates the isolator of TPIU" "0,1"
line.long 0x4 "fpgaintf_en_2,Used to disable individual interfaces between the FPGA and HPS."
hexmask.long.byte 0x4 25.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 24. "spim_1,Used to disable signals from the FPGA fabric to the SPI master modules that could potentially interfere with their normal operation." "0,1"
newline
hexmask.long.byte 0x4 17.--23. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 16. "spim_0,Used to disable signals from the FPGA fabric to the SPI master modules that could potentially interfere with their normal operation." "0,1"
newline
hexmask.long.byte 0x4 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 8. "sdmmc,Used to disable signals from the FPGA fabric to the SD/MMC controller module that could potentially interfere with its normal operation." "0,1"
newline
rbitfld.long 0x4 5.--7. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 4. "nand,Used to disable signals from the FPGA fabric to the NAND flash controller module that could potentially interfere with its normal operation." "0,1"
newline
hexmask.long.byte 0x4 0.--3. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x8 "fpgaintf_en_3,Used to disable individual interfaces between the FPGA and HPS."
hexmask.long.word 0x8 17.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 16. "tsn_2,Used to disable signals from the FPGA fabric to the TSN modules that could potentially interfere with their normal operation." "0,1"
newline
hexmask.long.byte 0x8 9.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 8. "tsn_1,Used to disable signals from the FPGA fabric to the TSN modules that could potentially interfere with their normal operation." "0,1"
newline
hexmask.long.byte 0x8 1.--7. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 0. "tsn_0,Used to disable signals from the FPGA fabric to the TSN modules that could potentially interfere with their normal operation." "0,1"
line.long 0xC "dmac0_l3master,Register for ACE-lite control - dma_l3master"
hexmask.long.byte 0xC 26.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0xC 16.--25. 1. "aruser,ar sid register"
newline
bitfld.long 0xC 14.--15. "ardomain,ar domain regisger" "0,1,2,3"
newline
bitfld.long 0xC 12.--13. "awdomain,aw domain register" "0,1,2,3"
newline
rbitfld.long 0xC 10.--11. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0xC 0.--9. 1. "awuser,aw sid register"
line.long 0x10 "etr_l3master,Register for ACE-lite control - etr_l3master"
hexmask.long.byte 0x10 26.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x10 16.--25. 1. "aruser,ar sid register"
newline
bitfld.long 0x10 14.--15. "ardomain,ar domain regisger" "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "awdomain,aw domain register" "0,1,2,3"
newline
rbitfld.long 0x10 10.--11. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x10 0.--9. 1. "awuser,aw sid register"
line.long 0x14 "dmac1_l3master,Register for ACE-lite control - dma_l3master"
hexmask.long.byte 0x14 26.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x14 16.--25. 1. "aruser,ar sid register"
newline
bitfld.long 0x14 14.--15. "ardomain,ar domain regisger" "0,1,2,3"
newline
bitfld.long 0x14 12.--13. "awdomain,aw domain register" "0,1,2,3"
newline
rbitfld.long 0x14 10.--11. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x14 0.--9. 1. "awuser,aw sid register"
rgroup.long 0x80++0x7
line.long 0x0 "sec_ctrl_slt,This is the clock selection register. The APS oscillator selection is read only register. This value is driven from secure manager FS."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "val,1 bit register to read the value secure clock selection: secure internal oscillator and eosc1" "0,1"
line.long 0x4 "osc_trim,This is the osc_trim register to show internal oscillator"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x4 0.--7. 1. "val,RO 8 bit register that shows trim of internal oscillator"
group.long 0x88++0x13
line.long 0x0 "dmac0_ctrl_status_reg"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "mode" "0,1"
line.long 0x4 "dmac1_ctrl_status_reg"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 0. "mode" "0,1"
line.long 0x8 "ecc_intmask_value,ECC interrupt mask register."
hexmask.long.word 0x8 19.--31. 1. "Reserved_18,Reserved bitfield added by Magillem"
newline
bitfld.long 0x8 18. "dma1" "0,1"
newline
bitfld.long 0x8 17. "ddr1" "0,1"
newline
bitfld.long 0x8 16. "ddr0" "0,1"
newline
bitfld.long 0x8 15. "sdmmcb" "0,1"
newline
bitfld.long 0x8 14. "sdmmca" "0,1"
newline
bitfld.long 0x8 13. "nand_rd" "0,1"
newline
bitfld.long 0x8 12. "usb31_ram2" "0,1"
newline
bitfld.long 0x8 11. "usb31_ram1" "0,1"
newline
bitfld.long 0x8 10. "dma0" "0,1"
newline
bitfld.long 0x8 9. "tsn2_tx" "0,1"
newline
bitfld.long 0x8 8. "tsn2_rx" "0,1"
newline
bitfld.long 0x8 7. "tsn1_tx" "0,1"
newline
bitfld.long 0x8 6. "tsn1_rx" "0,1"
newline
bitfld.long 0x8 5. "tsn0_tx" "0,1"
newline
bitfld.long 0x8 4. "tsn0_rx" "0,1"
newline
bitfld.long 0x8 3. "usb31_ram0" "0,1"
newline
bitfld.long 0x8 2. "usb0" "0,1"
newline
bitfld.long 0x8 1. "ocram" "0,1"
newline
rbitfld.long 0x8 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
line.long 0xC "ecc_intmask_set,Write 1 to set a specific modules interrupt mask."
hexmask.long.word 0xC 19.--31. 1. "Reserved_18,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 18. "dma1" "0,1"
newline
bitfld.long 0xC 17. "ddr1" "0,1"
newline
bitfld.long 0xC 16. "ddr0" "0,1"
newline
bitfld.long 0xC 15. "sdmmcb" "0,1"
newline
bitfld.long 0xC 14. "sdmmca" "0,1"
newline
bitfld.long 0xC 13. "nand_rd" "0,1"
newline
bitfld.long 0xC 12. "usb31_ram2" "0,1"
newline
bitfld.long 0xC 11. "usb31_ram1" "0,1"
newline
bitfld.long 0xC 10. "dma0" "0,1"
newline
bitfld.long 0xC 9. "tsn2_tx" "0,1"
newline
bitfld.long 0xC 8. "tsn2_rx" "0,1"
newline
bitfld.long 0xC 7. "tsn1_tx" "0,1"
newline
bitfld.long 0xC 6. "tsn1_rx" "0,1"
newline
bitfld.long 0xC 5. "tsn0_tx" "0,1"
newline
bitfld.long 0xC 4. "tsn0_rx" "0,1"
newline
bitfld.long 0xC 3. "usb31_ram0" "0,1"
newline
bitfld.long 0xC 2. "usb0" "0,1"
newline
bitfld.long 0xC 1. "ocram" "0,1"
newline
bitfld.long 0xC 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
line.long 0x10 "ecc_intmask_clr,Write 1 to Clear a specific modules interrupt mask."
hexmask.long.word 0x10 19.--31. 1. "Reserved_18,Reserved bitfield added by Magillem"
newline
eventfld.long 0x10 18. "dma1" "0,1"
newline
eventfld.long 0x10 17. "ddr1" "0,1"
newline
eventfld.long 0x10 16. "ddr0" "0,1"
newline
eventfld.long 0x10 15. "sdmmcb" "0,1"
newline
eventfld.long 0x10 14. "sdmmca" "0,1"
newline
eventfld.long 0x10 13. "nand_rd" "0,1"
newline
eventfld.long 0x10 12. "usb31_ram2" "0,1"
newline
eventfld.long 0x10 11. "usb31_ram1" "0,1"
newline
eventfld.long 0x10 10. "dma0" "0,1"
newline
eventfld.long 0x10 9. "tsn2_tx" "0,1"
newline
eventfld.long 0x10 8. "tsn2_rx" "0,1"
newline
eventfld.long 0x10 7. "tsn1_tx" "0,1"
newline
eventfld.long 0x10 6. "tsn1_rx" "0,1"
newline
eventfld.long 0x10 5. "tsn0_tx" "0,1"
newline
eventfld.long 0x10 4. "tsn0_rx" "0,1"
newline
eventfld.long 0x10 3. "usb31_ram0" "0,1"
newline
eventfld.long 0x10 2. "usb0" "0,1"
newline
eventfld.long 0x10 1. "ocram" "0,1"
newline
bitfld.long 0x10 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
rgroup.long 0x9C++0x7
line.long 0x0 "ecc_intstatus_serr,ECC single bit error status of individual modules."
hexmask.long.word 0x0 19.--31. 1. "Reserved_18,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 18. "dma1" "0,1"
newline
bitfld.long 0x0 17. "ddr1" "0,1"
newline
bitfld.long 0x0 16. "ddr0" "0,1"
newline
bitfld.long 0x0 15. "sdmmcb" "0,1"
newline
bitfld.long 0x0 14. "sdmmca" "0,1"
newline
bitfld.long 0x0 13. "nand_rd" "0,1"
newline
bitfld.long 0x0 12. "usb31_ram2" "0,1"
newline
bitfld.long 0x0 11. "usb31_ram1" "0,1"
newline
bitfld.long 0x0 10. "dma0" "0,1"
newline
bitfld.long 0x0 9. "tsn2_tx" "0,1"
newline
bitfld.long 0x0 8. "tsn2_rx" "0,1"
newline
bitfld.long 0x0 7. "tsn1_tx" "0,1"
newline
bitfld.long 0x0 6. "tsn1_rx" "0,1"
newline
bitfld.long 0x0 5. "tsn0_tx" "0,1"
newline
bitfld.long 0x0 4. "tsn0_rx" "0,1"
newline
bitfld.long 0x0 3. "usb31_ram0" "0,1"
newline
bitfld.long 0x0 2. "usb0" "0,1"
newline
bitfld.long 0x0 1. "ocram" "0,1"
newline
bitfld.long 0x0 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
line.long 0x4 "ecc_intstatus_derr,ECC double bit error status of individual modules."
hexmask.long.word 0x4 19.--31. 1. "Reserved_18,Reserved bitfield added by Magillem"
newline
bitfld.long 0x4 18. "dma1" "0,1"
newline
bitfld.long 0x4 17. "ddr1" "0,1"
newline
bitfld.long 0x4 16. "ddr0" "0,1"
newline
bitfld.long 0x4 15. "sdmmcb" "0,1"
newline
bitfld.long 0x4 14. "sdmmca" "0,1"
newline
bitfld.long 0x4 13. "nand_rd" "0,1"
newline
bitfld.long 0x4 12. "usb31_ram2" "0,1"
newline
bitfld.long 0x4 11. "usb31_ram1" "0,1"
newline
bitfld.long 0x4 10. "dma0" "0,1"
newline
bitfld.long 0x4 9. "tsn2_tx" "0,1"
newline
bitfld.long 0x4 8. "tsn2_rx" "0,1"
newline
bitfld.long 0x4 7. "tsn1_tx" "0,1"
newline
bitfld.long 0x4 6. "tsn1_rx" "0,1"
newline
bitfld.long 0x4 5. "tsn0_tx" "0,1"
newline
bitfld.long 0x4 4. "tsn0_rx" "0,1"
newline
bitfld.long 0x4 3. "usb31_ram0" "0,1"
newline
bitfld.long 0x4 2. "usb0" "0,1"
newline
bitfld.long 0x4 1. "ocram" "0,1"
newline
bitfld.long 0x4 0. "Reserved_0,Reserved bitfield added by Magillem" "0,1"
group.long 0xC0++0x3
line.long 0x0 "noc_timeout"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "en,NOC Timeout Enable. Write 1 to enable noc timeout." "0,1"
rgroup.long 0xD4++0x3
line.long 0x0 "noc_idlestatus,Status of IDLE from the NOC masters. A 1 in the field means the specific master is idle."
hexmask.long 0x0 5.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 4. "lwsoc2fpga" "0,1"
newline
bitfld.long 0x0 1.--3. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0. "soc2fpga" "0,1"
group.long 0xD8++0x3
line.long 0x0 "fpga2soc_ctrl,Converts transactions from fpga2soc to non secure or allows both secure or non-secure transactions by fpga2soc."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "allow_secure,0 - All Transactions from FPGA2SOC is converted to be Non-Secure" "0,1"
rgroup.long 0xDC++0x3
line.long 0x0 "fpga_config,FPGA configuration read only register"
hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 1. "early_usermode,FGPA configuration complete" "0,1"
newline
bitfld.long 0x0 0. "fpga_complete,FGPA configuration complete" "0,1"
group.long 0xE4++0x3
line.long 0x0 "gpo,Provides a low-latency. low-performance. and simple way to drive general-purpose signals to the FPGA fabric"
hexmask.long 0x0 0.--31. 1. "val,Drives s2f_gp[31:0] with specified value. When read  returns the current value being driven to the FPGA fabric"
rgroup.long 0xE8++0x3
line.long 0x0 "gpi,Provides a low-latency. low-performance. and simple way to read general-purpose signals driven from the FPGA fabric."
hexmask.long 0x0 0.--31. 1. "val,The value being driven from the FPGA fabric on f2s_gp[31:0]. If the FPGA is not in User Mode  the value of this field is undefined."
group.long 0xF0++0x37
line.long 0x0 "mpu,Provides a low-latency. low-performance. and simple way to read general-purpose signals driven from the FPGA fabric."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 0. "mpu_cfgsdisable,CFGSDISABLE is typically de-asserted (0) from reset until Secure software has configured the GIC-400 and then subsequently asserted permanently to provide extra security." "0,1"
line.long 0x4 "sdm_hps_spare,SDM to HPS spare signals are mapped to a system manager register. PSI side band signals will set these bits and HPS SW will clear this register"
hexmask.long.tbyte 0x4 12.--31. 1. "Reserved_12,Reserved bitfield added by Magillem"
newline
eventfld.long 0x4 11. "bit_11" "0,1"
newline
eventfld.long 0x4 10. "bit_10" "0,1"
newline
eventfld.long 0x4 9. "bit_9" "0,1"
newline
eventfld.long 0x4 8. "bit_8" "0,1"
newline
eventfld.long 0x4 7. "bit_7" "0,1"
newline
eventfld.long 0x4 6. "bit_6" "0,1"
newline
eventfld.long 0x4 5. "bit_5" "0,1"
newline
eventfld.long 0x4 4. "bit_4" "0,1"
newline
eventfld.long 0x4 3. "bit_3" "0,1"
newline
eventfld.long 0x4 2. "bit_2" "0,1"
newline
eventfld.long 0x4 1. "bit_1" "0,1"
newline
eventfld.long 0x4 0. "bit_0" "0,1"
line.long 0x8 "hps_sdm_spare,HPS to SDM spare signals are mapped to a system manager register."
hexmask.long.word 0x8 19.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.tbyte 0x8 0.--18. 1. "val,write to this register will drive the value PSI spare ports."
line.long 0xC "dfi_interface_cfg,control bit used to set active DFI interface. 0 - DFI"
hexmask.long 0xC 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
bitfld.long 0xC 0. "dfi_ctrl_sel" "0,1"
line.long 0x10 "nand_dd_ctrl"
hexmask.long.word 0x10 16.--31. 1. "rb_valid_time,The PHY initialization parameter for device discovery process. Value of this parameter should be calculated as: RB_VALID_TIME = Trb[us] * fsys [MHz]  where: Trb - value of the 'RB_valid_Vcc' time (from NAND flash device specification) fsys.."
newline
hexmask.long.word 0x10 5.--15. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
bitfld.long 0x10 4. "discovery_ignore_crc,When tied to 1  the controller will ignore CRC checking after reading of parameter page during device discovery process." "0,1"
newline
rbitfld.long 0x10 1.--3. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0. "discovery_inhibit,Bootstrap port to inhibit Controller from any initialization. Controller will not make device discovery process. This signal must be stable and have proper value by the time the Controller comes out of reset." "0,1"
line.long 0x14 "nand_phy_ctrl_reg"
hexmask.long.word 0x14 22.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 21. "pu_pd_polarity,Defines the polarity of the ALE port that in SD works as pull-up/pull-down signal for bit 2 of the DATA" "0,1"
newline
bitfld.long 0x14 20. "low_freq_sel,If this field is set high the DFI interface is synchronous to the falling edge of the clock ie. the input signals are latched at the falling edge of the clk_ctrl and output signals are sync to falling edge of the clk_ctrl. Otherwise the.." "0,1"
newline
hexmask.long.byte 0x14 15.--19. 1. "Reserved_3,Reserved bitfield added by Magillem"
newline
bitfld.long 0x14 14. "sdr_dqs_value,The value that should be driven on the DQS pin while SDR operations are in progress. Please note that in the DDR modes of operations  the command and address cycles are still in SDR mode. This field informs the PHY of the value to be driven.." "0,1"
newline
hexmask.long.byte 0x14 10.--13. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x14 4.--9. 1. "phony_dqs_timing,The timing of assertion of phony DQS to the data slices. If the extended_read_mode is disabled the value should be zero. If the extended_read_modeis enabled the value should match the width of the rebar pulse in terms of clock PHY clock.."
newline
rbitfld.long 0x14 1.--3. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0. "ctrl_clkperiod_delay,Defines additional latency on the control signals ALE/CLE/ WE/RE/CE/WP" "0,1"
line.long 0x18 "nand_phy_tsel_reg"
hexmask.long.byte 0x18 24.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x18 20.--23. 1. "tsel_off_value_data,Termination select off value for the data"
newline
hexmask.long.byte 0x18 16.--19. 1. "tsel_rd_value_data,ermination select read value for the data"
newline
hexmask.long.byte 0x18 12.--15. 1. "tsel_off_value_dqs,Termination select off valuefor the data strobe"
newline
hexmask.long.byte 0x18 8.--11. 1. "tsel_rd_value_dqs,Termination select read value for the data strobe"
newline
hexmask.long.byte 0x18 0.--7. 1. "Reserved_0,Reserved bitfield added by Magillem"
line.long 0x1C "nand_phy_dq_timing_reg"
hexmask.long.byte 0x1C 24.--31. 1. "Reserved_5,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x1C 16.--23. 1. "data_clkperiod_delay,Defines additional latency on the write datapath. It also adds a clock cycle delay for the data OE path which is equivalent of adding 2 to the data_select_oe_end and data_select_oe_start."
newline
hexmask.long.byte 0x1C 12.--15. 1. "data_select_tsel_start,Defines the DQ pad dynamic termination select enable time. Larger values add greater delay to when tsel turns on. Each bit changes the output enable time by a 1/2 cycle resolution"
newline
hexmask.long.byte 0x1C 8.--11. 1. "data_select_tsel_end,Defines the DQ pad dynamic termination select disable time. Larger values increase the delay to when tsel turns off. Each bit changes the output enable time by a 1/2 cycle resolution."
newline
rbitfld.long 0x1C 7. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x1C 4.--6. "data_select_oe_start,Adjusts the starting point of the DQ pad output enable window. Lower numbers pull the rising edge earlier in time and larger numbers cause the rising edge to be delayed. Each bit changes the output enable time by a 1/2 cycle.." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x1C 3. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x1C 0.--2. "data_select_oe_end,Adjusts the ending point of the DQ pad output enable window. Lower numbers pull the falling edge earlier in time and larger numbers cause the falling edge to be delayed. Each bit changes the output enable time by a 1/2 cycle resolution." "0,1,2,3,4,5,6,7"
line.long 0x20 "phy_dqs_timing_reg"
hexmask.long.byte 0x20 24.--31. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x20 23. "dqs_clkperiod_delay" "0,1"
newline
rbitfld.long 0x20 21.--22. "Reserved_6,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x20 20. "use_phony_dqs" "0,1"
newline
rbitfld.long 0x20 17.--19. "Reserved_5,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 16. "phony_dqs_sel" "0,1"
newline
hexmask.long.byte 0x20 12.--15. 1. "dqs_select_tsel_start"
newline
hexmask.long.byte 0x20 8.--11. 1. "dqs_select_tsel_end"
newline
hexmask.long.byte 0x20 4.--7. 1. "dqs_select_oe_start"
newline
hexmask.long.byte 0x20 0.--3. 1. "dqs_select_oe_end"
line.long 0x24 "nand_phy_gate_lpbk_ctrl_reg"
bitfld.long 0x24 31. "sync_method,Defines the method of transfering the data from DQS domain flops to the clk_phy clock domain.&bull;if set low the read pointer advances based upon a programmable delay of the dfi_rddata_en pulse from the DFI interface.&bull;if set high the.." "0,1"
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bitfld.long 0x24 30. "sw_dqs_phase_bypass,0 -Use phase detect circult to determine the half_cycle_shift." "0,1"
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bitfld.long 0x24 29. "en_sw_half_cycle,Enables the software half cycle shift. This determines if write data is transferred to the clk_wrdqs domain on the positive or negative edge of the PHY clock. This field is valid when sw_dqs_phase_bypass is low.&bull;'b0 -Hardware.." "0,1"
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bitfld.long 0x24 28. "sw_half_cycle_shift,0 -No effect." "0,1"
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bitfld.long 0x24 25.--27. "param_phase_detect_sel_oe,DLL Phase Detect Selector for DQS OE generation to handle the clock domain crossing between the clock and clk_wrdqs signal. Selects the number of delay elements to be inserted between the phase detect flip-flops. Defaults to.." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x24 19.--24. 1. "rd_del_sel,Defines the read data delay. Holds the number of cycles to delay the dfi_rddata_en signal prior to enabling the read FIFO. After this delay  the read pointers begin incrementing the read FIFO. If 'sync_method' is set high the value of this.."
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bitfld.long 0x24 18. "underrun_suppress,This field turns off the generation of theunderrun signal when 'sync_method' is set high. Recommended value is zero" "0,1"
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rbitfld.long 0x24 17. "Reserved_8,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x24 16. "rd_del_sel_empty,Defines the read data delay for the empty signal generated based on the incoming DQS strobes. For zero delay the data are passed from entry flops to the iodatain* flops one clock cycle after the !empty signals is asserted. Normally the.." "0,1"
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bitfld.long 0x24 13.--15. "lpbk_err_check_timing,Sets the cycle delay between the LFSR and loopback error check logic to ensure that the LFSR sourced data and data being looped back arrive at the same clock cycle for comparison. This value is related to the rd_del_sel field  and.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 12. "lpbk_fail_muxsel,Selects data output typefor phy_obs_reg_0[23:8]." "0: Return the expected data,1: Return the actual dat"
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bitfld.long 0x24 10.--11. "loopback_control,&bull;0 = Normal Operation Mode." "0: Normal Operation Mode,1: lpbk_start,2: lpbk_stop,3: clear"
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bitfld.long 0x24 9. "lpbk_internal,Controls the loopback read multiplexer." "0: External Loopback,1: Internal loopback"
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bitfld.long 0x24 8. "lpbk_en,Controls internal write multiplexer." "0: Normal Operation,1: Enable loopback"
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rbitfld.long 0x24 6.--7. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
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bitfld.long 0x24 4.--5. "gate_cfg_close,Normally the gate is closing when all bits of dfi_cebar are high or when dfi_rd_pre_post_amble and rebar_dfi are high. This parameter allows to extend the closing of the DQS gate. Recommended value is zero." "0,1,2,3"
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hexmask.long.byte 0x24 0.--3. 1. "gate_cfg,Coarse adjust of gate open time. This value is the number of cycles to delay the dfi_rddata_en signal prior to opening the gate in full cycle increments. Decreasing this value pulls the gate earlier in time. This field should be programmed such.."
line.long 0x28 "nand_phy_dll_master_ctrl_reg"
hexmask.long.byte 0x28 24.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
bitfld.long 0x28 23. "param_dll_bypass_mode,DLL bypass mode control. Controls the bypass mode of the master and slave DLLs. The param_dll_bypass_mode is intended to be used only for debug." "0,1"
newline
bitfld.long 0x28 20.--22. "param_phase_detect_sel,Selects the number of delay elements to be inserted between the phase detect flip-flops. Defaults to 0x0 although the recommended value is 2 elements but if a lock condition is not detected  the user should increase the number of.." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x28 19. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x28 16.--18. "param_dll_lock_num,Holds the number of consecutive increment or decrement indications that will trigger an unlock condition and increment the dll_unlock_cnt field (bits [7:3]) and either the lock_dec_dbg (bits [23:16]) or lock_inc_dbg (bits [31:24]).." "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 8.--15. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x28 0.--7. 1. "param_dll_start_point,e for the DLL. This value is also used as the increment value if the initial value is less than a half-clock cycle. This field should be set such that it is not greater than 7/8ths of a clock period given the worst case element.."
line.long 0x2C "nand_phy_dll_slave_ctrl_reg"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x2C 16.--23. 1. "clk_wrdqs_delay,Controls the clk_wrdqs delay line which adjusts the write DQS timing in 1/256th steps of the clock period in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements. clk_wrdqs delay line is used.."
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hexmask.long.byte 0x2C 8.--15. 1. "clk_wr_delay,Controls the clk_wr delay line which adjusts the write DQ bit timing in 1/256th steps of the clock period in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements"
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hexmask.long.byte 0x2C 0.--7. 1. "read_dqs_delay,Controls the read DQS delay which adjusts the timing in 1/256th of the clock period when in normal DLL locked mode. In bypass mode  this field directly programs the number of delay elements."
line.long 0x30 "nand_dd_default_setting_reg0,NAND Device Discovery Default Settings Register 1"
hexmask.long.word 0x30 16.--31. 1. "dd_pages_per_block,Device Discovery external parameters &ndash; number of pages in single block."
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hexmask.long.word 0x30 0.--15. 1. "dd_page_size,Device Discovery external parameters &ndash; number of bytes in single Nand Flash page."
line.long 0x34 "nand_dd_default_setting_reg1,NAND Device Discovery Default Settings Register 2"
hexmask.long.tbyte 0x34 9.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
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bitfld.long 0x34 8. "dd_ack,Device Discovery external parameters acknowledge signal." "0,1"
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hexmask.long.byte 0x34 4.--7. 1. "dd_lun_number,Device Discovery external parameters &ndash; number of LUNs in single NandFlash device."
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rbitfld.long 0x34 3. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x34 1.--2. "dd_row_addr_width,Device Discovery external parameters &ndash; number of row address cycles. Port encoding is as following:" "0,1,2,3"
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bitfld.long 0x34 0. "dd_support_16_bit,Device Discovery external parameters - 16b NF" "0,1"
rgroup.long 0x128++0xB
line.long 0x0 "nand_dd_status_reg,Nand Device DiscoveryStatus Register"
hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
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bitfld.long 0x0 3. "dd_req" "0,1"
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bitfld.long 0x0 2. "init_comp" "0,1"
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bitfld.long 0x0 1. "init_fail" "0,1"
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bitfld.long 0x0 0. "ctrl_busy" "0,1"
line.long 0x4 "nand_dd_id_low_reg,Device ID low Rgister"
hexmask.long 0x4 0.--31. 1. "dd_id_value"
line.long 0x8 "nand_dd_id_high_reg,Device ID High Rgister"
hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x8 0.--7. 1. "dd_id_value"
group.long 0x134++0x9F
line.long 0x0 "nand_write_prot_en_reg,NAND write protection enable register"
hexmask.long 0x0 5.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
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bitfld.long 0x0 4. "wre_prot_en_1,Write protect enable signal for registers. Setting 1 on this pin will enableblocking access to the Write Protect registers with suffix _1." "0,1"
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rbitfld.long 0x0 1.--3. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. "wre_prot_en_0,rite protect enable signal for registers. Setting 1 on this pin will enable blocking access to the Write Protect registers with suffix _0." "0,1"
line.long 0x4 "sdmmc_cmd_queue_setting_reg,SDMMC Command queue setting register"
hexmask.long.word 0x4 20.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x4 16.--19. 1. "ITCMFMUL,ITCFMUL -Internal Timer Clock Frequency Multiplier (ITCFMUL)Defines the multiplier of internal clock frequency for the coalescing timer and for the SQS polling period."
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rbitfld.long 0x4 15. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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hexmask.long.word 0x4 5.--14. 1. "ITCMFVAL,ITCFVAL - Internal Timer Clock Frequency Value (ITCFVAL) Value defines internal clock frequency for the coalescing timer and for the SQS polling period. The frequency is equal to ITCFMUL * ITCFVAL."
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hexmask.long.byte 0x4 0.--4. 1. "ITCFSEL,ITCFSEL-This is a system clock divider value."
line.long 0x8 "i3c_slv_pid_low"
hexmask.long 0x8 0.--31. 1. "Val"
line.long 0xC "i3c_slv_pid_high"
hexmask.long.word 0xC 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
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hexmask.long.word 0xC 0.--15. 1. "Val"
line.long 0x10 "i3c_slv_ctrl_0"
rbitfld.long 0x10 31. "wakeup" "0,1"
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rbitfld.long 0x10 30. "i2c_glitch_filter_en" "0,1"
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hexmask.long.tbyte 0x10 8.--29. 1. "Reserved_4,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x10 4.--7. 1. "pending_in"
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bitfld.long 0x10 3. "static_addr_en" "0,1"
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bitfld.long 0x10 1.--2. "act_mode" "0,1,2,3"
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bitfld.long 0x10 0. "mode_i2c" "0,1"
line.long 0x14 "i3c_slv_ctrl_1"
rbitfld.long 0x14 31. "Reserved_6,Reserved bitfield added by Magillem" "0,1"
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hexmask.long.byte 0x14 24.--30. 1. "static_addr"
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hexmask.long.byte 0x14 20.--23. 1. "inst_id"
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rbitfld.long 0x14 19. "Reserved_4,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x14 16.--18. "slv_clk_data_turn_time" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x14 15. "Reserved_3,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x14 12.--14. "slv_max_wr_speed" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x14 11. "Reserved_2,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x14 8.--10. "slv_max_rd_speed" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x14 0.--7. 1. "slv_dcr"
line.long 0x18 "f2s_bridge_ctrl,f2s bridge control register"
hexmask.long 0x18 3.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
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bitfld.long 0x18 2. "f2soc_force_drain" "0,1"
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bitfld.long 0x18 1. "f2soc_ready_latency_enable,0 = f2s bridge ready latency disable" "0: f2s bridge ready latency disable,1: f2s bridge ready latency enabled"
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bitfld.long 0x18 0. "f2soc_enable,0 = f2s bridge disable" "0: f2s bridge disable,1: f2s bridge enabled"
line.long 0x1C "dma_tbu_stash_ctrl_reg_0_dma0"
rbitfld.long 0x1C 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x1C 24.--28. 1. "stashlpid_reg_val"
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rbitfld.long 0x1C 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x1C 16.--20. 1. "stashnid_reg_val"
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hexmask.long.byte 0x1C 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x1C 8.--11. 1. "wsnoop_reg_val"
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bitfld.long 0x1C 6.--7. "rdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x1C 4.--5. "wdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x1C 3. "rdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x1C 2. "wdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x1C 1. "stashlpiden_reg_ctrl" "0,1"
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bitfld.long 0x1C 0. "stashniden_reg_ctrl" "0,1"
line.long 0x20 "dma_tbu_stash_ctrl_reg_0_dma1"
rbitfld.long 0x20 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 24.--28. 1. "stashlpid_reg_val"
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rbitfld.long 0x20 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 16.--20. 1. "stashnid_reg_val"
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hexmask.long.byte 0x20 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x20 8.--11. 1. "wsnoop_reg_val"
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bitfld.long 0x20 6.--7. "rdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x20 4.--5. "wdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x20 3. "rdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x20 2. "wdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x20 1. "stashlpiden_reg_ctrl" "0,1"
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bitfld.long 0x20 0. "stashniden_reg_ctrl" "0,1"
line.long 0x24 "sdm_tbu_stash_ctrl_reg_1_sdm"
rbitfld.long 0x24 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x24 24.--28. 1. "stashlpid_reg_val"
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rbitfld.long 0x24 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x24 16.--20. 1. "stashnid_reg_val"
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hexmask.long.byte 0x24 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x24 8.--11. 1. "wsnoop_reg_val"
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bitfld.long 0x24 6.--7. "rdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x24 4.--5. "wdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x24 3. "rdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x24 2. "wdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x24 1. "stashlpiden_reg_ctrl" "0,1"
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bitfld.long 0x24 0. "stashniden_reg_ctrl" "0,1"
line.long 0x28 "io_tbu_stash_ctrl_reg_2_usb2"
rbitfld.long 0x28 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 24.--28. 1. "stashlpid_reg_val"
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rbitfld.long 0x28 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x28 16.--20. 1. "stashnid_reg_val"
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hexmask.long.byte 0x28 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x28 8.--11. 1. "wsnoop_reg_val"
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bitfld.long 0x28 6.--7. "rdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x28 4.--5. "wdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x28 3. "rdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x28 2. "wdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x28 1. "stashlpiden_reg_ctrl" "0,1"
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bitfld.long 0x28 0. "stashniden_reg_ctrl" "0,1"
line.long 0x2C "io_tbu_stash_ctrl_reg_2_usb3"
rbitfld.long 0x2C 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x2C 24.--28. 1. "stashlpid_reg_val"
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rbitfld.long 0x2C 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x2C 16.--20. 1. "stashnid_reg_val"
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hexmask.long.byte 0x2C 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x2C 8.--11. 1. "wsnoop_reg_val"
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bitfld.long 0x2C 6.--7. "rdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x2C 4.--5. "wdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x2C 3. "rdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x2C 2. "wdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x2C 1. "stashlpiden_reg_ctrl" "0,1"
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bitfld.long 0x2C 0. "stashniden_reg_ctrl" "0,1"
line.long 0x30 "io_tbu_stash_ctrl_reg_2_sdmmc"
rbitfld.long 0x30 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x30 24.--28. 1. "stashlpid_reg_val"
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rbitfld.long 0x30 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x30 16.--20. 1. "stashnid_reg_val"
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hexmask.long.byte 0x30 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x30 8.--11. 1. "wsnoop_reg_val"
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bitfld.long 0x30 6.--7. "rdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x30 4.--5. "wdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x30 3. "rdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x30 2. "wdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x30 1. "stashlpiden_reg_ctrl" "0,1"
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bitfld.long 0x30 0. "stashniden_reg_ctrl" "0,1"
line.long 0x34 "io_tbu_stash_ctrl_reg_2_nand"
rbitfld.long 0x34 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x34 24.--28. 1. "stashlpid_reg_val"
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rbitfld.long 0x34 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x34 16.--20. 1. "stashnid_reg_val"
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hexmask.long.byte 0x34 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x34 8.--11. 1. "wsnoop_reg_val"
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bitfld.long 0x34 6.--7. "rdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x34 4.--5. "wdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x34 3. "rdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x34 2. "wdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x34 1. "stashlpiden_reg_ctrl" "0,1"
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bitfld.long 0x34 0. "stashniden_reg_ctrl" "0,1"
line.long 0x38 "io_tbu_stash_ctrl_reg_2_etr"
rbitfld.long 0x38 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x38 24.--28. 1. "stashlpid_reg_val"
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rbitfld.long 0x38 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x38 16.--20. 1. "stashnid_reg_val"
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hexmask.long.byte 0x38 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x38 8.--11. 1. "wsnoop_reg_val"
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bitfld.long 0x38 6.--7. "rdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x38 4.--5. "wdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x38 3. "rdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x38 2. "wdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x38 1. "stashlpiden_reg_ctrl" "0,1"
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bitfld.long 0x38 0. "stashniden_reg_ctrl" "0,1"
line.long 0x3C "tsn_tbu_stash_ctrl_reg_3_tsn0"
rbitfld.long 0x3C 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x3C 24.--28. 1. "stashlpid_reg_val"
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rbitfld.long 0x3C 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x3C 16.--20. 1. "stashnid_reg_val"
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hexmask.long.byte 0x3C 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
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hexmask.long.byte 0x3C 8.--11. 1. "wsnoop_reg_val"
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bitfld.long 0x3C 6.--7. "rdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x3C 4.--5. "wdoaminen_reg_val" "0,1,2,3"
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bitfld.long 0x3C 3. "rdoaminen_reg_ctrl" "0,1"
newline
bitfld.long 0x3C 2. "wdoaminen_reg_ctrl" "0,1"
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bitfld.long 0x3C 1. "stashlpiden_reg_ctrl" "0,1"
newline
bitfld.long 0x3C 0. "stashniden_reg_ctrl" "0,1"
line.long 0x40 "tsn_tbu_stash_ctrl_reg_3_tsn1"
rbitfld.long 0x40 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x40 24.--28. 1. "stashlpid_reg_val"
newline
rbitfld.long 0x40 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x40 16.--20. 1. "stashnid_reg_val"
newline
hexmask.long.byte 0x40 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x40 8.--11. 1. "wsnoop_reg_val"
newline
bitfld.long 0x40 6.--7. "rdoaminen_reg_val" "0,1,2,3"
newline
bitfld.long 0x40 4.--5. "wdoaminen_reg_val" "0,1,2,3"
newline
bitfld.long 0x40 3. "rdoaminen_reg_ctrl" "0,1"
newline
bitfld.long 0x40 2. "wdoaminen_reg_ctrl" "0,1"
newline
bitfld.long 0x40 1. "stashlpiden_reg_ctrl" "0,1"
newline
bitfld.long 0x40 0. "stashniden_reg_ctrl" "0,1"
line.long 0x44 "tsn_tbu_stash_ctrl_reg_3_tsn2"
rbitfld.long 0x44 29.--31. "Reserved_9,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x44 24.--28. 1. "stashlpid_reg_val"
newline
rbitfld.long 0x44 21.--23. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x44 16.--20. 1. "stashnid_reg_val"
newline
hexmask.long.byte 0x44 12.--15. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x44 8.--11. 1. "wsnoop_reg_val"
newline
bitfld.long 0x44 6.--7. "rdoaminen_reg_val" "0,1,2,3"
newline
bitfld.long 0x44 4.--5. "wdoaminen_reg_val" "0,1,2,3"
newline
bitfld.long 0x44 3. "rdoaminen_reg_ctrl" "0,1"
newline
bitfld.long 0x44 2. "wdoaminen_reg_ctrl" "0,1"
newline
bitfld.long 0x44 1. "stashlpiden_reg_ctrl" "0,1"
newline
bitfld.long 0x44 0. "stashniden_reg_ctrl" "0,1"
line.long 0x48 "dma_tbu_stream_ctrl_reg_0_dma0"
hexmask.long 0x48 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x48 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x48 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x48 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x48 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x48 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x48 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x4C "dma_tbu_stream_ctrl_reg_0_dma1"
hexmask.long 0x4C 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x4C 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x4C 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x4C 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x4C 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x4C 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x4C 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x50 "sdm_tbu_stream_ctrl_reg_1_sdm"
hexmask.long 0x50 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x50 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x50 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x50 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x50 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x50 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x50 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x54 "io_tbu_stream_ctrl_reg_2_usb2"
hexmask.long 0x54 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x54 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x54 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x54 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x54 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x54 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x54 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x58 "io_tbu_stream_ctrl_reg_2_usb3,for future use"
hexmask.long 0x58 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x58 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x58 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x58 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x58 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x58 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x58 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x5C "io_tbu_stream_ctrl_reg_2_sdmmc"
hexmask.long 0x5C 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x5C 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x5C 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x5C 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x5C 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x5C 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x5C 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x60 "io_tbu_stream_ctrl_reg_2_nand"
hexmask.long 0x60 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x60 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x60 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x60 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x60 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x60 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x60 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x64 "io_tbu_stream_ctrl_reg_2_etr"
hexmask.long 0x64 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x64 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x64 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x64 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x64 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x64 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x64 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x68 "tsn_tbu_stream_ctrl_reg_3_tsn0"
hexmask.long 0x68 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x68 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x68 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x68 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x68 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x68 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x68 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x6C "tsn_tbu_stream_ctrl_reg_3_tsn1"
hexmask.long 0x6C 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x6C 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x6C 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x6C 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x6C 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x6C 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x6C 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x70 "tsn_tbu_stream_ctrl_reg_3_tsn2"
hexmask.long 0x70 6.--31. 1. "spare_ctrl,for future use"
newline
bitfld.long 0x70 5. "rmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction31:6RO0hReserved"
newline
bitfld.long 0x70 4. "wmmusecsid_reg_Val,Provide the Secure or Non-secure register value for AW stream transaction;" "0: Non-secure transaction,1: Secure transaction"
newline
bitfld.long 0x70 3. "rstreamsiden_reg_ctrl,Enable the Substream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x70 2. "wstreamsiden_reg_ctrl,Enable the Substream ID Value at AW stream interface;" "0,1"
newline
bitfld.long 0x70 1. "rstreamiden_reg_ctrl,Enable the Stream ID Value at AR stream interface;" "0,1"
newline
bitfld.long 0x70 0. "wstreamiden_reg_ctrl,Enable the Stream ID Value at AW stream interface;" "0,1"
line.long 0x74 "dma_tbu_stream_id_Ax_reg_0_dma0"
hexmask.long.word 0x74 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x74 0.--15. 1. "wmmusid_reg_val"
line.long 0x78 "dma_tbu_stream_id_Ax_reg_0_dma1"
hexmask.long.word 0x78 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x78 0.--15. 1. "wmmusid_reg_val"
line.long 0x7C "sdm_tbu_stream_id_Ax_reg_1_sdm"
hexmask.long.word 0x7C 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x7C 0.--15. 1. "wmmusid_reg_val"
line.long 0x80 "io_tbu_stream_id_Ax_reg_2_usb2"
hexmask.long.word 0x80 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x80 0.--15. 1. "wmmusid_reg_val"
line.long 0x84 "io_tbu_stream_id_Ax_reg_2_usb3"
hexmask.long.word 0x84 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x84 0.--15. 1. "wmmusid_reg_val"
line.long 0x88 "io_tbu_stream_id_Ax_reg_2_sdmmc"
hexmask.long.word 0x88 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x88 0.--15. 1. "wmmusid_reg_val"
line.long 0x8C "io_tbu_stream_id_Ax_reg_2_nand"
hexmask.long.word 0x8C 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x8C 0.--15. 1. "wmmusid_reg_val"
line.long 0x90 "io_tbu_stream_id_Ax_reg_2_etr"
hexmask.long.word 0x90 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x90 0.--15. 1. "wmmusid_reg_val"
line.long 0x94 "tsn_tbu_stream_id_Ax_reg_3_tsn0"
hexmask.long.word 0x94 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x94 0.--15. 1. "wmmusid_reg_val"
line.long 0x98 "tsn_tbu_stream_id_Ax_reg_3_tsn1"
hexmask.long.word 0x98 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x98 0.--15. 1. "wmmusid_reg_val"
line.long 0x9C "tsn_tbu_stream_id_Ax_reg_3_tsn2"
hexmask.long.word 0x9C 16.--31. 1. "rmmusid_reg_val"
newline
hexmask.long.word 0x9C 0.--15. 1. "wmmusid_reg_val"
group.long 0x1F0++0x7
line.long 0x0 "usb3_misc_ctrl_reg0"
bitfld.long 0x0 31. "bigendian_gs" "0,1"
newline
hexmask.long.byte 0x0 27.--30. 1. "devspd_ovrd"
newline
hexmask.long.byte 0x0 23.--26. 1. "bus_filter_bypass"
newline
hexmask.long.byte 0x0 17.--22. 1. "fladj_30mhz_reg"
newline
bitfld.long 0x0 15.--16. "port_perm_attach" "0,1,2,3"
newline
bitfld.long 0x0 13.--14. "port_overcurrent" "0,1,2,3"
newline
bitfld.long 0x0 12. "reset_pulse_ovrd" "0,1"
newline
bitfld.long 0x0 11. "xhc_bme" "0,1"
newline
bitfld.long 0x0 10. "force_gen1_speed" "0,1"
newline
bitfld.long 0x0 9. "u3_disable_port" "0,1"
newline
bitfld.long 0x0 8. "u2_disable_port" "0,1"
newline
hexmask.long.byte 0x0 4.--7. 1. "num_u3_port"
newline
hexmask.long.byte 0x0 0.--3. 1. "num_u2_port"
line.long 0x4 "usb3_misc_ctrl_reg1"
hexmask.long 0x4 0.--31. 1. "val"
group.long 0x200++0x2B
line.long 0x0 "boot_scratch_cold0,Boot scratch register 0"
hexmask.long 0x0 0.--31. 1. "val,the scratch register value"
line.long 0x4 "boot_scratch_cold1,Boot scratch register 1"
hexmask.long 0x4 0.--31. 1. "val,the scratch register value"
line.long 0x8 "boot_scratch_cold2,Boot scratch register 2"
hexmask.long 0x8 0.--31. 1. "val,the scratch register value"
line.long 0xC "boot_scratch_cold3,Boot scratch register 3"
hexmask.long 0xC 0.--31. 1. "val,the scratch register value"
line.long 0x10 "boot_scratch_cold4,Boot scratch register 4"
hexmask.long 0x10 0.--31. 1. "val,the scratch register value"
line.long 0x14 "boot_scratch_cold5,Boot scratch register 5"
hexmask.long 0x14 0.--31. 1. "val,the scratch register value"
line.long 0x18 "boot_scratch_cold6,Boot scratch register 6"
hexmask.long 0x18 0.--31. 1. "val,the scratch register value"
line.long 0x1C "boot_scratch_cold7,Boot scratch register 7"
hexmask.long 0x1C 0.--31. 1. "val,the scratch register value"
line.long 0x20 "boot_scratch_cold8,Boot scratch register 8"
hexmask.long 0x20 0.--31. 1. "val,the scratch register value"
line.long 0x24 "boot_scratch_cold9,Boot scratch register 9"
hexmask.long 0x24 0.--31. 1. "val,the scratch register value"
line.long 0x28 "mpfe_config,MPFE Interface Select"
hexmask.long.word 0x28 16.--31. 1. "Reserved_10,Reserved bitfield added by Magillem"
newline
hexmask.long.byte 0x28 9.--15. 1. "mpfe_config_spare,The spare MPFE - HPS spare ports and registers are implemented as a contingency in the event MPFE-Fabric-IO96-HMC issues arise that need management by HPS or SDM firmware."
newline
bitfld.long 0x28 8. "mpfe_lite_active,0 = mpfe_lite active" "0: mpfe_lite active,1: mpfe_lite not active"
newline
bitfld.long 0x28 7. "mpfe_f2sdram_active,0 = mpfe_f2sdram active" "0: mpfe_f2sdram active,1: mpfe_f2sdram not active"
newline
bitfld.long 0x28 6. "mpfe_f2soc_active,0 =mpfe_f2soc not active" "0: mpfe_f2soc not active,1: mpfe_f2soc active"
newline
bitfld.long 0x28 5. "mpfe_io96b_csr_clk_enable,mpfe_io96b_csr_clk_enable" "0: not enabled,1: enabled"
newline
bitfld.long 0x28 4. "mpfe_io96b_p1_clk_enable,mpfe_io96b_p1_clk_enable" "0: not enabled,1: enabled"
newline
bitfld.long 0x28 3. "mpfe_io96b_p0_clk_enable,mpfe_io96b_p0_clk_enable" "?,1: enabled"
newline
bitfld.long 0x28 2. "mpfe_lite_intfcsel,0 = don't select mpfe_lite" "0: don't select mpfe_lite,1: select mpfe_lite"
newline
bitfld.long 0x28 1. "f2sdram_intfcsel,0 = don't select f2dram" "0: don't select f2dram,1: select f2sdram"
newline
bitfld.long 0x28 0. "f2soc_intfcsel,0 = don't select f2soc" "0: don't select f2soc,1: select f2soc"
rgroup.long 0x22C++0x3
line.long 0x0 "mpfe_status"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "mpfeintfc_stat_spare_in"
group.long 0x230++0x57
line.long 0x0 "boot_scratch_warm0,Boot scratch register 0"
hexmask.long 0x0 0.--31. 1. "val,the scratch register value"
line.long 0x4 "boot_scratch_warm1,Boot scratch register 1"
hexmask.long 0x4 0.--31. 1. "val,the scratch register value"
line.long 0x8 "boot_scratch_warm2,Boot scratch register 2"
hexmask.long 0x8 0.--31. 1. "val,the scratch register value"
line.long 0xC "boot_scratch_warm3,Boot scratch register 3"
hexmask.long 0xC 0.--31. 1. "val,the scratch register value"
line.long 0x10 "boot_scratch_warm4,Boot scratch register 4"
hexmask.long 0x10 0.--31. 1. "val,the scratch register value"
line.long 0x14 "boot_scratch_warm5,Boot scratch register 5"
hexmask.long 0x14 0.--31. 1. "val,the scratch register value"
line.long 0x18 "boot_scratch_warm6,Boot scratch register 6"
hexmask.long 0x18 0.--31. 1. "val,the scratch register value"
line.long 0x1C "boot_scratch_warm7,Boot scratch register 7"
hexmask.long 0x1C 0.--31. 1. "val,the scratch register value"
line.long 0x20 "boot_scratch_warm8,Boot scratch register 8"
hexmask.long 0x20 0.--31. 1. "val,the scratch register value"
line.long 0x24 "boot_scratch_warm9,Boot scratch register 9"
hexmask.long.tbyte 0x24 12.--31. 1. "val2"
newline
hexmask.long.byte 0x24 8.--11. 1. "val1"
newline
hexmask.long.byte 0x24 0.--7. 1. "val0,the scratch register value"
line.long 0x28 "boot_scratch_por0,Boot scratch register 0"
hexmask.long 0x28 0.--31. 1. "val,the scratch register value"
line.long 0x2C "boot_scratch_por1,Boot scratch register 1"
hexmask.long 0x2C 0.--31. 1. "val,the scratch register value"
line.long 0x30 "boot_scratch_por2,Boot scratch register 2"
hexmask.long 0x30 0.--31. 1. "val,the scratch register value"
line.long 0x34 "boot_scratch_por3,Boot scratch register 3"
hexmask.long 0x34 0.--31. 1. "val,the scratch register value"
line.long 0x38 "boot_scratch_por4,Boot scratch register 4"
hexmask.long 0x38 0.--31. 1. "val,the scratch register value"
line.long 0x3C "boot_scratch_por5,Boot scratch register 5"
hexmask.long 0x3C 0.--31. 1. "val,the scratch register value"
line.long 0x40 "boot_scratch_por6,Boot scratch register 6"
hexmask.long 0x40 0.--31. 1. "val,the scratch register value"
line.long 0x44 "boot_scratch_por7,Boot scratch register 7"
hexmask.long 0x44 0.--31. 1. "val,the scratch register value"
line.long 0x48 "boot_scratch_por8,Boot scratch register 8"
hexmask.long 0x48 0.--31. 1. "val,the scratch register value"
line.long 0x4C "boot_scratch_por9,Boot scratch register 9"
hexmask.long 0x4C 0.--31. 1. "val,the scratch register value"
line.long 0x50 "sdm_be_awaddr_remap"
hexmask.long 0x50 0.--31. 1. "val,based address for SDM to access to OCRAM"
line.long 0x54 "sdm_be_araddr_remap"
hexmask.long 0x54 0.--31. 1. "val"
tree.end
tree "TIMERS"
base ad:0x0
tree "TIMER_SP_0"
base ad:0x10C03000
group.long 0x0++0x3
line.long 0x0 "TIMER1LOADCOUNT,Name: Timer1 Load Count Register"
hexmask.long 0x0 0.--31. 1. "TIMER1LOADCOUNT,Value to be loaded into Timer1. This is the value from which counting"
rgroup.long 0x4++0x3
line.long 0x0 "TIMER1CURRENTVAL,Name: Timer1 Current Value"
hexmask.long 0x0 0.--31. 1. "TIMER1CURRENTVAL,Current Value of Timer1. This register is supported only"
group.long 0x8++0x3
line.long 0x0 "TIMER1CONTROLREG,Name: Timer1 Control Register"
hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 2. "TIMER_INTERRUPT_MASK,Timer interrupt mask for Timer1." "0: not masked,1: masked"
newline
bitfld.long 0x0 1. "TIMER_MODE,Timer mode for Timer1." "0: free_running mode,1: user_defined count mode"
bitfld.long 0x0 0. "TIMER_ENABLE,Timer enable bit for Timer1." "0: disable,1: enable"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER1EOI,Name: Timer1 End-of-Interrupt Register"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "TIMER1EOI,Reading from this register" "0,1"
line.long 0x4 "TIMER1INTSTAT,Name: Timer1 Interrupt Status Register"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "TIMER1INTSTAT,Contains the interrupt status for Timer1." "0,1"
rgroup.long 0xA0++0xF
line.long 0x0 "TIMERSINTSTAT,Name: Timers Interrupt Status Register"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "TIMERSINTSTAT,Contains the interrupt status of all timers in the component. If a bit of" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0x4 "TIMERSEOI,Name: Timers End-of-Interrupt Register"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "TIMERSEOI,Reading this register returns all zeroes (0) and clears all active" "0,1"
line.long 0x8 "TIMERSRAWINTSTAT,Name: Timers Raw Interrupt Status Register"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "TIMERSRAWINTSTAT,The register contains the unmasked interrupt status of all timers in" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0xC "TIMERSCOMPVERSION,Name: Timers Component Version"
hexmask.long 0xC 0.--31. 1. "TIMERSCOMPVERSION,Current revision number of the DW_apb_timers component."
tree.end
tree "TIMER_SP_1"
base ad:0x10C03100
group.long 0x0++0x3
line.long 0x0 "TIMER1LOADCOUNT,Name: Timer1 Load Count Register"
hexmask.long 0x0 0.--31. 1. "TIMER1LOADCOUNT,Value to be loaded into Timer1. This is the value from which counting"
rgroup.long 0x4++0x3
line.long 0x0 "TIMER1CURRENTVAL,Name: Timer1 Current Value"
hexmask.long 0x0 0.--31. 1. "TIMER1CURRENTVAL,Current Value of Timer1. This register is supported only"
group.long 0x8++0x3
line.long 0x0 "TIMER1CONTROLREG,Name: Timer1 Control Register"
hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 2. "TIMER_INTERRUPT_MASK,Timer interrupt mask for Timer1." "0: not masked,1: masked"
newline
bitfld.long 0x0 1. "TIMER_MODE,Timer mode for Timer1." "0: free_running mode,1: user_defined count mode"
bitfld.long 0x0 0. "TIMER_ENABLE,Timer enable bit for Timer1." "0: disable,1: enable"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER1EOI,Name: Timer1 End-of-Interrupt Register"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "TIMER1EOI,Reading from this register" "0,1"
line.long 0x4 "TIMER1INTSTAT,Name: Timer1 Interrupt Status Register"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "TIMER1INTSTAT,Contains the interrupt status for Timer1." "0,1"
rgroup.long 0xA0++0xF
line.long 0x0 "TIMERSINTSTAT,Name: Timers Interrupt Status Register"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "TIMERSINTSTAT,Contains the interrupt status of all timers in the component. If a bit of" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0x4 "TIMERSEOI,Name: Timers End-of-Interrupt Register"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "TIMERSEOI,Reading this register returns all zeroes (0) and clears all active" "0,1"
line.long 0x8 "TIMERSRAWINTSTAT,Name: Timers Raw Interrupt Status Register"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "TIMERSRAWINTSTAT,The register contains the unmasked interrupt status of all timers in" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0xC "TIMERSCOMPVERSION,Name: Timers Component Version"
hexmask.long 0xC 0.--31. 1. "TIMERSCOMPVERSION,Current revision number of the DW_apb_timers component."
tree.end
tree "TIMER_SYS_0"
base ad:0x10D00000
group.long 0x0++0x3
line.long 0x0 "TIMER1LOADCOUNT,Name: Timer1 Load Count Register"
hexmask.long 0x0 0.--31. 1. "TIMER1LOADCOUNT,Value to be loaded into Timer1. This is the value from which counting"
rgroup.long 0x4++0x3
line.long 0x0 "TIMER1CURRENTVAL,Name: Timer1 Current Value"
hexmask.long 0x0 0.--31. 1. "TIMER1CURRENTVAL,Current Value of Timer1. This register is supported only"
group.long 0x8++0x3
line.long 0x0 "TIMER1CONTROLREG,Name: Timer1 Control Register"
hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 2. "TIMER_INTERRUPT_MASK,Timer interrupt mask for Timer1." "0: not masked,1: masked"
newline
bitfld.long 0x0 1. "TIMER_MODE,Timer mode for Timer1." "0: free_running mode,1: user_defined count mode"
bitfld.long 0x0 0. "TIMER_ENABLE,Timer enable bit for Timer1." "0: disable,1: enable"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER1EOI,Name: Timer1 End-of-Interrupt Register"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "TIMER1EOI,Reading from this register" "0,1"
line.long 0x4 "TIMER1INTSTAT,Name: Timer1 Interrupt Status Register"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "TIMER1INTSTAT,Contains the interrupt status for Timer1." "0,1"
rgroup.long 0xA0++0xF
line.long 0x0 "TIMERSINTSTAT,Name: Timers Interrupt Status Register"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "TIMERSINTSTAT,Contains the interrupt status of all timers in the component. If a bit of" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0x4 "TIMERSEOI,Name: Timers End-of-Interrupt Register"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "TIMERSEOI,Reading this register returns all zeroes (0) and clears all active" "0,1"
line.long 0x8 "TIMERSRAWINTSTAT,Name: Timers Raw Interrupt Status Register"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "TIMERSRAWINTSTAT,The register contains the unmasked interrupt status of all timers in" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0xC "TIMERSCOMPVERSION,Name: Timers Component Version"
hexmask.long 0xC 0.--31. 1. "TIMERSCOMPVERSION,Current revision number of the DW_apb_timers component."
tree.end
tree "TIMER_SYS_1"
base ad:0x10D00100
group.long 0x0++0x3
line.long 0x0 "TIMER1LOADCOUNT,Name: Timer1 Load Count Register"
hexmask.long 0x0 0.--31. 1. "TIMER1LOADCOUNT,Value to be loaded into Timer1. This is the value from which counting"
rgroup.long 0x4++0x3
line.long 0x0 "TIMER1CURRENTVAL,Name: Timer1 Current Value"
hexmask.long 0x0 0.--31. 1. "TIMER1CURRENTVAL,Current Value of Timer1. This register is supported only"
group.long 0x8++0x3
line.long 0x0 "TIMER1CONTROLREG,Name: Timer1 Control Register"
hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 2. "TIMER_INTERRUPT_MASK,Timer interrupt mask for Timer1." "0: not masked,1: masked"
newline
bitfld.long 0x0 1. "TIMER_MODE,Timer mode for Timer1." "0: free_running mode,1: user_defined count mode"
bitfld.long 0x0 0. "TIMER_ENABLE,Timer enable bit for Timer1." "0: disable,1: enable"
rgroup.long 0xC++0x7
line.long 0x0 "TIMER1EOI,Name: Timer1 End-of-Interrupt Register"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "TIMER1EOI,Reading from this register" "0,1"
line.long 0x4 "TIMER1INTSTAT,Name: Timer1 Interrupt Status Register"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "TIMER1INTSTAT,Contains the interrupt status for Timer1." "0,1"
rgroup.long 0xA0++0xF
line.long 0x0 "TIMERSINTSTAT,Name: Timers Interrupt Status Register"
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "TIMERSINTSTAT,Contains the interrupt status of all timers in the component. If a bit of" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0x4 "TIMERSEOI,Name: Timers End-of-Interrupt Register"
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "TIMERSEOI,Reading this register returns all zeroes (0) and clears all active" "0,1"
line.long 0x8 "TIMERSRAWINTSTAT,Name: Timers Raw Interrupt Status Register"
hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x8 0. "TIMERSRAWINTSTAT,The register contains the unmasked interrupt status of all timers in" "0: either timer_intr or timer_intr_n is not active..,1: either timer_intr or timer_intr_n is active.."
line.long 0xC "TIMERSCOMPVERSION,Name: Timers Component Version"
hexmask.long 0xC 0.--31. 1. "TIMERSCOMPVERSION,Current revision number of the DW_apb_timers component."
tree.end
tree.end
tree "UART (UART Controller)"
base ad:0x0
tree "UART_0"
base ad:0x10C02000
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_RBR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "rbr,Receive Buffer Register:"
group.long 0x0++0x3
line.long 0x0 "DLL,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLL_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "dll,Divisor Latch (Low):"
group.long 0x0++0x7
line.long 0x0 "THR,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_THR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "thr,Transmit Holding Register:"
line.long 0x4 "IER,Interrupt Enable Register:"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IER_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "PTIME,Interrupt Enable Register: PTIME  Programmable THRE Interrupt Mode Enable." "0: disabled,1: enabled"
newline
rbitfld.long 0x4 4.--6. "RSVD_IER_6to4,Reserved bits [6:4] - Read Only" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "EDSSI,Interrupt Enable Register: EDSSI  Enable Modem Status Interrupt." "0: disabled,1: enabled"
newline
bitfld.long 0x4 2. "ELSI,Interrupt Enable Register: ELSI  Enable Receiver Line Status Interrupt." "0: disabled,1: enabled"
bitfld.long 0x4 1. "ETBEI,Interrupt Enable Register: ETBEI  Enable Transmit Holding Register Empty Interrupt." "0: disabled,1: enabled"
newline
bitfld.long 0x4 0. "ERBFI,Interrupt Enable Register: ERBFI  Enable Received Data Available Interrupt." "0: disabled,1: enabled"
group.long 0x4++0x3
line.long 0x0 "DLH,Divisor Latch High (DLH) Register."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLH_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "dlh,Divisor Latch High 8-bit register field - used to set the UART baud-rate"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,Interrupt Identification Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IIR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 6.--7. "FIFOSE,Bits[7:6]  FIFO's Enabled (or FIFOSE):" "0: disabled,?,?,?"
newline
bitfld.long 0x0 4.--5. "RSVD_IIR_5to4,Reserved bits [5:4] - Read Only" "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "IID,Bits[3:0]  Interrupt ID (or IID):"
group.long 0x8++0xB
line.long 0x0 "FCR,FIFO Control Register."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_FCR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 6.--7. "RT,Bits[7:6]  RCVR Trigger (or RT):." "0: 1 character in the FIFO,1: FIFO 1/4 full,?,?"
newline
bitfld.long 0x0 4.--5. "TET,Bits[5:4]  TX Empty Trigger (or TET):" "0: FIFO empty,1: 2 characters in the FIFO,?,?"
bitfld.long 0x0 3. "DMAM,Bit[3]  DMA Mode (or DMAM):" "0: mode 0,1: mode 1"
newline
bitfld.long 0x0 2. "XFIFOR,Bit[2]  XMIT FIFO Reset (or XFIFOR):" "0,1"
bitfld.long 0x0 1. "RFIFOR,Bit[1]  RCVR FIFO Reset (or RFIFOR):" "0,1"
newline
bitfld.long 0x0 0. "FIFOE,Bit[0]  FIFO Enable (or FIFOE):" "0,1"
line.long 0x4 "LCR,Line Control Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_LCR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "DLAB,Divisor Latch Access Bit." "0,1"
newline
bitfld.long 0x4 6. "Break,Break Control Bit." "0,1"
bitfld.long 0x4 5. "SP,From DW_apb_uart_regfile.sv:" "0,1"
newline
bitfld.long 0x4 4. "EPS,Even Parity Select." "0,1"
bitfld.long 0x4 3. "PEN,Parity Enable." "0: parity disabled,1: parity enabled"
newline
bitfld.long 0x4 2. "STOP,Number of stop bits." "0: 1 stop bit,1: 1"
bitfld.long 0x4 0.--1. "DLS,Data Length Select." "0: 5 bits,1: 6 bits,?,?"
line.long 0x8 "MCR,Modem Control Register"
hexmask.long 0x8 7.--31. 1. "RSVD_MCR_31to7,Reserved bits [31:7] - Read Only"
rbitfld.long 0x8 6. "SIRE,SIR Mode Enable." "0: IrDA SIR Mode disabled,1: IrDA SIR Mode enabled"
newline
bitfld.long 0x8 5. "AFCE,Auto Flow Control Enable." "0: Auto Flow Control Mode disabled,1: Auto Flow Control Mode enabled"
bitfld.long 0x8 4. "LoopBack,LoopBack Bit." "0,1"
newline
bitfld.long 0x8 3. "OUT2,OUT2." "0: out2_n de-asserted,1: out2_n asserted"
bitfld.long 0x8 2. "OUT1,OUT1." "0: out1_n de-asserted,1: out1_n asserted"
newline
bitfld.long 0x8 1. "RTS,Request to Send." "0,1"
bitfld.long 0x8 0. "DTR,Data Terminal Ready." "0: dtr_n de-asserted,1: dtr_n asserted"
rgroup.long 0x14++0x7
line.long 0x0 "LSR,Line Status Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_LSR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 7. "RFE,Receiver FIFO Error bit." "0: no error in RX FIFO,1: error in RX FIFO"
newline
bitfld.long 0x0 6. "TEMT,Transmitter Empty bit." "0,1"
bitfld.long 0x0 5. "THRE,Transmit Holding Register Empty bit." "0,1"
newline
bitfld.long 0x0 4. "BI,Break Interrupt bit." "0,1"
bitfld.long 0x0 3. "FE,Framing Error bit." "0: no framing error,1: framing error"
newline
bitfld.long 0x0 2. "PE,Parity Error bit." "0: no parity error,1: parity error"
bitfld.long 0x0 1. "OE,Overrun error bit." "0: no overrun error,1: overrun error"
newline
bitfld.long 0x0 0. "DR,Data Ready bit." "0: no data ready,1: data ready"
line.long 0x4 "MSR,Modem Status Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_MSR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "DCD,Data Carrier Detect." "0: dcd_n input is de-asserted,1: dcd_n input is asserted"
newline
bitfld.long 0x4 6. "RI,Ring Indicator." "0: ri_n input is de-asserted,1: ri_n input is asserted"
bitfld.long 0x4 5. "DSR,Data Set Ready." "0: dsr_n input is de-asserted,1: dsr_n input is asserted"
newline
bitfld.long 0x4 4. "CTS,Clear to Send." "0: cts_n input is de-asserted,1: cts_n input is asserted"
bitfld.long 0x4 3. "DDCD,Delta Data Carrier Detect." "0: no change on dcd_n since last read of MSR,1: change on dcd_n since last read of MSR"
newline
bitfld.long 0x4 2. "TERI,Trailing Edge of Ring Indicator." "0: no change on ri_n since last read of MSR,1: change on ri_n since last read of MSR"
bitfld.long 0x4 1. "DDSR,Delta Data Set Ready." "0: no change on dsr_n since last read of MSR,1: change on dsr_n since last read of MSR"
newline
bitfld.long 0x4 0. "DCTS,Delta Clear to Send." "0: no change on cts_n since last read of MSR,1: change on cts_n since last read of MSR"
group.long 0x1C++0x3
line.long 0x0 "SCR,Scratchpad Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SCR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "scr,This register is for programmers to use as a temporary storage space. It has no"
rgroup.long 0x30++0x3
line.long 0x0 "SRBR0,Shadow Receive Buffer Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR0_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr0,Shadow Receive Buffer Register 0:"
group.long 0x30++0x3
line.long 0x0 "STHR0,Shadow Transmit Holding Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR0_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr0,Shadow Transmit Holding Register 0:"
rgroup.long 0x34++0x3
line.long 0x0 "SRBR1,Shadow Receive Buffer Register 1"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR1_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr1,See srbr0 description"
group.long 0x34++0x3
line.long 0x0 "STHR1,Shadow Transmit Holding Register 1"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR1_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr1,See sthr0 description."
rgroup.long 0x38++0x3
line.long 0x0 "SRBR2,Shadow Receive Buffer Register 2"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR2_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr2,See srbr0 description"
group.long 0x38++0x3
line.long 0x0 "STHR2,Shadow Transmit Holding Register 2"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR2_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr2,See sthr0 description."
rgroup.long 0x3C++0x3
line.long 0x0 "SRBR3,Shadow Receive Buffer Register 3"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR3_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr3,See srbr0 description"
group.long 0x3C++0x3
line.long 0x0 "STHR3,Shadow Transmit Holding Register 3"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR3_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr3,See sthr0 description."
rgroup.long 0x40++0x3
line.long 0x0 "SRBR4,Shadow Receive Buffer Register 4"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR4_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr4,See srbr0 description"
group.long 0x40++0x3
line.long 0x0 "STHR4,Shadow Transmit Holding Register 4"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR4_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr4,See sthr0 description."
rgroup.long 0x44++0x3
line.long 0x0 "SRBR5,Shadow Receive Buffer Register 5"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR5_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr5,See srbr0 description"
group.long 0x44++0x3
line.long 0x0 "STHR5,Shadow Transmit Holding Register 5"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR5_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr5,See sthr0 description."
rgroup.long 0x48++0x3
line.long 0x0 "SRBR6,Shadow Receive Buffer Register 6"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR6_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr6,See srbr0 description"
group.long 0x48++0x3
line.long 0x0 "STHR6,Shadow Transmit Holding Register 6"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR6_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr6,See sthr0 description."
rgroup.long 0x4C++0x3
line.long 0x0 "SRBR7,Shadow Receive Buffer Register 7"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR7_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr7,See srbr0 description"
group.long 0x4C++0x3
line.long 0x0 "STHR7,Shadow Transmit Holding Register 7"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR7_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr7,See sthr0 description."
rgroup.long 0x50++0x3
line.long 0x0 "SRBR8,Shadow Receive Buffer Register 8"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR8_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr8,See srbr0 description"
group.long 0x50++0x3
line.long 0x0 "STHR8,Shadow Transmit Holding Register 8"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR8_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr8,See sthr0 description."
rgroup.long 0x54++0x3
line.long 0x0 "SRBR9,Shadow Receive Buffer Register 9"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR9_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr9,See srbr0 description"
group.long 0x54++0x3
line.long 0x0 "STHR9,Shadow Transmit Holding Register 9"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR9_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr9,See sthr0 description."
rgroup.long 0x58++0x3
line.long 0x0 "SRBR10,Shadow Receive Buffer Register 10"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR10_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr10,See srbr0 description"
group.long 0x58++0x3
line.long 0x0 "STHR10,Shadow Transmit Holding Register 10"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR10_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr10,See sthr0 description."
rgroup.long 0x5C++0x3
line.long 0x0 "SRBR11,Shadow Receive Buffer Register 11"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR11_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr11,See srbr0 description"
group.long 0x5C++0x3
line.long 0x0 "STHR11,Shadow Transmit Holding Register 11"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR11_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr11,See sthr0 description."
rgroup.long 0x60++0x3
line.long 0x0 "SRBR12,Shadow Receive Buffer Register 12"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR12_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr12,See srbr0 description"
group.long 0x60++0x3
line.long 0x0 "STHR12,Shadow Transmit Holding Register 12"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR12_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr12,See sthr0 description."
rgroup.long 0x64++0x3
line.long 0x0 "SRBR13,Shadow Receive Buffer Register 13"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR13_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr13,See srbr0 description"
group.long 0x64++0x3
line.long 0x0 "STHR13,Shadow Transmit Holding Register 13"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR13_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr13,See sthr0 description."
rgroup.long 0x68++0x3
line.long 0x0 "SRBR14,Shadow Receive Buffer Register 14"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR14_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr14,See srbr0 description"
group.long 0x68++0x3
line.long 0x0 "STHR14,Shadow Transmit Holding Register 14"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR14_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr14,See sthr0 description."
rgroup.long 0x6C++0x3
line.long 0x0 "SRBR15,Shadow Receive Buffer Register 15"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR15_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr15,See srbr0 description"
group.long 0x6C++0x7
line.long 0x0 "STHR15,Shadow Transmit Holding Register 15"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR15_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr15,See sthr0 description."
line.long 0x4 "FAR,FIFO Access Register"
hexmask.long 0x4 1.--31. 1. "RSVD_FAR_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x4 0. "far,Writes will have no effect when FIFO_ACCESS == No  always readable. This register" "0: FIFO access mode disabled,1: FIFO access mode enabled"
rgroup.long 0x74++0x3
line.long 0x0 "TFR,Transmit FIFO Read"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TFR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "tfr,Transmit FIFO Read."
group.long 0x78++0x3
line.long 0x0 "RFW,Receive FIFO Write"
hexmask.long.tbyte 0x0 10.--31. 1. "RSVD_RFW_31to10,Reserved bits [31:10] - Read Only"
bitfld.long 0x0 9. "RFFE,Receive FIFO Framing Error." "0,1"
newline
bitfld.long 0x0 8. "RFPE,Receive FIFO Parity Error." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "RFWD,Receive FIFO Write Data."
rgroup.long 0x7C++0xB
line.long 0x0 "USR,UART Status register."
hexmask.long 0x0 5.--31. 1. "RSVD_USR_31to5,Reserved bits [31:5] - Read Only"
bitfld.long 0x0 4. "RFF,Receive FIFO Full." "0: Receive FIFO not full,1: Receive FIFO Full"
newline
bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
bitfld.long 0x0 2. "TFE,Transmit FIFO Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 0. "RSVD_BUSY,UART Busy." "0,1"
line.long 0x4 "TFL,Transmit FIFO Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_TFL_31toADDR_WIDTH,Reserved bits: 31 downto addr bus width + 1 - Read Only"
hexmask.long.byte 0x4 0.--7. 1. "tfl,Transmit FIFO Level."
line.long 0x8 "RFL,Receive FIFO Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_RFL_31toADDR_WIDTH,Reserved bits: 31 downnto addr bus width + 1 - Read Only"
hexmask.long.byte 0x8 0.--7. 1. "rfl,Receive FIFO Level."
group.long 0x88++0x23
line.long 0x0 "SRR,Software Reset Register."
hexmask.long 0x0 3.--31. 1. "RSVD_SRR_31to3,Reserved bits [31:3] - Read Only"
bitfld.long 0x0 2. "XFR,XMIT FIFO Reset." "0,1"
newline
bitfld.long 0x0 1. "RFR,RCVR FIFO Reset." "0,1"
bitfld.long 0x0 0. "UR,UART Reset." "0,1"
line.long 0x4 "SRTS,Shadow Request to Send."
hexmask.long 0x4 1.--31. 1. "RSVD_SRTS_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x4 0. "srts,Shadow Request to Send." "0,1"
line.long 0x8 "SBCR,Shadow Break Control Register."
hexmask.long 0x8 1.--31. 1. "RSVD_SBCR_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x8 0. "sbcb,Shadow Break Control Bit." "0,1"
line.long 0xC "SDMAM,Shadow DMA Mode."
hexmask.long 0xC 1.--31. 1. "RSVD_SDMAM_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0xC 0. "sdmam,Shadow DMA Mode." "0: mode 0,1: mode 1"
line.long 0x10 "SFE,Shadow FIFO Enable"
hexmask.long 0x10 1.--31. 1. "RSVD_SFE_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x10 0. "sfe,Shadow FIFO Enable." "0,1"
line.long 0x14 "SRT,Shadow RCVR Trigger"
hexmask.long 0x14 2.--31. 1. "RSVD_SRT_31to2,Reserved bits [31:2] - Read Only"
bitfld.long 0x14 0.--1. "srt,Shadow RCVR Trigger." "0: 1 character in the FIFO,1: FIFO 1/4 full,?,?"
line.long 0x18 "STET,Shadow TX Empty Trigger"
hexmask.long 0x18 2.--31. 1. "RSVD_STET_31to2,Reserved bits [31:2] - Read Only"
bitfld.long 0x18 0.--1. "stet,Shadow TX Empty Trigger." "0: FIFO empty,1: 2 characters in the FIFO,?,?"
line.long 0x1C "HTX,Halt TX"
hexmask.long 0x1C 1.--31. 1. "RSVD_HTX_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x1C 0. "htx,Halt TX." "0: Halt TX disabled,1: Halt TX enabled"
line.long 0x20 "DMASA,DMA Software Acknowledge"
hexmask.long 0x20 1.--31. 1. "RSVD_DMASA_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x20 0. "dmasa,DMA Software Acknowledge." "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "CPR,Component Parameter Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_CPR_31to24,Reserved bits [31:24] - Read Only"
hexmask.long.byte 0x0 16.--23. 1. "FIFO_MODE,Encoding of FIFO_MODE configuration parameter value.DW_apb_uart.ralf"
newline
bitfld.long 0x0 14.--15. "RSVD_CPR_15to14,Reserved bits [15:14] - Read Only" "0,1,2,3"
bitfld.long 0x0 13. "DMA_EXTRA,Encoding of DMA_EXTRA configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 12. "UART_ADD_ENCODED_PARAMS,Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 11. "SHADOW,Encoding of SHADOW configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 10. "FIFO_STAT,Encoding of FIFO_STAT configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 9. "FIFO_ACCESS,Encoding of FIFO_ACCESS configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 8. "ADDITIONAL_FEAT,Encoding of ADDITIONAL_FEATURES configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 7. "SIR_LP_MODE,Encoding of SIR_LP_MODE configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 6. "SIR_MODE,Encoding of SIR_MODE configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 5. "THRE_MODE,Encoding of THRE_MODE configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 4. "AFCE_MODE,Encoding of AFCE_MODE configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 2.--3. "RSVD_CPR_3to2,Reserved bits [3:2] - Read Only" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,Encoding of APB_DATA_WIDTH configuration parameter value." "0: 8 bits,1: 16 bits,?,?"
line.long 0x4 "UCV,Component Version"
hexmask.long 0x4 0.--31. 1. "UART_Component_Version,ASCII value for each number in the version  followed by *."
line.long 0x8 "CTR,Component Type Register"
hexmask.long 0x8 0.--31. 1. "Peripheral_ID,This register contains the peripherals identification code."
tree.end
tree "UART_1"
base ad:0x10C02100
rgroup.long 0x0++0x3
line.long 0x0 "RBR,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_RBR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "rbr,Receive Buffer Register:"
group.long 0x0++0x3
line.long 0x0 "DLL,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLL_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "dll,Divisor Latch (Low):"
group.long 0x0++0x7
line.long 0x0 "THR,Receive Buffer Register. reading this register when the DLAB bit is zero;"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_THR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "thr,Transmit Holding Register:"
line.long 0x4 "IER,Interrupt Enable Register:"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IER_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "PTIME,Interrupt Enable Register: PTIME  Programmable THRE Interrupt Mode Enable." "0: disabled,1: enabled"
newline
rbitfld.long 0x4 4.--6. "RSVD_IER_6to4,Reserved bits [6:4] - Read Only" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. "EDSSI,Interrupt Enable Register: EDSSI  Enable Modem Status Interrupt." "0: disabled,1: enabled"
newline
bitfld.long 0x4 2. "ELSI,Interrupt Enable Register: ELSI  Enable Receiver Line Status Interrupt." "0: disabled,1: enabled"
bitfld.long 0x4 1. "ETBEI,Interrupt Enable Register: ETBEI  Enable Transmit Holding Register Empty Interrupt." "0: disabled,1: enabled"
newline
bitfld.long 0x4 0. "ERBFI,Interrupt Enable Register: ERBFI  Enable Received Data Available Interrupt." "0: disabled,1: enabled"
group.long 0x4++0x3
line.long 0x0 "DLH,Divisor Latch High (DLH) Register."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLH_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "dlh,Divisor Latch High 8-bit register field - used to set the UART baud-rate"
rgroup.long 0x8++0x3
line.long 0x0 "IIR,Interrupt Identification Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IIR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 6.--7. "FIFOSE,Bits[7:6]  FIFO's Enabled (or FIFOSE):" "0: disabled,?,?,?"
newline
bitfld.long 0x0 4.--5. "RSVD_IIR_5to4,Reserved bits [5:4] - Read Only" "0,1,2,3"
hexmask.long.byte 0x0 0.--3. 1. "IID,Bits[3:0]  Interrupt ID (or IID):"
group.long 0x8++0xB
line.long 0x0 "FCR,FIFO Control Register."
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_FCR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 6.--7. "RT,Bits[7:6]  RCVR Trigger (or RT):." "0: 1 character in the FIFO,1: FIFO 1/4 full,?,?"
newline
bitfld.long 0x0 4.--5. "TET,Bits[5:4]  TX Empty Trigger (or TET):" "0: FIFO empty,1: 2 characters in the FIFO,?,?"
bitfld.long 0x0 3. "DMAM,Bit[3]  DMA Mode (or DMAM):" "0: mode 0,1: mode 1"
newline
bitfld.long 0x0 2. "XFIFOR,Bit[2]  XMIT FIFO Reset (or XFIFOR):" "0,1"
bitfld.long 0x0 1. "RFIFOR,Bit[1]  RCVR FIFO Reset (or RFIFOR):" "0,1"
newline
bitfld.long 0x0 0. "FIFOE,Bit[0]  FIFO Enable (or FIFOE):" "0,1"
line.long 0x4 "LCR,Line Control Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_LCR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "DLAB,Divisor Latch Access Bit." "0,1"
newline
bitfld.long 0x4 6. "Break,Break Control Bit." "0,1"
bitfld.long 0x4 5. "SP,From DW_apb_uart_regfile.sv:" "0,1"
newline
bitfld.long 0x4 4. "EPS,Even Parity Select." "0,1"
bitfld.long 0x4 3. "PEN,Parity Enable." "0: parity disabled,1: parity enabled"
newline
bitfld.long 0x4 2. "STOP,Number of stop bits." "0: 1 stop bit,1: 1"
bitfld.long 0x4 0.--1. "DLS,Data Length Select." "0: 5 bits,1: 6 bits,?,?"
line.long 0x8 "MCR,Modem Control Register"
hexmask.long 0x8 7.--31. 1. "RSVD_MCR_31to7,Reserved bits [31:7] - Read Only"
rbitfld.long 0x8 6. "SIRE,SIR Mode Enable." "0: IrDA SIR Mode disabled,1: IrDA SIR Mode enabled"
newline
bitfld.long 0x8 5. "AFCE,Auto Flow Control Enable." "0: Auto Flow Control Mode disabled,1: Auto Flow Control Mode enabled"
bitfld.long 0x8 4. "LoopBack,LoopBack Bit." "0,1"
newline
bitfld.long 0x8 3. "OUT2,OUT2." "0: out2_n de-asserted,1: out2_n asserted"
bitfld.long 0x8 2. "OUT1,OUT1." "0: out1_n de-asserted,1: out1_n asserted"
newline
bitfld.long 0x8 1. "RTS,Request to Send." "0,1"
bitfld.long 0x8 0. "DTR,Data Terminal Ready." "0: dtr_n de-asserted,1: dtr_n asserted"
rgroup.long 0x14++0x7
line.long 0x0 "LSR,Line Status Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_LSR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x0 7. "RFE,Receiver FIFO Error bit." "0: no error in RX FIFO,1: error in RX FIFO"
newline
bitfld.long 0x0 6. "TEMT,Transmitter Empty bit." "0,1"
bitfld.long 0x0 5. "THRE,Transmit Holding Register Empty bit." "0,1"
newline
bitfld.long 0x0 4. "BI,Break Interrupt bit." "0,1"
bitfld.long 0x0 3. "FE,Framing Error bit." "0: no framing error,1: framing error"
newline
bitfld.long 0x0 2. "PE,Parity Error bit." "0: no parity error,1: parity error"
bitfld.long 0x0 1. "OE,Overrun error bit." "0: no overrun error,1: overrun error"
newline
bitfld.long 0x0 0. "DR,Data Ready bit." "0: no data ready,1: data ready"
line.long 0x4 "MSR,Modem Status Register"
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_MSR_31to8,Reserved bits [31:8] - Read Only"
bitfld.long 0x4 7. "DCD,Data Carrier Detect." "0: dcd_n input is de-asserted,1: dcd_n input is asserted"
newline
bitfld.long 0x4 6. "RI,Ring Indicator." "0: ri_n input is de-asserted,1: ri_n input is asserted"
bitfld.long 0x4 5. "DSR,Data Set Ready." "0: dsr_n input is de-asserted,1: dsr_n input is asserted"
newline
bitfld.long 0x4 4. "CTS,Clear to Send." "0: cts_n input is de-asserted,1: cts_n input is asserted"
bitfld.long 0x4 3. "DDCD,Delta Data Carrier Detect." "0: no change on dcd_n since last read of MSR,1: change on dcd_n since last read of MSR"
newline
bitfld.long 0x4 2. "TERI,Trailing Edge of Ring Indicator." "0: no change on ri_n since last read of MSR,1: change on ri_n since last read of MSR"
bitfld.long 0x4 1. "DDSR,Delta Data Set Ready." "0: no change on dsr_n since last read of MSR,1: change on dsr_n since last read of MSR"
newline
bitfld.long 0x4 0. "DCTS,Delta Clear to Send." "0: no change on cts_n since last read of MSR,1: change on cts_n since last read of MSR"
group.long 0x1C++0x3
line.long 0x0 "SCR,Scratchpad Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SCR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "scr,This register is for programmers to use as a temporary storage space. It has no"
rgroup.long 0x30++0x3
line.long 0x0 "SRBR0,Shadow Receive Buffer Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR0_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr0,Shadow Receive Buffer Register 0:"
group.long 0x30++0x3
line.long 0x0 "STHR0,Shadow Transmit Holding Register"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR0_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr0,Shadow Transmit Holding Register 0:"
rgroup.long 0x34++0x3
line.long 0x0 "SRBR1,Shadow Receive Buffer Register 1"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR1_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr1,See srbr0 description"
group.long 0x34++0x3
line.long 0x0 "STHR1,Shadow Transmit Holding Register 1"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR1_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr1,See sthr0 description."
rgroup.long 0x38++0x3
line.long 0x0 "SRBR2,Shadow Receive Buffer Register 2"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR2_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr2,See srbr0 description"
group.long 0x38++0x3
line.long 0x0 "STHR2,Shadow Transmit Holding Register 2"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR2_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr2,See sthr0 description."
rgroup.long 0x3C++0x3
line.long 0x0 "SRBR3,Shadow Receive Buffer Register 3"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR3_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr3,See srbr0 description"
group.long 0x3C++0x3
line.long 0x0 "STHR3,Shadow Transmit Holding Register 3"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR3_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr3,See sthr0 description."
rgroup.long 0x40++0x3
line.long 0x0 "SRBR4,Shadow Receive Buffer Register 4"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR4_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr4,See srbr0 description"
group.long 0x40++0x3
line.long 0x0 "STHR4,Shadow Transmit Holding Register 4"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR4_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr4,See sthr0 description."
rgroup.long 0x44++0x3
line.long 0x0 "SRBR5,Shadow Receive Buffer Register 5"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR5_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr5,See srbr0 description"
group.long 0x44++0x3
line.long 0x0 "STHR5,Shadow Transmit Holding Register 5"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR5_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr5,See sthr0 description."
rgroup.long 0x48++0x3
line.long 0x0 "SRBR6,Shadow Receive Buffer Register 6"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR6_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr6,See srbr0 description"
group.long 0x48++0x3
line.long 0x0 "STHR6,Shadow Transmit Holding Register 6"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR6_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr6,See sthr0 description."
rgroup.long 0x4C++0x3
line.long 0x0 "SRBR7,Shadow Receive Buffer Register 7"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR7_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr7,See srbr0 description"
group.long 0x4C++0x3
line.long 0x0 "STHR7,Shadow Transmit Holding Register 7"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR7_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr7,See sthr0 description."
rgroup.long 0x50++0x3
line.long 0x0 "SRBR8,Shadow Receive Buffer Register 8"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR8_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr8,See srbr0 description"
group.long 0x50++0x3
line.long 0x0 "STHR8,Shadow Transmit Holding Register 8"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR8_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr8,See sthr0 description."
rgroup.long 0x54++0x3
line.long 0x0 "SRBR9,Shadow Receive Buffer Register 9"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR9_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr9,See srbr0 description"
group.long 0x54++0x3
line.long 0x0 "STHR9,Shadow Transmit Holding Register 9"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR9_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr9,See sthr0 description."
rgroup.long 0x58++0x3
line.long 0x0 "SRBR10,Shadow Receive Buffer Register 10"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR10_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr10,See srbr0 description"
group.long 0x58++0x3
line.long 0x0 "STHR10,Shadow Transmit Holding Register 10"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR10_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr10,See sthr0 description."
rgroup.long 0x5C++0x3
line.long 0x0 "SRBR11,Shadow Receive Buffer Register 11"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR11_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr11,See srbr0 description"
group.long 0x5C++0x3
line.long 0x0 "STHR11,Shadow Transmit Holding Register 11"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR11_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr11,See sthr0 description."
rgroup.long 0x60++0x3
line.long 0x0 "SRBR12,Shadow Receive Buffer Register 12"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR12_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr12,See srbr0 description"
group.long 0x60++0x3
line.long 0x0 "STHR12,Shadow Transmit Holding Register 12"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR12_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr12,See sthr0 description."
rgroup.long 0x64++0x3
line.long 0x0 "SRBR13,Shadow Receive Buffer Register 13"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR13_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr13,See srbr0 description"
group.long 0x64++0x3
line.long 0x0 "STHR13,Shadow Transmit Holding Register 13"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR13_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr13,See sthr0 description."
rgroup.long 0x68++0x3
line.long 0x0 "SRBR14,Shadow Receive Buffer Register 14"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR14_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr14,See srbr0 description"
group.long 0x68++0x3
line.long 0x0 "STHR14,Shadow Transmit Holding Register 14"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR14_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr14,See sthr0 description."
rgroup.long 0x6C++0x3
line.long 0x0 "SRBR15,Shadow Receive Buffer Register 15"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SRBR15_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "srbr15,See srbr0 description"
group.long 0x6C++0x7
line.long 0x0 "STHR15,Shadow Transmit Holding Register 15"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_STHR15_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "sthr15,See sthr0 description."
line.long 0x4 "FAR,FIFO Access Register"
hexmask.long 0x4 1.--31. 1. "RSVD_FAR_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x4 0. "far,Writes will have no effect when FIFO_ACCESS == No  always readable. This register" "0: FIFO access mode disabled,1: FIFO access mode enabled"
rgroup.long 0x74++0x3
line.long 0x0 "TFR,Transmit FIFO Read"
hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TFR_31to8,Reserved bits [31:8] - Read Only"
hexmask.long.byte 0x0 0.--7. 1. "tfr,Transmit FIFO Read."
group.long 0x78++0x3
line.long 0x0 "RFW,Receive FIFO Write"
hexmask.long.tbyte 0x0 10.--31. 1. "RSVD_RFW_31to10,Reserved bits [31:10] - Read Only"
bitfld.long 0x0 9. "RFFE,Receive FIFO Framing Error." "0,1"
newline
bitfld.long 0x0 8. "RFPE,Receive FIFO Parity Error." "0,1"
hexmask.long.byte 0x0 0.--7. 1. "RFWD,Receive FIFO Write Data."
rgroup.long 0x7C++0xB
line.long 0x0 "USR,UART Status register."
hexmask.long 0x0 5.--31. 1. "RSVD_USR_31to5,Reserved bits [31:5] - Read Only"
bitfld.long 0x0 4. "RFF,Receive FIFO Full." "0: Receive FIFO not full,1: Receive FIFO Full"
newline
bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty." "0: Receive FIFO is empty,1: Receive FIFO is not empty"
bitfld.long 0x0 2. "TFE,Transmit FIFO Empty." "0: Transmit FIFO is not empty,1: Transmit FIFO is empty"
newline
bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full." "0: Transmit FIFO is full,1: Transmit FIFO is not full"
bitfld.long 0x0 0. "RSVD_BUSY,UART Busy." "0,1"
line.long 0x4 "TFL,Transmit FIFO Level."
hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_TFL_31toADDR_WIDTH,Reserved bits: 31 downto addr bus width + 1 - Read Only"
hexmask.long.byte 0x4 0.--7. 1. "tfl,Transmit FIFO Level."
line.long 0x8 "RFL,Receive FIFO Level."
hexmask.long.tbyte 0x8 8.--31. 1. "RSVD_RFL_31toADDR_WIDTH,Reserved bits: 31 downnto addr bus width + 1 - Read Only"
hexmask.long.byte 0x8 0.--7. 1. "rfl,Receive FIFO Level."
group.long 0x88++0x23
line.long 0x0 "SRR,Software Reset Register."
hexmask.long 0x0 3.--31. 1. "RSVD_SRR_31to3,Reserved bits [31:3] - Read Only"
bitfld.long 0x0 2. "XFR,XMIT FIFO Reset." "0,1"
newline
bitfld.long 0x0 1. "RFR,RCVR FIFO Reset." "0,1"
bitfld.long 0x0 0. "UR,UART Reset." "0,1"
line.long 0x4 "SRTS,Shadow Request to Send."
hexmask.long 0x4 1.--31. 1. "RSVD_SRTS_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x4 0. "srts,Shadow Request to Send." "0,1"
line.long 0x8 "SBCR,Shadow Break Control Register."
hexmask.long 0x8 1.--31. 1. "RSVD_SBCR_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x8 0. "sbcb,Shadow Break Control Bit." "0,1"
line.long 0xC "SDMAM,Shadow DMA Mode."
hexmask.long 0xC 1.--31. 1. "RSVD_SDMAM_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0xC 0. "sdmam,Shadow DMA Mode." "0: mode 0,1: mode 1"
line.long 0x10 "SFE,Shadow FIFO Enable"
hexmask.long 0x10 1.--31. 1. "RSVD_SFE_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x10 0. "sfe,Shadow FIFO Enable." "0,1"
line.long 0x14 "SRT,Shadow RCVR Trigger"
hexmask.long 0x14 2.--31. 1. "RSVD_SRT_31to2,Reserved bits [31:2] - Read Only"
bitfld.long 0x14 0.--1. "srt,Shadow RCVR Trigger." "0: 1 character in the FIFO,1: FIFO 1/4 full,?,?"
line.long 0x18 "STET,Shadow TX Empty Trigger"
hexmask.long 0x18 2.--31. 1. "RSVD_STET_31to2,Reserved bits [31:2] - Read Only"
bitfld.long 0x18 0.--1. "stet,Shadow TX Empty Trigger." "0: FIFO empty,1: 2 characters in the FIFO,?,?"
line.long 0x1C "HTX,Halt TX"
hexmask.long 0x1C 1.--31. 1. "RSVD_HTX_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x1C 0. "htx,Halt TX." "0: Halt TX disabled,1: Halt TX enabled"
line.long 0x20 "DMASA,DMA Software Acknowledge"
hexmask.long 0x20 1.--31. 1. "RSVD_DMASA_31to1,Reserved bits [31:1] - Read Only"
bitfld.long 0x20 0. "dmasa,DMA Software Acknowledge." "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "CPR,Component Parameter Register"
hexmask.long.byte 0x0 24.--31. 1. "RSVD_CPR_31to24,Reserved bits [31:24] - Read Only"
hexmask.long.byte 0x0 16.--23. 1. "FIFO_MODE,Encoding of FIFO_MODE configuration parameter value.DW_apb_uart.ralf"
newline
bitfld.long 0x0 14.--15. "RSVD_CPR_15to14,Reserved bits [15:14] - Read Only" "0,1,2,3"
bitfld.long 0x0 13. "DMA_EXTRA,Encoding of DMA_EXTRA configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 12. "UART_ADD_ENCODED_PARAMS,Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 11. "SHADOW,Encoding of SHADOW configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 10. "FIFO_STAT,Encoding of FIFO_STAT configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 9. "FIFO_ACCESS,Encoding of FIFO_ACCESS configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 8. "ADDITIONAL_FEAT,Encoding of ADDITIONAL_FEATURES configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 7. "SIR_LP_MODE,Encoding of SIR_LP_MODE configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 6. "SIR_MODE,Encoding of SIR_MODE configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 5. "THRE_MODE,Encoding of THRE_MODE configuration parameter value." "0: FALSE,1: TRUE"
newline
bitfld.long 0x0 4. "AFCE_MODE,Encoding of AFCE_MODE configuration parameter value." "0: FALSE,1: TRUE"
bitfld.long 0x0 2.--3. "RSVD_CPR_3to2,Reserved bits [3:2] - Read Only" "0,1,2,3"
newline
bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,Encoding of APB_DATA_WIDTH configuration parameter value." "0: 8 bits,1: 16 bits,?,?"
line.long 0x4 "UCV,Component Version"
hexmask.long 0x4 0.--31. 1. "UART_Component_Version,ASCII value for each number in the version  followed by *."
line.long 0x8 "CTR,Component Type Register"
hexmask.long 0x8 0.--31. 1. "Peripheral_ID,This register contains the peripherals identification code."
tree.end
tree.end
tree "USB_3.1 (USB 3.1 Gen1 Controller)"
base ad:0x11000000
rgroup.long 0x0++0x1F
line.long 0x0 "CAPLENGTH,Capability Registers Length"
hexmask.long.word 0x0 16.--31. 1. "HCIVERSION,HC Interface Version Number (HCIVERSION)"
newline
hexmask.long.byte 0x0 8.--15. 1. "reserved_15_8,Reserved"
newline
hexmask.long.byte 0x0 0.--7. 1. "CAPLENGTH,Capability Registers Length (CAPLENGTH)"
line.long 0x4 "HCSPARAMS1,Structural Parameters 1 Register"
hexmask.long.byte 0x4 24.--31. 1. "MAXPORTS,Number of Ports (MaxPorts)"
newline
hexmask.long.byte 0x4 19.--23. 1. "reserved_23_19,Reserved_23_19"
newline
hexmask.long.word 0x4 8.--18. 1. "MAXINTRS,Number of Interrupters (MaxIntrs)"
newline
hexmask.long.byte 0x4 0.--7. 1. "MAXSLOTS,Number of device slots (MaxSlots)"
line.long 0x8 "HCSPARAMS2,Structural Parameters 2 Register"
hexmask.long.byte 0x8 27.--31. 1. "MAXSCRATCHPADBUFS,Max Scratchpad Bufs Lo"
newline
bitfld.long 0x8 26. "SPR,Scratchpad Restore (SPR)" "0,1"
newline
hexmask.long.byte 0x8 21.--25. 1. "MAXSCRATCHPADBUFS_HI,Max Scratchpad Bufs HI"
newline
hexmask.long.word 0x8 8.--20. 1. "reserved_20_8,Reserved"
newline
hexmask.long.byte 0x8 4.--7. 1. "ERSTMAX,Event Ring Segment Table Max (ERST Max)"
newline
hexmask.long.byte 0x8 0.--3. 1. "IST,Isochronous Scheduling Threshold (IST)"
line.long 0xC "HCSPARAMS3,Structural Parameters 3 Register"
hexmask.long.word 0xC 16.--31. 1. "U2_DEVICE_EXIT_LAT,U2 Device Exit Latency"
newline
hexmask.long.byte 0xC 8.--15. 1. "reserved_15_8,Reserved_15_8"
newline
hexmask.long.byte 0xC 0.--7. 1. "U1_DEVICE_EXIT_LAT,U1 Device Exit Latency"
line.long 0x10 "HCCPARAMS1,Capability Parameters 1 Register"
hexmask.long.word 0x10 16.--31. 1. "XECP,xHCI Extended Capabilities Pointer (xECP)"
newline
hexmask.long.byte 0x10 12.--15. 1. "MAXPSASIZE,Maximum Primary Stream Array Size (MaxPSASize)"
newline
bitfld.long 0x10 11. "CFC,Contiguous Frame ID Capability (CFC)" "0,1"
newline
bitfld.long 0x10 10. "SEC,Stopped EDLTA Capability (SEC)" "0,1"
newline
bitfld.long 0x10 9. "SPC,Short Packet Capability (SPC)" "0,1"
newline
bitfld.long 0x10 8. "PAE,Parse All Event Data (PAE)" "0,1"
newline
bitfld.long 0x10 7. "NSS,No Secondary SID Support (NSS)" "0,1"
newline
bitfld.long 0x10 6. "LTC,Latency Tolerance Messaging Capability (LTC)" "0,1"
newline
bitfld.long 0x10 5. "LHRC,Light HC Reset Capability" "0,1"
newline
bitfld.long 0x10 4. "PIND,Port Indicators (PIND)" "0,1"
newline
bitfld.long 0x10 3. "PPC,Port Power Control" "0,1"
newline
bitfld.long 0x10 2. "CSZ,Context Size (CSZ)" "0,1"
newline
bitfld.long 0x10 1. "BNC,Bandwidth Negotiation Capability (BNC)" "0,1"
newline
bitfld.long 0x10 0. "AC64,64-bit Addressing Capability (AC64)" "0,1"
line.long 0x14 "DBOFF,Doorbell Offset Register"
hexmask.long 0x14 2.--31. 1. "DOORBELL_ARRAY_OFFSET,Doorbell Array Offset - RO"
newline
bitfld.long 0x14 0.--1. "reserved_1_0,Reserved_1_0" "0,1,2,3"
line.long 0x18 "RTSOFF,Runtime Register Space Offset Register"
hexmask.long 0x18 5.--31. 1. "RUNTIME_REG_SPACE_OFFSET,Runtime Register Space Offset"
newline
hexmask.long.byte 0x18 0.--4. 1. "reserved_4_0,Reserved_4_0"
line.long 0x1C "HCCPARAMS2,Host Controller Capability Parameters 2"
hexmask.long.tbyte 0x1C 8.--31. 1. "reserved_31_8,Reserved_31_8"
newline
bitfld.long 0x1C 7. "ETC_TSC,Extended TBC TRB Status Capability-ETC_TSC" "0,1"
newline
bitfld.long 0x1C 6. "ETC,ETC" "0,1"
newline
bitfld.long 0x1C 5. "CIC,Configuration Information Capability (CIC)" "0,1"
newline
bitfld.long 0x1C 4. "LEC,Large ESIT Payload Capability (LEC)" "0,1"
newline
bitfld.long 0x1C 3. "CTC,Compliance Transition Capability (CTC)" "0,1"
newline
bitfld.long 0x1C 2. "FSC,Force Save Context Capability (FSC)" "0,1"
newline
bitfld.long 0x1C 1. "CMC,Configure Endpoint Command Max Exit Latency Too Large Capability (CMC)" "0,1"
newline
bitfld.long 0x1C 0. "U3C,U3 Entry Capability (U3C)" "0,1"
group.long 0x20++0x7
line.long 0x0 "USBCMD,USB Command Register"
hexmask.long.tbyte 0x0 15.--31. 1. "reserved_31_15,Reserved_31_15"
newline
bitfld.long 0x0 14. "ETE,Extended TBC Enable" "0,1"
newline
bitfld.long 0x0 13. "CME,CEM Enable" "0,1"
newline
bitfld.long 0x0 12. "reserved_12,Reserved_12" "0,1"
newline
bitfld.long 0x0 11. "EU3S,EU3S" "0,1"
newline
bitfld.long 0x0 10. "EWE,EWE" "0,1"
newline
bitfld.long 0x0 9. "CRS,Controller Restore State" "0,1"
newline
bitfld.long 0x0 8. "CSS,Controller Save State" "0,1"
newline
bitfld.long 0x0 7. "LHCRST,Light Host Controller Reset" "0,1"
newline
rbitfld.long 0x0 4.--6. "reserved_6_4,Reserved_6_4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3. "HSEE,HSEE" "0,1"
newline
bitfld.long 0x0 2. "INTE,INTE" "0,1"
newline
bitfld.long 0x0 1. "HCRST,HCRST" "0,1"
newline
bitfld.long 0x0 0. "R_S,R_S" "0,1"
line.long 0x4 "USBSTS,USB Status Register Bit Definitions"
hexmask.long.tbyte 0x4 13.--31. 1. "reserved_31_13,Reserved_31_13"
newline
rbitfld.long 0x4 12. "HCE,Host Controller Error (HCE) - RO" "0: No internal xHC error conditions exist and,1: Internal xHC error condition"
newline
rbitfld.long 0x4 11. "CNR,Controller Not Ready (CNR) - RO" "0: Ready and,1: Not Ready"
newline
eventfld.long 0x4 10. "SRE,Save/Restore Error" "0,1"
newline
rbitfld.long 0x4 9. "RSS,Restore State Status" "0,1"
newline
rbitfld.long 0x4 8. "SSS,Save State Status" "0,1"
newline
rbitfld.long 0x4 5.--7. "reserved_7_5,Reserved" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x4 4. "PCD,Port Change Detect" "0,1"
newline
eventfld.long 0x4 3. "EINT,Event Interrupt" "0,1"
newline
eventfld.long 0x4 2. "HSE,HSE" "0,1"
newline
rbitfld.long 0x4 1. "reserved_1,Reserved" "0,1"
newline
rbitfld.long 0x4 0. "HCH,HCH" "0,1"
rgroup.long 0x28++0x3
line.long 0x0 "PAGESIZE,Page Size Register Bit Definitions"
hexmask.long.word 0x0 16.--31. 1. "reserved_31_16,Reserved_31_16"
newline
hexmask.long.word 0x0 0.--15. 1. "PAGE_SIZE,PAGE_SIZE"
group.long 0x34++0xB
line.long 0x0 "DNCTRL,Device Notification Register Bit Definitions"
hexmask.long.word 0x0 16.--31. 1. "reserved_31_16,Reserved_31_16"
newline
hexmask.long.word 0x0 0.--15. 1. "N0_N15,N0_N15"
line.long 0x4 "CRCR_LO,CRCR_LO"
hexmask.long 0x4 6.--31. 1. "CMD_RING_PNTR,CMD_RING_PNTR"
newline
rbitfld.long 0x4 4.--5. "reserved_5_4,Reserved_5_4" "0,1,2,3"
newline
rbitfld.long 0x4 3. "CRR,CRR" "0,1"
newline
bitfld.long 0x4 2. "CA,CA" "0,1"
newline
bitfld.long 0x4 1. "CS,CS" "0,1"
newline
bitfld.long 0x4 0. "RCS,RCS" "0,1"
line.long 0x8 "CRCR_HI,CRCR_HI"
hexmask.long 0x8 0.--31. 1. "CMD_RING_PNTR,COMMAND_RING_POINTER"
group.long 0x50++0xB
line.long 0x0 "DCBAAP_LO,DCBAAP_LO"
hexmask.long 0x0 6.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP"
newline
hexmask.long.byte 0x0 0.--5. 1. "reserved_5_0,Reserved_5_0"
line.long 0x4 "DCBAAP_HI,DCBAAP_HI"
hexmask.long 0x4 0.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP"
line.long 0x8 "CONFIG,Configure Register Bit Definitions"
hexmask.long.tbyte 0x8 10.--31. 1. "reserved_31_10,Reserved_31_10"
newline
bitfld.long 0x8 9. "CIE,Configuration Information Enable" "0,1"
newline
bitfld.long 0x8 8. "U3E,U3 Entry Enable" "0,1"
newline
hexmask.long.byte 0x8 0.--7. 1. "MAXSLOTSEN,MAXSLOTSEN"
tree "PORTSC_20_REGS[0] (U2 Port Status and Control Register)"
base ad:0x11000420
group.long 0x0++0x7
line.long 0x0 "PORTSC_20,Port Status and Control Register Bit Definitions"
rbitfld.long 0x0 31. "reserved_31,Reserved" "0,1"
rbitfld.long 0x0 30. "DR,Reset Value" "0,1"
rbitfld.long 0x0 28.--29. "reserved_29_28,Reserved_29_28" "0,1,2,3"
bitfld.long 0x0 27. "WOE,WOE" "0,1"
bitfld.long 0x0 26. "WDE,WDE" "0,1"
bitfld.long 0x0 25. "WCE,WCE" "0,1"
newline
rbitfld.long 0x0 24. "CAS,Cold Attach Status" "0,1"
rbitfld.long 0x0 23. "reserved_23,Reserved" "0,1"
eventfld.long 0x0 22. "PLC,PLC" "0,1"
eventfld.long 0x0 21. "PRC,PRC" "0,1"
eventfld.long 0x0 20. "OCC,OCC" "0,1"
rbitfld.long 0x0 19. "reserved_19,WRC" "0,1"
newline
eventfld.long 0x0 18. "PEC,PEC" "0,1"
eventfld.long 0x0 17. "CSC,CSC" "0,1"
bitfld.long 0x0 16. "LWS,LWS" "0,1"
bitfld.long 0x0 14.--15. "PIC,PIC" "0,1,2,3"
hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED"
bitfld.long 0x0 9. "PP,PP" "0,1"
newline
hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS"
bitfld.long 0x0 4. "PR,PR" "0,1"
rbitfld.long 0x0 3. "OCA,OCA" "0,1"
rbitfld.long 0x0 2. "reserved_2,Reserved_2" "0,1"
eventfld.long 0x0 1. "PED,PED" "0,1"
rbitfld.long 0x0 0. "CCS,CCS" "0,1"
line.long 0x4 "PORTPMSC_20,USB3 Port Power Management Status and Control Register Bit Definitions"
hexmask.long.byte 0x4 28.--31. 1. "PRTTSTCTRL,Port Test Control (Test Mode)"
hexmask.long.word 0x4 17.--27. 1. "reserved_27_17,Reserved_27_17"
bitfld.long 0x4 16. "HLE,Hardware LPM Enable" "0,1"
hexmask.long.byte 0x4 8.--15. 1. "L1DSLOT,L1DSLOT"
hexmask.long.byte 0x4 4.--7. 1. "BESL,Best Effort Service Latency"
bitfld.long 0x4 3. "RWE,Remote Wake Enable" "0,1"
newline
rbitfld.long 0x4 0.--2. "L1S,L1 Status (L1S) - RO. Default = 0." "0,1,2,3,4,5,6,7"
rgroup.long 0x8++0x3
line.long 0x0 "PORTLI_20,Port Link Info Register"
hexmask.long 0x0 0.--31. 1. "reserved_31_0,Reserved_31_0"
group.long 0xC++0x3
line.long 0x0 "PORTHLPMC_20,USB2 Port Hardware LPM Control Register Bit Definitions"
hexmask.long.tbyte 0x0 14.--31. 1. "reserved_31_14,Reserved"
hexmask.long.byte 0x0 10.--13. 1. "BESLD,Best Effort Service Latency Deep (BESLD)"
hexmask.long.byte 0x0 2.--9. 1. "L1_TIMEOUT,PORTHLPMC_20 L1_TIMEOUT."
bitfld.long 0x0 0.--1. "HIRDM,Host Initiated Resume Duration Mode (HIRDM)" "0,1,2,3"
tree.end
tree "PORTSC_30_REGS[0] (U3 Port Status and Control Register)"
base ad:0x11000430
group.long 0x0++0x7
line.long 0x0 "PORTSC_30,Port Status and Control Register Bit Definitions"
bitfld.long 0x0 31. "WPR,Reset Value" "0,1"
rbitfld.long 0x0 30. "DR,Reset Value" "0,1"
rbitfld.long 0x0 28.--29. "reserved_29_28,Reserved_29_28" "0,1,2,3"
bitfld.long 0x0 27. "WOE,WOE" "0,1"
bitfld.long 0x0 26. "WDE,WDE" "0,1"
newline
bitfld.long 0x0 25. "WCE,WCE" "0,1"
rbitfld.long 0x0 24. "CAS,Cold Attach Status" "0,1"
eventfld.long 0x0 23. "CEC,CEC" "0,1"
eventfld.long 0x0 22. "PLC,PLC" "0,1"
eventfld.long 0x0 21. "PRC,PRC" "0,1"
newline
eventfld.long 0x0 20. "OCC,OCC" "0,1"
eventfld.long 0x0 19. "WRC,WRC" "0,1"
eventfld.long 0x0 18. "PEC,PEC" "0,1"
eventfld.long 0x0 17. "CSC,CSC" "0,1"
bitfld.long 0x0 16. "LWS,LWS" "0,1"
newline
bitfld.long 0x0 14.--15. "PIC,PIC" "0,1,2,3"
hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED"
bitfld.long 0x0 9. "PP,PP" "0,1"
hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS"
bitfld.long 0x0 4. "PR,PR" "0,1"
newline
rbitfld.long 0x0 3. "OCA,OCA" "0,1"
rbitfld.long 0x0 2. "reserved_2,Reserved_2" "0,1"
eventfld.long 0x0 1. "PED,PED" "0,1"
rbitfld.long 0x0 0. "CCS,CCS" "0,1"
line.long 0x4 "PORTPMSC_30,USB3 Port Power Management Status and Control Register Bit Definitions"
hexmask.long.word 0x4 17.--31. 1. "reserved_31_17,Reserved_31_17"
bitfld.long 0x4 16. "FLA,FLA" "0,1"
hexmask.long.byte 0x4 8.--15. 1. "U2_TIMEOUT,U2_TIMEOUT"
hexmask.long.byte 0x4 0.--7. 1. "U1_TIMEOUT,U1_TIMEOUT"
rgroup.long 0x8++0x7
line.long 0x0 "PORTLI_30,Port Link Info Register"
hexmask.long.byte 0x0 24.--31. 1. "reserved_31_24,Reserved_31_24"
hexmask.long.byte 0x0 20.--23. 1. "TLC,Tx Lane Count (TLC)"
hexmask.long.byte 0x0 16.--19. 1. "RLC,Rx Lane Count (RLC)"
hexmask.long.word 0x0 0.--15. 1. "LINK_ERROR_COUNT,LINK_ERROR_COUNT"
line.long 0x4 "PORTHLPMC_30,USB2 Port Hardware LPM Control Register Bit Definitions"
hexmask.long 0x4 0.--31. 1. "reserved_31_0,Reserved"
tree.end
base ad:0x11000000
newline
group.long 0x440++0x7
newline
line.long 0x0 "USBLEGSUP,USBLEGSUP"
hexmask.long.byte 0x0 25.--31. 1. "reserved_31_25,Reserved_31_25"
newline
bitfld.long 0x0 24. "HC_OS_OWNED,HC_OS_OWNED SEMAPHORE" "0,1"
newline
hexmask.long.byte 0x0 17.--23. 1. "reserved_23_17,Reserved_23_17"
newline
bitfld.long 0x0 16. "HC_BIOS_OWNED,HC_BIOS_OWNED SEMAPHORE" "0,1"
newline
hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER"
newline
hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID"
line.long 0x4 "USBLEGCTLSTS,USBLEGCTLSTS"
eventfld.long 0x4 31. "SMI_ON_BAR,SMI_ON_BAR" "0,1"
newline
eventfld.long 0x4 30. "SMI_ON_PCI,SMI_ON_PCI COMMAND" "0,1"
newline
eventfld.long 0x4 29. "SMI_ON_OS,SMI_ON_OS OWNERSHIP CHANGE" "0,1"
newline
hexmask.long.byte 0x4 21.--28. 1. "reserved_28_21,Reserved_28_21"
newline
rbitfld.long 0x4 20. "SMI_ON_HOST,SMI_ON_HOST SYSTEM ERROR" "0,1"
newline
rbitfld.long 0x4 17.--19. "reserved_19_17,Reserved_19_17" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x4 16. "SMI_ON_EVENT,SMI_ON_EVENT INTERRUPT" "0,1"
newline
bitfld.long 0x4 15. "SMI_ON_BAR_E,SMI_ON_BAR ENABLE" "0,1"
newline
bitfld.long 0x4 14. "SMI_ON_PCI_E,SMI_ON_PCI COMMAND ENABLE" "0,1"
newline
bitfld.long 0x4 13. "SMI_ON_OS_E,SMI_ON_OS OWNERSHIP ENABLE" "0,1"
newline
hexmask.long.byte 0x4 5.--12. 1. "reserved_12_5,Reserved_12_5"
newline
bitfld.long 0x4 4. "SMI_ON_HOST_E,SMI_ON_HOST SYSTEM ERROR ENABLE" "0,1"
newline
rbitfld.long 0x4 1.--3. "reserved_3_1,Reserved_3_1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "USB_SMI_ENABLE,USB_SMI_ENABLE" "0,1"
rgroup.long 0x450++0xF
line.long 0x0 "SUPTPRT2_DW0,SUPTPRT2_DW0"
hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION"
newline
hexmask.long.byte 0x0 16.--23. 1. "MINOR_REVISION,MINOR_REVISION"
newline
hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER"
newline
hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID"
line.long 0x4 "SUPTPRT2_DW1,Register SUPTPRT2_DW1"
hexmask.long 0x4 0.--31. 1. "NAME_STRING,NAME_STRING"
line.long 0x8 "SUPTPRT2_DW2,xHCI Supported Protocol Capability_ Data Word 2"
hexmask.long.byte 0x8 28.--31. 1. "PSIC,PSIC"
newline
bitfld.long 0x8 25.--27. "MHD,Hub Depth" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 21.--24. 1. "Reserved_24_21,Reserved"
newline
bitfld.long 0x8 20. "BLC,BESL LPM Capability." "0: The ports described by this xHCI Supported..,1: The ports described by this xHCI Supported.."
newline
bitfld.long 0x8 19. "HLC,Compatible Port Offset." "0,1"
newline
bitfld.long 0x8 18. "IHI,IHI" "0,1"
newline
bitfld.long 0x8 17. "HSO,HSO" "0,1"
newline
bitfld.long 0x8 16. "L1C,L1C" "0,1"
newline
hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT"
newline
hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET"
line.long 0xC "SUPTPRT2_DW3,Register SUPTPRT2_DW3"
hexmask.long 0xC 5.--31. 1. "reserved_31_5,Reserved_31_5"
newline
hexmask.long.byte 0xC 0.--4. 1. "PROTCL_SLT_TY,Protocol Slot Type"
tree "SUPT_30_REGS[0] (EXTENDED SUPR CAP REGISTER)"
base ad:0x11000460
rgroup.long 0x0++0x1F
line.long 0x0 "SUPTPRT3_DW0,Register SUPTPRT3_DW0"
hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION"
hexmask.long.byte 0x0 16.--23. 1. "MINOR_REVISION,MINOR_REVISION"
hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER"
hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID"
line.long 0x4 "SUPTPRT3_DW1,Register SUPTPRT3_DW1"
hexmask.long 0x4 0.--31. 1. "NAME_STRING,NAME_STRING"
line.long 0x8 "SUPTPRT3_DW2,SUPTPRT3_DW2"
hexmask.long.byte 0x8 28.--31. 1. "PSIC,PSIC"
hexmask.long.word 0x8 16.--27. 1. "reserved_27_16,Protocol defined"
hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT"
hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET"
line.long 0xC "SUPTPRT3_DW3,SUPTPRT3_DW3"
hexmask.long 0xC 5.--31. 1. "reserved_31_5,Reserved_31_5"
hexmask.long.byte 0xC 0.--4. 1. "PROTCL_SLT_TY,Protocol Slot Type"
line.long 0x10 "SUPTPRT3_DW4,SUPTPRT3_DW4"
hexmask.long.word 0x10 16.--31. 1. "PSIM,PSIM"
bitfld.long 0x10 14.--15. "LP,Link Protocol" "0,1,2,3"
hexmask.long.byte 0x10 9.--13. 1. "reserved_13_9,reserved_13_9"
bitfld.long 0x10 8. "PFD,PSI full-duplex" "0,1"
newline
bitfld.long 0x10 6.--7. "PLT,PSI type" "0,1,2,3"
bitfld.long 0x10 4.--5. "PSIE,Protocol speed ID exponent" "0,1,2,3"
hexmask.long.byte 0x10 0.--3. 1. "PSIV,Protocol speed ID value"
line.long 0x14 "SUPTPRT3_DW5,SUPTPRT3_DW5"
hexmask.long.word 0x14 16.--31. 1. "PSIM,protocol speed mantissa"
bitfld.long 0x14 14.--15. "LP,Link Protocol" "0,1,2,3"
hexmask.long.byte 0x14 9.--13. 1. "reserved_13_9,reserved_13_9"
bitfld.long 0x14 8. "PFD,PSI full-duplex" "0,1"
newline
bitfld.long 0x14 6.--7. "PLT,PSI type" "0,1,2,3"
bitfld.long 0x14 4.--5. "PSIE,Protocol speed ID exponent" "0,1,2,3"
hexmask.long.byte 0x14 0.--3. 1. "PSIV,PSIV"
line.long 0x18 "SUPTPRT3_DW6,SUPTPRT3_DW6"
hexmask.long 0x18 0.--31. 1. "reserved_31_0,Reserved - dummy register for simple decoding"
line.long 0x1C "SUPTPRT3_DW7,SUPTPRT3_DW7"
hexmask.long 0x1C 0.--31. 1. "reserved_31_0,Reserved - dummy register for simple decoding"
tree.end
base ad:0x11000000
newline
rgroup.long 0x480++0x3
newline
line.long 0x0 "DCID,DCID"
hexmask.long.word 0x0 21.--31. 1. "reserved_31_21,Reserved_31_21"
newline
hexmask.long.byte 0x0 16.--20. 1. "DCERSTMAX,DCERSTMAX"
newline
hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER"
newline
hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID"
group.long 0x484++0x7
line.long 0x0 "DCDB,Register DCDB"
hexmask.long.word 0x0 16.--31. 1. "reserved_31_16,Reserved_31_16"
newline
hexmask.long.byte 0x0 8.--15. 1. "DBTARGET,DBTARGET"
newline
hexmask.long.byte 0x0 0.--7. 1. "reserved_7_0,Reserved_7_0"
line.long 0x4 "DCERSTSZ,DCERSTSZ"
hexmask.long.word 0x4 16.--31. 1. "reserved_31_16,Reserved_31_16"
newline
hexmask.long.word 0x4 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE"
rgroup.long 0x48C++0x3
line.long 0x0 "RSVD0,Reserved-0"
hexmask.long 0x0 0.--31. 1. "reserved_31_0,reserved_31_0"
group.long 0x490++0x13
line.long 0x0 "DCERSTBA_LO,DCERSTBA_LO"
hexmask.long 0x0 4.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR"
newline
hexmask.long.byte 0x0 0.--3. 1. "reserved_3_0,Reserved_3_0"
line.long 0x4 "DCERSTBA_HI,Register DCERSTBA_HI"
hexmask.long 0x4 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR"
line.long 0x8 "DCERDP_LO,DCERDP_LO"
hexmask.long 0x8 4.--31. 1. "DEQUEUE_POINTER,DEQUEUE_POINTER"
newline
bitfld.long 0x8 3. "reserved_3,Reserved_3" "0,1"
newline
bitfld.long 0x8 0.--2. "DESI,DESI" "0,1,2,3,4,5,6,7"
line.long 0xC "DCERDP_HI,DCERDP_HI"
hexmask.long 0xC 0.--31. 1. "DEQUEUE_POINTER,DEQUEUE_POINTER"
line.long 0x10 "DCCTRL,DCCTRL"
bitfld.long 0x10 31. "DCE,DCE" "0,1"
newline
hexmask.long.byte 0x10 24.--30. 1. "DEVICE_ADDRESS,DEVICE_ADDRESS"
newline
hexmask.long.byte 0x10 16.--23. 1. "DEBUG_MAX_BURST_SIZE,DEBUG_PROTOCOL"
newline
hexmask.long.word 0x10 5.--15. 1. "reserved_15_5,Reserved_15_5"
newline
eventfld.long 0x10 4. "DRC,DRC" "0,1"
newline
bitfld.long 0x10 3. "HIT,HIT" "0,1"
newline
bitfld.long 0x10 2. "HOT,HOT" "0,1"
newline
bitfld.long 0x10 1. "LSE,LSE" "0,1"
newline
rbitfld.long 0x10 0. "DCR,DCR" "0,1"
rgroup.long 0x4A4++0x3
line.long 0x0 "DCST,DCST"
hexmask.long.byte 0x0 24.--31. 1. "DEBUG_PORT_NUMBER,DEBUG_PORT_NUMBER"
newline
hexmask.long.tbyte 0x0 2.--23. 1. "reserved_23_2,Reserved_23_2"
newline
bitfld.long 0x0 1. "SBR,SBR" "0,1"
newline
bitfld.long 0x0 0. "ER,ER" "0,1"
group.long 0x4A8++0x3
line.long 0x0 "DCPORTSC,Register DCPORTSC"
hexmask.long.byte 0x0 24.--31. 1. "reserved_31_24,Reserved_31_24"
newline
eventfld.long 0x0 23. "CEC,CEC" "0,1"
newline
eventfld.long 0x0 22. "PLC,PLC" "0,1"
newline
eventfld.long 0x0 21. "PRC,PRC" "0,1"
newline
rbitfld.long 0x0 18.--20. "reserved_20_18,Reserved_20_18" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x0 17. "CSC,CSC" "0,1"
newline
rbitfld.long 0x0 14.--16. "reserved_16_14,Reserved_16_14" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED"
newline
rbitfld.long 0x0 9. "reserved_9,Reserved_9" "0,1"
newline
hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS"
newline
rbitfld.long 0x0 4. "PR,PR" "0,1"
newline
rbitfld.long 0x0 2.--3. "reserved_3_2,Reserved_3_2" "0,1,2,3"
newline
bitfld.long 0x0 1. "PED,PED" "0,1"
newline
rbitfld.long 0x0 0. "CCS,CCS" "0,1"
rgroup.long 0x4AC++0x3
line.long 0x0 "RSVD1,Reserved-1"
hexmask.long 0x0 0.--31. 1. "reserved_31_0,reserved_31_0"
group.long 0x4B0++0xF
line.long 0x0 "DCCP_LO,DCCP_LO"
hexmask.long 0x0 4.--31. 1. "DCCPR,DCCPR"
newline
hexmask.long.byte 0x0 0.--3. 1. "reserved_3_0,Reserved_3_0"
line.long 0x4 "DCCP_HI,Register DCCP_HI"
hexmask.long 0x4 0.--31. 1. "DCCPR,DCCPR"
line.long 0x8 "DCDDI1,Register DCDDI1"
hexmask.long.word 0x8 16.--31. 1. "VENDORID,VENDORID"
newline
hexmask.long.byte 0x8 8.--15. 1. "reserved_15_8,Reserved_15_8"
newline
hexmask.long.byte 0x8 0.--7. 1. "DBCPROTOCOL,DBCPROTOCOL"
line.long 0xC "DCDDI2,Register DCDDI2"
hexmask.long.word 0xC 16.--31. 1. "DEVICEREV,DEVICEREV"
newline
hexmask.long.word 0xC 0.--15. 1. "PRODUCTID,PRODUCTID"
rgroup.long 0x1000++0x7
line.long 0x0 "MFINDEX,Microframe Index Register Bit Definitions"
hexmask.long.tbyte 0x0 14.--31. 1. "reserved_31_14,Reserved_31_14"
newline
hexmask.long.word 0x0 0.--13. 1. "MICROFRAME_INDEX,MICROFRAME_INDEX"
line.long 0x4 "RsvdZ,RsvdZ"
hexmask.long 0x4 0.--31. 1. "reserved_31_0,Reserved_31_0"
tree "DB_REGS"
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x11002000 ad:0x11002004 ad:0x11002008 ad:0x1100200C ad:0x11002010 ad:0x11002014 ad:0x11002018 ad:0x1100201C ad:0x11002020 ad:0x11002024 ad:0x11002028 ad:0x1100202C ad:0x11002030 ad:0x11002034 ad:0x11002038 ad:0x1100203C)
tree "DB_REGS[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DB,Doorbell Register Bit Field Definitions"
hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID"
hexmask.long.byte 0x0 8.--15. 1. "reserved_15_8,Reserved_15_8"
hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET"
tree.end
repeat.end
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x11002040 ad:0x11002044 ad:0x11002048 ad:0x1100204C ad:0x11002050 ad:0x11002054 ad:0x11002058 ad:0x1100205C ad:0x11002060 ad:0x11002064 ad:0x11002068 ad:0x1100206C ad:0x11002070 ad:0x11002074 ad:0x11002078 ad:0x1100207C)
tree "DB_REGS[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DB,Doorbell Register Bit Field Definitions"
hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID"
hexmask.long.byte 0x0 8.--15. 1. "reserved_15_8,Reserved_15_8"
hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET"
tree.end
repeat.end
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F)(list ad:0x11002080 ad:0x11002084 ad:0x11002088 ad:0x1100208C ad:0x11002090 ad:0x11002094 ad:0x11002098 ad:0x1100209C ad:0x110020A0 ad:0x110020A4 ad:0x110020A8 ad:0x110020AC ad:0x110020B0 ad:0x110020B4 ad:0x110020B8 ad:0x110020BC)
tree "DB_REGS[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DB,Doorbell Register Bit Field Definitions"
hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID"
hexmask.long.byte 0x0 8.--15. 1. "reserved_15_8,Reserved_15_8"
hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET"
tree.end
repeat.end
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F)(list ad:0x110020C0 ad:0x110020C4 ad:0x110020C8 ad:0x110020CC ad:0x110020D0 ad:0x110020D4 ad:0x110020D8 ad:0x110020DC ad:0x110020E0 ad:0x110020E4 ad:0x110020E8 ad:0x110020EC ad:0x110020F0 ad:0x110020F4 ad:0x110020F8 ad:0x110020FC)
tree "DB_REGS[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DB,Doorbell Register Bit Field Definitions"
hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID"
hexmask.long.byte 0x0 8.--15. 1. "reserved_15_8,Reserved_15_8"
hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET"
tree.end
repeat.end
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F)(list ad:0x11002100 ad:0x11002104 ad:0x11002108 ad:0x1100210C ad:0x11002110 ad:0x11002114 ad:0x11002118 ad:0x1100211C ad:0x11002120 ad:0x11002124 ad:0x11002128 ad:0x1100212C ad:0x11002130 ad:0x11002134 ad:0x11002138 ad:0x1100213C)
tree "DB_REGS[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DB,Doorbell Register Bit Field Definitions"
hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID"
hexmask.long.byte 0x0 8.--15. 1. "reserved_15_8,Reserved_15_8"
hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET"
tree.end
repeat.end
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F)(list ad:0x11002140 ad:0x11002144 ad:0x11002148 ad:0x1100214C ad:0x11002150 ad:0x11002154 ad:0x11002158 ad:0x1100215C ad:0x11002160 ad:0x11002164 ad:0x11002168 ad:0x1100216C ad:0x11002170 ad:0x11002174 ad:0x11002178 ad:0x1100217C)
tree "DB_REGS[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DB,Doorbell Register Bit Field Definitions"
hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID"
hexmask.long.byte 0x0 8.--15. 1. "reserved_15_8,Reserved_15_8"
hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET"
tree.end
repeat.end
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F)(list ad:0x11002180 ad:0x11002184 ad:0x11002188 ad:0x1100218C ad:0x11002190 ad:0x11002194 ad:0x11002198 ad:0x1100219C ad:0x110021A0 ad:0x110021A4 ad:0x110021A8 ad:0x110021AC ad:0x110021B0 ad:0x110021B4 ad:0x110021B8 ad:0x110021BC)
tree "DB_REGS[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DB,Doorbell Register Bit Field Definitions"
hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID"
hexmask.long.byte 0x0 8.--15. 1. "reserved_15_8,Reserved_15_8"
hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET"
tree.end
repeat.end
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F)(list ad:0x110021C0 ad:0x110021C4 ad:0x110021C8 ad:0x110021CC ad:0x110021D0 ad:0x110021D4 ad:0x110021D8 ad:0x110021DC ad:0x110021E0 ad:0x110021E4 ad:0x110021E8 ad:0x110021EC ad:0x110021F0 ad:0x110021F4 ad:0x110021F8 ad:0x110021FC)
tree "DB_REGS[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DB,Doorbell Register Bit Field Definitions"
hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID"
hexmask.long.byte 0x0 8.--15. 1. "reserved_15_8,Reserved_15_8"
hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET"
tree.end
repeat.end
tree.end
tree "IMAN_REGS[0] (Interrupter Management Register)"
base ad:0x11001020
group.long 0x0++0xB
line.long 0x0 "IMAN,Interrupter Management Register Bit Definitions"
hexmask.long 0x0 2.--31. 1. "reserved_31_2,Reserved_31_2"
bitfld.long 0x0 1. "IE,IE" "0,1"
eventfld.long 0x0 0. "IP,IP Interrupt Pending" "0,1"
line.long 0x4 "IMOD,Interrupter Moderation Register"
hexmask.long.word 0x4 16.--31. 1. "IMODC,Interrupt Moderation Counter (IMODC)"
hexmask.long.word 0x4 0.--15. 1. "IMODI,Interrupt Moderation Interval (IMODI) - RW."
line.long 0x8 "ERSTSZ,Event Ring Segment Table Size Register Bit Definitions"
hexmask.long.word 0x8 16.--31. 1. "reserved_31_16,Reserved_31_16"
hexmask.long.word 0x8 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE"
rgroup.long 0xC++0x3
line.long 0x0 "RsvdP,RsvdP"
hexmask.long 0x0 0.--31. 1. "reserved_31_0,Reserved_31_0"
group.long 0x10++0xF
line.long 0x0 "ERSTBA_LO,ERSTBA_LO"
hexmask.long 0x0 6.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR"
hexmask.long.byte 0x0 0.--5. 1. "reserved_5_0,Reserved_5_0"
line.long 0x4 "ERSTBA_HI,ERSTBA_HI"
hexmask.long 0x4 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR"
line.long 0x8 "ERDP_LO,ERDP_LO"
hexmask.long 0x8 4.--31. 1. "ERD_PNTR,ERD_PNTR"
eventfld.long 0x8 3. "EHB,HC OS Owned SemaphoreERS_TABLE_SIZEHC BIOS Owned Semaphore" "0,1"
bitfld.long 0x8 0.--2. "DESI,DESI" "0,1,2,3,4,5,6,7"
line.long 0xC "ERDP_HI,ERDP_HI"
hexmask.long 0xC 0.--31. 1. "ERD_PNTR,ERD_PNTR"
tree.end
base ad:0x11000000
newline
group.long 0xC100++0x1F
newline
line.long 0x0 "GSBUSCFG0,Global SoC Bus Configuration Register 0"
hexmask.long.byte 0x0 28.--31. 1. "DATRDREQINFO,DATRDREQINFO"
newline
hexmask.long.byte 0x0 24.--27. 1. "DESRDREQINFO,DESRDREQINFO"
newline
hexmask.long.byte 0x0 20.--23. 1. "DATWRREQINFO,DATWRREQINFO"
newline
hexmask.long.byte 0x0 16.--19. 1. "DESWRREQINFO,DESWRREQINFO"
newline
hexmask.long.byte 0x0 12.--15. 1. "reserved_15_12,Reserved_15_12"
newline
bitfld.long 0x0 11. "DATBIGEND,Data Access is Big Endian" "0,1"
newline
bitfld.long 0x0 10. "DESBIGEND,Descriptor Access is Big Endian" "0,1"
newline
bitfld.long 0x0 8.--9. "reserved_9_8,Reserved_9_8" "0,1,2,3"
newline
bitfld.long 0x0 7. "INCR256BRSTENA,INCR256 Burst Type Enable" "0,1"
newline
bitfld.long 0x0 6. "INCR128BRSTENA,INCR128 Burst Type Enable" "0,1"
newline
bitfld.long 0x0 5. "INCR64BRSTENA,INCR64 Burst Type Enable" "0,1"
newline
bitfld.long 0x0 4. "INCR32BRSTENA,INCR32 Burst Type Enable" "0,1"
newline
bitfld.long 0x0 3. "INCR16BRSTENA,INCR16 Burst Type Enable" "0,1"
newline
bitfld.long 0x0 2. "INCR8BRSTENA,INCR8 Burst Type Enable" "0,1"
newline
bitfld.long 0x0 1. "INCR4BRSTENA,INCR4 Burst Type Enable" "0,1"
newline
bitfld.long 0x0 0. "INCRBRSTENA,Undefined Length INCR Burst Type Enable (INCRBrstEna)" "0: INCRX burst mode,1: INCR"
line.long 0x4 "GSBUSCFG1,Global SoC Bus Configuration Register 1"
hexmask.long.word 0x4 17.--31. 1. "reserved_31_17,Reserved"
newline
hexmask.long.byte 0x4 13.--16. 1. "ExtdPipeTransLimit,AXI Pipelined Transfers Extended Burst Request Limit"
newline
bitfld.long 0x4 12. "EN1KPAGE,1k Page Boundary Enable" "0,1"
newline
hexmask.long.byte 0x4 8.--11. 1. "PipeTransLimit,AXI Pipelined Transfers Burst Request Limit"
newline
hexmask.long.byte 0x4 0.--7. 1. "reserved_7_0,Reserved_7_0"
line.long 0x8 "GTXTHRCFG,Global Tx Threshold Control Register"
hexmask.long.byte 0x8 27.--31. 1. "reserved_31_27,Reserved"
newline
bitfld.long 0x8 26. "UsbTxPktCntSel,USB Async ESS Transmit Packet Threshold Enable - Host/Device Modes" "0: USB transmission multi-packet thresholding is..,1: USB transmission multi-packet thresholding is.."
newline
hexmask.long.byte 0x8 21.--25. 1. "UsbTxPktCnt,USB Async ESS Transmit Packet Threshold Count - Host/Device Modes"
newline
hexmask.long.byte 0x8 16.--20. 1. "UsbMaxTxBurstSize,USB Async ESS Maximum TX Burst Size - Host Mode Only"
newline
bitfld.long 0x8 15. "UsbTxThrNumPktSel_HS_Prd,USB HS High Bandwidth Periodic Transmit Packet Threshold Enable - Host Mode Only" "0: USB HS High Bandwidth Periodic transmission..,1: USB HS High Bandwidth Periodic transmission.."
newline
bitfld.long 0x8 13.--14. "UsbTxThrNumPkt_HS_Prd,USB HS High Bandwidth Periodic Transmit Packet Threshold Count - Host Mode Only" "0,1,2,3"
newline
bitfld.long 0x8 11.--12. "reserved_12_11,Reserved" "0,1,2,3"
newline
bitfld.long 0x8 10. "UsbTxThrNumPktSel_Prd,USB Periodic ESS Transmit Packet Threshold Enable - Host Mode Only" "0: USB transmission multi-packet thresholding is..,1: USB transmission multi-packet thresholding is.."
newline
hexmask.long.byte 0x8 5.--9. 1. "UsbTxThrNumPkt_Prd,USB Periodic ESS Transmit Packet Threshold Count - Host Mode Only"
newline
hexmask.long.byte 0x8 0.--4. 1. "UsbMaxTxBurstSize_Prd,USB Maximum Periodic ESS TX Burst Size - Host Mode Only"
line.long 0xC "GRXTHRCFG,Global Rx Threshold Control Register"
hexmask.long.byte 0xC 27.--31. 1. "reserved_31_27,Reserved"
newline
bitfld.long 0xC 26. "UsbRxPktCntSel,USB Async ESS Receive Packet Threshold Enable - Host/Device Modes" "0: The controller can only start reception on the..,1: The controller can only start reception on the.."
newline
hexmask.long.byte 0xC 21.--25. 1. "UsbRxPktCnt,USB Async ESS Receive Packet Threshold Count - Host/Device Modes"
newline
hexmask.long.byte 0xC 16.--20. 1. "UsbMaxRxBurstSize,USB Async ESS Maximum Receive Burst Size - Host/Device Modes"
newline
bitfld.long 0xC 15. "UsbRxThrNumPktSel_HS_Prd,USB HS High Bandwidth Periodic Receive Packet Threshold Enable - Host Mode Only" "0: USB HS High Bandwidth Periodic Receive..,1: USB HS High Bandwidth Periodic Receive.."
newline
bitfld.long 0xC 13.--14. "UsbRxThrNumPkt_HS_Prd,USB HS High Bandwidth Periodic Receive Packet Threshold Count - Host Mode Only" "0,1,2,3"
newline
bitfld.long 0xC 11.--12. "reserved_12_11,Reserved" "0,1,2,3"
newline
bitfld.long 0xC 10. "UsbRxThrNumPktSel_Prd,USB Periodic ESS Receive Packet Threshold Enable - Host Mode Only. This field should be programmed to 0 in Device mode." "0: USB Periodic ESS Receive multi-packet..,1: USB Periodic ESS Receive multi-packet.."
newline
hexmask.long.byte 0xC 5.--9. 1. "UsbRxThrNumPkt_Prd,USB Periodic ESS Receive Packet Threshold Count - Host Mode Only. This field should be programmed to 0 in Device mode."
newline
hexmask.long.byte 0xC 0.--4. 1. "UsbMaxRxBurstSize_Prd,USB Maximum Periodic ESS RX Burst Size - Host Mode Only. This field should be programmed to 0 in Device mode."
line.long 0x10 "GCTL,Global Core Control Register"
hexmask.long.word 0x10 19.--31. 1. "PWRDNSCALE,Power Down Scale"
newline
bitfld.long 0x10 18. "MASTERFILTBYPASS,Master Filter Bypass" "0,1"
newline
bitfld.long 0x10 17. "BYPSSETADDR,Bypass SetAddress in Device Mode" "0,1"
newline
bitfld.long 0x10 16. "U2RSTECN,U2RSTECN" "0,1"
newline
bitfld.long 0x10 14.--15. "FRMSCLDWN,FRMSCLDWN" "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "PRTCAPDIR,PRTCAPDIR: Port Capability Direction" "?,1: for Host configurations,2: for Device configurations,3: not supported"
newline
bitfld.long 0x10 11. "CORESOFTRESET,Core Soft Reset" "0,1"
newline
bitfld.long 0x10 10. "reserved_10,Reserved" "0,1"
newline
bitfld.long 0x10 9. "U1U2TimerScale,Disable U1/U2 timer Scaledown" "0,1"
newline
bitfld.long 0x10 8. "DEBUGATTACH,Debug Attach" "0,1"
newline
bitfld.long 0x10 6.--7. "RAMCLKSEL,RAM Clock Select" "0: bus clock,1: pipe clock,2: In device mode,3: In device mode"
newline
bitfld.long 0x10 4.--5. "SCALEDOWN,Scale-Down Mode" "0: Disables all scale-downs,1: Enables scaled down SS timing and repeat values..,2: No TxEq training sequences are sent,3: Enables bit 0 and bit 1 scale-down timing values"
newline
bitfld.long 0x10 3. "DISSCRAMBLE,Disable Scrambling" "0,1"
newline
bitfld.long 0x10 2. "U2EXIT_LFPS,U2EXIT_LFPS" "0: the link treats 248ns LFPS as a valid U2 exit,1: the link waits for 8us of LFPS before it detects.."
newline
rbitfld.long 0x10 1. "GblHibernationEn,GblHibernationEn" "0,1"
newline
bitfld.long 0x10 0. "DSBLCLKGTNG,Disable Clock Gating" "0,1"
line.long 0x14 "GPMSTS,Global Power Management Status Register"
hexmask.long.byte 0x14 28.--31. 1. "PortSel,Global Power Management Status Register  PortSel"
newline
hexmask.long.word 0x14 17.--27. 1. "reserved_27_17,Reserved"
newline
hexmask.long.byte 0x14 12.--16. 1. "U3Wakeup,U3Wakeup"
newline
rbitfld.long 0x14 10.--11. "reserved_11_10,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x14 0.--9. 1. "U2Wakeup,U2Wakeup"
line.long 0x18 "GSTS,Global Status Register"
hexmask.long.word 0x18 20.--31. 1. "CBELT,Current BELT Value"
newline
hexmask.long.byte 0x18 12.--19. 1. "reserved_19_12,Reserved"
newline
hexmask.long.byte 0x18 8.--11. 1. "reserved_11_8,Reserved"
newline
rbitfld.long 0x18 7. "Host_IP,Host Interrupt Pending:" "0,1"
newline
rbitfld.long 0x18 6. "Device_IP,Device Interrupt Pending" "0,1"
newline
eventfld.long 0x18 5. "CSRTimeout,CSR Timeout" "0,1"
newline
eventfld.long 0x18 4. "BUSERRADDRVLD,Bus Error Address Valid (BusErrAddrVld)" "0,1"
newline
rbitfld.long 0x18 2.--3. "reserved_3_2,Reserved" "0,1,2,3"
newline
rbitfld.long 0x18 0.--1. "CURMOD,Current Mode of Operation (CurMod)" "0: Device mode,1: Host mode,?,?"
line.long 0x1C "GUCTL1,Global User Control Register 1"
bitfld.long 0x1C 31. "DEV_DECOUPLE_L1L2_EVT,DEV_DECOUPLE_L1L2_EVT" "0: L1 and L2 events,1: L1 and L2 events are separated when operating in.."
newline
bitfld.long 0x1C 30. "DS_RXDET_MAX_TOUT_CTRL,DS_RXDET_MAX_TOUT_CTRL" "0: 12ms is used as tRxDetectTimeoutDFP,1: 120ms is used as the tRxDetectTimeoutDFP"
newline
bitfld.long 0x1C 29. "FILTER_SE0_FSLS_EOP,FILTER_SE0_FSLS_EOP" "0: Single sampling,1: Feature enabled"
newline
bitfld.long 0x1C 28. "TX_IPGAP_LINECHECK_DIS,TX_IPGAP_LINECHECK_DIS" "0: The linestate transitioning from J to idle for..,1: Feature enabled"
newline
bitfld.long 0x1C 27. "DEV_TRB_OUT_SPR_IND,DEV_TRB_OUT_SPR_IND" "0: Feature disabled,1: Feature enabled"
newline
bitfld.long 0x1C 26. "reserved_26,Reserved" "0,1"
newline
bitfld.long 0x1C 25. "reserved_25,Reserved" "0,1"
newline
bitfld.long 0x1C 24. "DEV_L1_EXIT_BY_HW,DEV_L1_EXIT_BY_HW" "0: Disables device L1 hardware exit logic,1: Feature enabled"
newline
bitfld.long 0x1C 21.--23. "IP_GAP_ADD_ON,This register field is used to add on to the default inter packet gap setting in the USB 2.0 MAC." "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x1C 20. "reserved_20,Reserved" "0,1"
newline
hexmask.long.byte 0x1C 15.--19. 1. "reserved_19_15,Reserved"
newline
bitfld.long 0x1C 14. "HW_LPM_CAP_DISABLE,Disable hardware LPM capability in the xHCI capability register." "0,1"
newline
bitfld.long 0x1C 13. "HW_LPM_HLE_DISABLE,Disable hardware LPM function in all USB 2.0 ports." "0,1"
newline
rbitfld.long 0x1C 12. "DisUSB2RefClkGtng,Disable ref_clk gating for USB 2.0 PHY (DisUSB2RefClkGtng)" "0: ref_clk gating enabled for USB 2,1: ref_clk gating disabled for USB 2"
newline
rbitfld.long 0x1C 11. "DisRefClkGtng,Disable ref_clk gating (DisRefClkGtng" "0: ref_clk gating Enabled for SSPHY,1: ref_clk gating Disabled for SSPHY"
newline
bitfld.long 0x1C 10. "RESUME_OPMODE_HS_HOST,RESUME_OPMODE_HS_HOST" "0,1"
newline
bitfld.long 0x1C 9. "reserved_9,Reserved" "0,1"
newline
bitfld.long 0x1C 8. "L1_SUSP_THRLD_EN_FOR_HOST,L1_SUSP_THRLD_EN_FOR_HOST" "0,1"
newline
hexmask.long.byte 0x1C 4.--7. 1. "L1_SUSP_THRLD_FOR_HOST,L1_SUSP_THRLD_FOR_HOST"
newline
bitfld.long 0x1C 3. "HC_ERRATA_ENABLE,Host ELD Enable (HELDEn)" "0,1"
newline
bitfld.long 0x1C 2. "HC_PARCHK_DISABLE,Host Parameter Check Disable (HParChkDisable)" "0,1"
newline
bitfld.long 0x1C 1. "reserved_1,Reserved" "0,1"
newline
bitfld.long 0x1C 0. "LOA_FILTER_EN,LOA_FILTER_EN" "0,1"
rgroup.long 0xC120++0x3
line.long 0x0 "USB31_IP_NAME,IP NAME REGISTER"
hexmask.long 0x0 0.--31. 1. "SYNOPSYSIP,Synopsys IP Name"
group.long 0xC124++0xB
line.long 0x0 "GGPIO,Global General Purpose Input/Output Register"
hexmask.long.word 0x0 16.--31. 1. "GPO,General Purpose Output"
newline
hexmask.long.word 0x0 0.--15. 1. "GPI,General Purpose Input"
line.long 0x4 "GUID,Global User ID Register"
hexmask.long 0x4 0.--31. 1. "USERID,USERID"
line.long 0x8 "GUCTL,Global User Control Register"
hexmask.long.word 0x8 22.--31. 1. "REFCLKPER,REFCLKPER"
newline
bitfld.long 0x8 21. "NoExtrDl,No Extra Delay Between SOF and the First Packet(NoExtrDl)" "0: Host waits for 2 microseconds after a SOF before..,1: Host doesn't wait after a SOF before it sends.."
newline
bitfld.long 0x8 20. "DMAIgnoreHCE,DMA Ignore HCE" "0,1"
newline
bitfld.long 0x8 19. "IgnoreHCETimeout,IgnoreHCETimeout" "0,1"
newline
bitfld.long 0x8 18. "EN_EXTD_TBC_CAP,When set  the Extended TBC Capability is reported in HCCPARAMS2 if the DWC_USB31_EXTD_TBC_CAP_EN parameter is enabled." "0,1"
newline
bitfld.long 0x8 17. "SprsCtrlTransEn,Sparse Control Transaction Enable" "0,1"
newline
bitfld.long 0x8 16. "ResBwHSEPS,Reserving 85% Bandwidth for HS Periodic EPs (ResBwHSEPS)" "0: HC reserves 80% of the bandwidth for periodic EPs,1: HC relaxes the bandwidth to 85% to accommodate.."
newline
bitfld.long 0x8 15. "reserved_15,Reserved" "0,1"
newline
bitfld.long 0x8 14. "USBHstInImmRetryEn,Host IN Immediate Retry (USBHstInImmRetryEn)" "0: Immediate Retry Disabled,1: Immediate Retry Enabled"
newline
bitfld.long 0x8 13. "reserved_13,Reserved" "0,1"
newline
bitfld.long 0x8 12. "ExtCapSupptEN,External Extended Capability Support Enable (ExtCapSuptEN)" "0,1"
newline
bitfld.long 0x8 11. "InsrtExtrFSBODI,Insert Extra Delay Between FS Bulk OUT Transactions (InsrtExtrFSBODl)." "0: Host doesn't insert extra delay between..,1: Host inserts about 12us extra delay between.."
newline
hexmask.long.word 0x8 0.--10. 1. "DTOUT,Device Timeout (DTOUT)"
rgroup.long 0xC130++0x7
line.long 0x0 "GBUSERRADDRLO,Global SoC Bus Error Address Register - Low"
hexmask.long 0x0 0.--31. 1. "BUSERRADDR,Bus Address - Low (BusAddrLo)"
line.long 0x4 "GBUSERRADDRHI,Global SoC Bus Error Address Register - High"
hexmask.long 0x4 0.--31. 1. "BUSERRADDR,Bus Address - High (BusAddrHi)"
group.long 0xC138++0x3
line.long 0x0 "GPRTBIMAPLO,Global ESS Port to Bus Instance Mapping Register - Low"
hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: ESS USB Instance Number for Port 8."
newline
hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: ESS USB Instance Number for Port 7."
newline
hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6: ESS USB Instance Number for Port 6."
newline
hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: ESS USB Instance Number for Port 5."
newline
hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: ESS USB Instance Number for Port 4."
newline
hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: ESS USB Instance Number for Port 3."
newline
hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: ESS USB Instance Number for Port 2."
newline
hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: ESS USB Instance Number for Port 1."
rgroup.long 0xC13C++0x23
line.long 0x0 "GPRTBIMAPHI,Global ESS Port to Bus Instance Mapping Register - High"
hexmask.long.byte 0x0 28.--31. 1. "reserved_31_28,Reserved_31_28"
newline
hexmask.long.byte 0x0 24.--27. 1. "BINUM15,BINUM15: ESS USB Instance Number for Port 15."
newline
hexmask.long.byte 0x0 20.--23. 1. "BINUM14,BINUM14: ESS USB Instance Number for Port 14."
newline
hexmask.long.byte 0x0 16.--19. 1. "BINUM13,BINUM13: ESS USB Instance Number for Port 13."
newline
hexmask.long.byte 0x0 12.--15. 1. "BINUM12,BINUM12: ESS USB Instance Number for Port 12."
newline
hexmask.long.byte 0x0 8.--11. 1. "BINUM11,BINUM11: ESS USB Instance Number for Port 11."
newline
hexmask.long.byte 0x0 4.--7. 1. "BINUM10,BINUM10: ESS USB Instance Number for Port 10."
newline
hexmask.long.byte 0x0 0.--3. 1. "BINUM9,BINUM9: ESS USB Instance Number for Port 9."
line.long 0x4 "GHWPARAMS0,Global Hardware Parameters Register 0"
hexmask.long.byte 0x4 24.--31. 1. "ghwparams0_31_24,`DWC_USB31_AWIDTH"
newline
hexmask.long.byte 0x4 16.--23. 1. "ghwparams0_23_16,`DWC_USB31_SDWIDTH"
newline
hexmask.long.byte 0x4 8.--15. 1. "ghwparams0_15_8,`DWC_USB31_MDWIDTH"
newline
bitfld.long 0x4 6.--7. "ghwparams0_7_6,`DWC_USB31_SBUS_TYPE" "0,1,2,3"
newline
bitfld.long 0x4 3.--5. "ghwparams0_5_3,`DWC_USB31_MBUS_TYPE" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0.--2. "ghwparams0_2_0,`DWC_USB31_MODE" "0,1,2,3,4,5,6,7"
line.long 0x8 "GHWPARAMS1,Global Hardware Parameters Register 1"
bitfld.long 0x8 31. "ghwparams1_31,`DWC_USB31_EN_DBC" "0,1"
newline
bitfld.long 0x8 30. "ghwparams1_30,`DWC_USB31_RM_OPT_FEATURES" "0,1"
newline
bitfld.long 0x8 29. "ghwparams1_29,Reserved" "0,1"
newline
bitfld.long 0x8 28. "ghwparams1_28,`DWC_USB31_RAM_BUS_CLKS_SYNC" "0,1"
newline
bitfld.long 0x8 27. "ghwparams1_27,`DWC_USB31_MAC_RAM_CLKS_SYNC" "0,1"
newline
bitfld.long 0x8 26. "ghwparams1_26,`DWC_USB31_MAC_PHY_CLKS_SYNC" "0,1"
newline
bitfld.long 0x8 24.--25. "ghwparams1_25_24,`DWC_USB31_EN_PWROPT" "0,1,2,3"
newline
bitfld.long 0x8 23. "ghwparams1_23,`DWC_USB31_SPRAM_TYP" "0,1"
newline
hexmask.long.byte 0x8 17.--22. 1. "ghwparams1_22_17,`DWC_USB31_DEVICE_NUM_INT"
newline
bitfld.long 0x8 14.--16. "ghwparams1_16_14,`DWC_USB31_ASPACEWIDTH" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 11.--13. "ghwparams1_13_11,`DWC_USB31_REQINFOWIDTH" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 8.--10. "ghwparams1_10_8,`DWC_USB31_DATAINFOWIDTH" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x8 4.--7. 1. "ghwparams1_7_4,`DWC_USB31_BURSTWIDTH"
newline
hexmask.long.byte 0x8 0.--3. 1. "ghwparams1_3_0,`DWC_USB31_IDWIDTH"
line.long 0xC "GHWPARAMS2,Global Hardware Parameters Register 2"
hexmask.long 0xC 0.--31. 1. "ghwparams2_31_0,`DWC_USB31_USERID"
line.long 0x10 "GHWPARAMS3,Global Hardware Parameters Register 3"
bitfld.long 0x10 31. "ghwparams3_31,Reserved" "0,1"
newline
hexmask.long.byte 0x10 23.--30. 1. "ghwparams3_30_23,`DWC_USB31_CACHE_TOTAL_XFER_RESOURCES"
newline
hexmask.long.byte 0x10 18.--22. 1. "ghwparams3_22_18,`DWC_USB31_NUM_IN_EPS"
newline
hexmask.long.byte 0x10 12.--17. 1. "ghwparams3_17_12,`DWC_USB31_NUM_EPS"
newline
bitfld.long 0x10 11. "ghwparams3_11,Reserved" "0,1"
newline
bitfld.long 0x10 10. "ghwparams3_10,DWC_USB31_VENDOR_CTL_INTERFACE" "0,1"
newline
bitfld.long 0x10 8.--9. "ghwparams3_9_8,Reserved" "0,1,2,3"
newline
bitfld.long 0x10 6.--7. "ghwparams3_7_6,`DWC_USB31_HSPHY_DWIDTH" "0,1,2,3"
newline
bitfld.long 0x10 4.--5. "ghwparams3_5_4,Reserved" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "ghwparams3_3_2,`DWC_USB31_HSPHY_INTERFACE" "0,1,2,3"
newline
bitfld.long 0x10 0.--1. "ghwparams3_1_0,`DWC_USB31_SSPHY_INTERFACE" "0,1,2,3"
line.long 0x14 "GHWPARAMS4,Global Hardware Parameters Register 4"
hexmask.long.byte 0x14 28.--31. 1. "ghwparams4_31_28,`DWC_USB31_BMU_LSP_DEPTH"
newline
hexmask.long.byte 0x14 23.--27. 1. "ghwparams4_27_23,`DWC_USB31_BMU_PTL_DEPTH"
newline
bitfld.long 0x14 22. "ghwparams4_22,`DWC_USB31_EN_ISOC_SUPT" "0,1"
newline
bitfld.long 0x14 21. "ghwparams4_21,`DWC_USB31_EXT_BUFF_CONTROL" "0,1"
newline
hexmask.long.byte 0x14 17.--20. 1. "ghwparams4_20_17,`DWC_USB31_NUM_ESS_USB_INSTANCES"
newline
hexmask.long.byte 0x14 13.--16. 1. "ghwparams4_16_13,`DWC_USB31_HIBER_SCRATCHBUFS"
newline
hexmask.long.byte 0x14 6.--12. 1. "ghwparams4_12_6,Reserved"
newline
hexmask.long.byte 0x14 0.--5. 1. "ghwparams4_5_0,`DWC_USB31_CACHE_TRBS_PER_TRANSFER"
line.long 0x18 "GHWPARAMS5,Global Hardware Parameters Register 5"
bitfld.long 0x18 29.--31. "ghwparams5_31_29,`DWC_USB31_NUM_RAMS" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x18 23.--28. 1. "ghwparams5_28_23,`DWC_USB31_DFQ_FIFO_DEPTH"
newline
hexmask.long.byte 0x18 17.--22. 1. "ghwparams5_22_17,`DWC_USB31_DWQ_FIFO_DEPTH"
newline
hexmask.long.byte 0x18 11.--16. 1. "ghwparams5_16_11,`DWC_USB31_TXQ_FIFO_DEPTH"
newline
hexmask.long.byte 0x18 5.--10. 1. "ghwparams5_10_5,`DWC_USB31_RXQ_FIFO_DEPTH"
newline
hexmask.long.byte 0x18 0.--4. 1. "ghwparams5_4_0,`DWC_USB31_BMU_BUSGM_DEPTH"
line.long 0x1C "GHWPARAMS6,Global Hardware Parameters Register 6"
hexmask.long.word 0x1C 16.--31. 1. "ghwparams6_31_16,`DWC_USB31_RAM0_DEPTH"
newline
bitfld.long 0x1C 15. "BusFltrsSupport,`DWC_USB31_EN_BUS_FILTERS" "0,1"
newline
hexmask.long.byte 0x1C 10.--14. 1. "ghwparams6_14_10,Reserved"
newline
bitfld.long 0x1C 8.--9. "ghwparams6_9_8,Reserved" "0,1,2,3"
newline
bitfld.long 0x1C 7. "ghwparams6_7,`DWC_USB31_EN_FPGA" "0,1"
newline
bitfld.long 0x1C 6. "ghwparams6_6,`DWC_USB31_EN_DBG_PORTS" "0,1"
newline
hexmask.long.byte 0x1C 0.--5. 1. "ghwparams6_5_0,`DWC_USB31_PSQ_FIFO_DEPTH"
line.long 0x20 "GHWPARAMS7,Global Hardware Parameters Register 7"
hexmask.long.word 0x20 16.--31. 1. "ghwparams7_31_16,`DWC_USB31_RAM2_DEPTH"
newline
hexmask.long.word 0x20 0.--15. 1. "ghwparams7_15_0,`DWC_USB31_RAM1_DEPTH"
group.long 0xC160++0x7
line.long 0x0 "GDBGFIFOSPACE,Global Debug Queue/FIFO Space Available Register"
hexmask.long.word 0x0 16.--31. 1. "SPACE_AVAILABLE,SPACE_AVAILABLE"
newline
hexmask.long.byte 0x0 9.--15. 1. "reserved_15_9,Reserved_15_9"
newline
hexmask.long.word 0x0 0.--8. 1. "FIFO_QUEUE_SELECT,FIFO/Queue Select"
line.long 0x4 "GBMUCTL,Global BMU Control Register"
hexmask.long.word 0x4 16.--31. 1. "reserved_31_16,Reserved"
newline
hexmask.long.word 0x4 6.--15. 1. "reserved_15_6,Reserved"
newline
bitfld.long 0x4 5. "separate_psq_en,When DWC_USB31_EN_SEPARATE_PSQ_PER_DIR is enabled Separate internal process queue and state machine per direction is enabled" "0,1"
newline
rbitfld.long 0x4 3.--4. "reserved_4_3,Reserved" "0,1,2,3"
newline
bitfld.long 0x4 2. "axi_storder_en,When DWC_USB31_AXI_STRICT_ORDER_EN parameter is enabled  both descriptor and data RxDMAs should be configured to use non-posted commands. For a given BI  descriptor/event RxDMA won't be issued until the previous issued data RxDMA is.." "0,1"
newline
bitfld.long 0x4 1. "active_id_en,Active Id enabled" "0,1"
newline
bitfld.long 0x4 0. "reserved_0,Reserved" "0,1"
rgroup.long 0xC16C++0x3
line.long 0x0 "GDBGBMU,Global Debug BMU Register"
hexmask.long.tbyte 0x0 8.--31. 1. "BMU_BCU,BMU_BCU Debug information"
newline
hexmask.long.byte 0x0 4.--7. 1. "BMU_DCU,BMU_DCU Debug information"
newline
hexmask.long.byte 0x0 0.--3. 1. "BMU_CCU,BMU_CCU Debug information"
group.long 0xC170++0x3
line.long 0x0 "GDBGLSPMUX,Global Debug LSP MUX Register in host mode"
hexmask.long.byte 0x0 24.--31. 1. "reserved_31_24,Reserved_31_24"
newline
hexmask.long.byte 0x0 16.--23. 1. "logic_analyzer_trace,logic_analyzer_trace Port MUX Select"
newline
rbitfld.long 0x0 15. "reserved_15,Reserved_15" "0,1"
newline
hexmask.long.word 0x0 0.--14. 1. "LSPSELECT,LSP Select"
rgroup.long 0xC174++0xB
line.long 0x0 "GDBGLSP,Global Debug LSP Register"
hexmask.long 0x0 0.--31. 1. "LSPDEBUG,LSP Debug Information"
line.long 0x4 "GDBGEPINFO0,Global Debug Endpoint Information Register 0"
hexmask.long 0x4 0.--31. 1. "EPDEBUG,Endpoint Debug Information"
line.long 0x8 "GDBGEPINFO1,Global Debug Endpoint Information Register 1"
hexmask.long 0x8 0.--31. 1. "EPDEBUG,Endpoint Debug Information  bits[63:32]"
group.long 0xC180++0x3
line.long 0x0 "GPRTBIMAP_HSLO,Global High-Speed Port to Bus Instance Mapping Register - Low"
hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: HS USB Instance Number for Port 8."
newline
hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: HS USB Instance Number for Port 7."
newline
hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6 USB Instance Number for Port 6."
newline
hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: HS USB Instance Number for Port 5."
newline
hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: HS USB Instance Number for Port 4."
newline
hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: HS USB Instance Number for Port 3."
newline
hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: HS USB Instance Number for Port 2."
newline
hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: HS USB Instance Number for Port 1."
rgroup.long 0xC184++0x3
line.long 0x0 "GPRTBIMAP_HSHI,Global High-Speed Port to Bus Instance Mapping Register - High"
hexmask.long.byte 0x0 28.--31. 1. "reserved_31_28,Reserved_31_28"
newline
hexmask.long.byte 0x0 24.--27. 1. "BINUM15,BINUM15: HS USB Instance Number for Port 15."
newline
hexmask.long.byte 0x0 20.--23. 1. "BINUM14,BINUM14: HS USB Instance Number for Port 14."
newline
hexmask.long.byte 0x0 16.--19. 1. "BINUM13,BINUM13: HS USB Instance Number for Port 13."
newline
hexmask.long.byte 0x0 12.--15. 1. "BINUM12,BINUM12: HS USB Instance Number for Port 12."
newline
hexmask.long.byte 0x0 8.--11. 1. "BINUM11,BINUM11: HS USB Instance Number for 11."
newline
hexmask.long.byte 0x0 4.--7. 1. "BINUM10,BINUM10: HS USB Instance Number for Port 10."
newline
hexmask.long.byte 0x0 0.--3. 1. "BINUM9,BINUM9: HS USB Instance Number for Port 9."
group.long 0xC188++0x3
line.long 0x0 "GPRTBIMAP_FSLO,Global Full/Low-Speed Port to Bus Instance Mapping Register - Low"
hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: FS/LS USB Instance Number for Port 8."
newline
hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: FS/LS USB Instance Number for Port 7."
newline
hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6: FS/LS USB Instance Number for Port 6."
newline
hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: FS/LS USB Instance Number for Port 5."
newline
hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: FS/LS USB Instance Number for Port 4."
newline
hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: FS/LS USB Instance Number for Port 3."
newline
hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: FS/LS USB Instance Number for Port 2."
newline
hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: FS/LS USB Instance Number for Port 1."
rgroup.long 0xC18C++0x3
line.long 0x0 "GPRTBIMAP_FSHI,Global Full/Low-Speed Port to Bus Instance Mapping Register - High"
hexmask.long.byte 0x0 28.--31. 1. "reserved_31_28,Reserved_31_28"
newline
hexmask.long.byte 0x0 24.--27. 1. "BINUM15,BINUM15: FS/LS USB Instance Number for Port 15."
newline
hexmask.long.byte 0x0 20.--23. 1. "BINUM14,BINUM14: FS/LS USB Instance Number for Port 14."
newline
hexmask.long.byte 0x0 16.--19. 1. "BINUM13,BINUM13: FS/LS USB Instance Number for Port 13."
newline
hexmask.long.byte 0x0 12.--15. 1. "BINUM12,BINUM12: FS/LS USB Instance Number for Port 12."
newline
hexmask.long.byte 0x0 8.--11. 1. "BINUM11,BINUM11: FS/LS USB Instance Number for Port 11."
newline
hexmask.long.byte 0x0 4.--7. 1. "BINUM10,BINUM10: FS/LS USB Instance Number for Port 10."
newline
hexmask.long.byte 0x0 0.--3. 1. "BINUM9,BINUM9: FS/LS USB Instance Number for Port 9."
group.long 0xC190++0x3
line.long 0x0 "GHMSOCBWOR,Global Host Mode SoC Bandwidth Override Register"
bitfld.long 0x0 31. "ovrd_port_soc_bw,Overrides the SoC bandwidth port values" "0,1"
newline
bitfld.long 0x0 30. "ovrd_common_soc_rd_wr,Override value for the common_soc_rd_wr port" "0: Separate SoC Bus for Read and Write,1: Common SoC Bus for Read and Write"
newline
hexmask.long.word 0x0 15.--29. 1. "ovrd_soc_wr_uF_kB_bandwidth,SoC Bus Write Bandwidth in KiloBytes/Micro-Frame"
newline
hexmask.long.word 0x0 0.--14. 1. "ovrd_soc_rd_uF_kB_bandwidth,SoC Bus Read Bandwidth in KiloBytes/Micro-Frame"
rgroup.long 0xC1A0++0x7
line.long 0x0 "USB31_VER_NUMBER,USB31 IP VERSION"
hexmask.long 0x0 0.--31. 1. "VERSION_NUM,VERSION_NUM"
line.long 0x4 "USB31_VER_TYPE,USB31 IP VERSION TYPE"
hexmask.long 0x4 0.--31. 1. "VERSIONTYPE,VERSIONTYPE"
group.long 0xC1B0++0x7
line.long 0x0 "GSYSBLKWINCTRL,Global System Bus Blocking Window Control"
bitfld.long 0x0 31. "sys_blocking_ok_all_the_time,Always assert ok_to_block_sysbus=1" "0,1"
newline
bitfld.long 0x0 30. "disable_no_blocking_window,Setting this bit does not check uf_start_no_blocking_time and uf_end_no_blocking_time" "0,1"
newline
bitfld.long 0x0 29. "erst_prefetching_en,Enable ERST Entry Prefetching" "0,1"
newline
hexmask.long.byte 0x0 24.--28. 1. "erst_prefetching_watermark,ERST Prefetching Watermark"
newline
hexmask.long.byte 0x0 16.--23. 1. "reserved_23_16,Reserved"
newline
hexmask.long.byte 0x0 8.--15. 1. "end_no_blocking_time,System bus no blocking time window (in usec) at end of uframe."
newline
hexmask.long.byte 0x0 0.--7. 1. "beginining_no_blocking_time,System bus no blocking time window (in usec) at start of uframe."
line.long 0x4 "GPCIEL1EXTLAT,Global PCIe L1 exit Latency Register"
bitfld.long 0x4 30.--31. "pcie_l1_exit_mode_ctrl,pcie_l1_exit_mode_ctrl" "0,1,2,3"
newline
hexmask.long.tbyte 0x4 12.--29. 1. "reserved_29_12,Reserved"
newline
hexmask.long.word 0x4 0.--11. 1. "pcie_l1_exit_latency,pcie_l1_exit_latency"
tree "GEVNTADRLO_REGS[0] (Global Event Buffer Address Register)"
base ad:0x1100C400
group.long 0x0++0xF
line.long 0x0 "GEVNTADRLO,Global Event Buffer Address (Low) Register"
hexmask.long 0x0 0.--31. 1. "EVNTADRLO,Event Buffer Address (EvntAdrLo)"
line.long 0x4 "GEVNTADRHI,Global Event Buffer Address (High) Register"
hexmask.long 0x4 0.--31. 1. "EVNTADRHI,Event Buffer Address (EvntAdrHi)"
line.long 0x8 "GEVNTSIZ,Global Event Buffer Size Register"
bitfld.long 0x8 31. "EVNTINTRPTMASK,Event Interrupt Mask (EvntIntMask)." "0,1"
hexmask.long.word 0x8 16.--30. 1. "reserved_30_16,Reserved_30_16"
hexmask.long.word 0x8 0.--15. 1. "EVENTSIZ,Event Buffer Size in bytes (EVNTSiz)"
line.long 0xC "GEVNTCOUNT,Global Event Buffer Count Register"
bitfld.long 0xC 31. "EVNT_HANDLER_BUSY,Event Handler Busy" "0,1"
hexmask.long.word 0xC 16.--30. 1. "reserved_30_16,Reserved_30_16"
hexmask.long.word 0xC 0.--15. 1. "EVNTCOUNT,Event Count (EVNTCount)"
tree.end
tree "GRXFIFOSIZ_REGS[0] (Global Receive FIFO Size Register)"
base ad:0x1100C380
group.long 0x0++0x17
line.long 0x0 "GRXFIFOSIZ0,Global Receive FIFO Size Register"
hexmask.long.word 0x0 16.--31. 1. "RXFSTADDR_N,RxFIFOn RAM Start Address (RxFStAddr_n)"
rbitfld.long 0x0 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x0 0.--14. 1. "RXFDEP_N,RxFIFO Depth (RxFDep_n)"
line.long 0x4 "GRXFIFOSIZ1,Register"
hexmask.long.word 0x4 16.--31. 1. "RXFSTADDR_N,RXFSTADDR_N"
rbitfld.long 0x4 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x4 0.--14. 1. "RXFDEP_N,RxFIFO Depth"
line.long 0x8 "GRXFIFOSIZ2,Register"
hexmask.long.word 0x8 16.--31. 1. "RXFSTADDR_N,RAM Start Address"
rbitfld.long 0x8 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x8 0.--14. 1. "RXFDEP_N,RxFIFO Depth"
line.long 0xC "GRXFIFOSIZ3,Register"
hexmask.long.word 0xC 16.--31. 1. "RXFSTADDR_N,RXFSTADDR_N"
rbitfld.long 0xC 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0xC 0.--14. 1. "RXFDEP_N,RxFIFO Depth"
line.long 0x10 "GRXFIFOSIZ4,Register"
hexmask.long.word 0x10 16.--31. 1. "RXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x10 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x10 0.--14. 1. "RXFDEP_N,RXFDEP_N: RxFIFO Depth (RxFDep_n)"
line.long 0x14 "GRXFIFOSIZ5,Register"
hexmask.long.word 0x14 16.--31. 1. "RXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x14 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x14 0.--14. 1. "RXFDEP_N,RxFIFO Depth"
tree.end
tree "GTXFIFOSIZ_REGS[0] (Global Transmit FIFO Size Register)"
base ad:0x1100C300
group.long 0x0++0x3F
line.long 0x0 "GTXFIFOSIZ0,Global Transmit FIFO Size Register"
hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x0 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x0 0.--14. 1. "TXFDEP_N,TxFIFO Depth"
line.long 0x4 "GTXFIFOSIZ1,Register GTXFIFOSIZ 1"
hexmask.long.word 0x4 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x4 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x4 0.--14. 1. "TXFDEP_N,TXFDEP_N"
line.long 0x8 "GTXFIFOSIZ2,Transmit FIFOn RAM Start Address"
hexmask.long.word 0x8 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x8 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x8 0.--14. 1. "TXFDEP_N,TxFIFO Depth"
line.long 0xC "GTXFIFOSIZ3,Register GTXFIFOSIZ 3"
hexmask.long.word 0xC 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0xC 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0xC 0.--14. 1. "TXFDEP_N,TXFDEP_N: TxFIFO Depth (TxFDep_n)"
line.long 0x10 "GTXFIFOSIZ4,Register GTXFIFOSIZ 4"
hexmask.long.word 0x10 16.--31. 1. "TXFSTADDR_N,TXFSTADDR_N"
rbitfld.long 0x10 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x10 0.--14. 1. "TXFDEP_N,TXFDEP_N: TxFIFO Depth (TxFDep_n)"
line.long 0x14 "GTXFIFOSIZ5,Register GTXFIFOSIZ 5"
hexmask.long.word 0x14 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x14 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x14 0.--14. 1. "TXFDEP_N,TxFIFO Depth"
line.long 0x18 "GTXFIFOSIZ6,Register GTXFIFOSIZ 6"
hexmask.long.word 0x18 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x18 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x18 0.--14. 1. "TXFDEP_N,TxFIFO Depth"
line.long 0x1C "GTXFIFOSIZ7,Register GTXFIFOSIZ 7"
hexmask.long.word 0x1C 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x1C 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x1C 0.--14. 1. "TXFDEP_N,TXFDEP_N"
line.long 0x20 "GTXFIFOSIZ8,Register GTXFIFOSIZ 8"
hexmask.long.word 0x20 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x20 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x20 0.--14. 1. "TXFDEP_N,TxFIFO Depth"
line.long 0x24 "GTXFIFOSIZ9,Register GTXFIFOSIZ 9"
hexmask.long.word 0x24 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x24 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x24 0.--14. 1. "TXFDEP_N,TxFIFO Depth"
line.long 0x28 "GTXFIFOSIZ10,GTXFIFOSIZ 10"
hexmask.long.word 0x28 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x28 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x28 0.--14. 1. "TXFDEP_N,TXFDEP_N: TxFIFO Depth (TxFDep_n)"
line.long 0x2C "GTXFIFOSIZ11,Register GTXFIFOSIZ 11"
hexmask.long.word 0x2C 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x2C 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x2C 0.--14. 1. "TXFDEP_N,TxFIFO Depth"
line.long 0x30 "GTXFIFOSIZ12,GTXFIFOSIZ 12"
hexmask.long.word 0x30 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x30 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x30 0.--14. 1. "TXFDEP_N,TxFIFO Depth"
line.long 0x34 "GTXFIFOSIZ13,Register GTXFIFOSIZ 13"
hexmask.long.word 0x34 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x34 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x34 0.--14. 1. "TXFDEP_N,TXFDEP_N"
line.long 0x38 "GTXFIFOSIZ14,Register GTXFIFOSIZ 14"
hexmask.long.word 0x38 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address"
rbitfld.long 0x38 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x38 0.--14. 1. "TXFDEP_N,TXFDEP_N"
line.long 0x3C "GTXFIFOSIZ15,Register GTXFIFOSIZ 15"
hexmask.long.word 0x3C 16.--31. 1. "TXFSTADDR_N,TXFSTADDR_N"
rbitfld.long 0x3C 15. "reserved_15,Reserved" "0,1"
hexmask.long.word 0x3C 0.--14. 1. "TXFDEP_N,TXFDEP_N"
tree.end
tree "GUSB2PHYACC_REGS[0] (Global USB 2.0 UTMI PHY Vendor Control Register)"
base ad:0x1100C280
group.long 0x0++0x3
line.long 0x0 "GUSB2PHYACC_ULPI,Global USB 2.0 ULPI PHY Vendor Control Register"
hexmask.long.byte 0x0 27.--31. 1. "reserved_31_27,Reserved_31_27"
rbitfld.long 0x0 26. "DISUIPIDRVR,DISUIPIDRVR" "0,1"
bitfld.long 0x0 25. "NEWREGREQ,New Register Request" "0,1"
rbitfld.long 0x0 24. "VSTSDONE,VSTSDONE" "0,1"
bitfld.long 0x0 23. "VSTSBSY,VSTSBSY" "0,1"
bitfld.long 0x0 22. "REGWR,Register Write" "0,1"
newline
hexmask.long.byte 0x0 16.--21. 1. "REGADDR,Register Address"
hexmask.long.byte 0x0 8.--15. 1. "EXTREGADDR,EXTREGADDR"
hexmask.long.byte 0x0 0.--7. 1. "REGDATA,REGDATA"
tree.end
tree "GUSB2PHYCFG_REGS[0] (Global USB2 PHY Configuration Register)"
base ad:0x1100C200
group.long 0x0++0x3
line.long 0x0 "GUSB2PHYCFG,Global USB2 PHY Configuration Register"
bitfld.long 0x0 31. "PHYSOFTRST,UTMI PHY Soft Reset (PHYSoftRst)" "0,1"
newline
rbitfld.long 0x0 30. "reserved_30,Reserved_30" "0,1"
newline
bitfld.long 0x0 29. "ULPI_LPM_WITH_OPMODE_CHK,ULPI_LPM_WITH_OPMODE_CHK" "0: A NOPID is sent before sending an EXTPID for LPM,1: An EXTPID is sent without previously sending a.."
newline
rbitfld.long 0x0 27.--28. "HSIC_CON_WIDTH_ADJ,HSIC_CON_WIDTH_ADJ" "0: 3 times the strobe period,1: 4 times the strobe period,2: 5 times the strobe period,3: 6 times the strobe period"
newline
rbitfld.long 0x0 26. "INV_SEL_HSIC,INV_SEL_HSIC" "0: HSIC Capability is disabled,1: HSIC Capability is enabled"
newline
bitfld.long 0x0 25. "OVRD_FSLS_DISC_TIME,Overriding the FS/LS disconnect time to 32us." "0,1"
newline
bitfld.long 0x0 22.--24. "LSTRD,LS Turnaround Time (LSTRDTIM)" "0: 2 bit times,1: 2,2: 3 bit times,3: 3,4: 4 bit times,5: 4,6: 5 bit times,7: 5"
newline
bitfld.long 0x0 19.--21. "LSIPD,LS Inter-Packet Time (LSIPD)" "0: 2 bit times,1: 2,2: 3 bit times,3: 3,4: 4 bit times,5: 4,6: 5 bit times,7: 5"
newline
bitfld.long 0x0 18. "ULPIEXTVBUSINDIACTOR,ULPI External VBUS Indicator (ULPIExtVbusIndicator)" "0: PHY uses an internal VBUS valid comparator,1: PHY uses an external VBUS valid comparator"
newline
bitfld.long 0x0 17. "ULPIEXTVBUSDRV,ULPI External VBUS Drive (ULPIExtVbusDrv)" "0: PHY drives VBUS with internal charge pump,1: PHY drives VBUS with an external supply"
newline
rbitfld.long 0x0 16. "reserved_16,Reserved" "0,1"
newline
bitfld.long 0x0 15. "ULPIAUTORES,ULPI Auto Resume (ULPIAutoRes)" "0: PHY does not use the AutoResume feature,1: PHY uses the AutoResume feature"
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bitfld.long 0x0 14. "eUSB2OPMODE,eUSB 2.0 UTMI interface enhancement (eUSB2OPMODE)" "0: eUSB UTMI interface enhancement disabled,1: eUSB UTMI interface enhancement enabled"
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hexmask.long.byte 0x0 10.--13. 1. "USBTRDTIM,USB 2.0 Turnaround Time (USBTrdTim)"
newline
bitfld.long 0x0 9. "XCVRDLY,Transceiver Delay:" "0,1"
newline
bitfld.long 0x0 8. "ENBLSLPM,Enable utmi_sleep_n and utmi_l1_suspend_n" "0: utmi_sleep_n and utmi_l1_suspend_n assertion..,1: utmi_sleep_n and utmi_l1_suspend_n assertion.."
newline
bitfld.long 0x0 7. "PHYSEL,USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select" "0: USB 2,1: USB 1"
newline
bitfld.long 0x0 6. "SUSPENDUSB20,Suspend USB2.0 HS/FS/LS PHY" "0,1"
newline
rbitfld.long 0x0 5. "FSINTF,Full-Speed Serial Interface Select (FSIntf)" "0: 6-pin unidirectional full-speed serial interface,1: 3-pin bidirectional full-speed serial interface"
newline
rbitfld.long 0x0 4. "ULPI_UTMI_Sel,ULPI or UTMI+ Select (ULPI_UTMI_Sel)" "0: UTMI+ Interface,1: ULPI Interface"
newline
bitfld.long 0x0 3. "PHYIF,PHY Interface (PHYIf)" "0: 8 bits,1: 16 bits"
newline
bitfld.long 0x0 0.--2. "TOutCal,HS/FS Timeout Calibration (TOutCal)" "0,1,2,3,4,5,6,7"
tree.end
tree "GUSB3PIPECTL_REGS[0] (Global USB 3.1 PIPE Control Register)"
base ad:0x1100C2C0
group.long 0x0++0x3
line.long 0x0 "GUSB3PIPECTL,Global USB 3.1 PIPE Control Register"
bitfld.long 0x0 31. "PHYSoftRst,USB 3.1 PHY Soft Reset" "0,1"
newline
bitfld.long 0x0 30. "HstPrtCmpl,HstPrtCmpl" "0,1"
newline
bitfld.long 0x0 29. "U2P3ok,Enable P3 entry during U2/SSInactive (U2P3ok). This is not recommended with Synopsys PHY which has P3 exit time of ~1ms and P2 exit time of ~100uS. This is recommended only if your PHYs P3 exit time is close to P2 exit time. Putting the ESS PHY in.." "0: During link state U2/ESS,1: During link state U2/ESS"
newline
bitfld.long 0x0 28. "DisRxDetP3,Disabled receiver detection in P3 (DisRxDetP3)" "0: If PHY is in P3 and controller needs to perform..,1: If PHY is in P3 and controller needs to perform.."
newline
bitfld.long 0x0 27. "Ux_exit_in_Px,Ux Exit in Px (Ux_exit_in_Px)" "0: The controller does U1/U2/U3 exit in PHY power..,1: The controller does U1/U2/U3 exit in PHY power.."
newline
bitfld.long 0x0 26. "ping_enhancement_en,Ping Enhancement Enable (ping_enhancement_en)" "0,1"
newline
bitfld.long 0x0 25. "u1u2exitfail_to_recov,U1U2exitfail to Recovery (u1u2exitfail_to_recov)" "0,1"
newline
bitfld.long 0x0 24. "request_p1p2p3,Always Request P1/P2/P3 for U1/U2/U3 (request_p1p2p3)" "0,1"
newline
bitfld.long 0x0 23. "StartRxDetU3RxDet,Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet)" "0,1"
newline
bitfld.long 0x0 22. "DisRxDetU3RxDet,Disable Receiver Detection in U3/Rx.Det" "0,1"
newline
bitfld.long 0x0 19.--21. "DelayP1P2P3,Delay P1P2P3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18. "DELAYP1TRANS,Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively." "0: When entering U1/U2/U3,1: When entering U1/U2/U3"
newline
bitfld.long 0x0 17. "SUSPENDENABLE,Suspend USB 3.1 ESS PHY (Suspend_en)" "0,1"
newline
rbitfld.long 0x0 15.--16. "DATWIDTH,PIPE Data Width (DatWidth)" "0: 32 bits,1: 16 bits,2: 8 bits,?"
newline
bitfld.long 0x0 14. "AbortRxDetInU2,Abort Rx Detect in U2 (AbortRxDetInU2)" "0,1"
newline
bitfld.long 0x0 13. "SkipRxDet,Skip Rx Detect:" "0,1"
newline
bitfld.long 0x0 12. "LFPSP0Algn,LFPS P0 Align" "0,1"
newline
bitfld.long 0x0 11. "P3P2TranOK,P3 P2 Transitions OK (P3P2TranOK)" "0,1"
newline
bitfld.long 0x0 10. "P3ExSigP2,P3 Exit Signal in P2 (P3ExSigP2)" "0,1"
newline
bitfld.long 0x0 9. "LFPSFILTER,LFPS Filter (LFPSFilt)" "0,1"
newline
bitfld.long 0x0 8. "RX_DETECT_to_Polling_LFPS_Control,RX_DETECT to Polling.LFPS Control" "0: Enables a 400us delay to start Polling LFPS..,1: Disables the 400us delay to start Polling LFPS.."
newline
bitfld.long 0x0 7. "reserved_7,Reserved" "0,1"
newline
bitfld.long 0x0 6. "TX_SWING,Tx Swing (TxSwing)" "0,1"
newline
bitfld.long 0x0 3.--5. "TX_MARGIN,Tx Margin[2:0] (TxMargin)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1.--2. "SS_TX_DE_EMPHASIS,Tx Deemphasis (TxDeemphasis)" "0,1,2,3"
newline
bitfld.long 0x0 0. "ELASTIC_BUFFER_MODE,Elastic Buffer Mode (ElasticBufferMode)" "0,1"
tree.end
base ad:0x11000000
newline
rgroup.long 0xC600++0x3
newline
line.long 0x0 "GHWPARAMS8,Global Hardware Parameters Register 8"
hexmask.long 0x0 0.--31. 1. "ghwparams8_32_0,`DWC_USB31_DCACHE_DEPTH_INFO"
group.long 0xC604++0xF
line.long 0x0 "GSMACCTL,Global SMAC CONTROL REGISTER"
bitfld.long 0x0 30.--31. "dbg_tis_index,SMAC bus instance index" "0,1,2,3"
newline
hexmask.long.byte 0x0 26.--29. 1. "dbg_ptl_addr,PTL debug address"
newline
hexmask.long.byte 0x0 18.--25. 1. "reserved_25_8,Reserved"
newline
bitfld.long 0x0 17. "hostin_signle_en,Host: Limit a maximum of one active IN transfer on USB at a time" "0,1"
newline
bitfld.long 0x0 16. "hostout_single_en,Host: Limit a maximum of one active OUT transfer on USB at a time" "0,1"
newline
hexmask.long.word 0x0 4.--15. 1. "reserved_15_4,Reserved"
newline
bitfld.long 0x0 3. "single_psqdir_en,Enable PSQ message type [PSQDIR] sorting" "0: PSQDIR=0 for all messages,1: PSQDIR=0 for OUT endpoints"
newline
bitfld.long 0x0 2. "host_mask_nump0,Mask TPACK nump0 (stream) with nump1" "0: Normal operation,1: Convert TP"
newline
bitfld.long 0x0 1. "ignore_babble,Ignore Receive babble conditions" "0: detect receive payload babble conditions,1: ignore receive payload babble conditions"
newline
bitfld.long 0x0 0. "single_TBT_req,Disable pipelined Transmit Data" "0: enable transmit data pipelining,1: disable transmit data pipelining"
line.long 0x4 "GUCTL2,Global User Control Register 2"
hexmask.long.byte 0x4 25.--31. 1. "PERIODIC_UF_THR,Periodic microseconds threshold"
newline
hexmask.long.byte 0x4 18.--24. 1. "ASYNC_UF_THR,Asynchronous microseconds threshold"
newline
hexmask.long.byte 0x4 11.--17. 1. "PERIODIC_TXDMA_UF_THR,Indicates the number of microseconds before the end of the microframe that the LSP needs to start issuing TX DMA for periodic OUT endpoints scheduled in the next microframe."
newline
bitfld.long 0x4 9.--10. "SVC_OPP_PER_SSP,Service opportunities to Enhanced SuperSpeedPlus bulk endpoints" "0: maxburstsize service opportunities,1: 2* maxburstsize service opportunities,2: 4*maxburstsize service opportunities,3: maxburstsize/2 service opportunities"
newline
bitfld.long 0x4 7.--8. "SVC_OPP_PER_SS,Service opportunities to SuperSpeed bulk endpoints" "0: maxburstsize service opportunities,1: 2* maxburstsize service opportunities,2: 4*maxburstsize service opportunities,3: maxburstsize/2 service opportunities"
newline
bitfld.long 0x4 5.--6. "SVC_OPP_PER_HS,Service opportunities to HS bulk endpoints" "0: 1 service opportunity,1: 1 service opportunities,2: 3 service opportunities,3: 4 service opportunities"
newline
bitfld.long 0x4 3.--4. "SVC_OPP_PER_FSLS,Service opportunities to FS/LS bulk endpoints" "0: 1 service opportunity,1: 1 service opportunities,2: 3 service opportunities,3: 4 service opportunities"
newline
bitfld.long 0x4 1.--2. "MAX_REISU_CNT,Indicates the number of re-issue opportunities that will be allocated to OUT transactions that meet the following criteria:" "0,1,2,3"
newline
bitfld.long 0x4 0. "SCHEDDULE_LT_THR,Indicates that the Host LSP schedulers should schedule transactions before all the TRBs have been fetched. This may increase performance by allowing transactions to start earlier  but may also have a negative effect because more TRQ.." "0,1"
line.long 0x8 "GUCTL3,Global User Control Register 3"
bitfld.long 0x8 31. "reserved_31,Reserved" "0,1"
newline
hexmask.long.byte 0x8 25.--30. 1. "reserved_30_22,Reserved"
newline
bitfld.long 0x8 22.--24. "CFGEP_CMD_SWITCHING_TIME_CTRL,Configure EP command switching time control" "0: Maximum Switching Frame boundary is 32ms,1: Maximum Switching Frame boundary is 1ms,2: Maximum Switching Frame boundary is 4ms,3: Maximum Switching Frame boundary is 8ms,?,?,?,?"
newline
bitfld.long 0x8 21. "BLOCK_CONCURRENT_IN_CTRL_XFERS,Block concurrent IN transactions during Control transfers" "0: Concurrent IN transfers are blocked during..,1: Concurrent IN transfers are not blocked during.."
newline
bitfld.long 0x8 20. "SSBI_SINGLE_EP_MODE_DISABLE,SS BI Single EP mode Disable" "0: Single EP mode in SS BI enabled,1: Single EP mode in SS BI disabled"
newline
bitfld.long 0x8 19. "DISEXTBUSCLKGT_U1U2L1,Disable External Bus Clock Gating in U1/U2/L1 state" "0,1"
newline
bitfld.long 0x8 18. "DISEXTBUSCLKGT,Disable External Bus Clock Gating" "0,1"
newline
bitfld.long 0x8 17. "RSVD_PERI_BANDWIDTH_FS,85percent bandwidth reservation for periodic transfer for FS bus behind HS hub" "0: 85% of FS bus bandwidth reserved for periodic..,1: 90% of FS bus bandwidth reserved for periodic.."
newline
bitfld.long 0x8 16. "USB20_RETRY_DISABLE,USB2.0 Internal Retry Disable" "0: Internal retry feature enabled,1: Internal retry feature disabled"
newline
bitfld.long 0x8 15. "reserved_15,Reserved" "0,1"
newline
bitfld.long 0x8 14. "reserved_14,Reserved" "0,1"
newline
bitfld.long 0x8 13. "reserved_13,Reserved" "0,1"
newline
hexmask.long.byte 0x8 9.--12. 1. "SVC_OPP_PER_HS_SEP,Service opportunities for HS bulk endpoints in single endpoint mode"
newline
bitfld.long 0x8 8. "BARB_BURST_ENABLE,LSP BARB Burst Support" "0: The lbc interface between LSP and BMU does not..,1: The lbc interface between LSP and BMU supports.."
newline
bitfld.long 0x8 7. "INTR_EP_PING_ENABLE,Interrupt EP PING Support" "0: Host does not send PING for SS/SSP interrupt EPs,1: Host sends PING for SS/SSP interrupt EPs"
newline
hexmask.long.byte 0x8 0.--6. 1. "PERIODIC_UF_THR_FSLS,Periodic microseconds threshold"
line.long 0xC "GTXFIFOPRIDEV,Global Device TXFIFO DMA Priority Register"
hexmask.long.word 0xC 16.--31. 1. "reserved_31_n,Reserved"
newline
hexmask.long.word 0xC 0.--15. 1. "gtxfifopridev,Device TxFIFO priority"
group.long 0xC618++0x23
line.long 0x0 "GTXFIFOPRIHST,Global Host TXFIFO DMA Priority Register (GTXFIFOPRIHST)"
hexmask.long 0x0 7.--31. 1. "reserved_31_y,Reserved"
newline
hexmask.long.byte 0x0 0.--6. 1. "gtxfifoprihst,Host TxFIFO priority"
line.long 0x4 "GRXFIFOPRIHST,Global Host RXFIFO DMA Priority Register"
hexmask.long 0x4 6.--31. 1. "reserved_31_y,Reserved"
newline
hexmask.long.byte 0x4 0.--5. 1. "grxfifoprihst,Host RxFIFO priority"
line.long 0x8 "GFIFOPRIDBC,Global Host Debug Capability DMA Priority Register"
hexmask.long 0x8 2.--31. 1. "reserved_31_2,Reserved"
newline
bitfld.long 0x8 0.--1. "gfifopridbc,Host DbC DMA priority" "0,1,2,3"
line.long 0xC "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register"
rbitfld.long 0xC 29.--31. "reserved_31_29,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xC 24.--28. 1. "hstrxfifo_mac,RX MAC ESS Priority Count"
newline
rbitfld.long 0xC 21.--23. "reserved_23_21,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xC 16.--20. 1. "hsttxfifo_mac,TX MAC ESS Priority Count"
newline
rbitfld.long 0xC 13.--15. "reserved_15_13,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xC 8.--12. 1. "hstrxfifo_dma,RX DMA ESS Priority Count"
newline
rbitfld.long 0xC 5.--7. "reserved_7_5,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0xC 0.--4. 1. "hsttxfifo_dma,TX DMA ESS Priority Count"
line.long 0x10 "GOSTDDMA_ASYNC,Global Number of Async Outstanding DMA Register"
hexmask.long.byte 0x10 24.--31. 1. "OSTDRX_ASYNC,Number of outstanding async RX DMA"
newline
hexmask.long.byte 0x10 16.--23. 1. "OSTDTX_ASYNC_ACTIVE,Number of outstanding async TX DMA for active FIFO/BI on USB"
newline
hexmask.long.byte 0x10 8.--15. 1. "OSTDTX_ASYNC_INACTIVE,Number of outstanding async TX DMA for inactive FIFO/BI on USB"
newline
hexmask.long.byte 0x10 0.--7. 1. "OSTDTX_ASYNC,Number of outstanding async TX DMA"
line.long 0x14 "GOSTDDMA_PRD,Global Number of Periodic Outstanding DMA Register"
hexmask.long.byte 0x14 24.--31. 1. "OSTDRX_PRD,Number of outstanding periodic RX DMA"
newline
hexmask.long.byte 0x14 16.--23. 1. "OSTDTX_PRD_ACTIVE,Number of outstanding periodic TX DMA for active FIFO/BI on USB"
newline
hexmask.long.byte 0x14 8.--15. 1. "OSTDTX_PRD_INACTIVE,Number of outstanding periodic TX DMA for inactive FIFO/BI on USB"
newline
hexmask.long.byte 0x14 0.--7. 1. "OSTDTX_PRD,Number of outstanding periodic TX DMA"
line.long 0x18 "GFLADJ,Global Frame Length Adjustment Register"
bitfld.long 0x18 31. "GFLADJ_REFCLK_240MHZDECR_PLS1,GFLADJ_REFCLK_240MHZDECR_PLS1" "0,1"
newline
hexmask.long.byte 0x18 24.--30. 1. "GFLADJ_REFCLK_240MHZ_DECR,This field indicates the decrement value that the controller applies for each ref_clk in order to derive a frame timer in terms of a 240-MHz clock."
newline
bitfld.long 0x18 23. "GFLADJ_REFCLK_LPM_SEL,The ref_clk frequencies supported are 16/17/19.2/20/24/39.7 MHz." "?,1: This bit internally enables the functionality of.."
newline
bitfld.long 0x18 22. "reserved_22,Reserved_22" "0,1"
newline
hexmask.long.word 0x18 8.--21. 1. "GFLADJ_REFCLK_FLADJ,This field indicates the frame length adjustment to be applied to the SOF/ITP counter that is running on the ref_clk."
newline
bitfld.long 0x18 7. "GFLADJ_30MHZ_SDBND_SEL,GFLADJ_30MHZ_SDBND_SEL" "0,1"
newline
bitfld.long 0x18 6. "reserved_6,Reserved_6" "0,1"
newline
hexmask.long.byte 0x18 0.--5. 1. "GFLADJ_30MHZ,GFLADJ_30MHZ"
line.long 0x1C "GUCTL4,Global User Control Register 4"
rbitfld.long 0x1C 31. "reserved_31,Reserved" "0,1"
newline
hexmask.long.byte 0x1C 26.--30. 1. "SSP_BWD_OVHD_ADJ,SS/SSP bandwidth adjuest control"
newline
hexmask.long.byte 0x1C 21.--25. 1. "reserved_25_21,Reserved"
newline
bitfld.long 0x1C 19.--20. "LOA_EOP_CHECK_CLKS_WORD,Number of clock cycles to check for EOP SE0 for LOA logic" "0,1,2,3"
newline
bitfld.long 0x1C 17.--18. "LOA_EOP_CHECK_CLKS_BYTE,Number of clock cycles to check for EOP SE0 for LOA logic" "0,1,2,3"
newline
hexmask.long.tbyte 0x1C 0.--16. 1. "CSR_TIMEOUT_VL,CSR Timeout Value"
line.long 0x20 "GUCTL5,Global User Control Register 5"
hexmask.long 0x20 0.--31. 1. "reserved_31_0,Reserved"
tree "GUSB2RHBCTL_REGS[0] (Global USB2 RHB Configuration Register)"
base ad:0x1100C640
group.long 0x0++0x3
line.long 0x0 "GUSB2RHBCTL,Global USB2 Root Hub Control Register"
hexmask.long.word 0x0 20.--31. 1. "Reserved_31_20,Reserved"
hexmask.long.byte 0x0 12.--19. 1. "OVRD_FS_INT_PKT_DEL,Overriding the internal FS interpacket delay."
hexmask.long.byte 0x0 4.--11. 1. "OVRD_HS_INT_PKT_DEL,Overriding the internal HS interpacket delay."
hexmask.long.byte 0x0 0.--3. 1. "OVRD_L1TIMEOUT,Overriding the driver programmed L1TIMEOUT value."
tree.end
base ad:0x11000000
newline
group.long 0xC700++0x1B
newline
line.long 0x0 "DCFG,Device Configuration Register."
hexmask.long.byte 0x0 25.--31. 1. "reserved_31_25,Reserved_31_25"
newline
bitfld.long 0x0 24. "reserved_24,Reserved" "0,1"
newline
bitfld.long 0x0 23. "IgnStrmPP,IgnoreStreamPP" "0,1"
newline
bitfld.long 0x0 22. "LPMCAP,LPM Capable" "0: LPM capability is not enabled,1: LPM capability is enabled"
newline
hexmask.long.byte 0x0 17.--21. 1. "NUMP,Number of Receive Buffers."
newline
hexmask.long.byte 0x0 12.--16. 1. "INTRNUM,Interrupt number"
newline
bitfld.long 0x0 10.--11. "reserved_10_11,Reserved" "0,1,2,3"
newline
hexmask.long.byte 0x0 3.--9. 1. "DEVADDR,Device Address."
newline
bitfld.long 0x0 0.--2. "DEVSPD,Device Speed." "0: High-speed,1: Full-speed,?,?,4: SuperSpeed,5: Enhanced SuperSpeed,?,?"
line.long 0x4 "DCTL,Device Control Register"
bitfld.long 0x4 31. "RUN_STOP,Run/Stop" "0,1"
newline
bitfld.long 0x4 30. "CSFTRST,Core Soft Reset" "0,1"
newline
bitfld.long 0x4 29. "reserved_29,Reserved1" "0,1"
newline
hexmask.long.byte 0x4 24.--28. 1. "HIRDTHRES,HIRD Threshold (HIRD_Thres)"
newline
hexmask.long.byte 0x4 20.--23. 1. "LPM_NYET_thres,When LPM Errata is enabled (DWC_USB31_EN_LPM_ERRATA=1):"
newline
bitfld.long 0x4 19. "KeepConnect,When '1'  this bit enables the save and restore programming model by preventing the controller from disconnecting from the host when DCTL.RunStop is set to '0'." "0,1"
newline
bitfld.long 0x4 18. "L1HibernationEn,L1HibernationEn" "0,1"
newline
bitfld.long 0x4 17. "CRS,Controller Restore State (CRS)" "0,1"
newline
bitfld.long 0x4 16. "CSS,Controller Save State (CSS)" "0,1"
newline
rbitfld.long 0x4 13.--15. "reserved_15_13,Reserved_15_13" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 12. "INITU2ENA,Initiate U2 Enable" "0: May not initiate U2,1: May initiate U2"
newline
bitfld.long 0x4 11. "ACCEPTU2ENA,Accept U2 Enable" "0: Reject U2 except when Force_LinkPM_Accept bit is..,1: Controller accepts transition to U2 state if.."
newline
bitfld.long 0x4 10. "INITU1ENA,Initiate U1 Enable" "0: May not initiate U1,1: May initiate U1"
newline
bitfld.long 0x4 9. "ACCEPTU1ENA,Accept U1 Enable" "0: Controller rejects U1 except when..,1: Controller accepts transition to U1 state if.."
newline
hexmask.long.byte 0x4 5.--8. 1. "ULSTCHNGREQ,ULSTCHNGREQ"
newline
hexmask.long.byte 0x4 1.--4. 1. "TSTCTL,Test Control"
newline
rbitfld.long 0x4 0. "reserved_0,Reserved_0" "0,1"
line.long 0x8 "DEVTEN,Device Event Enable Register"
hexmask.long.word 0x8 16.--31. 1. "reserved_31_16,Reserved_31_16"
newline
bitfld.long 0x8 15. "LDMEVTEN,LDM Response Event Enable." "0,1"
newline
bitfld.long 0x8 14. "L1WKUPEVTEN,L1 Resume Detected Event Enable." "0,1"
newline
rbitfld.long 0x8 13. "reserved_13,Reserved" "0,1"
newline
bitfld.long 0x8 12. "VENDEVTSTRCVDEN,Vendor Device Test LMP Received Event (VndrDevTstRcvedEn)" "0,1"
newline
bitfld.long 0x8 11. "reserved_11,Reserved_11" "0,1"
newline
bitfld.long 0x8 10. "reserved_10,Reserved_10" "0,1"
newline
bitfld.long 0x8 9. "ERRTICERREVTEN,Erratic Error Event Enable" "0,1"
newline
bitfld.long 0x8 8. "L1SUSPEN,L1 Suspend Event Enable" "0,1"
newline
bitfld.long 0x8 7. "SOFTEVTEN,Start of (u)frame" "0,1"
newline
bitfld.long 0x8 6. "U3L2L1SuspEn,U3/L2-L1 Suspend Event Enable." "0,1"
newline
bitfld.long 0x8 5. "HibernationReqEvtEn,This bit enables/disables the generation of the Hibernation Request Event." "0,1"
newline
bitfld.long 0x8 4. "WKUPEVTEN,Resume/Remote Wakeup Detected Event Enable." "0,1"
newline
bitfld.long 0x8 3. "ULSTCNGEN,USB/Link State Change Event Enable" "0,1"
newline
bitfld.long 0x8 2. "CONNECTDONEEVTEN,Connection Done Enable" "0,1"
newline
bitfld.long 0x8 1. "USBRSTEVTEN,USB Reset Enable" "0,1"
newline
bitfld.long 0x8 0. "DISSCONNEVTEN,Disconnect Detected Event Enable" "0,1"
line.long 0xC "DSTS,Device Status Register"
rbitfld.long 0xC 30.--31. "reserved_31_30,Reserved_31_30" "0,1,2,3"
newline
rbitfld.long 0xC 29. "DCNRD,Device Controller Not Ready" "0,1"
newline
eventfld.long 0xC 28. "SRE,Save Restore Error - currently not supported" "0,1"
newline
rbitfld.long 0xC 26.--27. "reserved_27_26,Reserved" "0,1,2,3"
newline
rbitfld.long 0xC 25. "RSS,RSS Restore State Status" "0,1"
newline
rbitfld.long 0xC 24. "SSS,SSS Save State Status" "0,1"
newline
rbitfld.long 0xC 23. "COREIDLE,Core Idle" "0,1"
newline
rbitfld.long 0xC 22. "DEVCTRLHLT,Device Controller Halted" "0,1"
newline
hexmask.long.byte 0xC 18.--21. 1. "USBLNKST,USBLNKST."
newline
rbitfld.long 0xC 17. "RXFIFOEMPTY,RxFIFO Empty." "0,1"
newline
hexmask.long.word 0xC 3.--16. 1. "SOFFN,Frame/Microframe/ITP Number of the Received SOF."
newline
rbitfld.long 0xC 0.--2. "CONNECTSPD,Connected Speed (ConnectSpd)" "0: High-speed,1: Full-speed,?,?,4: SuperSpeed,5: Enhanced SuperSpeed,?,?"
line.long 0x10 "DGCMDPAR,Device Generic Command Parameter Register"
hexmask.long 0x10 0.--31. 1. "PARAMETER,PARAMETER"
line.long 0x14 "DGCMD,Device Generic Command Register"
hexmask.long.word 0x14 16.--31. 1. "reserved_31_16,Reserved_31_16"
newline
hexmask.long.byte 0x14 12.--15. 1. "CMDSTATUS,Command Status"
newline
rbitfld.long 0x14 11. "reserved_11,Reserved_11" "0,1"
newline
bitfld.long 0x14 10. "CMDACT,Command Active" "0,1"
newline
rbitfld.long 0x14 9. "reserved_9,Reserved_9" "0,1"
newline
bitfld.long 0x14 8. "CMDIOC,Command Interrupt on Complete" "0,1"
newline
hexmask.long.byte 0x14 0.--7. 1. "CMDTYP,Generic Command Type"
line.long 0x18 "DCTL1,Device Control Register1."
hexmask.long 0x18 3.--31. 1. "reserved_31_3,reserved_31_3"
newline
bitfld.long 0x18 2. "EN_ENDXFER_ON_RJCT_STRM,EN_ENDXFER_ON_RJCT_STRM" "0: Feature disabled,1: Feature enabled"
newline
bitfld.long 0x18 1. "DIS_CLRSPR_SXFER,DIS_CLRSPR_SXFER" "0: The SPR bit is cleared when a Start Transfer..,1: The SPR bit is not cleared when a Start Transfer.."
newline
bitfld.long 0x18 0. "reserved_0,reserved_0" "0,1"
group.long 0xC720++0x7
line.long 0x0 "DALEPENA,Device Active USB Endpoint Enable Register."
hexmask.long 0x0 0.--31. 1. "USBACTEP,USBACTEP"
line.long 0x4 "DLDMENA,Device LDM Request Control Register."
hexmask.long.word 0x4 16.--31. 1. "LDMADJ,LDMADJ"
newline
hexmask.long.byte 0x4 8.--15. 1. "LDMDUR,LDMDUR"
newline
hexmask.long.byte 0x4 4.--7. 1. "NOLOWPWRDUR,NOLOWPWRDUR"
newline
bitfld.long 0x4 1.--3. "LDMRQS,LDMRQS" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 0. "LDMENA,LDMENA" "0,1"
tree "DEPCMDPAR2_REGS"
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x1100C800 ad:0x1100C810 ad:0x1100C820 ad:0x1100C830 ad:0x1100C840 ad:0x1100C850 ad:0x1100C860 ad:0x1100C870 ad:0x1100C880 ad:0x1100C890 ad:0x1100C8A0 ad:0x1100C8B0 ad:0x1100C8C0 ad:0x1100C8D0 ad:0x1100C8E0 ad:0x1100C8F0)
tree "DEPCMDPAR2_REGS[$1]"
base $2
group.long ($2)++0xF
line.long 0x0 "DEPCMDPAR2,Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)"
hexmask.long 0x0 0.--31. 1. "PARAMETER,PARAMETER"
line.long 0x4 "DEPCMDPAR1,Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n)"
hexmask.long 0x4 0.--31. 1. "PARAMETER,PARAMETER"
line.long 0x8 "DEPCMDPAR0,Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n)"
hexmask.long 0x8 0.--31. 1. "PARAMETER,PARAMETER"
line.long 0xC "DEPCMD,Device Physical Endpoint-n Command Register"
hexmask.long.word 0xC 16.--31. 1. "COMMANDPARAM,Command Parameters or Event Parameters"
hexmask.long.byte 0xC 12.--15. 1. "CMDSTATUS,Command Completion Status (CmdStatus)"
bitfld.long 0xC 11. "HIPRI_FORCERM,ForceRM" "0,1"
bitfld.long 0xC 10. "CMDACT,Command Active (CmdAct)" "0,1"
bitfld.long 0xC 9. "reserved_9,Reserved" "0,1"
bitfld.long 0xC 8. "CMDIOC,CMDIOC" "0,1"
hexmask.long.byte 0xC 4.--7. 1. "reserved_7_4,Reserved_7_4"
newline
hexmask.long.byte 0xC 0.--3. 1. "CMDTYP,Command Type"
tree.end
repeat.end
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x1100C900 ad:0x1100C910 ad:0x1100C920 ad:0x1100C930 ad:0x1100C940 ad:0x1100C950 ad:0x1100C960 ad:0x1100C970 ad:0x1100C980 ad:0x1100C990 ad:0x1100C9A0 ad:0x1100C9B0 ad:0x1100C9C0 ad:0x1100C9D0 ad:0x1100C9E0 ad:0x1100C9F0)
tree "DEPCMDPAR2_REGS[$1]"
base $2
group.long ($2)++0xF
line.long 0x0 "DEPCMDPAR2,Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n)"
hexmask.long 0x0 0.--31. 1. "PARAMETER,PARAMETER"
line.long 0x4 "DEPCMDPAR1,Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n)"
hexmask.long 0x4 0.--31. 1. "PARAMETER,PARAMETER"
line.long 0x8 "DEPCMDPAR0,Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n)"
hexmask.long 0x8 0.--31. 1. "PARAMETER,PARAMETER"
line.long 0xC "DEPCMD,Device Physical Endpoint-n Command Register"
hexmask.long.word 0xC 16.--31. 1. "COMMANDPARAM,Command Parameters or Event Parameters"
hexmask.long.byte 0xC 12.--15. 1. "CMDSTATUS,Command Completion Status (CmdStatus)"
bitfld.long 0xC 11. "HIPRI_FORCERM,ForceRM" "0,1"
bitfld.long 0xC 10. "CMDACT,Command Active (CmdAct)" "0,1"
bitfld.long 0xC 9. "reserved_9,Reserved" "0,1"
bitfld.long 0xC 8. "CMDIOC,CMDIOC" "0,1"
hexmask.long.byte 0xC 4.--7. 1. "reserved_7_4,Reserved_7_4"
newline
hexmask.long.byte 0xC 0.--3. 1. "CMDTYP,Command Type"
tree.end
repeat.end
tree.end
tree "DEV_IMOD_REGS[0] (Device Interrupt Moderation Register Array)"
base ad:0x1100CA00
group.long 0x0++0x3
line.long 0x0 "DEV_IMOD,Device Interrupt Moderation Register (DEV_IMOD)"
hexmask.long.word 0x0 16.--31. 1. "DEVICE_IMODC,Interrupt Moderation Down Counter"
hexmask.long.word 0x0 0.--15. 1. "DEVICE_IMODI,Moderation Interval (DEVICE_IMODI)"
tree.end
tree "LINK_REGS[0] (LINK REGISTERS)"
base ad:0x1100D000
group.long 0x0++0x4F
line.long 0x0 "LU1LFPSRXTIM,U1_LFPS_RX_TIMER_REG"
hexmask.long.byte 0x0 24.--31. 1. "gen2_u1_lfps_exit_rx_clk,gen2 U1_LFPS_EXIT_RX_CLKS"
hexmask.long.byte 0x0 16.--23. 1. "gen2_u1_exit_rsp_rx_clk,gen2 U1_EXIT_RESP_RX_CLKS"
newline
hexmask.long.byte 0x0 8.--15. 1. "gen1_u1_lfps_exit_rx_clk,gen1 U1_LFPS_EXIT_RX_CLKS"
hexmask.long.byte 0x0 0.--7. 1. "gen1_u1_exit_rsp_rx_clk,gen1 U1_EXIT_RESP_RX_CLKS"
line.long 0x4 "LU1LFPSTXTIM,U1 LFPS TX TIMER REGISTER"
rbitfld.long 0x4 30.--31. "reserved_2,Reserved" "0,1,2,3"
hexmask.long.word 0x4 16.--29. 1. "gen2_u1_exit_resp_tx_clk,gen2 U1_EXIT_RESP_TX_CLKS"
newline
rbitfld.long 0x4 14.--15. "reserved_1,Reserved" "0,1,2,3"
hexmask.long.word 0x4 0.--13. 1. "gen1_u1_exit_rsp_tx_clk,gen1 U1_EXIT_RESP_TX_CLKS"
line.long 0x8 "LU2LFPSRXTIM,U2 LFPS RX TIMER REGISTER"
hexmask.long.byte 0x8 24.--31. 1. "gen2_u2_lfps_exit_rx_clk,gen2 U2_LFPS_EXIT_RX_CLKS"
hexmask.long.byte 0x8 16.--23. 1. "gen2_u2_exit_rsp_rx_clk,gen2 U2_EXIT_RESP_RX_CLKS"
newline
hexmask.long.byte 0x8 8.--15. 1. "gen1_u2_lfps_exit_rx_clk,gen1 U2_LFPS_EXIT_RX_CLKS"
hexmask.long.byte 0x8 0.--7. 1. "gen1_u2_exit_rsp_rx_clk,gen1 U2_EXIT_RESP_RX_CLKS"
line.long 0xC "LU2LFPSTXTIM,U2 LFPS TX TIMER REG REGISTER"
hexmask.long.tbyte 0xC 14.--31. 1. "reserved_1,Reserved"
hexmask.long.word 0xC 0.--13. 1. "u2_exit_rsp_tx_us,U2_EXIT_RESP_TX_US"
line.long 0x10 "LU3LFPSRXTIM,U3 LFPS RX TIMER REGS REGISTER"
hexmask.long.byte 0x10 24.--31. 1. "gen2_u3_lfps_exit_rx_clk,gen2 U3_LFPS_EXIT_RX_CLKS"
hexmask.long.byte 0x10 16.--23. 1. "gen2_u3_exit_rsp_rx_clk,gen2 U3_EXIT_RESP_RX_CLKS"
newline
hexmask.long.byte 0x10 8.--15. 1. "gen1_u3_lfps_exit_rx_clk,gen1 U3_LFPS_EXIT_RX_CLKS"
hexmask.long.byte 0x10 0.--7. 1. "gen1_u3_exit_rsp_rx_clk,gen1 U3_EXIT_RESP_RX_CLKS"
line.long 0x14 "LU3LFPSTXTIM,U3 LFPS TX TIMER REGS REGISTER"
bitfld.long 0x14 30.--31. "reserved_31_30,reserved_31_30" "0,1,2,3"
hexmask.long.word 0x14 16.--29. 1. "gen2_u3_exit_tx_clk,gen2 U3_EXIT_RESP_TX_CLKS"
newline
bitfld.long 0x14 14.--15. "reserved_15_14,reserved_15_14" "0,1,2,3"
hexmask.long.word 0x14 0.--13. 1. "gen1_u3_exit_rsp_tx_clk,gen1 U3_EXIT_RESP_TX_CLKS"
line.long 0x18 "LPINGLFPSTIM,PING LFPS TIMER REGISTER"
hexmask.long.byte 0x18 26.--31. 1. "gen2_lfps_ping_burst_clk,gen2 LFPS_PING_BURST_CLKS: TX ping.LFPS tBurst"
hexmask.long.byte 0x18 20.--25. 1. "gen2_lfps_ping_max_clk,gen2 LFPS_PING_MAX_CLKS: Max RX ping.LFPS tBurst"
newline
hexmask.long.byte 0x18 16.--19. 1. "gen2_lfps_ping_min_clk,gen2 LFPS_PING_MIN_CLKS: Min RX ping.LFPS tBurst"
hexmask.long.byte 0x18 10.--15. 1. "gen1_lfps_ping_burst_clk,gen1 LFPS_PING_BURST_CLKS: TX ping.LFPS tBurst"
newline
hexmask.long.byte 0x18 4.--9. 1. "gen1_lfps_ping_max_clk,gen1 LFPS_PING_MAX_CLKS: Max RX ping.LFPS tBurst"
hexmask.long.byte 0x18 0.--3. 1. "gen1_lfps_ping_min_clk,gen1 LFPS_PING_MIN_CLKS: Minx RX ping.LFPS tBurst"
line.long 0x1C "LPOLLLFPSTXTIM,POLL LFPS TX TIMER REGISTER"
hexmask.long.word 0x1C 22.--31. 1. "reserved_31_22,reserved_31_22"
hexmask.long.word 0x1C 11.--21. 1. "lfps_poll_space_clk,LFPS_POLL_SPACE_CLKS: space between Polling.LFPS"
newline
hexmask.long.word 0x1C 0.--10. 1. "lfps_poll_burst_clk,LFPS_POLL_BURST_CLKS: TX Polling.LFPS tBurst"
line.long 0x20 "LSKIPFREQ,SKIP FREQUENCY REGISTER"
rbitfld.long 0x20 31. "Reserved_1,Reserved_1" "0,1"
bitfld.long 0x20 28.--30. "u1_resid_timer_us,Programmable U1 MIN RESIDENCY TIMER" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x20 27. "en_pm_timer_us,Enable us PM timers" "0,1"
bitfld.long 0x20 24.--26. "pm_lc_timer_us,Programmable PM_LC_TIMER" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x20 20.--23. 1. "pm_entry_timer_us,Programmable PM_ENTRY_TIMER"
hexmask.long.byte 0x20 12.--19. 1. "gen2_skp_freq,gen2 SKP frequency"
newline
hexmask.long.word 0x20 0.--11. 1. "gen1_skp_freq,gen1 SKP frequency"
line.long 0x24 "LLUCTL,TX TS1 COUNT REGISTER"
bitfld.long 0x24 31. "Reserved_31,Reserved" "0,1"
bitfld.long 0x24 30. "inverse_sync_header,For Gen2 polarity detection  link uses data block (0011b) sync header for SYNC OS instead of control block (1100b)." "0,1"
newline
bitfld.long 0x24 29. "support_p4_pg,PHY P4 Power gate mode (PG) is enabled." "0,1"
bitfld.long 0x24 28. "support_p4,Support PHY P3.CPM and P4." "0,1"
newline
hexmask.long.byte 0x24 24.--27. 1. "delay_tx_gen1_dp,delay_tx_gen1_dp."
bitfld.long 0x24 23. "DisRxDet_LTSSM_Timer_Ovrrd,DisRxDet_LTSSM_Timer_Ovrrd." "0,1"
newline
bitfld.long 0x24 22. "force_dpp_truncate,force_dpp_truncate." "0,1"
bitfld.long 0x24 21. "en_dpp_truncate,en_dpp_truncate." "0,1"
newline
hexmask.long.byte 0x24 16.--20. 1. "pending_hp_timer_us,pending_hp_timer_us."
bitfld.long 0x24 15. "en_us_hp_timer,en_us_hp_timer." "0,1"
newline
bitfld.long 0x24 13.--14. "ring_buf_d_delay,ring_buf_d_delay." "0,1,2,3"
bitfld.long 0x24 12. "U2P3CPMok,P3CPM OK for U2/SSInactive (U2P3CPMok)" "0: During link state U2/ESS,1: During link state U2/ESS"
newline
bitfld.long 0x24 11. "en_reset_pipe_after_phy_mux,en_reset_pipe_after_phy_mux." "0,1"
bitfld.long 0x24 10. "force_gen1,Force Gen1" "0,1"
newline
bitfld.long 0x24 9. "gen2_loopback_entry_mode,Gen2 loopback entry mode." "0,1"
bitfld.long 0x24 8. "gen1_loopback_entry_mode,Gen1 loopback entry mode." "0,1"
newline
bitfld.long 0x24 7. "mask_pipe_reset,Mask pipe reset." "0,1"
bitfld.long 0x24 6. "delay_ux_after_lpma,delay_ux_after_lpma." "0,1"
newline
bitfld.long 0x24 5. "no_ux_exit_p0_trans,no_ux_exit_p0_trans." "0,1"
hexmask.long.byte 0x24 0.--4. 1. "tx_ts1_cnt,Additional TX_TS1_count"
line.long 0x28 "LPTMDPDELAY,PTM DATAPATH DELAY REGISTER"
hexmask.long.byte 0x28 27.--31. 1. "rx_path_delay_gen2,rx_path_delay_gen2"
hexmask.long.byte 0x28 22.--26. 1. "tx_path_delay_gen2,tx_path_delay_gen2"
newline
hexmask.long.word 0x28 10.--21. 1. "p3cpmp4_residency,Minimum number of suspend_clk periods that"
hexmask.long.byte 0x28 5.--9. 1. "rx_path_delay,rx_path_delay"
newline
hexmask.long.byte 0x28 0.--4. 1. "tx_path_delay,tx_path_delay"
line.long 0x2C "LSCDTIM1,SCD TIMER 1 REGISTER"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved_1,Reserved_1"
hexmask.long.word 0x2C 12.--23. 1. "scd_bit0_rpt_max_clk,SCD_BIT0_REPEAT_MAX_CLKS"
newline
hexmask.long.word 0x2C 0.--11. 1. "cd_bit0_rpt_min_clk,CD_BIT0_REPEAT_MIN_CLKS"
line.long 0x30 "LSCDTIM2,SCD TIMER2 REGISTER"
hexmask.long.byte 0x30 24.--31. 1. "Reserved_1,Reserved_1"
hexmask.long.word 0x30 12.--23. 1. "scd_bit1_rpt_max_clk,SCD_BIT1_REPEAT_MAX_CLKS"
newline
hexmask.long.word 0x30 0.--11. 1. "cd_bit1_rpt_min_clk,CD_BIT1_REPEAT_MIN_CLKS"
line.long 0x34 "LSCDTIM3,SCD TIMER3 REGISTER"
hexmask.long.word 0x34 20.--31. 1. "lfps_scd_space1_clk,LFPS_SCD_SPACE1_CLKS"
hexmask.long.word 0x34 8.--19. 1. "lfps_scd_space0_clk,LFPS_SCD_SPACE0_CLKS"
newline
hexmask.long.byte 0x34 0.--7. 1. "lfps_scd_burst_clk,LFPS_SCD_BURST_CLKS"
line.long 0x38 "LSCDTIM4,SCD TIMER4 REGISTER"
hexmask.long.tbyte 0x38 12.--31. 1. "Reserved_1,Reserved_1"
hexmask.long.word 0x38 0.--11. 1. "lfps_scd_last_space,LFPS_SCD_LAST_SPACE_CLKS"
line.long 0x3C "LLPBMTIM1,LPBM TIMER1 REGISTER"
hexmask.long.byte 0x3C 24.--31. 1. "lfps_lbps1_burst_max_clk,LFPS_LBPS1_BURST_MAX_CLKS"
hexmask.long.byte 0x3C 16.--23. 1. "lfps_lbps1_burst_min_clk,LFPS_LBPS1_BURST_MIN_CLKS"
newline
hexmask.long.byte 0x3C 8.--15. 1. "lfps_lbps0_burst_max_clk,LFPS_LBPS0_BURST_MAX_CLKS"
hexmask.long.byte 0x3C 0.--7. 1. "lfps_lbps0_burst_min_clk,LFPS_LBPS0_BURST_MIN_CLKS"
line.long 0x40 "LLPBMTIM2,LPBM TIMER2 REGISTER"
hexmask.long.word 0x40 18.--31. 1. "Reserved_1,Reserved_1"
hexmask.long.word 0x40 9.--17. 1. "lfps_lbpm_tpwm_max_clk,LFPS_LBPM_TPWM_MAX_CLKS"
newline
hexmask.long.word 0x40 0.--8. 1. "lfps_lbpm_tpwm_min_clk,LFPS_LBPM_TPWM_MIN_CLKS"
line.long 0x44 "LLPBMTXTIM,LPBM TX TIMER REGISTER"
rbitfld.long 0x44 30.--31. "Reserved_2,Reserved" "0,1,2,3"
hexmask.long.word 0x44 20.--29. 1. "lfps_lpbs_tpwm_clk,LFPS LBPS TPWM CLKS"
newline
bitfld.long 0x44 18.--19. "Reserved_1,Reserved" "0,1,2,3"
hexmask.long.word 0x44 8.--17. 1. "lfps_lbps_burst1_clk,LFPS LBPS BURST1 CLKs"
newline
hexmask.long.byte 0x44 0.--7. 1. "lfps_lbps_burst0_clk,LFPS LBPS BURST0 CLKs"
line.long 0x48 "LLINKERRINJ,LINK ERROR TYPE INJECT REGISTER"
bitfld.long 0x48 31. "pipe_txdata,PIPE TxData" "0,1"
bitfld.long 0x48 30. "TX_insert_defer,TX Insert Deferred Bit" "0,1"
newline
bitfld.long 0x48 29. "TX_insert_delay,TX Insert Delayed Bit" "0,1"
bitfld.long 0x48 28. "TX_TS2,TX_TS2 : Corrupt entired TS2" "0,1"
newline
bitfld.long 0x48 27. "TX_TS1,TX_TS1 : Corrupt entired TS1" "0,1"
bitfld.long 0x48 26. "TX_TSEQ,TX_TSEQ : Corrupt entired TSEQ" "0,1"
newline
bitfld.long 0x48 25. "TX_LFR,TX_LFR" "0,1"
bitfld.long 0x48 24. "TX_delay_credit_rl,TX Delay credit release" "0,1"
newline
bitfld.long 0x48 23. "TX_one_srt_frame_sybl,TX DPP all start framing symbol" "0,1"
bitfld.long 0x48 22. "TX_all_end_frame_sybl,TX DPP all end framing symbol" "0,1"
newline
bitfld.long 0x48 21. "TX_one_end_frame_sybl,TX DPP one end framing symbol" "0,1"
bitfld.long 0x48 20. "TX_all_frame_sybl,TX TPH/DPH all framing symbol" "0,1"
newline
bitfld.long 0x48 19. "TX_one_frame_sybl,TX TPH/DPH one framing symbol" "0,1"
bitfld.long 0x48 18. "TX_CRC32,TX_CRC32" "0,1"
newline
bitfld.long 0x48 17. "TX_CRC16,TX_CRC16" "0,1"
bitfld.long 0x48 16. "TX_CRC5,TX_CRC5" "0,1"
newline
bitfld.long 0x48 15. "Rx_pipe_rxdata,Rx_pipe_rxdata" "0,1"
bitfld.long 0x48 14. "RX_insert_defer,RX_insert_defer" "0,1"
newline
bitfld.long 0x48 13. "RX_insert_delay,RX_insert_delay" "0,1"
bitfld.long 0x48 12. "RX_TS2,RX_TS2" "0,1"
newline
bitfld.long 0x48 11. "RX_TS1,RX_TS1" "0,1"
bitfld.long 0x48 10. "RX_TSEQ,RX_TSEQ" "0,1"
newline
bitfld.long 0x48 9. "RX_LFR,RX_LFR" "0,1"
bitfld.long 0x48 8. "RX_all_start_frame_sybl,DPP all start framing symbol" "0,1"
newline
bitfld.long 0x48 7. "RX_one_srt_frame_sybl,DPP one start framing symbol" "0,1"
bitfld.long 0x48 6. "RX_all_end_frame_sybl,DPP all end framing symbol" "0,1"
newline
bitfld.long 0x48 5. "RX_one_end_frame_sybl,RX DPP one end framing symbol" "0,1"
bitfld.long 0x48 4. "RX_all_frame_sybl,RX TPH/DPH all framing symbol" "0,1"
newline
bitfld.long 0x48 3. "RX_one_frame_sybl,RX TPH/DPH one framing symbol" "0,1"
bitfld.long 0x48 2. "RX_CRC32,RX_CRC32" "0,1"
newline
bitfld.long 0x48 1. "RX_CRC16,RX_CRC16" "0,1"
bitfld.long 0x48 0. "RX_CRC5,RX_CRC5" "0,1"
line.long 0x4C "LLINKERRINJEN,LINK ERROR INJECT ENABLE REGISTER"
hexmask.long.word 0x4C 16.--31. 1. "disable_inj_err_cnt,Disable injected error count"
hexmask.long.word 0x4C 0.--15. 1. "B2B_err_cnt,B2B error count"
rgroup.long 0x50++0x7
line.long 0x0 "GDBGLTSSM,Global Debug LTSSM Register"
bitfld.long 0x0 31. "reserved_31_31,Reserved_31_31" "0,1"
bitfld.long 0x0 30. "RxElecidle,RxElecidle" "0,1"
newline
bitfld.long 0x0 27.--29. "reserved1,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 26. "LTDBTIMEOUT,LTDB Timeout (LTDBTimeout)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "LTDBLINKSTATE,LTDB Link State (LTDBLinkState)"
hexmask.long.byte 0x0 18.--21. 1. "LTDBSUBSTATE,LTDB Sub-State (LTDBSubState)"
newline
bitfld.long 0x0 17. "ELASTICBUFFERMODE,Elastic Buffer Mode (ElasticBufferMode)" "0,1"
bitfld.long 0x0 16. "TXELECLDLE,Tx Elec Idle (TxElecIdle)" "0,1"
newline
bitfld.long 0x0 15. "RXPOLARITY,Rx Polarity (RxPolarity)" "0,1"
bitfld.long 0x0 14. "TxDetRxLoopback,Tx Detect Rx/Loopback (TxDetRxLoopback)" "0,1"
newline
bitfld.long 0x0 11.--13. "LTDBPhyCmdState,LTSSM PHY command State (LTDBPhyCmdState)" "0: PHY_IDLE,1: PHY_DET,?,?,?,?,?,?"
bitfld.long 0x0 9.--10. "POWERDOWN,POWERDOWN (PowerDown)" "0,1,2,3"
newline
bitfld.long 0x0 8. "RXEQTRAIN,RxEq Train" "0,1"
bitfld.long 0x0 6.--7. "TXDEEMPHASIS,TXDEEMPHASIS (TxDeemphasis)" "0,1,2,3"
newline
bitfld.long 0x0 3.--5. "LTDBClkState,LTSSM Clock State (LTDBClkState)" "0: CLK_NORM,1: CLK_TO_P3,?,?,?,?,?,?"
bitfld.long 0x0 2. "TXSWING,Tx Swing (TxSwing)" "0,1"
newline
bitfld.long 0x0 1. "RXTERMINATION,Rx Termination (RxTermination)" "0,1"
bitfld.long 0x0 0. "TXONESZEROS,Tx Ones/Zeros (TxOnesZeros)" "0,1"
line.long 0x4 "GDBGLNMCC,Global Debug LNMCC Register"
hexmask.long.word 0x4 16.--31. 1. "LNMCC_LSERC,This field indicates the value of link soft error counter for the port selected in the GDBGFIFOSPACE.PortSelect field."
hexmask.long.byte 0x4 9.--15. 1. "reserved_16_9,Reserved_16_9"
newline
hexmask.long.word 0x4 0.--8. 1. "LNMCC_BERC,This field indicates the bit error rate information for the port selected in the GDBGFIFOSPACE.PortSelect field."
group.long 0x58++0x17
line.long 0x0 "LLINKDBGCTRL,LINK DEBUG CONTROL REGISTER"
bitfld.long 0x0 31. "retry_DP,Link retries full DP instead of DPH in Gen2. When link needs to resend header due to LBAD or recovery replay  enabling this bit makes link to send full DPH + DPP. This workaround is for a non-compliance 3.1 device" "0,1"
rbitfld.long 0x0 30. "trigger_end_sts,Trigger End Status" "0,1"
newline
rbitfld.long 0x0 29. "trigger_start_sts,Trigger Start Status" "0,1"
bitfld.long 0x0 28. "link_state_trigger_descrambled,Link State Trigger Descrambled Debug Control" "0,1"
newline
bitfld.long 0x0 27. "link_state_trigger_scrambled,Link State Trigger Scrambled Debug Control" "0,1"
bitfld.long 0x0 26. "pipe_txdetectrxlb_trigger,PIPE TXDETECTRXLB Trigger Debug Control" "0,1"
newline
bitfld.long 0x0 25. "pipe_rxlecidle_trigger,PIPE RXELECIDLE Trigger Debug Control" "0,1"
bitfld.long 0x0 24. "pipe_phystatus_trigger,PIPE PHYSTATUS Trigger Debug Control" "0,1"
newline
hexmask.long.byte 0x0 20.--23. 1. "sub_state_trigger,Sub-state Trigger"
hexmask.long.byte 0x0 16.--19. 1. "link_state_trigger,Link State Trigger"
newline
hexmask.long.byte 0x0 12.--15. 1. "peri_rsc_rxfifo_number,Periodic Resource RXFIFO Number"
hexmask.long.byte 0x0 8.--11. 1. "peri_rsc_txfifo_number,Periodic Resource TXFIFO Number"
newline
hexmask.long.byte 0x0 4.--7. 1. "rxfifo_number,RXFIFO Number"
hexmask.long.byte 0x0 0.--3. 1. "txfifo_number,TXFIFO Number"
line.long 0x4 "LLINKDBGCNTTRIG,LINK DEBUG COUNT TRIGGER REGISTER"
hexmask.long.word 0x4 16.--31. 1. "stp_cnt,Stop Count"
hexmask.long.word 0x4 0.--15. 1. "srt_cnt,Start Count"
line.long 0x8 "LCSR_TX_DEEMPH,LCSR_TX_DEEMPH REGISTER"
hexmask.long.word 0x8 18.--31. 1. "Reserved_31_18,Reserved_31_18"
hexmask.long.tbyte 0x8 0.--17. 1. "csr_tx_deemph_field_1,18 bits of TX deemphasis  defined in PIPE4 spec  in normal operation (non-compliance mode)"
line.long 0xC "LCSR_TX_DEEMPH_1,LCSR_TX_DEEMPH_1 REGISTER"
hexmask.long.word 0xC 18.--31. 1. "Reserved_31_18,Reserved_31_18"
hexmask.long.tbyte 0xC 0.--17. 1. "csr_tx_deemph_1_field_1,18 bits of TX deemphasis used by controller in gen2 compliance pattern 13"
line.long 0x10 "LCSR_TX_DEEMPH_2,LCSR_TX_DEEMPH_2 REGISTER"
hexmask.long.word 0x10 18.--31. 1. "Reserved_31_18,Reserved_31_18"
hexmask.long.tbyte 0x10 0.--17. 1. "csr_tx_deemph_2_field_1,18 bits of TX deemphasis used by controller in gen2 compliance pattern 14"
line.long 0x14 "LCSR_TX_DEEMPH_3,LCSR_TX_DEEMPH_3 REGISTER"
hexmask.long.word 0x14 18.--31. 1. "Reserved_31_18,Reserved"
hexmask.long.tbyte 0x14 0.--17. 1. "csr_tx_deemph_3_field_1,18 bits of TX deemphasis used by controller in gen2 compliance pattern 16"
rgroup.long 0x70++0x7
line.long 0x0 "LCSRPTMDEBUG1,LCSRPTMDEBUG1 REGISTER: This register stores LDM t1 and LDM t32 values"
bitfld.long 0x0 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3"
hexmask.long.word 0x0 17.--29. 1. "LDM_T32,LDM_T32"
newline
hexmask.long.tbyte 0x0 0.--16. 1. "LDM_T1,LDM_T1"
line.long 0x4 "LCSRPTMDEBUG2,LCSRPTMDELAY2 REGISTER : This register stores LSM t4 value"
hexmask.long.word 0x4 17.--31. 1. "RESERVED_31_17,Reserved"
hexmask.long.tbyte 0x4 0.--16. 1. "LDM_T4,LDM_T4"
group.long 0x78++0x3
line.long 0x0 "LPTMDPDELAY2,PTM DATAPATH DELAY REGISTER2"
hexmask.long.word 0x0 20.--31. 1. "Reserved_1,Reserved_1"
hexmask.long.byte 0x0 15.--19. 1. "link_rx_delay_gen2,link_rx_delay_gen2"
newline
hexmask.long.byte 0x0 10.--14. 1. "link_tx_delay_gen2,link_tx_delay_gen2"
hexmask.long.byte 0x0 5.--9. 1. "link_rx_delay_gen1,link_rx_delay_gen1"
newline
hexmask.long.byte 0x0 0.--4. 1. "link_tx_delay_gen1,link_tx_delay_gen1"
tree.end
tree "RHBDBG_REGS[0] (RHB DEBUG REGISTERS)"
base ad:0x1100D800
group.long 0x0++0x3
line.long 0x0 "BU31RHBDBG,U31 ROOT HUB DEBUG REG"
hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_31_10,Reserved_31_10"
hexmask.long.byte 0x0 4.--9. 1. "reserved_9_4,Reserved"
bitfld.long 0x0 3. "tpcfg_tout_ctrl,tpcfg_tout_ctrl" "0: The port configuration timeout counter does not..,1: The port configuration timeout counter resets.."
bitfld.long 0x0 1.--2. "pcap,pcap" "0,1,2,3"
newline
bitfld.long 0x0 0. "ovrcur,ovrcur" "0,1"
tree.end
base ad:0x11000000
tree "Rsvd_REGS"
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x1100C728 ad:0x1100C72C ad:0x1100C730 ad:0x1100C734 ad:0x1100C738 ad:0x1100C73C ad:0x1100C740 ad:0x1100C744 ad:0x1100C748 ad:0x1100C74C ad:0x1100C750 ad:0x1100C754 ad:0x1100C758 ad:0x1100C75C ad:0x1100C760 ad:0x1100C764)
tree "Rsvd_REGS[$1]"
base $2
rgroup.long ($2)++0x3
line.long 0x0 "Rsvd,Reserved"
hexmask.long 0x0 0.--31. 1. "reserved_31_0,Reserved_31_0"
tree.end
repeat.end
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x1100C768 ad:0x1100C76C ad:0x1100C770 ad:0x1100C774 ad:0x1100C778 ad:0x1100C77C ad:0x1100C780 ad:0x1100C784 ad:0x1100C788 ad:0x1100C78C ad:0x1100C790 ad:0x1100C794 ad:0x1100C798 ad:0x1100C79C ad:0x1100C7A0 ad:0x1100C7A4)
tree "Rsvd_REGS[$1]"
base $2
rgroup.long ($2)++0x3
line.long 0x0 "Rsvd,Reserved"
hexmask.long 0x0 0.--31. 1. "reserved_31_0,Reserved_31_0"
tree.end
repeat.end
tree.end
newline
rgroup.long 0xCC00++0x3
newline
line.long 0x0 "rsvd0_reg,Reserved Register"
hexmask.long 0x0 0.--31. 1. "rsvd_field,Reserved Register"
group.long 0xD84C++0x13
line.long 0x0 "BRAMHIADDR,RAM HIGHER ADDRESS REGISTER"
hexmask.long.word 0x0 21.--31. 1. "Reserved_2,Reserved_2"
newline
bitfld.long 0x0 18.--20. "ram_select,Chip select for RAM 0-4" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 12.--17. 1. "ramhiaddr,Partial decoding bits for RAM higher address"
newline
hexmask.long.word 0x0 0.--11. 1. "Reserved_1,Reserved_1"
line.long 0x4 "BRSERRCNT,RAM Single Error Count. 6 bit count for each od 5 RAMS"
rbitfld.long 0x4 30.--31. "Reserved_1,Reserved_1" "0,1,2,3"
newline
hexmask.long.byte 0x4 24.--29. 1. "ram4serrcnt,RAM4 Single Error Count"
newline
hexmask.long.byte 0x4 18.--23. 1. "ram3serrcnt,RAM3 Single Error Count"
newline
hexmask.long.byte 0x4 12.--17. 1. "ram2serrcnt,RAM2 Single Error Count"
newline
hexmask.long.byte 0x4 6.--11. 1. "ram1serrcnt,RAM1 Single Error Count"
newline
hexmask.long.byte 0x4 0.--5. 1. "ram0serrcnt,RAM0 Single Error Count"
line.long 0x8 "BRMERRCNT,RAM Multiple Error Count. 6 bit count for each od 5 RAMS"
rbitfld.long 0x8 30.--31. "Reserved_1,Reserved_1" "0,1,2,3"
newline
hexmask.long.byte 0x8 24.--29. 1. "ram4merrcnt,RAM4 Multiple Error Count"
newline
hexmask.long.byte 0x8 18.--23. 1. "ram3merrcnt,RAM3 Multiple Error Count"
newline
hexmask.long.byte 0x8 12.--17. 1. "ram2merrcnt,RAM2 Multiple Error Count"
newline
hexmask.long.byte 0x8 6.--11. 1. "ram1merrcnt,RAM1 Multiple Error Count"
newline
hexmask.long.byte 0x8 0.--5. 1. "ram0merrcnt,RAM0 Multiple Error Count"
line.long 0xC "BRAMECCERR,RAM ECC Error Register"
hexmask.long.tbyte 0xC 12.--31. 1. "reserved_31_12,Reserved"
newline
eventfld.long 0xC 11. "ramserr,RAM Single Error" "0,1"
newline
eventfld.long 0xC 10. "rammerr,RAM Multiple Error" "0,1"
newline
hexmask.long.byte 0xC 5.--9. 1. "ramserrvec,RAM0 Single Error Vector"
newline
hexmask.long.byte 0xC 0.--4. 1. "rammerrvec,RAM Multiple Error Vector"
line.long 0x10 "BRERRCTL,RAM ERROR CONTROL REGISTER"
hexmask.long 0x10 2.--31. 1. "Reserved_1,Reserved"
newline
bitfld.long 0x10 1. "rserrclr,RAM Single Error Clear" "0,1"
newline
bitfld.long 0x10 0. "rmerrclr,RAM Multiple Error Clear" "0,1"
rgroup.long 0xD860++0x13
line.long 0x0 "BRAM0ADDRERR,Address of RAM0 which had uncorrectable error"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved"
newline
hexmask.long.word 0x0 0.--15. 1. "ram0errloc,RAM0 Address Error Location"
line.long 0x4 "BRAM1ADDRERR,RAM1 Address Error Register"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved"
newline
hexmask.long.word 0x4 0.--15. 1. "ram1errloc,RAM1 address error location"
line.long 0x8 "BRAM2ADDRERR,RAM2 Address Error Register"
hexmask.long.word 0x8 16.--31. 1. "Reserved_1,Reserved"
newline
hexmask.long.word 0x8 0.--15. 1. "ram2errloc,RAM2 address error location"
line.long 0xC "BRAM3ADDRERR,RAM3 Address Error Register"
hexmask.long.word 0xC 16.--31. 1. "Reserved_1,Reserved"
newline
hexmask.long.word 0xC 0.--15. 1. "ram3errloc,RAM3 address error location"
line.long 0x10 "BRAM4ADDRERR,RAM4 Address Error Register"
hexmask.long.word 0x10 16.--31. 1. "Reserved_1,Reserved"
newline
hexmask.long.word 0x10 0.--15. 1. "ram4errloc,RAM4 address error location"
group.long 0xD900++0xF
line.long 0x0 "BLOOPBCKCTRL,Loopback Control Register"
hexmask.long.tbyte 0x0 11.--31. 1. "reserved_31_11,Reserved"
newline
bitfld.long 0x0 8.--10. "reserved_10_8,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x0 4.--7. 1. "loopback_prtnum,Loopback Port Number"
newline
bitfld.long 0x0 2.--3. "loopback_level,Loopback Level" "0: SSP PIPE,1: SSP PHY,2: Reserved,3: Reserved"
newline
bitfld.long 0x0 1. "loopback_mode,Loopback Mode" "0: SW loopback Mode,1: BIST HW Loopback Mode"
newline
bitfld.long 0x0 0. "loopback_mode_en,Enable Loopback Mode" "0,1"
line.long 0x4 "BLOOPBCKTFERSZ,Loopback Transfer Size Register"
hexmask.long.byte 0x4 24.--31. 1. "reserved_31_24,Reserved"
newline
hexmask.long.tbyte 0x4 0.--23. 1. "loopback_xfer_sz,Loopback Transfer Size"
line.long 0x8 "BBISTDATAPATSEED,BIST Data Pattern Seed Register"
hexmask.long 0x8 0.--31. 1. "BIST_pattern_seed,Data is repeated or inverted or incremented or used as seed for LSFR"
line.long 0xC "BBISTCTRL,BIST Control Register"
bitfld.long 0xC 31. "start_BIST_test,Start BIST Test" "0: Stop Test,1: Start Test"
newline
bitfld.long 0xC 30. "BIST_test_type,BIST Test Type" "0: BIST Transfer loopback test,1: BIST Register/RAM test"
newline
bitfld.long 0xC 29. "fail,fail" "0,1"
newline
bitfld.long 0xC 27.--28. "reserved_28_27,Reserved" "0,1,2,3"
newline
bitfld.long 0xC 24.--26. "BIST_pattern,BIST Pattern" "0: Use same pattern,1: Alternate Invert,2: Increment Pattern,3: LSFR,4: Shift right,?,?,?"
newline
hexmask.long.tbyte 0xC 0.--23. 1. "BIST_iteration_cnt,BIST Iteration Count"
rgroup.long 0xD910++0x2F
line.long 0x0 "BBISTXFERSTS0,BIST Transfer Status Register 0"
hexmask.long.byte 0x0 24.--31. 1. "reserved_31_24,Reserved"
newline
hexmask.long.tbyte 0x0 0.--23. 1. "bist_pending_trans_size,BIST Pending Transfer Size"
line.long 0x4 "BBISTXFERSTS1,BIST Transfer Status Register 1"
hexmask.long.byte 0x4 24.--31. 1. "reserved_31_24,Reserved"
newline
hexmask.long.tbyte 0x4 0.--23. 1. "failed_pending_trans_size,Failed Pending Transfer Size"
line.long 0x8 "BBISTXFERSTS2,BIST Transfer Status Register 2"
hexmask.long.byte 0x8 24.--31. 1. "reserved_31_24,Reserved"
newline
hexmask.long.tbyte 0x8 0.--23. 1. "failed_iteration,Failed Iteration Count"
line.long 0xC "BBISTXFERSTS3,BIST Transfer Status Register 3"
hexmask.long 0xC 4.--31. 1. "reserved_31_4,Reserved"
newline
hexmask.long.byte 0xC 0.--3. 1. "loopback_statemachine,Loopback state machine"
line.long 0x10 "BBISTEXPDATASTS0,BIST Expected Data Status Register 0"
hexmask.long 0x10 0.--31. 1. "exp_data,Expected Data-0"
line.long 0x14 "BBISTEXPDATASTS1,BIST Expected Data Status Register 1"
hexmask.long 0x14 0.--31. 1. "exp_data,Expected Data-1"
line.long 0x18 "BBISTEXPDATASTS2,BIST Expected Data Status Register 2"
hexmask.long 0x18 0.--31. 1. "exp_data,Expected Data-2"
line.long 0x1C "BBISTEXPDATASTS3,BIST Expected Data Status Register 3"
hexmask.long 0x1C 0.--31. 1. "exp_data,Expected Data-3"
line.long 0x20 "BBISTRCVDDATASTS0,BIST Received Data Status Register 0"
hexmask.long 0x20 0.--31. 1. "received_data,Received Data-0"
line.long 0x24 "BBISTRCVDDATASTS1,BIST Received Data Status Register 1"
hexmask.long 0x24 0.--31. 1. "received_data,Received Data-1"
line.long 0x28 "BBISTRCVDDATASTS2,BIST Received Data Status Register 2"
hexmask.long 0x28 0.--31. 1. "received_data,Received Data-2"
line.long 0x2C "BBISTRCVDDATASTS3,BIST Received Data Status Register 3"
hexmask.long 0x2C 0.--31. 1. "received_data,Received Data-3"
rgroup.long 0xDA00++0x3
line.long 0x0 "rsvd_reg,Reserved Register"
hexmask.long 0x0 0.--31. 1. "rsvd_field,Reserved Register"
tree.end
tree "USB_OTG (USB 2.0 OTG Controller)"
base ad:0x10B00000
group.long 0x0++0x1B
line.long 0x0 "GOTGCTL,OTG Control and Status Register"
hexmask.long.byte 0x0 28.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x0 22.--27. 1. "Reserved_19,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x0 21. "CurMod,Mode: Host and Device" "0: Device mode,1: Host mode"
newline
bitfld.long 0x0 20. "OTGVer,OTG Version (OTGVer)" "0: OTG Version 1,1: OTG Version 2"
newline
rbitfld.long 0x0 19. "BSesVld,Mode: Device only" "0: B-session is not valid,1: B-session is valid"
newline
rbitfld.long 0x0 18. "ASesVld,Mode: Host only" "0: A-session is not valid,1: A-session is valid"
newline
rbitfld.long 0x0 17. "DbncTime,Mode: Host only" "0: Long debounce time,1: Short debounce time"
newline
rbitfld.long 0x0 16. "ConIDSts,Mode: Host and Device" "0: The DWC_otg core is in A-Device mode,1: The DWC_otg core is in B-Device mode"
newline
rbitfld.long 0x0 13.--15. "Reserved_13,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12. "EHEn,Mode: SRP Capable Host" "0: Disable Embedded Host Mode,1: Enable Embedded Host Mode"
newline
bitfld.long 0x0 11. "DevHNPEn,Mode: Device only" "0: HNP is not enabled in the application,1: HNP is enabled in the application"
newline
bitfld.long 0x0 10. "HstSetHNPEn,Mode: Host only" "0: Host Set HNP is not enabled,1: Host Set HNP is enabled"
newline
bitfld.long 0x0 9. "HNPReq,Mode: Device only" "0: No HNP request,1: HNP request"
newline
rbitfld.long 0x0 8. "HstNegScs,Mode: Device only" "0: Host negotiation failure,1: Host negotiation success"
newline
bitfld.long 0x0 7. "BvalidOvVal,B-Peripheral Session Valid OverrideValue (BvalidOvVal)" "0: Bvalid value is 1'b0 when GOTGCTL,1: Bvalid value is 1'b1 when GOTGCTL"
newline
bitfld.long 0x0 6. "BvalidOvEn,B-Peripheral Session Valid Override Enable (BvalidOvEn)" "0: Override is disabled and bvalid signal from the..,1: Internally Bvalid received from the PHY is.."
newline
bitfld.long 0x0 5. "AvalidOvVal,A-Peripheral Session Valid OverrideValue (AvalidOvVal)" "0: Avalid value is 1'b0 when GOTGCTL,1: Avalid value is 1'b1 when GOTGCTL"
newline
bitfld.long 0x0 4. "AvalidOvEn,A-Peripheral Session Valid Override Enable (AvalidOvEn)" "0: Override is disabled and avalid signal from the..,1: Internally Avalid received from the PHY is.."
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bitfld.long 0x0 3. "VbvalidOvVal,VBUS Valid OverrideValue (VbvalidOvVal)" "0: vbusvalid value is 1'b0 when GOTGCTL,1: vbusvalid value is 1'b1 when GOTGCTL"
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bitfld.long 0x0 2. "VbvalidOvEn,VBUS Valid Override Enable (VbvalidOvEn)" "0: Override is disabled and bvalid signal from the..,1: Internally Bvalid received from the PHY is.."
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bitfld.long 0x0 1. "SesReq,Mode: Device only" "0: No session request,1: Session request"
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rbitfld.long 0x0 0. "SesReqScs,Mode: Device only" "0: Session request failure,1: Session request success"
line.long 0x4 "GOTGINT,OTG Interrupt Register"
hexmask.long.word 0x4 21.--31. 1. "RESERVED,RESERVED"
newline
rbitfld.long 0x4 20. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
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eventfld.long 0x4 19. "DbnceDone,Mode: Host only" "0,1"
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eventfld.long 0x4 18. "ADevTOUTChg,Mode:Host and Device" "0,1"
newline
eventfld.long 0x4 17. "HstNegDet,Mode:Host and Device" "0,1"
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hexmask.long.byte 0x4 10.--16. 1. "RESERVED1,RESERVED"
newline
eventfld.long 0x4 9. "HstNegSucStsChng,Mode:Host and Device" "0,1"
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eventfld.long 0x4 8. "SesReqSucStsChng,Mode:Host and Device" "0,1"
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hexmask.long.byte 0x4 3.--7. 1. "RESERVED2,RESERVED"
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eventfld.long 0x4 2. "SesEndDet,Mode:Host and Device" "0,1"
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rbitfld.long 0x4 0.--1. "RESERVED3,RESERVED" "0,1,2,3"
line.long 0x8 "GAHBCFG,AHB Configuration Register"
hexmask.long.byte 0x8 25.--31. 1. "RESERVED1,RESERVED"
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bitfld.long 0x8 24. "InvDescEndianess,Invert Descriptor Endianess (InvDescEndianess)" "0: Descriptor Endianness is same as AHB Master..,1: Descriptor Endianness is Little Endian if AHB.."
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bitfld.long 0x8 23. "AHBSingle,AHB Single Support (AHBSingle)" "0: The remaining data in the transfer is sent using..,1: The remaining data in the transfer is sent using.."
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bitfld.long 0x8 22. "NotiAllDmaWrit,Notify All Dma Write Transactions (NotiAllDmaWrit)" "0,1"
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bitfld.long 0x8 21. "RemMemSupp,Remote Memory Support (RemMemSupp)" "0,1"
newline
hexmask.long.word 0x8 9.--20. 1. "Reserved_6,Reserved bitfield added by Magillem"
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bitfld.long 0x8 8. "PTxFEmpLvl,Mode:Host only" "0: GINTSTS,1: GINTSTS"
newline
bitfld.long 0x8 7. "NPTxFEmpLvl,Mode:Host and device" "0: DIEPINTn,1: DIEPINTn"
newline
rbitfld.long 0x8 6. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x8 5. "DMAEn,Mode:Host and device" "0: Core operates in Slave mode,1: Core operates in a DMA mode"
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hexmask.long.byte 0x8 1.--4. 1. "HBstLen,Mode:Host and device"
newline
bitfld.long 0x8 0. "GlblIntrMsk,Mode:Host and device" "0: Mask the interrupt assertion to the application,1: Unmask the interrupt assertion to the application"
line.long 0xC "GUSBCFG,USB Configuration Register"
bitfld.long 0xC 31. "CorruptTxPkt,Mode:Host and device" "0,1"
newline
bitfld.long 0xC 30. "ForceDevMode,Mode:Host and device" "0: Normal Mode,1: Force Device Mode"
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bitfld.long 0xC 29. "ForceHstMode,Mode:Host and device" "0: Normal Mode,1: Force Host Mode"
newline
bitfld.long 0xC 28. "TxEndDelay,Mode: Device only" "0: Normal Mode,1: Tx End delay"
newline
rbitfld.long 0xC 27. "Reserved_19,Reserved bitfield added by Magillem" "0,1"
newline
rbitfld.long 0xC 26. "IC_USBCap,IC_USB-Capable (IC_USBCap)" "0: IC_USB PHY Interface is not selected,1: IC_USB PHY Interface is selected"
newline
bitfld.long 0xC 25. "ULPI,Mode:Host only" "0: Enables the interface protect circuit,1: Disables the interface protect circuit"
newline
bitfld.long 0xC 24. "Indicator,Mode:Host only" "0: Complement Output signal is qualified with the..,1: Complement Output signal is not qualified with the"
newline
bitfld.long 0xC 23. "Complement,Mode:Host only" "0: PHY does not invert ExternalVbusIndicator signal,1: PHY does invert ExternalVbusIndicator signal"
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bitfld.long 0xC 22. "TermSelDLPulse,Mode:Device only" "0: Data line pulsing using utmi_txvalid,1: Data line pulsing using utmi_termsel"
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bitfld.long 0xC 21. "ULPIExtVbusIndicator,Mode:Host only" "0: PHY uses internal VBUS valid comparator,1: PHY uses external VBUS valid comparator"
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bitfld.long 0xC 20. "ULPIExtVbusDrv,Mode:Host only" "0: PHY drives VBUS using internal charge pump,1: PHY drives VBUS using external supply"
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bitfld.long 0xC 19. "ULPIClkSusM,Mode:Host and Device" "0: PHY powers down internal clock during suspend,1: PHY does not power down internal clock"
newline
bitfld.long 0xC 18. "ULPIAutoRes,Mode:Host and Device" "0: PHY does not use AutoResume feature,1: PHY uses AutoResume feature"
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rbitfld.long 0xC 15.--17. "Reserved_10,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0xC 14. "RESERVED,RESERVED" "0,1"
newline
hexmask.long.byte 0xC 10.--13. 1. "USBTrdTim,Mode: Device only"
newline
bitfld.long 0xC 9. "HNPCap,Mode:Host and Device" "0: HNP capability is not enabled,1: HNP capability is enabled"
newline
bitfld.long 0xC 8. "SRPCap,Mode:Host and Device" "0: SRP capability is not enabled,1: SRP capability is enabled"
newline
bitfld.long 0xC 7. "DDRSel,Mode:Host and Device" "0: Single Data Rate ULPI Interface,1: Double Data Rate ULPI Interface"
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rbitfld.long 0xC 6. "PHYSel,Mode:Host and Device" "0: USB 2,1: USB 1"
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rbitfld.long 0xC 5. "FSIntf,Mode:Host and Device" "0: 6-pin unidirectional full-speed serial interface,1: 3-pin bidirectional full-speed serial interface"
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rbitfld.long 0xC 4. "ULPI_UTMI_Sel,Mode:Host and Device" "0: UTMI+ Interface,1: ULPI Interface"
newline
rbitfld.long 0xC 3. "PHYIf,Mode:Host and Device" "0: 8 bits,1: 16 bits"
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bitfld.long 0xC 0.--2. "TOutCal,Mode:Host and Device" "0,1,2,3,4,5,6,7"
line.long 0x10 "GRSTCTL,Reset Register"
rbitfld.long 0x10 31. "AHBIdle,Mode:Host and Device" "0,1"
newline
rbitfld.long 0x10 30. "DMAReq,Mode:Host and Device" "0,1"
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hexmask.long.tbyte 0x10 11.--29. 1. "RESERVED,RESERVED"
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hexmask.long.byte 0x10 6.--10. 1. "TxFNum,Mode:Host and Device"
newline
bitfld.long 0x10 5. "TxFFlsh,Mode:Host and Device" "0,1"
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bitfld.long 0x10 4. "RxFFlsh,Mode:Host and Device" "0,1"
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rbitfld.long 0x10 3. "Reserved_3,Reserved bitfield added by Magillem" "0,1"
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bitfld.long 0x10 2. "FrmCntrRst,Mode:Host only" "0,1"
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bitfld.long 0x10 1. "PIUFSSftRst,Mode:Host and Device" "0,1"
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bitfld.long 0x10 0. "CSftRst,Mode:Host and Device" "0,1"
line.long 0x14 "GINTSTS,Interrupt Register"
eventfld.long 0x14 31. "WkUpInt,Mode:Host and Device" "0,1"
newline
eventfld.long 0x14 30. "SessReqInt,Mode:Host and Device" "0,1"
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eventfld.long 0x14 29. "DisconnInt,Mode:Host only" "0,1"
newline
eventfld.long 0x14 28. "ConIDStsChng,Mode:Host and Device" "0,1"
newline
rbitfld.long 0x14 27. "Reserved_24,Reserved bitfield added by Magillem" "0,1"
newline
rbitfld.long 0x14 26. "PTxFEmp,Mode:Host only" "0,1"
newline
rbitfld.long 0x14 25. "HChInt,Mode:Host only" "0,1"
newline
rbitfld.long 0x14 24. "PrtInt,Mode:Host only" "0,1"
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eventfld.long 0x14 23. "ResetDet,Mode: Device only" "0,1"
newline
eventfld.long 0x14 22. "FetSusp,Mode: Device only" "0,1"
newline
eventfld.long 0x14 21. "incomplP,Incomplete Periodic Transfer (incomplP)" "0,1"
newline
eventfld.long 0x14 20. "incompISOIN,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 19. "OEPInt,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 18. "IEPInt,Mode: Device only" "0,1"
newline
eventfld.long 0x14 17. "EPMis,Mode: Device only" "0,1"
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rbitfld.long 0x14 16. "Reserved_14,Reserved bitfield added by Magillem" "0,1"
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eventfld.long 0x14 15. "EOPF,Mode: Device only" "0,1"
newline
eventfld.long 0x14 14. "ISOOutDrop,Mode: Device only" "0,1"
newline
eventfld.long 0x14 13. "EnumDone,Mode: Device only" "0,1"
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eventfld.long 0x14 12. "USBRst,Mode: Device only" "0,1"
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eventfld.long 0x14 11. "USBSusp,Mode: Device only" "0,1"
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eventfld.long 0x14 10. "ErlySusp,Mode: Device only" "0,1"
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rbitfld.long 0x14 8.--9. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3"
newline
rbitfld.long 0x14 7. "GOUTNakEff,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 6. "GINNakEff,Mode: Device only" "0,1"
newline
rbitfld.long 0x14 5. "NPTxFEmp,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x14 4. "RxFLvl,Mode: Host and Device" "0,1"
newline
eventfld.long 0x14 3. "Sof,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x14 2. "OTGInt,Mode: Host and Device" "0,1"
newline
eventfld.long 0x14 1. "ModeMis,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x14 0. "CurMod,Mode: Host and Device" "0: Device mode,1: Host mode"
line.long 0x18 "GINTMSK,Interrupt Mask Register"
bitfld.long 0x18 31. "WkUpIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 30. "SessReqIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 29. "DisconnIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 28. "ConIDStsChngMsk,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x18 27. "Reserved_24,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x18 26. "PTxFEmpMsk,Mode: Host only" "0,1"
newline
bitfld.long 0x18 25. "HChIntMsk,Mode: Host only" "0,1"
newline
bitfld.long 0x18 24. "PrtIntMsk,Mode: Host only" "0,1"
newline
bitfld.long 0x18 23. "ResetDetMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 22. "FetSuspMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 21. "incomplPMsK,Mode: Host only" "0,1"
newline
bitfld.long 0x18 20. "incompISOINMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 19. "OEPIntMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 18. "IEPIntMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 17. "EPMisMsk,Mode: Device only" "0,1"
newline
rbitfld.long 0x18 16. "Reserved_14,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x18 15. "EOPFMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 14. "ISOOutDropMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 13. "EnumDoneMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 12. "USBRstMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 11. "USBSuspMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 10. "ErlySuspMsk,Mode: Device only" "0,1"
newline
rbitfld.long 0x18 8.--9. "Reserved_8,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x18 7. "GOUTNakEffMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 6. "GINNakEffMsk,Mode: Device only" "0,1"
newline
bitfld.long 0x18 5. "NPTxFEmpMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 4. "RxFLvlMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 3. "SofMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 2. "OTGIntMsk,Mode: Host and Device" "0,1"
newline
bitfld.long 0x18 1. "ModeMisMsk,Mode: Host and Device" "0,1"
newline
rbitfld.long 0x18 0. "RESERVED,RESERVED" "0,1"
rgroup.long 0x1C++0x7
line.long 0x0 "GRXSTSR,Receive Status Debug Read Register"
bitfld.long 0x0 31. "Reserved_6,Reserved bitfield added by Magillem" "0,1"
newline
hexmask.long.byte 0x0 25.--30. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x0 21.--24. 1. "FN,Mode: Device only"
newline
hexmask.long.byte 0x0 17.--20. 1. "PktSts,Mode: Host only"
newline
bitfld.long 0x0 15.--16. "DPID,Mode: Host only" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x0 4.--14. 1. "BCnt,Mode: Host only"
newline
hexmask.long.byte 0x0 0.--3. 1. "ChNum,Mode: Host only"
line.long 0x4 "GRXSTSP,Receive Status Read /Pop Register"
bitfld.long 0x4 31. "Reserved_6,Reserved bitfield added by Magillem" "0,1"
newline
hexmask.long.byte 0x4 25.--30. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x4 21.--24. 1. "FN,Mode: Device only"
newline
hexmask.long.byte 0x4 17.--20. 1. "PktSts,Mode: Host only"
newline
bitfld.long 0x4 15.--16. "DPID,Mode: Host only" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x4 4.--14. 1. "BCnt,Mode: Host only"
newline
hexmask.long.byte 0x4 0.--3. 1. "ChNum,Mode: Host only"
group.long 0x24++0x7
line.long 0x0 "GRXFSIZ,Receive FIFO Size Register"
hexmask.long.byte 0x0 28.--31. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 14.--27. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--13. 1. "RxFDep,Mode: Host and Device"
line.long 0x4 "GNPTXFSIZ,Non-periodic Transmit FIFO Size Register"
hexmask.long.word 0x4 16.--31. 1. "NPTXFDep,Mode: Host only"
newline
hexmask.long.word 0x4 0.--15. 1. "NPTXFStAddr,Mode: Host only"
rgroup.long 0x2C++0x3
line.long 0x0 "GNPTXSTS,Non-periodic Transmit FIFO/Queue Status Register"
bitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
hexmask.long.byte 0x0 24.--30. 1. "NPTxQTop,Top of the Non-periodic Transmit Request Queue (NPTxQTop)"
newline
hexmask.long.byte 0x0 16.--23. 1. "NPTxQSpcAvail,Non-periodic Transmit Request Queue Space Available"
newline
hexmask.long.word 0x0 0.--15. 1. "NPTxFSpcAvail,Non-periodic TxFIFO Space Avail (NPTxFSpcAvail)"
group.long 0x34++0x7
line.long 0x0 "GPVNDCTL,PHY Vendor Control Register"
bitfld.long 0x0 31. "DisUlpiDrvr,Disable ULPI Drivers (DisUlpiDrvr)" "0,1"
newline
rbitfld.long 0x0 28.--30. "RESERVED,RESERVED" "0,1,2,3,4,5,6,7"
newline
eventfld.long 0x0 27. "VStsDone,VStatus Done (VStsDone)" "0,1"
newline
rbitfld.long 0x0 26. "VStsBsy,VStatus Busy (VStsBsy)" "0,1"
newline
bitfld.long 0x0 25. "NewRegReq,New Register Request (NewRegReq)" "0,1"
newline
rbitfld.long 0x0 23.--24. "RESERVED1,RESERVED" "0,1,2,3"
newline
bitfld.long 0x0 22. "RegWr,Register Write (RegWr)" "0,1"
newline
hexmask.long.byte 0x0 16.--21. 1. "RegAddr,Register Address (RegAddr)"
newline
hexmask.long.byte 0x0 8.--15. 1. "VCtrl,UTMI+ Vendor Control Register Address (VCtrl)"
newline
hexmask.long.byte 0x0 0.--7. 1. "RegData,Register Data (RegData)"
line.long 0x4 "GGPIO,General Purpose Input/Output Register"
hexmask.long.word 0x4 16.--31. 1. "GPO,General Purpose Output (GPO)"
newline
hexmask.long.word 0x4 0.--15. 1. "GPI,General Purpose Input (GPI)"
rgroup.long 0x3C++0x17
line.long 0x0 "GUID,User ID Register"
hexmask.long 0x0 0.--31. 1. "GUID,User ID (UserID)"
line.long 0x4 "GSNPSID,Synopsys ID Register"
hexmask.long 0x4 0.--31. 1. "SynopsysID,Release number of the DWC_otg core being used currently"
line.long 0x8 "GHWCFG1,User HW Config1 Register"
hexmask.long 0x8 0.--31. 1. "EpDir,This 32-bit field uses two bits per"
line.long 0xC "GHWCFG2,User HW Config2 Register"
bitfld.long 0xC 31. "Reserved_14,Reserved bitfield added by Magillem" "0,1"
newline
hexmask.long.byte 0xC 26.--30. 1. "TknQDepth,Device Mode IN Token Sequence Learning Queue Depth"
newline
bitfld.long 0xC 24.--25. "PTxQDepth,Host Mode Periodic Request Queue Depth (PTxQDepth)" "0: 2,1: 4,2: 8,3: 16"
newline
bitfld.long 0xC 22.--23. "NPTxQDepth,Non-periodic Request Queue Depth (NPTxQDepth)" "0: 2,1: 4,2: 8,?"
newline
bitfld.long 0xC 21. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0xC 20. "MultiProcIntrpt,Multi Processor Interrupt Enabled (MultiProcIntrpt)" "0: No,1: Yes"
newline
bitfld.long 0xC 19. "DynFifoSizing,Dynamic FIFO Sizing Enabled (DynFifoSizing)" "0: No,1: Yes"
newline
bitfld.long 0xC 18. "PerioSupport,Periodic OUT Channels Supported in Host Mode (PerioSupport)" "0: No,1: Yes"
newline
hexmask.long.byte 0xC 14.--17. 1. "NumHstChnl,Number of Host Channels (NumHstChnl)"
newline
hexmask.long.byte 0xC 10.--13. 1. "NumDevEps,Number of Device Endpoints (NumDevEps)"
newline
bitfld.long 0xC 8.--9. "FSPhyType,Full-Speed PHY Interface Type (FSPhyType)" "0: Full-speed interface not supported,1: Dedicated full-speed interface,2: FS pins shared with UTMI+ pins,3: FS pins shared with ULPI pins"
newline
bitfld.long 0xC 6.--7. "HSPhyType,High-Speed PHY Interface Type (HSPhyType)" "0: High-Speed interface not supported,1: UTMI+,2: ULPI,3: UTMI+ and ULPI"
newline
bitfld.long 0xC 5. "SingPnt,Point-to-Point (SingPnt)" "0: Multi-point application,1: Single-point application"
newline
bitfld.long 0xC 3.--4. "OtgArch,Architecture (OtgArch)" "0: Slave-Only,1: External DMA,2: Internal DMA,?"
newline
bitfld.long 0xC 0.--2. "OtgMode,Mode of Operation (OtgMode)" "0: HNP- and SRP-Capable OTG,1: SRP-Capable OTG,2: Non-HNP and Non-SRP Capable OTG,3: SRP-Capable Device,4: Non-OTG Device,5: SRP-Capable Host,6: Non-OTG Host,?"
line.long 0x10 "GHWCFG3,User HW Config3 Register"
hexmask.long.word 0x10 16.--31. 1. "DfifoDepth,DFIFO Depth (DfifoDepth - EP_LOC_CNT)"
newline
bitfld.long 0x10 15. "LPMMode,LPM mode specified for Mode of Operation." "0,1"
newline
bitfld.long 0x10 14. "BCSupport,This bit indicates the HS OTG controller support for Battery Charger." "0,1"
newline
bitfld.long 0x10 13. "HSICMode,HSIC mode specified for Mode of Operation" "0: Non-HSIC-capable,1: HSIC-capable with shared UTMI PHY interface"
newline
bitfld.long 0x10 12. "ADPSupport,This bit indicates whether ADP logic is present within or external to the HS OTG" "0: No ADP logic present with DWC_otg controller,1: ADP logic is present along with DWC_otg controller"
newline
bitfld.long 0x10 11. "RstType,Reset Style For Clocked always Blocks in RTL (RstType)" "0: Asynchronous reset is used in the core,1: Synchronous reset is used in the core"
newline
bitfld.long 0x10 10. "OptFeature,Optional Features Removed (OptFeature)" "0: No,1: Yes"
newline
bitfld.long 0x10 9. "VndctlSupt,Vendor Control Interface Support (VndctlSupt)" "0: Vendor Control Interface is not available on the..,1: Vendor Control Interface is available"
newline
bitfld.long 0x10 8. "I2CIntSel,I2C Selection (I2CIntSel)" "0: I2C Interface is not available on the core,1: I2C Interface is available on the core"
newline
bitfld.long 0x10 7. "OtgEn,OTG Function Enabled (OtgEn)" "0: Not OTG capable,1: OTG Capable"
newline
bitfld.long 0x10 4.--6. "PktSizeWidth,Width of Packet Size Counters (PktSizeWidth)" "0: 4 bits,1: 5 bits,2: 6 bits,3: 7 bits,4: 8 bits,5: 9 bits,6: 10 bits,?"
newline
hexmask.long.byte 0x10 0.--3. 1. "XferSizeWidth,Width of Transfer Size Counters (XferSizeWidth)"
line.long 0x14 "GHWCFG4,User HW Config4 Register"
bitfld.long 0x14 31. "DescDMA,Scatter/Gather DMA configuration" "0: Non Dynamic configuration,1: Dynamic configuration"
newline
bitfld.long 0x14 30. "DescDMAEnabled,Scatter/Gather DMA configuration" "0: Non-Scatter/Gather DMA configuration,1: Scatter/Gather DMA configuration"
newline
hexmask.long.byte 0x14 26.--29. 1. "INEps,Number of Device Mode IN Endpoints Including Control"
newline
bitfld.long 0x14 25. "DedFifoMode,Enable Dedicated Transmit FIFO For device IN Endpoints" "0: Dedicated Transmit FIFO Operation not enabled,1: Dedicated Transmit FIFO Operation enabled"
newline
bitfld.long 0x14 24. "SessEndFltr,session_end Filter Enabled (SessEndFltr)" "0: No filter,1: Filter"
newline
bitfld.long 0x14 23. "BValidFltr,b_valid Filter Enabled (BValidFltr)" "0: No filter,1: Filter"
newline
bitfld.long 0x14 22. "AValidFltr,a_valid Filter Enabled (AValidFltr)" "0: No filter,1: Filter"
newline
bitfld.long 0x14 21. "VBusValidFltr,VBUS Valid Filter Enabled (VBusValidFltr)" "0: No filter,1: Filter"
newline
bitfld.long 0x14 20. "IddgFltr,IDDIG Filter Enable (IddgFltr)" "0: No filter,1: Filter"
newline
hexmask.long.byte 0x14 16.--19. 1. "NumCtlEps,Number of Device Mode Control Endpoints in Addition to"
newline
bitfld.long 0x14 14.--15. "PhyDataWidth,UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width" "0: 8 bits,1: 16 bits,2: 8/16 bits,?"
newline
hexmask.long.byte 0x14 8.--13. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x14 7. "ExtendedHibernation,Enable Hibernation" "0: Extended Hibernation feature not enabled,1: Extended Hibernation feature enabled"
newline
bitfld.long 0x14 6. "Hibernation,Enable Hibernation (Hibernation)" "0: Hibernation feature not enabled,1: Hibernation feature enabled"
newline
bitfld.long 0x14 5. "AhbFreq,Minimum AHB Frequency Less Than 60 MHz (AhbFreq)" "0: No,1: Yes"
newline
bitfld.long 0x14 4. "PartialPwrDn,Enable Partial Power Down (PartialPwrDn)" "0: Partial Power Down Not Enabled,1: Partial Power Down Enabled"
newline
hexmask.long.byte 0x14 0.--3. 1. "NumDevPerioEps,Number of Device Mode Periodic IN Endpoints"
group.long 0x5C++0x3
line.long 0x0 "GDFIFOCFG,Global DFIFO Configuration Register"
hexmask.long.word 0x0 16.--31. 1. "EPInfoBaseAddr,EPInfoBaseAddr"
newline
hexmask.long.word 0x0 0.--15. 1. "GDFIFOCfg,GDFIFOCfg"
group.long 0x100++0x3F
line.long 0x0 "HPTXFSIZ,Host Periodic Transmit FIFO Size Register"
rbitfld.long 0x0 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x0 16.--29. 1. "PTxFSize,Host Periodic TxFIFO Depth (PTxFSize)"
newline
rbitfld.long 0x0 15. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
newline
hexmask.long.word 0x0 0.--14. 1. "PTxFStAddr,Host Periodic TxFIFO Start Address (PTxFStAddr)"
line.long 0x4 "DIEPTXF1,Device IN Endpoint Transmit FIFO Size Register 1"
rbitfld.long 0x4 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x4 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
rbitfld.long 0x4 15. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
newline
hexmask.long.word 0x4 0.--14. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x8 "DIEPTXF2,Device IN Endpoint Transmit FIFO Size Register 2"
rbitfld.long 0x8 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x8 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
rbitfld.long 0x8 15. "Reserved_1,Reserved bitfield added by Magillem" "0,1"
newline
hexmask.long.word 0x8 0.--14. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0xC "DIEPTXF3,Device IN Endpoint Transmit FIFO Size Register 3"
rbitfld.long 0xC 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0xC 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0xC 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x10 "DIEPTXF4,Device IN Endpoint Transmit FIFO Size Register 4"
rbitfld.long 0x10 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x10 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x10 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x14 "DIEPTXF5,Device IN Endpoint Transmit FIFO Size Register 5"
rbitfld.long 0x14 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x14 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x14 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x18 "DIEPTXF6,Device IN Endpoint Transmit FIFO Size Register 6"
rbitfld.long 0x18 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x18 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x18 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x1C "DIEPTXF7,Device IN Endpoint Transmit FIFO Size Register 7"
rbitfld.long 0x1C 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x1C 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x1C 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x20 "DIEPTXF8,Device IN Endpoint Transmit FIFO Size Register 8"
rbitfld.long 0x20 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x20 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x20 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x24 "DIEPTXF9,Device IN Endpoint Transmit FIFO Size Register 9"
rbitfld.long 0x24 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x24 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x24 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x28 "DIEPTXF10,Device IN Endpoint Transmit FIFO Size Register 10"
rbitfld.long 0x28 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x28 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x28 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x2C "DIEPTXF11,Device IN Endpoint Transmit FIFO Size Register 11"
rbitfld.long 0x2C 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x2C 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x2C 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x30 "DIEPTXF12,Device IN Endpoint Transmit FIFO Size Register 12"
rbitfld.long 0x30 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x30 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x30 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x34 "DIEPTXF13,Device IN Endpoint Transmit FIFO Size Register 13"
rbitfld.long 0x34 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x34 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x34 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x38 "DIEPTXF14,Device IN Endpoint Transmit FIFO Size Register 14"
rbitfld.long 0x38 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x38 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x38 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
line.long 0x3C "DIEPTXF15,Device IN Endpoint Transmit FIFO Size Register 15"
rbitfld.long 0x3C 30.--31. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
hexmask.long.word 0x3C 16.--29. 1. "INEPnTxFDep,IN Endpoint TxFIFO Depth (INEPnTxFDep)"
newline
hexmask.long.word 0x3C 0.--15. 1. "INEPnTxFStAddr,IN Endpoint FIFOn Transmit RAM Start Address"
group.long 0x400++0x7
line.long 0x0 "HCFG,Host Configuration Register"
bitfld.long 0x0 31. "ModeChTimEn,Mode Change Ready Timer Enable (ModeChTimEn)" "0: The Host core waits for either 200 PHY clock..,1: The Host core waits only for a linstate of SE0.."
newline
hexmask.long.byte 0x0 27.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x0 26. "PerSchedEna,Enable Periodic Scheduling (PerSchedEna):" "0,1"
newline
bitfld.long 0x0 24.--25. "FrListEn,Frame List Entries(FrListEn). The value in the register specifies the number" "0: 8 Entries,1: 16 Entries,2: 32 Entries,3: 63 Entries"
newline
bitfld.long 0x0 23. "DescDMA,Enable Scatter/gather DMA in Host mode (DescDMA)." "0: Buffered DMA mode,1: Scatter/Gather DMA mode"
newline
hexmask.long.byte 0x0 16.--22. 1. "RESERVED1,RESERVED"
newline
hexmask.long.byte 0x0 8.--15. 1. "ResValid,Resume Validation Period (ResValid)"
newline
bitfld.long 0x0 7. "Ena32KHzS,Enable 32 KHz Suspend mode (Ena32KHzS)" "0,1"
newline
hexmask.long.byte 0x0 3.--6. 1. "RESERVED2,RESERVED"
newline
bitfld.long 0x0 2. "FSLSSupp,FS- and LS-Only Support (FSLSSupp)" "0: HS/FS/LS,1: FS/LS-only"
newline
bitfld.long 0x0 0.--1. "FSLSPclkSel,FS/LS PHY Clock Select (FSLSPclkSel)" "0: Internal and external clocks have the same..,1: PHY clock is running at 48 MHz,2: Internal clock is the divided by eight version..,3: Reserved"
line.long 0x4 "HFIR,Host Frame Interval Register"
hexmask.long.word 0x4 17.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x4 16. "HFIRRldCtrl,Reload Control (HFIRRldCtrl)" "0: The HFIR cannot be reloaded dynamically,1: the HFIR can be dynamically reloaded during.."
newline
hexmask.long.word 0x4 0.--15. 1. "FrInt,Frame Interval (FrInt)"
rgroup.long 0x408++0x3
line.long 0x0 "HFNUM,Host Frame Number/Frame Time Remaining Register"
hexmask.long.word 0x0 16.--31. 1. "FrRem,Frame Time Remaining (FrRem)"
newline
hexmask.long.word 0x0 0.--15. 1. "FrNum,Frame Number (FrNum)"
rgroup.long 0x410++0x7
line.long 0x0 "HPTXSTS,Host Periodic Transmit FIFO/Queue Status Register"
hexmask.long.byte 0x0 24.--31. 1. "PTxQTop,Top of the Periodic Transmit Request Queue (PTxQTop)"
newline
hexmask.long.byte 0x0 16.--23. 1. "PTxQSpcAvail,Periodic Transmit Request Queue Space Available"
newline
hexmask.long.word 0x0 0.--15. 1. "PTxFSpcAvail,Periodic Transmit Data FIFO Space Available"
line.long 0x4 "HAINT,Host All Channels Interrupt Register"
hexmask.long.word 0x4 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x4 0.--15. 1. "HAINT,Channel Interrupt for channel no."
group.long 0x418++0x7
line.long 0x0 "HAINTMSK,Host All Channels Interrupt Mask Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--15. 1. "HAINTMsk,Channel Interrupt Msk for channel"
line.long 0x4 "HFLBAddr,Host Frame List Base Address Register"
hexmask.long 0x4 0.--31. 1. "HFLBAddr,The starting address of the Frame list."
group.long 0x440++0x3
line.long 0x0 "HPRT,Host Port Control and Status Register"
hexmask.long.word 0x0 19.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x0 17.--18. "PrtSpd,Port Speed (PrtSpd)" "0: High speed,1: Full speed,2: Low speed,3: Reserved"
newline
hexmask.long.byte 0x0 13.--16. 1. "PrtTstCtl,Port Test Control (PrtTstCtl)"
newline
bitfld.long 0x0 12. "PrtPwr,Port Power (PrtPwr)" "0: Power off,1: Power on"
newline
rbitfld.long 0x0 10.--11. "PrtLnSts,Port Line Status (PrtLnSts)" "0,1,2,3"
newline
rbitfld.long 0x0 9. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 8. "PrtRst,Port Reset (PrtRst)" "0: Port not in reset,1: Port in reset"
newline
bitfld.long 0x0 7. "PrtSusp,Port Suspend (PrtSusp)" "0: Port not in Suspend mode,1: Port in Suspend mode"
newline
bitfld.long 0x0 6. "PrtRes,Port Resume (PrtRes)" "0: No resume driven,1: Resume driven"
newline
eventfld.long 0x0 5. "PrtOvrCurrChng,Port Overcurrent Change (PrtOvrCurrChng)" "0,1"
newline
rbitfld.long 0x0 4. "PrtOvrCurrAct,Port Overcurrent Active (PrtOvrCurrAct)" "0: No overcurrent condition,1: Overcurrent condition"
newline
eventfld.long 0x0 3. "PrtEnChng,Port Enable/Disable Change (PrtEnChng)" "0,1"
newline
eventfld.long 0x0 2. "PrtEna,Port Enable (PrtEna)" "0: Port disabled,1: Port enabled"
newline
eventfld.long 0x0 1. "PrtConnDet,Port Connect Detected (PrtConnDet)" "0,1"
newline
rbitfld.long 0x0 0. "PrtConnSts,Port Connect Status (PrtConnSts)" "0: No device is attached to the port,1: A device is attached to the port"
group.long 0x500++0x17
line.long 0x0 "HCCHAR0,Host Channel 0 Characteristics Register"
bitfld.long 0x0 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x0 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x0 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x0 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x0 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x0 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x0 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x0 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x4 "HCSPLT0,Host Channel 0 Split Control Register"
bitfld.long 0x4 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x4 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x4 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x4 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x4 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x4 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0x8 "HCINT0,Host Channel 0 Interrupt Register"
hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x8 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0x8 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0x8 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x8 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0x8 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0x8 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0x8 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0x8 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0x8 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0x8 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0x8 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0x8 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x8 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0x8 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0xC "HCINTMSK0,Host Channel 0 Interrupt Mask Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0xC 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0xC 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0xC 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0xC 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0xC 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0xC 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0xC 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0xC 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0xC 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0xC 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0xC 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0xC 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0xC 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0xC 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x10 "HCTSIZ0,Host Channel 0 Transfer Size Register"
bitfld.long 0x10 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x10 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x10 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x10 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x14 "HCDMA0,Host Channel 0 DMA Address Register"
hexmask.long 0x14 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x51C++0x1B
line.long 0x0 "HCDMAB0,Host Channel 0 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR1,Host Channel 1 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT1,Host Channel 1 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT1,Host Channel 1 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK1,Host Channel 1 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ1,Host Channel 1 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA1,Host Channel 1 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x53C++0x1B
line.long 0x0 "HCDMAB1,Host Channel 1 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR2,Host Channel 2 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT2,Host Channel 2 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT2,Host Channel 2 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK2,Host Channel 2 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ2,Host Channel 2 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA2,Host Channel 2 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x55C++0x1B
line.long 0x0 "HCDMAB2,Host Channel 2 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR3,Host Channel 3 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT3,Host Channel 3 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT3,Host Channel 3 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK3,Host Channel 3 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ3,Host Channel 3 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA3,Host Channel 3 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x57C++0x1B
line.long 0x0 "HCDMAB3,Host Channel 3 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR4,Host Channel 4 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT4,Host Channel 4 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT4,Host Channel 4 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK4,Host Channel 4 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ4,Host Channel 4 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA4,Host Channel 4 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x59C++0x1B
line.long 0x0 "HCDMAB4,Host Channel 4 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR5,Host Channel 5 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
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bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
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rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
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bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
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hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
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hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT5,Host Channel 5 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
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hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
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bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
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bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
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hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
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hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT5,Host Channel 5 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
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eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
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eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
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eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
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eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
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eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
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eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
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eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
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eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
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eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
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eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
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eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
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eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
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eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
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eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK5,Host Channel 5 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
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rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
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bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
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bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
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bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
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bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
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bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
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bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
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bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
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bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
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bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
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bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ5,Host Channel 5 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
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bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
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hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
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hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA5,Host Channel 5 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x5BC++0x1B
line.long 0x0 "HCDMAB5,Host Channel 5 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR6,Host Channel 6 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
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bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
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bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
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hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
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bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
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bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
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bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
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rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
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bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
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hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
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hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT6,Host Channel 6 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
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hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
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bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
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bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
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hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
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hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT6,Host Channel 6 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
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eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
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eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
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eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
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eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
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eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
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eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
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eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
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eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
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eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
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eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
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eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
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eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
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eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
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eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK6,Host Channel 6 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
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bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
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rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
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bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
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bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
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bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
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bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
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bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
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bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
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bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
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bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
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bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
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bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ6,Host Channel 6 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
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bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
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hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
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hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA6,Host Channel 6 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x5DC++0x1B
line.long 0x0 "HCDMAB6,Host Channel 6 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR7,Host Channel 7 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
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bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
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bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
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hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
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bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
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bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
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hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT7,Host Channel 7 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT7,Host Channel 7 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
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eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
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eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
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eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK7,Host Channel 7 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ7,Host Channel 7 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA7,Host Channel 7 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x5FC++0x1B
line.long 0x0 "HCDMAB7,Host Channel 7 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR8,Host Channel 8 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT8,Host Channel 8 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT8,Host Channel 8 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK8,Host Channel 8 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ8,Host Channel 8 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA8,Host Channel 8 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x61C++0x1B
line.long 0x0 "HCDMAB8,Host Channel 8 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR9,Host Channel 9 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT9,Host Channel 9 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT9,Host Channel 9 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK9,Host Channel 9 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ9,Host Channel 9 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA9,Host Channel 9 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x63C++0x1B
line.long 0x0 "HCDMAB9,Host Channel 9 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR10,Host Channel 10 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT10,Host Channel 10 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT10,Host Channel 10 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK10,Host Channel 10 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ10,Host Channel 10 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA10,Host Channel 10 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x65C++0x1B
line.long 0x0 "HCDMAB10,Host Channel 10 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR11,Host Channel 11 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT11,Host Channel 11 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT11,Host Channel 11 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK11,Host Channel 11 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ11,Host Channel 11 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA11,Host Channel 11 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x67C++0x1B
line.long 0x0 "HCDMAB11,Host Channel 11 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR12,Host Channel 12 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT12,Host Channel 12 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT12,Host Channel 12 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK12,Host Channel 12 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
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bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
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bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
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bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ12,Host Channel 12 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
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bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
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hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA12,Host Channel 12 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x69C++0x1B
line.long 0x0 "HCDMAB12,Host Channel 12 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR13,Host Channel 13 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT13,Host Channel 13 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT13,Host Channel 13 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
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eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK13,Host Channel 13 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
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bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
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bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ13,Host Channel 13 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA13,Host Channel 13 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x6BC++0x1B
line.long 0x0 "HCDMAB13,Host Channel 13 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR14,Host Channel 14 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT14,Host Channel 14 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT14,Host Channel 14 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK14,Host Channel 14 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ14,Host Channel 14 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA14,Host Channel 14 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x6DC++0x1B
line.long 0x0 "HCDMAB14,Host Channel 14 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
line.long 0x4 "HCCHAR15,Host Channel 15 Characteristics Register"
bitfld.long 0x4 31. "ChEna,Channel Enable (ChEna)" "0: Channel disabled,1: Channel enabled"
newline
bitfld.long 0x4 30. "ChDis,Channel Disable (ChDis)" "0,1"
newline
bitfld.long 0x4 29. "OddFrm,Odd Frame (OddFrm)" "0: Even,1: Odd"
newline
hexmask.long.byte 0x4 22.--28. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x4 20.--21. "EC,Multi Count (MC) / Error Count (EC)" "0: Reserved This field yields undefined results,1: 1 transaction,2: 2 transactions to be issued for this endpoint per,3: 3 transactions to be issued for this endpoint per"
newline
bitfld.long 0x4 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
bitfld.long 0x4 17. "LSpdDev,Low-Speed Device (LSpdDev)" "0,1"
newline
rbitfld.long 0x4 16. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x4 15. "EPDir,Endpoint Direction (EPDir)" "0: OUT,1: IN"
newline
hexmask.long.byte 0x4 11.--14. 1. "EPNum,Endpoint Number (EPNum)"
newline
hexmask.long.word 0x4 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
line.long 0x8 "HCSPLT15,Host Channel 15 Split Control Register"
bitfld.long 0x8 31. "SpltEna,Split Enable (SpltEna)" "0,1"
newline
hexmask.long.word 0x8 17.--30. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 16. "CompSplt,Do Complete Split (CompSplt)" "0,1"
newline
bitfld.long 0x8 14.--15. "XactPos,Transaction Position (XactPos)" "0: Mid,1: End,2: Begin,3: All"
newline
hexmask.long.byte 0x8 7.--13. 1. "HubAddr,Hub Address (HubAddr)"
newline
hexmask.long.byte 0x8 0.--6. 1. "PrtAddr,Port Address (PrtAddr)"
line.long 0xC "HCINT15,Host Channel 15 Interrupt Register"
hexmask.long.tbyte 0xC 14.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0xC 13. "DESC_LST_ROLLIntr,Descriptor rollover interrupt (DESC_LST_ROLLIntr)" "0,1"
newline
eventfld.long 0xC 12. "XCS_XACT_ERR,Excessive Transaction Error (XCS_XACT_ERR)" "0,1"
newline
eventfld.long 0xC 11. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0xC 10. "DataTglErr,Data Toggle Error (DataTglErr).This bit can be set only by the core and the application should write 1 to clear" "0,1"
newline
eventfld.long 0xC 9. "FrmOvrun,Frame Overrun (FrmOvrun).In Scatter/Gather DMA mode  the interrupt due to this bit is masked" "0,1"
newline
eventfld.long 0xC 8. "BblErr,Babble Error (BblErr)" "0,1"
newline
eventfld.long 0xC 7. "XactErr,Transaction Error (XactErr)" "0,1"
newline
eventfld.long 0xC 6. "NYET,NYET Response Received Interrupt (NYET)" "0,1"
newline
eventfld.long 0xC 5. "ACK,ACK Response Received/Transmitted Interrupt (ACK)" "0,1"
newline
eventfld.long 0xC 4. "NAK,NAK Response Received Interrupt (NAK)" "0,1"
newline
eventfld.long 0xC 3. "STALL,STALL Response Received Interrupt (STALL)" "0,1"
newline
eventfld.long 0xC 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0xC 1. "ChHltd,Channel Halted (ChHltd)" "0,1"
newline
eventfld.long 0xC 0. "XferCompl,Transfer Completed (XferCompl)" "0,1"
line.long 0x10 "HCINTMSK15,Host Channel 15 Interrupt Mask Register"
hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x10 13. "FRM_LST_ROLLIntrMsk,Framelist rollover interrupt Mask register(FRM_LST_ROLLIntrMsk)" "0,1"
newline
rbitfld.long 0x10 12. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x10 11. "BNAIntrMsk,BNA (Buffer Not Available) Interrupt mask register (BNAIntrMsk)" "0,1"
newline
bitfld.long 0x10 10. "DataTglErrMsk,Data Toggle Error Mask (DataTglErrMsk)" "0,1"
newline
bitfld.long 0x10 9. "FrmOvrunMsk,Frame Overrun Mask (FrmOvrunMsk)" "0,1"
newline
bitfld.long 0x10 8. "BblErrMsk,Babble Error Mask (BblErrMsk)" "0,1"
newline
bitfld.long 0x10 7. "XactErrMsk,Transaction Error Mask (XactErrMsk)" "0,1"
newline
bitfld.long 0x10 6. "NyetMsk,NYET Response Received Interrupt Mask (NyetMsk)" "0,1"
newline
bitfld.long 0x10 5. "AckMsk,ACK Response Received/Transmitted Interrupt Mask (AckMsk)" "0,1"
newline
bitfld.long 0x10 4. "NakMsk,NAK Response Received Interrupt Mask (NakMsk)" "0,1"
newline
bitfld.long 0x10 3. "StallMsk,STALL Response Received Interrupt Mask (StallMsk)" "0,1"
newline
bitfld.long 0x10 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x10 1. "ChHltdMsk,Channel Halted Mask (ChHltdMsk)" "0,1"
newline
bitfld.long 0x10 0. "XferComplMsk,Transfer Completed Mask (XferComplMsk)" "0,1"
line.long 0x14 "HCTSIZ15,Host Channel 15 Transfer Size Register"
bitfld.long 0x14 31. "DoPng,Do Ping (DoPng)" "0,1"
newline
bitfld.long 0x14 29.--30. "Pid,PID (Pid)" "0: DATA0,1: DATA2,2: DATA1,3: MDATA"
newline
hexmask.long.word 0x14 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x14 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x18 "HCDMA15,Host Channel 15 DMA Address Register"
hexmask.long 0x18 0.--31. 1. "DMAAddr,Buffer DMA Mode:"
group.long 0x6FC++0x3
line.long 0x0 "HCDMAB15,Host Channel 15 DMA Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "HCDMAB,Holds the current buffer address."
group.long 0x800++0x7
line.long 0x0 "DCFG,Device Configuration Register"
hexmask.long.byte 0x0 26.--31. 1. "ResValid,Resume Validation Period (ResValid)"
newline
bitfld.long 0x0 24.--25. "PerSchIntvl,Periodic Scheduling Interval (PerSchIntvl)" "0: 25% of,1: 50% of,2: 75% of,3: Reserved"
newline
bitfld.long 0x0 23. "DescDMA,Enable Scatter/gather DMA in device mode (DescDMA)." "0: Buffered DMA,1: Scatter/Gather DMA mode"
newline
hexmask.long.byte 0x0 18.--22. 1. "Reserved_9,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x0 16.--17. "RESERVED,RESERVED" "0,1,2,3"
newline
bitfld.long 0x0 15. "ErraticIntMsk,Erratic Error Interrupt Mask" "0: Early suspend interrupt is generated on erratic..,1: Mask early suspend interrupt on erratic error"
newline
bitfld.long 0x0 14. "XCVRDLY,1'b1: Enable delay between xcvr_sel and txvalid during Device chirp" "0: No delay between xcvr_sel and txvalid during..,1: Enable delay between xcvr_sel and txvalid during.."
newline
bitfld.long 0x0 13. "EnDevOutNak,Enable Device OUT NAK (EnDevOutNak)" "0: The core does not set NAK after Bulk OUT..,1: The core sets NAK after Bulk OUT transfer complete"
newline
bitfld.long 0x0 11.--12. "PerFrInt,Periodic Frame Interval (PerFrInt)" "0: 80% of the,1: 85%,2: 90%,3: 95%"
newline
hexmask.long.byte 0x0 4.--10. 1. "DevAddr,Device Address (DevAddr)"
newline
bitfld.long 0x0 3. "Ena32KHzSusp,Enable 32 KHz Suspend mode (Ena32KHzSusp)" "0,1"
newline
bitfld.long 0x0 2. "NZStsOUTHShk,Non-Zero-Length Status OUT Handshake (NZStsOUTHShk)" "0: Send the received OUT packet to the application,1: Send a STALL handshake on a nonzero-length status"
newline
bitfld.long 0x0 0.--1. "DevSpd,Device Speed (DevSpd)" "0: High speed,1: Full speed,2: Low speed,3: Full speed"
line.long 0x4 "DCTL,Device Control Register"
hexmask.long.word 0x4 19.--31. 1. "RESERVED,RESERVED"
newline
rbitfld.long 0x4 18. "Reserved_14,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x4 17. "EnContOnBNA,Enable Continue on BNA (EnContOnBNA)" "0: After receiving BNA interrupt,1: After receiving BNA interrupt"
newline
bitfld.long 0x4 16. "NakOnBble,NAK on Babble Error (NakOnBble)" "0,1"
newline
bitfld.long 0x4 15. "IgnrFrmNum,Ignore Frame number For Isochronous End points (IgnrFrmNum)" "0: periodic transfer interrupt feature is disabled,1: periodic transfer interrupt feature is enabled"
newline
bitfld.long 0x4 13.--14. "GMC,Global Multi Count (GMC)" "0: Invalid,1: 1 packet,2: 2 packets,3: 3 packets"
newline
rbitfld.long 0x4 12. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x4 11. "PWROnPrgDone,Power-On Programming Done (PWROnPrgDone)" "0,1"
newline
bitfld.long 0x4 10. "CGOUTNak,Clear Global OUT NAK (CGOUTNak)" "0,1"
newline
bitfld.long 0x4 9. "SGOUTNak,Set Global OUT NAK (SGOUTNak)" "0,1"
newline
bitfld.long 0x4 8. "CGNPInNak,Clear Global Non-periodic IN NAK (CGNPInNak)" "0,1"
newline
bitfld.long 0x4 7. "SGNPInNak,Set Global Non-periodic IN NAK (SGNPInNak)" "0,1"
newline
bitfld.long 0x4 4.--6. "TstCtl,Test Control (TstCtl)" "0: Test mode disabled,1: Test_J mode,2: Test_K mode,3: Test_SE0_NAK mode,4: Test_Packet mode,5: Test_Force_Enable,?,?"
newline
rbitfld.long 0x4 3. "GOUTNakSts,Global OUT NAK Status (GOUTNakSts)" "0: A handshake is sent based on the FIFO Status and..,1: No data is written to the RxFIFO"
newline
rbitfld.long 0x4 2. "GNPINNakSts,Global Non-periodic IN NAK Status (GNPINNakSts)" "0: A handshake is sent out based on the data..,1: A NAK handshake is sent out on all non-periodic IN"
newline
bitfld.long 0x4 1. "SftDiscon,Soft Disconnect (SftDiscon)" "0: Normal operation,1: The core drives the phy_opmode_o signal on the"
newline
bitfld.long 0x4 0. "RmtWkUpSig,Remote Wakeup Signaling (RmtWkUpSig)" "0,1"
rgroup.long 0x808++0x3
line.long 0x0 "DSTS,Device Status Register"
hexmask.long.byte 0x0 24.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x0 22.--23. "DevLnSts,Device Line Status (DevLnSts)" "0,1,2,3"
newline
hexmask.long.word 0x0 8.--21. 1. "SOFFN,Frame or Microframe Number of the Received SOF (SOFFN)"
newline
hexmask.long.byte 0x0 4.--7. 1. "RESERVED1,RESERVED"
newline
bitfld.long 0x0 3. "ErrticErr,Erratic Error (ErrticErr)" "0,1"
newline
bitfld.long 0x0 1.--2. "EnumSpd,Enumerated Speed (EnumSpd)" "0: High speed,1: Full speed,2: Low speed,3: Full speed"
newline
bitfld.long 0x0 0. "SuspSts,Suspend Status (SuspSts)" "0,1"
group.long 0x810++0x7
line.long 0x0 "DIEPMSK,Device IN Endpoint Common Interrupt Mask Register"
hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x0 13. "NAKMsk,NAK interrupt Mask (NAKMsk)" "0,1"
newline
rbitfld.long 0x0 10.--12. "Reserved_10,Reserved bitfield added by Magillem" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 9. "BNAInIntrMsk,BNA interrupt Mask (BNAInIntrMsk)" "0,1"
newline
bitfld.long 0x0 8. "TxfifoUndrnMsk,Fifo Underrun Mask (TxfifoUndrnMsk)" "0,1"
newline
rbitfld.long 0x0 7. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x0 6. "INEPNakEffMsk,IN Endpoint NAK Effective Mask (INEPNakEffMsk)" "0,1"
newline
bitfld.long 0x0 5. "INTknEPMisMsk,IN Token received with EP Mismatch Mask (INTknEPMisMsk)" "0,1"
newline
bitfld.long 0x0 4. "INTknTXFEmpMsk,IN Token Received When TxFIFO Empty Mask" "0,1"
newline
bitfld.long 0x0 3. "TimeOUTMsk,Timeout Condition Mask (TimeOUTMsk)" "0,1"
newline
bitfld.long 0x0 2. "AHBErrMsk,AHB Error Mask (AHBErrMsk)" "0,1"
newline
bitfld.long 0x0 1. "EPDisbldMsk,Endpoint Disabled Interrupt Mask (EPDisbldMsk)" "0,1"
newline
bitfld.long 0x0 0. "XferComplMsk,Transfer Completed Interrupt Mask (XferComplMsk)" "0,1"
line.long 0x4 "DOEPMSK,Device OUT Endpoint Common Interrupt Mask Register"
hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x4 14. "NYETMsk,NYET interrupt Mask (NYETMsk)" "0,1"
newline
bitfld.long 0x4 13. "NAKMsk,NAK interrupt Mask (NAKMsk)" "0,1"
newline
bitfld.long 0x4 12. "BbleErrMsk,Babble Error interrupt Mask (BbleErrMsk)" "0,1"
newline
rbitfld.long 0x4 10.--11. "Reserved_10,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x4 9. "BnaOutIntrMsk,BNA interrupt Mask (BnaOutIntrMsk)" "0,1"
newline
bitfld.long 0x4 8. "OutPktErrMsk,OUT Packet Error Mask (OutPktErrMsk)" "0,1"
newline
rbitfld.long 0x4 7. "RESERVED1,RESERVED" "0,1"
newline
bitfld.long 0x4 6. "Back2BackSETup,Back-to-Back SETUP Packets Received Mask" "0,1"
newline
bitfld.long 0x4 5. "StsPhseRcvdMsk,Status Phase Received Mask" "0,1"
newline
bitfld.long 0x4 4. "OUTTknEPdisMsk,OUT Token Received when Endpoint Disabled Mask" "0,1"
newline
bitfld.long 0x4 3. "SetUPMsk,SETUP Phase Done Mask (SetUPMsk)" "0,1"
newline
bitfld.long 0x4 2. "AHBErrMsk,AHB Error (AHBErrMsk)" "0,1"
newline
bitfld.long 0x4 1. "EPDisbldMsk,Endpoint Disabled Interrupt Mask (EPDisbldMsk)" "0,1"
newline
bitfld.long 0x4 0. "XferComplMsk,Transfer Completed Interrupt Mask (XferComplMsk)" "0,1"
rgroup.long 0x818++0x3
line.long 0x0 "DAINT,Device All Endpoints Interrupt Register"
bitfld.long 0x0 31. "OutEPInt15,OUT Endpoint 15 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 30. "OutEPInt14,OUT Endpoint 14 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 29. "OutEPInt13,OUT Endpoint 13 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 28. "OutEPInt12,OUT Endpoint 12 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 27. "OutEPInt11,OUT Endpoint 11 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 26. "OutEPInt10,OUT Endpoint 10 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 25. "OutEPInt9,OUT Endpoint 9 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 24. "OutEPInt8,OUT Endpoint 8 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 23. "OutEPInt7,OUT Endpoint 7 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 22. "OutEPInt6,OUT Endpoint 6 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 21. "OutEPInt5,OUT Endpoint 5 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 20. "OutEPInt4,OUT Endpoint 4 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 19. "OutEPInt3,OUT Endpoint 3 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 18. "OutEPInt2,OUT Endpoint 2 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 17. "OutEPInt1,OUT Endpoint 1 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 16. "OutEPInt0,OUT Endpoint 0 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 15. "InEpInt15,IN Endpoint 15 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 14. "InEpInt14,IN Endpoint 14 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 13. "InEpInt13,IN Endpoint 13 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 12. "InEpInt12,IN Endpoint 12 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 11. "InEpInt11,IN Endpoint 11 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 10. "InEpInt10,IN Endpoint 10 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 9. "InEpInt9,IN Endpoint 9 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 8. "InEpInt8,IN Endpoint 8 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 7. "InEpInt7,IN Endpoint 7 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 6. "InEpInt6,IN Endpoint 6 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 5. "InEpInt5,IN Endpoint 5 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 4. "InEpInt4,IN Endpoint 4 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 3. "InEpInt3,IN Endpoint 3 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 2. "InEpInt2,IN Endpoint 2 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 1. "InEpInt1,IN Endpoint 1 Interrupt Bit" "0,1"
newline
bitfld.long 0x0 0. "InEpInt0,IN Endpoint 0 Interrupt Bit" "0,1"
group.long 0x81C++0x3
line.long 0x0 "DAINTMSK,Device All Endpoints Interrupt Mask Register"
bitfld.long 0x0 31. "OutEPMsk15,OUT Endpoint 15 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 30. "OutEPMsk14,OUT Endpoint 14 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 29. "OutEPMsk13,OUT Endpoint 13 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 28. "OutEPMsk12,OUT Endpoint 12 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 27. "OutEPMsk11,OUT Endpoint 11 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 26. "OutEPMsk10,OUT Endpoint 10 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 25. "OutEPMsk9,OUT Endpoint 9 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 24. "OutEPMsk8,OUT Endpoint 8 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 23. "OutEPMsk7,OUT Endpoint 7 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 22. "OutEPMsk6,OUT Endpoint 6 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 21. "OutEPMsk5,OUT Endpoint 5 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 20. "OutEPMsk4,OUT Endpoint 4 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 19. "OutEPMsk3,OUT Endpoint 3 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 18. "OutEPMsk2,OUT Endpoint 2 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 17. "OutEPMsk1,OUT Endpoint 1 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 16. "OutEPMsk0,OUT Endpoint 0 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 15. "InEpMsk15,IN Endpoint 15 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 14. "InEpMsk14,IN Endpoint 14 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 13. "InEpMsk13,IN Endpoint 13 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 12. "InEpMsk12,IN Endpoint 12 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 11. "InEpMsk11,IN Endpoint 11 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 10. "InEpMsk10,IN Endpoint 10 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 9. "InEpMsk9,IN Endpoint 9 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 8. "InEpMsk8,IN Endpoint 8 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 7. "InEpMsk7,IN Endpoint 7 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 6. "InEpMsk6,IN Endpoint 6 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 5. "InEpMsk5,IN Endpoint 5 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 4. "InEpMsk4,IN Endpoint 4 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 3. "InEpMsk3,IN Endpoint 3 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 2. "InEpMsk2,IN Endpoint 2 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 1. "InEpMsk1,IN Endpoint 1 Interrupt mask Bit" "0,1"
newline
bitfld.long 0x0 0. "InEpMsk0,IN Endpoint 0 Interrupt mask Bit" "0,1"
group.long 0x828++0xF
line.long 0x0 "DVBUSDIS,Device VBUS Discharge Time Register"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "DVBUSDis,Device VBUS Discharge Time (DVBUSDis)"
line.long 0x4 "DVBUSPULSE,Device VBUS Pulsing Time Register"
hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x4 0.--11. 1. "DVBUSPulse,Device VBUS Pulsing Time (DVBUSPulse)"
line.long 0x8 "DTHRCTL,Device Threshold Control Register"
hexmask.long.byte 0x8 28.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x8 27. "ArbPrkEn,Arbiter Parking Enable (ArbPrkEn)" "0,1"
newline
rbitfld.long 0x8 26. "RESERVED1,RESERVED" "0,1"
newline
hexmask.long.word 0x8 17.--25. 1. "RxThrLen,Receive Threshold Length (RxThrLen)"
newline
bitfld.long 0x8 16. "RxThrEn,Receive Threshold Enable (RxThrEn)" "0,1"
newline
rbitfld.long 0x8 13.--15. "RESERVED2,RESERVED" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x8 11.--12. "AHBThrRatio,AHB Threshold Ratio (AHBThrRatio)" "0: AHB threshold = MAC threshold,1: AHB threshold = MAC threshold / 2,2: AHB threshold = MAC threshold / 4,3: AHB threshold = MAC threshold / 8"
newline
hexmask.long.word 0x8 2.--10. 1. "TxThrLen,Transmit Threshold Length (TxThrLen)"
newline
bitfld.long 0x8 1. "ISOThrEn,ISO IN Endpoints Threshold Enable. (ISOThrEn)" "0,1"
newline
bitfld.long 0x8 0. "NonISOThrEn,Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn)" "0,1"
line.long 0xC "DIEPEMPMSK,Device IN Endpoint FIFO Empty Interrupt Mask Register"
hexmask.long.word 0xC 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0xC 0.--15. 1. "InEpTxfEmpMsk,IN EP Tx FIFO Empty Interrupt Mask Bits (InEpTxfEmpMsk)"
group.long 0x900++0x3
line.long 0x0 "DIEPCTL0,Device Control IN Endpoint 0 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
rbitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "RESERVED1,RESERVED" "0,1"
newline
rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0,1,2,3"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "RESERVED2,RESERVED" "0,1"
newline
rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_2,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 2.--10. 1. "RESERVED3,RESERVED"
newline
bitfld.long 0x0 0.--1. "MPS,Maximum Packet Size (MPS)" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes"
group.long 0x908++0x3
line.long 0x0 "DIEPINT0,Device IN Endpoint 0 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x910++0x7
line.long 0x0 "DIEPTSIZ0,Device IN Endpoint 0 Transfer Size Register"
hexmask.long.word 0x0 21.--31. 1. "RESERVED,RESERVED"
newline
bitfld.long 0x0 19.--20. "PktCnt,Packet Count (PktCnt)" "0,1,2,3"
newline
hexmask.long.word 0x0 7.--18. 1. "RESERVED1,RESERVED"
newline
hexmask.long.byte 0x0 0.--6. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA0,Device IN Endpoint 0 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x918++0x7
line.long 0x0 "DTXFSTS0,Device IN Endpoint Transmit FIFO Status Register 0"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB0,Device IN Endpoint 16 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x920++0x3
line.long 0x0 "DIEPCTL1,Device Control IN Endpoint 1 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x928++0x3
line.long 0x0 "DIEPINT1,Device IN Endpoint 1 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x930++0x7
line.long 0x0 "DIEPTSIZ1,Device IN Endpoint 1 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA1,Device IN Endpoint 1 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x938++0x7
line.long 0x0 "DTXFSTS1,Device IN Endpoint Transmit FIFO Status Register 1"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB1,Device IN Endpoint 1 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x940++0x3
line.long 0x0 "DIEPCTL2,Device Control IN Endpoint 2 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x948++0x3
line.long 0x0 "DIEPINT2,Device IN Endpoint 2 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x950++0x7
line.long 0x0 "DIEPTSIZ2,Device IN Endpoint 2 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA2,Device IN Endpoint 2 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x958++0x7
line.long 0x0 "DTXFSTS2,Device IN Endpoint Transmit FIFO Status Register 2"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB2,Device IN Endpoint 2 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x960++0x3
line.long 0x0 "DIEPCTL3,Device Control IN Endpoint 3 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x968++0x3
line.long 0x0 "DIEPINT3,Device IN Endpoint 3 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x970++0x7
line.long 0x0 "DIEPTSIZ3,Device IN Endpoint 3 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA3,Device IN Endpoint 3 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x978++0x7
line.long 0x0 "DTXFSTS3,Device IN Endpoint Transmit FIFO Status Register 3"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB3,Device IN Endpoint 3 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x980++0x3
line.long 0x0 "DIEPCTL4,Device Control IN Endpoint 4 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x988++0x3
line.long 0x0 "DIEPINT4,Device IN Endpoint 4 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x990++0x7
line.long 0x0 "DIEPTSIZ4,Device IN Endpoint 4 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA4,Device IN Endpoint 4 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x998++0x7
line.long 0x0 "DTXFSTS4,Device IN Endpoint Transmit FIFO Status Register 4"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB4,Device IN Endpoint 4 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x9A0++0x3
line.long 0x0 "DIEPCTL5,Device Control IN Endpoint 5 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x9A8++0x3
line.long 0x0 "DIEPINT5,Device IN Endpoint 5 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x9B0++0x7
line.long 0x0 "DIEPTSIZ5,Device IN Endpoint 5 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA5,Device IN Endpoint 5 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x9B8++0x7
line.long 0x0 "DTXFSTS5,Device IN Endpoint Transmit FIFO Status Register 5"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB5,Device IN Endpoint 5 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x9C0++0x3
line.long 0x0 "DIEPCTL6,Device Control IN Endpoint 6 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x9C8++0x3
line.long 0x0 "DIEPINT6,Device IN Endpoint 6 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x9D0++0x7
line.long 0x0 "DIEPTSIZ6,Device IN Endpoint 6 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA6,Device IN Endpoint 6 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x9D8++0x7
line.long 0x0 "DTXFSTS6,Device IN Endpoint Transmit FIFO Status Register 6"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB6,Device IN Endpoint 6 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0x9E0++0x3
line.long 0x0 "DIEPCTL7,Device Control IN Endpoint 7 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0x9E8++0x3
line.long 0x0 "DIEPINT7,Device IN Endpoint 7 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0x9F0++0x7
line.long 0x0 "DIEPTSIZ7,Device IN Endpoint 7 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA7,Device IN Endpoint 7 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0x9F8++0x7
line.long 0x0 "DTXFSTS7,Device IN Endpoint Transmit FIFO Status Register 7"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB7,Device IN Endpoint 7 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA00++0x3
line.long 0x0 "DIEPCTL8,Device Control IN Endpoint 8 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA08++0x3
line.long 0x0 "DIEPINT8,Device IN Endpoint 8 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA10++0x7
line.long 0x0 "DIEPTSIZ8,Device IN Endpoint 8 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA8,Device IN Endpoint 8 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA18++0x7
line.long 0x0 "DTXFSTS8,Device IN Endpoint Transmit FIFO Status Register 8"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB8,Device IN Endpoint 8 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA20++0x3
line.long 0x0 "DIEPCTL9,Device Control IN Endpoint 9 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA28++0x3
line.long 0x0 "DIEPINT9,Device IN Endpoint 9 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA30++0x7
line.long 0x0 "DIEPTSIZ9,Device IN Endpoint 9 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA9,Device IN Endpoint 9 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA38++0x7
line.long 0x0 "DTXFSTS9,Device IN Endpoint Transmit FIFO Status Register 9"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB9,Device IN Endpoint 9 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA40++0x3
line.long 0x0 "DIEPCTL10,Device Control IN Endpoint 10 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA48++0x3
line.long 0x0 "DIEPINT10,Device IN Endpoint 10 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA50++0x7
line.long 0x0 "DIEPTSIZ10,Device IN Endpoint 10 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA10,Device IN Endpoint 10 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA58++0x7
line.long 0x0 "DTXFSTS10,Device IN Endpoint Transmit FIFO Status Register 10"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB10,Device IN Endpoint 10 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA60++0x3
line.long 0x0 "DIEPCTL11,Device Control IN Endpoint 11 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA68++0x3
line.long 0x0 "DIEPINT11,Device IN Endpoint 11 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA70++0x7
line.long 0x0 "DIEPTSIZ11,Device IN Endpoint 11 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA11,Device IN Endpoint 11 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA78++0x7
line.long 0x0 "DTXFSTS11,Device IN Endpoint Transmit FIFO Status Register 11"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB11,Device IN Endpoint 11 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xA80++0x3
line.long 0x0 "DIEPCTL12,Device Control IN Endpoint 12 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xA88++0x3
line.long 0x0 "DIEPINT12,Device IN Endpoint 12 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xA90++0x7
line.long 0x0 "DIEPTSIZ12,Device IN Endpoint 12 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA12,Device IN Endpoint 12 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xA98++0x7
line.long 0x0 "DTXFSTS12,Device IN Endpoint Transmit FIFO Status Register 12"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB12,Device IN Endpoint 12 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xAA0++0x3
line.long 0x0 "DIEPCTL13,Device Control IN Endpoint 13 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xAA8++0x3
line.long 0x0 "DIEPINT13,Device IN Endpoint 13 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xAB0++0x7
line.long 0x0 "DIEPTSIZ13,Device IN Endpoint 13 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA13,Device IN Endpoint 13 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xAB8++0x7
line.long 0x0 "DTXFSTS13,Device IN Endpoint Transmit FIFO Status Register 13"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB13,Device IN Endpoint 13 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xAC0++0x3
line.long 0x0 "DIEPCTL14,Device Control IN Endpoint 14 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xAC8++0x3
line.long 0x0 "DIEPINT14,Device IN Endpoint 14 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xAD0++0x7
line.long 0x0 "DIEPTSIZ14,Device IN Endpoint 14 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA14,Device IN Endpoint 14 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xAD8++0x7
line.long 0x0 "DTXFSTS14,Device IN Endpoint Transmit FIFO Status Register 14"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB14,Device IN Endpoint 14 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xAE0++0x3
line.long 0x0 "DIEPCTL15,Device Control IN Endpoint 15 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "TxFNum,TxFIFO Number (TxFNum)"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
rbitfld.long 0x0 20. "Reserved_5,Reserved bitfield added by Magillem" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xAE8++0x3
line.long 0x0 "DIEPINT15,Device IN Endpoint 15 Interrupt Register"
hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,RESERVED"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_10,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "TxfifoUndrn,Fifo Underrun (TxfifoUndrn)" "0,1"
newline
rbitfld.long 0x0 7. "TxFEmp,Transmit FIFO Empty (TxFEmp)" "0,1"
newline
eventfld.long 0x0 6. "INEPNakEff,IN Endpoint NAK Effective (INEPNakEff)" "0,1"
newline
eventfld.long 0x0 5. "INTknEPMis,IN Token Received with EP Mismatch (INTknEPMis)" "0,1"
newline
eventfld.long 0x0 4. "INTknTXFEmp,IN Token Received When TxFIFO is Empty (INTknTXFEmp)" "0,1"
newline
eventfld.long 0x0 3. "TimeOUT,Timeout Condition (TimeOUT)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xAF0++0x7
line.long 0x0 "DIEPTSIZ15,Device IN Endpoint 15 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "MC,Applies to IN endpoints only." "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DIEPDMA15,Device IN Endpoint 15 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xAF8++0x7
line.long 0x0 "DTXFSTS15,Device IN Endpoint Transmit FIFO Status Register 15"
hexmask.long.word 0x0 16.--31. 1. "RESERVED,RESERVED"
newline
hexmask.long.word 0x0 0.--15. 1. "INEPTxFSpcAvail,IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail)"
line.long 0x4 "DIEPDMAB15,Device IN Endpoint 15 Buffer Address Register"
hexmask.long 0x4 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB00++0x3
line.long 0x0 "DOEPCTL0,Device Control OUT Endpoint 0 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
rbitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
rbitfld.long 0x0 28.--29. "RESERVED,RESERVED" "0,1,2,3"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "RESERVED1,RESERVED"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
rbitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0,1,2,3"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes based,1: The core is transmitting NAK handshakes on this"
newline
rbitfld.long 0x0 16. "RESERVED2,RESERVED" "0,1"
newline
rbitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.word 0x0 2.--14. 1. "RESERVED3,RESERVED"
newline
rbitfld.long 0x0 0.--1. "MPS,Maximum Packet Size (MPS)" "0: 64 bytes,1: 32 bytes,2: 16 bytes,3: 8 bytes"
group.long 0xB08++0x3
line.long 0x0 "DOEPINT0,Device OUT Endpoint 0 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB10++0x7
line.long 0x0 "DOEPTSIZ0,Device OUT Endpoint 0 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
bitfld.long 0x0 29.--30. "SUPCnt,SETUP Packet Count (SUPCnt)" "?,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 20.--28. 1. "RESERVED1,RESERVED"
newline
bitfld.long 0x0 19. "PktCnt,Packet Count (PktCnt)" "0,1"
newline
hexmask.long.word 0x0 7.--18. 1. "RESERVED2,RESERVED"
newline
hexmask.long.byte 0x0 0.--6. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA0,Device OUT Endpoint 0 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB1C++0x3
line.long 0x0 "DOEPDMAB0,Device OUT Endpoint 16 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB20++0x3
line.long 0x0 "DOEPCTL1,Device Control OUT Endpoint 1 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB28++0x3
line.long 0x0 "DOEPINT1,Device OUT Endpoint 1 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB30++0x7
line.long 0x0 "DOEPTSIZ1,Device OUT Endpoint 1 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA1,Device OUT Endpoint 1 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB3C++0x3
line.long 0x0 "DOEPDMAB1,Device OUT Endpoint 1 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB40++0x3
line.long 0x0 "DOEPCTL2,Device Control OUT Endpoint 2 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB48++0x3
line.long 0x0 "DOEPINT2,Device OUT Endpoint 2 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB50++0x7
line.long 0x0 "DOEPTSIZ2,Device OUT Endpoint 2 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA2,Device OUT Endpoint 2 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB5C++0x3
line.long 0x0 "DOEPDMAB2,Device OUT Endpoint 2 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB60++0x3
line.long 0x0 "DOEPCTL3,Device Control OUT Endpoint 3 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB68++0x3
line.long 0x0 "DOEPINT3,Device OUT Endpoint 3 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB70++0x7
line.long 0x0 "DOEPTSIZ3,Device OUT Endpoint 3 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA3,Device OUT Endpoint 3 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB7C++0x3
line.long 0x0 "DOEPDMAB3,Device OUT Endpoint 3 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xB80++0x3
line.long 0x0 "DOEPCTL4,Device Control OUT Endpoint 4 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xB88++0x3
line.long 0x0 "DOEPINT4,Device OUT Endpoint 4 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xB90++0x7
line.long 0x0 "DOEPTSIZ4,Device OUT Endpoint 4 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA4,Device OUT Endpoint 4 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xB9C++0x3
line.long 0x0 "DOEPDMAB4,Device OUT Endpoint 4 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xBA0++0x3
line.long 0x0 "DOEPCTL5,Device Control OUT Endpoint 5 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xBA8++0x3
line.long 0x0 "DOEPINT5,Device OUT Endpoint 5 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xBB0++0x7
line.long 0x0 "DOEPTSIZ5,Device OUT Endpoint 5 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA5,Device OUT Endpoint 5 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xBBC++0x3
line.long 0x0 "DOEPDMAB5,Device OUT Endpoint 5 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xBC0++0x3
line.long 0x0 "DOEPCTL6,Device Control OUT Endpoint 6 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xBC8++0x3
line.long 0x0 "DOEPINT6,Device OUT Endpoint 6 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xBD0++0x7
line.long 0x0 "DOEPTSIZ6,Device OUT Endpoint 6 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA6,Device OUT Endpoint 6 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xBDC++0x3
line.long 0x0 "DOEPDMAB6,Device OUT Endpoint 6 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xBE0++0x3
line.long 0x0 "DOEPCTL7,Device Control OUT Endpoint 7 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xBE8++0x3
line.long 0x0 "DOEPINT7,Device OUT Endpoint 7 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xBF0++0x7
line.long 0x0 "DOEPTSIZ7,Device OUT Endpoint 7 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA7,Device OUT Endpoint 7 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xBFC++0x3
line.long 0x0 "DOEPDMAB7,Device OUT Endpoint 7 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC00++0x3
line.long 0x0 "DOEPCTL8,Device Control OUT Endpoint 8 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC08++0x3
line.long 0x0 "DOEPINT8,Device OUT Endpoint 8 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC10++0x7
line.long 0x0 "DOEPTSIZ8,Device OUT Endpoint 8 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA8,Device OUT Endpoint 8 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC1C++0x3
line.long 0x0 "DOEPDMAB8,Device OUT Endpoint 8 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC20++0x3
line.long 0x0 "DOEPCTL9,Device Control OUT Endpoint 9 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC28++0x3
line.long 0x0 "DOEPINT9,Device OUT Endpoint 9 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC30++0x7
line.long 0x0 "DOEPTSIZ9,Device OUT Endpoint 9 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA9,Device OUT Endpoint 9 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC3C++0x3
line.long 0x0 "DOEPDMAB9,Device OUT Endpoint 9 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC40++0x3
line.long 0x0 "DOEPCTL10,Device Control OUT Endpoint 10 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC48++0x3
line.long 0x0 "DOEPINT10,Device OUT Endpoint 10 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC50++0x7
line.long 0x0 "DOEPTSIZ10,Device OUT Endpoint 10 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA10,Device OUT Endpoint 10 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC5C++0x3
line.long 0x0 "DOEPDMAB10,Device OUT Endpoint 10 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC60++0x3
line.long 0x0 "DOEPCTL11,Device Control OUT Endpoint 11 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC68++0x3
line.long 0x0 "DOEPINT11,Device OUT Endpoint 11 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC70++0x7
line.long 0x0 "DOEPTSIZ11,Device OUT Endpoint 11 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA11,Device OUT Endpoint 11 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC7C++0x3
line.long 0x0 "DOEPDMAB11,Device OUT Endpoint 11 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xC80++0x3
line.long 0x0 "DOEPCTL12,Device Control OUT Endpoint 12 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xC88++0x3
line.long 0x0 "DOEPINT12,Device OUT Endpoint 12 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xC90++0x7
line.long 0x0 "DOEPTSIZ12,Device OUT Endpoint 12 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA12,Device OUT Endpoint 12 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xC9C++0x3
line.long 0x0 "DOEPDMAB12,Device OUT Endpoint 12 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xCA0++0x3
line.long 0x0 "DOEPCTL13,Device Control OUT Endpoint 13 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xCA8++0x3
line.long 0x0 "DOEPINT13,Device OUT Endpoint 13 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xCB0++0x7
line.long 0x0 "DOEPTSIZ13,Device OUT Endpoint 13 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA13,Device OUT Endpoint 13 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xCBC++0x3
line.long 0x0 "DOEPDMAB13,Device OUT Endpoint 13 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xCC0++0x3
line.long 0x0 "DOEPCTL14,Device Control OUT Endpoint 14 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xCC8++0x3
line.long 0x0 "DOEPINT14,Device OUT Endpoint 14 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xCD0++0x7
line.long 0x0 "DOEPTSIZ14,Device OUT Endpoint 14 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA14,Device OUT Endpoint 14 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xCDC++0x3
line.long 0x0 "DOEPDMAB14,Device OUT Endpoint 14 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xCE0++0x3
line.long 0x0 "DOEPCTL15,Device Control OUT Endpoint 15 Control Register"
bitfld.long 0x0 31. "EPEna,Endpoint Enable (EPEna)" "0,1"
newline
bitfld.long 0x0 30. "EPDis,Endpoint Disable (EPDis)" "0,1"
newline
bitfld.long 0x0 29. "SetD1PID,Set DATA1 PID (SetD1PID)" "0,1"
newline
bitfld.long 0x0 28. "SetD0PID,Set DATA0 PID (SetD0PID)" "0,1"
newline
bitfld.long 0x0 27. "SNAK,Set NAK (SNAK)" "0,1"
newline
bitfld.long 0x0 26. "CNAK,Clear NAK (CNAK)" "0,1"
newline
hexmask.long.byte 0x0 22.--25. 1. "Reserved_7,Reserved bitfield added by Magillem"
newline
bitfld.long 0x0 21. "Stall,STALL Handshake (Stall)" "0,1"
newline
bitfld.long 0x0 20. "Snp,Snoop Mode (Snp)" "0,1"
newline
bitfld.long 0x0 18.--19. "EPType,Endpoint Type (EPType)" "0: Control,1: Isochronous,2: Bulk,3: Interrupt"
newline
rbitfld.long 0x0 17. "NAKSts,NAK Status (NAKSts)" "0: The core is transmitting non-NAK handshakes..,1: The core is transmitting NAK handshakes on this.."
newline
rbitfld.long 0x0 16. "DPID,Endpoint Data PID (DPID)" "0: Even,1: Odd"
newline
bitfld.long 0x0 15. "USBActEP,USB Active Endpoint (USBActEP)" "0,1"
newline
hexmask.long.byte 0x0 11.--14. 1. "Reserved_1,Reserved bitfield added by Magillem"
newline
hexmask.long.word 0x0 0.--10. 1. "MPS,Maximum Packet Size (MPS)"
group.long 0xCE8++0x3
line.long 0x0 "DOEPINT15,Device OUT Endpoint 15 Interrupt Register"
hexmask.long.word 0x0 16.--31. 1. "Reserved_14,Reserved bitfield added by Magillem"
newline
eventfld.long 0x0 15. "StupPktRcvd,Setup Packet Received" "0: No Setup packet received,1: Setup packet received"
newline
eventfld.long 0x0 14. "NYETIntrpt,NYET Interrupt (NYETIntrpt)" "0,1"
newline
eventfld.long 0x0 13. "NAKIntrpt,NAK Interrupt (NAKInterrupt)" "0,1"
newline
eventfld.long 0x0 12. "BbleErr,NAK Interrupt (BbleErr)" "0,1"
newline
eventfld.long 0x0 11. "PktDrpSts,Packet Drop Status (PktDrpSts)" "0,1"
newline
rbitfld.long 0x0 10. "Reserved_9,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 9. "BNAIntr,BNA (Buffer Not Available) Interrupt (BNAIntr)" "0,1"
newline
eventfld.long 0x0 8. "OutPktErr,OUT Packet Error (OutPktErr)" "0,1"
newline
rbitfld.long 0x0 7. "Reserved_7,Reserved bitfield added by Magillem" "0,1"
newline
eventfld.long 0x0 6. "Back2BackSETup,Back-to-Back SETUP Packets Received (Back2BackSETup)" "0,1"
newline
eventfld.long 0x0 5. "StsPhseRcvd,Status Phase Received For Control Write (StsPhseRcvd)" "0,1"
newline
eventfld.long 0x0 4. "OUTTknEPdis,OUT Token Received When Endpoint Disabled (OUTTknEPdis)" "0,1"
newline
eventfld.long 0x0 3. "SetUp,SETUP Phase Done (SetUp)" "0,1"
newline
eventfld.long 0x0 2. "AHBErr,AHB Error (AHBErr)" "0,1"
newline
eventfld.long 0x0 1. "EPDisbld,Endpoint Disabled Interrupt (EPDisbld)" "0,1"
newline
eventfld.long 0x0 0. "XferCompl,Transfer Completed Interrupt (XferCompl)" "0,1"
group.long 0xCF0++0x7
line.long 0x0 "DOEPTSIZ15,Device OUT Endpoint 15 Transfer Size Register"
rbitfld.long 0x0 31. "RESERVED,RESERVED" "0,1"
newline
rbitfld.long 0x0 29.--30. "RxDPID,Applies to isochronous OUT endpoints only." "0: DATA0,1: 1 packet,2: 2 packets,3: 3 packets"
newline
hexmask.long.word 0x0 19.--28. 1. "PktCnt,Packet Count (PktCnt)"
newline
hexmask.long.tbyte 0x0 0.--18. 1. "XferSize,Transfer Size (XferSize)"
line.long 0x4 "DOEPDMA15,Device OUT Endpoint 15 DMA Address Register"
hexmask.long 0x4 0.--31. 1. "DMAAddr,Holds the start address of the external memory for storing or fetching endpoint"
rgroup.long 0xCFC++0x3
line.long 0x0 "DOEPDMAB15,Device OUT Endpoint 15 Buffer Address Register"
hexmask.long 0x0 0.--31. 1. "DMABufferAddr,Holds the current buffer address.This register is updated as and when the data"
group.long 0xE00++0x3
line.long 0x0 "PCGCCTL,Power and Clock Gating Control Register"
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_4,Reserved bitfield added by Magillem"
newline
rbitfld.long 0x0 7. "L1Suspended,L1 Deep Sleep" "0,1"
newline
rbitfld.long 0x0 6. "PhySleep,PHY In Sleep" "0,1"
newline
rbitfld.long 0x0 4.--5. "Reserved_2,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x0 3. "RstPdwnModule,Reset Power-Down Modules (RstPdwnModule)" "0,1"
newline
rbitfld.long 0x0 1.--2. "Reserved_1,Reserved bitfield added by Magillem" "0,1,2,3"
newline
bitfld.long 0x0 0. "StopPclk,Stop Pclk (StopPclk)" "0,1"
tree.end
tree "WATCHDOG (Watchdog Timers)"
base ad:0x0
tree "WATCHDOG_0"
base ad:0x10D00200
group.long 0x0++0x7
line.long 0x0 "WDT_CR,Control Register"
hexmask.long 0x0 5.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 2.--4. "RPL,Reset pulse length. Writes have no effect when the configuration parameter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1. "RMOD,Response mode. Writes have no effect when the parameter" "0: Generate a system reset,1: First generate an interrupt and if it is not.."
bitfld.long 0x0 0. "WDT_EN,When the configuration parameter WDT_ALWAYS_EN = 0  this bit can be set" "0: WDT disabled,1: WDT enabled"
line.long 0x4 "WDT_TORR,Timeout Range Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved,Reserved and read as 0."
hexmask.long.byte 0x4 4.--7. 1. "TOP_INIT,Timeout period for initialization."
newline
hexmask.long.byte 0x4 0.--3. 1. "TOP,Timeout period. Writes have no effect when the configuration parameter"
rgroup.long 0x8++0x3
line.long 0x0 "WDT_CCVR,Current Counter Value Register."
hexmask.long 0x0 0.--31. 1. "wdt_ccvr,This register  when read  is the current value of the internal"
wgroup.long 0xC++0x3
line.long 0x0 "WDT_CRR,Counter Restart Register."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "wdt_crr,This register is used to restart the WDT counter. As a safety feature to"
rgroup.long 0x10++0x7
line.long 0x0 "WDT_STAT,Interrupt Status Register."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "wdt_stat,This register shows the interrupt status of the WDT." "0: Interrupt is inactive,1: Interrupt is active regardless of polarity"
line.long 0x4 "WDT_EOI,Interrupt Clear Register."
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "wdt_eoi,Clears the watchdog interrupt. This can be used to clear the interrupt" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "WDT_COMP_PARAM_1,Component Parameters Register 1"
bitfld.long 0x0 29.--31. "RSVD_31_29" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 24.--28. 1. "WDT_CNT_WIDTH"
newline
hexmask.long.byte 0x0 20.--23. 1. "WDT_DFLT_TOP_INIT"
hexmask.long.byte 0x0 16.--19. 1. "WDT_DFLT_TOP"
newline
bitfld.long 0x0 13.--15. "RSVD_15_13" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 10.--12. "WDT_DFLT_RPL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8.--9. "APB_DATA_WIDTH" "0,1,2,3"
bitfld.long 0x0 7. "WDT_PAUSE" "0,1"
newline
bitfld.long 0x0 6. "WDT_USE_FIX_TOP" "0,1"
bitfld.long 0x0 5. "WDT_HC_TOP" "0,1"
newline
bitfld.long 0x0 4. "WDT_HC_RPL" "0,1"
bitfld.long 0x0 3. "WDT_HC_RMOD" "0,1"
newline
bitfld.long 0x0 2. "WDT_DUAL_TOP" "0,1"
bitfld.long 0x0 1. "WDT_DFLT_RMOD" "0,1"
newline
bitfld.long 0x0 0. "WDT_ALWAYS_EN" "0,1"
line.long 0x4 "WDT_COMP_VERSION,Component Version Register"
hexmask.long 0x4 0.--31. 1. "wdt_comp_version,ASCII value for each number in the version  followed by *. For example "
line.long 0x8 "WDT_COMP_TYPE,Component Type Register"
hexmask.long 0x8 0.--31. 1. "wdt_comp_type,Component Type Register"
tree.end
tree "WATCHDOG_1"
base ad:0x10D00300
group.long 0x0++0x7
line.long 0x0 "WDT_CR,Control Register"
hexmask.long 0x0 5.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 2.--4. "RPL,Reset pulse length. Writes have no effect when the configuration parameter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1. "RMOD,Response mode. Writes have no effect when the parameter" "0: Generate a system reset,1: First generate an interrupt and if it is not.."
bitfld.long 0x0 0. "WDT_EN,When the configuration parameter WDT_ALWAYS_EN = 0  this bit can be set" "0: WDT disabled,1: WDT enabled"
line.long 0x4 "WDT_TORR,Timeout Range Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved,Reserved and read as 0."
hexmask.long.byte 0x4 4.--7. 1. "TOP_INIT,Timeout period for initialization."
newline
hexmask.long.byte 0x4 0.--3. 1. "TOP,Timeout period. Writes have no effect when the configuration parameter"
rgroup.long 0x8++0x3
line.long 0x0 "WDT_CCVR,Current Counter Value Register."
hexmask.long 0x0 0.--31. 1. "wdt_ccvr,This register  when read  is the current value of the internal"
wgroup.long 0xC++0x3
line.long 0x0 "WDT_CRR,Counter Restart Register."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "wdt_crr,This register is used to restart the WDT counter. As a safety feature to"
rgroup.long 0x10++0x7
line.long 0x0 "WDT_STAT,Interrupt Status Register."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "wdt_stat,This register shows the interrupt status of the WDT." "0: Interrupt is inactive,1: Interrupt is active regardless of polarity"
line.long 0x4 "WDT_EOI,Interrupt Clear Register."
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "wdt_eoi,Clears the watchdog interrupt. This can be used to clear the interrupt" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "WDT_COMP_PARAM_1,Component Parameters Register 1"
bitfld.long 0x0 29.--31. "RSVD_31_29" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 24.--28. 1. "WDT_CNT_WIDTH"
newline
hexmask.long.byte 0x0 20.--23. 1. "WDT_DFLT_TOP_INIT"
hexmask.long.byte 0x0 16.--19. 1. "WDT_DFLT_TOP"
newline
bitfld.long 0x0 13.--15. "RSVD_15_13" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 10.--12. "WDT_DFLT_RPL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8.--9. "APB_DATA_WIDTH" "0,1,2,3"
bitfld.long 0x0 7. "WDT_PAUSE" "0,1"
newline
bitfld.long 0x0 6. "WDT_USE_FIX_TOP" "0,1"
bitfld.long 0x0 5. "WDT_HC_TOP" "0,1"
newline
bitfld.long 0x0 4. "WDT_HC_RPL" "0,1"
bitfld.long 0x0 3. "WDT_HC_RMOD" "0,1"
newline
bitfld.long 0x0 2. "WDT_DUAL_TOP" "0,1"
bitfld.long 0x0 1. "WDT_DFLT_RMOD" "0,1"
newline
bitfld.long 0x0 0. "WDT_ALWAYS_EN" "0,1"
line.long 0x4 "WDT_COMP_VERSION,Component Version Register"
hexmask.long 0x4 0.--31. 1. "wdt_comp_version,ASCII value for each number in the version  followed by *. For example "
line.long 0x8 "WDT_COMP_TYPE,Component Type Register"
hexmask.long 0x8 0.--31. 1. "wdt_comp_type,Component Type Register"
tree.end
tree "WATCHDOG_2"
base ad:0x10D00400
group.long 0x0++0x7
line.long 0x0 "WDT_CR,Control Register"
hexmask.long 0x0 5.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 2.--4. "RPL,Reset pulse length. Writes have no effect when the configuration parameter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1. "RMOD,Response mode. Writes have no effect when the parameter" "0: Generate a system reset,1: First generate an interrupt and if it is not.."
bitfld.long 0x0 0. "WDT_EN,When the configuration parameter WDT_ALWAYS_EN = 0  this bit can be set" "0: WDT disabled,1: WDT enabled"
line.long 0x4 "WDT_TORR,Timeout Range Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved,Reserved and read as 0."
hexmask.long.byte 0x4 4.--7. 1. "TOP_INIT,Timeout period for initialization."
newline
hexmask.long.byte 0x4 0.--3. 1. "TOP,Timeout period. Writes have no effect when the configuration parameter"
rgroup.long 0x8++0x3
line.long 0x0 "WDT_CCVR,Current Counter Value Register."
hexmask.long 0x0 0.--31. 1. "wdt_ccvr,This register  when read  is the current value of the internal"
wgroup.long 0xC++0x3
line.long 0x0 "WDT_CRR,Counter Restart Register."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "wdt_crr,This register is used to restart the WDT counter. As a safety feature to"
rgroup.long 0x10++0x7
line.long 0x0 "WDT_STAT,Interrupt Status Register."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "wdt_stat,This register shows the interrupt status of the WDT." "0: Interrupt is inactive,1: Interrupt is active regardless of polarity"
line.long 0x4 "WDT_EOI,Interrupt Clear Register."
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "wdt_eoi,Clears the watchdog interrupt. This can be used to clear the interrupt" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "WDT_COMP_PARAM_1,Component Parameters Register 1"
bitfld.long 0x0 29.--31. "RSVD_31_29" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 24.--28. 1. "WDT_CNT_WIDTH"
newline
hexmask.long.byte 0x0 20.--23. 1. "WDT_DFLT_TOP_INIT"
hexmask.long.byte 0x0 16.--19. 1. "WDT_DFLT_TOP"
newline
bitfld.long 0x0 13.--15. "RSVD_15_13" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 10.--12. "WDT_DFLT_RPL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8.--9. "APB_DATA_WIDTH" "0,1,2,3"
bitfld.long 0x0 7. "WDT_PAUSE" "0,1"
newline
bitfld.long 0x0 6. "WDT_USE_FIX_TOP" "0,1"
bitfld.long 0x0 5. "WDT_HC_TOP" "0,1"
newline
bitfld.long 0x0 4. "WDT_HC_RPL" "0,1"
bitfld.long 0x0 3. "WDT_HC_RMOD" "0,1"
newline
bitfld.long 0x0 2. "WDT_DUAL_TOP" "0,1"
bitfld.long 0x0 1. "WDT_DFLT_RMOD" "0,1"
newline
bitfld.long 0x0 0. "WDT_ALWAYS_EN" "0,1"
line.long 0x4 "WDT_COMP_VERSION,Component Version Register"
hexmask.long 0x4 0.--31. 1. "wdt_comp_version,ASCII value for each number in the version  followed by *. For example "
line.long 0x8 "WDT_COMP_TYPE,Component Type Register"
hexmask.long 0x8 0.--31. 1. "wdt_comp_type,Component Type Register"
tree.end
tree "WATCHDOG_3"
base ad:0x10D00500
group.long 0x0++0x7
line.long 0x0 "WDT_CR,Control Register"
hexmask.long 0x0 5.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 2.--4. "RPL,Reset pulse length. Writes have no effect when the configuration parameter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1. "RMOD,Response mode. Writes have no effect when the parameter" "0: Generate a system reset,1: First generate an interrupt and if it is not.."
bitfld.long 0x0 0. "WDT_EN,When the configuration parameter WDT_ALWAYS_EN = 0  this bit can be set" "0: WDT disabled,1: WDT enabled"
line.long 0x4 "WDT_TORR,Timeout Range Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved,Reserved and read as 0."
hexmask.long.byte 0x4 4.--7. 1. "TOP_INIT,Timeout period for initialization."
newline
hexmask.long.byte 0x4 0.--3. 1. "TOP,Timeout period. Writes have no effect when the configuration parameter"
rgroup.long 0x8++0x3
line.long 0x0 "WDT_CCVR,Current Counter Value Register."
hexmask.long 0x0 0.--31. 1. "wdt_ccvr,This register  when read  is the current value of the internal"
wgroup.long 0xC++0x3
line.long 0x0 "WDT_CRR,Counter Restart Register."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "wdt_crr,This register is used to restart the WDT counter. As a safety feature to"
rgroup.long 0x10++0x7
line.long 0x0 "WDT_STAT,Interrupt Status Register."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "wdt_stat,This register shows the interrupt status of the WDT." "0: Interrupt is inactive,1: Interrupt is active regardless of polarity"
line.long 0x4 "WDT_EOI,Interrupt Clear Register."
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "wdt_eoi,Clears the watchdog interrupt. This can be used to clear the interrupt" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "WDT_COMP_PARAM_1,Component Parameters Register 1"
bitfld.long 0x0 29.--31. "RSVD_31_29" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 24.--28. 1. "WDT_CNT_WIDTH"
newline
hexmask.long.byte 0x0 20.--23. 1. "WDT_DFLT_TOP_INIT"
hexmask.long.byte 0x0 16.--19. 1. "WDT_DFLT_TOP"
newline
bitfld.long 0x0 13.--15. "RSVD_15_13" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 10.--12. "WDT_DFLT_RPL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8.--9. "APB_DATA_WIDTH" "0,1,2,3"
bitfld.long 0x0 7. "WDT_PAUSE" "0,1"
newline
bitfld.long 0x0 6. "WDT_USE_FIX_TOP" "0,1"
bitfld.long 0x0 5. "WDT_HC_TOP" "0,1"
newline
bitfld.long 0x0 4. "WDT_HC_RPL" "0,1"
bitfld.long 0x0 3. "WDT_HC_RMOD" "0,1"
newline
bitfld.long 0x0 2. "WDT_DUAL_TOP" "0,1"
bitfld.long 0x0 1. "WDT_DFLT_RMOD" "0,1"
newline
bitfld.long 0x0 0. "WDT_ALWAYS_EN" "0,1"
line.long 0x4 "WDT_COMP_VERSION,Component Version Register"
hexmask.long 0x4 0.--31. 1. "wdt_comp_version,ASCII value for each number in the version  followed by *. For example "
line.long 0x8 "WDT_COMP_TYPE,Component Type Register"
hexmask.long 0x8 0.--31. 1. "wdt_comp_type,Component Type Register"
tree.end
tree "WATCHDOG_4"
base ad:0x10D00600
group.long 0x0++0x7
line.long 0x0 "WDT_CR,Control Register"
hexmask.long 0x0 5.--31. 1. "Reserved_3,Reserved bitfield added by Magillem"
bitfld.long 0x0 2.--4. "RPL,Reset pulse length. Writes have no effect when the configuration parameter" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 1. "RMOD,Response mode. Writes have no effect when the parameter" "0: Generate a system reset,1: First generate an interrupt and if it is not.."
bitfld.long 0x0 0. "WDT_EN,When the configuration parameter WDT_ALWAYS_EN = 0  this bit can be set" "0: WDT disabled,1: WDT enabled"
line.long 0x4 "WDT_TORR,Timeout Range Register"
hexmask.long.tbyte 0x4 8.--31. 1. "Reserved,Reserved and read as 0."
hexmask.long.byte 0x4 4.--7. 1. "TOP_INIT,Timeout period for initialization."
newline
hexmask.long.byte 0x4 0.--3. 1. "TOP,Timeout period. Writes have no effect when the configuration parameter"
rgroup.long 0x8++0x3
line.long 0x0 "WDT_CCVR,Current Counter Value Register."
hexmask.long 0x0 0.--31. 1. "wdt_ccvr,This register  when read  is the current value of the internal"
wgroup.long 0xC++0x3
line.long 0x0 "WDT_CRR,Counter Restart Register."
hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
hexmask.long.byte 0x0 0.--7. 1. "wdt_crr,This register is used to restart the WDT counter. As a safety feature to"
rgroup.long 0x10++0x7
line.long 0x0 "WDT_STAT,Interrupt Status Register."
hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x0 0. "wdt_stat,This register shows the interrupt status of the WDT." "0: Interrupt is inactive,1: Interrupt is active regardless of polarity"
line.long 0x4 "WDT_EOI,Interrupt Clear Register."
hexmask.long 0x4 1.--31. 1. "Reserved_1,Reserved bitfield added by Magillem"
bitfld.long 0x4 0. "wdt_eoi,Clears the watchdog interrupt. This can be used to clear the interrupt" "0,1"
rgroup.long 0xF4++0xB
line.long 0x0 "WDT_COMP_PARAM_1,Component Parameters Register 1"
bitfld.long 0x0 29.--31. "RSVD_31_29" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x0 24.--28. 1. "WDT_CNT_WIDTH"
newline
hexmask.long.byte 0x0 20.--23. 1. "WDT_DFLT_TOP_INIT"
hexmask.long.byte 0x0 16.--19. 1. "WDT_DFLT_TOP"
newline
bitfld.long 0x0 13.--15. "RSVD_15_13" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 10.--12. "WDT_DFLT_RPL" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 8.--9. "APB_DATA_WIDTH" "0,1,2,3"
bitfld.long 0x0 7. "WDT_PAUSE" "0,1"
newline
bitfld.long 0x0 6. "WDT_USE_FIX_TOP" "0,1"
bitfld.long 0x0 5. "WDT_HC_TOP" "0,1"
newline
bitfld.long 0x0 4. "WDT_HC_RPL" "0,1"
bitfld.long 0x0 3. "WDT_HC_RMOD" "0,1"
newline
bitfld.long 0x0 2. "WDT_DUAL_TOP" "0,1"
bitfld.long 0x0 1. "WDT_DFLT_RMOD" "0,1"
newline
bitfld.long 0x0 0. "WDT_ALWAYS_EN" "0,1"
line.long 0x4 "WDT_COMP_VERSION,Component Version Register"
hexmask.long 0x4 0.--31. 1. "wdt_comp_version,ASCII value for each number in the version  followed by *. For example "
line.long 0x8 "WDT_COMP_TYPE,Component Type Register"
hexmask.long 0x8 0.--31. 1. "wdt_comp_type,Component Type Register"
tree.end
tree.end
newline
AUTOINDENT.OFF