#! armclang --target=arm-arm-none-eabi -mcpu=cortex-r52 -E -x c /* * Linker script * * GENERATED FILE: DO NOT EDIT * Generated by C:/ADAS_PRK/LW/pcu-10a_mcu/source/boards/GRAY_HAWK_EVB_V1_MK\genld-ARM-Mk-armkeil.pl on 2026-03-04 16:48 */ /* TOOLDIAG List of possible tool diagnostics * * TOOLDIAG-1) Possible diagnostic: RemovedUnusedSection * Pattern only matches removed unused sections. * * Reason: Not all regions need to contain data variables. * * TOOLDIAG-2) Possible diagnostic: UnusedSection * No section matches pattern . * * Reason: Config specific auto-generated sections which sometimes are empty. */ /* Possible diagnostic TOOLDIAG-1 <*> */ /* Possible diagnostic TOOLDIAG-2 <*> */ /* TOOLDIAG List of possible tool diagnostics * * TOOLDIAG-1) Possible diagnostic: RemovedUnusedSection * Pattern only matches removed unused sections. * * Reason: Not all regions need to contain data variables. * * TOOLDIAG-2) Possible diagnostic: UnusedSection * No section matches pattern . * * Reason: Config specific auto-generated sections which sometimes are empty. */ /* Possible diagnostic TOOLDIAG-1 <*> */ /* Possible diagnostic TOOLDIAG-2 <*> */ #define exctable_addr 0xE2100000 #define exctable_size 0x00001000 #define reset_addr 0xE2101000 #define reset_size 0x00000200 #define RAM_start_addr 0xE2540000 #define RAM_size 0x01000000 #define ROM_start_addr 0xE2101200 #define ROM_size 0x00400000 #define GPIO_start_addr 0xe6061800 #define GPIO_end_addr 0xe6061a00 #define rom_sect_addr exctable_addr #define rom_addr ROM_start_addr #define rom_size ROM_size ;#define rom_data_addr RAM_start_addr ;#define rom_data_size RAM_size ;#define ram_addr ImageLimit(ROM_DATA_END) ;#define ram_size ((RAM_start_addr + RAM_size) - ram_addr) ;#define cx_ram_size (RAM_size/4) /*==========================================================================*/ /*CUSTOM: R52 core ram size*/ #define cx_ram_size 0x00100000 /*==========================================================================*/ #define ram_C0_START RAM_start_addr /*==========================================================================*/ /*CUSTOM: R52 core ram size*/ #define ram_C0_addr RAM_start_addr /*==========================================================================*/ #define ram_C0_size cx_ram_size #define ram_C1_START (ram_C0_addr + cx_ram_size) /*==========================================================================*/ /*CUSTOM: R52 core ram size*/ #define ram_C1_addr (ram_C0_addr + cx_ram_size) /*==========================================================================*/ #define ram_C1_size cx_ram_size #define ram_C2_START (ram_C1_addr + cx_ram_size) /*==========================================================================*/ /*CUSTOM: R52 core ram size*/ #define ram_C2_addr (ram_C1_addr + cx_ram_size) /*==========================================================================*/ #define ram_C2_size cx_ram_size /*==========================================================================*/ /*CUSTOM: R52 shared memory between cores*/ #define ram_SHARED_addr (ram_C2_addr + cx_ram_size) /* = 0xE2540000 */ #define ram_SHARED_size 0x00001000 /*==========================================================================*/ /* IOC readable region */ #define BOARD_C0_RAM_BEG ram_C0_addr #define BOARD_C0_URAM_END (ram_C0_addr + cx_ram_size) #define BOARD_C1_RAM_BEG ram_C1_addr #define BOARD_C1_URAM_END (ram_C1_addr + cx_ram_size) #define BOARD_C2_RAM_BEG ram_C2_addr #define BOARD_C2_URAM_END (ram_C2_addr + cx_ram_size) /*=================================================*/ /* definition of global HW specific symbols */ GLOBAL_HW_SPECIFIC_SYMBOLS 0 { ; MK: core local GIC IO registers MK_RSA_MK_Io0 0xf0000000 EMPTY 0 { } MK_RLA_MK_Io0 0xf0200000 EMPTY 0 { } ; MK: TMU1 memory-mapped device registers MK_RSA_MK_Io1 0xe6fc0000 EMPTY 0 { } MK_RLA_MK_Io1 0xe6fc1000 EMPTY 0 { } ; MK: TMU2 memory-mapped device registers MK_RSA_MK_Io2 0xe6fd0000 EMPTY 0 { } MK_RLA_MK_Io2 0xe6fd1000 EMPTY 0 { } ; MK: TMU3 memory-mapped device registers MK_RSA_MK_Io3 0xe6fe0000 EMPTY 0 { } MK_RLA_MK_Io3 0xe6fe1000 EMPTY 0 { } ; MK: TMU4 memory-mapped device registers MK_RSA_MK_Io4 0xffc00000 EMPTY 0 { } MK_RLA_MK_Io4 0xffc10000 EMPTY 0 { } ; MK: MFIS multifunctional interface MK_RSA_MK_Io5 0xe6269400 EMPTY 0 { } MK_RLA_MK_Io5 0xe626a500 EMPTY 0 { } ; counter subsystem: TMU0 memory-mapped device registers MK_RSA_MK_OsIo0 0xe61e0000 EMPTY 0 { } MK_RLA_MK_OsIo0 0xe61f0000 EMPTY 0 { } ; counter subsystem: TMU1 memory-mapped device registers MK_RSA_MK_OsIo1 0xe6fc0000 EMPTY 0 { } MK_RLA_MK_OsIo1 0xe6fc1000 EMPTY 0 { } ; counter subsystem: TMU2 memory-mapped device registers MK_RSA_MK_OsIo2 0xe6fd0000 EMPTY 0 { } MK_RLA_MK_OsIo2 0xe6fd1000 EMPTY 0 { } ; counter subsystem: TMU3 memory-mapped device registers MK_RSA_MK_OsIo3 0xe6fe0000 EMPTY 0 { } MK_RLA_MK_OsIo3 0xe6fe1000 EMPTY 0 { } ; counter subsystem: TMU4 memory-mapped device registers MK_RSA_MK_OsIo4 0xffc00000 EMPTY 0 { } MK_RLA_MK_OsIo4 0xffc10000 EMPTY 0 { } } /*==========================================================================*/ /* CUSTOM: R52 shared memory between cores*/ ram_SHARED ram_SHARED_addr ram_SHARED_size { mk_shared_sync +0 ALIGN 256 FIXED { *(.mk_shared_sync) *(.mk_shared_sync.*) } } /*==========================================================================*/ exctable exctable_addr exctable_size { ; Output section MK_RamExctable (Type RESET) MK_RamExctable +0 ALIGN 256 FIXED { *(.mk_exceptiontable) *(.mk_exceptiontable.*) } MK_RLA_MK_RamExctable +0 ALIGN 256 EMPTY FIXED 0 { } } reset reset_addr reset_size { ; Output section mk_reset (Type RESET) mk_reset +0 ALIGN 256 FIXED { *(.mk_reset) *(.mk_reset.*) } MK_RLA_MK_Reset +0 ALIGN 256 EMPTY FIXED 0 { } } rom rom_addr rom_size { ; Output section text (Type TEXT) __GLBL_TEXT_START +0 ALIGN 256 EMPTY FIXED 0 { } text +0 ALIGN 256 FIXED { *(.text) *(.text.*) *(.mk_text) *(.mk_text.*) *(.os_text) *(.os_text.*) *(.rdata) *(.rdata.*) *(.ARM.use_no_argv) *(.ARM.use_no_argv.*) *(i.*) *(i.*.*) *(t.*) *(t.*.*) *(x$fpl*) *(x$fpl*.*) } __GLBL_TEXT_END +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section rodata (Type RODATA) __GLBL_RODATA_START +0 ALIGN 256 EMPTY FIXED 0 { } rodata +0 ALIGN 256 FIXED { *(.rodata) *(.rodata.*) *(.zrodata) *(.zrodata.*) *(.ldata) *(.ldata.*) *(.constdata) *(.constdata.*) *(.ARM.extab) *(.ARM.extab.*) *(.ARM.exidx) *(.ARM.exidx.*) } __GLBL_RODATA_END +0 ALIGN 256 EMPTY FIXED 0 { } } ram_C0 ram_C0_addr ram_C0_size { ; -------------------------------------------------------- ; Memory regions for the MK and counter subsystem data on core 0 ; -------------------------------------------------------- MK_RSA_ram_C0 ram_C0_addr ALIGN 256 EMPTY FIXED 0 { } ; Output section MK_Ram_data_C0 (Type DATA) MK_RDA_MK_Ram_C0 +0 ALIGN 8192 EMPTY FIXED 0 { } MK_RSA_MK_Ram_C0 +0 ALIGN 8192 EMPTY FIXED 0 { } MK_Ram_data_C0 +0 ALIGN 8192 FIXED { Mk_c0_*(.data) Mk_c0_*(.data.*) Mk_c0_*(.zdata) Mk_c0_*(.zdata.*) Mk_c0_*(.sdata) Mk_c0_*(.sdata.*) Ioc_data_kern_c0_*(.data) Ioc_data_kern_c0_*(.data.*) Ioc_data_kern_c0_*(.zdata) Ioc_data_kern_c0_*(.zdata.*) Ioc_data_kern_c0_*(.sdata) Ioc_data_kern_c0_*(.sdata.*) } ; Output section MK_Ram_bss_C0 (Type DATA_BSS) MK_BSA_MK_Ram_C0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_Ram_bss_C0 +0 ALIGN 256 UNINIT FIXED { Mk_c0_*(.bss) Mk_c0_*(.bss.*) Mk_c0_*(.zbss) Mk_c0_*(.zbss.*) Mk_c0_*(.sbss) Mk_c0_*(.sbss.*) Ioc_data_kern_c0_*(.bss) Ioc_data_kern_c0_*(.bss.*) Ioc_data_kern_c0_*(.zbss) Ioc_data_kern_c0_*(.zbss.*) Ioc_data_kern_c0_*(.sbss) Ioc_data_kern_c0_*(.sbss.*) } MK_RLA_MK_Ram_C0 +0 ALIGN 8192 EMPTY FIXED 0 { } ; Output section MK_OsRam_data_C0 (Type DATA) MK_RDA_MK_OsRam_C0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_MK_OsRam_C0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_OsRam_data_C0 +0 ALIGN 256 FIXED { kern-*(.data.core0) kern-*(.data.core0.*) kern-*(.data.shared.core0) kern-*(.data.shared.core0.*) ARM-*(.data.core0) ARM-*(.data.core0.*) ARM-*(.data.shared.core0) ARM-*(.data.shared.core0.*) Os_*(.data.core0) Os_*(.data.core0.*) Os_*(.data.shared.core0) Os_*(.data.shared.core0.*) } ; Output section MK_OsRam_bss_C0 (Type DATA_BSS) MK_BSA_MK_OsRam_C0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_OsRam_bss_C0 +0 ALIGN 256 UNINIT FIXED { kern-*(.bss.core0) kern-*(.bss.core0.*) kern-*(.bss.shared.core0) kern-*(.bss.shared.core0.*) ARM-*(.bss.core0) ARM-*(.bss.core0.*) ARM-*(.bss.shared.core0) ARM-*(.bss.shared.core0.*) Os_*(.bss.core0) Os_*(.bss.core0.*) Os_*(.bss.shared.core0) Os_*(.bss.shared.core0.*) } MK_RLA_MK_OsRam_C0 +0 ALIGN 256 EMPTY FIXED 0 { } ; MPU cache on core 0 MK_BSA_MK_c0_mpuCache +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section .mk_c0_mpu_cache (Type BSS) MK_RSA_MK_c0_mpuCache +0 ALIGN 256 EMPTY FIXED 0 { } .mk_c0_mpu_cache +0 ALIGN 256 UNINIT FIXED { Mk_ARM_*configuration.o(.bss.mk_c0_mpuCache) Mk_ARM_*configuration.o(.bss.mk_c0_mpuCache.*) } MK_RLA_MK_c0_mpuCache +0 ALIGN 256 EMPTY FIXED 0 { } ; Stacks on core 0 MK_RSA_MK_mk_stack_MK_c0_kernelStack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c0_kernelStack (Type STACK) MK_RSA_MK_c0_kernelStack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c0_kernelStack +0 ALIGN 512 FIXED { Mk_c0_kernel_stack.o(.bss) Mk_c0_kernel_stack.o(.bss.*) Mk_c0_kernel_stack.o(.zbss) Mk_c0_kernel_stack.o(.zbss.*) Mk_c0_kernel_stack.o(.sbss) Mk_c0_kernel_stack.o(.sbss.*) } MK_RLA_MK_c0_kernelStack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c0_aux1Stack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c0_aux1Stack (Type STACK) MK_RSA_MK_c0_aux1Stack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c0_aux1Stack +0 ALIGN 512 FIXED { Mk_c0_aux1_stack.o(.bss) Mk_c0_aux1_stack.o(.bss.*) Mk_c0_aux1_stack.o(.zbss) Mk_c0_aux1_stack.o(.zbss.*) Mk_c0_aux1_stack.o(.sbss) Mk_c0_aux1_stack.o(.sbss.*) } MK_RLA_MK_c0_aux1Stack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c0_aux2Stack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c0_aux2Stack (Type STACK) MK_RSA_MK_c0_aux2Stack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c0_aux2Stack +0 ALIGN 512 FIXED { Mk_c0_aux2_stack.o(.bss) Mk_c0_aux2_stack.o(.bss.*) Mk_c0_aux2_stack.o(.zbss) Mk_c0_aux2_stack.o(.zbss.*) Mk_c0_aux2_stack.o(.sbss) Mk_c0_aux2_stack.o(.sbss.*) } MK_RLA_MK_c0_aux2Stack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c0_idleshutdownStack +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c0_idleshutdownStack (Type STACK) MK_RSA_MK_c0_idleshutdownStack +0 ALIGN 256 EMPTY FIXED 0 { } mk_stack_MK_c0_idleshutdownStack +0 ALIGN 256 FIXED { Mk_c0_idleshutdown_stack.o(.bss) Mk_c0_idleshutdown_stack.o(.bss.*) Mk_c0_idleshutdown_stack.o(.zbss) Mk_c0_idleshutdown_stack.o(.zbss.*) Mk_c0_idleshutdown_stack.o(.sbss) Mk_c0_idleshutdown_stack.o(.sbss.*) } MK_RLA_MK_c0_idleshutdownStack +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c0_errorhookStack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c0_errorhookStack (Type STACK) MK_RSA_MK_c0_errorhookStack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c0_errorhookStack +0 ALIGN 512 FIXED { Mk_c0_errorhook_stack.o(.bss) Mk_c0_errorhook_stack.o(.bss.*) Mk_c0_errorhook_stack.o(.zbss) Mk_c0_errorhook_stack.o(.zbss.*) Mk_c0_errorhook_stack.o(.sbss) Mk_c0_errorhook_stack.o(.sbss.*) } MK_RLA_MK_c0_errorhookStack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c0_protectionHookStack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c0_protectionHookStack (Type STACK) MK_RSA_MK_c0_protectionHookStack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c0_protectionHookStack +0 ALIGN 512 FIXED { Mk_c0_protectionhook_stack.o(.bss) Mk_c0_protectionhook_stack.o(.bss.*) Mk_c0_protectionhook_stack.o(.zbss) Mk_c0_protectionhook_stack.o(.zbss.*) Mk_c0_protectionhook_stack.o(.sbss) Mk_c0_protectionhook_stack.o(.sbss.*) } MK_RLA_MK_c0_protectionHookStack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot0 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot0 (Type STACK) MK_threadStack0_slot0 +0 ALIGN 4096 FIXED { *.o(.bss.core0.mk_threadstack0_slot0) *.o(.bss.core0.mk_threadstack0_slot0.*) } MK_RLA_MK_threadStack0_slot0 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot1 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot1 (Type STACK) MK_threadStack0_slot1 +0 ALIGN 4096 FIXED { *.o(.bss.core0.mk_threadstack0_slot1) *.o(.bss.core0.mk_threadstack0_slot1.*) } MK_RLA_MK_threadStack0_slot1 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot2 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot2 (Type STACK) MK_threadStack0_slot2 +0 ALIGN 4096 FIXED { *.o(.bss.core0.mk_threadstack0_slot2) *.o(.bss.core0.mk_threadstack0_slot2.*) } MK_RLA_MK_threadStack0_slot2 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot3 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot3 (Type STACK) MK_threadStack0_slot3 +0 ALIGN 4096 FIXED { *.o(.bss.core0.mk_threadstack0_slot3) *.o(.bss.core0.mk_threadstack0_slot3.*) } MK_RLA_MK_threadStack0_slot3 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot4 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot4 (Type STACK) MK_threadStack0_slot4 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot4) *.o(.bss.core0.mk_threadstack0_slot4.*) } MK_RLA_MK_threadStack0_slot4 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot5 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot5 (Type STACK) MK_threadStack0_slot5 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot5) *.o(.bss.core0.mk_threadstack0_slot5.*) } MK_RLA_MK_threadStack0_slot5 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot6 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot6 (Type STACK) MK_threadStack0_slot6 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot6) *.o(.bss.core0.mk_threadstack0_slot6.*) } MK_RLA_MK_threadStack0_slot6 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot7 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot7 (Type STACK) MK_threadStack0_slot7 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot7) *.o(.bss.core0.mk_threadstack0_slot7.*) } MK_RLA_MK_threadStack0_slot7 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot8 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot8 (Type STACK) MK_threadStack0_slot8 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot8) *.o(.bss.core0.mk_threadstack0_slot8.*) } MK_RLA_MK_threadStack0_slot8 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot9 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot9 (Type STACK) MK_threadStack0_slot9 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot9) *.o(.bss.core0.mk_threadstack0_slot9.*) } MK_RLA_MK_threadStack0_slot9 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot10 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot10 (Type STACK) MK_threadStack0_slot10 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot10) *.o(.bss.core0.mk_threadstack0_slot10.*) } MK_RLA_MK_threadStack0_slot10 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot11 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot11 (Type STACK) MK_threadStack0_slot11 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot11) *.o(.bss.core0.mk_threadstack0_slot11.*) } MK_RLA_MK_threadStack0_slot11 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot12 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot12 (Type STACK) MK_threadStack0_slot12 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot12) *.o(.bss.core0.mk_threadstack0_slot12.*) } MK_RLA_MK_threadStack0_slot12 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot13 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot13 (Type STACK) MK_threadStack0_slot13 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot13) *.o(.bss.core0.mk_threadstack0_slot13.*) } MK_RLA_MK_threadStack0_slot13 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot14 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot14 (Type STACK) MK_threadStack0_slot14 +0 ALIGN 2048 FIXED { *.o(.bss.core0.mk_threadstack0_slot14) *.o(.bss.core0.mk_threadstack0_slot14.*) } MK_RLA_MK_threadStack0_slot14 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack0_slot15 +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section MK_threadStack0_slot15 (Type STACK) MK_threadStack0_slot15 +0 ALIGN 512 FIXED { *.o(.bss.core0.mk_threadstack0_slot15) *.o(.bss.core0.mk_threadstack0_slot15.*) } MK_RLA_MK_threadStack0_slot15 +0 ALIGN 512 EMPTY FIXED 0 { } ; --------------------------------------------------------- ; Private memory regions of the application on core 0 ; --------------------------------------------------------- ; Output section OsApplication_0_data (Type DATA) MK_RDA_OsApplication_0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_OsApplication_0 +0 ALIGN 256 EMPTY FIXED 0 { } OsApplication_0_data +0 ALIGN 256 FIXED { OsApplication_0_gen.o(.data) OsApplication_0_gen.o(.data.*) OsApplication_0_gen.o(.zdata) OsApplication_0_gen.o(.zdata.*) OsApplication_0_gen.o(.sdata) OsApplication_0_gen.o(.sdata.*) } ; Output section OsApplication_0_bss (Type DATA_BSS) MK_BSA_OsApplication_0 +0 ALIGN 256 EMPTY FIXED 0 { } OsApplication_0_bss +0 ALIGN 256 UNINIT FIXED { OsApplication_0_gen.o(.bss) OsApplication_0_gen.o(.bss.*) OsApplication_0_gen.o(.zbss) OsApplication_0_gen.o(.zbss.*) OsApplication_0_gen.o(.sbss) OsApplication_0_gen.o(.sbss.*) } MK_RLA_OsApplication_0 +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_BSW_Init_Core0 --- NO FILES MK_RSA_OsTask_BSW_Init_Core0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_BSW_Init_Core0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_BSW_Init_Core0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_BSW_Init_Core0 +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_BswSE_BSW_FG1_5ms_com --- NO FILES MK_RSA_OsTask_BswSE_BSW_FG1_5ms_com +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_BswSE_BSW_FG1_5ms_com +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_BswSE_BSW_FG1_5ms_com +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_BswSE_BSW_FG1_5ms_com +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_BswSE_BSW_FG1_10ms --- NO FILES MK_RSA_OsTask_BswSE_BSW_FG1_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_BswSE_BSW_FG1_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_BswSE_BSW_FG1_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_BswSE_BSW_FG1_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtComASILD_RX_5ms --- NO FILES MK_RSA_OsTask_ASW_RCtComASILD_RX_5ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtComASILD_RX_5ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtComASILD_RX_5ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtComASILD_RX_5ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtComASILD_TX_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtComASILD_TX_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtComASILD_TX_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtComASILD_TX_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtComASILD_TX_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtComQM_RX_5ms --- NO FILES MK_RSA_OsTask_ASW_RCtComQM_RX_5ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtComQM_RX_5ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtComQM_RX_5ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtComQM_RX_5ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtComQM_TX_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtComQM_TX_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtComQM_TX_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtComQM_TX_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtComQM_TX_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApHWIOP_P_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApHWIOP_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApHWIOP_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApHWIOP_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApHWIOP_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_Init_Core0 --- NO FILES MK_RSA_OsTask_ASW_Init_Core0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_Init_Core0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_Init_Core0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_Init_Core0 +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtCdICCOM_Rx_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtCdICCOM_Rx_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtCdICCOM_Rx_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtCdICCOM_Rx_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtCdICCOM_Rx_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtCdICCOM_Tx_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtCdICCOM_Tx_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtCdICCOM_Tx_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtCdICCOM_Tx_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtCdICCOM_Tx_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_BSW_Mem_Process_10ms --- NO FILES MK_RSA_OsTask_BSW_Mem_Process_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_BSW_Mem_Process_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_BSW_Mem_Process_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_BSW_Mem_Process_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApDCM_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApDCM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApDCM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApDCM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApDCM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Isr MFIS_xIICR0_CAT2_ISR --- NO FILES MK_RSA_MFIS_xIICR0_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_MFIS_xIICR0_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_MFIS_xIICR0_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_MFIS_xIICR0_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } ; Isr MFIS_xIICR1_CAT2_ISR --- NO FILES MK_RSA_MFIS_xIICR1_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_MFIS_xIICR1_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_MFIS_xIICR1_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_MFIS_xIICR1_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } ; Isr MFIS_xIICR2_CAT2_ISR --- NO FILES MK_RSA_MFIS_xIICR2_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_MFIS_xIICR2_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_MFIS_xIICR2_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_MFIS_xIICR2_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } ; Isr SPI_MSIOF1_CAT2_ISR --- NO FILES MK_RSA_SPI_MSIOF1_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_SPI_MSIOF1_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_SPI_MSIOF1_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_SPI_MSIOF1_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section OS_SYSTEM_0_data (Type DATA) MK_RDA_OS_SYSTEM_0 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_OS_SYSTEM_0 +0 ALIGN 256 EMPTY FIXED 0 { } OS_SYSTEM_0_data +0 ALIGN 256 FIXED { OS_SYSTEM_0_gen.o(.data) OS_SYSTEM_0_gen.o(.data.*) OS_SYSTEM_0_gen.o(.zdata) OS_SYSTEM_0_gen.o(.zdata.*) OS_SYSTEM_0_gen.o(.sdata) OS_SYSTEM_0_gen.o(.sdata.*) } ; Output section OS_SYSTEM_0_bss (Type DATA_BSS) MK_BSA_OS_SYSTEM_0 +0 ALIGN 256 EMPTY FIXED 0 { } OS_SYSTEM_0_bss +0 ALIGN 256 UNINIT FIXED { OS_SYSTEM_0_gen.o(.bss) OS_SYSTEM_0_gen.o(.bss.*) OS_SYSTEM_0_gen.o(.zbss) OS_SYSTEM_0_gen.o(.zbss.*) OS_SYSTEM_0_gen.o(.sbss) OS_SYSTEM_0_gen.o(.sbss.*) } MK_RLA_OS_SYSTEM_0 +0 ALIGN 256 EMPTY FIXED 0 { } ; -------------------------------------------------------------------------------- ; Board data that shall be global, but not mapped into the regions of the ; microkernel. For example, on S32V234AA32 this is used for the bootup page table. ; -------------------------------------------------------------------------------- ; Output section MK_Board_data (Type DATA) MK_RSA_MK_Board_anon +0 ALIGN 256 EMPTY FIXED 0 { } MK_Board_data +0 ALIGN 256 FIXED { Mk_board_anon.o(.data) Mk_board_anon.o(.data.*) Mk_board_anon.o(.zdata) Mk_board_anon.o(.zdata.*) Mk_board_anon.o(.sdata) Mk_board_anon.o(.sdata.*) } ; Output section MK_Board_bss (Type BSS) MK_BSA_MK_Board_anon +0 ALIGN 256 EMPTY FIXED 0 { } MK_Board_bss +0 ALIGN 256 UNINIT FIXED { Mk_board_anon.o(.bss) Mk_board_anon.o(.bss.*) Mk_board_anon.o(.zbss) Mk_board_anon.o(.zbss.*) Mk_board_anon.o(.sbss) Mk_board_anon.o(.sbss.*) } MK_RLA_MK_Board_anon +0 ALIGN 256 EMPTY FIXED 0 { } ; -------------------------------------------------------- ; Memory regions for the MK and counter subsystem data (core spanning) ; -------------------------------------------------------- ; Output section MK_Ram_data (Type DATA) MK_RDA_MK_Ram +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_MK_Ram +0 ALIGN 256 EMPTY FIXED 0 { } MK_Ram_data +0 ALIGN 256 FIXED { Mk_*(.data) Mk_*(.data.*) Mk_*(.zdata) Mk_*(.zdata.*) Mk_*(.sdata) Mk_*(.sdata.*) Ioc_data_kern_shared*(.data) Ioc_data_kern_shared*(.data.*) Ioc_data_kern_shared*(.zdata) Ioc_data_kern_shared*(.zdata.*) Ioc_data_kern_shared*(.sdata) Ioc_data_kern_shared*(.sdata.*) } ; Output section MK_Ram_bss (Type BSS) MK_BSA_MK_Ram +0 ALIGN 256 EMPTY FIXED 0 { } MK_Ram_bss +0 ALIGN 256 UNINIT FIXED { Mk_*(.bss) Mk_*(.bss.*) Mk_*(.zbss) Mk_*(.zbss.*) Mk_*(.sbss) Mk_*(.sbss.*) Ioc_data_kern_shared*(.bss) Ioc_data_kern_shared*(.bss.*) Ioc_data_kern_shared*(.zbss) Ioc_data_kern_shared*(.zbss.*) Ioc_data_kern_shared*(.sbss) Ioc_data_kern_shared*(.sbss.*) } MK_RLA_MK_Ram +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section MK_OsRam_data (Type DATA) MK_RDA_MK_OsRam +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_MK_OsRam +0 ALIGN 256 EMPTY FIXED 0 { } MK_OsRam_data +0 ALIGN 256 FIXED { kern-*(.data.OS*) kern-*(.data.OS*.*) ARM-*(.data.OS*) ARM-*(.data.OS*.*) Os_*(.data.OS*) Os_*(.data.OS*.*) } ; Output section MK_OsRam_bss (Type BSS) MK_BSA_MK_OsRam +0 ALIGN 256 EMPTY FIXED 0 { } MK_OsRam_bss +0 ALIGN 256 UNINIT FIXED { kern-*(.bss.OS*) kern-*(.bss.OS*.*) ARM-*(.bss.OS*) ARM-*(.bss.OS*.*) Os_*(.bss.OS*) Os_*(.bss.OS*.*) } MK_RLA_MK_OsRam +0 ALIGN 256 EMPTY FIXED 0 { } ; ----------------------------------------------------- ; Anonymous catch-all sections for everything remaining ; ----------------------------------------------------- ; Output section data_MK_ANON (Type DATA) MK_ANON_IDAT +0 ALIGN 256 EMPTY FIXED 0 { } MK_ANON_DATA +0 ALIGN 256 EMPTY FIXED 0 { } data_MK_ANON +0 ALIGN 256 FIXED { *(.data) *(.data.*) *(.zdata) *(.zdata.*) *(.sdata) *(.sdata.*) } MK_ANON_DATA_END +0 EMPTY FIXED 0 { } ; Output section bss_MK_ANON (Type DATA_BSS) MK_ANON_BSS +0 ALIGN 256 EMPTY FIXED 0 { } bss_MK_ANON +0 ALIGN 256 UNINIT FIXED { *(.bss) *(.bss.*) *(.zbss) *(.zbss.*) *(.sbss) *(.sbss.*) } MK_ANON_BSS_END +0 EMPTY FIXED 0 { } } ram_C1 ram_C1_addr ram_C1_size { ; -------------------------------------------------------- ; Memory regions for the MK and counter subsystem data on core 1 ; -------------------------------------------------------- MK_RSA_ram_C1 ram_C1_addr ALIGN 256 EMPTY FIXED 0 { } ; Output section MK_Ram_data_C1 (Type DATA) MK_RDA_MK_Ram_C1 +0 ALIGN 8192 EMPTY FIXED 0 { } MK_RSA_MK_Ram_C1 +0 ALIGN 8192 EMPTY FIXED 0 { } MK_Ram_data_C1 +0 ALIGN 8192 FIXED { Mk_c1_*(.data) Mk_c1_*(.data.*) Mk_c1_*(.zdata) Mk_c1_*(.zdata.*) Mk_c1_*(.sdata) Mk_c1_*(.sdata.*) Ioc_data_kern_c1_*(.data) Ioc_data_kern_c1_*(.data.*) Ioc_data_kern_c1_*(.zdata) Ioc_data_kern_c1_*(.zdata.*) Ioc_data_kern_c1_*(.sdata) Ioc_data_kern_c1_*(.sdata.*) } ; Output section MK_Ram_bss_C1 (Type DATA_BSS) MK_BSA_MK_Ram_C1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_Ram_bss_C1 +0 ALIGN 256 UNINIT FIXED { Mk_c1_*(.bss) Mk_c1_*(.bss.*) Mk_c1_*(.zbss) Mk_c1_*(.zbss.*) Mk_c1_*(.sbss) Mk_c1_*(.sbss.*) Ioc_data_kern_c1_*(.bss) Ioc_data_kern_c1_*(.bss.*) Ioc_data_kern_c1_*(.zbss) Ioc_data_kern_c1_*(.zbss.*) Ioc_data_kern_c1_*(.sbss) Ioc_data_kern_c1_*(.sbss.*) } MK_RLA_MK_Ram_C1 +0 ALIGN 8192 EMPTY FIXED 0 { } ; Output section MK_OsRam_data_C1 (Type DATA) MK_RDA_MK_OsRam_C1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_MK_OsRam_C1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_OsRam_data_C1 +0 ALIGN 256 FIXED { kern-*(.data.core1) kern-*(.data.core1.*) kern-*(.data.shared.core1) kern-*(.data.shared.core1.*) ARM-*(.data.core1) ARM-*(.data.core1.*) ARM-*(.data.shared.core1) ARM-*(.data.shared.core1.*) Os_*(.data.core1) Os_*(.data.core1.*) Os_*(.data.shared.core1) Os_*(.data.shared.core1.*) } ; Output section MK_OsRam_bss_C1 (Type DATA_BSS) MK_BSA_MK_OsRam_C1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_OsRam_bss_C1 +0 ALIGN 256 UNINIT FIXED { kern-*(.bss.core1) kern-*(.bss.core1.*) kern-*(.bss.shared.core1) kern-*(.bss.shared.core1.*) ARM-*(.bss.core1) ARM-*(.bss.core1.*) ARM-*(.bss.shared.core1) ARM-*(.bss.shared.core1.*) Os_*(.bss.core1) Os_*(.bss.core1.*) Os_*(.bss.shared.core1) Os_*(.bss.shared.core1.*) } MK_RLA_MK_OsRam_C1 +0 ALIGN 256 EMPTY FIXED 0 { } ; MPU cache on core 1 MK_BSA_MK_c1_mpuCache +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section .mk_c1_mpu_cache (Type BSS) MK_RSA_MK_c1_mpuCache +0 ALIGN 256 EMPTY FIXED 0 { } .mk_c1_mpu_cache +0 ALIGN 256 UNINIT FIXED { Mk_ARM_*configuration.o(.bss.mk_c1_mpuCache) Mk_ARM_*configuration.o(.bss.mk_c1_mpuCache.*) } MK_RLA_MK_c1_mpuCache +0 ALIGN 256 EMPTY FIXED 0 { } ; Stacks on core 1 MK_RSA_MK_mk_stack_MK_c1_kernelStack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c1_kernelStack (Type STACK) MK_RSA_MK_c1_kernelStack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c1_kernelStack +0 ALIGN 512 FIXED { Mk_c1_kernel_stack.o(.bss) Mk_c1_kernel_stack.o(.bss.*) Mk_c1_kernel_stack.o(.zbss) Mk_c1_kernel_stack.o(.zbss.*) Mk_c1_kernel_stack.o(.sbss) Mk_c1_kernel_stack.o(.sbss.*) } MK_RLA_MK_c1_kernelStack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c1_aux1Stack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c1_aux1Stack (Type STACK) MK_RSA_MK_c1_aux1Stack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c1_aux1Stack +0 ALIGN 512 FIXED { Mk_c1_aux1_stack.o(.bss) Mk_c1_aux1_stack.o(.bss.*) Mk_c1_aux1_stack.o(.zbss) Mk_c1_aux1_stack.o(.zbss.*) Mk_c1_aux1_stack.o(.sbss) Mk_c1_aux1_stack.o(.sbss.*) } MK_RLA_MK_c1_aux1Stack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c1_aux2Stack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c1_aux2Stack (Type STACK) MK_RSA_MK_c1_aux2Stack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c1_aux2Stack +0 ALIGN 512 FIXED { Mk_c1_aux2_stack.o(.bss) Mk_c1_aux2_stack.o(.bss.*) Mk_c1_aux2_stack.o(.zbss) Mk_c1_aux2_stack.o(.zbss.*) Mk_c1_aux2_stack.o(.sbss) Mk_c1_aux2_stack.o(.sbss.*) } MK_RLA_MK_c1_aux2Stack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c1_idleshutdownStack +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c1_idleshutdownStack (Type STACK) MK_RSA_MK_c1_idleshutdownStack +0 ALIGN 256 EMPTY FIXED 0 { } mk_stack_MK_c1_idleshutdownStack +0 ALIGN 256 FIXED { Mk_c1_idleshutdown_stack.o(.bss) Mk_c1_idleshutdown_stack.o(.bss.*) Mk_c1_idleshutdown_stack.o(.zbss) Mk_c1_idleshutdown_stack.o(.zbss.*) Mk_c1_idleshutdown_stack.o(.sbss) Mk_c1_idleshutdown_stack.o(.sbss.*) } MK_RLA_MK_c1_idleshutdownStack +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c1_errorhookStack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c1_errorhookStack (Type STACK) MK_RSA_MK_c1_errorhookStack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c1_errorhookStack +0 ALIGN 512 FIXED { Mk_c1_errorhook_stack.o(.bss) Mk_c1_errorhook_stack.o(.bss.*) Mk_c1_errorhook_stack.o(.zbss) Mk_c1_errorhook_stack.o(.zbss.*) Mk_c1_errorhook_stack.o(.sbss) Mk_c1_errorhook_stack.o(.sbss.*) } MK_RLA_MK_c1_errorhookStack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c1_protectionHookStack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c1_protectionHookStack (Type STACK) MK_RSA_MK_c1_protectionHookStack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c1_protectionHookStack +0 ALIGN 512 FIXED { Mk_c1_protectionhook_stack.o(.bss) Mk_c1_protectionhook_stack.o(.bss.*) Mk_c1_protectionhook_stack.o(.zbss) Mk_c1_protectionhook_stack.o(.zbss.*) Mk_c1_protectionhook_stack.o(.sbss) Mk_c1_protectionhook_stack.o(.sbss.*) } MK_RLA_MK_c1_protectionHookStack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_threadStack1_slot0 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack1_slot0 (Type STACK) MK_threadStack1_slot0 +0 ALIGN 4096 FIXED { *.o(.bss.core1.mk_threadstack1_slot0) *.o(.bss.core1.mk_threadstack1_slot0.*) } MK_RLA_MK_threadStack1_slot0 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack1_slot1 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack1_slot1 (Type STACK) MK_threadStack1_slot1 +0 ALIGN 4096 FIXED { *.o(.bss.core1.mk_threadstack1_slot1) *.o(.bss.core1.mk_threadstack1_slot1.*) } MK_RLA_MK_threadStack1_slot1 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack1_slot2 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack1_slot2 (Type STACK) MK_threadStack1_slot2 +0 ALIGN 4096 FIXED { *.o(.bss.core1.mk_threadstack1_slot2) *.o(.bss.core1.mk_threadstack1_slot2.*) } MK_RLA_MK_threadStack1_slot2 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack1_slot3 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack1_slot3 (Type STACK) MK_threadStack1_slot3 +0 ALIGN 4096 FIXED { *.o(.bss.core1.mk_threadstack1_slot3) *.o(.bss.core1.mk_threadstack1_slot3.*) } MK_RLA_MK_threadStack1_slot3 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack1_slot4 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack1_slot4 (Type STACK) MK_threadStack1_slot4 +0 ALIGN 2048 FIXED { *.o(.bss.core1.mk_threadstack1_slot4) *.o(.bss.core1.mk_threadstack1_slot4.*) } MK_RLA_MK_threadStack1_slot4 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack1_slot5 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack1_slot5 (Type STACK) MK_threadStack1_slot5 +0 ALIGN 2048 FIXED { *.o(.bss.core1.mk_threadstack1_slot5) *.o(.bss.core1.mk_threadstack1_slot5.*) } MK_RLA_MK_threadStack1_slot5 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack1_slot6 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack1_slot6 (Type STACK) MK_threadStack1_slot6 +0 ALIGN 2048 FIXED { *.o(.bss.core1.mk_threadstack1_slot6) *.o(.bss.core1.mk_threadstack1_slot6.*) } MK_RLA_MK_threadStack1_slot6 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack1_slot7 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack1_slot7 (Type STACK) MK_threadStack1_slot7 +0 ALIGN 2048 FIXED { *.o(.bss.core1.mk_threadstack1_slot7) *.o(.bss.core1.mk_threadstack1_slot7.*) } MK_RLA_MK_threadStack1_slot7 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack1_slot8 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack1_slot8 (Type STACK) MK_threadStack1_slot8 +0 ALIGN 2048 FIXED { *.o(.bss.core1.mk_threadstack1_slot8) *.o(.bss.core1.mk_threadstack1_slot8.*) } MK_RLA_MK_threadStack1_slot8 +0 ALIGN 2048 EMPTY FIXED 0 { } ; --------------------------------------------------------- ; Private memory regions of the application on core 1 ; --------------------------------------------------------- ; Output section OsApplication_1_data (Type DATA) MK_RDA_OsApplication_1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_OsApplication_1 +0 ALIGN 256 EMPTY FIXED 0 { } OsApplication_1_data +0 ALIGN 256 FIXED { OsApplication_1_gen.o(.data) OsApplication_1_gen.o(.data.*) OsApplication_1_gen.o(.zdata) OsApplication_1_gen.o(.zdata.*) OsApplication_1_gen.o(.sdata) OsApplication_1_gen.o(.sdata.*) } ; Output section OsApplication_1_bss (Type DATA_BSS) MK_BSA_OsApplication_1 +0 ALIGN 256 EMPTY FIXED 0 { } OsApplication_1_bss +0 ALIGN 256 UNINIT FIXED { OsApplication_1_gen.o(.bss) OsApplication_1_gen.o(.bss.*) OsApplication_1_gen.o(.zbss) OsApplication_1_gen.o(.zbss.*) OsApplication_1_gen.o(.sbss) OsApplication_1_gen.o(.sbss.*) } MK_RLA_OsApplication_1 +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_BSW_Init_Core1 --- NO FILES MK_RSA_OsTask_BSW_Init_Core1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_BSW_Init_Core1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_BSW_Init_Core1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_BSW_Init_Core1 +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApIVC_P_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApIVC_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApIVC_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApIVC_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApIVC_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApPCA_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApPCA_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApPCA_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApPCA_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApPCA_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApPDW_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApPDW_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApPDW_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApPDW_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApPDW_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApRSPA_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApRSPA_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApRSPA_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApRSPA_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApRSPA_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApSF_P_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApSF_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApSF_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApSF_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApSF_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_BswSE_BSW_FG1_10ms_Sub1 --- NO FILES MK_RSA_OsTask_BswSE_BSW_FG1_10ms_Sub1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_BswSE_BSW_FG1_10ms_Sub1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_BswSE_BSW_FG1_10ms_Sub1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_BswSE_BSW_FG1_10ms_Sub1 +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_Init_Core1 --- NO FILES MK_RSA_OsTask_ASW_Init_Core1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_Init_Core1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_Init_Core1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_Init_Core1 +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section OS_SYSTEM_1_data (Type DATA) MK_RDA_OS_SYSTEM_1 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_OS_SYSTEM_1 +0 ALIGN 256 EMPTY FIXED 0 { } OS_SYSTEM_1_data +0 ALIGN 256 FIXED { OS_SYSTEM_1_gen.o(.data) OS_SYSTEM_1_gen.o(.data.*) OS_SYSTEM_1_gen.o(.zdata) OS_SYSTEM_1_gen.o(.zdata.*) OS_SYSTEM_1_gen.o(.sdata) OS_SYSTEM_1_gen.o(.sdata.*) } ; Output section OS_SYSTEM_1_bss (Type DATA_BSS) MK_BSA_OS_SYSTEM_1 +0 ALIGN 256 EMPTY FIXED 0 { } OS_SYSTEM_1_bss +0 ALIGN 256 UNINIT FIXED { OS_SYSTEM_1_gen.o(.bss) OS_SYSTEM_1_gen.o(.bss.*) OS_SYSTEM_1_gen.o(.zbss) OS_SYSTEM_1_gen.o(.zbss.*) OS_SYSTEM_1_gen.o(.sbss) OS_SYSTEM_1_gen.o(.sbss.*) } MK_RLA_OS_SYSTEM_1 +0 ALIGN 256 EMPTY FIXED 0 { } } ram_C2 ram_C2_addr ram_C2_size { ; -------------------------------------------------------- ; Memory regions for the MK and counter subsystem data on core 2 ; -------------------------------------------------------- MK_RSA_ram_C2 ram_C2_addr ALIGN 256 EMPTY FIXED 0 { } ; Output section MK_Ram_data_C2 (Type DATA) MK_RDA_MK_Ram_C2 +0 ALIGN 8192 EMPTY FIXED 0 { } MK_RSA_MK_Ram_C2 +0 ALIGN 8192 EMPTY FIXED 0 { } MK_Ram_data_C2 +0 ALIGN 8192 FIXED { Mk_c2_*(.data) Mk_c2_*(.data.*) Mk_c2_*(.zdata) Mk_c2_*(.zdata.*) Mk_c2_*(.sdata) Mk_c2_*(.sdata.*) Ioc_data_kern_c2_*(.data) Ioc_data_kern_c2_*(.data.*) Ioc_data_kern_c2_*(.zdata) Ioc_data_kern_c2_*(.zdata.*) Ioc_data_kern_c2_*(.sdata) Ioc_data_kern_c2_*(.sdata.*) } ; Output section MK_Ram_bss_C2 (Type DATA_BSS) MK_BSA_MK_Ram_C2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_Ram_bss_C2 +0 ALIGN 256 UNINIT FIXED { Mk_c2_*(.bss) Mk_c2_*(.bss.*) Mk_c2_*(.zbss) Mk_c2_*(.zbss.*) Mk_c2_*(.sbss) Mk_c2_*(.sbss.*) Ioc_data_kern_c2_*(.bss) Ioc_data_kern_c2_*(.bss.*) Ioc_data_kern_c2_*(.zbss) Ioc_data_kern_c2_*(.zbss.*) Ioc_data_kern_c2_*(.sbss) Ioc_data_kern_c2_*(.sbss.*) } MK_RLA_MK_Ram_C2 +0 ALIGN 8192 EMPTY FIXED 0 { } ; Output section MK_OsRam_data_C2 (Type DATA) MK_RDA_MK_OsRam_C2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_MK_OsRam_C2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_OsRam_data_C2 +0 ALIGN 256 FIXED { kern-*(.data.core2) kern-*(.data.core2.*) kern-*(.data.shared.core2) kern-*(.data.shared.core2.*) ARM-*(.data.core2) ARM-*(.data.core2.*) ARM-*(.data.shared.core2) ARM-*(.data.shared.core2.*) Os_*(.data.core2) Os_*(.data.core2.*) Os_*(.data.shared.core2) Os_*(.data.shared.core2.*) } ; Output section MK_OsRam_bss_C2 (Type DATA_BSS) MK_BSA_MK_OsRam_C2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_OsRam_bss_C2 +0 ALIGN 256 UNINIT FIXED { kern-*(.bss.core2) kern-*(.bss.core2.*) kern-*(.bss.shared.core2) kern-*(.bss.shared.core2.*) ARM-*(.bss.core2) ARM-*(.bss.core2.*) ARM-*(.bss.shared.core2) ARM-*(.bss.shared.core2.*) Os_*(.bss.core2) Os_*(.bss.core2.*) Os_*(.bss.shared.core2) Os_*(.bss.shared.core2.*) } MK_RLA_MK_OsRam_C2 +0 ALIGN 256 EMPTY FIXED 0 { } ; MPU cache on core 2 MK_BSA_MK_c2_mpuCache +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section .mk_c2_mpu_cache (Type BSS) MK_RSA_MK_c2_mpuCache +0 ALIGN 256 EMPTY FIXED 0 { } .mk_c2_mpu_cache +0 ALIGN 256 UNINIT FIXED { Mk_ARM_*configuration.o(.bss.mk_c2_mpuCache) Mk_ARM_*configuration.o(.bss.mk_c2_mpuCache.*) } MK_RLA_MK_c2_mpuCache +0 ALIGN 256 EMPTY FIXED 0 { } ; Stacks on core 2 MK_RSA_MK_mk_stack_MK_c2_kernelStack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c2_kernelStack (Type STACK) MK_RSA_MK_c2_kernelStack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c2_kernelStack +0 ALIGN 512 FIXED { Mk_c2_kernel_stack.o(.bss) Mk_c2_kernel_stack.o(.bss.*) Mk_c2_kernel_stack.o(.zbss) Mk_c2_kernel_stack.o(.zbss.*) Mk_c2_kernel_stack.o(.sbss) Mk_c2_kernel_stack.o(.sbss.*) } MK_RLA_MK_c2_kernelStack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c2_aux1Stack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c2_aux1Stack (Type STACK) MK_RSA_MK_c2_aux1Stack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c2_aux1Stack +0 ALIGN 512 FIXED { Mk_c2_aux1_stack.o(.bss) Mk_c2_aux1_stack.o(.bss.*) Mk_c2_aux1_stack.o(.zbss) Mk_c2_aux1_stack.o(.zbss.*) Mk_c2_aux1_stack.o(.sbss) Mk_c2_aux1_stack.o(.sbss.*) } MK_RLA_MK_c2_aux1Stack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c2_aux2Stack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c2_aux2Stack (Type STACK) MK_RSA_MK_c2_aux2Stack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c2_aux2Stack +0 ALIGN 512 FIXED { Mk_c2_aux2_stack.o(.bss) Mk_c2_aux2_stack.o(.bss.*) Mk_c2_aux2_stack.o(.zbss) Mk_c2_aux2_stack.o(.zbss.*) Mk_c2_aux2_stack.o(.sbss) Mk_c2_aux2_stack.o(.sbss.*) } MK_RLA_MK_c2_aux2Stack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c2_idleshutdownStack +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c2_idleshutdownStack (Type STACK) MK_RSA_MK_c2_idleshutdownStack +0 ALIGN 256 EMPTY FIXED 0 { } mk_stack_MK_c2_idleshutdownStack +0 ALIGN 256 FIXED { Mk_c2_idleshutdown_stack.o(.bss) Mk_c2_idleshutdown_stack.o(.bss.*) Mk_c2_idleshutdown_stack.o(.zbss) Mk_c2_idleshutdown_stack.o(.zbss.*) Mk_c2_idleshutdown_stack.o(.sbss) Mk_c2_idleshutdown_stack.o(.sbss.*) } MK_RLA_MK_c2_idleshutdownStack +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c2_errorhookStack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c2_errorhookStack (Type STACK) MK_RSA_MK_c2_errorhookStack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c2_errorhookStack +0 ALIGN 512 FIXED { Mk_c2_errorhook_stack.o(.bss) Mk_c2_errorhook_stack.o(.bss.*) Mk_c2_errorhook_stack.o(.zbss) Mk_c2_errorhook_stack.o(.zbss.*) Mk_c2_errorhook_stack.o(.sbss) Mk_c2_errorhook_stack.o(.sbss.*) } MK_RLA_MK_c2_errorhookStack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_mk_stack_MK_c2_protectionHookStack +0 ALIGN 512 EMPTY FIXED 0 { } ; Output section mk_stack_MK_c2_protectionHookStack (Type STACK) MK_RSA_MK_c2_protectionHookStack +0 ALIGN 512 EMPTY FIXED 0 { } mk_stack_MK_c2_protectionHookStack +0 ALIGN 512 FIXED { Mk_c2_protectionhook_stack.o(.bss) Mk_c2_protectionhook_stack.o(.bss.*) Mk_c2_protectionhook_stack.o(.zbss) Mk_c2_protectionhook_stack.o(.zbss.*) Mk_c2_protectionhook_stack.o(.sbss) Mk_c2_protectionhook_stack.o(.sbss.*) } MK_RLA_MK_c2_protectionHookStack +0 ALIGN 512 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot0 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot0 (Type STACK) MK_threadStack2_slot0 +0 ALIGN 4096 FIXED { *.o(.bss.core2.mk_threadstack2_slot0) *.o(.bss.core2.mk_threadstack2_slot0.*) } MK_RLA_MK_threadStack2_slot0 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot1 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot1 (Type STACK) MK_threadStack2_slot1 +0 ALIGN 4096 FIXED { *.o(.bss.core2.mk_threadstack2_slot1) *.o(.bss.core2.mk_threadstack2_slot1.*) } MK_RLA_MK_threadStack2_slot1 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot2 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot2 (Type STACK) MK_threadStack2_slot2 +0 ALIGN 4096 FIXED { *.o(.bss.core2.mk_threadstack2_slot2) *.o(.bss.core2.mk_threadstack2_slot2.*) } MK_RLA_MK_threadStack2_slot2 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot3 +0 ALIGN 4096 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot3 (Type STACK) MK_threadStack2_slot3 +0 ALIGN 4096 FIXED { *.o(.bss.core2.mk_threadstack2_slot3) *.o(.bss.core2.mk_threadstack2_slot3.*) } MK_RLA_MK_threadStack2_slot3 +0 ALIGN 4096 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot4 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot4 (Type STACK) MK_threadStack2_slot4 +0 ALIGN 2048 FIXED { *.o(.bss.core2.mk_threadstack2_slot4) *.o(.bss.core2.mk_threadstack2_slot4.*) } MK_RLA_MK_threadStack2_slot4 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot5 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot5 (Type STACK) MK_threadStack2_slot5 +0 ALIGN 2048 FIXED { *.o(.bss.core2.mk_threadstack2_slot5) *.o(.bss.core2.mk_threadstack2_slot5.*) } MK_RLA_MK_threadStack2_slot5 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot6 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot6 (Type STACK) MK_threadStack2_slot6 +0 ALIGN 2048 FIXED { *.o(.bss.core2.mk_threadstack2_slot6) *.o(.bss.core2.mk_threadstack2_slot6.*) } MK_RLA_MK_threadStack2_slot6 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot7 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot7 (Type STACK) MK_threadStack2_slot7 +0 ALIGN 2048 FIXED { *.o(.bss.core2.mk_threadstack2_slot7) *.o(.bss.core2.mk_threadstack2_slot7.*) } MK_RLA_MK_threadStack2_slot7 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot8 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot8 (Type STACK) MK_threadStack2_slot8 +0 ALIGN 2048 FIXED { *.o(.bss.core2.mk_threadstack2_slot8) *.o(.bss.core2.mk_threadstack2_slot8.*) } MK_RLA_MK_threadStack2_slot8 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot9 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot9 (Type STACK) MK_threadStack2_slot9 +0 ALIGN 2048 FIXED { *.o(.bss.core2.mk_threadstack2_slot9) *.o(.bss.core2.mk_threadstack2_slot9.*) } MK_RLA_MK_threadStack2_slot9 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot10 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot10 (Type STACK) MK_threadStack2_slot10 +0 ALIGN 2048 FIXED { *.o(.bss.core2.mk_threadstack2_slot10) *.o(.bss.core2.mk_threadstack2_slot10.*) } MK_RLA_MK_threadStack2_slot10 +0 ALIGN 2048 EMPTY FIXED 0 { } MK_RSA_MK_threadStack2_slot11 +0 ALIGN 2048 EMPTY FIXED 0 { } ; Output section MK_threadStack2_slot11 (Type STACK) MK_threadStack2_slot11 +0 ALIGN 2048 FIXED { *.o(.bss.core2.mk_threadstack2_slot11) *.o(.bss.core2.mk_threadstack2_slot11.*) } MK_RLA_MK_threadStack2_slot11 +0 ALIGN 2048 EMPTY FIXED 0 { } ; --------------------------------------------------------- ; Private memory regions of the application on core 2 ; --------------------------------------------------------- ; Output section OsApplication_2_data (Type DATA) MK_RDA_OsApplication_2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_OsApplication_2 +0 ALIGN 256 EMPTY FIXED 0 { } OsApplication_2_data +0 ALIGN 256 FIXED { OsApplication_2_gen.o(.data) OsApplication_2_gen.o(.data.*) OsApplication_2_gen.o(.zdata) OsApplication_2_gen.o(.zdata.*) OsApplication_2_gen.o(.sdata) OsApplication_2_gen.o(.sdata.*) } ; Output section OsApplication_2_bss (Type DATA_BSS) MK_BSA_OsApplication_2 +0 ALIGN 256 EMPTY FIXED 0 { } OsApplication_2_bss +0 ALIGN 256 UNINIT FIXED { OsApplication_2_gen.o(.bss) OsApplication_2_gen.o(.bss.*) OsApplication_2_gen.o(.zbss) OsApplication_2_gen.o(.zbss.*) OsApplication_2_gen.o(.sbss) OsApplication_2_gen.o(.sbss.*) } MK_RLA_OsApplication_2 +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_BSW_Init_Core2 --- NO FILES MK_RSA_OsTask_BSW_Init_Core2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_BSW_Init_Core2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_BSW_Init_Core2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_BSW_Init_Core2 +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApUISP_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApUISP_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApUISP_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApUISP_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApUISP_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_BswSE_BSW_FG1_10ms_Sub2 --- NO FILES MK_RSA_OsTask_BswSE_BSW_FG1_10ms_Sub2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_BswSE_BSW_FG1_10ms_Sub2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_BswSE_BSW_FG1_10ms_Sub2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_BswSE_BSW_FG1_10ms_Sub2 +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_Init_Core2 --- NO FILES MK_RSA_OsTask_ASW_Init_Core2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_Init_Core2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_Init_Core2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_Init_Core2 +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApUISP_20ms --- NO FILES MK_RSA_OsTask_ASW_RCtApUISP_20ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApUISP_20ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApUISP_20ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApUISP_20ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApUISP_40ms --- NO FILES MK_RSA_OsTask_ASW_RCtApUISP_40ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApUISP_40ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApUISP_40ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApUISP_40ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApNVM_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApNVM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApNVM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApNVM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApNVM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApDEM_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApDEM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApDEM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApDEM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApDEM_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApVDISP_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApVDISP_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApVDISP_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApVDISP_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApVDISP_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Task OsTask_ASW_RCtApVPE_P_10ms --- NO FILES MK_RSA_OsTask_ASW_RCtApVPE_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_OsTask_ASW_RCtApVPE_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_OsTask_ASW_RCtApVPE_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_OsTask_ASW_RCtApVPE_P_10ms +0 ALIGN 256 EMPTY FIXED 0 { } ; Isr SPI_MSIOF5_CAT2_ISR --- NO FILES MK_RSA_SPI_MSIOF5_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_SPI_MSIOF5_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_SPI_MSIOF5_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_SPI_MSIOF5_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } ; Isr TMU_CH00_CAT2_ISR --- NO FILES MK_RSA_TMU_CH00_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_TMU_CH00_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_TMU_CH00_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_TMU_CH00_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } ; Isr TMU_CH01_CAT2_ISR --- NO FILES MK_RSA_TMU_CH01_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RLA_TMU_CH01_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_RDA_TMU_CH01_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } MK_BSA_TMU_CH01_CAT2_ISR +0 ALIGN 256 EMPTY FIXED 0 { } ; Output section OS_SYSTEM_2_data (Type DATA) MK_RDA_OS_SYSTEM_2 +0 ALIGN 256 EMPTY FIXED 0 { } MK_RSA_OS_SYSTEM_2 +0 ALIGN 256 EMPTY FIXED 0 { } OS_SYSTEM_2_data +0 ALIGN 256 FIXED { OS_SYSTEM_2_gen.o(.data) OS_SYSTEM_2_gen.o(.data.*) OS_SYSTEM_2_gen.o(.zdata) OS_SYSTEM_2_gen.o(.zdata.*) OS_SYSTEM_2_gen.o(.sdata) OS_SYSTEM_2_gen.o(.sdata.*) } ; Output section OS_SYSTEM_2_bss (Type DATA_BSS) MK_BSA_OS_SYSTEM_2 +0 ALIGN 256 EMPTY FIXED 0 { } OS_SYSTEM_2_bss +0 ALIGN 256 UNINIT FIXED { OS_SYSTEM_2_gen.o(.bss) OS_SYSTEM_2_gen.o(.bss.*) OS_SYSTEM_2_gen.o(.zbss) OS_SYSTEM_2_gen.o(.zbss.*) OS_SYSTEM_2_gen.o(.sbss) OS_SYSTEM_2_gen.o(.sbss.*) } MK_RLA_OS_SYSTEM_2 +0 ALIGN 256 EMPTY FIXED 0 { } } GLOBAL_SYMBOLS 0 { MK_RSA_MK_Rom exctable_addr ALIGN 256 EMPTY 0 { } MK_RLA_MK_Rom (ROM_start_addr + ROM_size) ALIGN 256 EMPTY 0 { } IOC_RSA_READABLE_OsApplication_0 BOARD_C0_RAM_BEG ALIGN 256 EMPTY 0 { } IOC_RLA_READABLE_OsApplication_0 BOARD_C0_URAM_END ALIGN 256 EMPTY 0 { } IOC_RSA_READABLE_OS_SYSTEM_0 BOARD_C0_RAM_BEG ALIGN 256 EMPTY 0 { } IOC_RLA_READABLE_OS_SYSTEM_0 BOARD_C0_URAM_END ALIGN 256 EMPTY 0 { } IOC_RSA_READABLE_OsApplication_1 BOARD_C1_RAM_BEG ALIGN 256 EMPTY 0 { } IOC_RLA_READABLE_OsApplication_1 BOARD_C1_URAM_END ALIGN 256 EMPTY 0 { } IOC_RSA_READABLE_OS_SYSTEM_1 BOARD_C1_RAM_BEG ALIGN 256 EMPTY 0 { } IOC_RLA_READABLE_OS_SYSTEM_1 BOARD_C1_URAM_END ALIGN 256 EMPTY 0 { } IOC_RSA_READABLE_OsApplication_2 BOARD_C2_RAM_BEG ALIGN 256 EMPTY 0 { } IOC_RLA_READABLE_OsApplication_2 BOARD_C2_URAM_END ALIGN 256 EMPTY 0 { } IOC_RSA_READABLE_OS_SYSTEM_2 BOARD_C2_RAM_BEG ALIGN 256 EMPTY 0 { } IOC_RLA_READABLE_OS_SYSTEM_2 BOARD_C2_URAM_END ALIGN 256 EMPTY 0 { } MK_RSA_MK_GlobalRam RAM_start_addr ALIGN 256 EMPTY 0 { } MK_RLA_MK_GlobalRam (RAM_start_addr + RAM_size) ALIGN 256 EMPTY 0 { } MK_RSA_GPIO_LED GPIO_start_addr ALIGN 256 EMPTY 0 { } MK_RLA_GPIO_LED GPIO_end_addr ALIGN 256 EMPTY 0 { } }